| /src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv50/ |
| nouveau_dispnv50_core.c | 49 } cores[] = { local in function:nv50_core_new
69 cid = nvif_mclass(&disp->disp->object, cores);
75 return cores[cid].new(drm, cores[cid].oclass, pcore);
|
| nouveau_dispnv50_core.c | 49 } cores[] = { local in function:nv50_core_new
69 cid = nvif_mclass(&disp->disp->object, cores);
75 return cores[cid].new(drm, cores[cid].oclass, pcore);
|
| nouveau_dispnv50_core.c | 49 } cores[] = { local in function:nv50_core_new
69 cid = nvif_mclass(&disp->disp->object, cores);
75 return cores[cid].new(drm, cores[cid].oclass, pcore);
|
| nouveau_dispnv50_core.c | 49 } cores[] = { local in function:nv50_core_new
69 cid = nvif_mclass(&disp->disp->object, cores);
75 return cores[cid].new(drm, cores[cid].oclass, pcore);
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| socfpga_arria5.dtsi | 7 /* First 4KB has trampoline code for secondary cores. */
|
| socfpga_cyclone5.dtsi | 7 /* First 4KB has trampoline code for secondary cores. */
|
| socfpga_arria5.dtsi | 7 /* First 4KB has trampoline code for secondary cores. */
|
| socfpga_cyclone5.dtsi | 7 /* First 4KB has trampoline code for secondary cores. */
|
| socfpga_arria5.dtsi | 7 /* First 4KB has trampoline code for secondary cores. */
|
| socfpga_cyclone5.dtsi | 7 /* First 4KB has trampoline code for secondary cores. */
|
| socfpga_arria5.dtsi | 7 /* First 4KB has trampoline code for secondary cores. */
|
| socfpga_cyclone5.dtsi | 7 /* First 4KB has trampoline code for secondary cores. */
|
| exynos5422-odroidxu3-lite.dts | 39 * than Odroid XU3/XU4 boards: 1.8 GHz for A15 cores & 1.3 GHz for A7 cores.
|
| exynos5422-odroidxu3-lite.dts | 39 * than Odroid XU3/XU4 boards: 1.8 GHz for A15 cores & 1.3 GHz for A7 cores.
|
| exynos5422-odroidxu3-lite.dts | 39 * than Odroid XU3/XU4 boards: 1.8 GHz for A15 cores & 1.3 GHz for A7 cores.
|
| exynos5422-odroidxu3-lite.dts | 39 * than Odroid XU3/XU4 boards: 1.8 GHz for A15 cores & 1.3 GHz for A7 cores.
|
| vexpress-v2p-ca15-tc1.dts | 199 volt-cores {
203 regulator-name = "Cores";
207 label = "Cores";
210 amp-cores {
211 /* Total current for the two cores */
214 label = "Cores";
224 power-cores {
228 label = "Cores";
235 label = "Cores";
|
| vexpress-v2p-ca15-tc1.dts | 199 volt-cores {
203 regulator-name = "Cores";
207 label = "Cores";
210 amp-cores {
211 /* Total current for the two cores */
214 label = "Cores";
224 power-cores {
228 label = "Cores";
235 label = "Cores";
|
| vexpress-v2p-ca15-tc1.dts | 199 volt-cores {
203 regulator-name = "Cores";
207 label = "Cores";
210 amp-cores {
211 /* Total current for the two cores */
214 label = "Cores";
224 power-cores {
228 label = "Cores";
235 label = "Cores";
|
| vexpress-v2p-ca15-tc1.dts | 199 volt-cores {
203 regulator-name = "Cores";
207 label = "Cores";
210 amp-cores {
211 /* Total current for the two cores */
214 label = "Cores";
224 power-cores {
228 label = "Cores";
235 label = "Cores";
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/marvell/ |
| armada-ap810-ap0-octa-core.dtsi | 5 * Device Tree file for Marvell Armada AP810 OCTA cores.
|
| armada-ap810-ap0-octa-core.dtsi | 5 * Device Tree file for Marvell Armada AP810 OCTA cores.
|
| armada-ap810-ap0-octa-core.dtsi | 5 * Device Tree file for Marvell Armada AP810 OCTA cores.
|
| armada-ap810-ap0-octa-core.dtsi | 5 * Device Tree file for Marvell Armada AP810 OCTA cores.
|
| /src/sys/arch/evbmips/cavium/ |
| machdep.c | 390 const int cores = popcount64(fuse); local in function:mach_init_memory
391 mem_clusters[0].start += cores * PAGE_SIZE;
392 mem_clusters[0].size -= cores * PAGE_SIZE;
|
