| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| core_types.h | 185 struct display_stream_compressor *dscs[MAX_PIPES]; member in struct:resource_pool
|
| core_types.h | 185 struct display_stream_compressor *dscs[MAX_PIPES]; member in struct:resource_pool
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/ |
| amdgpu_dm_mst_types.c | 554 params[i].sink->ctx->dc->res_pool->dscs[0],
575 param.sink->ctx->dc->res_pool->dscs[0],
776 stream->sink->ctx->dc->res_pool->dscs[0],
|
| amdgpu_dm_mst_types.c | 554 params[i].sink->ctx->dc->res_pool->dscs[0],
575 param.sink->ctx->dc->res_pool->dscs[0],
776 stream->sink->ctx->dc->res_pool->dscs[0],
|
| amdgpu_dm.c | 4109 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
|
| amdgpu_dm.c | 4109 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_resource.c | 881 if (pool->base.dscs[i] != NULL)
882 dcn20_dsc_destroy(&pool->base.dscs[i]);
1885 pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
1886 if (pool->base.dscs[i] == NULL) {
|
| amdgpu_dcn21_resource.c | 881 if (pool->base.dscs[i] != NULL)
882 dcn20_dsc_destroy(&pool->base.dscs[i]);
1885 pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
1886 if (pool->base.dscs[i] == NULL) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_resource.c | 1326 if (pool->base.dscs[i] != NULL)
1327 dcn20_dsc_destroy(&pool->base.dscs[i]);
1551 *dsc = pool->dscs[pipe_idx];
1559 *dsc = pool->dscs[i];
1572 if (pool->dscs[i] == *dsc) {
1601 /* The number of DSCs can be less than the number of pipes */
3754 pool->base.dscs[i] = dcn20_dsc_create(ctx, i);
3755 if (pool->base.dscs[i] == NULL) {
|
| amdgpu_dcn20_resource.c | 1326 if (pool->base.dscs[i] != NULL)
1327 dcn20_dsc_destroy(&pool->base.dscs[i]);
1551 *dsc = pool->dscs[pipe_idx];
1559 *dsc = pool->dscs[i];
1572 if (pool->dscs[i] == *dsc) {
1601 /* The number of DSCs can be less than the number of pipes */
3754 pool->base.dscs[i] = dcn20_dsc_create(ctx, i);
3755 if (pool->base.dscs[i] == NULL) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_hw_sequencer.c | 398 struct display_stream_compressor *dsc = pool->dscs[i];
1320 /* Power gate DSCs */
1323 hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
|
| amdgpu_dcn10_hw_sequencer.c | 398 struct display_stream_compressor *dsc = pool->dscs[i];
1320 /* Power gate DSCs */
1323 hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
|
