/src/sys/arch/sparc/include/ |
instr.h | 349 #define _I_OP3_GEN(form, rd, op3, rs1, low14) \ 350 _I_ANY(form, (rd) << 25 | (op3) << 19 | (rs1) << 14 | (low14)) 351 #define _I_OP3_LS_RAR(rd, op3, rs1, asi, rs2) \ 352 _I_OP3_GEN(IOP_mem, rd, op3, rs1, (asi) << 5 | (rs2)) 353 #define _I_OP3_LS_RI(rd, op3, rs1, simm13) \ 354 _I_OP3_GEN(IOP_mem, rd, op3, rs1, _I_SIMM(simm13)) 355 #define _I_OP3_LS_RR(rd, op3, rs1, rs2) \ 356 _I_OP3_GEN(IOP_mem, rd, op3, rs1, rs2) 357 #define _I_OP3_R_RAR(rd, op3, rs1, asi, rs2) \ 358 _I_OP3_GEN(IOP_reg, rd, op3, rs1, (asi) << 5 | (rs2) [all...] |
instr.h | 349 #define _I_OP3_GEN(form, rd, op3, rs1, low14) \ 350 _I_ANY(form, (rd) << 25 | (op3) << 19 | (rs1) << 14 | (low14)) 351 #define _I_OP3_LS_RAR(rd, op3, rs1, asi, rs2) \ 352 _I_OP3_GEN(IOP_mem, rd, op3, rs1, (asi) << 5 | (rs2)) 353 #define _I_OP3_LS_RI(rd, op3, rs1, simm13) \ 354 _I_OP3_GEN(IOP_mem, rd, op3, rs1, _I_SIMM(simm13)) 355 #define _I_OP3_LS_RR(rd, op3, rs1, rs2) \ 356 _I_OP3_GEN(IOP_mem, rd, op3, rs1, rs2) 357 #define _I_OP3_R_RAR(rd, op3, rs1, asi, rs2) \ 358 _I_OP3_GEN(IOP_reg, rd, op3, rs1, (asi) << 5 | (rs2) [all...] |
/src/sys/arch/amd64/amd64/ |
db_disasm.c | 130 #define op3(x,y,z) ((x)|((y)<<8)|((z)<<16)) macro 339 /*a4*/ { "shld", true, LONG, op3(Ib,R,E), 0 }, 340 /*a5*/ { "shld", true, LONG, op3(CL,R,E), 0 }, 348 /*ac*/ { "shrd", true, LONG, op3(Ib,R,E), 0 }, 349 /*ad*/ { "shrd", true, LONG, op3(CL,R,E), 0 }, 721 /*69*/ { "imul", true, LONG, op3(I,E,R), 0 }, 723 /*6b*/ { "imul", true, LONG, op3(Ibs,E,R),0 },
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db_disasm.c | 130 #define op3(x,y,z) ((x)|((y)<<8)|((z)<<16)) macro 339 /*a4*/ { "shld", true, LONG, op3(Ib,R,E), 0 }, 340 /*a5*/ { "shld", true, LONG, op3(CL,R,E), 0 }, 348 /*ac*/ { "shrd", true, LONG, op3(Ib,R,E), 0 }, 349 /*ad*/ { "shrd", true, LONG, op3(CL,R,E), 0 }, 721 /*69*/ { "imul", true, LONG, op3(I,E,R), 0 }, 723 /*6b*/ { "imul", true, LONG, op3(Ibs,E,R),0 },
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/src/sys/arch/i386/i386/ |
db_disasm.c | 113 #define op3(x,y,z) ((x)|((y)<<8)|((z)<<16)) macro 307 /*a4*/ { "shld", true, LONG, op3(Ib,R,E), 0 }, 308 /*a5*/ { "shld", true, LONG, op3(CL,R,E), 0 }, 316 /*ac*/ { "shrd", true, LONG, op3(Ib,R,E), 0 }, 317 /*ad*/ { "shrd", true, LONG, op3(CL,R,E), 0 }, 684 /*69*/ { "imul", true, LONG, op3(I,E,R), 0 }, 686 /*6b*/ { "imul", true, LONG, op3(Ibs,E,R),0 },
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db_disasm.c | 113 #define op3(x,y,z) ((x)|((y)<<8)|((z)<<16)) macro 307 /*a4*/ { "shld", true, LONG, op3(Ib,R,E), 0 }, 308 /*a5*/ { "shld", true, LONG, op3(CL,R,E), 0 }, 316 /*ac*/ { "shrd", true, LONG, op3(Ib,R,E), 0 }, 317 /*ad*/ { "shrd", true, LONG, op3(CL,R,E), 0 }, 684 /*69*/ { "imul", true, LONG, op3(I,E,R), 0 }, 686 /*6b*/ { "imul", true, LONG, op3(Ibs,E,R),0 },
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/src/sys/arch/aarch64/aarch64/ |
disasm.c | 777 #define SHIFTOP4(s, op1, op2, op3, op4) \ 778 ((const char *[]){ op1, op2, op3, op4 })[(s) & 3] 779 #define SHIFTOP8(s, op1, op2, op3, op4, op5, op6, op7, op8) \ 780 ((const char *[]){ op1, op2, op3, op4, op5, op6, op7, op8 })[(s) & 7] 1058 const char *op, const char *op2, const char *op3) 1062 op3,
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disasm.c | 777 #define SHIFTOP4(s, op1, op2, op3, op4) \ 778 ((const char *[]){ op1, op2, op3, op4 })[(s) & 3] 779 #define SHIFTOP8(s, op1, op2, op3, op4, op5, op6, op7, op8) \ 780 ((const char *[]){ op1, op2, op3, op4, op5, op6, op7, op8 })[(s) & 7] 1058 const char *op, const char *op2, const char *op3) 1062 op3,
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/src/sys/external/bsd/sljit/dist/sljit_src/ |
sljitNativeTILEGX_64.c | 746 static sljit_s32 push_4_buffer(struct sljit_compiler *compiler, tilegx_mnemonic opc, int op0, int op1, int op2, int op3, int line) 757 inst_buf[inst_buf_index].operand_value[3] = op3;
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sljitNativeTILEGX_64.c | 746 static sljit_s32 push_4_buffer(struct sljit_compiler *compiler, tilegx_mnemonic opc, int op0, int op1, int op2, int op3, int line) 757 inst_buf[inst_buf_index].operand_value[3] = op3;
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/src/sys/arch/sparc/sparc/ |
locore.s | 2085 ! instruction format: op=2, op3=0x3b (see also instr.h) 2086 set ((3 << 30) | (0x3f << 19)), %l7 ! extract op & op3 fields
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locore.s | 2085 ! instruction format: op=2, op3=0x3b (see also instr.h) 2086 set ((3 << 30) | (0x3f << 19)), %l7 ! extract op & op3 fields
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