| /src/external/gpl3/gcc/dist/gcc/ |
| gimple-match.h | 227 tree op4, tree op5)
236 ops[5] = op5;
243 tree op4, tree op5, tree op6)
252 ops[5] = op5;
346 tree op5)
356 ops[5] = op5;
362 tree op5, tree op6)
372 ops[5] = op5;
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| simplify-rtx.cc | 8593 rtx op5 = make_test_reg (mode);
8598 rtx vm3 = gen_rtx_VEC_MERGE (mode, op4, op5, mask1);
8632 ASSERT_RTX_EQ (gen_rtx_FMA (mode, op1, op3, op5),
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| /src/external/historical/nawk/dist/ |
| awkgram.y | 385 { $$ = op5(GENSUB, NIL, (Node*)makedfa($3, 1), $5, $7, rectonode()); }
388 $$ = op5(GENSUB, NIL, (Node *)makedfa(strnode($3), 1), $5, $7, rectonode());
391 $$ = op5(GENSUB, (Node *)1, $3, $5, $7, rectonode());
394 { $$ = op5(GENSUB, NIL, (Node*)makedfa($3, 1), $5, $7, $9); }
397 $$ = op5(GENSUB, NIL, (Node *)makedfa(strnode($3),1), $5,$7,$9);
400 $$ = op5(GENSUB, (Node *)1, $3, $5, $7, $9);
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| proto.h | 80 extern Node *op5(int, Node *, Node *, Node *, Node *, Node *);
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| parse.c | 186 Node *op5(int a, Node *b, Node *c, Node *d, Node *e, Node *f) function
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| /xsrc/external/mit/libdrm/dist/freedreno/kgsl/ |
| msm_kgsl.h | 385 unsigned int op5; member in struct:kgsl_cff_user_event
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| /src/external/gpl3/binutils/dist/include/opcode/ |
| nds32.h | 98 #define N16_TYPE55(op5, rt5, ra5) \
99 (0x8000 | __MF (N16_T55_##op5, 10, 5) | __MF (rt5, 5, 5) \
122 #define N16_TYPE10(op5, imm10) \
123 (0x8000 | __MF (N16_T10_##op5, 10, 5) | __MF (imm10, 0, 10))
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| /src/external/gpl3/binutils.old/dist/include/opcode/ |
| nds32.h | 98 #define N16_TYPE55(op5, rt5, ra5) \
99 (0x8000 | __MF (N16_T55_##op5, 10, 5) | __MF (rt5, 5, 5) \
122 #define N16_TYPE10(op5, imm10) \
123 (0x8000 | __MF (N16_T10_##op5, 10, 5) | __MF (imm10, 0, 10))
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| /src/external/gpl3/gdb.old/dist/include/opcode/ |
| nds32.h | 98 #define N16_TYPE55(op5, rt5, ra5) \
99 (0x8000 | __MF (N16_T55_##op5, 10, 5) | __MF (rt5, 5, 5) \
122 #define N16_TYPE10(op5, imm10) \
123 (0x8000 | __MF (N16_T10_##op5, 10, 5) | __MF (imm10, 0, 10))
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| /src/external/gpl3/gdb/dist/include/opcode/ |
| nds32.h | 98 #define N16_TYPE55(op5, rt5, ra5) \
99 (0x8000 | __MF (N16_T55_##op5, 10, 5) | __MF (rt5, 5, 5) \
122 #define N16_TYPE10(op5, imm10) \
123 (0x8000 | __MF (N16_T10_##op5, 10, 5) | __MF (imm10, 0, 10))
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| /xsrc/external/mit/MesaLib/dist/src/freedreno/vulkan/ |
| msm_kgsl.h | 659 unsigned int op5; member in struct:kgsl_cff_user_event
|
| /src/external/gpl3/gcc/dist/gcc/config/visium/ |
| visium.cc | 2163 rtx op5; local
2180 op5 = gen_int_mode (val, SImode);
2185 op5 = gen_lowpart (SImode, op2);
2190 pat = gen_negsi2_insn_set_carry (op3, op5);
2192 pat = gen_subsi3_insn_set_carry (op3, op4, op5);
2194 pat = gen_addsi3_insn_set_carry (op3, op4, op5);
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| /src/external/gpl3/gcc.old/dist/gcc/config/visium/ |
| visium.cc | 2160 rtx op5; local
2177 op5 = gen_int_mode (val, SImode);
2182 op5 = gen_lowpart (SImode, op2);
2187 pat = gen_negsi2_insn_set_carry (op3, op5);
2189 pat = gen_subsi3_insn_set_carry (op3, op4, op5);
2191 pat = gen_addsi3_insn_set_carry (op3, op4, op5);
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| /src/sys/arch/aarch64/aarch64/ |
| disasm.c | 780 #define SHIFTOP8(s, op1, op2, op3, op4, op5, op6, op7, op8) \
781 ((const char *[]){ op1, op2, op3, op4, op5, op6, op7, op8 })[(s) & 7]
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| /src/external/gpl3/gcc.old/dist/gcc/ |
| simplify-rtx.cc | 8216 rtx op5 = make_test_reg (mode);
8221 rtx vm3 = gen_rtx_VEC_MERGE (mode, op4, op5, mask1);
8255 ASSERT_RTX_EQ (gen_rtx_FMA (mode, op1, op3, op5),
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| /src/external/gpl3/gcc/dist/gcc/config/i386/ |
| i386-expand.cc | 16743 rtx ops[64], op0, op1, op2, op3, op4, op5; local
16853 op5 = gen_reg_rtx (half_mode);
16863 emit_insn (gen_rtx_SET (op5, gen_rtx_VEC_CONCAT (half_mode, op2, op3)));
16864 emit_insn (gen_rtx_SET (target, gen_rtx_VEC_CONCAT (mode, op4, op5)));
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| /src/external/gpl3/gcc.old/dist/gcc/config/i386/ |
| i386-expand.cc | 15727 rtx ops[64], op0, op1, op2, op3, op4, op5; local
15827 op5 = gen_reg_rtx (half_mode);
15837 emit_insn (gen_rtx_SET (op5, gen_rtx_VEC_CONCAT (half_mode, op2, op3)));
15838 emit_insn (gen_rtx_SET (target, gen_rtx_VEC_CONCAT (mode, op4, op5)));
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