| /src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvfw/ |
| flcn.h | 17 u32 overlay_dma_base; member in struct:loader_config
37 u64 overlay_dma_base; member in struct:loader_config_v1
|
| flcn.h | 17 u32 overlay_dma_base; member in struct:loader_config
37 u64 overlay_dma_base; member in struct:loader_config_v1
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/nvfw/ |
| nouveau_nvkm_nvfw_flcn.c | 41 nvkm_debug(subdev, "\toverlayDmaBase: 0x%x\n", hdr->overlay_dma_base);
62 nvkm_debug(subdev, "\toverlayDmaBase: 0x%"PRIx64"\n", hdr->overlay_dma_base);
|
| nouveau_nvkm_nvfw_flcn.c | 41 nvkm_debug(subdev, "\toverlayDmaBase: 0x%x\n", hdr->overlay_dma_base);
62 nvkm_debug(subdev, "\toverlayDmaBase: 0x%"PRIx64"\n", hdr->overlay_dma_base);
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/pmu/ |
| nouveau_nvkm_subdev_pmu_gm20b.c | 93 addr = ((u64)hdr.overlay_dma_base1 << 40 | hdr.overlay_dma_base << 8);
94 hdr.overlay_dma_base = lower_32_bits((addr + adjust) << 8);
116 .overlay_dma_base = lower_32_bits(code),
|
| nouveau_nvkm_subdev_pmu_gm20b.c | 93 addr = ((u64)hdr.overlay_dma_base1 << 40 | hdr.overlay_dma_base << 8);
94 hdr.overlay_dma_base = lower_32_bits((addr + adjust) << 8);
116 .overlay_dma_base = lower_32_bits(code),
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/sec2/ |
| nouveau_nvkm_engine_sec2_gp102.c | 91 hdr.overlay_dma_base = hdr.overlay_dma_base + adjust;
109 .overlay_dma_base = lsfw->offset.img + lsfw->app_start_offset,
|
| nouveau_nvkm_engine_sec2_gp102.c | 91 hdr.overlay_dma_base = hdr.overlay_dma_base + adjust;
109 .overlay_dma_base = lsfw->offset.img + lsfw->app_start_offset,
|
