| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_gmc.h | 85 uint32_t vm_context0_cntl; member in struct:amdgpu_vmhub
|
| amdgpu_gmc_v10_0.c | 94 reg = hub->vm_context0_cntl + i;
103 reg = hub->vm_context0_cntl + i;
113 reg = hub->vm_context0_cntl + i;
122 reg = hub->vm_context0_cntl + i;
|
| amdgpu_gmc.h | 85 uint32_t vm_context0_cntl; member in struct:amdgpu_vmhub
|
| amdgpu_gmc_v10_0.c | 94 reg = hub->vm_context0_cntl + i;
103 reg = hub->vm_context0_cntl + i;
113 reg = hub->vm_context0_cntl + i;
122 reg = hub->vm_context0_cntl + i;
|
| amdgpu_gmc.h | 85 uint32_t vm_context0_cntl; member in struct:amdgpu_vmhub
|
| amdgpu_gmc_v10_0.c | 94 reg = hub->vm_context0_cntl + i;
103 reg = hub->vm_context0_cntl + i;
113 reg = hub->vm_context0_cntl + i;
122 reg = hub->vm_context0_cntl + i;
|
| amdgpu_gmc.h | 85 uint32_t vm_context0_cntl; member in struct:amdgpu_vmhub
|
| amdgpu_gmc_v10_0.c | 94 reg = hub->vm_context0_cntl + i;
103 reg = hub->vm_context0_cntl + i;
113 reg = hub->vm_context0_cntl + i;
122 reg = hub->vm_context0_cntl + i;
|
| amdgpu_gfxhub_v1_0.c | 189 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
190 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
191 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
388 hub->vm_context0_cntl =
|
| amdgpu_gfxhub_v2_0.c | 370 hub->vm_context0_cntl =
|
| amdgpu_mmhub_v2_0.c | 362 hub->vm_context0_cntl =
|
| amdgpu_gfxhub_v1_0.c | 189 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
190 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
191 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
388 hub->vm_context0_cntl =
|
| amdgpu_gfxhub_v2_0.c | 370 hub->vm_context0_cntl =
|
| amdgpu_mmhub_v2_0.c | 362 hub->vm_context0_cntl =
|
| amdgpu_gfxhub_v1_0.c | 189 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
190 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
191 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
388 hub->vm_context0_cntl =
|
| amdgpu_gfxhub_v2_0.c | 370 hub->vm_context0_cntl =
|
| amdgpu_mmhub_v2_0.c | 362 hub->vm_context0_cntl =
|
| amdgpu_gfxhub_v1_0.c | 189 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
190 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
191 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
388 hub->vm_context0_cntl =
|
| amdgpu_gfxhub_v2_0.c | 370 hub->vm_context0_cntl =
|
| amdgpu_mmhub_v2_0.c | 362 hub->vm_context0_cntl =
|
| amdgpu_gmc_v9_0.c | 281 reg = hub->vm_context0_cntl + i;
292 reg = hub->vm_context0_cntl + i;
|
| amdgpu_gmc_v9_0.c | 281 reg = hub->vm_context0_cntl + i;
292 reg = hub->vm_context0_cntl + i;
|
| amdgpu_gmc_v9_0.c | 281 reg = hub->vm_context0_cntl + i;
292 reg = hub->vm_context0_cntl + i;
|
| amdgpu_gmc_v9_0.c | 281 reg = hub->vm_context0_cntl + i;
292 reg = hub->vm_context0_cntl + i;
|
| amdgpu_mmhub_v1_0.c | 208 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
209 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
210 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
430 hub->vm_context0_cntl =
|
