| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| clk_mgr.h | 146 struct wm_table { struct
154 struct wm_table wm_table; member in struct:clk_bw_params
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| clk_mgr.h | 146 struct wm_table { struct
154 struct wm_table wm_table; member in struct:clk_bw_params
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| clk_mgr.h | 146 struct wm_table { struct
154 struct wm_table wm_table; member in struct:clk_bw_params
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn21/ |
| amdgpu_rn_clk_mgr.c | 421 if (!bw_params->wm_table.entries[i].valid)
424 ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst;
425 ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type;
552 struct wm_table ddr4_wm_table = {
589 struct wm_table lpddr4_wm_table = {
676 bw_params->wm_table.entries[i].wm_inst = i;
679 bw_params->wm_table.entries[i].valid = false;
683 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
684 bw_params->wm_table.entries[i].valid = true;
691 bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY
[all...] |
| amdgpu_rn_clk_mgr.c | 421 if (!bw_params->wm_table.entries[i].valid)
424 ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst;
425 ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type;
552 struct wm_table ddr4_wm_table = {
589 struct wm_table lpddr4_wm_table = {
676 bw_params->wm_table.entries[i].wm_inst = i;
679 bw_params->wm_table.entries[i].valid = false;
683 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
684 bw_params->wm_table.entries[i].valid = true;
691 bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY
[all...] |
| amdgpu_rn_clk_mgr.c | 421 if (!bw_params->wm_table.entries[i].valid)
424 ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst;
425 ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type;
552 struct wm_table ddr4_wm_table = {
589 struct wm_table lpddr4_wm_table = {
676 bw_params->wm_table.entries[i].wm_inst = i;
679 bw_params->wm_table.entries[i].valid = false;
683 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
684 bw_params->wm_table.entries[i].valid = true;
691 bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_resource.c | 1018 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us =
1025 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us =
1036 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us =
1103 table_entry = &bw_params->wm_table.entries[WM_D];
1111 table_entry = &bw_params->wm_table.entries[WM_C];
1116 table_entry = &bw_params->wm_table.entries[WM_B];
1122 table_entry = &bw_params->wm_table.entries[WM_A];
|
| amdgpu_dcn21_resource.c | 1018 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us =
1025 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us =
1036 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us =
1103 table_entry = &bw_params->wm_table.entries[WM_D];
1111 table_entry = &bw_params->wm_table.entries[WM_C];
1116 table_entry = &bw_params->wm_table.entries[WM_B];
1122 table_entry = &bw_params->wm_table.entries[WM_A];
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| amdgpu_dcn21_resource.c | 1018 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us =
1025 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us =
1036 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us =
1103 table_entry = &bw_params->wm_table.entries[WM_D];
1111 table_entry = &bw_params->wm_table.entries[WM_C];
1116 table_entry = &bw_params->wm_table.entries[WM_B];
1122 table_entry = &bw_params->wm_table.entries[WM_A];
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_vega12_hwmgr.c | 2379 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); local in function:vega12_display_configuration_changed_task
2384 (uint8_t *)wm_table, TABLE_WATERMARKS, false);
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| amdgpu_vega12_hwmgr.c | 2379 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); local in function:vega12_display_configuration_changed_task
2384 (uint8_t *)wm_table, TABLE_WATERMARKS, false);
|
| amdgpu_vega12_hwmgr.c | 2379 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); local in function:vega12_display_configuration_changed_task
2384 (uint8_t *)wm_table, TABLE_WATERMARKS, false);
|
| amdgpu_vega20_hwmgr.c | 3557 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); local in function:vega20_display_configuration_changed_task
3562 (uint8_t *)wm_table, TABLE_WATERMARKS, false);
|
| amdgpu_vega20_hwmgr.c | 3557 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); local in function:vega20_display_configuration_changed_task
3562 (uint8_t *)wm_table, TABLE_WATERMARKS, false);
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| amdgpu_vega20_hwmgr.c | 3557 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); local in function:vega20_display_configuration_changed_task
3562 (uint8_t *)wm_table, TABLE_WATERMARKS, false);
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| amdgpu_vega10_hwmgr.c | 4656 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); local in function:vega10_display_configuration_changed_task
4661 result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false);
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| amdgpu_vega10_hwmgr.c | 4656 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); local in function:vega10_display_configuration_changed_task
4661 result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false);
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| amdgpu_vega10_hwmgr.c | 4656 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); local in function:vega10_display_configuration_changed_task
4661 result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false);
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