| /src/tests/usr.bin/xlint/lint1/ |
| msg_306.c | 16 u8 = 0x100;
19 /* expect+1: warning: constant 0x100 truncated by conversion, op '&=' [306] */
20 u8 &= 0x100;
22 u8 = u8 & 0x100;
25 /* expect+1: warning: constant 0x100 truncated by conversion, op '|=' [306] */
26 u8 |= 0x100;
28 u8 = u8 | 0x100;
31 /* expect+1: warning: constant 0x100 truncated by conversion, op '&=' [306] */
32 s8 &= 0x100;
34 s8 = s8 & 0x100;
[all...] |
| msg_306.c | 16 u8 = 0x100;
19 /* expect+1: warning: constant 0x100 truncated by conversion, op '&=' [306] */
20 u8 &= 0x100;
22 u8 = u8 & 0x100;
25 /* expect+1: warning: constant 0x100 truncated by conversion, op '|=' [306] */
26 u8 |= 0x100;
28 u8 = u8 | 0x100;
31 /* expect+1: warning: constant 0x100 truncated by conversion, op '&=' [306] */
32 s8 &= 0x100;
34 s8 = s8 & 0x100;
[all...] |
| /src/sys/dev/ic/ |
| igpioreg.h | 98 { "INT344B", 0, 0, 47, 0x100, 0x120 },
99 { "INT344B", 1, 48, 119, 0x100, 0x120 },
100 { "INT344B", 2, 120, 151, 0x100, 0x120 },
103 { "INT3451", 0, 0, 47, 0x100, 0x120 },
104 { "INT3451", 1, 48, 180, 0x100, 0x120 },
105 { "INT3451", 2, 181, 191, 0x100, 0x120 },
108 { "INT345D", 0, 0, 47, 0x100, 0x120 },
109 { "INT345D", 1, 48, 180, 0x100, 0x120 },
110 { "INT345D", 2, 181, 191, 0x100, 0x120 },
121 { "INT3450", 0, 0, 50, 0x100, 0x120 }
[all...] |
| igpioreg.h | 98 { "INT344B", 0, 0, 47, 0x100, 0x120 },
99 { "INT344B", 1, 48, 119, 0x100, 0x120 },
100 { "INT344B", 2, 120, 151, 0x100, 0x120 },
103 { "INT3451", 0, 0, 47, 0x100, 0x120 },
104 { "INT3451", 1, 48, 180, 0x100, 0x120 },
105 { "INT3451", 2, 181, 191, 0x100, 0x120 },
108 { "INT345D", 0, 0, 47, 0x100, 0x120 },
109 { "INT345D", 1, 48, 180, 0x100, 0x120 },
110 { "INT345D", 2, 181, 191, 0x100, 0x120 },
121 { "INT3450", 0, 0, 50, 0x100, 0x120 }
[all...] |
| aic77xxreg.h | 34 #define AHC_EISA_IOSIZE 0x100
|
| aic77xxreg.h | 34 #define AHC_EISA_IOSIZE 0x100
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| dra62x.dtsi | 16 <0x1200 0x100>;
20 reg = <0x1000 0x100>;
|
| dra62x.dtsi | 16 <0x1200 0x100>;
20 reg = <0x1000 0x100>;
|
| /src/sys/arch/arm/imx/ |
| imxspireg.h | 35 #define SPI_SIZE 0x100
|
| imxspireg.h | 35 #define SPI_SIZE 0x100
|
| /src/sys/external/bsd/drm2/dist/drm/vmwgfx/device_include/ |
| svga3d_caps.h | 69 SVGA3DCAPS_RECORD_DEVCAPS_MIN = 0x100,
70 SVGA3DCAPS_RECORD_DEVCAPS = 0x100,
|
| svga3d_caps.h | 69 SVGA3DCAPS_RECORD_DEVCAPS_MIN = 0x100,
70 SVGA3DCAPS_RECORD_DEVCAPS = 0x100,
|
| /src/sys/arch/sh3/include/ |
| fpreg.h | 41 #define FPSCR_EXCEPTION_UNDERFLOW 0x100 /* Underflow */
|
| fpreg.h | 41 #define FPSCR_EXCEPTION_UNDERFLOW 0x100 /* Underflow */
|
| /src/sys/dev/isa/ |
| elink.h | 32 #define ELINK_ID_PORT 0x100
|
| elink.h | 32 #define ELINK_ID_PORT 0x100
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/sprd/ |
| sharkl64.dtsi | 28 reg = <0 0x70000000 0 0x100>;
36 reg = <0 0x70100000 0 0x100>;
44 reg = <0 0x70200000 0 0x100>;
52 reg = <0 0x70300000 0 0x100>;
|
| sharkl64.dtsi | 28 reg = <0 0x70000000 0 0x100>;
36 reg = <0 0x70100000 0 0x100>;
44 reg = <0 0x70200000 0 0x100>;
52 reg = <0 0x70300000 0 0x100>;
|
| /src/sys/arch/arm/broadcom/ |
| bcm2835_dmac.h | 34 #define DMAC_CS(n) (0x00 + (0x100 * (n)))
50 #define DMAC_CONBLK_AD(n) (0x04 + (0x100 * (n)))
51 #define DMAC_TI(n) (0x08 + (0x100 * (n)))
52 #define DMAC_SOURCE_AD(n) (0x0c + (0x100 * (n)))
53 #define DMAC_DEST_AD(n) (0x10 + (0x100 * (n)))
54 #define DMAC_TXFR_LEN(n) (0x14 + (0x100 * (n)))
55 #define DMAC_STRIDE(n) (0x18 + (0x100 * (n)))
56 #define DMAC_NEXTCONBK(n) (0x1c + (0x100 * (n)))
57 #define DMAC_DEBUG(n) (0x20 + (0x100 * (n)))
|
| bcm2835_dmac.h | 34 #define DMAC_CS(n) (0x00 + (0x100 * (n)))
50 #define DMAC_CONBLK_AD(n) (0x04 + (0x100 * (n)))
51 #define DMAC_TI(n) (0x08 + (0x100 * (n)))
52 #define DMAC_SOURCE_AD(n) (0x0c + (0x100 * (n)))
53 #define DMAC_DEST_AD(n) (0x10 + (0x100 * (n)))
54 #define DMAC_TXFR_LEN(n) (0x14 + (0x100 * (n)))
55 #define DMAC_STRIDE(n) (0x18 + (0x100 * (n)))
56 #define DMAC_NEXTCONBK(n) (0x1c + (0x100 * (n)))
57 #define DMAC_DEBUG(n) (0x20 + (0x100 * (n)))
|
| /src/sys/arch/arm/nvidia/ |
| tegra_timerreg.h | 63 #define WDT0_CONFIG_REG 0x100
67 #define WDT1_CONFIG_REG 0x100
71 #define WDT2_CONFIG_REG 0x100
75 #define WDT3_CONFIG_REG 0x100
79 #define WDT4_CONFIG_REG 0x100
|
| tegra_timerreg.h | 63 #define WDT0_CONFIG_REG 0x100
67 #define WDT1_CONFIG_REG 0x100
71 #define WDT2_CONFIG_REG 0x100
75 #define WDT3_CONFIG_REG 0x100
79 #define WDT4_CONFIG_REG 0x100
|
| /src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/ralink/ |
| mt7620a.dtsi | 30 reg = <0x0 0x100>;
35 reg = <0x200 0x100>;
46 reg = <0x300 0x100>;
51 reg = <0xc00 0x100>;
|
| rt2880.dtsi | 30 reg = <0x0 0x100>;
35 reg = <0x200 0x100>;
46 reg = <0x300 0x100>;
51 reg = <0xc00 0x100>;
|
| rt3883.dtsi | 30 reg = <0x0 0x100>;
35 reg = <0x200 0x100>;
46 reg = <0x300 0x100>;
51 reg = <0xc00 0x100>;
|
