/src/sys/dev/ic/ |
igpioreg.h | 132 { "INT3455", 0, 0, 58, 0x100, 0x110 }, 133 { "INT3455", 1, 59, 152, 0x100, 0x110 }, 134 { "INT3455", 2, 153, 215, 0x100, 0x110 }, 135 { "INT3455", 3, 216, 240, 0x100, 0x110 }, 144 { "INT34C4", 0, 0, 59, 0x100, 0x110 }, 145 { "INT34C4", 1, 60, 148, 0x100, 0x110 }, 146 { "INT34C4", 2, 149, 237, 0x100, 0x110 }, 147 { "INT34C4", 3, 238, 266, 0x100, 0x110 }, 195 { "INT3536", 0, 0, 71, 0x100, 0x110 }, 196 { "INT3536", 1, 72, 132, 0x100, 0x110 }, [all...] |
igpioreg.h | 132 { "INT3455", 0, 0, 58, 0x100, 0x110 }, 133 { "INT3455", 1, 59, 152, 0x100, 0x110 }, 134 { "INT3455", 2, 153, 215, 0x100, 0x110 }, 135 { "INT3455", 3, 216, 240, 0x100, 0x110 }, 144 { "INT34C4", 0, 0, 59, 0x100, 0x110 }, 145 { "INT34C4", 1, 60, 148, 0x100, 0x110 }, 146 { "INT34C4", 2, 149, 237, 0x100, 0x110 }, 147 { "INT34C4", 3, 238, 266, 0x100, 0x110 }, 195 { "INT3536", 0, 0, 71, 0x100, 0x110 }, 196 { "INT3536", 1, 72, 132, 0x100, 0x110 }, [all...] |
/src/sys/arch/arm/imx/ |
imx23_apbxdmareg.h | 50 #define HW_APBX_CH0_NXTCMDAR 0x110
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imx23_apbxdmareg.h | 50 #define HW_APBX_CH0_NXTCMDAR 0x110
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/src/sys/arch/arm/nvidia/ |
tegra_pciereg.h | 59 #define AFI_PEXn_CTRL_REG(n) (0x110 + (n) * 8)
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tegra_pciereg.h | 59 #define AFI_PEXn_CTRL_REG(n) (0x110 + (n) * 8)
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/src/sys/arch/arm/samsung/ |
mct_reg.h | 38 #define MCT_G_CNT_WSTAT 0x110 /* wait for write OK cntr */
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mct_reg.h | 38 #define MCT_G_CNT_WSTAT 0x110 /* wait for write OK cntr */
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/src/sys/arch/hpcmips/dev/ |
plumicureg.h | 74 #define PLUM_INT_EXTIEN_REG 0x110
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plumicureg.h | 74 #define PLUM_INT_EXTIEN_REG 0x110
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/src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/ |
lpc18xx-ccu.h | 17 #define CLK_APB3_DAC 0x110
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lpc18xx-ccu.h | 17 #define CLK_APB3_DAC 0x110
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/src/sys/arch/ia64/include/ |
setjmp.h | 70 #define J_F23 0x110
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setjmp.h | 70 #define J_F23 0x110
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/src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
stih407-family.dtsi | 273 reg = <0x9840000 0x110>; 287 reg = <0x9841000 0x110>; 302 reg = <0x9842000 0x110>; 317 reg = <0x9843000 0x110>; 332 reg = <0x9844000 0x110>; 347 reg = <0x9845000 0x110>; 364 reg = <0x9540000 0x110>; 379 reg = <0x9541000 0x110>; 458 reg = <0x9840000 0x110>; 472 reg = <0x9841000 0x110>; [all...] |
stih407-family.dtsi | 273 reg = <0x9840000 0x110>; 287 reg = <0x9841000 0x110>; 302 reg = <0x9842000 0x110>; 317 reg = <0x9843000 0x110>; 332 reg = <0x9844000 0x110>; 347 reg = <0x9845000 0x110>; 364 reg = <0x9540000 0x110>; 379 reg = <0x9541000 0x110>; 458 reg = <0x9840000 0x110>; 472 reg = <0x9841000 0x110>; [all...] |
/src/sys/arch/powerpc/include/ |
spr.h | 136 #define SPR_SPRG0 0x110 /* E468 SPR General 0 */
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spr.h | 136 #define SPR_SPRG0 0x110 /* E468 SPR General 0 */
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/src/sys/dev/pci/qat/ |
qat_c3xxxreg.h | 115 #define RICPPINTCTL_C3XXX (0x3A000 + 0x110)
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qat_c3xxxreg.h | 115 #define RICPPINTCTL_C3XXX (0x3A000 + 0x110)
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qat_c62xreg.h | 118 #define RICPPINTCTL_C62X (0x3A000 + 0x110)
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qat_d15xxreg.h | 118 #define RICPPINTCTL_D15XX (0x3A000 + 0x110)
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qat_c62xreg.h | 118 #define RICPPINTCTL_C62X (0x3A000 + 0x110)
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/src/sys/arch/amiga/dev/ |
ioblix_zbus.c | 93 { "com", 0x110, 24000000 },
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ioblix_zbus.c | 93 { "com", 0x110, 24000000 },
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