| /src/sys/arch/arm/nvidia/ |
| tegra_mcreg.h | 85 #define MC_SMMU_TRANSLATION_ENABLE_2_REG 0x230
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| tegra_mcreg.h | 85 #define MC_SMMU_TRANSLATION_ENABLE_2_REG 0x230
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| /src/sys/dev/ic/ |
| igpioreg.h | 213 { "INTC3001", 0, 0, 167, 0x200, 0x230 },
214 { "INTC3001", 1, 168, 236, 0x200, 0x230 },
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| igpioreg.h | 213 { "INTC3001", 0, 0, 167, 0x200, 0x230 },
214 { "INTC3001", 1, 168, 236, 0x200, 0x230 },
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| mvsatareg.h | 174 #define DMA_DTHBA 0x230 /* Descriptor Table High Base Address */
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| /src/sys/external/bsd/drm2/dist/drm/i915/gt/ |
| intel_lrc.h | 40 #define RING_ELSP(base) _MMIO((base) + 0x230)
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| intel_lrc.h | 40 #define RING_ELSP(base) _MMIO((base) + 0x230)
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| /src/sys/dev/gpib/ |
| rdreg.h | 77 #define RD2203AID 0x230 /* yet another guess */
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| rdreg.h | 77 #define RD2203AID 0x230 /* yet another guess */
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| /src/sys/arch/arm/samsung/ |
| exynos_reg.h | 189 #define EXYNOS5_SYSREG_USB20_PHY_TYPE 0x230
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| exynos_reg.h | 189 #define EXYNOS5_SYSREG_USB20_PHY_TYPE 0x230
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| exynos_usbphy.c | 49 #define USB20PHY_CFG 0x230
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| /src/sys/arch/powerpc/include/mpc8xx/ |
| spr.h | 43 #define SPR_IC_CST 0x230 /* ..8 Instruction Cache CSR */
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| spr.h | 43 #define SPR_IC_CST 0x230 /* ..8 Instruction Cache CSR */
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| /src/sys/dev/eisa/ |
| bha_eisa.c | 77 port = 0x230;
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| bha_eisa.c | 77 port = 0x230;
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| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| trinityd.h | 172 #define SMC_RESP_0 0x230
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| trinityd.h | 172 #define SMC_RESP_0 0x230
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| /src/sys/arch/arm/marvell/ |
| mv78xx0reg.h | 180 #define MV78XX0_ICI_EIMLR 0x230 /* Endpoint Intr Mask Low */
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| mv78xx0reg.h | 180 #define MV78XX0_ICI_EIMLR 0x230 /* Endpoint Intr Mask Low */
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| /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/ |
| am4.h | 19 #define AM4_COUNTER_32K_CLKCTRL AM4_CLKCTRL_INDEX(0x230)
120 #define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230)
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| am4.h | 19 #define AM4_COUNTER_32K_CLKCTRL AM4_CLKCTRL_INDEX(0x230)
120 #define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230)
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| /src/sys/arch/arm/ti/ |
| omap2_gpmcreg.h | 167 #define GPMC_TESTMODE_CTRL 0x230
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| /src/sys/arch/sparc64/dev/ |
| ffbreg.h | 163 #define FFB_FBC_DCSF 0x230
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| /src/sys/dev/isa/ |
| dpt_isa.c | 72 static const int dpt_isa_iobases[] = { 0x230, 0x330, 0x1f0, 0x170, 0 };
|
