atomic_swap.S revision 1.3
11.3Smatt/*	$NetBSD: atomic_swap.S,v 1.3 2012/08/16 16:49:10 matt Exp $	*/
21.2Smatt
31.2Smatt/*-
41.3Smatt * Copyright (c) 2007,2012 The NetBSD Foundation, Inc.
51.2Smatt * All rights reserved.
61.2Smatt *
71.2Smatt * This code is derived from software contributed to The NetBSD Foundation
81.2Smatt * by Jason R. Thorpe and Matt Thomas.
91.2Smatt *
101.2Smatt * Redistribution and use in source and binary forms, with or without
111.2Smatt * modification, are permitted provided that the following conditions
121.2Smatt * are met:
131.2Smatt * 1. Redistributions of source code must retain the above copyright
141.2Smatt *    notice, this list of conditions and the following disclaimer.
151.2Smatt * 2. Redistributions in binary form must reproduce the above copyright
161.2Smatt *    notice, this list of conditions and the following disclaimer in the
171.2Smatt *    documentation and/or other materials provided with the distribution.
181.2Smatt *
191.2Smatt * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
201.2Smatt * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
211.2Smatt * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
221.2Smatt * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
231.2Smatt * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
241.2Smatt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
251.2Smatt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
261.2Smatt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
271.2Smatt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
281.2Smatt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
291.2Smatt * POSSIBILITY OF SUCH DAMAGE.
301.2Smatt */
311.2Smatt
321.2Smatt#include "atomic_op_asm.h"
331.2Smatt
341.3Smatt/*
351.3Smatt * While SWP{B} is sufficient on its own for pre-ARMv7 CPUs, on MP ARMv7 cores
361.3Smatt * SWP{B} is disabled since it's no longer atomic among multiple CPUs.  They
371.3Smatt * will actually raise an UNDEFINED exception.
381.3Smatt *
391.3Smatt * So if we use the LDREX/STREX template, but use a SWP instruction followed
401.3Smatt * by a MOV instruction (using a temporary register), that gives a handler
411.3Smatt * for the SWP UNDEFINED exception enough information to "patch" this instance
421.3Smatt * SWP with correct forms of LDREX/STREX.  (note that this would happen even
431.3Smatt * "read-only" pages.  If the page gets tossed, we will get another exception
441.3Smatt * and fix yet again).
451.3Smatt */
461.3Smatt
471.2SmattENTRY_NP(_atomic_swap_32)
481.3Smatt	mov	r2, r0
491.3Smatt1:
501.3Smatt#ifdef _ARM_ARCH_6
511.3Smatt	ldrex	r0, [r2]
521.3Smatt	strex	r3, r1, [r2]
531.3Smatt#else
541.3Smatt	swp	r0, r1, [r2]
551.3Smatt	mov	r3, #0
561.3Smatt#endif
571.3Smatt	cmp	r3, #0
581.3Smatt	bne	1b
591.2Smatt	RET
601.2Smatt	END(_atomic_swap_32)
611.2SmattATOMIC_OP_ALIAS(atomic_swap_32,_atomic_swap_32)
621.2SmattATOMIC_OP_ALIAS(atomic_swap_uint,_atomic_swap_32)
631.2SmattATOMIC_OP_ALIAS(atomic_swap_ulong,_atomic_swap_32)
641.2SmattATOMIC_OP_ALIAS(atomic_swap_ptr,_atomic_swap_32)
651.2SmattSTRONG_ALIAS(_atomic_swap_uint,_atomic_swap_32)
661.2SmattSTRONG_ALIAS(_atomic_swap_ulong,_atomic_swap_32)
671.2SmattSTRONG_ALIAS(_atomic_swap_ptr,_atomic_swap_32)
681.2Smatt
691.2SmattENTRY_NP(_atomic_swap_8)
701.3Smatt	mov	r2, r0
711.3Smatt1:
721.3Smatt#ifdef _ARM_ARCH_6
731.3Smatt	ldrexb	r0, [r2]
741.3Smatt	strexb	r3, r1, [r2]
751.3Smatt#else
761.3Smatt	swpb	r0, r1, [r2]
771.3Smatt	mov	r3, #0
781.3Smatt#endif
791.3Smatt	cmp	r3, #0
801.3Smatt	bne	1b
811.2Smatt	RET
821.2Smatt	END(_atomic_swap_8)
831.2SmattATOMIC_OP_ALIAS(atomic_swap_8,_atomic_swap_8)
841.2SmattATOMIC_OP_ALIAS(atomic_swap_char,_atomic_swap_8)
851.2SmattATOMIC_OP_ALIAS(atomic_swap_uchar,_atomic_swap_8)
861.3SmattSTRONG_ALIAS(_atomic_swap_char,_atomic_swap_8)
871.3SmattSTRONG_ALIAS(_atomic_swap_uchar,_atomic_swap_8)
88