atomic_swap_64.S revision 1.1 
1/*	$NetBSD: atomic_swap_64.S,v 1.1 2012/09/11 20:51:25 matt Exp $	*/
2
3/*-
4 * Copyright (c) 2007,2012 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe and Matt Thomas.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#include "atomic_op_asm.h"
33
34/*
35 * While SWP{B} is sufficient on its own for pre-ARMv7 CPUs, on MP ARMv7 cores
36 * SWP{B} is disabled since it's no longer atomic among multiple CPUs.  They
37 * will actually raise an UNDEFINED exception.
38 *
39 * So if we use the LDREX/STREX template, but use a SWP instruction followed
40 * by a MOV instruction (using a temporary register), that gives a handler
41 * for the SWP UNDEFINED exception enough information to "patch" this instance
42 * SWP with correct forms of LDREX/STREX.  (note that this would happen even
43 * "read-only" pages.  If the page gets tossed, we will get another exception
44 * and fix yet again).
45 */
46
47ENTRY_NP(_atomic_swap_64)
48	str	r4, [sp, #-4]!		/* save temporary */
49	mov	r4, r0			/* return value will be in r0 */
50#ifndef __ARM_EABI__
51	mov	r3, r2			/* r2 will be overwriten by r1 */
52	mov	r2, r1			/* and r1 will be overwritten by ldrexd */
53#endif
541:
55	ldrexd	r0, [r4]		/* load old value */
56	strexd	ip, r2, [r4]		/* store new value */
57	cmpne	ip, #0			/*    succeed? */
58	bne	1b			/*    no, try again */
59#ifdef _ARM_ARCH_7
60	dmb
61#else
62	mcr	p15, 0, ip, c7, c10, 5	/* data memory barrier */
63#endif
64	ldr	r4, [sp], #4		/* restore temporary */
65	RET
66	END(_atomic_swap_64)
67ATOMIC_OP_ALIAS(atomic_swap_64,_atomic_swap_64)
68