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atomic_cas.S revision 1.3
      1  1.3  ad /*	$NetBSD: atomic_cas.S,v 1.3 2007/12/08 22:42:46 ad Exp $	*/
      2  1.2  ad 
      3  1.2  ad /*-
      4  1.2  ad  * Copyright (c) 2007 The NetBSD Foundation, Inc.
      5  1.2  ad  * All rights reserved.
      6  1.2  ad  *
      7  1.2  ad  * This code is derived from software contributed to The NetBSD Foundation
      8  1.2  ad  * by Andrew Doran and Jason R. Thorpe.
      9  1.2  ad  *
     10  1.2  ad  * Redistribution and use in source and binary forms, with or without
     11  1.2  ad  * modification, are permitted provided that the following conditions
     12  1.2  ad  * are met:
     13  1.2  ad  * 1. Redistributions of source code must retain the above copyright
     14  1.2  ad  *    notice, this list of conditions and the following disclaimer.
     15  1.2  ad  * 2. Redistributions in binary form must reproduce the above copyright
     16  1.2  ad  *    notice, this list of conditions and the following disclaimer in the
     17  1.2  ad  *    documentation and/or other materials provided with the distribution.
     18  1.2  ad  * 3. All advertising materials mentioning features or use of this software
     19  1.2  ad  *    must display the following acknowledgement:
     20  1.2  ad  *	This product includes software developed by the NetBSD
     21  1.2  ad  *	Foundation, Inc. and its contributors.
     22  1.2  ad  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23  1.2  ad  *    contributors may be used to endorse or promote products derived
     24  1.2  ad  *    from this software without specific prior written permission.
     25  1.2  ad  *
     26  1.2  ad  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27  1.2  ad  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28  1.2  ad  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29  1.2  ad  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30  1.2  ad  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31  1.2  ad  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32  1.2  ad  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33  1.2  ad  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34  1.2  ad  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35  1.2  ad  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36  1.2  ad  * POSSIBILITY OF SUCH DAMAGE.
     37  1.2  ad  */
     38  1.2  ad 
     39  1.2  ad #include "atomic_op_asm.h"
     40  1.2  ad 
     41  1.2  ad #if defined(_KERNEL)
     42  1.2  ad 
     43  1.3  ad #include <machine/psl.h>
     44  1.3  ad 
     45  1.2  ad #include "opt_multiprocessor.h"
     46  1.2  ad 
     47  1.2  ad #define	DISABLE_INTERRUPTS						 \
     48  1.3  ad 	rd	%psr, %o4			/* disable interrupts */;\
     49  1.3  ad 	or	%o4, PSR_PIL, %o5					;\
     50  1.2  ad 	wr	%o5, 0, %psr						;\
     51  1.2  ad 	nop								;\
     52  1.2  ad 	nop								;\
     53  1.2  ad 	nop
     54  1.2  ad 
     55  1.2  ad #define	RESTORE_INTERRUPTS						 \
     56  1.3  ad 	wr	%o4, 0, %psr			/* enable interrupts */	;\
     57  1.2  ad 	nop								;\
     58  1.2  ad 	nop								;\
     59  1.2  ad 	nop
     60  1.2  ad 
     61  1.2  ad #if defined(MULTIPROCESSOR)
     62  1.2  ad 	.section .bss
     63  1.2  ad 	.align	1024
     64  1.2  ad OTYPE(_C_LABEL(_atomic_cas_locktab))
     65  1.2  ad _C_LABEL(_atomic_cas_locktab):
     66  1.2  ad 	.space	1024
     67  1.2  ad 
     68  1.2  ad #define	ACQUIRE_INTERLOCK						 \
     69  1.2  ad 	DISABLE_INTERRUPTS						;\
     70  1.3  ad 	srl	%o0, 3, %o5			/* get lock address */	;\
     71  1.2  ad 	and	%o5, 1023, %o5						;\
     72  1.3  ad 	sethi	%hi(_C_LABEL(_atomic_cas_locktab)), %o3			;\
     73  1.2  ad 	add	%o5, %o3, %o5						;\
     74  1.2  ad 									;\
     75  1.3  ad 	/* %o5 has interlock address */					;\
     76  1.2  ad 									;\
     77  1.3  ad 1:	ldstub	[%o5], %o3			/* acquire lock */	;\
     78  1.2  ad 	tst	%o3							;\
     79  1.2  ad 	bz,a	2f							;\
     80  1.2  ad 	 nop								;\
     81  1.2  ad 	nop								;\
     82  1.2  ad 	nop								;\
     83  1.3  ad 	b,a	1b				/* spin	*/		;\
     84  1.2  ad 	 nop								;\
     85  1.3  ad 	/* We now hold the interlock */					;\
     86  1.2  ad 2:
     87  1.2  ad 
     88  1.2  ad #define	RELEASE_INTERLOCK						 \
     89  1.3  ad 	stb	%g0, [%o5]			/* release interlock */	;\
     90  1.2  ad 	RESTORE_INTERRUPTS
     91  1.2  ad 
     92  1.2  ad #else /* ! MULTIPROCESSOR */
     93  1.2  ad 
     94  1.2  ad #define	ACQUIRE_INTERLOCK	DISABLE_INTERRUPTS
     95  1.2  ad 
     96  1.2  ad #define	RELEASE_INTERLOCK	RESTORE_INTERRUPTS
     97  1.2  ad 
     98  1.2  ad #endif /* MULTIPROCESSOR */
     99  1.2  ad 
    100  1.2  ad 	.text
    101  1.2  ad 
    102  1.2  ad /*
    103  1.2  ad  * The v7 and v8 SPARC doesn't have compare-and-swap, so we block interrupts
    104  1.2  ad  * and use an interlock.
    105  1.2  ad  *
    106  1.2  ad  * XXX On single CPU systems, this should use a restartable sequence:
    107  1.2  ad  * XXX there we don't need the overhead of interlocking.
    108  1.2  ad  *
    109  1.2  ad  * XXX NOTE!  The interlock trick only works if EVERYTHING writes to
    110  1.2  ad  * XXX the memory cell through this code path!
    111  1.2  ad  */
    112  1.2  ad ENTRY_NOPROFILE(_atomic_cas_32)
    113  1.2  ad 	ACQUIRE_INTERLOCK
    114  1.2  ad 	! %o4 has saved PSR value
    115  1.2  ad 	! %o5 has interlock address
    116  1.2  ad 
    117  1.2  ad 	ld	[%o0], %o3			! get old value
    118  1.2  ad 	cmp	%o1, %o3			! old == new?
    119  1.2  ad 	beq,a	3f				! yes, do the store
    120  1.2  ad 	 st	%o2, [%o0]			! (in the delay slot)
    121  1.2  ad 
    122  1.2  ad 3:	RELEASE_INTERLOCK
    123  1.2  ad 
    124  1.2  ad 	retl
    125  1.2  ad 	 mov	%o3, %o0			! return old value
    126  1.2  ad 
    127  1.2  ad ATOMIC_OP_ALIAS(atomic_cas_32,_atomic_cas_32)
    128  1.2  ad ATOMIC_OP_ALIAS(atomic_cas_uint,_atomic_cas_32)
    129  1.2  ad STRONG_ALIAS(_atomic_cas_uint,_atomic_cas_32)
    130  1.2  ad ATOMIC_OP_ALIAS(atomic_cas_ulong,_atomic_cas_32)
    131  1.2  ad STRONG_ALIAS(_atomic_cas_ulong,_atomic_cas_32)
    132  1.2  ad ATOMIC_OP_ALIAS(atomic_cas_ptr,_atomic_cas_32)
    133  1.2  ad STRONG_ALIAS(_atomic_cas_ptr,_atomic_cas_32)
    134  1.2  ad 
    135  1.2  ad #else /* _KERNEL */
    136  1.2  ad 
    137  1.2  ad #endif /* _KERNEL */
    138