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atomic_cas.S revision 1.10 
      1 /*	$NetBSD: atomic_cas.S,v 1.10 2009/03/13 16:40:22 nakayama Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 2007, 2008 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Andrew Doran and Jason R. Thorpe.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #include <sys/param.h>
     33 #include "atomic_op_asm.h"
     34 
     35 #if defined(_HARDKERNEL)
     36 
     37 #include <machine/psl.h>
     38 
     39 #include "opt_multiprocessor.h"
     40 
     41 #define	DISABLE_INTERRUPTS						 \
     42 	rd	%psr, %o4			/* disable interrupts */;\
     43 	or	%o4, PSR_PIL, %o5					;\
     44 	wr	%o5, 0, %psr						;\
     45 	nop								;\
     46 	nop								;\
     47 	nop
     48 
     49 #define	RESTORE_INTERRUPTS						 \
     50 	wr	%o4, 0, %psr			/* enable interrupts */	;\
     51 	nop								;\
     52 	nop								;\
     53 	nop
     54 
     55 #else	/* _HARDKERNEL */
     56 
     57 #define	MULTIPROCESSOR	1
     58 #define	DISABLE_INTERRUPTS		/* nothing */
     59 #define	RESTORE_INTERRUPTS		/* nothing */
     60 
     61 #endif	/* _HARDKERNEL */
     62 
     63 #if defined(MULTIPROCESSOR)
     64 	.section .bss
     65 	.align	1024
     66 OTYPE(_C_LABEL(_atomic_cas_locktab))
     67 _C_LABEL(_atomic_cas_locktab):
     68 	.space	1024
     69 
     70 #define	ACQUIRE_INTERLOCK						 \
     71 	DISABLE_INTERRUPTS						;\
     72 	srl	%o0, 3, %o5			/* get lock address */	;\
     73 	and	%o5, 1023, %o5						;\
     74 	sethi	%hi(_C_LABEL(_atomic_cas_locktab)), %o3			;\
     75 	add	%o5, %o3, %o5						;\
     76 									;\
     77 	/* %o5 has interlock address */					;\
     78 									;\
     79 1:	ldstub	[%o5], %o3			/* acquire lock */	;\
     80 	tst	%o3							;\
     81 	bz,a	2f							;\
     82 	 nop								;\
     83 	nop								;\
     84 	nop								;\
     85 	b,a	1b				/* spin	*/		;\
     86 	 nop								;\
     87 	/* We now hold the interlock */					;\
     88 2:
     89 
     90 #define	RELEASE_INTERLOCK						 \
     91 	stb	%g0, [%o5]			/* release interlock */	;\
     92 	RESTORE_INTERRUPTS
     93 
     94 #else /* ! MULTIPROCESSOR */
     95 
     96 #define	ACQUIRE_INTERLOCK	DISABLE_INTERRUPTS
     97 
     98 #define	RELEASE_INTERLOCK	RESTORE_INTERRUPTS
     99 
    100 #endif /* MULTIPROCESSOR */
    101 
    102 	.text
    103 
    104 /*
    105  * The v7 and v8 SPARC doesn't have compare-and-swap, so we block interrupts
    106  * and use an interlock.
    107  *
    108  * XXX On single CPU systems, this should use a restartable sequence:
    109  * XXX there we don't need the overhead of interlocking.
    110  *
    111  * XXX NOTE!  The interlock trick only works if EVERYTHING writes to
    112  * XXX the memory cell through this code path!
    113  */
    114 ENTRY(_atomic_cas_32)
    115 	ACQUIRE_INTERLOCK
    116 	! %o4 has saved PSR value
    117 	! %o5 has interlock address
    118 
    119 	ld	[%o0], %o3			! get old value
    120 	cmp	%o1, %o3			! old == new?
    121 	beq,a	3f				! yes, do the store
    122 	 st	%o2, [%o0]			! (in the delay slot)
    123 
    124 3:	RELEASE_INTERLOCK
    125 
    126 	retl
    127 	 mov	%o3, %o0			! return old value
    128 
    129 ATOMIC_OP_ALIAS(atomic_cas_32,_atomic_cas_32)
    130 ATOMIC_OP_ALIAS(atomic_cas_uint,_atomic_cas_32)
    131 STRONG_ALIAS(_atomic_cas_uint,_atomic_cas_32)
    132 ATOMIC_OP_ALIAS(atomic_cas_ulong,_atomic_cas_32)
    133 STRONG_ALIAS(_atomic_cas_ulong,_atomic_cas_32)
    134 ATOMIC_OP_ALIAS(atomic_cas_ptr,_atomic_cas_32)
    135 STRONG_ALIAS(_atomic_cas_ptr,_atomic_cas_32)
    136 
    137 ATOMIC_OP_ALIAS(atomic_cas_32_ni,_atomic_cas_32)
    138 STRONG_ALIAS(_atomic_cas_32_ni,_atomic_cas_32)
    139 ATOMIC_OP_ALIAS(atomic_cas_uint_ni,_atomic_cas_32)
    140 STRONG_ALIAS(_atomic_cas_uint_ni,_atomic_cas_32)
    141 ATOMIC_OP_ALIAS(atomic_cas_ulong_ni,_atomic_cas_32)
    142 STRONG_ALIAS(_atomic_cas_ulong_ni,_atomic_cas_32)
    143 ATOMIC_OP_ALIAS(atomic_cas_ptr_ni,_atomic_cas_32)
    144 STRONG_ALIAS(_atomic_cas_ptr_ni,_atomic_cas_32)
    145