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atomic_cas.S revision 1.2 
      1 /*	$NetBSD: atomic_cas.S,v 1.2 2007/11/29 02:01:22 ad Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 2007 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Andrew Doran and Jason R. Thorpe.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  * 3. All advertising materials mentioning features or use of this software
     19  *    must display the following acknowledgement:
     20  *	This product includes software developed by the NetBSD
     21  *	Foundation, Inc. and its contributors.
     22  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23  *    contributors may be used to endorse or promote products derived
     24  *    from this software without specific prior written permission.
     25  *
     26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36  * POSSIBILITY OF SUCH DAMAGE.
     37  */
     38 
     39 #include "atomic_op_asm.h"
     40 
     41 #if defined(_KERNEL)
     42 
     43 #include "opt_multiprocessor.h"
     44 
     45 #define	DISABLE_INTERRUPTS						 \
     46 	rd	%psr, %o4			! disable interrupts	;\
     47 	or	%o4, PSR_IPL, %o5					;\
     48 	wr	%o5, 0, %psr						;\
     49 	nop								;\
     50 	nop								;\
     51 	nop
     52 
     53 #define	RESTORE_INTERRUPTS						 \
     54 	wr	%o4, 0, %psr			! re-enable interrupts	;\
     55 	nop								;\
     56 	nop								;\
     57 	nop
     58 
     59 #if defined(MULTIPROCESSOR)
     60 	.section .bss
     61 	.align	1024
     62 OTYPE(_C_LABEL(_atomic_cas_locktab))
     63 _C_LABEL(_atomic_cas_locktab):
     64 	.space	1024
     65 
     66 #define	ACQUIRE_INTERLOCK						 \
     67 	DISABLE_INTERRUPTS						;\
     68 	srl	%o0, 3, %o5			! get interlock address	;\
     69 	and	%o5, 1023, %o5						;\
     70 	set	_C_LABEL(_atomic_cas_locktab), %o3			;\
     71 	add	%o5, %o3, %o5						;\
     72 									;\
     73 	! %o5 has interlock address					;\
     74 									;\
     75 1:	ldstub	[%o5], %o3			! acquire interlock	;\
     76 	tst	%o3							;\
     77 	bz,a	2f							;\
     78 	 nop								;\
     79 	nop								;\
     80 	nop								;\
     81 	b,a	1b				! spin			;\
     82 	 nop								;\
     83 									;\
     84 	! We now hold the interlock					;\
     85 2:
     86 
     87 #define	RELEASE_INTERLOCK						 \
     88 	stb	%g0, [%o5]			! release interlock	;\
     89 	RESTORE_INTERRUPTS
     90 
     91 #else /* ! MULTIPROCESSOR */
     92 
     93 #define	ACQUIRE_INTERLOCK	DISABLE_INTERRUPTS
     94 
     95 #define	RELEASE_INTERLOCK	RESTORE_INTERRUPTS
     96 
     97 #endif /* MULTIPROCESSOR */
     98 
     99 	.text
    100 
    101 /*
    102  * The v7 and v8 SPARC doesn't have compare-and-swap, so we block interrupts
    103  * and use an interlock.
    104  *
    105  * XXX On single CPU systems, this should use a restartable sequence:
    106  * XXX there we don't need the overhead of interlocking.
    107  *
    108  * XXX NOTE!  The interlock trick only works if EVERYTHING writes to
    109  * XXX the memory cell through this code path!
    110  */
    111 ENTRY_NOPROFILE(_atomic_cas_32)
    112 	ACQUIRE_INTERLOCK
    113 	! %o4 has saved PSR value
    114 	! %o5 has interlock address
    115 
    116 	ld	[%o0], %o3			! get old value
    117 	cmp	%o1, %o3			! old == new?
    118 	beq,a	3f				! yes, do the store
    119 	 st	%o2, [%o0]			! (in the delay slot)
    120 
    121 3:	RELEASE_INTERLOCK
    122 
    123 	retl
    124 	 mov	%o3, %o0			! return old value
    125 
    126 ATOMIC_OP_ALIAS(atomic_cas_32,_atomic_cas_32)
    127 ATOMIC_OP_ALIAS(atomic_cas_uint,_atomic_cas_32)
    128 STRONG_ALIAS(_atomic_cas_uint,_atomic_cas_32)
    129 ATOMIC_OP_ALIAS(atomic_cas_ulong,_atomic_cas_32)
    130 STRONG_ALIAS(_atomic_cas_ulong,_atomic_cas_32)
    131 ATOMIC_OP_ALIAS(atomic_cas_ptr,_atomic_cas_32)
    132 STRONG_ALIAS(_atomic_cas_ptr,_atomic_cas_32)
    133 
    134 #else /* _KERNEL */
    135 
    136 #endif /* _KERNEL */
    137