11.1SmaxvKnown issues in NVMM, low priority in most cases.
21.1Smaxv
31.1Smaxv====== KERNEL NVMM DRIVER ======
41.1Smaxv
51.2Smaxv * 32bit-PAE guests can misbehave on Intel, because we need to manually
61.2Smaxv   install the PDPTEs, and currently we don't do it. In practice they don't
71.2Smaxv   misbehave because the emulator never has to interfere with CR3.
81.1Smaxv
91.4Smaxv * AMD: we don't support VCPU_CONF_TPR, would be nice to.
101.1Smaxv
111.5Smaxv * AMD: need to do comprehensive CPUID filtering, like we already do on
121.5Smaxv   Intel.
131.1Smaxv
141.1Smaxv====== LIBNVMM ======
151.1Smaxv
161.1Smaxv * There are still a few twisted corner cases we don't handle in the instruction
171.1Smaxv   emulator. For example if the guest makes an MMIO access relative to RSP, we
181.1Smaxv   must base the GVA on %SS and not %DS. This is tiring, and in practice, no
191.1Smaxv   guest is dumb enough to perform such accesses.
201.1Smaxv
211.4Smaxv * Maybe the __areas should have a rwlock? I don't think Qemu unmaps memory
221.4Smaxv   while VCPUs are running, but still.
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