TODO.nvmm revision 1.2
11.1SmaxvKnown issues in NVMM, low priority in most cases. 21.1Smaxv 31.1Smaxv====== KERNEL NVMM DRIVER ====== 41.1Smaxv 51.2Smaxv * 32bit-PAE guests can misbehave on Intel, because we need to manually 61.2Smaxv install the PDPTEs, and currently we don't do it. In practice they don't 71.2Smaxv misbehave because the emulator never has to interfere with CR3. 81.1Smaxv 91.1Smaxv * Maybe we will want a way to return to userland when the guest TPR changes. 101.1Smaxv On Intel that's not complicated, but on old AMD CPUs, we need to disassemble 111.1Smaxv the instruction, and I don't like that. 121.1Smaxv 131.1Smaxv * Maybe we shouldn't modify the INT/NMI windows during event injection. The 141.1Smaxv virtualizer is supposed to inject the event only when these windows allow 151.1Smaxv it. (Eg Qemu does.) 161.1Smaxv 171.1Smaxv * We need a cleaner way to handle CPUID exits. It is not complicated to solve, 181.1Smaxv but I'm still not sure which design is the cleanest. 191.1Smaxv 201.1Smaxv * Same for the MSRs. 211.1Smaxv 221.1Smaxv====== LIBNVMM ====== 231.1Smaxv 241.1Smaxv * There are still a few twisted corner cases we don't handle in the instruction 251.1Smaxv emulator. For example if the guest makes an MMIO access relative to RSP, we 261.1Smaxv must base the GVA on %SS and not %DS. This is tiring, and in practice, no 271.1Smaxv guest is dumb enough to perform such accesses. 281.1Smaxv 29