elf32-msp430.c revision 1.5
1 /* MSP430-specific support for 32-bit ELF 2 Copyright (C) 2002-2016 Free Software Foundation, Inc. 3 Contributed by Dmitry Diky <diwil (at) mail.ru> 4 5 This file is part of BFD, the Binary File Descriptor library. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; if not, write to the Free Software 19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 20 MA 02110-1301, USA. */ 21 22 #include "sysdep.h" 23 #include "bfd.h" 24 #include "libiberty.h" 25 #include "libbfd.h" 26 #include "elf-bfd.h" 27 #include "elf/msp430.h" 28 29 static bfd_reloc_status_type 30 rl78_sym_diff_handler (bfd * abfd, 31 arelent * reloc, 32 asymbol * sym ATTRIBUTE_UNUSED, 33 void * addr ATTRIBUTE_UNUSED, 34 asection * input_sec, 35 bfd * out_bfd ATTRIBUTE_UNUSED, 36 char ** error_message ATTRIBUTE_UNUSED) 37 { 38 bfd_size_type octets; 39 octets = reloc->address * bfd_octets_per_byte (abfd); 40 41 /* Catch the case where bfd_install_relocation would return 42 bfd_reloc_outofrange because the SYM_DIFF reloc is being used in a very 43 small section. It does not actually matter if this happens because all 44 that SYM_DIFF does is compute a (4-byte) value. A second reloc then uses 45 this value, and it is that reloc that must fit into the section. 46 47 This happens in eg, gcc/testsuite/gcc.c-torture/compile/labels-3.c. */ 48 if ((octets + bfd_get_reloc_size (reloc->howto)) 49 > bfd_get_section_limit_octets (abfd, input_sec)) 50 return bfd_reloc_ok; 51 return bfd_reloc_continue; 52 } 53 54 static reloc_howto_type elf_msp430_howto_table[] = 55 { 56 HOWTO (R_MSP430_NONE, /* type */ 57 0, /* rightshift */ 58 3, /* size (0 = byte, 1 = short, 2 = long) */ 59 0, /* bitsize */ 60 FALSE, /* pc_relative */ 61 0, /* bitpos */ 62 complain_overflow_dont,/* complain_on_overflow */ 63 bfd_elf_generic_reloc, /* special_function */ 64 "R_MSP430_NONE", /* name */ 65 FALSE, /* partial_inplace */ 66 0, /* src_mask */ 67 0, /* dst_mask */ 68 FALSE), /* pcrel_offset */ 69 70 HOWTO (R_MSP430_32, /* type */ 71 0, /* rightshift */ 72 2, /* size (0 = byte, 1 = short, 2 = long) */ 73 32, /* bitsize */ 74 FALSE, /* pc_relative */ 75 0, /* bitpos */ 76 complain_overflow_bitfield,/* complain_on_overflow */ 77 bfd_elf_generic_reloc, /* special_function */ 78 "R_MSP430_32", /* name */ 79 FALSE, /* partial_inplace */ 80 0xffffffff, /* src_mask */ 81 0xffffffff, /* dst_mask */ 82 FALSE), /* pcrel_offset */ 83 84 /* A 10 bit PC relative relocation. */ 85 HOWTO (R_MSP430_10_PCREL, /* type */ 86 1, /* rightshift */ 87 1, /* size (0 = byte, 1 = short, 2 = long) */ 88 10, /* bitsize */ 89 TRUE, /* pc_relative */ 90 0, /* bitpos */ 91 complain_overflow_bitfield,/* complain_on_overflow */ 92 bfd_elf_generic_reloc, /* special_function */ 93 "R_MSP430_10_PCREL", /* name */ 94 FALSE, /* partial_inplace */ 95 0x3ff, /* src_mask */ 96 0x3ff, /* dst_mask */ 97 TRUE), /* pcrel_offset */ 98 99 /* A 16 bit absolute relocation. */ 100 HOWTO (R_MSP430_16, /* type */ 101 0, /* rightshift */ 102 1, /* size (0 = byte, 1 = short, 2 = long) */ 103 16, /* bitsize */ 104 FALSE, /* pc_relative */ 105 0, /* bitpos */ 106 complain_overflow_dont,/* complain_on_overflow */ 107 bfd_elf_generic_reloc, /* special_function */ 108 "R_MSP430_16", /* name */ 109 FALSE, /* partial_inplace */ 110 0, /* src_mask */ 111 0xffff, /* dst_mask */ 112 FALSE), /* pcrel_offset */ 113 114 /* A 16 bit PC relative relocation for command address. */ 115 HOWTO (R_MSP430_16_PCREL, /* type */ 116 1, /* rightshift */ 117 1, /* size (0 = byte, 1 = short, 2 = long) */ 118 16, /* bitsize */ 119 TRUE, /* pc_relative */ 120 0, /* bitpos */ 121 complain_overflow_dont,/* complain_on_overflow */ 122 bfd_elf_generic_reloc, /* special_function */ 123 "R_MSP430_16_PCREL", /* name */ 124 FALSE, /* partial_inplace */ 125 0, /* src_mask */ 126 0xffff, /* dst_mask */ 127 TRUE), /* pcrel_offset */ 128 129 /* A 16 bit absolute relocation, byte operations. */ 130 HOWTO (R_MSP430_16_BYTE, /* type */ 131 0, /* rightshift */ 132 1, /* size (0 = byte, 1 = short, 2 = long) */ 133 16, /* bitsize */ 134 FALSE, /* pc_relative */ 135 0, /* bitpos */ 136 complain_overflow_dont,/* complain_on_overflow */ 137 bfd_elf_generic_reloc, /* special_function */ 138 "R_MSP430_16_BYTE", /* name */ 139 FALSE, /* partial_inplace */ 140 0xffff, /* src_mask */ 141 0xffff, /* dst_mask */ 142 FALSE), /* pcrel_offset */ 143 144 /* A 16 bit absolute relocation for command address. */ 145 HOWTO (R_MSP430_16_PCREL_BYTE,/* type */ 146 1, /* rightshift */ 147 1, /* size (0 = byte, 1 = short, 2 = long) */ 148 16, /* bitsize */ 149 TRUE, /* pc_relative */ 150 0, /* bitpos */ 151 complain_overflow_dont,/* complain_on_overflow */ 152 bfd_elf_generic_reloc, /* special_function */ 153 "R_MSP430_16_PCREL_BYTE",/* name */ 154 FALSE, /* partial_inplace */ 155 0xffff, /* src_mask */ 156 0xffff, /* dst_mask */ 157 TRUE), /* pcrel_offset */ 158 159 /* A 10 bit PC relative relocation for complicated polymorphs. */ 160 HOWTO (R_MSP430_2X_PCREL, /* type */ 161 1, /* rightshift */ 162 2, /* size (0 = byte, 1 = short, 2 = long) */ 163 10, /* bitsize */ 164 TRUE, /* pc_relative */ 165 0, /* bitpos */ 166 complain_overflow_bitfield,/* complain_on_overflow */ 167 bfd_elf_generic_reloc, /* special_function */ 168 "R_MSP430_2X_PCREL", /* name */ 169 FALSE, /* partial_inplace */ 170 0x3ff, /* src_mask */ 171 0x3ff, /* dst_mask */ 172 TRUE), /* pcrel_offset */ 173 174 /* A 16 bit relaxable relocation for command address. */ 175 HOWTO (R_MSP430_RL_PCREL, /* type */ 176 1, /* rightshift */ 177 1, /* size (0 = byte, 1 = short, 2 = long) */ 178 16, /* bitsize */ 179 TRUE, /* pc_relative */ 180 0, /* bitpos */ 181 complain_overflow_dont,/* complain_on_overflow */ 182 bfd_elf_generic_reloc, /* special_function */ 183 "R_MSP430_RL_PCREL", /* name */ 184 FALSE, /* partial_inplace */ 185 0, /* src_mask */ 186 0xffff, /* dst_mask */ 187 TRUE) /* pcrel_offset */ 188 189 /* A 8-bit absolute relocation. */ 190 , HOWTO (R_MSP430_8, /* type */ 191 0, /* rightshift */ 192 0, /* size (0 = byte, 1 = short, 2 = long) */ 193 8, /* bitsize */ 194 FALSE, /* pc_relative */ 195 0, /* bitpos */ 196 complain_overflow_dont,/* complain_on_overflow */ 197 bfd_elf_generic_reloc, /* special_function */ 198 "R_MSP430_8", /* name */ 199 FALSE, /* partial_inplace */ 200 0, /* src_mask */ 201 0xffff, /* dst_mask */ 202 FALSE), /* pcrel_offset */ 203 204 /* Together with a following reloc, allows for the difference 205 between two symbols to be the real addend of the second reloc. */ 206 HOWTO (R_MSP430_SYM_DIFF, /* type */ 207 0, /* rightshift */ 208 2, /* size (0 = byte, 1 = short, 2 = long) */ 209 32, /* bitsize */ 210 FALSE, /* pc_relative */ 211 0, /* bitpos */ 212 complain_overflow_dont,/* complain_on_overflow */ 213 rl78_sym_diff_handler, /* special handler. */ 214 "R_MSP430_SYM_DIFF", /* name */ 215 FALSE, /* partial_inplace */ 216 0xffffffff, /* src_mask */ 217 0xffffffff, /* dst_mask */ 218 FALSE) /* pcrel_offset */ 219 }; 220 221 static reloc_howto_type elf_msp430x_howto_table[] = 222 { 223 HOWTO (R_MSP430_NONE, /* type */ 224 0, /* rightshift */ 225 3, /* size (0 = byte, 1 = short, 2 = long) */ 226 0, /* bitsize */ 227 FALSE, /* pc_relative */ 228 0, /* bitpos */ 229 complain_overflow_dont,/* complain_on_overflow */ 230 bfd_elf_generic_reloc, /* special_function */ 231 "R_MSP430_NONE", /* name */ 232 FALSE, /* partial_inplace */ 233 0, /* src_mask */ 234 0, /* dst_mask */ 235 FALSE), /* pcrel_offset */ 236 237 HOWTO (R_MSP430_ABS32, /* type */ 238 0, /* rightshift */ 239 2, /* size (0 = byte, 1 = short, 2 = long) */ 240 32, /* bitsize */ 241 FALSE, /* pc_relative */ 242 0, /* bitpos */ 243 complain_overflow_bitfield,/* complain_on_overflow */ 244 bfd_elf_generic_reloc, /* special_function */ 245 "R_MSP430_ABS32", /* name */ 246 FALSE, /* partial_inplace */ 247 0xffffffff, /* src_mask */ 248 0xffffffff, /* dst_mask */ 249 FALSE), /* pcrel_offset */ 250 251 HOWTO (R_MSP430_ABS16, /* type */ 252 0, /* rightshift */ 253 1, /* size (0 = byte, 1 = short, 2 = long) */ 254 16, /* bitsize */ 255 FALSE, /* pc_relative */ 256 0, /* bitpos */ 257 complain_overflow_dont,/* complain_on_overflow */ 258 bfd_elf_generic_reloc, /* special_function */ 259 "R_MSP430_ABS16", /* name */ 260 FALSE, /* partial_inplace */ 261 0, /* src_mask */ 262 0xffff, /* dst_mask */ 263 FALSE), /* pcrel_offset */ 264 265 HOWTO (R_MSP430_ABS8, /* type */ 266 0, /* rightshift */ 267 0, /* size (0 = byte, 1 = short, 2 = long) */ 268 8, /* bitsize */ 269 FALSE, /* pc_relative */ 270 0, /* bitpos */ 271 complain_overflow_bitfield,/* complain_on_overflow */ 272 bfd_elf_generic_reloc, /* special_function */ 273 "R_MSP430_ABS8", /* name */ 274 FALSE, /* partial_inplace */ 275 0xff, /* src_mask */ 276 0xff, /* dst_mask */ 277 FALSE), /* pcrel_offset */ 278 279 HOWTO (R_MSP430_PCR16, /* type */ 280 1, /* rightshift */ 281 1, /* size (0 = byte, 1 = short, 2 = long) */ 282 16, /* bitsize */ 283 TRUE, /* pc_relative */ 284 0, /* bitpos */ 285 complain_overflow_dont,/* complain_on_overflow */ 286 bfd_elf_generic_reloc, /* special_function */ 287 "R_MSP430_PCR16", /* name */ 288 FALSE, /* partial_inplace */ 289 0, /* src_mask */ 290 0xffff, /* dst_mask */ 291 TRUE), /* pcrel_offset */ 292 293 HOWTO (R_MSP430X_PCR20_EXT_SRC,/* type */ 294 0, /* rightshift */ 295 2, /* size (0 = byte, 1 = short, 2 = long) */ 296 32, /* bitsize */ 297 TRUE, /* pc_relative */ 298 0, /* bitpos */ 299 complain_overflow_dont,/* complain_on_overflow */ 300 bfd_elf_generic_reloc, /* special_function */ 301 "R_MSP430X_PCR20_EXT_SRC",/* name */ 302 FALSE, /* partial_inplace */ 303 0, /* src_mask */ 304 0xffff, /* dst_mask */ 305 TRUE), /* pcrel_offset */ 306 307 HOWTO (R_MSP430X_PCR20_EXT_DST,/* type */ 308 0, /* rightshift */ 309 2, /* size (0 = byte, 1 = short, 2 = long) */ 310 32, /* bitsize */ 311 TRUE, /* pc_relative */ 312 0, /* bitpos */ 313 complain_overflow_dont,/* complain_on_overflow */ 314 bfd_elf_generic_reloc, /* special_function */ 315 "R_MSP430X_PCR20_EXT_DST",/* name */ 316 FALSE, /* partial_inplace */ 317 0, /* src_mask */ 318 0xffff, /* dst_mask */ 319 TRUE), /* pcrel_offset */ 320 321 HOWTO (R_MSP430X_PCR20_EXT_ODST,/* type */ 322 0, /* rightshift */ 323 2, /* size (0 = byte, 1 = short, 2 = long) */ 324 32, /* bitsize */ 325 TRUE, /* pc_relative */ 326 0, /* bitpos */ 327 complain_overflow_dont,/* complain_on_overflow */ 328 bfd_elf_generic_reloc, /* special_function */ 329 "R_MSP430X_PCR20_EXT_ODST",/* name */ 330 FALSE, /* partial_inplace */ 331 0, /* src_mask */ 332 0xffff, /* dst_mask */ 333 TRUE), /* pcrel_offset */ 334 335 HOWTO (R_MSP430X_ABS20_EXT_SRC,/* type */ 336 0, /* rightshift */ 337 2, /* size (0 = byte, 1 = short, 2 = long) */ 338 32, /* bitsize */ 339 TRUE, /* pc_relative */ 340 0, /* bitpos */ 341 complain_overflow_dont,/* complain_on_overflow */ 342 bfd_elf_generic_reloc, /* special_function */ 343 "R_MSP430X_ABS20_EXT_SRC",/* name */ 344 FALSE, /* partial_inplace */ 345 0, /* src_mask */ 346 0xffff, /* dst_mask */ 347 TRUE), /* pcrel_offset */ 348 349 HOWTO (R_MSP430X_ABS20_EXT_DST,/* type */ 350 0, /* rightshift */ 351 2, /* size (0 = byte, 1 = short, 2 = long) */ 352 32, /* bitsize */ 353 TRUE, /* pc_relative */ 354 0, /* bitpos */ 355 complain_overflow_dont,/* complain_on_overflow */ 356 bfd_elf_generic_reloc, /* special_function */ 357 "R_MSP430X_ABS20_EXT_DST",/* name */ 358 FALSE, /* partial_inplace */ 359 0, /* src_mask */ 360 0xffff, /* dst_mask */ 361 TRUE), /* pcrel_offset */ 362 363 HOWTO (R_MSP430X_ABS20_EXT_ODST,/* type */ 364 0, /* rightshift */ 365 2, /* size (0 = byte, 1 = short, 2 = long) */ 366 32, /* bitsize */ 367 TRUE, /* pc_relative */ 368 0, /* bitpos */ 369 complain_overflow_dont,/* complain_on_overflow */ 370 bfd_elf_generic_reloc, /* special_function */ 371 "R_MSP430X_ABS20_EXT_ODST",/* name */ 372 FALSE, /* partial_inplace */ 373 0, /* src_mask */ 374 0xffff, /* dst_mask */ 375 TRUE), /* pcrel_offset */ 376 377 HOWTO (R_MSP430X_ABS20_ADR_SRC,/* type */ 378 0, /* rightshift */ 379 2, /* size (0 = byte, 1 = short, 2 = long) */ 380 32, /* bitsize */ 381 TRUE, /* pc_relative */ 382 0, /* bitpos */ 383 complain_overflow_dont,/* complain_on_overflow */ 384 bfd_elf_generic_reloc, /* special_function */ 385 "R_MSP430X_ABS20_ADR_SRC",/* name */ 386 FALSE, /* partial_inplace */ 387 0, /* src_mask */ 388 0xffff, /* dst_mask */ 389 TRUE), /* pcrel_offset */ 390 391 HOWTO (R_MSP430X_ABS20_ADR_DST,/* type */ 392 0, /* rightshift */ 393 2, /* size (0 = byte, 1 = short, 2 = long) */ 394 32, /* bitsize */ 395 TRUE, /* pc_relative */ 396 0, /* bitpos */ 397 complain_overflow_dont,/* complain_on_overflow */ 398 bfd_elf_generic_reloc, /* special_function */ 399 "R_MSP430X_ABS20_ADR_DST",/* name */ 400 FALSE, /* partial_inplace */ 401 0, /* src_mask */ 402 0xffff, /* dst_mask */ 403 TRUE), /* pcrel_offset */ 404 405 HOWTO (R_MSP430X_PCR16, /* type */ 406 0, /* rightshift */ 407 2, /* size (0 = byte, 1 = short, 2 = long) */ 408 32, /* bitsize */ 409 TRUE, /* pc_relative */ 410 0, /* bitpos */ 411 complain_overflow_dont,/* complain_on_overflow */ 412 bfd_elf_generic_reloc, /* special_function */ 413 "R_MSP430X_PCR16", /* name */ 414 FALSE, /* partial_inplace */ 415 0, /* src_mask */ 416 0xffff, /* dst_mask */ 417 TRUE), /* pcrel_offset */ 418 419 HOWTO (R_MSP430X_PCR20_CALL, /* type */ 420 0, /* rightshift */ 421 2, /* size (0 = byte, 1 = short, 2 = long) */ 422 32, /* bitsize */ 423 TRUE, /* pc_relative */ 424 0, /* bitpos */ 425 complain_overflow_dont,/* complain_on_overflow */ 426 bfd_elf_generic_reloc, /* special_function */ 427 "R_MSP430X_PCR20_CALL",/* name */ 428 FALSE, /* partial_inplace */ 429 0, /* src_mask */ 430 0xffff, /* dst_mask */ 431 TRUE), /* pcrel_offset */ 432 433 HOWTO (R_MSP430X_ABS16, /* type */ 434 0, /* rightshift */ 435 2, /* size (0 = byte, 1 = short, 2 = long) */ 436 32, /* bitsize */ 437 TRUE, /* pc_relative */ 438 0, /* bitpos */ 439 complain_overflow_dont,/* complain_on_overflow */ 440 bfd_elf_generic_reloc, /* special_function */ 441 "R_MSP430X_ABS16", /* name */ 442 FALSE, /* partial_inplace */ 443 0, /* src_mask */ 444 0xffff, /* dst_mask */ 445 TRUE), /* pcrel_offset */ 446 447 HOWTO (R_MSP430_ABS_HI16, /* type */ 448 0, /* rightshift */ 449 2, /* size (0 = byte, 1 = short, 2 = long) */ 450 32, /* bitsize */ 451 TRUE, /* pc_relative */ 452 0, /* bitpos */ 453 complain_overflow_dont,/* complain_on_overflow */ 454 bfd_elf_generic_reloc, /* special_function */ 455 "R_MSP430_ABS_HI16", /* name */ 456 FALSE, /* partial_inplace */ 457 0, /* src_mask */ 458 0xffff, /* dst_mask */ 459 TRUE), /* pcrel_offset */ 460 461 HOWTO (R_MSP430_PREL31, /* type */ 462 0, /* rightshift */ 463 2, /* size (0 = byte, 1 = short, 2 = long) */ 464 32, /* bitsize */ 465 TRUE, /* pc_relative */ 466 0, /* bitpos */ 467 complain_overflow_dont,/* complain_on_overflow */ 468 bfd_elf_generic_reloc, /* special_function */ 469 "R_MSP430_PREL31", /* name */ 470 FALSE, /* partial_inplace */ 471 0, /* src_mask */ 472 0xffff, /* dst_mask */ 473 TRUE), /* pcrel_offset */ 474 475 EMPTY_HOWTO (R_MSP430_EHTYPE), 476 477 /* A 10 bit PC relative relocation. */ 478 HOWTO (R_MSP430X_10_PCREL, /* type */ 479 1, /* rightshift */ 480 1, /* size (0 = byte, 1 = short, 2 = long) */ 481 10, /* bitsize */ 482 TRUE, /* pc_relative */ 483 0, /* bitpos */ 484 complain_overflow_bitfield,/* complain_on_overflow */ 485 bfd_elf_generic_reloc, /* special_function */ 486 "R_MSP430X_10_PCREL", /* name */ 487 FALSE, /* partial_inplace */ 488 0x3ff, /* src_mask */ 489 0x3ff, /* dst_mask */ 490 TRUE), /* pcrel_offset */ 491 492 /* A 10 bit PC relative relocation for complicated polymorphs. */ 493 HOWTO (R_MSP430X_2X_PCREL, /* type */ 494 1, /* rightshift */ 495 2, /* size (0 = byte, 1 = short, 2 = long) */ 496 10, /* bitsize */ 497 TRUE, /* pc_relative */ 498 0, /* bitpos */ 499 complain_overflow_bitfield,/* complain_on_overflow */ 500 bfd_elf_generic_reloc, /* special_function */ 501 "R_MSP430X_2X_PCREL", /* name */ 502 FALSE, /* partial_inplace */ 503 0x3ff, /* src_mask */ 504 0x3ff, /* dst_mask */ 505 TRUE), /* pcrel_offset */ 506 507 /* Together with a following reloc, allows for the difference 508 between two symbols to be the real addend of the second reloc. */ 509 HOWTO (R_MSP430X_SYM_DIFF, /* type */ 510 0, /* rightshift */ 511 2, /* size (0 = byte, 1 = short, 2 = long) */ 512 32, /* bitsize */ 513 FALSE, /* pc_relative */ 514 0, /* bitpos */ 515 complain_overflow_dont,/* complain_on_overflow */ 516 rl78_sym_diff_handler, /* special handler. */ 517 "R_MSP430X_SYM_DIFF", /* name */ 518 FALSE, /* partial_inplace */ 519 0xffffffff, /* src_mask */ 520 0xffffffff, /* dst_mask */ 521 FALSE) /* pcrel_offset */ 522 }; 523 524 /* Map BFD reloc types to MSP430 ELF reloc types. */ 525 526 struct msp430_reloc_map 527 { 528 bfd_reloc_code_real_type bfd_reloc_val; 529 unsigned int elf_reloc_val; 530 }; 531 532 static const struct msp430_reloc_map msp430_reloc_map[] = 533 { 534 {BFD_RELOC_NONE, R_MSP430_NONE}, 535 {BFD_RELOC_32, R_MSP430_32}, 536 {BFD_RELOC_MSP430_10_PCREL, R_MSP430_10_PCREL}, 537 {BFD_RELOC_16, R_MSP430_16_BYTE}, 538 {BFD_RELOC_MSP430_16_PCREL, R_MSP430_16_PCREL}, 539 {BFD_RELOC_MSP430_16, R_MSP430_16}, 540 {BFD_RELOC_MSP430_16_PCREL_BYTE, R_MSP430_16_PCREL_BYTE}, 541 {BFD_RELOC_MSP430_16_BYTE, R_MSP430_16_BYTE}, 542 {BFD_RELOC_MSP430_2X_PCREL, R_MSP430_2X_PCREL}, 543 {BFD_RELOC_MSP430_RL_PCREL, R_MSP430_RL_PCREL}, 544 {BFD_RELOC_8, R_MSP430_8}, 545 {BFD_RELOC_MSP430_SYM_DIFF, R_MSP430_SYM_DIFF} 546 }; 547 548 static const struct msp430_reloc_map msp430x_reloc_map[] = 549 { 550 {BFD_RELOC_NONE, R_MSP430_NONE}, 551 {BFD_RELOC_32, R_MSP430_ABS32}, 552 {BFD_RELOC_16, R_MSP430_ABS16}, 553 {BFD_RELOC_8, R_MSP430_ABS8}, 554 {BFD_RELOC_MSP430_ABS8, R_MSP430_ABS8}, 555 {BFD_RELOC_MSP430X_PCR20_EXT_SRC, R_MSP430X_PCR20_EXT_SRC}, 556 {BFD_RELOC_MSP430X_PCR20_EXT_DST, R_MSP430X_PCR20_EXT_DST}, 557 {BFD_RELOC_MSP430X_PCR20_EXT_ODST, R_MSP430X_PCR20_EXT_ODST}, 558 {BFD_RELOC_MSP430X_ABS20_EXT_SRC, R_MSP430X_ABS20_EXT_SRC}, 559 {BFD_RELOC_MSP430X_ABS20_EXT_DST, R_MSP430X_ABS20_EXT_DST}, 560 {BFD_RELOC_MSP430X_ABS20_EXT_ODST, R_MSP430X_ABS20_EXT_ODST}, 561 {BFD_RELOC_MSP430X_ABS20_ADR_SRC, R_MSP430X_ABS20_ADR_SRC}, 562 {BFD_RELOC_MSP430X_ABS20_ADR_DST, R_MSP430X_ABS20_ADR_DST}, 563 {BFD_RELOC_MSP430X_PCR16, R_MSP430X_PCR16}, 564 {BFD_RELOC_MSP430X_PCR20_CALL, R_MSP430X_PCR20_CALL}, 565 {BFD_RELOC_MSP430X_ABS16, R_MSP430X_ABS16}, 566 {BFD_RELOC_MSP430_ABS_HI16, R_MSP430_ABS_HI16}, 567 {BFD_RELOC_MSP430_PREL31, R_MSP430_PREL31}, 568 {BFD_RELOC_MSP430_10_PCREL, R_MSP430X_10_PCREL}, 569 {BFD_RELOC_MSP430_2X_PCREL, R_MSP430X_2X_PCREL}, 570 {BFD_RELOC_MSP430_RL_PCREL, R_MSP430X_PCR16}, 571 {BFD_RELOC_MSP430_SYM_DIFF, R_MSP430X_SYM_DIFF} 572 }; 573 574 static inline bfd_boolean 575 uses_msp430x_relocs (bfd * abfd) 576 { 577 extern const bfd_target msp430_elf32_ti_vec; 578 579 return bfd_get_mach (abfd) == bfd_mach_msp430x 580 || abfd->xvec == & msp430_elf32_ti_vec; 581 } 582 583 static reloc_howto_type * 584 bfd_elf32_bfd_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, 585 bfd_reloc_code_real_type code) 586 { 587 unsigned int i; 588 589 if (uses_msp430x_relocs (abfd)) 590 { 591 for (i = ARRAY_SIZE (msp430x_reloc_map); i--;) 592 if (msp430x_reloc_map[i].bfd_reloc_val == code) 593 return elf_msp430x_howto_table + msp430x_reloc_map[i].elf_reloc_val; 594 } 595 else 596 { 597 for (i = 0; i < ARRAY_SIZE (msp430_reloc_map); i++) 598 if (msp430_reloc_map[i].bfd_reloc_val == code) 599 return &elf_msp430_howto_table[msp430_reloc_map[i].elf_reloc_val]; 600 } 601 602 return NULL; 603 } 604 605 static reloc_howto_type * 606 bfd_elf32_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, 607 const char *r_name) 608 { 609 unsigned int i; 610 611 if (uses_msp430x_relocs (abfd)) 612 { 613 for (i = ARRAY_SIZE (elf_msp430x_howto_table); i--;) 614 if (elf_msp430x_howto_table[i].name != NULL 615 && strcasecmp (elf_msp430x_howto_table[i].name, r_name) == 0) 616 return elf_msp430x_howto_table + i; 617 } 618 else 619 { 620 for (i = 0; 621 i < (sizeof (elf_msp430_howto_table) 622 / sizeof (elf_msp430_howto_table[0])); 623 i++) 624 if (elf_msp430_howto_table[i].name != NULL 625 && strcasecmp (elf_msp430_howto_table[i].name, r_name) == 0) 626 return &elf_msp430_howto_table[i]; 627 } 628 629 return NULL; 630 } 631 632 /* Set the howto pointer for an MSP430 ELF reloc. */ 633 634 static void 635 msp430_info_to_howto_rela (bfd * abfd ATTRIBUTE_UNUSED, 636 arelent * cache_ptr, 637 Elf_Internal_Rela * dst) 638 { 639 unsigned int r_type; 640 641 r_type = ELF32_R_TYPE (dst->r_info); 642 643 if (uses_msp430x_relocs (abfd)) 644 { 645 if (r_type >= (unsigned int) R_MSP430x_max) 646 { 647 _bfd_error_handler (_("%B: invalid MSP430X reloc number: %d"), abfd, r_type); 648 r_type = 0; 649 } 650 cache_ptr->howto = elf_msp430x_howto_table + r_type; 651 return; 652 } 653 654 if (r_type >= (unsigned int) R_MSP430_max) 655 { 656 _bfd_error_handler (_("%B: invalid MSP430 reloc number: %d"), abfd, r_type); 657 r_type = 0; 658 } 659 cache_ptr->howto = &elf_msp430_howto_table[r_type]; 660 } 661 662 /* Look through the relocs for a section during the first phase. 663 Since we don't do .gots or .plts, we just need to consider the 664 virtual table relocs for gc. */ 665 666 static bfd_boolean 667 elf32_msp430_check_relocs (bfd * abfd, struct bfd_link_info * info, 668 asection * sec, const Elf_Internal_Rela * relocs) 669 { 670 Elf_Internal_Shdr *symtab_hdr; 671 struct elf_link_hash_entry **sym_hashes; 672 const Elf_Internal_Rela *rel; 673 const Elf_Internal_Rela *rel_end; 674 675 if (bfd_link_relocatable (info)) 676 return TRUE; 677 678 symtab_hdr = &elf_tdata (abfd)->symtab_hdr; 679 sym_hashes = elf_sym_hashes (abfd); 680 681 rel_end = relocs + sec->reloc_count; 682 for (rel = relocs; rel < rel_end; rel++) 683 { 684 struct elf_link_hash_entry *h; 685 unsigned long r_symndx; 686 687 r_symndx = ELF32_R_SYM (rel->r_info); 688 if (r_symndx < symtab_hdr->sh_info) 689 h = NULL; 690 else 691 { 692 h = sym_hashes[r_symndx - symtab_hdr->sh_info]; 693 while (h->root.type == bfd_link_hash_indirect 694 || h->root.type == bfd_link_hash_warning) 695 h = (struct elf_link_hash_entry *) h->root.u.i.link; 696 697 /* PR15323, ref flags aren't set for references in the same 698 object. */ 699 h->root.non_ir_ref = 1; 700 } 701 } 702 703 return TRUE; 704 } 705 706 /* Perform a single relocation. By default we use the standard BFD 707 routines, but a few relocs, we have to do them ourselves. */ 708 709 static bfd_reloc_status_type 710 msp430_final_link_relocate (reloc_howto_type * howto, 711 bfd * input_bfd, 712 asection * input_section, 713 bfd_byte * contents, 714 Elf_Internal_Rela * rel, 715 bfd_vma relocation, 716 struct bfd_link_info * info) 717 { 718 static asection * sym_diff_section; 719 static bfd_vma sym_diff_value; 720 721 struct bfd_elf_section_data * esd = elf_section_data (input_section); 722 bfd_reloc_status_type r = bfd_reloc_ok; 723 bfd_vma x; 724 bfd_signed_vma srel; 725 bfd_boolean is_rel_reloc = FALSE; 726 727 if (uses_msp430x_relocs (input_bfd)) 728 { 729 /* See if we have a REL type relocation. */ 730 is_rel_reloc = (esd->rel.hdr != NULL); 731 /* Sanity check - only one type of relocation per section. 732 FIXME: Theoretically it is possible to have both types, 733 but if that happens how can we distinguish between the two ? */ 734 BFD_ASSERT (! is_rel_reloc || ! esd->rela.hdr); 735 /* If we are using a REL relocation then the addend should be empty. */ 736 BFD_ASSERT (! is_rel_reloc || rel->r_addend == 0); 737 } 738 739 if (sym_diff_section != NULL) 740 { 741 BFD_ASSERT (sym_diff_section == input_section); 742 743 if (uses_msp430x_relocs (input_bfd)) 744 switch (howto->type) 745 { 746 case R_MSP430_ABS32: 747 /* If we are computing a 32-bit value for the location lists 748 and the result is 0 then we add one to the value. A zero 749 value can result because of linker relaxation deleteing 750 prologue instructions and using a value of 1 (for the begin 751 and end offsets in the location list entry) results in a 752 nul entry which does not prevent the following entries from 753 being parsed. */ 754 if (relocation == sym_diff_value 755 && strcmp (input_section->name, ".debug_loc") == 0) 756 ++ relocation; 757 /* Fall through. */ 758 case R_MSP430_ABS16: 759 case R_MSP430X_ABS16: 760 case R_MSP430_ABS8: 761 BFD_ASSERT (! is_rel_reloc); 762 relocation -= sym_diff_value; 763 break; 764 765 default: 766 return bfd_reloc_dangerous; 767 } 768 else 769 switch (howto->type) 770 { 771 case R_MSP430_32: 772 case R_MSP430_16: 773 case R_MSP430_16_BYTE: 774 case R_MSP430_8: 775 relocation -= sym_diff_value; 776 break; 777 778 default: 779 return bfd_reloc_dangerous; 780 } 781 782 sym_diff_section = NULL; 783 } 784 785 if (uses_msp430x_relocs (input_bfd)) 786 switch (howto->type) 787 { 788 case R_MSP430X_SYM_DIFF: 789 /* Cache the input section and value. 790 The offset is unreliable, since relaxation may 791 have reduced the following reloc's offset. */ 792 BFD_ASSERT (! is_rel_reloc); 793 sym_diff_section = input_section; 794 sym_diff_value = relocation; 795 return bfd_reloc_ok; 796 797 case R_MSP430_ABS16: 798 contents += rel->r_offset; 799 srel = (bfd_signed_vma) relocation; 800 if (is_rel_reloc) 801 srel += bfd_get_16 (input_bfd, contents); 802 else 803 srel += rel->r_addend; 804 bfd_put_16 (input_bfd, srel & 0xffff, contents); 805 break; 806 807 case R_MSP430X_10_PCREL: 808 contents += rel->r_offset; 809 srel = (bfd_signed_vma) relocation; 810 if (is_rel_reloc) 811 srel += bfd_get_16 (input_bfd, contents) & 0x3ff; 812 else 813 srel += rel->r_addend; 814 srel -= rel->r_offset; 815 srel -= 2; /* Branch instructions add 2 to the PC... */ 816 srel -= (input_section->output_section->vma + 817 input_section->output_offset); 818 if (srel & 1) 819 return bfd_reloc_outofrange; 820 821 /* MSP430 addresses commands as words. */ 822 srel >>= 1; 823 824 /* Check for an overflow. */ 825 if (srel < -512 || srel > 511) 826 { 827 if (info->disable_target_specific_optimizations < 0) 828 { 829 static bfd_boolean warned = FALSE; 830 if (! warned) 831 { 832 info->callbacks->warning 833 (info, 834 _("Try enabling relaxation to avoid relocation truncations"), 835 NULL, input_bfd, input_section, relocation); 836 warned = TRUE; 837 } 838 } 839 return bfd_reloc_overflow; 840 } 841 842 x = bfd_get_16 (input_bfd, contents); 843 x = (x & 0xfc00) | (srel & 0x3ff); 844 bfd_put_16 (input_bfd, x, contents); 845 break; 846 847 case R_MSP430X_PCR20_EXT_ODST: 848 /* [0,4]+[48,16] = ---F ---- ---- FFFF */ 849 contents += rel->r_offset; 850 srel = (bfd_signed_vma) relocation; 851 if (is_rel_reloc) 852 { 853 bfd_vma addend; 854 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16; 855 addend |= bfd_get_16 (input_bfd, contents + 6); 856 srel += addend; 857 858 } 859 else 860 srel += rel->r_addend; 861 srel -= rel->r_offset; 862 srel -= (input_section->output_section->vma + 863 input_section->output_offset); 864 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 6); 865 x = bfd_get_16 (input_bfd, contents); 866 x = (x & 0xfff0) | ((srel >> 16) & 0xf); 867 bfd_put_16 (input_bfd, x, contents); 868 break; 869 870 case R_MSP430X_ABS20_EXT_SRC: 871 /* [7,4]+[32,16] = -78- ---- FFFF */ 872 contents += rel->r_offset; 873 srel = (bfd_signed_vma) relocation; 874 if (is_rel_reloc) 875 { 876 bfd_vma addend; 877 addend = (bfd_get_16 (input_bfd, contents) & 0x0780) << 9; 878 addend |= bfd_get_16 (input_bfd, contents + 4); 879 srel += addend; 880 } 881 else 882 srel += rel->r_addend; 883 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4); 884 srel >>= 16; 885 x = bfd_get_16 (input_bfd, contents); 886 x = (x & 0xf87f) | ((srel << 7) & 0x0780); 887 bfd_put_16 (input_bfd, x, contents); 888 break; 889 890 case R_MSP430_16_PCREL: 891 contents += rel->r_offset; 892 srel = (bfd_signed_vma) relocation; 893 if (is_rel_reloc) 894 srel += bfd_get_16 (input_bfd, contents); 895 else 896 srel += rel->r_addend; 897 srel -= rel->r_offset; 898 /* Only branch instructions add 2 to the PC... */ 899 srel -= (input_section->output_section->vma + 900 input_section->output_offset); 901 if (srel & 1) 902 return bfd_reloc_outofrange; 903 bfd_put_16 (input_bfd, srel & 0xffff, contents); 904 break; 905 906 case R_MSP430X_PCR20_EXT_DST: 907 /* [0,4]+[32,16] = ---F ---- FFFF */ 908 contents += rel->r_offset; 909 srel = (bfd_signed_vma) relocation; 910 if (is_rel_reloc) 911 { 912 bfd_vma addend; 913 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16; 914 addend |= bfd_get_16 (input_bfd, contents + 4); 915 srel += addend; 916 } 917 else 918 srel += rel->r_addend; 919 srel -= rel->r_offset; 920 srel -= (input_section->output_section->vma + 921 input_section->output_offset); 922 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4); 923 srel >>= 16; 924 x = bfd_get_16 (input_bfd, contents); 925 x = (x & 0xfff0) | (srel & 0xf); 926 bfd_put_16 (input_bfd, x, contents); 927 break; 928 929 case R_MSP430X_PCR20_EXT_SRC: 930 /* [7,4]+[32,16] = -78- ---- FFFF */ 931 contents += rel->r_offset; 932 srel = (bfd_signed_vma) relocation; 933 if (is_rel_reloc) 934 { 935 bfd_vma addend; 936 addend = ((bfd_get_16 (input_bfd, contents) & 0x0780) << 9); 937 addend |= bfd_get_16 (input_bfd, contents + 4); 938 srel += addend;; 939 } 940 else 941 srel += rel->r_addend; 942 srel -= rel->r_offset; 943 /* Only branch instructions add 2 to the PC... */ 944 srel -= (input_section->output_section->vma + 945 input_section->output_offset); 946 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4); 947 srel >>= 16; 948 x = bfd_get_16 (input_bfd, contents); 949 x = (x & 0xf87f) | ((srel << 7) & 0x0780); 950 bfd_put_16 (input_bfd, x, contents); 951 break; 952 953 case R_MSP430_ABS8: 954 contents += rel->r_offset; 955 srel = (bfd_signed_vma) relocation; 956 if (is_rel_reloc) 957 srel += bfd_get_8 (input_bfd, contents); 958 else 959 srel += rel->r_addend; 960 bfd_put_8 (input_bfd, srel & 0xff, contents); 961 break; 962 963 case R_MSP430X_ABS20_EXT_DST: 964 /* [0,4]+[32,16] = ---F ---- FFFF */ 965 contents += rel->r_offset; 966 srel = (bfd_signed_vma) relocation; 967 if (is_rel_reloc) 968 { 969 bfd_vma addend; 970 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16; 971 addend |= bfd_get_16 (input_bfd, contents + 4); 972 srel += addend; 973 } 974 else 975 srel += rel->r_addend; 976 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4); 977 srel >>= 16; 978 x = bfd_get_16 (input_bfd, contents); 979 x = (x & 0xfff0) | (srel & 0xf); 980 bfd_put_16 (input_bfd, x, contents); 981 break; 982 983 case R_MSP430X_ABS20_EXT_ODST: 984 /* [0,4]+[48,16] = ---F ---- ---- FFFF */ 985 contents += rel->r_offset; 986 srel = (bfd_signed_vma) relocation; 987 if (is_rel_reloc) 988 { 989 bfd_vma addend; 990 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16; 991 addend |= bfd_get_16 (input_bfd, contents + 6); 992 srel += addend; 993 } 994 else 995 srel += rel->r_addend; 996 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 6); 997 srel >>= 16; 998 x = bfd_get_16 (input_bfd, contents); 999 x = (x & 0xfff0) | (srel & 0xf); 1000 bfd_put_16 (input_bfd, x, contents); 1001 break; 1002 1003 case R_MSP430X_ABS20_ADR_SRC: 1004 /* [8,4]+[16,16] = -F-- FFFF */ 1005 contents += rel->r_offset; 1006 srel = (bfd_signed_vma) relocation; 1007 if (is_rel_reloc) 1008 { 1009 bfd_vma addend; 1010 1011 addend = ((bfd_get_16 (input_bfd, contents) & 0xf00) << 8); 1012 addend |= bfd_get_16 (input_bfd, contents + 2); 1013 srel += addend; 1014 } 1015 else 1016 srel += rel->r_addend; 1017 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 2); 1018 srel >>= 16; 1019 x = bfd_get_16 (input_bfd, contents); 1020 x = (x & 0xf0ff) | ((srel << 8) & 0x0f00); 1021 bfd_put_16 (input_bfd, x, contents); 1022 break; 1023 1024 case R_MSP430X_ABS20_ADR_DST: 1025 /* [0,4]+[16,16] = ---F FFFF */ 1026 contents += rel->r_offset; 1027 srel = (bfd_signed_vma) relocation; 1028 if (is_rel_reloc) 1029 { 1030 bfd_vma addend; 1031 addend = ((bfd_get_16 (input_bfd, contents) & 0xf) << 16); 1032 addend |= bfd_get_16 (input_bfd, contents + 2); 1033 srel += addend; 1034 } 1035 else 1036 srel += rel->r_addend; 1037 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 2); 1038 srel >>= 16; 1039 x = bfd_get_16 (input_bfd, contents); 1040 x = (x & 0xfff0) | (srel & 0xf); 1041 bfd_put_16 (input_bfd, x, contents); 1042 break; 1043 1044 case R_MSP430X_ABS16: 1045 contents += rel->r_offset; 1046 srel = (bfd_signed_vma) relocation; 1047 if (is_rel_reloc) 1048 srel += bfd_get_16 (input_bfd, contents); 1049 else 1050 srel += rel->r_addend; 1051 x = srel; 1052 if (x > 0xffff) 1053 return bfd_reloc_overflow; 1054 bfd_put_16 (input_bfd, srel & 0xffff, contents); 1055 break; 1056 1057 case R_MSP430_ABS_HI16: 1058 /* The EABI specifies that this must be a RELA reloc. */ 1059 BFD_ASSERT (! is_rel_reloc); 1060 contents += rel->r_offset; 1061 srel = (bfd_signed_vma) relocation; 1062 srel += rel->r_addend; 1063 bfd_put_16 (input_bfd, (srel >> 16) & 0xffff, contents); 1064 break; 1065 1066 case R_MSP430X_PCR20_CALL: 1067 /* [0,4]+[16,16] = ---F FFFF*/ 1068 contents += rel->r_offset; 1069 srel = (bfd_signed_vma) relocation; 1070 if (is_rel_reloc) 1071 { 1072 bfd_vma addend; 1073 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16; 1074 addend |= bfd_get_16 (input_bfd, contents + 2); 1075 srel += addend; 1076 } 1077 else 1078 srel += rel->r_addend; 1079 srel -= rel->r_offset; 1080 srel -= (input_section->output_section->vma + 1081 input_section->output_offset); 1082 bfd_put_16 (input_bfd, srel & 0xffff, contents + 2); 1083 srel >>= 16; 1084 x = bfd_get_16 (input_bfd, contents); 1085 x = (x & 0xfff0) | (srel & 0xf); 1086 bfd_put_16 (input_bfd, x, contents); 1087 break; 1088 1089 case R_MSP430X_PCR16: 1090 contents += rel->r_offset; 1091 srel = (bfd_signed_vma) relocation; 1092 if (is_rel_reloc) 1093 srel += bfd_get_16 (input_bfd, contents); 1094 else 1095 srel += rel->r_addend; 1096 srel -= rel->r_offset; 1097 srel -= (input_section->output_section->vma + 1098 input_section->output_offset); 1099 bfd_put_16 (input_bfd, srel & 0xffff, contents); 1100 break; 1101 1102 case R_MSP430_PREL31: 1103 contents += rel->r_offset; 1104 srel = (bfd_signed_vma) relocation; 1105 if (is_rel_reloc) 1106 srel += (bfd_get_32 (input_bfd, contents) & 0x7fffffff); 1107 else 1108 srel += rel->r_addend; 1109 srel += rel->r_addend; 1110 x = bfd_get_32 (input_bfd, contents); 1111 x = (x & 0x80000000) | ((srel >> 31) & 0x7fffffff); 1112 bfd_put_32 (input_bfd, x, contents); 1113 break; 1114 1115 default: 1116 r = _bfd_final_link_relocate (howto, input_bfd, input_section, 1117 contents, rel->r_offset, 1118 relocation, rel->r_addend); 1119 } 1120 else 1121 switch (howto->type) 1122 { 1123 case R_MSP430_10_PCREL: 1124 contents += rel->r_offset; 1125 srel = (bfd_signed_vma) relocation; 1126 srel += rel->r_addend; 1127 srel -= rel->r_offset; 1128 srel -= 2; /* Branch instructions add 2 to the PC... */ 1129 srel -= (input_section->output_section->vma + 1130 input_section->output_offset); 1131 1132 if (srel & 1) 1133 return bfd_reloc_outofrange; 1134 1135 /* MSP430 addresses commands as words. */ 1136 srel >>= 1; 1137 1138 /* Check for an overflow. */ 1139 if (srel < -512 || srel > 511) 1140 { 1141 if (info->disable_target_specific_optimizations < 0) 1142 { 1143 static bfd_boolean warned = FALSE; 1144 if (! warned) 1145 { 1146 info->callbacks->warning 1147 (info, 1148 _("Try enabling relaxation to avoid relocation truncations"), 1149 NULL, input_bfd, input_section, relocation); 1150 warned = TRUE; 1151 } 1152 } 1153 return bfd_reloc_overflow; 1154 } 1155 1156 x = bfd_get_16 (input_bfd, contents); 1157 x = (x & 0xfc00) | (srel & 0x3ff); 1158 bfd_put_16 (input_bfd, x, contents); 1159 break; 1160 1161 case R_MSP430_2X_PCREL: 1162 contents += rel->r_offset; 1163 srel = (bfd_signed_vma) relocation; 1164 srel += rel->r_addend; 1165 srel -= rel->r_offset; 1166 srel -= 2; /* Branch instructions add 2 to the PC... */ 1167 srel -= (input_section->output_section->vma + 1168 input_section->output_offset); 1169 1170 if (srel & 1) 1171 return bfd_reloc_outofrange; 1172 1173 /* MSP430 addresses commands as words. */ 1174 srel >>= 1; 1175 1176 /* Check for an overflow. */ 1177 if (srel < -512 || srel > 511) 1178 return bfd_reloc_overflow; 1179 1180 x = bfd_get_16 (input_bfd, contents); 1181 x = (x & 0xfc00) | (srel & 0x3ff); 1182 bfd_put_16 (input_bfd, x, contents); 1183 /* Handle second jump instruction. */ 1184 x = bfd_get_16 (input_bfd, contents - 2); 1185 srel += 1; 1186 x = (x & 0xfc00) | (srel & 0x3ff); 1187 bfd_put_16 (input_bfd, x, contents - 2); 1188 break; 1189 1190 case R_MSP430_RL_PCREL: 1191 case R_MSP430_16_PCREL: 1192 contents += rel->r_offset; 1193 srel = (bfd_signed_vma) relocation; 1194 srel += rel->r_addend; 1195 srel -= rel->r_offset; 1196 /* Only branch instructions add 2 to the PC... */ 1197 srel -= (input_section->output_section->vma + 1198 input_section->output_offset); 1199 1200 if (srel & 1) 1201 return bfd_reloc_outofrange; 1202 1203 bfd_put_16 (input_bfd, srel & 0xffff, contents); 1204 break; 1205 1206 case R_MSP430_16_PCREL_BYTE: 1207 contents += rel->r_offset; 1208 srel = (bfd_signed_vma) relocation; 1209 srel += rel->r_addend; 1210 srel -= rel->r_offset; 1211 /* Only branch instructions add 2 to the PC... */ 1212 srel -= (input_section->output_section->vma + 1213 input_section->output_offset); 1214 1215 bfd_put_16 (input_bfd, srel & 0xffff, contents); 1216 break; 1217 1218 case R_MSP430_16_BYTE: 1219 contents += rel->r_offset; 1220 srel = (bfd_signed_vma) relocation; 1221 srel += rel->r_addend; 1222 bfd_put_16 (input_bfd, srel & 0xffff, contents); 1223 break; 1224 1225 case R_MSP430_16: 1226 contents += rel->r_offset; 1227 srel = (bfd_signed_vma) relocation; 1228 srel += rel->r_addend; 1229 1230 if (srel & 1) 1231 return bfd_reloc_notsupported; 1232 1233 bfd_put_16 (input_bfd, srel & 0xffff, contents); 1234 break; 1235 1236 case R_MSP430_8: 1237 contents += rel->r_offset; 1238 srel = (bfd_signed_vma) relocation; 1239 srel += rel->r_addend; 1240 1241 bfd_put_8 (input_bfd, srel & 0xff, contents); 1242 break; 1243 1244 case R_MSP430_SYM_DIFF: 1245 /* Cache the input section and value. 1246 The offset is unreliable, since relaxation may 1247 have reduced the following reloc's offset. */ 1248 sym_diff_section = input_section; 1249 sym_diff_value = relocation; 1250 return bfd_reloc_ok; 1251 1252 default: 1253 r = _bfd_final_link_relocate (howto, input_bfd, input_section, 1254 contents, rel->r_offset, 1255 relocation, rel->r_addend); 1256 } 1257 1258 return r; 1259 } 1260 1261 /* Relocate an MSP430 ELF section. */ 1262 1263 static bfd_boolean 1264 elf32_msp430_relocate_section (bfd * output_bfd ATTRIBUTE_UNUSED, 1265 struct bfd_link_info * info, 1266 bfd * input_bfd, 1267 asection * input_section, 1268 bfd_byte * contents, 1269 Elf_Internal_Rela * relocs, 1270 Elf_Internal_Sym * local_syms, 1271 asection ** local_sections) 1272 { 1273 Elf_Internal_Shdr *symtab_hdr; 1274 struct elf_link_hash_entry **sym_hashes; 1275 Elf_Internal_Rela *rel; 1276 Elf_Internal_Rela *relend; 1277 1278 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr; 1279 sym_hashes = elf_sym_hashes (input_bfd); 1280 relend = relocs + input_section->reloc_count; 1281 1282 for (rel = relocs; rel < relend; rel++) 1283 { 1284 reloc_howto_type *howto; 1285 unsigned long r_symndx; 1286 Elf_Internal_Sym *sym; 1287 asection *sec; 1288 struct elf_link_hash_entry *h; 1289 bfd_vma relocation; 1290 bfd_reloc_status_type r; 1291 const char *name = NULL; 1292 int r_type; 1293 1294 r_type = ELF32_R_TYPE (rel->r_info); 1295 r_symndx = ELF32_R_SYM (rel->r_info); 1296 1297 if (uses_msp430x_relocs (input_bfd)) 1298 howto = elf_msp430x_howto_table + r_type; 1299 else 1300 howto = elf_msp430_howto_table + r_type; 1301 1302 h = NULL; 1303 sym = NULL; 1304 sec = NULL; 1305 1306 if (r_symndx < symtab_hdr->sh_info) 1307 { 1308 sym = local_syms + r_symndx; 1309 sec = local_sections[r_symndx]; 1310 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel); 1311 1312 name = bfd_elf_string_from_elf_section 1313 (input_bfd, symtab_hdr->sh_link, sym->st_name); 1314 name = (name == NULL || * name == 0) ? bfd_section_name (input_bfd, sec) : name; 1315 } 1316 else 1317 { 1318 bfd_boolean unresolved_reloc, warned, ignored; 1319 1320 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, 1321 r_symndx, symtab_hdr, sym_hashes, 1322 h, sec, relocation, 1323 unresolved_reloc, warned, ignored); 1324 name = h->root.root.string; 1325 } 1326 1327 if (sec != NULL && discarded_section (sec)) 1328 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section, 1329 rel, 1, relend, howto, 0, contents); 1330 1331 if (bfd_link_relocatable (info)) 1332 continue; 1333 1334 r = msp430_final_link_relocate (howto, input_bfd, input_section, 1335 contents, rel, relocation, info); 1336 1337 if (r != bfd_reloc_ok) 1338 { 1339 const char *msg = (const char *) NULL; 1340 1341 switch (r) 1342 { 1343 case bfd_reloc_overflow: 1344 (*info->callbacks->reloc_overflow) 1345 (info, (h ? &h->root : NULL), name, howto->name, 1346 (bfd_vma) 0, input_bfd, input_section, rel->r_offset); 1347 break; 1348 1349 case bfd_reloc_undefined: 1350 (*info->callbacks->undefined_symbol) 1351 (info, name, input_bfd, input_section, rel->r_offset, TRUE); 1352 break; 1353 1354 case bfd_reloc_outofrange: 1355 msg = _("internal error: branch/jump to an odd address detected"); 1356 break; 1357 1358 case bfd_reloc_notsupported: 1359 msg = _("internal error: unsupported relocation error"); 1360 break; 1361 1362 case bfd_reloc_dangerous: 1363 msg = _("internal error: dangerous relocation"); 1364 break; 1365 1366 default: 1367 msg = _("internal error: unknown error"); 1368 break; 1369 } 1370 1371 if (msg) 1372 (*info->callbacks->warning) (info, msg, name, input_bfd, 1373 input_section, rel->r_offset); 1374 } 1375 1376 } 1377 1378 return TRUE; 1379 } 1380 1381 /* The final processing done just before writing out a MSP430 ELF object 1382 file. This gets the MSP430 architecture right based on the machine 1383 number. */ 1384 1385 static void 1386 bfd_elf_msp430_final_write_processing (bfd * abfd, 1387 bfd_boolean linker ATTRIBUTE_UNUSED) 1388 { 1389 unsigned long val; 1390 1391 switch (bfd_get_mach (abfd)) 1392 { 1393 default: 1394 case bfd_mach_msp110: val = E_MSP430_MACH_MSP430x11x1; break; 1395 case bfd_mach_msp11: val = E_MSP430_MACH_MSP430x11; break; 1396 case bfd_mach_msp12: val = E_MSP430_MACH_MSP430x12; break; 1397 case bfd_mach_msp13: val = E_MSP430_MACH_MSP430x13; break; 1398 case bfd_mach_msp14: val = E_MSP430_MACH_MSP430x14; break; 1399 case bfd_mach_msp15: val = E_MSP430_MACH_MSP430x15; break; 1400 case bfd_mach_msp16: val = E_MSP430_MACH_MSP430x16; break; 1401 case bfd_mach_msp31: val = E_MSP430_MACH_MSP430x31; break; 1402 case bfd_mach_msp32: val = E_MSP430_MACH_MSP430x32; break; 1403 case bfd_mach_msp33: val = E_MSP430_MACH_MSP430x33; break; 1404 case bfd_mach_msp41: val = E_MSP430_MACH_MSP430x41; break; 1405 case bfd_mach_msp42: val = E_MSP430_MACH_MSP430x42; break; 1406 case bfd_mach_msp43: val = E_MSP430_MACH_MSP430x43; break; 1407 case bfd_mach_msp44: val = E_MSP430_MACH_MSP430x44; break; 1408 case bfd_mach_msp20: val = E_MSP430_MACH_MSP430x20; break; 1409 case bfd_mach_msp22: val = E_MSP430_MACH_MSP430x22; break; 1410 case bfd_mach_msp23: val = E_MSP430_MACH_MSP430x23; break; 1411 case bfd_mach_msp24: val = E_MSP430_MACH_MSP430x24; break; 1412 case bfd_mach_msp26: val = E_MSP430_MACH_MSP430x26; break; 1413 case bfd_mach_msp46: val = E_MSP430_MACH_MSP430x46; break; 1414 case bfd_mach_msp47: val = E_MSP430_MACH_MSP430x47; break; 1415 case bfd_mach_msp54: val = E_MSP430_MACH_MSP430x54; break; 1416 case bfd_mach_msp430x: val = E_MSP430_MACH_MSP430X; break; 1417 } 1418 1419 elf_elfheader (abfd)->e_machine = EM_MSP430; 1420 elf_elfheader (abfd)->e_flags &= ~EF_MSP430_MACH; 1421 elf_elfheader (abfd)->e_flags |= val; 1422 } 1423 1424 /* Set the right machine number. */ 1425 1426 static bfd_boolean 1427 elf32_msp430_object_p (bfd * abfd) 1428 { 1429 int e_set = bfd_mach_msp14; 1430 1431 if (elf_elfheader (abfd)->e_machine == EM_MSP430 1432 || elf_elfheader (abfd)->e_machine == EM_MSP430_OLD) 1433 { 1434 int e_mach = elf_elfheader (abfd)->e_flags & EF_MSP430_MACH; 1435 1436 switch (e_mach) 1437 { 1438 default: 1439 case E_MSP430_MACH_MSP430x11: e_set = bfd_mach_msp11; break; 1440 case E_MSP430_MACH_MSP430x11x1: e_set = bfd_mach_msp110; break; 1441 case E_MSP430_MACH_MSP430x12: e_set = bfd_mach_msp12; break; 1442 case E_MSP430_MACH_MSP430x13: e_set = bfd_mach_msp13; break; 1443 case E_MSP430_MACH_MSP430x14: e_set = bfd_mach_msp14; break; 1444 case E_MSP430_MACH_MSP430x15: e_set = bfd_mach_msp15; break; 1445 case E_MSP430_MACH_MSP430x16: e_set = bfd_mach_msp16; break; 1446 case E_MSP430_MACH_MSP430x31: e_set = bfd_mach_msp31; break; 1447 case E_MSP430_MACH_MSP430x32: e_set = bfd_mach_msp32; break; 1448 case E_MSP430_MACH_MSP430x33: e_set = bfd_mach_msp33; break; 1449 case E_MSP430_MACH_MSP430x41: e_set = bfd_mach_msp41; break; 1450 case E_MSP430_MACH_MSP430x42: e_set = bfd_mach_msp42; break; 1451 case E_MSP430_MACH_MSP430x43: e_set = bfd_mach_msp43; break; 1452 case E_MSP430_MACH_MSP430x44: e_set = bfd_mach_msp44; break; 1453 case E_MSP430_MACH_MSP430x20: e_set = bfd_mach_msp20; break; 1454 case E_MSP430_MACH_MSP430x22: e_set = bfd_mach_msp22; break; 1455 case E_MSP430_MACH_MSP430x23: e_set = bfd_mach_msp23; break; 1456 case E_MSP430_MACH_MSP430x24: e_set = bfd_mach_msp24; break; 1457 case E_MSP430_MACH_MSP430x26: e_set = bfd_mach_msp26; break; 1458 case E_MSP430_MACH_MSP430x46: e_set = bfd_mach_msp46; break; 1459 case E_MSP430_MACH_MSP430x47: e_set = bfd_mach_msp47; break; 1460 case E_MSP430_MACH_MSP430x54: e_set = bfd_mach_msp54; break; 1461 case E_MSP430_MACH_MSP430X: e_set = bfd_mach_msp430x; break; 1462 } 1463 } 1464 1465 return bfd_default_set_arch_mach (abfd, bfd_arch_msp430, e_set); 1466 } 1467 1468 /* These functions handle relaxing for the msp430. 1469 Relaxation required only in two cases: 1470 - Bad hand coding like jumps from one section to another or 1471 from file to file. 1472 - Sibling calls. This will affect only 'jump label' polymorph. Without 1473 relaxing this enlarges code by 2 bytes. Sibcalls implemented but 1474 do not work in gcc's port by the reason I do not know. 1475 - To convert out of range conditional jump instructions (found inside 1476 a function) into inverted jumps over an unconditional branch instruction. 1477 Anyway, if a relaxation required, user should pass -relax option to the 1478 linker. 1479 1480 There are quite a few relaxing opportunities available on the msp430: 1481 1482 ================================================================ 1483 1484 1. 3 words -> 1 word 1485 1486 eq == jeq label jne +4; br lab 1487 ne != jne label jeq +4; br lab 1488 lt < jl label jge +4; br lab 1489 ltu < jlo label lhs +4; br lab 1490 ge >= jge label jl +4; br lab 1491 geu >= jhs label jlo +4; br lab 1492 1493 2. 4 words -> 1 word 1494 1495 ltn < jn jn +2; jmp +4; br lab 1496 1497 3. 4 words -> 2 words 1498 1499 gt > jeq +2; jge label jeq +6; jl +4; br label 1500 gtu > jeq +2; jhs label jeq +6; jlo +4; br label 1501 1502 4. 4 words -> 2 words and 2 labels 1503 1504 leu <= jeq label; jlo label jeq +2; jhs +4; br label 1505 le <= jeq label; jl label jeq +2; jge +4; br label 1506 ================================================================= 1507 1508 codemap for first cases is (labels masked ): 1509 eq: 0x2002,0x4010,0x0000 -> 0x2400 1510 ne: 0x2402,0x4010,0x0000 -> 0x2000 1511 lt: 0x3402,0x4010,0x0000 -> 0x3800 1512 ltu: 0x2c02,0x4010,0x0000 -> 0x2800 1513 ge: 0x3802,0x4010,0x0000 -> 0x3400 1514 geu: 0x2802,0x4010,0x0000 -> 0x2c00 1515 1516 second case: 1517 ltn: 0x3001,0x3c02,0x4010,0x0000 -> 0x3000 1518 1519 third case: 1520 gt: 0x2403,0x3802,0x4010,0x0000 -> 0x2401,0x3400 1521 gtu: 0x2403,0x2802,0x4010,0x0000 -> 0x2401,0x2c00 1522 1523 fourth case: 1524 leu: 0x2401,0x2c02,0x4010,0x0000 -> 0x2400,0x2800 1525 le: 0x2401,0x3402,0x4010,0x0000 -> 0x2400,0x3800 1526 1527 Unspecified case :) 1528 jump: 0x4010,0x0000 -> 0x3c00. */ 1529 1530 #define NUMB_RELAX_CODES 12 1531 static struct rcodes_s 1532 { 1533 int f0, f1; /* From code. */ 1534 int t0, t1; /* To code. */ 1535 int labels; /* Position of labels: 1 - one label at first 1536 word, 2 - one at second word, 3 - two 1537 labels at both. */ 1538 int cdx; /* Words to match. */ 1539 int bs; /* Shrink bytes. */ 1540 int off; /* Offset from old label for new code. */ 1541 int ncl; /* New code length. */ 1542 } rcode[] = 1543 {/* lab,cdx,bs,off,ncl */ 1544 { 0x0000, 0x0000, 0x3c00, 0x0000, 1, 0, 2, 2, 2}, /* jump */ 1545 { 0x0000, 0x2002, 0x2400, 0x0000, 1, 1, 4, 4, 2}, /* eq */ 1546 { 0x0000, 0x2402, 0x2000, 0x0000, 1, 1, 4, 4, 2}, /* ne */ 1547 { 0x0000, 0x3402, 0x3800, 0x0000, 1, 1, 4, 4, 2}, /* lt */ 1548 { 0x0000, 0x2c02, 0x2800, 0x0000, 1, 1, 4, 4, 2}, /* ltu */ 1549 { 0x0000, 0x3802, 0x3400, 0x0000, 1, 1, 4, 4, 2}, /* ge */ 1550 { 0x0000, 0x2802, 0x2c00, 0x0000, 1, 1, 4, 4, 2}, /* geu */ 1551 { 0x3001, 0x3c02, 0x3000, 0x0000, 1, 2, 6, 6, 2}, /* ltn */ 1552 { 0x2403, 0x3802, 0x2401, 0x3400, 2, 2, 4, 6, 4}, /* gt */ 1553 { 0x2403, 0x2802, 0x2401, 0x2c00, 2, 2, 4, 6, 4}, /* gtu */ 1554 { 0x2401, 0x2c02, 0x2400, 0x2800, 3, 2, 4, 6, 4}, /* leu , 2 labels */ 1555 { 0x2401, 0x2c02, 0x2400, 0x2800, 3, 2, 4, 6, 4}, /* le , 2 labels */ 1556 { 0, 0, 0, 0, 0, 0, 0, 0, 0} 1557 }; 1558 1559 /* Return TRUE if a symbol exists at the given address. */ 1560 1561 static bfd_boolean 1562 msp430_elf_symbol_address_p (bfd * abfd, 1563 asection * sec, 1564 Elf_Internal_Sym * isym, 1565 bfd_vma addr) 1566 { 1567 Elf_Internal_Shdr *symtab_hdr; 1568 unsigned int sec_shndx; 1569 Elf_Internal_Sym *isymend; 1570 struct elf_link_hash_entry **sym_hashes; 1571 struct elf_link_hash_entry **end_hashes; 1572 unsigned int symcount; 1573 1574 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec); 1575 1576 /* Examine all the local symbols. */ 1577 symtab_hdr = &elf_tdata (abfd)->symtab_hdr; 1578 for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++) 1579 if (isym->st_shndx == sec_shndx && isym->st_value == addr) 1580 return TRUE; 1581 1582 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym) 1583 - symtab_hdr->sh_info); 1584 sym_hashes = elf_sym_hashes (abfd); 1585 end_hashes = sym_hashes + symcount; 1586 for (; sym_hashes < end_hashes; sym_hashes++) 1587 { 1588 struct elf_link_hash_entry *sym_hash = *sym_hashes; 1589 1590 if ((sym_hash->root.type == bfd_link_hash_defined 1591 || sym_hash->root.type == bfd_link_hash_defweak) 1592 && sym_hash->root.u.def.section == sec 1593 && sym_hash->root.u.def.value == addr) 1594 return TRUE; 1595 } 1596 1597 return FALSE; 1598 } 1599 1600 /* Adjust all local symbols defined as '.section + 0xXXXX' (.section has 1601 sec_shndx) referenced from current and other sections. */ 1602 1603 static bfd_boolean 1604 msp430_elf_relax_adjust_locals (bfd * abfd, asection * sec, bfd_vma addr, 1605 int count, unsigned int sec_shndx, 1606 bfd_vma toaddr) 1607 { 1608 Elf_Internal_Shdr *symtab_hdr; 1609 Elf_Internal_Rela *irel; 1610 Elf_Internal_Rela *irelend; 1611 Elf_Internal_Sym *isym; 1612 1613 irel = elf_section_data (sec)->relocs; 1614 if (irel == NULL) 1615 return TRUE; 1616 1617 irelend = irel + sec->reloc_count; 1618 symtab_hdr = & elf_tdata (abfd)->symtab_hdr; 1619 isym = (Elf_Internal_Sym *) symtab_hdr->contents; 1620 1621 for (;irel < irelend; irel++) 1622 { 1623 unsigned int sidx = ELF32_R_SYM(irel->r_info); 1624 Elf_Internal_Sym *lsym = isym + sidx; 1625 1626 /* Adjust symbols referenced by .sec+0xXX. */ 1627 if (irel->r_addend > addr && irel->r_addend < toaddr 1628 && sidx < symtab_hdr->sh_info 1629 && lsym->st_shndx == sec_shndx) 1630 irel->r_addend -= count; 1631 } 1632 1633 return TRUE; 1634 } 1635 1636 /* Delete some bytes from a section while relaxing. */ 1637 1638 static bfd_boolean 1639 msp430_elf_relax_delete_bytes (bfd * abfd, asection * sec, bfd_vma addr, 1640 int count) 1641 { 1642 Elf_Internal_Shdr *symtab_hdr; 1643 unsigned int sec_shndx; 1644 bfd_byte *contents; 1645 Elf_Internal_Rela *irel; 1646 Elf_Internal_Rela *irelend; 1647 bfd_vma toaddr; 1648 Elf_Internal_Sym *isym; 1649 Elf_Internal_Sym *isymend; 1650 struct elf_link_hash_entry **sym_hashes; 1651 struct elf_link_hash_entry **end_hashes; 1652 unsigned int symcount; 1653 asection *p; 1654 1655 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec); 1656 1657 contents = elf_section_data (sec)->this_hdr.contents; 1658 1659 toaddr = sec->size; 1660 1661 irel = elf_section_data (sec)->relocs; 1662 irelend = irel + sec->reloc_count; 1663 1664 /* Actually delete the bytes. */ 1665 memmove (contents + addr, contents + addr + count, 1666 (size_t) (toaddr - addr - count)); 1667 sec->size -= count; 1668 1669 /* Adjust all the relocs. */ 1670 symtab_hdr = & elf_tdata (abfd)->symtab_hdr; 1671 isym = (Elf_Internal_Sym *) symtab_hdr->contents; 1672 for (; irel < irelend; irel++) 1673 { 1674 /* Get the new reloc address. */ 1675 if ((irel->r_offset > addr && irel->r_offset < toaddr)) 1676 irel->r_offset -= count; 1677 } 1678 1679 for (p = abfd->sections; p != NULL; p = p->next) 1680 msp430_elf_relax_adjust_locals (abfd,p,addr,count,sec_shndx,toaddr); 1681 1682 /* Adjust the local symbols defined in this section. */ 1683 symtab_hdr = & elf_tdata (abfd)->symtab_hdr; 1684 isym = (Elf_Internal_Sym *) symtab_hdr->contents; 1685 for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++) 1686 { 1687 const char * name; 1688 1689 name = bfd_elf_string_from_elf_section 1690 (abfd, symtab_hdr->sh_link, isym->st_name); 1691 name = (name == NULL || * name == 0) ? bfd_section_name (abfd, sec) : name; 1692 1693 if (isym->st_shndx != sec_shndx) 1694 continue; 1695 1696 if (isym->st_value > addr 1697 && (isym->st_value < toaddr 1698 /* We also adjust a symbol at the end of the section if its name is 1699 on the list below. These symbols are used for debug info 1700 generation and they refer to the end of the current section, not 1701 the start of the next section. */ 1702 || (isym->st_value == toaddr 1703 && name != NULL 1704 && (CONST_STRNEQ (name, ".Letext") 1705 || CONST_STRNEQ (name, ".LFE"))))) 1706 { 1707 if (isym->st_value < addr + count) 1708 isym->st_value = addr; 1709 else 1710 isym->st_value -= count; 1711 } 1712 /* Adjust the function symbol's size as well. */ 1713 else if (ELF_ST_TYPE (isym->st_info) == STT_FUNC 1714 && isym->st_value + isym->st_size > addr 1715 && isym->st_value + isym->st_size < toaddr) 1716 isym->st_size -= count; 1717 } 1718 1719 /* Now adjust the global symbols defined in this section. */ 1720 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym) 1721 - symtab_hdr->sh_info); 1722 sym_hashes = elf_sym_hashes (abfd); 1723 end_hashes = sym_hashes + symcount; 1724 for (; sym_hashes < end_hashes; sym_hashes++) 1725 { 1726 struct elf_link_hash_entry *sym_hash = *sym_hashes; 1727 1728 if ((sym_hash->root.type == bfd_link_hash_defined 1729 || sym_hash->root.type == bfd_link_hash_defweak) 1730 && sym_hash->root.u.def.section == sec 1731 && sym_hash->root.u.def.value > addr 1732 && sym_hash->root.u.def.value < toaddr) 1733 { 1734 if (sym_hash->root.u.def.value < addr + count) 1735 sym_hash->root.u.def.value = addr; 1736 else 1737 sym_hash->root.u.def.value -= count; 1738 } 1739 /* Adjust the function symbol's size as well. */ 1740 else if (sym_hash->root.type == bfd_link_hash_defined 1741 && sym_hash->root.u.def.section == sec 1742 && sym_hash->type == STT_FUNC 1743 && sym_hash->root.u.def.value + sym_hash->size > addr 1744 && sym_hash->root.u.def.value + sym_hash->size < toaddr) 1745 sym_hash->size -= count; 1746 } 1747 1748 return TRUE; 1749 } 1750 1751 /* Insert two words into a section whilst relaxing. */ 1752 1753 static bfd_byte * 1754 msp430_elf_relax_add_two_words (bfd * abfd, asection * sec, bfd_vma addr, 1755 int word1, int word2) 1756 { 1757 Elf_Internal_Shdr *symtab_hdr; 1758 unsigned int sec_shndx; 1759 bfd_byte *contents; 1760 Elf_Internal_Rela *irel; 1761 Elf_Internal_Rela *irelend; 1762 Elf_Internal_Sym *isym; 1763 Elf_Internal_Sym *isymend; 1764 struct elf_link_hash_entry **sym_hashes; 1765 struct elf_link_hash_entry **end_hashes; 1766 unsigned int symcount; 1767 bfd_vma sec_end; 1768 asection *p; 1769 1770 contents = elf_section_data (sec)->this_hdr.contents; 1771 sec_end = sec->size; 1772 1773 /* Make space for the new words. */ 1774 contents = bfd_realloc (contents, sec_end + 4); 1775 memmove (contents + addr + 4, contents + addr, sec_end - addr); 1776 1777 /* Insert the new words. */ 1778 bfd_put_16 (abfd, word1, contents + addr); 1779 bfd_put_16 (abfd, word2, contents + addr + 2); 1780 1781 /* Update the section information. */ 1782 sec->size += 4; 1783 elf_section_data (sec)->this_hdr.contents = contents; 1784 1785 /* Adjust all the relocs. */ 1786 irel = elf_section_data (sec)->relocs; 1787 irelend = irel + sec->reloc_count; 1788 1789 for (; irel < irelend; irel++) 1790 if ((irel->r_offset >= addr && irel->r_offset < sec_end)) 1791 irel->r_offset += 4; 1792 1793 /* Adjust the local symbols defined in this section. */ 1794 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec); 1795 for (p = abfd->sections; p != NULL; p = p->next) 1796 msp430_elf_relax_adjust_locals (abfd, p, addr, -4, 1797 sec_shndx, sec_end); 1798 1799 /* Adjust the global symbols affected by the move. */ 1800 symtab_hdr = & elf_tdata (abfd)->symtab_hdr; 1801 isym = (Elf_Internal_Sym *) symtab_hdr->contents; 1802 for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++) 1803 if (isym->st_shndx == sec_shndx 1804 && isym->st_value >= addr && isym->st_value < sec_end) 1805 isym->st_value += 4; 1806 1807 /* Now adjust the global symbols defined in this section. */ 1808 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym) 1809 - symtab_hdr->sh_info); 1810 sym_hashes = elf_sym_hashes (abfd); 1811 end_hashes = sym_hashes + symcount; 1812 for (; sym_hashes < end_hashes; sym_hashes++) 1813 { 1814 struct elf_link_hash_entry *sym_hash = *sym_hashes; 1815 1816 if ((sym_hash->root.type == bfd_link_hash_defined 1817 || sym_hash->root.type == bfd_link_hash_defweak) 1818 && sym_hash->root.u.def.section == sec 1819 && sym_hash->root.u.def.value >= addr 1820 && sym_hash->root.u.def.value < sec_end) 1821 sym_hash->root.u.def.value += 4; 1822 } 1823 1824 return contents; 1825 } 1826 1827 static bfd_boolean 1828 msp430_elf_relax_section (bfd * abfd, asection * sec, 1829 struct bfd_link_info * link_info, 1830 bfd_boolean * again) 1831 { 1832 Elf_Internal_Shdr * symtab_hdr; 1833 Elf_Internal_Rela * internal_relocs; 1834 Elf_Internal_Rela * irel; 1835 Elf_Internal_Rela * irelend; 1836 bfd_byte * contents = NULL; 1837 Elf_Internal_Sym * isymbuf = NULL; 1838 1839 /* Assume nothing changes. */ 1840 *again = FALSE; 1841 1842 /* We don't have to do anything for a relocatable link, if 1843 this section does not have relocs, or if this is not a 1844 code section. */ 1845 if (bfd_link_relocatable (link_info) 1846 || (sec->flags & SEC_RELOC) == 0 1847 || sec->reloc_count == 0 || (sec->flags & SEC_CODE) == 0) 1848 return TRUE; 1849 1850 symtab_hdr = & elf_tdata (abfd)->symtab_hdr; 1851 1852 /* Get a copy of the native relocations. */ 1853 internal_relocs = 1854 _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, link_info->keep_memory); 1855 if (internal_relocs == NULL) 1856 goto error_return; 1857 1858 /* Walk through them looking for relaxing opportunities. */ 1859 irelend = internal_relocs + sec->reloc_count; 1860 1861 /* Do code size growing relocs first. */ 1862 for (irel = internal_relocs; irel < irelend; irel++) 1863 { 1864 bfd_vma symval; 1865 1866 /* If this isn't something that can be relaxed, then ignore 1867 this reloc. */ 1868 if (uses_msp430x_relocs (abfd) 1869 && ELF32_R_TYPE (irel->r_info) == (int) R_MSP430X_10_PCREL) 1870 ; 1871 else if (! uses_msp430x_relocs (abfd) 1872 && ELF32_R_TYPE (irel->r_info) == (int) R_MSP430_10_PCREL) 1873 ; 1874 else 1875 continue; 1876 1877 /* Get the section contents if we haven't done so already. */ 1878 if (contents == NULL) 1879 { 1880 /* Get cached copy if it exists. */ 1881 if (elf_section_data (sec)->this_hdr.contents != NULL) 1882 contents = elf_section_data (sec)->this_hdr.contents; 1883 else if (! bfd_malloc_and_get_section (abfd, sec, &contents)) 1884 goto error_return; 1885 } 1886 1887 /* Read this BFD's local symbols if we haven't done so already. */ 1888 if (isymbuf == NULL && symtab_hdr->sh_info != 0) 1889 { 1890 isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents; 1891 if (isymbuf == NULL) 1892 isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr, 1893 symtab_hdr->sh_info, 0, 1894 NULL, NULL, NULL); 1895 if (isymbuf == NULL) 1896 goto error_return; 1897 } 1898 1899 /* Get the value of the symbol referred to by the reloc. */ 1900 if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info) 1901 { 1902 /* A local symbol. */ 1903 Elf_Internal_Sym *isym; 1904 asection *sym_sec; 1905 1906 isym = isymbuf + ELF32_R_SYM (irel->r_info); 1907 if (isym->st_shndx == SHN_UNDEF) 1908 sym_sec = bfd_und_section_ptr; 1909 else if (isym->st_shndx == SHN_ABS) 1910 sym_sec = bfd_abs_section_ptr; 1911 else if (isym->st_shndx == SHN_COMMON) 1912 sym_sec = bfd_com_section_ptr; 1913 else 1914 sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx); 1915 symval = (isym->st_value 1916 + sym_sec->output_section->vma + sym_sec->output_offset); 1917 } 1918 else 1919 { 1920 unsigned long indx; 1921 struct elf_link_hash_entry *h; 1922 1923 /* An external symbol. */ 1924 indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info; 1925 h = elf_sym_hashes (abfd)[indx]; 1926 BFD_ASSERT (h != NULL); 1927 1928 if (h->root.type != bfd_link_hash_defined 1929 && h->root.type != bfd_link_hash_defweak) 1930 /* This appears to be a reference to an undefined 1931 symbol. Just ignore it--it will be caught by the 1932 regular reloc processing. */ 1933 continue; 1934 1935 symval = (h->root.u.def.value 1936 + h->root.u.def.section->output_section->vma 1937 + h->root.u.def.section->output_offset); 1938 } 1939 1940 /* For simplicity of coding, we are going to modify the section 1941 contents, the section relocs, and the BFD symbol table. We 1942 must tell the rest of the code not to free up this 1943 information. It would be possible to instead create a table 1944 of changes which have to be made, as is done in coff-mips.c; 1945 that would be more work, but would require less memory when 1946 the linker is run. */ 1947 1948 bfd_signed_vma value = symval; 1949 int opcode; 1950 1951 /* Compute the value that will be relocated. */ 1952 value += irel->r_addend; 1953 /* Convert to PC relative. */ 1954 value -= (sec->output_section->vma + sec->output_offset); 1955 value -= irel->r_offset; 1956 value -= 2; 1957 /* Scale. */ 1958 value >>= 1; 1959 1960 /* If it is in range then no modifications are needed. */ 1961 if (value >= -512 && value <= 511) 1962 continue; 1963 1964 /* Get the opcode. */ 1965 opcode = bfd_get_16 (abfd, contents + irel->r_offset); 1966 1967 /* Compute the new opcode. We are going to convert: 1968 J<cond> label 1969 into: 1970 J<inv-cond> 1f 1971 BR[A] #label 1972 1: */ 1973 switch (opcode & 0xfc00) 1974 { 1975 case 0x3800: opcode = 0x3402; break; /* Jl -> Jge +2 */ 1976 case 0x3400: opcode = 0x3802; break; /* Jge -> Jl +2 */ 1977 case 0x2c00: opcode = 0x2802; break; /* Jhs -> Jlo +2 */ 1978 case 0x2800: opcode = 0x2c02; break; /* Jlo -> Jhs +2 */ 1979 case 0x2400: opcode = 0x2002; break; /* Jeq -> Jne +2 */ 1980 case 0x2000: opcode = 0x2402; break; /* jne -> Jeq +2 */ 1981 case 0x3000: /* jn */ 1982 /* There is no direct inverse of the Jn insn. 1983 FIXME: we could do this as: 1984 Jn 1f 1985 br 2f 1986 1: br label 1987 2: */ 1988 continue; 1989 default: 1990 /* Not a conditional branch instruction. */ 1991 /* fprintf (stderr, "unrecog: %x\n", opcode); */ 1992 continue; 1993 } 1994 1995 /* Note that we've changed the relocs, section contents, etc. */ 1996 elf_section_data (sec)->relocs = internal_relocs; 1997 elf_section_data (sec)->this_hdr.contents = contents; 1998 symtab_hdr->contents = (unsigned char *) isymbuf; 1999 2000 /* Install the new opcode. */ 2001 bfd_put_16 (abfd, opcode, contents + irel->r_offset); 2002 2003 /* Insert the new branch instruction. */ 2004 if (uses_msp430x_relocs (abfd)) 2005 { 2006 /* Insert an absolute branch (aka MOVA) instruction. */ 2007 contents = msp430_elf_relax_add_two_words 2008 (abfd, sec, irel->r_offset + 2, 0x0080, 0x0000); 2009 2010 /* Update the relocation to point to the inserted branch 2011 instruction. Note - we are changing a PC-relative reloc 2012 into an absolute reloc, but this is OK because we have 2013 arranged with the assembler to have the reloc's value be 2014 a (local) symbol, not a section+offset value. */ 2015 irel->r_offset += 2; 2016 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), 2017 R_MSP430X_ABS20_ADR_SRC); 2018 } 2019 else 2020 { 2021 contents = msp430_elf_relax_add_two_words 2022 (abfd, sec, irel->r_offset + 2, 0x4030, 0x0000); 2023 2024 /* See comment above about converting a 10-bit PC-rel 2025 relocation into a 16-bit absolute relocation. */ 2026 irel->r_offset += 4; 2027 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), 2028 R_MSP430_16); 2029 } 2030 2031 /* Growing the section may mean that other 2032 conditional branches need to be fixed. */ 2033 *again = TRUE; 2034 } 2035 2036 for (irel = internal_relocs; irel < irelend; irel++) 2037 { 2038 bfd_vma symval; 2039 2040 /* Get the section contents if we haven't done so already. */ 2041 if (contents == NULL) 2042 { 2043 /* Get cached copy if it exists. */ 2044 if (elf_section_data (sec)->this_hdr.contents != NULL) 2045 contents = elf_section_data (sec)->this_hdr.contents; 2046 else if (! bfd_malloc_and_get_section (abfd, sec, &contents)) 2047 goto error_return; 2048 } 2049 2050 /* Read this BFD's local symbols if we haven't done so already. */ 2051 if (isymbuf == NULL && symtab_hdr->sh_info != 0) 2052 { 2053 isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents; 2054 if (isymbuf == NULL) 2055 isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr, 2056 symtab_hdr->sh_info, 0, 2057 NULL, NULL, NULL); 2058 if (isymbuf == NULL) 2059 goto error_return; 2060 } 2061 2062 /* Get the value of the symbol referred to by the reloc. */ 2063 if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info) 2064 { 2065 /* A local symbol. */ 2066 Elf_Internal_Sym *isym; 2067 asection *sym_sec; 2068 2069 isym = isymbuf + ELF32_R_SYM (irel->r_info); 2070 if (isym->st_shndx == SHN_UNDEF) 2071 sym_sec = bfd_und_section_ptr; 2072 else if (isym->st_shndx == SHN_ABS) 2073 sym_sec = bfd_abs_section_ptr; 2074 else if (isym->st_shndx == SHN_COMMON) 2075 sym_sec = bfd_com_section_ptr; 2076 else 2077 sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx); 2078 symval = (isym->st_value 2079 + sym_sec->output_section->vma + sym_sec->output_offset); 2080 } 2081 else 2082 { 2083 unsigned long indx; 2084 struct elf_link_hash_entry *h; 2085 2086 /* An external symbol. */ 2087 indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info; 2088 h = elf_sym_hashes (abfd)[indx]; 2089 BFD_ASSERT (h != NULL); 2090 2091 if (h->root.type != bfd_link_hash_defined 2092 && h->root.type != bfd_link_hash_defweak) 2093 /* This appears to be a reference to an undefined 2094 symbol. Just ignore it--it will be caught by the 2095 regular reloc processing. */ 2096 continue; 2097 2098 symval = (h->root.u.def.value 2099 + h->root.u.def.section->output_section->vma 2100 + h->root.u.def.section->output_offset); 2101 } 2102 2103 /* For simplicity of coding, we are going to modify the section 2104 contents, the section relocs, and the BFD symbol table. We 2105 must tell the rest of the code not to free up this 2106 information. It would be possible to instead create a table 2107 of changes which have to be made, as is done in coff-mips.c; 2108 that would be more work, but would require less memory when 2109 the linker is run. */ 2110 2111 /* Try to turn a 16bit pc-relative branch into a 10bit pc-relative 2112 branch. */ 2113 /* Paranoia? paranoia... */ 2114 if (! uses_msp430x_relocs (abfd) 2115 && ELF32_R_TYPE (irel->r_info) == (int) R_MSP430_RL_PCREL) 2116 { 2117 bfd_vma value = symval; 2118 2119 /* Deal with pc-relative gunk. */ 2120 value -= (sec->output_section->vma + sec->output_offset); 2121 value -= irel->r_offset; 2122 value += irel->r_addend; 2123 2124 /* See if the value will fit in 10 bits, note the high value is 2125 1016 as the target will be two bytes closer if we are 2126 able to relax. */ 2127 if ((long) value < 1016 && (long) value > -1016) 2128 { 2129 int code0 = 0, code1 = 0, code2 = 0; 2130 int i; 2131 struct rcodes_s *rx; 2132 2133 /* Get the opcode. */ 2134 if (irel->r_offset >= 6) 2135 code0 = bfd_get_16 (abfd, contents + irel->r_offset - 6); 2136 2137 if (irel->r_offset >= 4) 2138 code1 = bfd_get_16 (abfd, contents + irel->r_offset - 4); 2139 2140 code2 = bfd_get_16 (abfd, contents + irel->r_offset - 2); 2141 2142 if (code2 != 0x4010) 2143 continue; 2144 2145 /* Check r4 and r3. */ 2146 for (i = NUMB_RELAX_CODES - 1; i >= 0; i--) 2147 { 2148 rx = &rcode[i]; 2149 if (rx->cdx == 2 && rx->f0 == code0 && rx->f1 == code1) 2150 break; 2151 else if (rx->cdx == 1 && rx->f1 == code1) 2152 break; 2153 else if (rx->cdx == 0) /* This is an unconditional jump. */ 2154 break; 2155 } 2156 2157 /* Check labels: 2158 .Label0: ; we do not care about this label 2159 jeq +6 2160 .Label1: ; make sure there is no label here 2161 jl +4 2162 .Label2: ; make sure there is no label here 2163 br .Label_dst 2164 2165 So, if there is .Label1 or .Label2 we cannot relax this code. 2166 This actually should not happen, cause for relaxable 2167 instructions we use RL_PCREL reloc instead of 16_PCREL. 2168 Will change this in the future. */ 2169 2170 if (rx->cdx > 0 2171 && msp430_elf_symbol_address_p (abfd, sec, isymbuf, 2172 irel->r_offset - 2)) 2173 continue; 2174 if (rx->cdx > 1 2175 && msp430_elf_symbol_address_p (abfd, sec, isymbuf, 2176 irel->r_offset - 4)) 2177 continue; 2178 2179 /* Note that we've changed the relocs, section contents, etc. */ 2180 elf_section_data (sec)->relocs = internal_relocs; 2181 elf_section_data (sec)->this_hdr.contents = contents; 2182 symtab_hdr->contents = (unsigned char *) isymbuf; 2183 2184 /* Fix the relocation's type. */ 2185 if (uses_msp430x_relocs (abfd)) 2186 { 2187 if (rx->labels == 3) /* Handle special cases. */ 2188 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), 2189 R_MSP430X_2X_PCREL); 2190 else 2191 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), 2192 R_MSP430X_10_PCREL); 2193 } 2194 else 2195 { 2196 if (rx->labels == 3) /* Handle special cases. */ 2197 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), 2198 R_MSP430_2X_PCREL); 2199 else 2200 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), 2201 R_MSP430_10_PCREL); 2202 } 2203 2204 /* Fix the opcode right way. */ 2205 bfd_put_16 (abfd, rx->t0, contents + irel->r_offset - rx->off); 2206 if (rx->t1) 2207 bfd_put_16 (abfd, rx->t1, 2208 contents + irel->r_offset - rx->off + 2); 2209 2210 /* Delete bytes. */ 2211 if (!msp430_elf_relax_delete_bytes (abfd, sec, 2212 irel->r_offset - rx->off + 2213 rx->ncl, rx->bs)) 2214 goto error_return; 2215 2216 /* Handle unconditional jumps. */ 2217 if (rx->cdx == 0) 2218 irel->r_offset -= 2; 2219 2220 /* That will change things, so, we should relax again. 2221 Note that this is not required, and it may be slow. */ 2222 *again = TRUE; 2223 } 2224 } 2225 2226 /* Try to turn a 16-bit absolute branch into a 10-bit pc-relative 2227 branch. */ 2228 if (uses_msp430x_relocs (abfd) 2229 && ELF32_R_TYPE (irel->r_info) == R_MSP430X_ABS16) 2230 { 2231 bfd_vma value = symval; 2232 2233 value -= (sec->output_section->vma + sec->output_offset); 2234 value -= irel->r_offset; 2235 value += irel->r_addend; 2236 2237 /* See if the value will fit in 10 bits, note the high value is 2238 1016 as the target will be two bytes closer if we are 2239 able to relax. */ 2240 if ((long) value < 1016 && (long) value > -1016) 2241 { 2242 int code2; 2243 2244 /* Get the opcode. */ 2245 code2 = bfd_get_16 (abfd, contents + irel->r_offset - 2); 2246 if (code2 != 0x4030) 2247 continue; 2248 /* FIXME: check r4 and r3 ? */ 2249 /* FIXME: Handle 0x4010 as well ? */ 2250 2251 /* Note that we've changed the relocs, section contents, etc. */ 2252 elf_section_data (sec)->relocs = internal_relocs; 2253 elf_section_data (sec)->this_hdr.contents = contents; 2254 symtab_hdr->contents = (unsigned char *) isymbuf; 2255 2256 /* Fix the relocation's type. */ 2257 if (uses_msp430x_relocs (abfd)) 2258 { 2259 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), 2260 R_MSP430X_10_PCREL); 2261 } 2262 else 2263 { 2264 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), 2265 R_MSP430_10_PCREL); 2266 } 2267 2268 /* Fix the opcode right way. */ 2269 bfd_put_16 (abfd, 0x3c00, contents + irel->r_offset - 2); 2270 irel->r_offset -= 2; 2271 2272 /* Delete bytes. */ 2273 if (!msp430_elf_relax_delete_bytes (abfd, sec, 2274 irel->r_offset + 2, 2)) 2275 goto error_return; 2276 2277 /* That will change things, so, we should relax again. 2278 Note that this is not required, and it may be slow. */ 2279 *again = TRUE; 2280 } 2281 } 2282 } 2283 2284 if (isymbuf != NULL && symtab_hdr->contents != (unsigned char *) isymbuf) 2285 { 2286 if (!link_info->keep_memory) 2287 free (isymbuf); 2288 else 2289 { 2290 /* Cache the symbols for elf_link_input_bfd. */ 2291 symtab_hdr->contents = (unsigned char *) isymbuf; 2292 } 2293 } 2294 2295 if (contents != NULL 2296 && elf_section_data (sec)->this_hdr.contents != contents) 2297 { 2298 if (!link_info->keep_memory) 2299 free (contents); 2300 else 2301 { 2302 /* Cache the section contents for elf_link_input_bfd. */ 2303 elf_section_data (sec)->this_hdr.contents = contents; 2304 } 2305 } 2306 2307 if (internal_relocs != NULL 2308 && elf_section_data (sec)->relocs != internal_relocs) 2309 free (internal_relocs); 2310 2311 return TRUE; 2312 2313 error_return: 2314 if (isymbuf != NULL && symtab_hdr->contents != (unsigned char *) isymbuf) 2315 free (isymbuf); 2316 if (contents != NULL 2317 && elf_section_data (sec)->this_hdr.contents != contents) 2318 free (contents); 2319 if (internal_relocs != NULL 2320 && elf_section_data (sec)->relocs != internal_relocs) 2321 free (internal_relocs); 2322 2323 return FALSE; 2324 } 2325 2326 /* Handle an MSP430 specific section when reading an object file. 2327 This is called when bfd_section_from_shdr finds a section with 2328 an unknown type. */ 2329 2330 static bfd_boolean 2331 elf32_msp430_section_from_shdr (bfd *abfd, 2332 Elf_Internal_Shdr * hdr, 2333 const char *name, 2334 int shindex) 2335 { 2336 switch (hdr->sh_type) 2337 { 2338 case SHT_MSP430_SEC_FLAGS: 2339 case SHT_MSP430_SYM_ALIASES: 2340 case SHT_MSP430_ATTRIBUTES: 2341 return _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex); 2342 default: 2343 return FALSE; 2344 } 2345 } 2346 2347 static bfd_boolean 2348 elf32_msp430_obj_attrs_handle_unknown (bfd *abfd, int tag) 2349 { 2350 _bfd_error_handler 2351 (_("Warning: %B: Unknown MSPABI object attribute %d"), 2352 abfd, tag); 2353 return TRUE; 2354 } 2355 2356 /* Determine whether an object attribute tag takes an integer, a 2357 string or both. */ 2358 2359 static int 2360 elf32_msp430_obj_attrs_arg_type (int tag) 2361 { 2362 if (tag == Tag_compatibility) 2363 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL; 2364 2365 if (tag < 32) 2366 return ATTR_TYPE_FLAG_INT_VAL; 2367 2368 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL; 2369 } 2370 2371 static inline const char * 2372 isa_type (int isa) 2373 { 2374 switch (isa) 2375 { 2376 case 1: return "MSP430"; 2377 case 2: return "MSP430X"; 2378 default: return "unknown"; 2379 } 2380 } 2381 2382 static inline const char * 2383 code_model (int model) 2384 { 2385 switch (model) 2386 { 2387 case 1: return "small"; 2388 case 2: return "large"; 2389 default: return "unknown"; 2390 } 2391 } 2392 2393 static inline const char * 2394 data_model (int model) 2395 { 2396 switch (model) 2397 { 2398 case 1: return "small"; 2399 case 2: return "large"; 2400 case 3: return "restricted large"; 2401 default: return "unknown"; 2402 } 2403 } 2404 2405 /* Merge MSPABI object attributes from IBFD into OBFD. 2406 Raise an error if there are conflicting attributes. */ 2407 2408 static bfd_boolean 2409 elf32_msp430_merge_mspabi_attributes (bfd *ibfd, bfd *obfd) 2410 { 2411 obj_attribute *in_attr; 2412 obj_attribute *out_attr; 2413 bfd_boolean result = TRUE; 2414 static bfd * first_input_bfd = NULL; 2415 2416 /* Skip linker created files. */ 2417 if (ibfd->flags & BFD_LINKER_CREATED) 2418 return TRUE; 2419 2420 /* If this is the first real object just copy the attributes. */ 2421 if (!elf_known_obj_attributes_proc (obfd)[0].i) 2422 { 2423 _bfd_elf_copy_obj_attributes (ibfd, obfd); 2424 2425 out_attr = elf_known_obj_attributes_proc (obfd); 2426 2427 /* Use the Tag_null value to indicate that 2428 the attributes have been initialized. */ 2429 out_attr[0].i = 1; 2430 2431 first_input_bfd = ibfd; 2432 return TRUE; 2433 } 2434 2435 in_attr = elf_known_obj_attributes_proc (ibfd); 2436 out_attr = elf_known_obj_attributes_proc (obfd); 2437 2438 /* The ISAs must be the same. */ 2439 if (in_attr[OFBA_MSPABI_Tag_ISA].i != out_attr[OFBA_MSPABI_Tag_ISA].i) 2440 { 2441 _bfd_error_handler 2442 (_("error: %B uses %s instructions but %B uses %s"), 2443 ibfd, first_input_bfd, 2444 isa_type (in_attr[OFBA_MSPABI_Tag_ISA].i), 2445 isa_type (out_attr[OFBA_MSPABI_Tag_ISA].i)); 2446 result = FALSE; 2447 } 2448 2449 /* The code models must be the same. */ 2450 if (in_attr[OFBA_MSPABI_Tag_Code_Model].i != 2451 out_attr[OFBA_MSPABI_Tag_Code_Model].i) 2452 { 2453 _bfd_error_handler 2454 (_("error: %B uses the %s code model whereas %B uses the %s code model"), 2455 ibfd, first_input_bfd, 2456 code_model (in_attr[OFBA_MSPABI_Tag_Code_Model].i), 2457 code_model (out_attr[OFBA_MSPABI_Tag_Code_Model].i)); 2458 result = FALSE; 2459 } 2460 2461 /* The large code model is only supported by the MSP430X. */ 2462 if (in_attr[OFBA_MSPABI_Tag_Code_Model].i == 2 2463 && out_attr[OFBA_MSPABI_Tag_ISA].i != 2) 2464 { 2465 _bfd_error_handler 2466 (_("error: %B uses the large code model but %B uses MSP430 instructions"), 2467 ibfd, first_input_bfd); 2468 result = FALSE; 2469 } 2470 2471 /* The data models must be the same. */ 2472 if (in_attr[OFBA_MSPABI_Tag_Data_Model].i != 2473 out_attr[OFBA_MSPABI_Tag_Data_Model].i) 2474 { 2475 _bfd_error_handler 2476 (_("error: %B uses the %s data model whereas %B uses the %s data model"), 2477 ibfd, first_input_bfd, 2478 data_model (in_attr[OFBA_MSPABI_Tag_Data_Model].i), 2479 data_model (out_attr[OFBA_MSPABI_Tag_Data_Model].i)); 2480 result = FALSE; 2481 } 2482 2483 /* The small code model requires the use of the small data model. */ 2484 if (in_attr[OFBA_MSPABI_Tag_Code_Model].i == 1 2485 && out_attr[OFBA_MSPABI_Tag_Data_Model].i != 1) 2486 { 2487 _bfd_error_handler 2488 (_("error: %B uses the small code model but %B uses the %s data model"), 2489 ibfd, first_input_bfd, 2490 data_model (out_attr[OFBA_MSPABI_Tag_Data_Model].i)); 2491 result = FALSE; 2492 } 2493 2494 /* The large data models are only supported by the MSP430X. */ 2495 if (in_attr[OFBA_MSPABI_Tag_Data_Model].i > 1 2496 && out_attr[OFBA_MSPABI_Tag_ISA].i != 2) 2497 { 2498 _bfd_error_handler 2499 (_("error: %B uses the %s data model but %B only uses MSP430 instructions"), 2500 ibfd, first_input_bfd, 2501 data_model (in_attr[OFBA_MSPABI_Tag_Data_Model].i)); 2502 result = FALSE; 2503 } 2504 2505 return result; 2506 } 2507 2508 /* Merge backend specific data from an object file to the output 2509 object file when linking. */ 2510 2511 static bfd_boolean 2512 elf32_msp430_merge_private_bfd_data (bfd * ibfd, bfd * obfd) 2513 { 2514 /* Make sure that the machine number reflects the most 2515 advanced version of the MSP architecture required. */ 2516 #define max(a,b) ((a) > (b) ? (a) : (b)) 2517 if (bfd_get_mach (ibfd) != bfd_get_mach (obfd)) 2518 bfd_default_set_arch_mach (obfd, bfd_get_arch (obfd), 2519 max (bfd_get_mach (ibfd), bfd_get_mach (obfd))); 2520 #undef max 2521 2522 return elf32_msp430_merge_mspabi_attributes (ibfd, obfd); 2523 } 2524 2525 static bfd_boolean 2526 msp430_elf_is_target_special_symbol (bfd *abfd, asymbol *sym) 2527 { 2528 return _bfd_elf_is_local_label_name (abfd, sym->name); 2529 } 2530 2531 static bfd_boolean 2532 uses_large_model (bfd *abfd) 2533 { 2534 obj_attribute * attr; 2535 2536 if (abfd->flags & BFD_LINKER_CREATED) 2537 return FALSE; 2538 2539 attr = elf_known_obj_attributes_proc (abfd); 2540 if (attr == NULL) 2541 return FALSE; 2542 2543 return attr[OFBA_MSPABI_Tag_Code_Model].i == 2; 2544 } 2545 2546 static unsigned int 2547 elf32_msp430_eh_frame_address_size (bfd *abfd, asection *sec ATTRIBUTE_UNUSED) 2548 { 2549 return uses_large_model (abfd) ? 4 : 2; 2550 } 2551 2552 /* This is gross. The MSP430 EABI says that (sec 11.5): 2553 2554 "An implementation may choose to use Rel or Rela 2555 type relocations for other relocations." 2556 2557 But it also says that: 2558 2559 "Certain relocations are identified as Rela only. [snip] 2560 Where Rela is specified, an implementation must honor 2561 this requirement." 2562 2563 There is one relocation marked as requiring RELA - R_MSP430_ABS_HI16 - but 2564 to keep things simple we choose to use RELA relocations throughout. The 2565 problem is that the TI compiler generates REL relocations, so we have to 2566 be able to accept those as well. */ 2567 2568 #define elf_backend_may_use_rel_p 1 2569 #define elf_backend_may_use_rela_p 1 2570 #define elf_backend_default_use_rela_p 1 2571 2572 #undef elf_backend_obj_attrs_vendor 2573 #define elf_backend_obj_attrs_vendor "mspabi" 2574 #undef elf_backend_obj_attrs_section 2575 #define elf_backend_obj_attrs_section ".MSP430.attributes" 2576 #undef elf_backend_obj_attrs_section_type 2577 #define elf_backend_obj_attrs_section_type SHT_MSP430_ATTRIBUTES 2578 #define elf_backend_section_from_shdr elf32_msp430_section_from_shdr 2579 #define elf_backend_obj_attrs_handle_unknown elf32_msp430_obj_attrs_handle_unknown 2580 #undef elf_backend_obj_attrs_arg_type 2581 #define elf_backend_obj_attrs_arg_type elf32_msp430_obj_attrs_arg_type 2582 #define bfd_elf32_bfd_merge_private_bfd_data elf32_msp430_merge_private_bfd_data 2583 #define elf_backend_eh_frame_address_size elf32_msp430_eh_frame_address_size 2584 2585 #define ELF_ARCH bfd_arch_msp430 2586 #define ELF_MACHINE_CODE EM_MSP430 2587 #define ELF_MACHINE_ALT1 EM_MSP430_OLD 2588 #define ELF_MAXPAGESIZE 4 2589 #define ELF_OSABI ELFOSABI_STANDALONE 2590 2591 #define TARGET_LITTLE_SYM msp430_elf32_vec 2592 #define TARGET_LITTLE_NAME "elf32-msp430" 2593 2594 #define elf_info_to_howto msp430_info_to_howto_rela 2595 #define elf_info_to_howto_rel NULL 2596 #define elf_backend_relocate_section elf32_msp430_relocate_section 2597 #define elf_backend_check_relocs elf32_msp430_check_relocs 2598 #define elf_backend_can_gc_sections 1 2599 #define elf_backend_final_write_processing bfd_elf_msp430_final_write_processing 2600 #define elf_backend_object_p elf32_msp430_object_p 2601 #define bfd_elf32_bfd_relax_section msp430_elf_relax_section 2602 #define bfd_elf32_bfd_is_target_special_symbol msp430_elf_is_target_special_symbol 2603 2604 #undef elf32_bed 2605 #define elf32_bed elf32_msp430_bed 2606 2607 #include "elf32-target.h" 2608 2609 /* The TI compiler sets the OSABI field to ELFOSABI_NONE. */ 2610 #undef TARGET_LITTLE_SYM 2611 #define TARGET_LITTLE_SYM msp430_elf32_ti_vec 2612 2613 #undef elf32_bed 2614 #define elf32_bed elf32_msp430_ti_bed 2615 2616 #undef ELF_OSABI 2617 #define ELF_OSABI ELFOSABI_NONE 2618 2619 static const struct bfd_elf_special_section msp430_ti_elf_special_sections[] = 2620 { 2621 /* prefix, prefix_length, suffix_len, type, attributes. */ 2622 { STRING_COMMA_LEN (".TI.symbol.alias"), 0, SHT_MSP430_SYM_ALIASES, 0 }, 2623 { STRING_COMMA_LEN (".TI.section.flags"), 0, SHT_MSP430_SEC_FLAGS, 0 }, 2624 { STRING_COMMA_LEN ("_TI_build_attrib"), 0, SHT_MSP430_ATTRIBUTES, 0 }, 2625 { NULL, 0, 0, 0, 0 } 2626 }; 2627 2628 #undef elf_backend_special_sections 2629 #define elf_backend_special_sections msp430_ti_elf_special_sections 2630 2631 #include "elf32-target.h" 2632
Indexes created Sun Mar 01 05:31:48 UTC 2026