elf32-msp430.c revision 1.5.2.1
1 /* MSP430-specific support for 32-bit ELF 2 Copyright (C) 2002-2018 Free Software Foundation, Inc. 3 Contributed by Dmitry Diky <diwil (at) mail.ru> 4 5 This file is part of BFD, the Binary File Descriptor library. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; if not, write to the Free Software 19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 20 MA 02110-1301, USA. */ 21 22 #include "sysdep.h" 23 #include "bfd.h" 24 #include "libiberty.h" 25 #include "libbfd.h" 26 #include "elf-bfd.h" 27 #include "elf/msp430.h" 28 29 static bfd_reloc_status_type 30 rl78_sym_diff_handler (bfd * abfd, 31 arelent * reloc, 32 asymbol * sym ATTRIBUTE_UNUSED, 33 void * addr ATTRIBUTE_UNUSED, 34 asection * input_sec, 35 bfd * out_bfd ATTRIBUTE_UNUSED, 36 char ** error_message ATTRIBUTE_UNUSED) 37 { 38 bfd_size_type octets; 39 octets = reloc->address * bfd_octets_per_byte (abfd); 40 41 /* Catch the case where bfd_install_relocation would return 42 bfd_reloc_outofrange because the SYM_DIFF reloc is being used in a very 43 small section. It does not actually matter if this happens because all 44 that SYM_DIFF does is compute a (4-byte) value. A second reloc then uses 45 this value, and it is that reloc that must fit into the section. 46 47 This happens in eg, gcc/testsuite/gcc.c-torture/compile/labels-3.c. */ 48 if ((octets + bfd_get_reloc_size (reloc->howto)) 49 > bfd_get_section_limit_octets (abfd, input_sec)) 50 return bfd_reloc_ok; 51 return bfd_reloc_continue; 52 } 53 54 static reloc_howto_type elf_msp430_howto_table[] = 55 { 56 HOWTO (R_MSP430_NONE, /* type */ 57 0, /* rightshift */ 58 3, /* size (0 = byte, 1 = short, 2 = long) */ 59 0, /* bitsize */ 60 FALSE, /* pc_relative */ 61 0, /* bitpos */ 62 complain_overflow_dont,/* complain_on_overflow */ 63 bfd_elf_generic_reloc, /* special_function */ 64 "R_MSP430_NONE", /* name */ 65 FALSE, /* partial_inplace */ 66 0, /* src_mask */ 67 0, /* dst_mask */ 68 FALSE), /* pcrel_offset */ 69 70 HOWTO (R_MSP430_32, /* type */ 71 0, /* rightshift */ 72 2, /* size (0 = byte, 1 = short, 2 = long) */ 73 32, /* bitsize */ 74 FALSE, /* pc_relative */ 75 0, /* bitpos */ 76 complain_overflow_bitfield,/* complain_on_overflow */ 77 bfd_elf_generic_reloc, /* special_function */ 78 "R_MSP430_32", /* name */ 79 FALSE, /* partial_inplace */ 80 0xffffffff, /* src_mask */ 81 0xffffffff, /* dst_mask */ 82 FALSE), /* pcrel_offset */ 83 84 /* A 10 bit PC relative relocation. */ 85 HOWTO (R_MSP430_10_PCREL, /* type */ 86 1, /* rightshift */ 87 1, /* size (0 = byte, 1 = short, 2 = long) */ 88 10, /* bitsize */ 89 TRUE, /* pc_relative */ 90 0, /* bitpos */ 91 complain_overflow_bitfield,/* complain_on_overflow */ 92 bfd_elf_generic_reloc, /* special_function */ 93 "R_MSP430_10_PCREL", /* name */ 94 FALSE, /* partial_inplace */ 95 0x3ff, /* src_mask */ 96 0x3ff, /* dst_mask */ 97 TRUE), /* pcrel_offset */ 98 99 /* A 16 bit absolute relocation. */ 100 HOWTO (R_MSP430_16, /* type */ 101 0, /* rightshift */ 102 1, /* size (0 = byte, 1 = short, 2 = long) */ 103 16, /* bitsize */ 104 FALSE, /* pc_relative */ 105 0, /* bitpos */ 106 complain_overflow_dont,/* complain_on_overflow */ 107 bfd_elf_generic_reloc, /* special_function */ 108 "R_MSP430_16", /* name */ 109 FALSE, /* partial_inplace */ 110 0, /* src_mask */ 111 0xffff, /* dst_mask */ 112 FALSE), /* pcrel_offset */ 113 114 /* A 16 bit PC relative relocation for command address. */ 115 HOWTO (R_MSP430_16_PCREL, /* type */ 116 1, /* rightshift */ 117 1, /* size (0 = byte, 1 = short, 2 = long) */ 118 16, /* bitsize */ 119 TRUE, /* pc_relative */ 120 0, /* bitpos */ 121 complain_overflow_dont,/* complain_on_overflow */ 122 bfd_elf_generic_reloc, /* special_function */ 123 "R_MSP430_16_PCREL", /* name */ 124 FALSE, /* partial_inplace */ 125 0, /* src_mask */ 126 0xffff, /* dst_mask */ 127 TRUE), /* pcrel_offset */ 128 129 /* A 16 bit absolute relocation, byte operations. */ 130 HOWTO (R_MSP430_16_BYTE, /* type */ 131 0, /* rightshift */ 132 1, /* size (0 = byte, 1 = short, 2 = long) */ 133 16, /* bitsize */ 134 FALSE, /* pc_relative */ 135 0, /* bitpos */ 136 complain_overflow_dont,/* complain_on_overflow */ 137 bfd_elf_generic_reloc, /* special_function */ 138 "R_MSP430_16_BYTE", /* name */ 139 FALSE, /* partial_inplace */ 140 0xffff, /* src_mask */ 141 0xffff, /* dst_mask */ 142 FALSE), /* pcrel_offset */ 143 144 /* A 16 bit absolute relocation for command address. */ 145 HOWTO (R_MSP430_16_PCREL_BYTE,/* type */ 146 1, /* rightshift */ 147 1, /* size (0 = byte, 1 = short, 2 = long) */ 148 16, /* bitsize */ 149 TRUE, /* pc_relative */ 150 0, /* bitpos */ 151 complain_overflow_dont,/* complain_on_overflow */ 152 bfd_elf_generic_reloc, /* special_function */ 153 "R_MSP430_16_PCREL_BYTE",/* name */ 154 FALSE, /* partial_inplace */ 155 0xffff, /* src_mask */ 156 0xffff, /* dst_mask */ 157 TRUE), /* pcrel_offset */ 158 159 /* A 10 bit PC relative relocation for complicated polymorphs. */ 160 HOWTO (R_MSP430_2X_PCREL, /* type */ 161 1, /* rightshift */ 162 2, /* size (0 = byte, 1 = short, 2 = long) */ 163 10, /* bitsize */ 164 TRUE, /* pc_relative */ 165 0, /* bitpos */ 166 complain_overflow_bitfield,/* complain_on_overflow */ 167 bfd_elf_generic_reloc, /* special_function */ 168 "R_MSP430_2X_PCREL", /* name */ 169 FALSE, /* partial_inplace */ 170 0x3ff, /* src_mask */ 171 0x3ff, /* dst_mask */ 172 TRUE), /* pcrel_offset */ 173 174 /* A 16 bit relaxable relocation for command address. */ 175 HOWTO (R_MSP430_RL_PCREL, /* type */ 176 1, /* rightshift */ 177 1, /* size (0 = byte, 1 = short, 2 = long) */ 178 16, /* bitsize */ 179 TRUE, /* pc_relative */ 180 0, /* bitpos */ 181 complain_overflow_dont,/* complain_on_overflow */ 182 bfd_elf_generic_reloc, /* special_function */ 183 "R_MSP430_RL_PCREL", /* name */ 184 FALSE, /* partial_inplace */ 185 0, /* src_mask */ 186 0xffff, /* dst_mask */ 187 TRUE) /* pcrel_offset */ 188 189 /* A 8-bit absolute relocation. */ 190 , HOWTO (R_MSP430_8, /* type */ 191 0, /* rightshift */ 192 0, /* size (0 = byte, 1 = short, 2 = long) */ 193 8, /* bitsize */ 194 FALSE, /* pc_relative */ 195 0, /* bitpos */ 196 complain_overflow_dont,/* complain_on_overflow */ 197 bfd_elf_generic_reloc, /* special_function */ 198 "R_MSP430_8", /* name */ 199 FALSE, /* partial_inplace */ 200 0, /* src_mask */ 201 0xffff, /* dst_mask */ 202 FALSE), /* pcrel_offset */ 203 204 /* Together with a following reloc, allows for the difference 205 between two symbols to be the real addend of the second reloc. */ 206 HOWTO (R_MSP430_SYM_DIFF, /* type */ 207 0, /* rightshift */ 208 2, /* size (0 = byte, 1 = short, 2 = long) */ 209 32, /* bitsize */ 210 FALSE, /* pc_relative */ 211 0, /* bitpos */ 212 complain_overflow_dont,/* complain_on_overflow */ 213 rl78_sym_diff_handler, /* special handler. */ 214 "R_MSP430_SYM_DIFF", /* name */ 215 FALSE, /* partial_inplace */ 216 0xffffffff, /* src_mask */ 217 0xffffffff, /* dst_mask */ 218 FALSE) /* pcrel_offset */ 219 }; 220 221 static reloc_howto_type elf_msp430x_howto_table[] = 222 { 223 HOWTO (R_MSP430_NONE, /* type */ 224 0, /* rightshift */ 225 3, /* size (0 = byte, 1 = short, 2 = long) */ 226 0, /* bitsize */ 227 FALSE, /* pc_relative */ 228 0, /* bitpos */ 229 complain_overflow_dont,/* complain_on_overflow */ 230 bfd_elf_generic_reloc, /* special_function */ 231 "R_MSP430_NONE", /* name */ 232 FALSE, /* partial_inplace */ 233 0, /* src_mask */ 234 0, /* dst_mask */ 235 FALSE), /* pcrel_offset */ 236 237 HOWTO (R_MSP430_ABS32, /* type */ 238 0, /* rightshift */ 239 2, /* size (0 = byte, 1 = short, 2 = long) */ 240 32, /* bitsize */ 241 FALSE, /* pc_relative */ 242 0, /* bitpos */ 243 complain_overflow_bitfield,/* complain_on_overflow */ 244 bfd_elf_generic_reloc, /* special_function */ 245 "R_MSP430_ABS32", /* name */ 246 FALSE, /* partial_inplace */ 247 0xffffffff, /* src_mask */ 248 0xffffffff, /* dst_mask */ 249 FALSE), /* pcrel_offset */ 250 251 HOWTO (R_MSP430_ABS16, /* type */ 252 0, /* rightshift */ 253 1, /* size (0 = byte, 1 = short, 2 = long) */ 254 16, /* bitsize */ 255 FALSE, /* pc_relative */ 256 0, /* bitpos */ 257 complain_overflow_dont,/* complain_on_overflow */ 258 bfd_elf_generic_reloc, /* special_function */ 259 "R_MSP430_ABS16", /* name */ 260 FALSE, /* partial_inplace */ 261 0, /* src_mask */ 262 0xffff, /* dst_mask */ 263 FALSE), /* pcrel_offset */ 264 265 HOWTO (R_MSP430_ABS8, /* type */ 266 0, /* rightshift */ 267 0, /* size (0 = byte, 1 = short, 2 = long) */ 268 8, /* bitsize */ 269 FALSE, /* pc_relative */ 270 0, /* bitpos */ 271 complain_overflow_bitfield,/* complain_on_overflow */ 272 bfd_elf_generic_reloc, /* special_function */ 273 "R_MSP430_ABS8", /* name */ 274 FALSE, /* partial_inplace */ 275 0xff, /* src_mask */ 276 0xff, /* dst_mask */ 277 FALSE), /* pcrel_offset */ 278 279 HOWTO (R_MSP430_PCR16, /* type */ 280 1, /* rightshift */ 281 1, /* size (0 = byte, 1 = short, 2 = long) */ 282 16, /* bitsize */ 283 TRUE, /* pc_relative */ 284 0, /* bitpos */ 285 complain_overflow_dont,/* complain_on_overflow */ 286 bfd_elf_generic_reloc, /* special_function */ 287 "R_MSP430_PCR16", /* name */ 288 FALSE, /* partial_inplace */ 289 0, /* src_mask */ 290 0xffff, /* dst_mask */ 291 TRUE), /* pcrel_offset */ 292 293 HOWTO (R_MSP430X_PCR20_EXT_SRC,/* type */ 294 0, /* rightshift */ 295 2, /* size (0 = byte, 1 = short, 2 = long) */ 296 32, /* bitsize */ 297 TRUE, /* pc_relative */ 298 0, /* bitpos */ 299 complain_overflow_dont,/* complain_on_overflow */ 300 bfd_elf_generic_reloc, /* special_function */ 301 "R_MSP430X_PCR20_EXT_SRC",/* name */ 302 FALSE, /* partial_inplace */ 303 0, /* src_mask */ 304 0xffff, /* dst_mask */ 305 TRUE), /* pcrel_offset */ 306 307 HOWTO (R_MSP430X_PCR20_EXT_DST,/* type */ 308 0, /* rightshift */ 309 2, /* size (0 = byte, 1 = short, 2 = long) */ 310 32, /* bitsize */ 311 TRUE, /* pc_relative */ 312 0, /* bitpos */ 313 complain_overflow_dont,/* complain_on_overflow */ 314 bfd_elf_generic_reloc, /* special_function */ 315 "R_MSP430X_PCR20_EXT_DST",/* name */ 316 FALSE, /* partial_inplace */ 317 0, /* src_mask */ 318 0xffff, /* dst_mask */ 319 TRUE), /* pcrel_offset */ 320 321 HOWTO (R_MSP430X_PCR20_EXT_ODST,/* type */ 322 0, /* rightshift */ 323 2, /* size (0 = byte, 1 = short, 2 = long) */ 324 32, /* bitsize */ 325 TRUE, /* pc_relative */ 326 0, /* bitpos */ 327 complain_overflow_dont,/* complain_on_overflow */ 328 bfd_elf_generic_reloc, /* special_function */ 329 "R_MSP430X_PCR20_EXT_ODST",/* name */ 330 FALSE, /* partial_inplace */ 331 0, /* src_mask */ 332 0xffff, /* dst_mask */ 333 TRUE), /* pcrel_offset */ 334 335 HOWTO (R_MSP430X_ABS20_EXT_SRC,/* type */ 336 0, /* rightshift */ 337 2, /* size (0 = byte, 1 = short, 2 = long) */ 338 32, /* bitsize */ 339 TRUE, /* pc_relative */ 340 0, /* bitpos */ 341 complain_overflow_dont,/* complain_on_overflow */ 342 bfd_elf_generic_reloc, /* special_function */ 343 "R_MSP430X_ABS20_EXT_SRC",/* name */ 344 FALSE, /* partial_inplace */ 345 0, /* src_mask */ 346 0xffff, /* dst_mask */ 347 TRUE), /* pcrel_offset */ 348 349 HOWTO (R_MSP430X_ABS20_EXT_DST,/* type */ 350 0, /* rightshift */ 351 2, /* size (0 = byte, 1 = short, 2 = long) */ 352 32, /* bitsize */ 353 TRUE, /* pc_relative */ 354 0, /* bitpos */ 355 complain_overflow_dont,/* complain_on_overflow */ 356 bfd_elf_generic_reloc, /* special_function */ 357 "R_MSP430X_ABS20_EXT_DST",/* name */ 358 FALSE, /* partial_inplace */ 359 0, /* src_mask */ 360 0xffff, /* dst_mask */ 361 TRUE), /* pcrel_offset */ 362 363 HOWTO (R_MSP430X_ABS20_EXT_ODST,/* type */ 364 0, /* rightshift */ 365 2, /* size (0 = byte, 1 = short, 2 = long) */ 366 32, /* bitsize */ 367 TRUE, /* pc_relative */ 368 0, /* bitpos */ 369 complain_overflow_dont,/* complain_on_overflow */ 370 bfd_elf_generic_reloc, /* special_function */ 371 "R_MSP430X_ABS20_EXT_ODST",/* name */ 372 FALSE, /* partial_inplace */ 373 0, /* src_mask */ 374 0xffff, /* dst_mask */ 375 TRUE), /* pcrel_offset */ 376 377 HOWTO (R_MSP430X_ABS20_ADR_SRC,/* type */ 378 0, /* rightshift */ 379 2, /* size (0 = byte, 1 = short, 2 = long) */ 380 32, /* bitsize */ 381 TRUE, /* pc_relative */ 382 0, /* bitpos */ 383 complain_overflow_dont,/* complain_on_overflow */ 384 bfd_elf_generic_reloc, /* special_function */ 385 "R_MSP430X_ABS20_ADR_SRC",/* name */ 386 FALSE, /* partial_inplace */ 387 0, /* src_mask */ 388 0xffff, /* dst_mask */ 389 TRUE), /* pcrel_offset */ 390 391 HOWTO (R_MSP430X_ABS20_ADR_DST,/* type */ 392 0, /* rightshift */ 393 2, /* size (0 = byte, 1 = short, 2 = long) */ 394 32, /* bitsize */ 395 TRUE, /* pc_relative */ 396 0, /* bitpos */ 397 complain_overflow_dont,/* complain_on_overflow */ 398 bfd_elf_generic_reloc, /* special_function */ 399 "R_MSP430X_ABS20_ADR_DST",/* name */ 400 FALSE, /* partial_inplace */ 401 0, /* src_mask */ 402 0xffff, /* dst_mask */ 403 TRUE), /* pcrel_offset */ 404 405 HOWTO (R_MSP430X_PCR16, /* type */ 406 0, /* rightshift */ 407 2, /* size (0 = byte, 1 = short, 2 = long) */ 408 32, /* bitsize */ 409 TRUE, /* pc_relative */ 410 0, /* bitpos */ 411 complain_overflow_dont,/* complain_on_overflow */ 412 bfd_elf_generic_reloc, /* special_function */ 413 "R_MSP430X_PCR16", /* name */ 414 FALSE, /* partial_inplace */ 415 0, /* src_mask */ 416 0xffff, /* dst_mask */ 417 TRUE), /* pcrel_offset */ 418 419 HOWTO (R_MSP430X_PCR20_CALL, /* type */ 420 0, /* rightshift */ 421 2, /* size (0 = byte, 1 = short, 2 = long) */ 422 32, /* bitsize */ 423 TRUE, /* pc_relative */ 424 0, /* bitpos */ 425 complain_overflow_dont,/* complain_on_overflow */ 426 bfd_elf_generic_reloc, /* special_function */ 427 "R_MSP430X_PCR20_CALL",/* name */ 428 FALSE, /* partial_inplace */ 429 0, /* src_mask */ 430 0xffff, /* dst_mask */ 431 TRUE), /* pcrel_offset */ 432 433 HOWTO (R_MSP430X_ABS16, /* type */ 434 0, /* rightshift */ 435 2, /* size (0 = byte, 1 = short, 2 = long) */ 436 32, /* bitsize */ 437 TRUE, /* pc_relative */ 438 0, /* bitpos */ 439 complain_overflow_dont,/* complain_on_overflow */ 440 bfd_elf_generic_reloc, /* special_function */ 441 "R_MSP430X_ABS16", /* name */ 442 FALSE, /* partial_inplace */ 443 0, /* src_mask */ 444 0xffff, /* dst_mask */ 445 TRUE), /* pcrel_offset */ 446 447 HOWTO (R_MSP430_ABS_HI16, /* type */ 448 0, /* rightshift */ 449 2, /* size (0 = byte, 1 = short, 2 = long) */ 450 32, /* bitsize */ 451 TRUE, /* pc_relative */ 452 0, /* bitpos */ 453 complain_overflow_dont,/* complain_on_overflow */ 454 bfd_elf_generic_reloc, /* special_function */ 455 "R_MSP430_ABS_HI16", /* name */ 456 FALSE, /* partial_inplace */ 457 0, /* src_mask */ 458 0xffff, /* dst_mask */ 459 TRUE), /* pcrel_offset */ 460 461 HOWTO (R_MSP430_PREL31, /* type */ 462 0, /* rightshift */ 463 2, /* size (0 = byte, 1 = short, 2 = long) */ 464 32, /* bitsize */ 465 TRUE, /* pc_relative */ 466 0, /* bitpos */ 467 complain_overflow_dont,/* complain_on_overflow */ 468 bfd_elf_generic_reloc, /* special_function */ 469 "R_MSP430_PREL31", /* name */ 470 FALSE, /* partial_inplace */ 471 0, /* src_mask */ 472 0xffff, /* dst_mask */ 473 TRUE), /* pcrel_offset */ 474 475 EMPTY_HOWTO (R_MSP430_EHTYPE), 476 477 /* A 10 bit PC relative relocation. */ 478 HOWTO (R_MSP430X_10_PCREL, /* type */ 479 1, /* rightshift */ 480 1, /* size (0 = byte, 1 = short, 2 = long) */ 481 10, /* bitsize */ 482 TRUE, /* pc_relative */ 483 0, /* bitpos */ 484 complain_overflow_bitfield,/* complain_on_overflow */ 485 bfd_elf_generic_reloc, /* special_function */ 486 "R_MSP430X_10_PCREL", /* name */ 487 FALSE, /* partial_inplace */ 488 0x3ff, /* src_mask */ 489 0x3ff, /* dst_mask */ 490 TRUE), /* pcrel_offset */ 491 492 /* A 10 bit PC relative relocation for complicated polymorphs. */ 493 HOWTO (R_MSP430X_2X_PCREL, /* type */ 494 1, /* rightshift */ 495 2, /* size (0 = byte, 1 = short, 2 = long) */ 496 10, /* bitsize */ 497 TRUE, /* pc_relative */ 498 0, /* bitpos */ 499 complain_overflow_bitfield,/* complain_on_overflow */ 500 bfd_elf_generic_reloc, /* special_function */ 501 "R_MSP430X_2X_PCREL", /* name */ 502 FALSE, /* partial_inplace */ 503 0x3ff, /* src_mask */ 504 0x3ff, /* dst_mask */ 505 TRUE), /* pcrel_offset */ 506 507 /* Together with a following reloc, allows for the difference 508 between two symbols to be the real addend of the second reloc. */ 509 HOWTO (R_MSP430X_SYM_DIFF, /* type */ 510 0, /* rightshift */ 511 2, /* size (0 = byte, 1 = short, 2 = long) */ 512 32, /* bitsize */ 513 FALSE, /* pc_relative */ 514 0, /* bitpos */ 515 complain_overflow_dont,/* complain_on_overflow */ 516 rl78_sym_diff_handler, /* special handler. */ 517 "R_MSP430X_SYM_DIFF", /* name */ 518 FALSE, /* partial_inplace */ 519 0xffffffff, /* src_mask */ 520 0xffffffff, /* dst_mask */ 521 FALSE) /* pcrel_offset */ 522 }; 523 524 /* Map BFD reloc types to MSP430 ELF reloc types. */ 525 526 struct msp430_reloc_map 527 { 528 bfd_reloc_code_real_type bfd_reloc_val; 529 unsigned int elf_reloc_val; 530 }; 531 532 static const struct msp430_reloc_map msp430_reloc_map[] = 533 { 534 {BFD_RELOC_NONE, R_MSP430_NONE}, 535 {BFD_RELOC_32, R_MSP430_32}, 536 {BFD_RELOC_MSP430_10_PCREL, R_MSP430_10_PCREL}, 537 {BFD_RELOC_16, R_MSP430_16_BYTE}, 538 {BFD_RELOC_MSP430_16_PCREL, R_MSP430_16_PCREL}, 539 {BFD_RELOC_MSP430_16, R_MSP430_16}, 540 {BFD_RELOC_MSP430_16_PCREL_BYTE, R_MSP430_16_PCREL_BYTE}, 541 {BFD_RELOC_MSP430_16_BYTE, R_MSP430_16_BYTE}, 542 {BFD_RELOC_MSP430_2X_PCREL, R_MSP430_2X_PCREL}, 543 {BFD_RELOC_MSP430_RL_PCREL, R_MSP430_RL_PCREL}, 544 {BFD_RELOC_8, R_MSP430_8}, 545 {BFD_RELOC_MSP430_SYM_DIFF, R_MSP430_SYM_DIFF} 546 }; 547 548 static const struct msp430_reloc_map msp430x_reloc_map[] = 549 { 550 {BFD_RELOC_NONE, R_MSP430_NONE}, 551 {BFD_RELOC_32, R_MSP430_ABS32}, 552 {BFD_RELOC_16, R_MSP430_ABS16}, 553 {BFD_RELOC_8, R_MSP430_ABS8}, 554 {BFD_RELOC_MSP430_ABS8, R_MSP430_ABS8}, 555 {BFD_RELOC_MSP430X_PCR20_EXT_SRC, R_MSP430X_PCR20_EXT_SRC}, 556 {BFD_RELOC_MSP430X_PCR20_EXT_DST, R_MSP430X_PCR20_EXT_DST}, 557 {BFD_RELOC_MSP430X_PCR20_EXT_ODST, R_MSP430X_PCR20_EXT_ODST}, 558 {BFD_RELOC_MSP430X_ABS20_EXT_SRC, R_MSP430X_ABS20_EXT_SRC}, 559 {BFD_RELOC_MSP430X_ABS20_EXT_DST, R_MSP430X_ABS20_EXT_DST}, 560 {BFD_RELOC_MSP430X_ABS20_EXT_ODST, R_MSP430X_ABS20_EXT_ODST}, 561 {BFD_RELOC_MSP430X_ABS20_ADR_SRC, R_MSP430X_ABS20_ADR_SRC}, 562 {BFD_RELOC_MSP430X_ABS20_ADR_DST, R_MSP430X_ABS20_ADR_DST}, 563 {BFD_RELOC_MSP430X_PCR16, R_MSP430X_PCR16}, 564 {BFD_RELOC_MSP430X_PCR20_CALL, R_MSP430X_PCR20_CALL}, 565 {BFD_RELOC_MSP430X_ABS16, R_MSP430X_ABS16}, 566 {BFD_RELOC_MSP430_ABS_HI16, R_MSP430_ABS_HI16}, 567 {BFD_RELOC_MSP430_PREL31, R_MSP430_PREL31}, 568 {BFD_RELOC_MSP430_10_PCREL, R_MSP430X_10_PCREL}, 569 {BFD_RELOC_MSP430_2X_PCREL, R_MSP430X_2X_PCREL}, 570 {BFD_RELOC_MSP430_RL_PCREL, R_MSP430X_PCR16}, 571 {BFD_RELOC_MSP430_SYM_DIFF, R_MSP430X_SYM_DIFF} 572 }; 573 574 static inline bfd_boolean 575 uses_msp430x_relocs (bfd * abfd) 576 { 577 extern const bfd_target msp430_elf32_ti_vec; 578 579 return bfd_get_mach (abfd) == bfd_mach_msp430x 580 || abfd->xvec == & msp430_elf32_ti_vec; 581 } 582 583 static reloc_howto_type * 584 bfd_elf32_bfd_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, 585 bfd_reloc_code_real_type code) 586 { 587 unsigned int i; 588 589 if (uses_msp430x_relocs (abfd)) 590 { 591 for (i = ARRAY_SIZE (msp430x_reloc_map); i--;) 592 if (msp430x_reloc_map[i].bfd_reloc_val == code) 593 return elf_msp430x_howto_table + msp430x_reloc_map[i].elf_reloc_val; 594 } 595 else 596 { 597 for (i = 0; i < ARRAY_SIZE (msp430_reloc_map); i++) 598 if (msp430_reloc_map[i].bfd_reloc_val == code) 599 return &elf_msp430_howto_table[msp430_reloc_map[i].elf_reloc_val]; 600 } 601 602 return NULL; 603 } 604 605 static reloc_howto_type * 606 bfd_elf32_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, 607 const char *r_name) 608 { 609 unsigned int i; 610 611 if (uses_msp430x_relocs (abfd)) 612 { 613 for (i = ARRAY_SIZE (elf_msp430x_howto_table); i--;) 614 if (elf_msp430x_howto_table[i].name != NULL 615 && strcasecmp (elf_msp430x_howto_table[i].name, r_name) == 0) 616 return elf_msp430x_howto_table + i; 617 } 618 else 619 { 620 for (i = 0; 621 i < (sizeof (elf_msp430_howto_table) 622 / sizeof (elf_msp430_howto_table[0])); 623 i++) 624 if (elf_msp430_howto_table[i].name != NULL 625 && strcasecmp (elf_msp430_howto_table[i].name, r_name) == 0) 626 return &elf_msp430_howto_table[i]; 627 } 628 629 return NULL; 630 } 631 632 /* Set the howto pointer for an MSP430 ELF reloc. */ 633 634 static bfd_boolean 635 msp430_info_to_howto_rela (bfd * abfd, 636 arelent * cache_ptr, 637 Elf_Internal_Rela * dst) 638 { 639 unsigned int r_type; 640 641 r_type = ELF32_R_TYPE (dst->r_info); 642 643 if (uses_msp430x_relocs (abfd)) 644 { 645 if (r_type >= (unsigned int) R_MSP430x_max) 646 { 647 /* xgettext:c-format */ 648 _bfd_error_handler (_("%pB: unsupported relocation type %#x"), 649 abfd, r_type); 650 bfd_set_error (bfd_error_bad_value); 651 return FALSE; 652 } 653 cache_ptr->howto = elf_msp430x_howto_table + r_type; 654 } 655 else if (r_type >= (unsigned int) R_MSP430_max) 656 { 657 /* xgettext:c-format */ 658 _bfd_error_handler (_("%pB: unsupported relocation type %#x"), 659 abfd, r_type); 660 bfd_set_error (bfd_error_bad_value); 661 return FALSE; 662 } 663 else 664 cache_ptr->howto = &elf_msp430_howto_table[r_type]; 665 666 return TRUE; 667 } 668 669 /* Look through the relocs for a section during the first phase. 670 Since we don't do .gots or .plts, we just need to consider the 671 virtual table relocs for gc. */ 672 673 static bfd_boolean 674 elf32_msp430_check_relocs (bfd * abfd, struct bfd_link_info * info, 675 asection * sec, const Elf_Internal_Rela * relocs) 676 { 677 Elf_Internal_Shdr *symtab_hdr; 678 struct elf_link_hash_entry **sym_hashes; 679 const Elf_Internal_Rela *rel; 680 const Elf_Internal_Rela *rel_end; 681 682 if (bfd_link_relocatable (info)) 683 return TRUE; 684 685 symtab_hdr = &elf_tdata (abfd)->symtab_hdr; 686 sym_hashes = elf_sym_hashes (abfd); 687 688 rel_end = relocs + sec->reloc_count; 689 for (rel = relocs; rel < rel_end; rel++) 690 { 691 struct elf_link_hash_entry *h; 692 unsigned long r_symndx; 693 694 r_symndx = ELF32_R_SYM (rel->r_info); 695 if (r_symndx < symtab_hdr->sh_info) 696 h = NULL; 697 else 698 { 699 h = sym_hashes[r_symndx - symtab_hdr->sh_info]; 700 while (h->root.type == bfd_link_hash_indirect 701 || h->root.type == bfd_link_hash_warning) 702 h = (struct elf_link_hash_entry *) h->root.u.i.link; 703 } 704 } 705 706 return TRUE; 707 } 708 709 /* Perform a single relocation. By default we use the standard BFD 710 routines, but a few relocs, we have to do them ourselves. */ 711 712 static bfd_reloc_status_type 713 msp430_final_link_relocate (reloc_howto_type * howto, 714 bfd * input_bfd, 715 asection * input_section, 716 bfd_byte * contents, 717 Elf_Internal_Rela * rel, 718 bfd_vma relocation, 719 struct bfd_link_info * info) 720 { 721 static asection * sym_diff_section; 722 static bfd_vma sym_diff_value; 723 724 struct bfd_elf_section_data * esd = elf_section_data (input_section); 725 bfd_reloc_status_type r = bfd_reloc_ok; 726 bfd_vma x; 727 bfd_signed_vma srel; 728 bfd_boolean is_rel_reloc = FALSE; 729 730 if (uses_msp430x_relocs (input_bfd)) 731 { 732 /* See if we have a REL type relocation. */ 733 is_rel_reloc = (esd->rel.hdr != NULL); 734 /* Sanity check - only one type of relocation per section. 735 FIXME: Theoretically it is possible to have both types, 736 but if that happens how can we distinguish between the two ? */ 737 BFD_ASSERT (! is_rel_reloc || ! esd->rela.hdr); 738 /* If we are using a REL relocation then the addend should be empty. */ 739 BFD_ASSERT (! is_rel_reloc || rel->r_addend == 0); 740 } 741 742 if (sym_diff_section != NULL) 743 { 744 BFD_ASSERT (sym_diff_section == input_section); 745 746 if (uses_msp430x_relocs (input_bfd)) 747 switch (howto->type) 748 { 749 case R_MSP430_ABS32: 750 /* If we are computing a 32-bit value for the location lists 751 and the result is 0 then we add one to the value. A zero 752 value can result because of linker relaxation deleteing 753 prologue instructions and using a value of 1 (for the begin 754 and end offsets in the location list entry) results in a 755 nul entry which does not prevent the following entries from 756 being parsed. */ 757 if (relocation == sym_diff_value 758 && strcmp (input_section->name, ".debug_loc") == 0) 759 ++ relocation; 760 /* Fall through. */ 761 case R_MSP430_ABS16: 762 case R_MSP430X_ABS16: 763 case R_MSP430_ABS8: 764 BFD_ASSERT (! is_rel_reloc); 765 relocation -= sym_diff_value; 766 break; 767 768 default: 769 return bfd_reloc_dangerous; 770 } 771 else 772 switch (howto->type) 773 { 774 case R_MSP430_32: 775 case R_MSP430_16: 776 case R_MSP430_16_BYTE: 777 case R_MSP430_8: 778 relocation -= sym_diff_value; 779 break; 780 781 default: 782 return bfd_reloc_dangerous; 783 } 784 785 sym_diff_section = NULL; 786 } 787 788 if (uses_msp430x_relocs (input_bfd)) 789 switch (howto->type) 790 { 791 case R_MSP430X_SYM_DIFF: 792 /* Cache the input section and value. 793 The offset is unreliable, since relaxation may 794 have reduced the following reloc's offset. */ 795 BFD_ASSERT (! is_rel_reloc); 796 sym_diff_section = input_section; 797 sym_diff_value = relocation; 798 return bfd_reloc_ok; 799 800 case R_MSP430_ABS16: 801 contents += rel->r_offset; 802 srel = (bfd_signed_vma) relocation; 803 if (is_rel_reloc) 804 srel += bfd_get_16 (input_bfd, contents); 805 else 806 srel += rel->r_addend; 807 bfd_put_16 (input_bfd, srel & 0xffff, contents); 808 break; 809 810 case R_MSP430X_10_PCREL: 811 contents += rel->r_offset; 812 srel = (bfd_signed_vma) relocation; 813 if (is_rel_reloc) 814 srel += bfd_get_16 (input_bfd, contents) & 0x3ff; 815 else 816 srel += rel->r_addend; 817 srel -= rel->r_offset; 818 srel -= 2; /* Branch instructions add 2 to the PC... */ 819 srel -= (input_section->output_section->vma + 820 input_section->output_offset); 821 if (srel & 1) 822 return bfd_reloc_outofrange; 823 824 /* MSP430 addresses commands as words. */ 825 srel >>= 1; 826 827 /* Check for an overflow. */ 828 if (srel < -512 || srel > 511) 829 { 830 if (info->disable_target_specific_optimizations < 0) 831 { 832 static bfd_boolean warned = FALSE; 833 if (! warned) 834 { 835 info->callbacks->warning 836 (info, 837 _("try enabling relaxation to avoid relocation truncations"), 838 NULL, input_bfd, input_section, relocation); 839 warned = TRUE; 840 } 841 } 842 return bfd_reloc_overflow; 843 } 844 845 x = bfd_get_16 (input_bfd, contents); 846 x = (x & 0xfc00) | (srel & 0x3ff); 847 bfd_put_16 (input_bfd, x, contents); 848 break; 849 850 case R_MSP430X_PCR20_EXT_ODST: 851 /* [0,4]+[48,16] = ---F ---- ---- FFFF */ 852 contents += rel->r_offset; 853 srel = (bfd_signed_vma) relocation; 854 if (is_rel_reloc) 855 { 856 bfd_vma addend; 857 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16; 858 addend |= bfd_get_16 (input_bfd, contents + 6); 859 srel += addend; 860 861 } 862 else 863 srel += rel->r_addend; 864 srel -= rel->r_offset; 865 srel -= (input_section->output_section->vma + 866 input_section->output_offset); 867 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 6); 868 x = bfd_get_16 (input_bfd, contents); 869 x = (x & 0xfff0) | ((srel >> 16) & 0xf); 870 bfd_put_16 (input_bfd, x, contents); 871 break; 872 873 case R_MSP430X_ABS20_EXT_SRC: 874 /* [7,4]+[32,16] = -78- ---- FFFF */ 875 contents += rel->r_offset; 876 srel = (bfd_signed_vma) relocation; 877 if (is_rel_reloc) 878 { 879 bfd_vma addend; 880 addend = (bfd_get_16 (input_bfd, contents) & 0x0780) << 9; 881 addend |= bfd_get_16 (input_bfd, contents + 4); 882 srel += addend; 883 } 884 else 885 srel += rel->r_addend; 886 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4); 887 srel >>= 16; 888 x = bfd_get_16 (input_bfd, contents); 889 x = (x & 0xf87f) | ((srel << 7) & 0x0780); 890 bfd_put_16 (input_bfd, x, contents); 891 break; 892 893 case R_MSP430_16_PCREL: 894 contents += rel->r_offset; 895 srel = (bfd_signed_vma) relocation; 896 if (is_rel_reloc) 897 srel += bfd_get_16 (input_bfd, contents); 898 else 899 srel += rel->r_addend; 900 srel -= rel->r_offset; 901 /* Only branch instructions add 2 to the PC... */ 902 srel -= (input_section->output_section->vma + 903 input_section->output_offset); 904 if (srel & 1) 905 return bfd_reloc_outofrange; 906 bfd_put_16 (input_bfd, srel & 0xffff, contents); 907 break; 908 909 case R_MSP430X_PCR20_EXT_DST: 910 /* [0,4]+[32,16] = ---F ---- FFFF */ 911 contents += rel->r_offset; 912 srel = (bfd_signed_vma) relocation; 913 if (is_rel_reloc) 914 { 915 bfd_vma addend; 916 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16; 917 addend |= bfd_get_16 (input_bfd, contents + 4); 918 srel += addend; 919 } 920 else 921 srel += rel->r_addend; 922 srel -= rel->r_offset; 923 srel -= (input_section->output_section->vma + 924 input_section->output_offset); 925 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4); 926 srel >>= 16; 927 x = bfd_get_16 (input_bfd, contents); 928 x = (x & 0xfff0) | (srel & 0xf); 929 bfd_put_16 (input_bfd, x, contents); 930 break; 931 932 case R_MSP430X_PCR20_EXT_SRC: 933 /* [7,4]+[32,16] = -78- ---- FFFF */ 934 contents += rel->r_offset; 935 srel = (bfd_signed_vma) relocation; 936 if (is_rel_reloc) 937 { 938 bfd_vma addend; 939 addend = ((bfd_get_16 (input_bfd, contents) & 0x0780) << 9); 940 addend |= bfd_get_16 (input_bfd, contents + 4); 941 srel += addend;; 942 } 943 else 944 srel += rel->r_addend; 945 srel -= rel->r_offset; 946 /* Only branch instructions add 2 to the PC... */ 947 srel -= (input_section->output_section->vma + 948 input_section->output_offset); 949 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4); 950 srel >>= 16; 951 x = bfd_get_16 (input_bfd, contents); 952 x = (x & 0xf87f) | ((srel << 7) & 0x0780); 953 bfd_put_16 (input_bfd, x, contents); 954 break; 955 956 case R_MSP430_ABS8: 957 contents += rel->r_offset; 958 srel = (bfd_signed_vma) relocation; 959 if (is_rel_reloc) 960 srel += bfd_get_8 (input_bfd, contents); 961 else 962 srel += rel->r_addend; 963 bfd_put_8 (input_bfd, srel & 0xff, contents); 964 break; 965 966 case R_MSP430X_ABS20_EXT_DST: 967 /* [0,4]+[32,16] = ---F ---- FFFF */ 968 contents += rel->r_offset; 969 srel = (bfd_signed_vma) relocation; 970 if (is_rel_reloc) 971 { 972 bfd_vma addend; 973 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16; 974 addend |= bfd_get_16 (input_bfd, contents + 4); 975 srel += addend; 976 } 977 else 978 srel += rel->r_addend; 979 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4); 980 srel >>= 16; 981 x = bfd_get_16 (input_bfd, contents); 982 x = (x & 0xfff0) | (srel & 0xf); 983 bfd_put_16 (input_bfd, x, contents); 984 break; 985 986 case R_MSP430X_ABS20_EXT_ODST: 987 /* [0,4]+[48,16] = ---F ---- ---- FFFF */ 988 contents += rel->r_offset; 989 srel = (bfd_signed_vma) relocation; 990 if (is_rel_reloc) 991 { 992 bfd_vma addend; 993 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16; 994 addend |= bfd_get_16 (input_bfd, contents + 6); 995 srel += addend; 996 } 997 else 998 srel += rel->r_addend; 999 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 6); 1000 srel >>= 16; 1001 x = bfd_get_16 (input_bfd, contents); 1002 x = (x & 0xfff0) | (srel & 0xf); 1003 bfd_put_16 (input_bfd, x, contents); 1004 break; 1005 1006 case R_MSP430X_ABS20_ADR_SRC: 1007 /* [8,4]+[16,16] = -F-- FFFF */ 1008 contents += rel->r_offset; 1009 srel = (bfd_signed_vma) relocation; 1010 if (is_rel_reloc) 1011 { 1012 bfd_vma addend; 1013 1014 addend = ((bfd_get_16 (input_bfd, contents) & 0xf00) << 8); 1015 addend |= bfd_get_16 (input_bfd, contents + 2); 1016 srel += addend; 1017 } 1018 else 1019 srel += rel->r_addend; 1020 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 2); 1021 srel >>= 16; 1022 x = bfd_get_16 (input_bfd, contents); 1023 x = (x & 0xf0ff) | ((srel << 8) & 0x0f00); 1024 bfd_put_16 (input_bfd, x, contents); 1025 break; 1026 1027 case R_MSP430X_ABS20_ADR_DST: 1028 /* [0,4]+[16,16] = ---F FFFF */ 1029 contents += rel->r_offset; 1030 srel = (bfd_signed_vma) relocation; 1031 if (is_rel_reloc) 1032 { 1033 bfd_vma addend; 1034 addend = ((bfd_get_16 (input_bfd, contents) & 0xf) << 16); 1035 addend |= bfd_get_16 (input_bfd, contents + 2); 1036 srel += addend; 1037 } 1038 else 1039 srel += rel->r_addend; 1040 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 2); 1041 srel >>= 16; 1042 x = bfd_get_16 (input_bfd, contents); 1043 x = (x & 0xfff0) | (srel & 0xf); 1044 bfd_put_16 (input_bfd, x, contents); 1045 break; 1046 1047 case R_MSP430X_ABS16: 1048 contents += rel->r_offset; 1049 srel = (bfd_signed_vma) relocation; 1050 if (is_rel_reloc) 1051 srel += bfd_get_16 (input_bfd, contents); 1052 else 1053 srel += rel->r_addend; 1054 x = srel; 1055 if (x > 0xffff) 1056 return bfd_reloc_overflow; 1057 bfd_put_16 (input_bfd, srel & 0xffff, contents); 1058 break; 1059 1060 case R_MSP430_ABS_HI16: 1061 /* The EABI specifies that this must be a RELA reloc. */ 1062 BFD_ASSERT (! is_rel_reloc); 1063 contents += rel->r_offset; 1064 srel = (bfd_signed_vma) relocation; 1065 srel += rel->r_addend; 1066 bfd_put_16 (input_bfd, (srel >> 16) & 0xffff, contents); 1067 break; 1068 1069 case R_MSP430X_PCR20_CALL: 1070 /* [0,4]+[16,16] = ---F FFFF*/ 1071 contents += rel->r_offset; 1072 srel = (bfd_signed_vma) relocation; 1073 if (is_rel_reloc) 1074 { 1075 bfd_vma addend; 1076 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16; 1077 addend |= bfd_get_16 (input_bfd, contents + 2); 1078 srel += addend; 1079 } 1080 else 1081 srel += rel->r_addend; 1082 srel -= rel->r_offset; 1083 srel -= (input_section->output_section->vma + 1084 input_section->output_offset); 1085 bfd_put_16 (input_bfd, srel & 0xffff, contents + 2); 1086 srel >>= 16; 1087 x = bfd_get_16 (input_bfd, contents); 1088 x = (x & 0xfff0) | (srel & 0xf); 1089 bfd_put_16 (input_bfd, x, contents); 1090 break; 1091 1092 case R_MSP430X_PCR16: 1093 contents += rel->r_offset; 1094 srel = (bfd_signed_vma) relocation; 1095 if (is_rel_reloc) 1096 srel += bfd_get_16 (input_bfd, contents); 1097 else 1098 srel += rel->r_addend; 1099 srel -= rel->r_offset; 1100 srel -= (input_section->output_section->vma + 1101 input_section->output_offset); 1102 bfd_put_16 (input_bfd, srel & 0xffff, contents); 1103 break; 1104 1105 case R_MSP430_PREL31: 1106 contents += rel->r_offset; 1107 srel = (bfd_signed_vma) relocation; 1108 if (is_rel_reloc) 1109 srel += (bfd_get_32 (input_bfd, contents) & 0x7fffffff); 1110 else 1111 srel += rel->r_addend; 1112 srel += rel->r_addend; 1113 x = bfd_get_32 (input_bfd, contents); 1114 x = (x & 0x80000000) | ((srel >> 31) & 0x7fffffff); 1115 bfd_put_32 (input_bfd, x, contents); 1116 break; 1117 1118 default: 1119 r = _bfd_final_link_relocate (howto, input_bfd, input_section, 1120 contents, rel->r_offset, 1121 relocation, rel->r_addend); 1122 } 1123 else 1124 switch (howto->type) 1125 { 1126 case R_MSP430_10_PCREL: 1127 contents += rel->r_offset; 1128 srel = (bfd_signed_vma) relocation; 1129 srel += rel->r_addend; 1130 srel -= rel->r_offset; 1131 srel -= 2; /* Branch instructions add 2 to the PC... */ 1132 srel -= (input_section->output_section->vma + 1133 input_section->output_offset); 1134 1135 if (srel & 1) 1136 return bfd_reloc_outofrange; 1137 1138 /* MSP430 addresses commands as words. */ 1139 srel >>= 1; 1140 1141 /* Check for an overflow. */ 1142 if (srel < -512 || srel > 511) 1143 { 1144 if (info->disable_target_specific_optimizations < 0) 1145 { 1146 static bfd_boolean warned = FALSE; 1147 if (! warned) 1148 { 1149 info->callbacks->warning 1150 (info, 1151 _("try enabling relaxation to avoid relocation truncations"), 1152 NULL, input_bfd, input_section, relocation); 1153 warned = TRUE; 1154 } 1155 } 1156 return bfd_reloc_overflow; 1157 } 1158 1159 x = bfd_get_16 (input_bfd, contents); 1160 x = (x & 0xfc00) | (srel & 0x3ff); 1161 bfd_put_16 (input_bfd, x, contents); 1162 break; 1163 1164 case R_MSP430_2X_PCREL: 1165 contents += rel->r_offset; 1166 srel = (bfd_signed_vma) relocation; 1167 srel += rel->r_addend; 1168 srel -= rel->r_offset; 1169 srel -= 2; /* Branch instructions add 2 to the PC... */ 1170 srel -= (input_section->output_section->vma + 1171 input_section->output_offset); 1172 1173 if (srel & 1) 1174 return bfd_reloc_outofrange; 1175 1176 /* MSP430 addresses commands as words. */ 1177 srel >>= 1; 1178 1179 /* Check for an overflow. */ 1180 if (srel < -512 || srel > 511) 1181 return bfd_reloc_overflow; 1182 1183 x = bfd_get_16 (input_bfd, contents); 1184 x = (x & 0xfc00) | (srel & 0x3ff); 1185 bfd_put_16 (input_bfd, x, contents); 1186 /* Handle second jump instruction. */ 1187 x = bfd_get_16 (input_bfd, contents - 2); 1188 srel += 1; 1189 x = (x & 0xfc00) | (srel & 0x3ff); 1190 bfd_put_16 (input_bfd, x, contents - 2); 1191 break; 1192 1193 case R_MSP430_RL_PCREL: 1194 case R_MSP430_16_PCREL: 1195 contents += rel->r_offset; 1196 srel = (bfd_signed_vma) relocation; 1197 srel += rel->r_addend; 1198 srel -= rel->r_offset; 1199 /* Only branch instructions add 2 to the PC... */ 1200 srel -= (input_section->output_section->vma + 1201 input_section->output_offset); 1202 1203 if (srel & 1) 1204 return bfd_reloc_outofrange; 1205 1206 bfd_put_16 (input_bfd, srel & 0xffff, contents); 1207 break; 1208 1209 case R_MSP430_16_PCREL_BYTE: 1210 contents += rel->r_offset; 1211 srel = (bfd_signed_vma) relocation; 1212 srel += rel->r_addend; 1213 srel -= rel->r_offset; 1214 /* Only branch instructions add 2 to the PC... */ 1215 srel -= (input_section->output_section->vma + 1216 input_section->output_offset); 1217 1218 bfd_put_16 (input_bfd, srel & 0xffff, contents); 1219 break; 1220 1221 case R_MSP430_16_BYTE: 1222 contents += rel->r_offset; 1223 srel = (bfd_signed_vma) relocation; 1224 srel += rel->r_addend; 1225 bfd_put_16 (input_bfd, srel & 0xffff, contents); 1226 break; 1227 1228 case R_MSP430_16: 1229 contents += rel->r_offset; 1230 srel = (bfd_signed_vma) relocation; 1231 srel += rel->r_addend; 1232 1233 if (srel & 1) 1234 return bfd_reloc_notsupported; 1235 1236 bfd_put_16 (input_bfd, srel & 0xffff, contents); 1237 break; 1238 1239 case R_MSP430_8: 1240 contents += rel->r_offset; 1241 srel = (bfd_signed_vma) relocation; 1242 srel += rel->r_addend; 1243 1244 bfd_put_8 (input_bfd, srel & 0xff, contents); 1245 break; 1246 1247 case R_MSP430_SYM_DIFF: 1248 /* Cache the input section and value. 1249 The offset is unreliable, since relaxation may 1250 have reduced the following reloc's offset. */ 1251 sym_diff_section = input_section; 1252 sym_diff_value = relocation; 1253 return bfd_reloc_ok; 1254 1255 default: 1256 r = _bfd_final_link_relocate (howto, input_bfd, input_section, 1257 contents, rel->r_offset, 1258 relocation, rel->r_addend); 1259 } 1260 1261 return r; 1262 } 1263 1264 /* Relocate an MSP430 ELF section. */ 1265 1266 static bfd_boolean 1267 elf32_msp430_relocate_section (bfd * output_bfd ATTRIBUTE_UNUSED, 1268 struct bfd_link_info * info, 1269 bfd * input_bfd, 1270 asection * input_section, 1271 bfd_byte * contents, 1272 Elf_Internal_Rela * relocs, 1273 Elf_Internal_Sym * local_syms, 1274 asection ** local_sections) 1275 { 1276 Elf_Internal_Shdr *symtab_hdr; 1277 struct elf_link_hash_entry **sym_hashes; 1278 Elf_Internal_Rela *rel; 1279 Elf_Internal_Rela *relend; 1280 1281 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr; 1282 sym_hashes = elf_sym_hashes (input_bfd); 1283 relend = relocs + input_section->reloc_count; 1284 1285 for (rel = relocs; rel < relend; rel++) 1286 { 1287 reloc_howto_type *howto; 1288 unsigned long r_symndx; 1289 Elf_Internal_Sym *sym; 1290 asection *sec; 1291 struct elf_link_hash_entry *h; 1292 bfd_vma relocation; 1293 bfd_reloc_status_type r; 1294 const char *name = NULL; 1295 int r_type; 1296 1297 r_type = ELF32_R_TYPE (rel->r_info); 1298 r_symndx = ELF32_R_SYM (rel->r_info); 1299 1300 if (uses_msp430x_relocs (input_bfd)) 1301 howto = elf_msp430x_howto_table + r_type; 1302 else 1303 howto = elf_msp430_howto_table + r_type; 1304 1305 h = NULL; 1306 sym = NULL; 1307 sec = NULL; 1308 1309 if (r_symndx < symtab_hdr->sh_info) 1310 { 1311 sym = local_syms + r_symndx; 1312 sec = local_sections[r_symndx]; 1313 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel); 1314 1315 name = bfd_elf_string_from_elf_section 1316 (input_bfd, symtab_hdr->sh_link, sym->st_name); 1317 name = (name == NULL || * name == 0) ? bfd_section_name (input_bfd, sec) : name; 1318 } 1319 else 1320 { 1321 bfd_boolean unresolved_reloc, warned, ignored; 1322 1323 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, 1324 r_symndx, symtab_hdr, sym_hashes, 1325 h, sec, relocation, 1326 unresolved_reloc, warned, ignored); 1327 name = h->root.root.string; 1328 } 1329 1330 if (sec != NULL && discarded_section (sec)) 1331 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section, 1332 rel, 1, relend, howto, 0, contents); 1333 1334 if (bfd_link_relocatable (info)) 1335 continue; 1336 1337 r = msp430_final_link_relocate (howto, input_bfd, input_section, 1338 contents, rel, relocation, info); 1339 1340 if (r != bfd_reloc_ok) 1341 { 1342 const char *msg = (const char *) NULL; 1343 1344 switch (r) 1345 { 1346 case bfd_reloc_overflow: 1347 (*info->callbacks->reloc_overflow) 1348 (info, (h ? &h->root : NULL), name, howto->name, 1349 (bfd_vma) 0, input_bfd, input_section, rel->r_offset); 1350 break; 1351 1352 case bfd_reloc_undefined: 1353 (*info->callbacks->undefined_symbol) 1354 (info, name, input_bfd, input_section, rel->r_offset, TRUE); 1355 break; 1356 1357 case bfd_reloc_outofrange: 1358 msg = _("internal error: branch/jump to an odd address detected"); 1359 break; 1360 1361 case bfd_reloc_notsupported: 1362 msg = _("internal error: unsupported relocation error"); 1363 break; 1364 1365 case bfd_reloc_dangerous: 1366 msg = _("internal error: dangerous relocation"); 1367 break; 1368 1369 default: 1370 msg = _("internal error: unknown error"); 1371 break; 1372 } 1373 1374 if (msg) 1375 (*info->callbacks->warning) (info, msg, name, input_bfd, 1376 input_section, rel->r_offset); 1377 } 1378 1379 } 1380 1381 return TRUE; 1382 } 1383 1384 /* The final processing done just before writing out a MSP430 ELF object 1385 file. This gets the MSP430 architecture right based on the machine 1386 number. */ 1387 1388 static void 1389 bfd_elf_msp430_final_write_processing (bfd * abfd, 1390 bfd_boolean linker ATTRIBUTE_UNUSED) 1391 { 1392 unsigned long val; 1393 1394 switch (bfd_get_mach (abfd)) 1395 { 1396 default: 1397 case bfd_mach_msp110: val = E_MSP430_MACH_MSP430x11x1; break; 1398 case bfd_mach_msp11: val = E_MSP430_MACH_MSP430x11; break; 1399 case bfd_mach_msp12: val = E_MSP430_MACH_MSP430x12; break; 1400 case bfd_mach_msp13: val = E_MSP430_MACH_MSP430x13; break; 1401 case bfd_mach_msp14: val = E_MSP430_MACH_MSP430x14; break; 1402 case bfd_mach_msp15: val = E_MSP430_MACH_MSP430x15; break; 1403 case bfd_mach_msp16: val = E_MSP430_MACH_MSP430x16; break; 1404 case bfd_mach_msp31: val = E_MSP430_MACH_MSP430x31; break; 1405 case bfd_mach_msp32: val = E_MSP430_MACH_MSP430x32; break; 1406 case bfd_mach_msp33: val = E_MSP430_MACH_MSP430x33; break; 1407 case bfd_mach_msp41: val = E_MSP430_MACH_MSP430x41; break; 1408 case bfd_mach_msp42: val = E_MSP430_MACH_MSP430x42; break; 1409 case bfd_mach_msp43: val = E_MSP430_MACH_MSP430x43; break; 1410 case bfd_mach_msp44: val = E_MSP430_MACH_MSP430x44; break; 1411 case bfd_mach_msp20: val = E_MSP430_MACH_MSP430x20; break; 1412 case bfd_mach_msp22: val = E_MSP430_MACH_MSP430x22; break; 1413 case bfd_mach_msp23: val = E_MSP430_MACH_MSP430x23; break; 1414 case bfd_mach_msp24: val = E_MSP430_MACH_MSP430x24; break; 1415 case bfd_mach_msp26: val = E_MSP430_MACH_MSP430x26; break; 1416 case bfd_mach_msp46: val = E_MSP430_MACH_MSP430x46; break; 1417 case bfd_mach_msp47: val = E_MSP430_MACH_MSP430x47; break; 1418 case bfd_mach_msp54: val = E_MSP430_MACH_MSP430x54; break; 1419 case bfd_mach_msp430x: val = E_MSP430_MACH_MSP430X; break; 1420 } 1421 1422 elf_elfheader (abfd)->e_machine = EM_MSP430; 1423 elf_elfheader (abfd)->e_flags &= ~EF_MSP430_MACH; 1424 elf_elfheader (abfd)->e_flags |= val; 1425 } 1426 1427 /* Set the right machine number. */ 1428 1429 static bfd_boolean 1430 elf32_msp430_object_p (bfd * abfd) 1431 { 1432 int e_set = bfd_mach_msp14; 1433 1434 if (elf_elfheader (abfd)->e_machine == EM_MSP430 1435 || elf_elfheader (abfd)->e_machine == EM_MSP430_OLD) 1436 { 1437 int e_mach = elf_elfheader (abfd)->e_flags & EF_MSP430_MACH; 1438 1439 switch (e_mach) 1440 { 1441 default: 1442 case E_MSP430_MACH_MSP430x11: e_set = bfd_mach_msp11; break; 1443 case E_MSP430_MACH_MSP430x11x1: e_set = bfd_mach_msp110; break; 1444 case E_MSP430_MACH_MSP430x12: e_set = bfd_mach_msp12; break; 1445 case E_MSP430_MACH_MSP430x13: e_set = bfd_mach_msp13; break; 1446 case E_MSP430_MACH_MSP430x14: e_set = bfd_mach_msp14; break; 1447 case E_MSP430_MACH_MSP430x15: e_set = bfd_mach_msp15; break; 1448 case E_MSP430_MACH_MSP430x16: e_set = bfd_mach_msp16; break; 1449 case E_MSP430_MACH_MSP430x31: e_set = bfd_mach_msp31; break; 1450 case E_MSP430_MACH_MSP430x32: e_set = bfd_mach_msp32; break; 1451 case E_MSP430_MACH_MSP430x33: e_set = bfd_mach_msp33; break; 1452 case E_MSP430_MACH_MSP430x41: e_set = bfd_mach_msp41; break; 1453 case E_MSP430_MACH_MSP430x42: e_set = bfd_mach_msp42; break; 1454 case E_MSP430_MACH_MSP430x43: e_set = bfd_mach_msp43; break; 1455 case E_MSP430_MACH_MSP430x44: e_set = bfd_mach_msp44; break; 1456 case E_MSP430_MACH_MSP430x20: e_set = bfd_mach_msp20; break; 1457 case E_MSP430_MACH_MSP430x22: e_set = bfd_mach_msp22; break; 1458 case E_MSP430_MACH_MSP430x23: e_set = bfd_mach_msp23; break; 1459 case E_MSP430_MACH_MSP430x24: e_set = bfd_mach_msp24; break; 1460 case E_MSP430_MACH_MSP430x26: e_set = bfd_mach_msp26; break; 1461 case E_MSP430_MACH_MSP430x46: e_set = bfd_mach_msp46; break; 1462 case E_MSP430_MACH_MSP430x47: e_set = bfd_mach_msp47; break; 1463 case E_MSP430_MACH_MSP430x54: e_set = bfd_mach_msp54; break; 1464 case E_MSP430_MACH_MSP430X: e_set = bfd_mach_msp430x; break; 1465 } 1466 } 1467 1468 return bfd_default_set_arch_mach (abfd, bfd_arch_msp430, e_set); 1469 } 1470 1471 /* These functions handle relaxing for the msp430. 1472 Relaxation required only in two cases: 1473 - Bad hand coding like jumps from one section to another or 1474 from file to file. 1475 - Sibling calls. This will affect only 'jump label' polymorph. Without 1476 relaxing this enlarges code by 2 bytes. Sibcalls implemented but 1477 do not work in gcc's port by the reason I do not know. 1478 - To convert out of range conditional jump instructions (found inside 1479 a function) into inverted jumps over an unconditional branch instruction. 1480 Anyway, if a relaxation required, user should pass -relax option to the 1481 linker. 1482 1483 There are quite a few relaxing opportunities available on the msp430: 1484 1485 ================================================================ 1486 1487 1. 3 words -> 1 word 1488 1489 eq == jeq label jne +4; br lab 1490 ne != jne label jeq +4; br lab 1491 lt < jl label jge +4; br lab 1492 ltu < jlo label lhs +4; br lab 1493 ge >= jge label jl +4; br lab 1494 geu >= jhs label jlo +4; br lab 1495 1496 2. 4 words -> 1 word 1497 1498 ltn < jn jn +2; jmp +4; br lab 1499 1500 3. 4 words -> 2 words 1501 1502 gt > jeq +2; jge label jeq +6; jl +4; br label 1503 gtu > jeq +2; jhs label jeq +6; jlo +4; br label 1504 1505 4. 4 words -> 2 words and 2 labels 1506 1507 leu <= jeq label; jlo label jeq +2; jhs +4; br label 1508 le <= jeq label; jl label jeq +2; jge +4; br label 1509 ================================================================= 1510 1511 codemap for first cases is (labels masked ): 1512 eq: 0x2002,0x4010,0x0000 -> 0x2400 1513 ne: 0x2402,0x4010,0x0000 -> 0x2000 1514 lt: 0x3402,0x4010,0x0000 -> 0x3800 1515 ltu: 0x2c02,0x4010,0x0000 -> 0x2800 1516 ge: 0x3802,0x4010,0x0000 -> 0x3400 1517 geu: 0x2802,0x4010,0x0000 -> 0x2c00 1518 1519 second case: 1520 ltn: 0x3001,0x3c02,0x4010,0x0000 -> 0x3000 1521 1522 third case: 1523 gt: 0x2403,0x3802,0x4010,0x0000 -> 0x2401,0x3400 1524 gtu: 0x2403,0x2802,0x4010,0x0000 -> 0x2401,0x2c00 1525 1526 fourth case: 1527 leu: 0x2401,0x2c02,0x4010,0x0000 -> 0x2400,0x2800 1528 le: 0x2401,0x3402,0x4010,0x0000 -> 0x2400,0x3800 1529 1530 Unspecified case :) 1531 jump: 0x4010,0x0000 -> 0x3c00. */ 1532 1533 #define NUMB_RELAX_CODES 12 1534 static struct rcodes_s 1535 { 1536 int f0, f1; /* From code. */ 1537 int t0, t1; /* To code. */ 1538 int labels; /* Position of labels: 1 - one label at first 1539 word, 2 - one at second word, 3 - two 1540 labels at both. */ 1541 int cdx; /* Words to match. */ 1542 int bs; /* Shrink bytes. */ 1543 int off; /* Offset from old label for new code. */ 1544 int ncl; /* New code length. */ 1545 } rcode[] = 1546 {/* lab,cdx,bs,off,ncl */ 1547 { 0x0000, 0x0000, 0x3c00, 0x0000, 1, 0, 2, 2, 2}, /* jump */ 1548 { 0x0000, 0x2002, 0x2400, 0x0000, 1, 1, 4, 4, 2}, /* eq */ 1549 { 0x0000, 0x2402, 0x2000, 0x0000, 1, 1, 4, 4, 2}, /* ne */ 1550 { 0x0000, 0x3402, 0x3800, 0x0000, 1, 1, 4, 4, 2}, /* lt */ 1551 { 0x0000, 0x2c02, 0x2800, 0x0000, 1, 1, 4, 4, 2}, /* ltu */ 1552 { 0x0000, 0x3802, 0x3400, 0x0000, 1, 1, 4, 4, 2}, /* ge */ 1553 { 0x0000, 0x2802, 0x2c00, 0x0000, 1, 1, 4, 4, 2}, /* geu */ 1554 { 0x3001, 0x3c02, 0x3000, 0x0000, 1, 2, 6, 6, 2}, /* ltn */ 1555 { 0x2403, 0x3802, 0x2401, 0x3400, 2, 2, 4, 6, 4}, /* gt */ 1556 { 0x2403, 0x2802, 0x2401, 0x2c00, 2, 2, 4, 6, 4}, /* gtu */ 1557 { 0x2401, 0x2c02, 0x2400, 0x2800, 3, 2, 4, 6, 4}, /* leu , 2 labels */ 1558 { 0x2401, 0x2c02, 0x2400, 0x2800, 3, 2, 4, 6, 4}, /* le , 2 labels */ 1559 { 0, 0, 0, 0, 0, 0, 0, 0, 0} 1560 }; 1561 1562 /* Return TRUE if a symbol exists at the given address. */ 1563 1564 static bfd_boolean 1565 msp430_elf_symbol_address_p (bfd * abfd, 1566 asection * sec, 1567 Elf_Internal_Sym * isym, 1568 bfd_vma addr) 1569 { 1570 Elf_Internal_Shdr *symtab_hdr; 1571 unsigned int sec_shndx; 1572 Elf_Internal_Sym *isymend; 1573 struct elf_link_hash_entry **sym_hashes; 1574 struct elf_link_hash_entry **end_hashes; 1575 unsigned int symcount; 1576 1577 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec); 1578 1579 /* Examine all the local symbols. */ 1580 symtab_hdr = &elf_tdata (abfd)->symtab_hdr; 1581 for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++) 1582 if (isym->st_shndx == sec_shndx && isym->st_value == addr) 1583 return TRUE; 1584 1585 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym) 1586 - symtab_hdr->sh_info); 1587 sym_hashes = elf_sym_hashes (abfd); 1588 end_hashes = sym_hashes + symcount; 1589 for (; sym_hashes < end_hashes; sym_hashes++) 1590 { 1591 struct elf_link_hash_entry *sym_hash = *sym_hashes; 1592 1593 if ((sym_hash->root.type == bfd_link_hash_defined 1594 || sym_hash->root.type == bfd_link_hash_defweak) 1595 && sym_hash->root.u.def.section == sec 1596 && sym_hash->root.u.def.value == addr) 1597 return TRUE; 1598 } 1599 1600 return FALSE; 1601 } 1602 1603 /* Adjust all local symbols defined as '.section + 0xXXXX' (.section has 1604 sec_shndx) referenced from current and other sections. */ 1605 1606 static bfd_boolean 1607 msp430_elf_relax_adjust_locals (bfd * abfd, asection * sec, bfd_vma addr, 1608 int count, unsigned int sec_shndx, 1609 bfd_vma toaddr) 1610 { 1611 Elf_Internal_Shdr *symtab_hdr; 1612 Elf_Internal_Rela *irel; 1613 Elf_Internal_Rela *irelend; 1614 Elf_Internal_Sym *isym; 1615 1616 irel = elf_section_data (sec)->relocs; 1617 if (irel == NULL) 1618 return TRUE; 1619 1620 irelend = irel + sec->reloc_count; 1621 symtab_hdr = & elf_tdata (abfd)->symtab_hdr; 1622 isym = (Elf_Internal_Sym *) symtab_hdr->contents; 1623 1624 for (;irel < irelend; irel++) 1625 { 1626 unsigned int sidx = ELF32_R_SYM(irel->r_info); 1627 Elf_Internal_Sym *lsym = isym + sidx; 1628 1629 /* Adjust symbols referenced by .sec+0xXX. */ 1630 if (irel->r_addend > addr && irel->r_addend < toaddr 1631 && sidx < symtab_hdr->sh_info 1632 && lsym->st_shndx == sec_shndx) 1633 irel->r_addend -= count; 1634 } 1635 1636 return TRUE; 1637 } 1638 1639 /* Delete some bytes from a section while relaxing. */ 1640 1641 static bfd_boolean 1642 msp430_elf_relax_delete_bytes (bfd * abfd, asection * sec, bfd_vma addr, 1643 int count) 1644 { 1645 Elf_Internal_Shdr *symtab_hdr; 1646 unsigned int sec_shndx; 1647 bfd_byte *contents; 1648 Elf_Internal_Rela *irel; 1649 Elf_Internal_Rela *irelend; 1650 bfd_vma toaddr; 1651 Elf_Internal_Sym *isym; 1652 Elf_Internal_Sym *isymend; 1653 struct elf_link_hash_entry **sym_hashes; 1654 struct elf_link_hash_entry **end_hashes; 1655 unsigned int symcount; 1656 asection *p; 1657 1658 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec); 1659 1660 contents = elf_section_data (sec)->this_hdr.contents; 1661 1662 toaddr = sec->size; 1663 1664 irel = elf_section_data (sec)->relocs; 1665 irelend = irel + sec->reloc_count; 1666 1667 /* Actually delete the bytes. */ 1668 memmove (contents + addr, contents + addr + count, 1669 (size_t) (toaddr - addr - count)); 1670 sec->size -= count; 1671 1672 /* Adjust all the relocs. */ 1673 symtab_hdr = & elf_tdata (abfd)->symtab_hdr; 1674 isym = (Elf_Internal_Sym *) symtab_hdr->contents; 1675 for (; irel < irelend; irel++) 1676 { 1677 /* Get the new reloc address. */ 1678 if ((irel->r_offset > addr && irel->r_offset < toaddr)) 1679 irel->r_offset -= count; 1680 } 1681 1682 for (p = abfd->sections; p != NULL; p = p->next) 1683 msp430_elf_relax_adjust_locals (abfd,p,addr,count,sec_shndx,toaddr); 1684 1685 /* Adjust the local symbols defined in this section. */ 1686 symtab_hdr = & elf_tdata (abfd)->symtab_hdr; 1687 isym = (Elf_Internal_Sym *) symtab_hdr->contents; 1688 for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++) 1689 { 1690 const char * name; 1691 1692 name = bfd_elf_string_from_elf_section 1693 (abfd, symtab_hdr->sh_link, isym->st_name); 1694 name = (name == NULL || * name == 0) ? bfd_section_name (abfd, sec) : name; 1695 1696 if (isym->st_shndx != sec_shndx) 1697 continue; 1698 1699 if (isym->st_value > addr 1700 && (isym->st_value < toaddr 1701 /* We also adjust a symbol at the end of the section if its name is 1702 on the list below. These symbols are used for debug info 1703 generation and they refer to the end of the current section, not 1704 the start of the next section. */ 1705 || (isym->st_value == toaddr 1706 && name != NULL 1707 && (CONST_STRNEQ (name, ".Letext") 1708 || CONST_STRNEQ (name, ".LFE"))))) 1709 { 1710 if (isym->st_value < addr + count) 1711 isym->st_value = addr; 1712 else 1713 isym->st_value -= count; 1714 } 1715 /* Adjust the function symbol's size as well. */ 1716 else if (ELF_ST_TYPE (isym->st_info) == STT_FUNC 1717 && isym->st_value + isym->st_size > addr 1718 && isym->st_value + isym->st_size < toaddr) 1719 isym->st_size -= count; 1720 } 1721 1722 /* Now adjust the global symbols defined in this section. */ 1723 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym) 1724 - symtab_hdr->sh_info); 1725 sym_hashes = elf_sym_hashes (abfd); 1726 end_hashes = sym_hashes + symcount; 1727 for (; sym_hashes < end_hashes; sym_hashes++) 1728 { 1729 struct elf_link_hash_entry *sym_hash = *sym_hashes; 1730 1731 if ((sym_hash->root.type == bfd_link_hash_defined 1732 || sym_hash->root.type == bfd_link_hash_defweak) 1733 && sym_hash->root.u.def.section == sec 1734 && sym_hash->root.u.def.value > addr 1735 && sym_hash->root.u.def.value < toaddr) 1736 { 1737 if (sym_hash->root.u.def.value < addr + count) 1738 sym_hash->root.u.def.value = addr; 1739 else 1740 sym_hash->root.u.def.value -= count; 1741 } 1742 /* Adjust the function symbol's size as well. */ 1743 else if (sym_hash->root.type == bfd_link_hash_defined 1744 && sym_hash->root.u.def.section == sec 1745 && sym_hash->type == STT_FUNC 1746 && sym_hash->root.u.def.value + sym_hash->size > addr 1747 && sym_hash->root.u.def.value + sym_hash->size < toaddr) 1748 sym_hash->size -= count; 1749 } 1750 1751 return TRUE; 1752 } 1753 1754 /* Insert two words into a section whilst relaxing. */ 1755 1756 static bfd_byte * 1757 msp430_elf_relax_add_two_words (bfd * abfd, asection * sec, bfd_vma addr, 1758 int word1, int word2) 1759 { 1760 Elf_Internal_Shdr *symtab_hdr; 1761 unsigned int sec_shndx; 1762 bfd_byte *contents; 1763 Elf_Internal_Rela *irel; 1764 Elf_Internal_Rela *irelend; 1765 Elf_Internal_Sym *isym; 1766 Elf_Internal_Sym *isymend; 1767 struct elf_link_hash_entry **sym_hashes; 1768 struct elf_link_hash_entry **end_hashes; 1769 unsigned int symcount; 1770 bfd_vma sec_end; 1771 asection *p; 1772 1773 contents = elf_section_data (sec)->this_hdr.contents; 1774 sec_end = sec->size; 1775 1776 /* Make space for the new words. */ 1777 contents = bfd_realloc (contents, sec_end + 4); 1778 memmove (contents + addr + 4, contents + addr, sec_end - addr); 1779 1780 /* Insert the new words. */ 1781 bfd_put_16 (abfd, word1, contents + addr); 1782 bfd_put_16 (abfd, word2, contents + addr + 2); 1783 1784 /* Update the section information. */ 1785 sec->size += 4; 1786 elf_section_data (sec)->this_hdr.contents = contents; 1787 1788 /* Adjust all the relocs. */ 1789 irel = elf_section_data (sec)->relocs; 1790 irelend = irel + sec->reloc_count; 1791 1792 for (; irel < irelend; irel++) 1793 if ((irel->r_offset >= addr && irel->r_offset < sec_end)) 1794 irel->r_offset += 4; 1795 1796 /* Adjust the local symbols defined in this section. */ 1797 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec); 1798 for (p = abfd->sections; p != NULL; p = p->next) 1799 msp430_elf_relax_adjust_locals (abfd, p, addr, -4, 1800 sec_shndx, sec_end); 1801 1802 /* Adjust the global symbols affected by the move. */ 1803 symtab_hdr = & elf_tdata (abfd)->symtab_hdr; 1804 isym = (Elf_Internal_Sym *) symtab_hdr->contents; 1805 for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++) 1806 if (isym->st_shndx == sec_shndx 1807 && isym->st_value >= addr && isym->st_value < sec_end) 1808 isym->st_value += 4; 1809 1810 /* Now adjust the global symbols defined in this section. */ 1811 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym) 1812 - symtab_hdr->sh_info); 1813 sym_hashes = elf_sym_hashes (abfd); 1814 end_hashes = sym_hashes + symcount; 1815 for (; sym_hashes < end_hashes; sym_hashes++) 1816 { 1817 struct elf_link_hash_entry *sym_hash = *sym_hashes; 1818 1819 if ((sym_hash->root.type == bfd_link_hash_defined 1820 || sym_hash->root.type == bfd_link_hash_defweak) 1821 && sym_hash->root.u.def.section == sec 1822 && sym_hash->root.u.def.value >= addr 1823 && sym_hash->root.u.def.value < sec_end) 1824 sym_hash->root.u.def.value += 4; 1825 } 1826 1827 return contents; 1828 } 1829 1830 static bfd_boolean 1831 msp430_elf_relax_section (bfd * abfd, asection * sec, 1832 struct bfd_link_info * link_info, 1833 bfd_boolean * again) 1834 { 1835 Elf_Internal_Shdr * symtab_hdr; 1836 Elf_Internal_Rela * internal_relocs; 1837 Elf_Internal_Rela * irel; 1838 Elf_Internal_Rela * irelend; 1839 bfd_byte * contents = NULL; 1840 Elf_Internal_Sym * isymbuf = NULL; 1841 1842 /* Assume nothing changes. */ 1843 *again = FALSE; 1844 1845 /* We don't have to do anything for a relocatable link, if 1846 this section does not have relocs, or if this is not a 1847 code section. */ 1848 if (bfd_link_relocatable (link_info) 1849 || (sec->flags & SEC_RELOC) == 0 1850 || sec->reloc_count == 0 || (sec->flags & SEC_CODE) == 0) 1851 return TRUE; 1852 1853 symtab_hdr = & elf_tdata (abfd)->symtab_hdr; 1854 1855 /* Get a copy of the native relocations. */ 1856 internal_relocs = 1857 _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, link_info->keep_memory); 1858 if (internal_relocs == NULL) 1859 goto error_return; 1860 1861 /* Walk through them looking for relaxing opportunities. */ 1862 irelend = internal_relocs + sec->reloc_count; 1863 1864 /* Do code size growing relocs first. */ 1865 for (irel = internal_relocs; irel < irelend; irel++) 1866 { 1867 bfd_vma symval; 1868 1869 /* If this isn't something that can be relaxed, then ignore 1870 this reloc. */ 1871 if (uses_msp430x_relocs (abfd) 1872 && ELF32_R_TYPE (irel->r_info) == (int) R_MSP430X_10_PCREL) 1873 ; 1874 else if (! uses_msp430x_relocs (abfd) 1875 && ELF32_R_TYPE (irel->r_info) == (int) R_MSP430_10_PCREL) 1876 ; 1877 else 1878 continue; 1879 1880 /* Get the section contents if we haven't done so already. */ 1881 if (contents == NULL) 1882 { 1883 /* Get cached copy if it exists. */ 1884 if (elf_section_data (sec)->this_hdr.contents != NULL) 1885 contents = elf_section_data (sec)->this_hdr.contents; 1886 else if (! bfd_malloc_and_get_section (abfd, sec, &contents)) 1887 goto error_return; 1888 } 1889 1890 /* Read this BFD's local symbols if we haven't done so already. */ 1891 if (isymbuf == NULL && symtab_hdr->sh_info != 0) 1892 { 1893 isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents; 1894 if (isymbuf == NULL) 1895 isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr, 1896 symtab_hdr->sh_info, 0, 1897 NULL, NULL, NULL); 1898 if (isymbuf == NULL) 1899 goto error_return; 1900 } 1901 1902 /* Get the value of the symbol referred to by the reloc. */ 1903 if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info) 1904 { 1905 /* A local symbol. */ 1906 Elf_Internal_Sym *isym; 1907 asection *sym_sec; 1908 1909 isym = isymbuf + ELF32_R_SYM (irel->r_info); 1910 if (isym->st_shndx == SHN_UNDEF) 1911 sym_sec = bfd_und_section_ptr; 1912 else if (isym->st_shndx == SHN_ABS) 1913 sym_sec = bfd_abs_section_ptr; 1914 else if (isym->st_shndx == SHN_COMMON) 1915 sym_sec = bfd_com_section_ptr; 1916 else 1917 sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx); 1918 symval = (isym->st_value 1919 + sym_sec->output_section->vma + sym_sec->output_offset); 1920 } 1921 else 1922 { 1923 unsigned long indx; 1924 struct elf_link_hash_entry *h; 1925 1926 /* An external symbol. */ 1927 indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info; 1928 h = elf_sym_hashes (abfd)[indx]; 1929 BFD_ASSERT (h != NULL); 1930 1931 if (h->root.type != bfd_link_hash_defined 1932 && h->root.type != bfd_link_hash_defweak) 1933 /* This appears to be a reference to an undefined 1934 symbol. Just ignore it--it will be caught by the 1935 regular reloc processing. */ 1936 continue; 1937 1938 symval = (h->root.u.def.value 1939 + h->root.u.def.section->output_section->vma 1940 + h->root.u.def.section->output_offset); 1941 } 1942 1943 /* For simplicity of coding, we are going to modify the section 1944 contents, the section relocs, and the BFD symbol table. We 1945 must tell the rest of the code not to free up this 1946 information. It would be possible to instead create a table 1947 of changes which have to be made, as is done in coff-mips.c; 1948 that would be more work, but would require less memory when 1949 the linker is run. */ 1950 1951 bfd_signed_vma value = symval; 1952 int opcode; 1953 1954 /* Compute the value that will be relocated. */ 1955 value += irel->r_addend; 1956 /* Convert to PC relative. */ 1957 value -= (sec->output_section->vma + sec->output_offset); 1958 value -= irel->r_offset; 1959 value -= 2; 1960 /* Scale. */ 1961 value >>= 1; 1962 1963 /* If it is in range then no modifications are needed. */ 1964 if (value >= -512 && value <= 511) 1965 continue; 1966 1967 /* Get the opcode. */ 1968 opcode = bfd_get_16 (abfd, contents + irel->r_offset); 1969 1970 /* Compute the new opcode. We are going to convert: 1971 J<cond> label 1972 into: 1973 J<inv-cond> 1f 1974 BR[A] #label 1975 1: */ 1976 switch (opcode & 0xfc00) 1977 { 1978 case 0x3800: opcode = 0x3402; break; /* Jl -> Jge +2 */ 1979 case 0x3400: opcode = 0x3802; break; /* Jge -> Jl +2 */ 1980 case 0x2c00: opcode = 0x2802; break; /* Jhs -> Jlo +2 */ 1981 case 0x2800: opcode = 0x2c02; break; /* Jlo -> Jhs +2 */ 1982 case 0x2400: opcode = 0x2002; break; /* Jeq -> Jne +2 */ 1983 case 0x2000: opcode = 0x2402; break; /* jne -> Jeq +2 */ 1984 case 0x3000: /* jn */ 1985 /* There is no direct inverse of the Jn insn. 1986 FIXME: we could do this as: 1987 Jn 1f 1988 br 2f 1989 1: br label 1990 2: */ 1991 continue; 1992 default: 1993 /* Not a conditional branch instruction. */ 1994 /* fprintf (stderr, "unrecog: %x\n", opcode); */ 1995 continue; 1996 } 1997 1998 /* Note that we've changed the relocs, section contents, etc. */ 1999 elf_section_data (sec)->relocs = internal_relocs; 2000 elf_section_data (sec)->this_hdr.contents = contents; 2001 symtab_hdr->contents = (unsigned char *) isymbuf; 2002 2003 /* Install the new opcode. */ 2004 bfd_put_16 (abfd, opcode, contents + irel->r_offset); 2005 2006 /* Insert the new branch instruction. */ 2007 if (uses_msp430x_relocs (abfd)) 2008 { 2009 /* Insert an absolute branch (aka MOVA) instruction. */ 2010 contents = msp430_elf_relax_add_two_words 2011 (abfd, sec, irel->r_offset + 2, 0x0080, 0x0000); 2012 2013 /* Update the relocation to point to the inserted branch 2014 instruction. Note - we are changing a PC-relative reloc 2015 into an absolute reloc, but this is OK because we have 2016 arranged with the assembler to have the reloc's value be 2017 a (local) symbol, not a section+offset value. */ 2018 irel->r_offset += 2; 2019 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), 2020 R_MSP430X_ABS20_ADR_SRC); 2021 } 2022 else 2023 { 2024 contents = msp430_elf_relax_add_two_words 2025 (abfd, sec, irel->r_offset + 2, 0x4030, 0x0000); 2026 2027 /* See comment above about converting a 10-bit PC-rel 2028 relocation into a 16-bit absolute relocation. */ 2029 irel->r_offset += 4; 2030 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), 2031 R_MSP430_16); 2032 } 2033 2034 /* Growing the section may mean that other 2035 conditional branches need to be fixed. */ 2036 *again = TRUE; 2037 } 2038 2039 for (irel = internal_relocs; irel < irelend; irel++) 2040 { 2041 bfd_vma symval; 2042 2043 /* Get the section contents if we haven't done so already. */ 2044 if (contents == NULL) 2045 { 2046 /* Get cached copy if it exists. */ 2047 if (elf_section_data (sec)->this_hdr.contents != NULL) 2048 contents = elf_section_data (sec)->this_hdr.contents; 2049 else if (! bfd_malloc_and_get_section (abfd, sec, &contents)) 2050 goto error_return; 2051 } 2052 2053 /* Read this BFD's local symbols if we haven't done so already. */ 2054 if (isymbuf == NULL && symtab_hdr->sh_info != 0) 2055 { 2056 isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents; 2057 if (isymbuf == NULL) 2058 isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr, 2059 symtab_hdr->sh_info, 0, 2060 NULL, NULL, NULL); 2061 if (isymbuf == NULL) 2062 goto error_return; 2063 } 2064 2065 /* Get the value of the symbol referred to by the reloc. */ 2066 if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info) 2067 { 2068 /* A local symbol. */ 2069 Elf_Internal_Sym *isym; 2070 asection *sym_sec; 2071 2072 isym = isymbuf + ELF32_R_SYM (irel->r_info); 2073 if (isym->st_shndx == SHN_UNDEF) 2074 sym_sec = bfd_und_section_ptr; 2075 else if (isym->st_shndx == SHN_ABS) 2076 sym_sec = bfd_abs_section_ptr; 2077 else if (isym->st_shndx == SHN_COMMON) 2078 sym_sec = bfd_com_section_ptr; 2079 else 2080 sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx); 2081 symval = (isym->st_value 2082 + sym_sec->output_section->vma + sym_sec->output_offset); 2083 } 2084 else 2085 { 2086 unsigned long indx; 2087 struct elf_link_hash_entry *h; 2088 2089 /* An external symbol. */ 2090 indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info; 2091 h = elf_sym_hashes (abfd)[indx]; 2092 BFD_ASSERT (h != NULL); 2093 2094 if (h->root.type != bfd_link_hash_defined 2095 && h->root.type != bfd_link_hash_defweak) 2096 /* This appears to be a reference to an undefined 2097 symbol. Just ignore it--it will be caught by the 2098 regular reloc processing. */ 2099 continue; 2100 2101 symval = (h->root.u.def.value 2102 + h->root.u.def.section->output_section->vma 2103 + h->root.u.def.section->output_offset); 2104 } 2105 2106 /* For simplicity of coding, we are going to modify the section 2107 contents, the section relocs, and the BFD symbol table. We 2108 must tell the rest of the code not to free up this 2109 information. It would be possible to instead create a table 2110 of changes which have to be made, as is done in coff-mips.c; 2111 that would be more work, but would require less memory when 2112 the linker is run. */ 2113 2114 /* Try to turn a 16bit pc-relative branch into a 10bit pc-relative 2115 branch. */ 2116 /* Paranoia? paranoia... */ 2117 if (! uses_msp430x_relocs (abfd) 2118 && ELF32_R_TYPE (irel->r_info) == (int) R_MSP430_RL_PCREL) 2119 { 2120 bfd_vma value = symval; 2121 2122 /* Deal with pc-relative gunk. */ 2123 value -= (sec->output_section->vma + sec->output_offset); 2124 value -= irel->r_offset; 2125 value += irel->r_addend; 2126 2127 /* See if the value will fit in 10 bits, note the high value is 2128 1016 as the target will be two bytes closer if we are 2129 able to relax. */ 2130 if ((long) value < 1016 && (long) value > -1016) 2131 { 2132 int code0 = 0, code1 = 0, code2 = 0; 2133 int i; 2134 struct rcodes_s *rx; 2135 2136 /* Get the opcode. */ 2137 if (irel->r_offset >= 6) 2138 code0 = bfd_get_16 (abfd, contents + irel->r_offset - 6); 2139 2140 if (irel->r_offset >= 4) 2141 code1 = bfd_get_16 (abfd, contents + irel->r_offset - 4); 2142 2143 code2 = bfd_get_16 (abfd, contents + irel->r_offset - 2); 2144 2145 if (code2 != 0x4010) 2146 continue; 2147 2148 /* Check r4 and r3. */ 2149 for (i = NUMB_RELAX_CODES - 1; i >= 0; i--) 2150 { 2151 rx = &rcode[i]; 2152 if (rx->cdx == 2 && rx->f0 == code0 && rx->f1 == code1) 2153 break; 2154 else if (rx->cdx == 1 && rx->f1 == code1) 2155 break; 2156 else if (rx->cdx == 0) /* This is an unconditional jump. */ 2157 break; 2158 } 2159 2160 /* Check labels: 2161 .Label0: ; we do not care about this label 2162 jeq +6 2163 .Label1: ; make sure there is no label here 2164 jl +4 2165 .Label2: ; make sure there is no label here 2166 br .Label_dst 2167 2168 So, if there is .Label1 or .Label2 we cannot relax this code. 2169 This actually should not happen, cause for relaxable 2170 instructions we use RL_PCREL reloc instead of 16_PCREL. 2171 Will change this in the future. */ 2172 2173 if (rx->cdx > 0 2174 && msp430_elf_symbol_address_p (abfd, sec, isymbuf, 2175 irel->r_offset - 2)) 2176 continue; 2177 if (rx->cdx > 1 2178 && msp430_elf_symbol_address_p (abfd, sec, isymbuf, 2179 irel->r_offset - 4)) 2180 continue; 2181 2182 /* Note that we've changed the relocs, section contents, etc. */ 2183 elf_section_data (sec)->relocs = internal_relocs; 2184 elf_section_data (sec)->this_hdr.contents = contents; 2185 symtab_hdr->contents = (unsigned char *) isymbuf; 2186 2187 /* Fix the relocation's type. */ 2188 if (uses_msp430x_relocs (abfd)) 2189 { 2190 if (rx->labels == 3) /* Handle special cases. */ 2191 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), 2192 R_MSP430X_2X_PCREL); 2193 else 2194 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), 2195 R_MSP430X_10_PCREL); 2196 } 2197 else 2198 { 2199 if (rx->labels == 3) /* Handle special cases. */ 2200 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), 2201 R_MSP430_2X_PCREL); 2202 else 2203 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), 2204 R_MSP430_10_PCREL); 2205 } 2206 2207 /* Fix the opcode right way. */ 2208 bfd_put_16 (abfd, rx->t0, contents + irel->r_offset - rx->off); 2209 if (rx->t1) 2210 bfd_put_16 (abfd, rx->t1, 2211 contents + irel->r_offset - rx->off + 2); 2212 2213 /* Delete bytes. */ 2214 if (!msp430_elf_relax_delete_bytes (abfd, sec, 2215 irel->r_offset - rx->off + 2216 rx->ncl, rx->bs)) 2217 goto error_return; 2218 2219 /* Handle unconditional jumps. */ 2220 if (rx->cdx == 0) 2221 irel->r_offset -= 2; 2222 2223 /* That will change things, so, we should relax again. 2224 Note that this is not required, and it may be slow. */ 2225 *again = TRUE; 2226 } 2227 } 2228 2229 /* Try to turn a 16-bit absolute branch into a 10-bit pc-relative 2230 branch. */ 2231 if ((uses_msp430x_relocs (abfd) 2232 && ELF32_R_TYPE (irel->r_info) == R_MSP430X_ABS16) 2233 || (! uses_msp430x_relocs (abfd) 2234 && ELF32_R_TYPE (irel->r_info) == R_MSP430_16)) 2235 { 2236 bfd_vma value = symval; 2237 2238 value -= (sec->output_section->vma + sec->output_offset); 2239 value -= irel->r_offset; 2240 value += irel->r_addend; 2241 2242 /* See if the value will fit in 10 bits, note the high value is 2243 1016 as the target will be two bytes closer if we are 2244 able to relax. */ 2245 if ((long) value < 1016 && (long) value > -1016) 2246 { 2247 int code2; 2248 2249 /* Get the opcode. */ 2250 code2 = bfd_get_16 (abfd, contents + irel->r_offset - 2); 2251 if (code2 != 0x4030) 2252 continue; 2253 /* FIXME: check r4 and r3 ? */ 2254 /* FIXME: Handle 0x4010 as well ? */ 2255 2256 /* Note that we've changed the relocs, section contents, etc. */ 2257 elf_section_data (sec)->relocs = internal_relocs; 2258 elf_section_data (sec)->this_hdr.contents = contents; 2259 symtab_hdr->contents = (unsigned char *) isymbuf; 2260 2261 /* Fix the relocation's type. */ 2262 if (uses_msp430x_relocs (abfd)) 2263 { 2264 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), 2265 R_MSP430X_10_PCREL); 2266 } 2267 else 2268 { 2269 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), 2270 R_MSP430_10_PCREL); 2271 } 2272 2273 /* Fix the opcode right way. */ 2274 bfd_put_16 (abfd, 0x3c00, contents + irel->r_offset - 2); 2275 irel->r_offset -= 2; 2276 2277 /* Delete bytes. */ 2278 if (!msp430_elf_relax_delete_bytes (abfd, sec, 2279 irel->r_offset + 2, 2)) 2280 goto error_return; 2281 2282 /* That will change things, so, we should relax again. 2283 Note that this is not required, and it may be slow. */ 2284 *again = TRUE; 2285 } 2286 } 2287 } 2288 2289 if (isymbuf != NULL && symtab_hdr->contents != (unsigned char *) isymbuf) 2290 { 2291 if (!link_info->keep_memory) 2292 free (isymbuf); 2293 else 2294 { 2295 /* Cache the symbols for elf_link_input_bfd. */ 2296 symtab_hdr->contents = (unsigned char *) isymbuf; 2297 } 2298 } 2299 2300 if (contents != NULL 2301 && elf_section_data (sec)->this_hdr.contents != contents) 2302 { 2303 if (!link_info->keep_memory) 2304 free (contents); 2305 else 2306 { 2307 /* Cache the section contents for elf_link_input_bfd. */ 2308 elf_section_data (sec)->this_hdr.contents = contents; 2309 } 2310 } 2311 2312 if (internal_relocs != NULL 2313 && elf_section_data (sec)->relocs != internal_relocs) 2314 free (internal_relocs); 2315 2316 return TRUE; 2317 2318 error_return: 2319 if (isymbuf != NULL && symtab_hdr->contents != (unsigned char *) isymbuf) 2320 free (isymbuf); 2321 if (contents != NULL 2322 && elf_section_data (sec)->this_hdr.contents != contents) 2323 free (contents); 2324 if (internal_relocs != NULL 2325 && elf_section_data (sec)->relocs != internal_relocs) 2326 free (internal_relocs); 2327 2328 return FALSE; 2329 } 2330 2331 /* Handle an MSP430 specific section when reading an object file. 2332 This is called when bfd_section_from_shdr finds a section with 2333 an unknown type. */ 2334 2335 static bfd_boolean 2336 elf32_msp430_section_from_shdr (bfd *abfd, 2337 Elf_Internal_Shdr * hdr, 2338 const char *name, 2339 int shindex) 2340 { 2341 switch (hdr->sh_type) 2342 { 2343 case SHT_MSP430_SEC_FLAGS: 2344 case SHT_MSP430_SYM_ALIASES: 2345 case SHT_MSP430_ATTRIBUTES: 2346 return _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex); 2347 default: 2348 return FALSE; 2349 } 2350 } 2351 2352 static bfd_boolean 2353 elf32_msp430_obj_attrs_handle_unknown (bfd *abfd, int tag) 2354 { 2355 _bfd_error_handler 2356 /* xgettext:c-format */ 2357 (_("warning: %pB: unknown MSPABI object attribute %d"), 2358 abfd, tag); 2359 return TRUE; 2360 } 2361 2362 /* Determine whether an object attribute tag takes an integer, a 2363 string or both. */ 2364 2365 static int 2366 elf32_msp430_obj_attrs_arg_type (int tag) 2367 { 2368 if (tag == Tag_compatibility) 2369 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL; 2370 2371 if (tag < 32) 2372 return ATTR_TYPE_FLAG_INT_VAL; 2373 2374 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL; 2375 } 2376 2377 static inline const char * 2378 isa_type (int isa) 2379 { 2380 switch (isa) 2381 { 2382 case 1: return "MSP430"; 2383 case 2: return "MSP430X"; 2384 default: return "unknown"; 2385 } 2386 } 2387 2388 static inline const char * 2389 code_model (int model) 2390 { 2391 switch (model) 2392 { 2393 case 1: return "small"; 2394 case 2: return "large"; 2395 default: return "unknown"; 2396 } 2397 } 2398 2399 static inline const char * 2400 data_model (int model) 2401 { 2402 switch (model) 2403 { 2404 case 1: return "small"; 2405 case 2: return "large"; 2406 case 3: return "restricted large"; 2407 default: return "unknown"; 2408 } 2409 } 2410 2411 /* Merge MSPABI object attributes from IBFD into OBFD. 2412 Raise an error if there are conflicting attributes. */ 2413 2414 static bfd_boolean 2415 elf32_msp430_merge_mspabi_attributes (bfd *ibfd, struct bfd_link_info *info) 2416 { 2417 bfd *obfd = info->output_bfd; 2418 obj_attribute *in_attr; 2419 obj_attribute *out_attr; 2420 bfd_boolean result = TRUE; 2421 static bfd * first_input_bfd = NULL; 2422 2423 /* Skip linker created files. */ 2424 if (ibfd->flags & BFD_LINKER_CREATED) 2425 return TRUE; 2426 2427 /* If this is the first real object just copy the attributes. */ 2428 if (!elf_known_obj_attributes_proc (obfd)[0].i) 2429 { 2430 _bfd_elf_copy_obj_attributes (ibfd, obfd); 2431 2432 out_attr = elf_known_obj_attributes_proc (obfd); 2433 2434 /* Use the Tag_null value to indicate that 2435 the attributes have been initialized. */ 2436 out_attr[0].i = 1; 2437 2438 first_input_bfd = ibfd; 2439 return TRUE; 2440 } 2441 2442 in_attr = elf_known_obj_attributes_proc (ibfd); 2443 out_attr = elf_known_obj_attributes_proc (obfd); 2444 2445 /* The ISAs must be the same. */ 2446 if (in_attr[OFBA_MSPABI_Tag_ISA].i != out_attr[OFBA_MSPABI_Tag_ISA].i) 2447 { 2448 _bfd_error_handler 2449 /* xgettext:c-format */ 2450 (_("error: %pB uses %s instructions but %pB uses %s"), 2451 ibfd, isa_type (in_attr[OFBA_MSPABI_Tag_ISA].i), 2452 first_input_bfd, isa_type (out_attr[OFBA_MSPABI_Tag_ISA].i)); 2453 result = FALSE; 2454 } 2455 2456 /* The code models must be the same. */ 2457 if (in_attr[OFBA_MSPABI_Tag_Code_Model].i != 2458 out_attr[OFBA_MSPABI_Tag_Code_Model].i) 2459 { 2460 _bfd_error_handler 2461 /* xgettext:c-format */ 2462 (_("error: %pB uses the %s code model whereas %pB uses the %s code model"), 2463 ibfd, code_model (in_attr[OFBA_MSPABI_Tag_Code_Model].i), 2464 first_input_bfd, code_model (out_attr[OFBA_MSPABI_Tag_Code_Model].i)); 2465 result = FALSE; 2466 } 2467 2468 /* The large code model is only supported by the MSP430X. */ 2469 if (in_attr[OFBA_MSPABI_Tag_Code_Model].i == 2 2470 && out_attr[OFBA_MSPABI_Tag_ISA].i != 2) 2471 { 2472 _bfd_error_handler 2473 /* xgettext:c-format */ 2474 (_("error: %pB uses the large code model but %pB uses MSP430 instructions"), 2475 ibfd, first_input_bfd); 2476 result = FALSE; 2477 } 2478 2479 /* The data models must be the same. */ 2480 if (in_attr[OFBA_MSPABI_Tag_Data_Model].i != 2481 out_attr[OFBA_MSPABI_Tag_Data_Model].i) 2482 { 2483 _bfd_error_handler 2484 /* xgettext:c-format */ 2485 (_("error: %pB uses the %s data model whereas %pB uses the %s data model"), 2486 ibfd, data_model (in_attr[OFBA_MSPABI_Tag_Data_Model].i), 2487 first_input_bfd, data_model (out_attr[OFBA_MSPABI_Tag_Data_Model].i)); 2488 result = FALSE; 2489 } 2490 2491 /* The small code model requires the use of the small data model. */ 2492 if (in_attr[OFBA_MSPABI_Tag_Code_Model].i == 1 2493 && out_attr[OFBA_MSPABI_Tag_Data_Model].i != 1) 2494 { 2495 _bfd_error_handler 2496 /* xgettext:c-format */ 2497 (_("error: %pB uses the small code model but %pB uses the %s data model"), 2498 ibfd, first_input_bfd, 2499 data_model (out_attr[OFBA_MSPABI_Tag_Data_Model].i)); 2500 result = FALSE; 2501 } 2502 2503 /* The large data models are only supported by the MSP430X. */ 2504 if (in_attr[OFBA_MSPABI_Tag_Data_Model].i > 1 2505 && out_attr[OFBA_MSPABI_Tag_ISA].i != 2) 2506 { 2507 _bfd_error_handler 2508 /* xgettext:c-format */ 2509 (_("error: %pB uses the %s data model but %pB only uses MSP430 instructions"), 2510 ibfd, data_model (in_attr[OFBA_MSPABI_Tag_Data_Model].i), 2511 first_input_bfd); 2512 result = FALSE; 2513 } 2514 2515 return result; 2516 } 2517 2518 /* Merge backend specific data from an object file to the output 2519 object file when linking. */ 2520 2521 static bfd_boolean 2522 elf32_msp430_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info) 2523 { 2524 bfd *obfd = info->output_bfd; 2525 /* Make sure that the machine number reflects the most 2526 advanced version of the MSP architecture required. */ 2527 #define max(a,b) ((a) > (b) ? (a) : (b)) 2528 if (bfd_get_mach (ibfd) != bfd_get_mach (obfd)) 2529 bfd_default_set_arch_mach (obfd, bfd_get_arch (obfd), 2530 max (bfd_get_mach (ibfd), bfd_get_mach (obfd))); 2531 #undef max 2532 2533 return elf32_msp430_merge_mspabi_attributes (ibfd, info); 2534 } 2535 2536 static bfd_boolean 2537 msp430_elf_is_target_special_symbol (bfd *abfd, asymbol *sym) 2538 { 2539 return _bfd_elf_is_local_label_name (abfd, sym->name); 2540 } 2541 2542 static bfd_boolean 2543 uses_large_model (bfd *abfd) 2544 { 2545 obj_attribute * attr; 2546 2547 if (abfd->flags & BFD_LINKER_CREATED) 2548 return FALSE; 2549 2550 attr = elf_known_obj_attributes_proc (abfd); 2551 if (attr == NULL) 2552 return FALSE; 2553 2554 return attr[OFBA_MSPABI_Tag_Code_Model].i == 2; 2555 } 2556 2557 static unsigned int 2558 elf32_msp430_eh_frame_address_size (bfd *abfd, 2559 const asection *sec ATTRIBUTE_UNUSED) 2560 { 2561 return uses_large_model (abfd) ? 4 : 2; 2562 } 2563 2564 /* This is gross. The MSP430 EABI says that (sec 11.5): 2565 2566 "An implementation may choose to use Rel or Rela 2567 type relocations for other relocations." 2568 2569 But it also says that: 2570 2571 "Certain relocations are identified as Rela only. [snip] 2572 Where Rela is specified, an implementation must honor 2573 this requirement." 2574 2575 There is one relocation marked as requiring RELA - R_MSP430_ABS_HI16 - but 2576 to keep things simple we choose to use RELA relocations throughout. The 2577 problem is that the TI compiler generates REL relocations, so we have to 2578 be able to accept those as well. */ 2579 2580 #define elf_backend_may_use_rel_p 1 2581 #define elf_backend_may_use_rela_p 1 2582 #define elf_backend_default_use_rela_p 1 2583 2584 #undef elf_backend_obj_attrs_vendor 2585 #define elf_backend_obj_attrs_vendor "mspabi" 2586 #undef elf_backend_obj_attrs_section 2587 #define elf_backend_obj_attrs_section ".MSP430.attributes" 2588 #undef elf_backend_obj_attrs_section_type 2589 #define elf_backend_obj_attrs_section_type SHT_MSP430_ATTRIBUTES 2590 #define elf_backend_section_from_shdr elf32_msp430_section_from_shdr 2591 #define elf_backend_obj_attrs_handle_unknown elf32_msp430_obj_attrs_handle_unknown 2592 #undef elf_backend_obj_attrs_arg_type 2593 #define elf_backend_obj_attrs_arg_type elf32_msp430_obj_attrs_arg_type 2594 #define bfd_elf32_bfd_merge_private_bfd_data elf32_msp430_merge_private_bfd_data 2595 #define elf_backend_eh_frame_address_size elf32_msp430_eh_frame_address_size 2596 2597 #define ELF_ARCH bfd_arch_msp430 2598 #define ELF_MACHINE_CODE EM_MSP430 2599 #define ELF_MACHINE_ALT1 EM_MSP430_OLD 2600 #define ELF_MAXPAGESIZE 4 2601 #define ELF_OSABI ELFOSABI_STANDALONE 2602 2603 #define TARGET_LITTLE_SYM msp430_elf32_vec 2604 #define TARGET_LITTLE_NAME "elf32-msp430" 2605 2606 #define elf_info_to_howto msp430_info_to_howto_rela 2607 #define elf_info_to_howto_rel NULL 2608 #define elf_backend_relocate_section elf32_msp430_relocate_section 2609 #define elf_backend_check_relocs elf32_msp430_check_relocs 2610 #define elf_backend_can_gc_sections 1 2611 #define elf_backend_final_write_processing bfd_elf_msp430_final_write_processing 2612 #define elf_backend_object_p elf32_msp430_object_p 2613 #define bfd_elf32_bfd_relax_section msp430_elf_relax_section 2614 #define bfd_elf32_bfd_is_target_special_symbol msp430_elf_is_target_special_symbol 2615 2616 #undef elf32_bed 2617 #define elf32_bed elf32_msp430_bed 2618 2619 #include "elf32-target.h" 2620 2621 /* The TI compiler sets the OSABI field to ELFOSABI_NONE. */ 2622 #undef TARGET_LITTLE_SYM 2623 #define TARGET_LITTLE_SYM msp430_elf32_ti_vec 2624 2625 #undef elf32_bed 2626 #define elf32_bed elf32_msp430_ti_bed 2627 2628 #undef ELF_OSABI 2629 #define ELF_OSABI ELFOSABI_NONE 2630 2631 static const struct bfd_elf_special_section msp430_ti_elf_special_sections[] = 2632 { 2633 /* prefix, prefix_length, suffix_len, type, attributes. */ 2634 { STRING_COMMA_LEN (".TI.symbol.alias"), 0, SHT_MSP430_SYM_ALIASES, 0 }, 2635 { STRING_COMMA_LEN (".TI.section.flags"), 0, SHT_MSP430_SEC_FLAGS, 0 }, 2636 { STRING_COMMA_LEN ("_TI_build_attrib"), 0, SHT_MSP430_ATTRIBUTES, 0 }, 2637 { NULL, 0, 0, 0, 0 } 2638 }; 2639 2640 #undef elf_backend_special_sections 2641 #define elf_backend_special_sections msp430_ti_elf_special_sections 2642 2643 #include "elf32-target.h" 2644
Indexes created Sun Mar 01 05:31:48 UTC 2026