tc-d10v.c revision 1.1.1.6
1 /* tc-d10v.c -- Assembler code for the Mitsubishi D10V 2 Copyright (C) 1996-2022 Free Software Foundation, Inc. 3 4 This file is part of GAS, the GNU Assembler. 5 6 GAS is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GAS is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GAS; see the file COPYING. If not, write to 18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, 19 Boston, MA 02110-1301, USA. */ 20 21 #include "as.h" 22 #include "safe-ctype.h" 23 #include "subsegs.h" 24 #include "opcode/d10v.h" 25 #include "elf/ppc.h" 26 #include "dwarf2dbg.h" 27 28 const char comment_chars[] = ";"; 29 const char line_comment_chars[] = "#"; 30 const char line_separator_chars[] = ""; 31 const char *md_shortopts = "O"; 32 const char EXP_CHARS[] = "eE"; 33 const char FLT_CHARS[] = "dD"; 34 35 int Optimizing = 0; 36 37 #define AT_WORD_P(X) ((X)->X_op == O_right_shift \ 38 && (X)->X_op_symbol != NULL \ 39 && symbol_constant_p ((X)->X_op_symbol) \ 40 && S_GET_VALUE ((X)->X_op_symbol) == AT_WORD_RIGHT_SHIFT) 41 #define AT_WORD_RIGHT_SHIFT 2 42 43 /* Fixups. */ 44 #define MAX_INSN_FIXUPS 5 45 46 struct d10v_fixup 47 { 48 expressionS exp; 49 int operand; 50 int pcrel; 51 int size; 52 bfd_reloc_code_real_type reloc; 53 }; 54 55 typedef struct _fixups 56 { 57 int fc; 58 struct d10v_fixup fix[MAX_INSN_FIXUPS]; 59 struct _fixups *next; 60 } Fixups; 61 62 static Fixups FixUps[2]; 63 static Fixups *fixups; 64 65 static int do_not_ignore_hash = 0; 66 67 typedef int packing_type; 68 #define PACK_UNSPEC (0) /* Packing order not specified. */ 69 #define PACK_PARALLEL (1) /* "||" */ 70 #define PACK_LEFT_RIGHT (2) /* "->" */ 71 #define PACK_RIGHT_LEFT (3) /* "<-" */ 72 static packing_type etype = PACK_UNSPEC; /* Used by d10v_cleanup. */ 73 74 /* TRUE if instruction swapping warnings should be inhibited. 75 --nowarnswap. */ 76 static bool flag_warn_suppress_instructionswap; 77 78 /* TRUE if instruction packing should be performed when --gstabs is specified. 79 --gstabs-packing, --no-gstabs-packing. */ 80 static bool flag_allow_gstabs_packing = 1; 81 82 /* Local functions. */ 83 84 enum options 85 { 86 OPTION_NOWARNSWAP = OPTION_MD_BASE, 87 OPTION_GSTABSPACKING, 88 OPTION_NOGSTABSPACKING 89 }; 90 91 struct option md_longopts[] = 92 { 93 {"nowarnswap", no_argument, NULL, OPTION_NOWARNSWAP}, 94 {"gstabspacking", no_argument, NULL, OPTION_GSTABSPACKING}, 95 {"gstabs-packing", no_argument, NULL, OPTION_GSTABSPACKING}, 96 {"nogstabspacking", no_argument, NULL, OPTION_NOGSTABSPACKING}, 97 {"no-gstabs-packing", no_argument, NULL, OPTION_NOGSTABSPACKING}, 98 {NULL, no_argument, NULL, 0} 99 }; 100 101 size_t md_longopts_size = sizeof (md_longopts); 102 103 /* Opcode hash table. */ 104 static htab_t d10v_hash; 105 106 /* Do a binary search of the d10v_predefined_registers array to see if 107 NAME is a valid register name. Return the register number from the 108 array on success, or -1 on failure. */ 109 110 static int 111 reg_name_search (char *name) 112 { 113 int middle, low, high; 114 int cmp; 115 116 low = 0; 117 high = d10v_reg_name_cnt () - 1; 118 119 do 120 { 121 middle = (low + high) / 2; 122 cmp = strcasecmp (name, d10v_predefined_registers[middle].name); 123 if (cmp < 0) 124 high = middle - 1; 125 else if (cmp > 0) 126 low = middle + 1; 127 else 128 return d10v_predefined_registers[middle].value; 129 } 130 while (low <= high); 131 return -1; 132 } 133 134 /* Check the string at input_line_pointer 135 to see if it is a valid register name. */ 136 137 static int 138 register_name (expressionS *expressionP) 139 { 140 int reg_number; 141 char c, *p = input_line_pointer; 142 143 while (*p 144 && *p != '\n' && *p != '\r' && *p != ',' && *p != ' ' && *p != ')') 145 p++; 146 147 c = *p; 148 if (c) 149 *p++ = 0; 150 151 /* Look to see if it's in the register table. */ 152 reg_number = reg_name_search (input_line_pointer); 153 if (reg_number >= 0) 154 { 155 expressionP->X_op = O_register; 156 /* Temporarily store a pointer to the string here. */ 157 expressionP->X_op_symbol = (symbolS *) input_line_pointer; 158 expressionP->X_add_number = reg_number; 159 input_line_pointer = p; 160 return 1; 161 } 162 if (c) 163 *(p - 1) = c; 164 return 0; 165 } 166 167 static int 168 check_range (unsigned long num, int bits, int flags) 169 { 170 long min, max; 171 int retval = 0; 172 173 /* Don't bother checking 16-bit values. */ 174 if (bits == 16) 175 return 0; 176 177 if (flags & OPERAND_SHIFT) 178 { 179 /* All special shift operands are unsigned and <= 16. 180 We allow 0 for now. */ 181 if (num > 16) 182 return 1; 183 else 184 return 0; 185 } 186 187 if (flags & OPERAND_SIGNED) 188 { 189 /* Signed 3-bit integers are restricted to the (-2, 3) range. */ 190 if (flags & RESTRICTED_NUM3) 191 { 192 if ((long) num < -2 || (long) num > 3) 193 retval = 1; 194 } 195 else 196 { 197 max = (1 << (bits - 1)) - 1; 198 min = - (1 << (bits - 1)); 199 if (((long) num > max) || ((long) num < min)) 200 retval = 1; 201 } 202 } 203 else 204 { 205 max = (1 << bits) - 1; 206 min = 0; 207 if (((long) num > max) || ((long) num < min)) 208 retval = 1; 209 } 210 return retval; 211 } 212 213 void 214 md_show_usage (FILE *stream) 215 { 216 fprintf (stream, _("D10V options:\n\ 217 -O Optimize. Will do some operations in parallel.\n\ 218 --gstabs-packing Pack adjacent short instructions together even\n\ 219 when --gstabs is specified. On by default.\n\ 220 --no-gstabs-packing If --gstabs is specified, do not pack adjacent\n\ 221 instructions together.\n")); 222 } 223 224 int 225 md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED) 226 { 227 switch (c) 228 { 229 case 'O': 230 /* Optimize. Will attempt to parallelize operations. */ 231 Optimizing = 1; 232 break; 233 case OPTION_NOWARNSWAP: 234 flag_warn_suppress_instructionswap = 1; 235 break; 236 case OPTION_GSTABSPACKING: 237 flag_allow_gstabs_packing = 1; 238 break; 239 case OPTION_NOGSTABSPACKING: 240 flag_allow_gstabs_packing = 0; 241 break; 242 default: 243 return 0; 244 } 245 return 1; 246 } 247 248 symbolS * 249 md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 250 { 251 return 0; 252 } 253 254 const char * 255 md_atof (int type, char *litP, int *sizeP) 256 { 257 return ieee_md_atof (type, litP, sizeP, true); 258 } 259 260 void 261 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, 262 asection *sec ATTRIBUTE_UNUSED, 263 fragS *fragP ATTRIBUTE_UNUSED) 264 { 265 abort (); 266 } 267 268 valueT 269 md_section_align (asection *seg, valueT addr) 270 { 271 int align = bfd_section_alignment (seg); 272 return ((addr + (1 << align) - 1) & -(1 << align)); 273 } 274 275 void 276 md_begin (void) 277 { 278 const char *prev_name = ""; 279 struct d10v_opcode *opcode; 280 d10v_hash = str_htab_create (); 281 282 /* Insert unique names into hash table. The D10v instruction set 283 has many identical opcode names that have different opcodes based 284 on the operands. This hash table then provides a quick index to 285 the first opcode with a particular name in the opcode table. */ 286 287 for (opcode = (struct d10v_opcode *) d10v_opcodes; opcode->name; opcode++) 288 { 289 if (strcmp (prev_name, opcode->name)) 290 { 291 prev_name = (char *) opcode->name; 292 str_hash_insert (d10v_hash, opcode->name, opcode, 0); 293 } 294 } 295 296 fixups = &FixUps[0]; 297 FixUps[0].next = &FixUps[1]; 298 FixUps[1].next = &FixUps[0]; 299 } 300 301 /* Remove the postincrement or postdecrement operator ( '+' or '-' ) 302 from an expression. */ 303 304 static int 305 postfix (char *p) 306 { 307 while (*p != '-' && *p != '+') 308 { 309 if (*p == 0 || *p == '\n' || *p == '\r') 310 break; 311 p++; 312 } 313 314 if (*p == '-') 315 { 316 *p = ' '; 317 return -1; 318 } 319 if (*p == '+') 320 { 321 *p = ' '; 322 return 1; 323 } 324 325 return 0; 326 } 327 328 static bfd_reloc_code_real_type 329 get_reloc (struct d10v_operand *op) 330 { 331 int bits = op->bits; 332 333 if (bits <= 4) 334 return 0; 335 336 if (op->flags & OPERAND_ADDR) 337 { 338 if (bits == 8) 339 return BFD_RELOC_D10V_10_PCREL_R; 340 else 341 return BFD_RELOC_D10V_18_PCREL; 342 } 343 344 return BFD_RELOC_16; 345 } 346 347 /* Parse a string of operands. Return an array of expressions. */ 348 349 static int 350 get_operands (expressionS exp[]) 351 { 352 char *p = input_line_pointer; 353 int numops = 0; 354 int post = 0; 355 int uses_at = 0; 356 357 while (*p) 358 { 359 while (*p == ' ' || *p == '\t' || *p == ',') 360 p++; 361 if (*p == 0 || *p == '\n' || *p == '\r') 362 break; 363 364 if (*p == '@') 365 { 366 uses_at = 1; 367 368 p++; 369 exp[numops].X_op = O_absent; 370 if (*p == '(') 371 { 372 p++; 373 exp[numops].X_add_number = OPERAND_ATPAR; 374 } 375 else if (*p == '-') 376 { 377 p++; 378 exp[numops].X_add_number = OPERAND_ATMINUS; 379 } 380 else 381 { 382 exp[numops].X_add_number = OPERAND_ATSIGN; 383 if (*p == '+') 384 { 385 numops++; 386 exp[numops].X_op = O_absent; 387 exp[numops].X_add_number = OPERAND_PLUS; 388 p++; 389 } 390 post = postfix (p); 391 } 392 numops++; 393 continue; 394 } 395 396 if (*p == ')') 397 { 398 /* Just skip the trailing paren. */ 399 p++; 400 continue; 401 } 402 403 input_line_pointer = p; 404 405 /* Check to see if it might be a register name. */ 406 if (!register_name (&exp[numops])) 407 { 408 /* Parse as an expression. */ 409 if (uses_at) 410 { 411 /* Any expression that involves the indirect addressing 412 cannot also involve immediate addressing. Therefore 413 the use of the hash character is illegal. */ 414 int save = do_not_ignore_hash; 415 do_not_ignore_hash = 1; 416 417 expression (&exp[numops]); 418 419 do_not_ignore_hash = save; 420 } 421 else 422 expression (&exp[numops]); 423 } 424 425 if (strncasecmp (input_line_pointer, "@word", 5) == 0) 426 { 427 input_line_pointer += 5; 428 if (exp[numops].X_op == O_register) 429 { 430 /* If it looked like a register name but was followed by 431 "@word" then it was really a symbol, so change it to 432 one. */ 433 exp[numops].X_op = O_symbol; 434 exp[numops].X_add_symbol = 435 symbol_find_or_make ((char *) exp[numops].X_op_symbol); 436 } 437 438 /* Check for identifier@word+constant. */ 439 if (*input_line_pointer == '-' || *input_line_pointer == '+') 440 { 441 expressionS new_exp; 442 expression (&new_exp); 443 exp[numops].X_add_number = new_exp.X_add_number; 444 } 445 446 /* Convert expr into a right shift by AT_WORD_RIGHT_SHIFT. */ 447 { 448 expressionS new_exp; 449 memset (&new_exp, 0, sizeof new_exp); 450 new_exp.X_add_number = AT_WORD_RIGHT_SHIFT; 451 new_exp.X_op = O_constant; 452 new_exp.X_unsigned = 1; 453 exp[numops].X_op_symbol = make_expr_symbol (&new_exp); 454 exp[numops].X_op = O_right_shift; 455 } 456 457 know (AT_WORD_P (&exp[numops])); 458 } 459 460 if (exp[numops].X_op == O_illegal) 461 as_bad (_("illegal operand")); 462 else if (exp[numops].X_op == O_absent) 463 as_bad (_("missing operand")); 464 465 numops++; 466 p = input_line_pointer; 467 } 468 469 switch (post) 470 { 471 case -1: /* Postdecrement mode. */ 472 exp[numops].X_op = O_absent; 473 exp[numops++].X_add_number = OPERAND_MINUS; 474 break; 475 case 1: /* Postincrement mode. */ 476 exp[numops].X_op = O_absent; 477 exp[numops++].X_add_number = OPERAND_PLUS; 478 break; 479 } 480 481 exp[numops].X_op = 0; 482 return numops; 483 } 484 485 static unsigned long 486 d10v_insert_operand (unsigned long insn, 487 int op_type, 488 offsetT value, 489 int left, 490 fixS *fix) 491 { 492 int shift, bits; 493 494 shift = d10v_operands[op_type].shift; 495 if (left) 496 shift += 15; 497 498 bits = d10v_operands[op_type].bits; 499 500 /* Truncate to the proper number of bits. */ 501 if (check_range (value, bits, d10v_operands[op_type].flags)) 502 as_bad_where (fix->fx_file, fix->fx_line, 503 _("operand out of range: %ld"), (long) value); 504 505 value &= 0x7FFFFFFF >> (31 - bits); 506 insn |= (value << shift); 507 508 return insn; 509 } 510 511 /* Take a pointer to the opcode entry in the opcode table and the 512 array of operand expressions. Return the instruction. */ 513 514 static unsigned long 515 build_insn (struct d10v_opcode *opcode, 516 expressionS *opers, 517 unsigned long insn) 518 { 519 int i, bits, shift, flags, format; 520 unsigned long number; 521 522 /* The insn argument is only used for the DIVS kludge. */ 523 if (insn) 524 format = LONG_R; 525 else 526 { 527 insn = opcode->opcode; 528 format = opcode->format; 529 } 530 531 for (i = 0; opcode->operands[i]; i++) 532 { 533 flags = d10v_operands[opcode->operands[i]].flags; 534 bits = d10v_operands[opcode->operands[i]].bits; 535 shift = d10v_operands[opcode->operands[i]].shift; 536 number = opers[i].X_add_number; 537 538 if (flags & OPERAND_REG) 539 { 540 number &= REGISTER_MASK; 541 if (format == LONG_L) 542 shift += 15; 543 } 544 545 if (opers[i].X_op != O_register && opers[i].X_op != O_constant) 546 { 547 /* Now create a fixup. */ 548 549 if (fixups->fc >= MAX_INSN_FIXUPS) 550 as_fatal (_("too many fixups")); 551 552 if (AT_WORD_P (&opers[i])) 553 { 554 /* Recognize XXX>>1+N aka XXX@word+N as special (AT_WORD). */ 555 fixups->fix[fixups->fc].reloc = BFD_RELOC_D10V_18; 556 opers[i].X_op = O_symbol; 557 opers[i].X_op_symbol = NULL; /* Should free it. */ 558 /* number is left shifted by AT_WORD_RIGHT_SHIFT so 559 that, it is aligned with the symbol's value. Later, 560 BFD_RELOC_D10V_18 will right shift (symbol_value + 561 X_add_number). */ 562 number <<= AT_WORD_RIGHT_SHIFT; 563 opers[i].X_add_number = number; 564 } 565 else 566 { 567 fixups->fix[fixups->fc].reloc = 568 get_reloc ((struct d10v_operand *) &d10v_operands[opcode->operands[i]]); 569 570 /* Check that an immediate was passed to ops that expect one. */ 571 if ((flags & OPERAND_NUM) 572 && (fixups->fix[fixups->fc].reloc == 0)) 573 as_bad (_("operand is not an immediate")); 574 } 575 576 if (fixups->fix[fixups->fc].reloc == BFD_RELOC_16 || 577 fixups->fix[fixups->fc].reloc == BFD_RELOC_D10V_18) 578 fixups->fix[fixups->fc].size = 2; 579 else 580 fixups->fix[fixups->fc].size = 4; 581 582 fixups->fix[fixups->fc].exp = opers[i]; 583 fixups->fix[fixups->fc].operand = opcode->operands[i]; 584 fixups->fix[fixups->fc].pcrel = (flags & OPERAND_ADDR) != 0; 585 (fixups->fc)++; 586 } 587 588 /* Truncate to the proper number of bits. */ 589 if ((opers[i].X_op == O_constant) && check_range (number, bits, flags)) 590 as_bad (_("operand out of range: %lu"), number); 591 number &= 0x7FFFFFFF >> (31 - bits); 592 insn = insn | (number << shift); 593 } 594 595 /* kludge: for DIVS, we need to put the operands in twice on the second 596 pass, format is changed to LONG_R to force the second set of operands 597 to not be shifted over 15. */ 598 if ((opcode->opcode == OPCODE_DIVS) && (format == LONG_L)) 599 insn = build_insn (opcode, opers, insn); 600 601 return insn; 602 } 603 604 /* Write out a long form instruction. */ 605 606 static void 607 write_long (unsigned long insn, Fixups *fx) 608 { 609 int i, where; 610 char *f = frag_more (4); 611 612 dwarf2_emit_insn (4); 613 insn |= FM11; 614 number_to_chars_bigendian (f, insn, 4); 615 616 for (i = 0; i < fx->fc; i++) 617 { 618 if (fx->fix[i].reloc) 619 { 620 where = f - frag_now->fr_literal; 621 if (fx->fix[i].size == 2) 622 where += 2; 623 624 if (fx->fix[i].reloc == BFD_RELOC_D10V_18) 625 fx->fix[i].operand |= 4096; 626 627 fix_new_exp (frag_now, 628 where, 629 fx->fix[i].size, 630 &(fx->fix[i].exp), 631 fx->fix[i].pcrel, 632 fx->fix[i].operand|2048); 633 } 634 } 635 fx->fc = 0; 636 } 637 638 /* Write out a short form instruction by itself. */ 639 640 static void 641 write_1_short (struct d10v_opcode *opcode, 642 unsigned long insn, 643 Fixups *fx) 644 { 645 char *f = frag_more (4); 646 int i, where; 647 648 dwarf2_emit_insn (4); 649 if (opcode->exec_type & PARONLY) 650 as_fatal (_("Instruction must be executed in parallel with another instruction.")); 651 652 /* The other container needs to be NOP. 653 According to 4.3.1: for FM=00, sub-instructions performed only by IU 654 cannot be encoded in L-container. */ 655 if (opcode->unit == IU) 656 insn |= FM00 | (NOP << 15); /* Right container. */ 657 else 658 insn = FM00 | (insn << 15) | NOP; /* Left container. */ 659 660 number_to_chars_bigendian (f, insn, 4); 661 for (i = 0; i < fx->fc; i++) 662 { 663 if (fx->fix[i].reloc) 664 { 665 where = f - frag_now->fr_literal; 666 if (fx->fix[i].size == 2) 667 where += 2; 668 669 if (fx->fix[i].reloc == BFD_RELOC_D10V_18) 670 fx->fix[i].operand |= 4096; 671 672 /* If it's an R reloc, we may have to switch it to L. */ 673 if ((fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R) 674 && (opcode->unit != IU)) 675 fx->fix[i].operand |= 1024; 676 677 fix_new_exp (frag_now, 678 where, 679 fx->fix[i].size, 680 &(fx->fix[i].exp), 681 fx->fix[i].pcrel, 682 fx->fix[i].operand|2048); 683 } 684 } 685 fx->fc = 0; 686 } 687 688 /* Determine if there are any resource conflicts among two manually 689 parallelized instructions. Some of this was lifted from parallel_ok. */ 690 691 static void 692 check_resource_conflict (struct d10v_opcode *op1, 693 unsigned long insn1, 694 struct d10v_opcode *op2, 695 unsigned long insn2) 696 { 697 int i, j, flags, mask, shift, regno; 698 unsigned long ins, mod[2]; 699 struct d10v_opcode *op; 700 701 if ((op1->exec_type & SEQ) 702 || ! ((op1->exec_type & PAR) || (op1->exec_type & PARONLY))) 703 { 704 as_warn (_("packing conflict: %s must dispatch sequentially"), 705 op1->name); 706 return; 707 } 708 709 if ((op2->exec_type & SEQ) 710 || ! ((op2->exec_type & PAR) || (op2->exec_type & PARONLY))) 711 { 712 as_warn (_("packing conflict: %s must dispatch sequentially"), 713 op2->name); 714 return; 715 } 716 717 /* See if both instructions write to the same resource. 718 719 The idea here is to create two sets of bitmasks (mod and used) which 720 indicate which registers are modified or used by each instruction. 721 The operation can only be done in parallel if neither instruction 722 modifies the same register. Accesses to control registers and memory 723 are treated as accesses to a single register. So if both instructions 724 write memory or if the first instruction writes memory and the second 725 reads, then they cannot be done in parallel. We treat reads to the PSW 726 (which includes C, F0, and F1) in isolation. So simultaneously writing 727 C and F0 in two different sub-instructions is permitted. */ 728 729 /* The bitmasks (mod and used) look like this (bit 31 = MSB). 730 r0-r15 0-15 731 a0-a1 16-17 732 cr (not psw) 18 733 psw(other) 19 734 mem 20 735 psw(C flag) 21 736 psw(F0 flag) 22 */ 737 738 for (j = 0; j < 2; j++) 739 { 740 if (j == 0) 741 { 742 op = op1; 743 ins = insn1; 744 } 745 else 746 { 747 op = op2; 748 ins = insn2; 749 } 750 mod[j] = 0; 751 if (op->exec_type & BRANCH_LINK) 752 mod[j] |= 1 << 13; 753 754 for (i = 0; op->operands[i]; i++) 755 { 756 flags = d10v_operands[op->operands[i]].flags; 757 shift = d10v_operands[op->operands[i]].shift; 758 mask = 0x7FFFFFFF >> (31 - d10v_operands[op->operands[i]].bits); 759 if (flags & OPERAND_REG) 760 { 761 regno = (ins >> shift) & mask; 762 if (flags & (OPERAND_ACC0 | OPERAND_ACC1)) 763 regno += 16; 764 else if (flags & OPERAND_CONTROL) /* mvtc or mvfc */ 765 { 766 if (regno == 0) 767 regno = 19; 768 else 769 regno = 18; 770 } 771 else if (flags & OPERAND_FFLAG) 772 regno = 22; 773 else if (flags & OPERAND_CFLAG) 774 regno = 21; 775 776 if (flags & OPERAND_DEST 777 /* Auto inc/dec also modifies the register. */ 778 || (op->operands[i + 1] != 0 779 && (d10v_operands[op->operands[i + 1]].flags 780 & (OPERAND_PLUS | OPERAND_MINUS)) != 0)) 781 { 782 mod[j] |= 1 << regno; 783 if (flags & OPERAND_EVEN) 784 mod[j] |= 1 << (regno + 1); 785 } 786 } 787 else if (flags & OPERAND_ATMINUS) 788 { 789 /* SP implicitly used/modified. */ 790 mod[j] |= 1 << 15; 791 } 792 } 793 794 if (op->exec_type & WMEM) 795 mod[j] |= 1 << 20; 796 else if (op->exec_type & WF0) 797 mod[j] |= 1 << 22; 798 else if (op->exec_type & WCAR) 799 mod[j] |= 1 << 21; 800 } 801 802 if ((mod[0] & mod[1]) == 0) 803 return; 804 else 805 { 806 unsigned long x; 807 x = mod[0] & mod[1]; 808 809 for (j = 0; j <= 15; j++) 810 if (x & (1 << j)) 811 as_warn (_("resource conflict (R%d)"), j); 812 for (j = 16; j <= 17; j++) 813 if (x & (1 << j)) 814 as_warn (_("resource conflict (A%d)"), j - 16); 815 if (x & (1 << 19)) 816 as_warn (_("resource conflict (PSW)")); 817 if (x & (1 << 21)) 818 as_warn (_("resource conflict (C flag)")); 819 if (x & (1 << 22)) 820 as_warn (_("resource conflict (F flag)")); 821 } 822 } 823 824 /* Check 2 instructions and determine if they can be safely 825 executed in parallel. Return 1 if they can be. */ 826 827 static int 828 parallel_ok (struct d10v_opcode *op1, 829 unsigned long insn1, 830 struct d10v_opcode *op2, 831 unsigned long insn2, 832 packing_type exec_type) 833 { 834 int i, j, flags, mask, shift, regno; 835 unsigned long ins, mod[2], used[2]; 836 struct d10v_opcode *op; 837 838 if ((op1->exec_type & SEQ) != 0 || (op2->exec_type & SEQ) != 0 839 || (op1->exec_type & PAR) == 0 || (op2->exec_type & PAR) == 0 840 || (op1->unit == BOTH) || (op2->unit == BOTH) 841 || (op1->unit == IU && op2->unit == IU) 842 || (op1->unit == MU && op2->unit == MU)) 843 return 0; 844 845 /* If this is auto parallelization, and the first instruction is a 846 branch or should not be packed, then don't parallelize. */ 847 if (exec_type == PACK_UNSPEC 848 && (op1->exec_type & (ALONE | BRANCH))) 849 return 0; 850 851 /* The idea here is to create two sets of bitmasks (mod and used) 852 which indicate which registers are modified or used by each 853 instruction. The operation can only be done in parallel if 854 instruction 1 and instruction 2 modify different registers, and 855 the first instruction does not modify registers that the second 856 is using (The second instruction can modify registers that the 857 first is using as they are only written back after the first 858 instruction has completed). Accesses to control registers, PSW, 859 and memory are treated as accesses to a single register. So if 860 both instructions write memory or if the first instruction writes 861 memory and the second reads, then they cannot be done in 862 parallel. Likewise, if the first instruction mucks with the psw 863 and the second reads the PSW (which includes C, F0, and F1), then 864 they cannot operate safely in parallel. */ 865 866 /* The bitmasks (mod and used) look like this (bit 31 = MSB). 867 r0-r15 0-15 868 a0-a1 16-17 869 cr (not psw) 18 870 psw 19 871 mem 20 */ 872 873 for (j = 0; j < 2; j++) 874 { 875 if (j == 0) 876 { 877 op = op1; 878 ins = insn1; 879 } 880 else 881 { 882 op = op2; 883 ins = insn2; 884 } 885 mod[j] = used[j] = 0; 886 if (op->exec_type & BRANCH_LINK) 887 mod[j] |= 1 << 13; 888 889 for (i = 0; op->operands[i]; i++) 890 { 891 flags = d10v_operands[op->operands[i]].flags; 892 shift = d10v_operands[op->operands[i]].shift; 893 mask = 0x7FFFFFFF >> (31 - d10v_operands[op->operands[i]].bits); 894 if (flags & OPERAND_REG) 895 { 896 regno = (ins >> shift) & mask; 897 if (flags & (OPERAND_ACC0 | OPERAND_ACC1)) 898 regno += 16; 899 else if (flags & OPERAND_CONTROL) /* mvtc or mvfc. */ 900 { 901 if (regno == 0) 902 regno = 19; 903 else 904 regno = 18; 905 } 906 else if (flags & (OPERAND_FFLAG | OPERAND_CFLAG)) 907 regno = 19; 908 909 if (flags & OPERAND_DEST) 910 { 911 mod[j] |= 1 << regno; 912 if (flags & OPERAND_EVEN) 913 mod[j] |= 1 << (regno + 1); 914 } 915 else 916 { 917 used[j] |= 1 << regno; 918 if (flags & OPERAND_EVEN) 919 used[j] |= 1 << (regno + 1); 920 921 /* Auto inc/dec also modifies the register. */ 922 if (op->operands[i + 1] != 0 923 && (d10v_operands[op->operands[i + 1]].flags 924 & (OPERAND_PLUS | OPERAND_MINUS)) != 0) 925 mod[j] |= 1 << regno; 926 } 927 } 928 else if (flags & OPERAND_ATMINUS) 929 { 930 /* SP implicitly used/modified. */ 931 mod[j] |= 1 << 15; 932 used[j] |= 1 << 15; 933 } 934 } 935 if (op->exec_type & RMEM) 936 used[j] |= 1 << 20; 937 else if (op->exec_type & WMEM) 938 mod[j] |= 1 << 20; 939 else if (op->exec_type & RF0) 940 used[j] |= 1 << 19; 941 else if (op->exec_type & WF0) 942 mod[j] |= 1 << 19; 943 else if (op->exec_type & WCAR) 944 mod[j] |= 1 << 19; 945 } 946 if ((mod[0] & mod[1]) == 0 && (mod[0] & used[1]) == 0) 947 return 1; 948 return 0; 949 } 950 951 /* Expects two short instructions. 952 If possible, writes out both as a single packed instruction. 953 Otherwise, writes out the first one, packed with a NOP. 954 Returns number of instructions not written out. */ 955 956 static int 957 write_2_short (struct d10v_opcode *opcode1, 958 unsigned long insn1, 959 struct d10v_opcode *opcode2, 960 unsigned long insn2, 961 packing_type exec_type, 962 Fixups *fx) 963 { 964 unsigned long insn; 965 char *f; 966 int i, j, where; 967 968 if ((exec_type != PACK_PARALLEL) 969 && ((opcode1->exec_type & PARONLY) || (opcode2->exec_type & PARONLY))) 970 as_fatal (_("Instruction must be executed in parallel")); 971 972 if ((opcode1->format & LONG_OPCODE) || (opcode2->format & LONG_OPCODE)) 973 as_fatal (_("Long instructions may not be combined.")); 974 975 switch (exec_type) 976 { 977 case PACK_UNSPEC: /* Order not specified. */ 978 if (opcode1->exec_type & ALONE) 979 { 980 /* Case of a short branch on a separate GAS line. Pack with NOP. */ 981 write_1_short (opcode1, insn1, fx->next); 982 return 1; 983 } 984 if (Optimizing 985 && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type)) 986 { 987 /* Parallel. */ 988 if (opcode1->unit == IU) 989 insn = FM00 | (insn2 << 15) | insn1; 990 else if (opcode2->unit == MU) 991 insn = FM00 | (insn2 << 15) | insn1; 992 else 993 insn = FM00 | (insn1 << 15) | insn2; 994 } 995 else if (opcode1->unit == IU) 996 /* Reverse sequential with IU opcode1 on right and done first. */ 997 insn = FM10 | (insn2 << 15) | insn1; 998 else 999 /* Sequential with non-IU opcode1 on left and done first. */ 1000 insn = FM01 | (insn1 << 15) | insn2; 1001 break; 1002 1003 case PACK_PARALLEL: 1004 if (opcode1->exec_type & SEQ || opcode2->exec_type & SEQ) 1005 as_fatal 1006 (_("One of these instructions may not be executed in parallel.")); 1007 if (opcode1->unit == IU) 1008 { 1009 if (opcode2->unit == IU) 1010 as_fatal (_("Two IU instructions may not be executed in parallel")); 1011 if (!flag_warn_suppress_instructionswap) 1012 as_warn (_("Swapping instruction order")); 1013 insn = FM00 | (insn2 << 15) | insn1; 1014 } 1015 else if (opcode2->unit == MU) 1016 { 1017 if (opcode1->unit == MU) 1018 as_fatal (_("Two MU instructions may not be executed in parallel")); 1019 if (!flag_warn_suppress_instructionswap) 1020 as_warn (_("Swapping instruction order")); 1021 insn = FM00 | (insn2 << 15) | insn1; 1022 } 1023 else 1024 insn = FM00 | (insn1 << 15) | insn2; 1025 check_resource_conflict (opcode1, insn1, opcode2, insn2); 1026 break; 1027 1028 case PACK_LEFT_RIGHT: 1029 if (opcode1->unit != IU) 1030 insn = FM01 | (insn1 << 15) | insn2; 1031 else if (opcode2->unit == MU || opcode2->unit == EITHER) 1032 { 1033 if (!flag_warn_suppress_instructionswap) 1034 as_warn (_("Swapping instruction order")); 1035 insn = FM10 | (insn2 << 15) | insn1; 1036 } 1037 else 1038 as_fatal (_("IU instruction may not be in the left container")); 1039 if (opcode1->exec_type & ALONE) 1040 as_warn (_("Instruction in R container is squashed by flow control instruction in L container.")); 1041 break; 1042 1043 case PACK_RIGHT_LEFT: 1044 if (opcode2->unit != MU) 1045 insn = FM10 | (insn1 << 15) | insn2; 1046 else if (opcode1->unit == IU || opcode1->unit == EITHER) 1047 { 1048 if (!flag_warn_suppress_instructionswap) 1049 as_warn (_("Swapping instruction order")); 1050 insn = FM01 | (insn2 << 15) | insn1; 1051 } 1052 else 1053 as_fatal (_("MU instruction may not be in the right container")); 1054 if (opcode2->exec_type & ALONE) 1055 as_warn (_("Instruction in R container is squashed by flow control instruction in L container.")); 1056 break; 1057 1058 default: 1059 as_fatal (_("unknown execution type passed to write_2_short()")); 1060 } 1061 1062 f = frag_more (4); 1063 dwarf2_emit_insn (4); 1064 number_to_chars_bigendian (f, insn, 4); 1065 1066 /* Process fixup chains. fx refers to insn2 when j == 0, and to 1067 insn1 when j == 1. Yes, it's reversed. */ 1068 1069 for (j = 0; j < 2; j++) 1070 { 1071 for (i = 0; i < fx->fc; i++) 1072 { 1073 if (fx->fix[i].reloc) 1074 { 1075 where = f - frag_now->fr_literal; 1076 if (fx->fix[i].size == 2) 1077 where += 2; 1078 1079 if (fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R 1080 /* A BFD_RELOC_D10V_10_PCREL_R relocation applied to 1081 the instruction in the L container has to be 1082 adjusted to BDF_RELOC_D10V_10_PCREL_L. When 1083 j==0, we're processing insn2's operands, so we 1084 want to mark the operand if insn2 is *not* in the 1085 R container. When j==1, we're processing insn1's 1086 operands, so we want to mark the operand if insn2 1087 *is* in the R container. Note that, if two 1088 instructions are identical, we're never going to 1089 swap them, so the test is safe. */ 1090 && j == ((insn & 0x7fff) == insn2)) 1091 fx->fix[i].operand |= 1024; 1092 1093 if (fx->fix[i].reloc == BFD_RELOC_D10V_18) 1094 fx->fix[i].operand |= 4096; 1095 1096 fix_new_exp (frag_now, 1097 where, 1098 fx->fix[i].size, 1099 &(fx->fix[i].exp), 1100 fx->fix[i].pcrel, 1101 fx->fix[i].operand|2048); 1102 } 1103 } 1104 fx->fc = 0; 1105 fx = fx->next; 1106 } 1107 return 0; 1108 } 1109 1110 /* This is the main entry point for the machine-dependent assembler. 1111 str points to a machine-dependent instruction. This function is 1112 supposed to emit the frags/bytes it assembles to. For the D10V, it 1113 mostly handles the special VLIW parsing and packing and leaves the 1114 difficult stuff to do_assemble(). */ 1115 1116 static unsigned long prev_insn; 1117 static struct d10v_opcode *prev_opcode = 0; 1118 static subsegT prev_subseg; 1119 static segT prev_seg = 0; 1120 1121 /* Find the symbol which has the same name as the register in exp. */ 1122 1123 static symbolS * 1124 find_symbol_matching_register (expressionS *exp) 1125 { 1126 int i; 1127 1128 if (exp->X_op != O_register) 1129 return NULL; 1130 1131 /* Find the name of the register. */ 1132 for (i = d10v_reg_name_cnt (); i--;) 1133 if (d10v_predefined_registers[i].value == exp->X_add_number) 1134 break; 1135 1136 if (i < 0) 1137 abort (); 1138 1139 /* Now see if a symbol has been defined with the same name. */ 1140 return symbol_find (d10v_predefined_registers[i].name); 1141 } 1142 1143 /* Get a pointer to an entry in the opcode table. 1144 The function must look at all opcodes with the same name and use 1145 the operands to choose the correct opcode. */ 1146 1147 static struct d10v_opcode * 1148 find_opcode (struct d10v_opcode *opcode, expressionS myops[]) 1149 { 1150 int i, match; 1151 struct d10v_opcode *next_opcode; 1152 1153 /* Get all the operands and save them as expressions. */ 1154 get_operands (myops); 1155 1156 /* Now see if the operand is a fake. If so, find the correct size 1157 instruction, if possible. */ 1158 if (opcode->format == OPCODE_FAKE) 1159 { 1160 int opnum = opcode->operands[0]; 1161 int flags; 1162 1163 if (myops[opnum].X_op == O_register) 1164 { 1165 myops[opnum].X_op = O_symbol; 1166 myops[opnum].X_add_symbol = 1167 symbol_find_or_make ((char *) myops[opnum].X_op_symbol); 1168 myops[opnum].X_add_number = 0; 1169 myops[opnum].X_op_symbol = NULL; 1170 } 1171 1172 next_opcode = opcode + 1; 1173 1174 /* If the first operand is supposed to be a register, make sure 1175 we got a valid one. */ 1176 flags = d10v_operands[next_opcode->operands[0]].flags; 1177 if (flags & OPERAND_REG) 1178 { 1179 int X_op = myops[0].X_op; 1180 int num = myops[0].X_add_number; 1181 1182 if (X_op != O_register 1183 || (num & ~flags 1184 & (OPERAND_GPR | OPERAND_ACC0 | OPERAND_ACC1 1185 | OPERAND_FFLAG | OPERAND_CFLAG | OPERAND_CONTROL)) 1186 || ((flags & OPERAND_SP) && ! (num & OPERAND_SP))) 1187 { 1188 as_bad (_("bad opcode or operands")); 1189 return 0; 1190 } 1191 } 1192 1193 if (myops[opnum].X_op == O_constant 1194 || (myops[opnum].X_op == O_symbol 1195 && S_IS_DEFINED (myops[opnum].X_add_symbol) 1196 && (S_GET_SEGMENT (myops[opnum].X_add_symbol) == now_seg))) 1197 { 1198 for (i = 0; opcode->operands[i + 1]; i++) 1199 { 1200 int bits = d10v_operands[next_opcode->operands[opnum]].bits; 1201 1202 flags = d10v_operands[next_opcode->operands[opnum]].flags; 1203 1204 if (flags & OPERAND_ADDR) 1205 bits += 2; 1206 1207 if (myops[opnum].X_op == O_constant) 1208 { 1209 if (!check_range (myops[opnum].X_add_number, bits, flags)) 1210 break; 1211 } 1212 else 1213 { 1214 fragS *sym_frag; 1215 fragS *f; 1216 unsigned long current_position; 1217 unsigned long symbol_position; 1218 unsigned long value; 1219 bool found_symbol; 1220 1221 /* Calculate the address of the current instruction 1222 and the address of the symbol. Do this by summing 1223 the offsets of previous frags until we reach the 1224 frag containing the symbol, and the current frag. */ 1225 sym_frag = symbol_get_frag (myops[opnum].X_add_symbol); 1226 found_symbol = false; 1227 1228 current_position = frag_now_fix_octets (); 1229 symbol_position = S_GET_VALUE (myops[opnum].X_add_symbol); 1230 1231 for (f = frchain_now->frch_root; f; f = f->fr_next) 1232 { 1233 current_position += f->fr_fix + f->fr_offset; 1234 1235 if (f == sym_frag) 1236 found_symbol = true; 1237 1238 if (! found_symbol) 1239 symbol_position += f->fr_fix + f->fr_offset; 1240 } 1241 1242 value = symbol_position; 1243 1244 if (flags & OPERAND_ADDR) 1245 value -= current_position; 1246 1247 if (AT_WORD_P (&myops[opnum])) 1248 { 1249 if (bits > 4) 1250 { 1251 bits += 2; 1252 if (!check_range (value, bits, flags)) 1253 break; 1254 } 1255 } 1256 else if (!check_range (value, bits, flags)) 1257 break; 1258 } 1259 next_opcode++; 1260 } 1261 1262 if (opcode->operands [i + 1] == 0) 1263 as_fatal (_("value out of range")); 1264 else 1265 opcode = next_opcode; 1266 } 1267 else 1268 /* Not a constant, so use a long instruction. */ 1269 opcode += 2; 1270 } 1271 1272 match = 0; 1273 1274 /* Now search the opcode table table for one with operands 1275 that matches what we've got. */ 1276 while (!match) 1277 { 1278 match = 1; 1279 for (i = 0; opcode->operands[i]; i++) 1280 { 1281 int flags = d10v_operands[opcode->operands[i]].flags; 1282 int X_op = myops[i].X_op; 1283 int num = myops[i].X_add_number; 1284 1285 if (X_op == 0) 1286 { 1287 match = 0; 1288 break; 1289 } 1290 1291 if (flags & OPERAND_REG) 1292 { 1293 if ((X_op != O_register) 1294 || (num & ~flags 1295 & (OPERAND_GPR | OPERAND_ACC0 | OPERAND_ACC1 1296 | OPERAND_FFLAG | OPERAND_CFLAG 1297 | OPERAND_CONTROL)) 1298 || ((flags & OPERAND_SP) && ! (num & OPERAND_SP))) 1299 { 1300 match = 0; 1301 break; 1302 } 1303 } 1304 1305 if (((flags & OPERAND_MINUS) && ((X_op != O_absent) || (num != OPERAND_MINUS))) || 1306 ((flags & OPERAND_PLUS) && ((X_op != O_absent) || (num != OPERAND_PLUS))) || 1307 ((flags & OPERAND_ATMINUS) && ((X_op != O_absent) || (num != OPERAND_ATMINUS))) || 1308 ((flags & OPERAND_ATPAR) && ((X_op != O_absent) || (num != OPERAND_ATPAR))) || 1309 ((flags & OPERAND_ATSIGN) && ((X_op != O_absent) || ((num != OPERAND_ATSIGN) && (num != OPERAND_ATPAR))))) 1310 { 1311 match = 0; 1312 break; 1313 } 1314 1315 /* Unfortunately, for the indirect operand in instructions such 1316 as ``ldb r1, @(c,r14)'' this function can be passed 1317 X_op == O_register (because 'c' is a valid register name). 1318 However we cannot just ignore the case when X_op == O_register 1319 but flags & OPERAND_REG is null, so we check to see if a symbol 1320 of the same name as the register exists. If the symbol does 1321 exist, then the parser was unable to distinguish the two cases 1322 and we fix things here. (Ref: PR14826) */ 1323 1324 if (!(flags & OPERAND_REG) && (X_op == O_register)) 1325 { 1326 symbolS * sym; 1327 1328 sym = find_symbol_matching_register (& myops[i]); 1329 1330 if (sym != NULL) 1331 { 1332 myops[i].X_op = X_op = O_symbol; 1333 myops[i].X_add_symbol = sym; 1334 } 1335 else 1336 as_bad 1337 (_("illegal operand - register name found where none expected")); 1338 } 1339 } 1340 1341 /* We're only done if the operands matched so far AND there 1342 are no more to check. */ 1343 if (match && myops[i].X_op == 0) 1344 break; 1345 else 1346 match = 0; 1347 1348 next_opcode = opcode + 1; 1349 1350 if (next_opcode->opcode == 0) 1351 break; 1352 1353 if (strcmp (next_opcode->name, opcode->name)) 1354 break; 1355 1356 opcode = next_opcode; 1357 } 1358 1359 if (!match) 1360 { 1361 as_bad (_("bad opcode or operands")); 1362 return 0; 1363 } 1364 1365 /* Check that all registers that are required to be even are. 1366 Also, if any operands were marked as registers, but were really symbols, 1367 fix that here. */ 1368 for (i = 0; opcode->operands[i]; i++) 1369 { 1370 if ((d10v_operands[opcode->operands[i]].flags & OPERAND_EVEN) && 1371 (myops[i].X_add_number & 1)) 1372 as_fatal (_("Register number must be EVEN")); 1373 if ((d10v_operands[opcode->operands[i]].flags & OPERAND_NOSP) 1374 && (myops[i].X_add_number & OPERAND_SP)) 1375 as_bad (_("Unsupported use of sp")); 1376 if (myops[i].X_op == O_register) 1377 { 1378 if (!(d10v_operands[opcode->operands[i]].flags & OPERAND_REG)) 1379 { 1380 myops[i].X_op = O_symbol; 1381 myops[i].X_add_symbol = 1382 symbol_find_or_make ((char *) myops[i].X_op_symbol); 1383 myops[i].X_add_number = 0; 1384 myops[i].X_op_symbol = NULL; 1385 } 1386 } 1387 if ((d10v_operands[opcode->operands[i]].flags & OPERAND_CONTROL) 1388 && (myops[i].X_add_number == OPERAND_CONTROL + 4 1389 || myops[i].X_add_number == OPERAND_CONTROL + 5 1390 || myops[i].X_add_number == OPERAND_CONTROL + 6 1391 || myops[i].X_add_number == OPERAND_CONTROL + 12 1392 || myops[i].X_add_number == OPERAND_CONTROL + 13 1393 || myops[i].X_add_number == OPERAND_CONTROL + 15)) 1394 as_warn (_("cr%ld is a reserved control register"), 1395 myops[i].X_add_number - OPERAND_CONTROL); 1396 } 1397 return opcode; 1398 } 1399 1400 /* Assemble a single instruction. 1401 Return an opcode, or -1 (an invalid opcode) on error. */ 1402 1403 static unsigned long 1404 do_assemble (char *str, struct d10v_opcode **opcode) 1405 { 1406 unsigned char *op_start, *op_end; 1407 char *save; 1408 char name[20]; 1409 int nlen = 0; 1410 expressionS myops[6]; 1411 1412 /* Drop leading whitespace. */ 1413 while (*str == ' ') 1414 str++; 1415 1416 /* Find the opcode end. */ 1417 for (op_start = op_end = (unsigned char *) str; 1418 *op_end && !is_end_of_line[*op_end] && *op_end != ' '; 1419 op_end++) 1420 { 1421 name[nlen] = TOLOWER (op_start[nlen]); 1422 nlen++; 1423 if (nlen == sizeof (name) - 1) 1424 break; 1425 } 1426 name[nlen] = 0; 1427 1428 if (nlen == 0) 1429 return -1; 1430 1431 /* Find the first opcode with the proper name. */ 1432 *opcode = (struct d10v_opcode *) str_hash_find (d10v_hash, name); 1433 if (*opcode == NULL) 1434 return -1; 1435 1436 save = input_line_pointer; 1437 input_line_pointer = (char *) op_end; 1438 *opcode = find_opcode (*opcode, myops); 1439 if (*opcode == 0) 1440 return -1; 1441 input_line_pointer = save; 1442 1443 return build_insn ((*opcode), myops, 0); 1444 } 1445 1446 /* If while processing a fixup, a reloc really needs to be created. 1447 Then it is done here. */ 1448 1449 arelent * 1450 tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp) 1451 { 1452 arelent *reloc; 1453 reloc = XNEW (arelent); 1454 reloc->sym_ptr_ptr = XNEW (asymbol *); 1455 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 1456 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 1457 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); 1458 if (reloc->howto == (reloc_howto_type *) NULL) 1459 { 1460 as_bad_where (fixp->fx_file, fixp->fx_line, 1461 _("reloc %d not supported by object file format"), 1462 (int) fixp->fx_r_type); 1463 return NULL; 1464 } 1465 1466 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 1467 reloc->address = fixp->fx_offset; 1468 1469 reloc->addend = 0; 1470 1471 return reloc; 1472 } 1473 1474 int 1475 md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED, 1476 asection *seg ATTRIBUTE_UNUSED) 1477 { 1478 abort (); 1479 return 0; 1480 } 1481 1482 long 1483 md_pcrel_from_section (fixS *fixp, segT sec) 1484 { 1485 if (fixp->fx_addsy != (symbolS *) NULL 1486 && (!S_IS_DEFINED (fixp->fx_addsy) 1487 || (S_GET_SEGMENT (fixp->fx_addsy) != sec))) 1488 return 0; 1489 return fixp->fx_frag->fr_address + fixp->fx_where; 1490 } 1491 1492 void 1493 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) 1494 { 1495 char *where; 1496 unsigned long insn; 1497 long value = *valP; 1498 int op_type; 1499 int left = 0; 1500 1501 if (fixP->fx_addsy == (symbolS *) NULL) 1502 fixP->fx_done = 1; 1503 1504 /* We don't actually support subtracting a symbol. */ 1505 if (fixP->fx_subsy != (symbolS *) NULL) 1506 as_bad_subtract (fixP); 1507 1508 op_type = fixP->fx_r_type; 1509 if (op_type & 2048) 1510 { 1511 op_type -= 2048; 1512 if (op_type & 1024) 1513 { 1514 op_type -= 1024; 1515 fixP->fx_r_type = BFD_RELOC_D10V_10_PCREL_L; 1516 left = 1; 1517 } 1518 else if (op_type & 4096) 1519 { 1520 op_type -= 4096; 1521 fixP->fx_r_type = BFD_RELOC_D10V_18; 1522 } 1523 else 1524 fixP->fx_r_type = 1525 get_reloc ((struct d10v_operand *) &d10v_operands[op_type]); 1526 } 1527 1528 /* Fetch the instruction, insert the fully resolved operand 1529 value, and stuff the instruction back again. */ 1530 where = fixP->fx_frag->fr_literal + fixP->fx_where; 1531 insn = bfd_getb32 ((unsigned char *) where); 1532 1533 switch (fixP->fx_r_type) 1534 { 1535 case BFD_RELOC_D10V_10_PCREL_L: 1536 case BFD_RELOC_D10V_10_PCREL_R: 1537 case BFD_RELOC_D10V_18_PCREL: 1538 /* If the fix is relative to a global symbol, not a section 1539 symbol, then ignore the offset. 1540 XXX - Do we have to worry about branches to a symbol + offset ? */ 1541 if (fixP->fx_addsy != NULL 1542 && S_IS_EXTERNAL (fixP->fx_addsy) ) 1543 { 1544 segT fseg = S_GET_SEGMENT (fixP->fx_addsy); 1545 segment_info_type *segf = seg_info(fseg); 1546 1547 if ( segf && segf->sym != fixP->fx_addsy) 1548 value = 0; 1549 } 1550 /* Fall through. */ 1551 case BFD_RELOC_D10V_18: 1552 /* Instruction addresses are always right-shifted by 2. */ 1553 value >>= AT_WORD_RIGHT_SHIFT; 1554 if (fixP->fx_size == 2) 1555 bfd_putb16 ((bfd_vma) value, (unsigned char *) where); 1556 else 1557 { 1558 struct d10v_opcode *rep, *repi; 1559 1560 rep = (struct d10v_opcode *) str_hash_find (d10v_hash, "rep"); 1561 repi = (struct d10v_opcode *) str_hash_find (d10v_hash, "repi"); 1562 if ((insn & FM11) == FM11 1563 && ((repi != NULL 1564 && (insn & repi->mask) == (unsigned) repi->opcode) 1565 || (rep != NULL 1566 && (insn & rep->mask) == (unsigned) rep->opcode)) 1567 && value < 4) 1568 as_fatal 1569 (_("line %d: rep or repi must include at least 4 instructions"), 1570 fixP->fx_line); 1571 insn = 1572 d10v_insert_operand (insn, op_type, (offsetT) value, left, fixP); 1573 bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); 1574 } 1575 break; 1576 case BFD_RELOC_32: 1577 bfd_putb32 ((bfd_vma) value, (unsigned char *) where); 1578 break; 1579 case BFD_RELOC_16: 1580 bfd_putb16 ((bfd_vma) value, (unsigned char *) where); 1581 break; 1582 case BFD_RELOC_8: 1583 *where = value; 1584 break; 1585 1586 case BFD_RELOC_VTABLE_INHERIT: 1587 case BFD_RELOC_VTABLE_ENTRY: 1588 fixP->fx_done = 0; 1589 return; 1590 1591 default: 1592 as_fatal (_("line %d: unknown relocation type: 0x%x"), 1593 fixP->fx_line, fixP->fx_r_type); 1594 } 1595 } 1596 1597 /* d10v_cleanup() is called after the assembler has finished parsing 1598 the input file, when a label is read from the input file, or when a 1599 stab directive is output. Because the D10V assembler sometimes 1600 saves short instructions to see if it can package them with the 1601 next instruction, there may be a short instruction that still needs 1602 to be written. 1603 1604 NOTE: accesses a global, etype. 1605 NOTE: invoked by various macros such as md_cleanup: see. */ 1606 1607 int 1608 d10v_cleanup (void) 1609 { 1610 segT seg; 1611 subsegT subseg; 1612 1613 /* If cleanup was invoked because the assembler encountered, e.g., a 1614 user label, we write out the pending instruction, if any. If it 1615 was invoked because the assembler is outputting a piece of line 1616 debugging information, though, we write out the pending 1617 instruction only if the --no-gstabs-packing command line switch 1618 has been specified. */ 1619 if (prev_opcode 1620 && etype == PACK_UNSPEC 1621 && (! outputting_stabs_line_debug || ! flag_allow_gstabs_packing)) 1622 { 1623 seg = now_seg; 1624 subseg = now_subseg; 1625 1626 if (prev_seg) 1627 subseg_set (prev_seg, prev_subseg); 1628 1629 write_1_short (prev_opcode, prev_insn, fixups->next); 1630 subseg_set (seg, subseg); 1631 prev_opcode = NULL; 1632 } 1633 return 1; 1634 } 1635 1636 void 1637 d10v_frob_label (symbolS *lab) 1638 { 1639 d10v_cleanup (); 1640 symbol_set_frag (lab, frag_now); 1641 S_SET_VALUE (lab, (valueT) frag_now_fix ()); 1642 dwarf2_emit_label (lab); 1643 } 1644 1645 /* Like normal .word, except support @word. 1646 Clobbers input_line_pointer, checks end-of-line. */ 1647 1648 static void 1649 d10v_dot_word (int dummy ATTRIBUTE_UNUSED) 1650 { 1651 expressionS exp; 1652 char *p; 1653 1654 if (is_it_end_of_statement ()) 1655 { 1656 demand_empty_rest_of_line (); 1657 return; 1658 } 1659 1660 do 1661 { 1662 expression (&exp); 1663 if (!strncasecmp (input_line_pointer, "@word", 5)) 1664 { 1665 exp.X_add_number = 0; 1666 input_line_pointer += 5; 1667 1668 p = frag_more (2); 1669 fix_new_exp (frag_now, p - frag_now->fr_literal, 2, 1670 &exp, 0, BFD_RELOC_D10V_18); 1671 } 1672 else 1673 emit_expr (&exp, 2); 1674 } 1675 while (*input_line_pointer++ == ','); 1676 1677 input_line_pointer--; /* Put terminator back into stream. */ 1678 demand_empty_rest_of_line (); 1679 } 1680 1681 /* Mitsubishi asked that we support some old syntax that apparently 1682 had immediate operands starting with '#'. This is in some of their 1683 sample code but is not documented (although it appears in some 1684 examples in their assembler manual). For now, we'll solve this 1685 compatibility problem by simply ignoring any '#' at the beginning 1686 of an operand. */ 1687 1688 /* Operands that begin with '#' should fall through to here. 1689 From expr.c. */ 1690 1691 void 1692 md_operand (expressionS *expressionP) 1693 { 1694 if (*input_line_pointer == '#' && ! do_not_ignore_hash) 1695 { 1696 input_line_pointer++; 1697 expression (expressionP); 1698 } 1699 } 1700 1701 bool 1702 d10v_fix_adjustable (fixS *fixP) 1703 { 1704 /* We need the symbol name for the VTABLE entries. */ 1705 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 1706 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 1707 return 0; 1708 1709 return 1; 1710 } 1711 1712 /* The target specific pseudo-ops which we support. */ 1713 const pseudo_typeS md_pseudo_table[] = 1714 { 1715 { "word", d10v_dot_word, 2 }, 1716 { NULL, NULL, 0 } 1717 }; 1718 1719 void 1720 md_assemble (char *str) 1721 { 1722 /* etype is saved extype. For multi-line instructions. */ 1723 packing_type extype = PACK_UNSPEC; /* Parallel, etc. */ 1724 struct d10v_opcode *opcode; 1725 unsigned long insn; 1726 char *str2; 1727 1728 if (etype == PACK_UNSPEC) 1729 { 1730 /* Look for the special multiple instruction separators. */ 1731 str2 = strstr (str, "||"); 1732 if (str2) 1733 extype = PACK_PARALLEL; 1734 else 1735 { 1736 str2 = strstr (str, "->"); 1737 if (str2) 1738 extype = PACK_LEFT_RIGHT; 1739 else 1740 { 1741 str2 = strstr (str, "<-"); 1742 if (str2) 1743 extype = PACK_RIGHT_LEFT; 1744 } 1745 } 1746 1747 /* str2 points to the separator, if there is one. */ 1748 if (str2) 1749 { 1750 *str2 = 0; 1751 1752 /* If two instructions are present and we already have one saved, 1753 then first write out the saved one. */ 1754 d10v_cleanup (); 1755 1756 /* Assemble first instruction and save it. */ 1757 prev_insn = do_assemble (str, &prev_opcode); 1758 prev_seg = now_seg; 1759 prev_subseg = now_subseg; 1760 if (prev_insn == (unsigned long) -1) 1761 as_fatal (_("can't find previous opcode ")); 1762 fixups = fixups->next; 1763 str = str2 + 2; 1764 } 1765 } 1766 1767 insn = do_assemble (str, &opcode); 1768 if (insn == (unsigned long) -1) 1769 { 1770 if (extype != PACK_UNSPEC) 1771 etype = extype; 1772 else 1773 as_bad (_("could not assemble: %s"), str); 1774 return; 1775 } 1776 1777 if (etype != PACK_UNSPEC) 1778 { 1779 extype = etype; 1780 etype = PACK_UNSPEC; 1781 } 1782 1783 /* If this is a long instruction, write it and any previous short 1784 instruction. */ 1785 if (opcode->format & LONG_OPCODE) 1786 { 1787 if (extype != PACK_UNSPEC) 1788 as_fatal (_("Unable to mix instructions as specified")); 1789 d10v_cleanup (); 1790 write_long (insn, fixups); 1791 prev_opcode = NULL; 1792 return; 1793 } 1794 1795 if (prev_opcode 1796 && prev_seg 1797 && ((prev_seg != now_seg) || (prev_subseg != now_subseg))) 1798 d10v_cleanup (); 1799 1800 if (prev_opcode 1801 && (0 == write_2_short (prev_opcode, prev_insn, opcode, insn, extype, 1802 fixups))) 1803 { 1804 /* No instructions saved. */ 1805 prev_opcode = NULL; 1806 } 1807 else 1808 { 1809 if (extype != PACK_UNSPEC) 1810 as_fatal (_("Unable to mix instructions as specified")); 1811 /* Save last instruction so it may be packed on next pass. */ 1812 prev_opcode = opcode; 1813 prev_insn = insn; 1814 prev_seg = now_seg; 1815 prev_subseg = now_subseg; 1816 fixups = fixups->next; 1817 } 1818 } 1819 1820
Indexes created Thu Aug 20 00:25:57 UTC 2026