tc-h8300.c revision 1.4.8.1
1 /* tc-h8300.c -- Assemble code for the Renesas H8/300 2 Copyright (C) 1991-2016 Free Software Foundation, Inc. 3 4 This file is part of GAS, the GNU Assembler. 5 6 GAS is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GAS is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GAS; see the file COPYING. If not, write to the Free 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 19 02110-1301, USA. */ 20 21 /* Written By Steve Chamberlain <sac (at) cygnus.com>. */ 22 23 #include "as.h" 24 #include "subsegs.h" 25 #include "dwarf2dbg.h" 26 27 #define DEFINE_TABLE 28 #define h8_opcodes ops 29 #include "opcode/h8300.h" 30 #include "safe-ctype.h" 31 32 #ifdef OBJ_ELF 33 #include "elf/h8.h" 34 #endif 35 36 const char comment_chars[] = ";"; 37 const char line_comment_chars[] = "#"; 38 #ifdef TE_LINUX 39 const char line_separator_chars[] = "!"; 40 #else 41 const char line_separator_chars[] = ""; 42 #endif 43 44 static void sbranch (int); 45 static void h8300hmode (int); 46 static void h8300smode (int); 47 static void h8300hnmode (int); 48 static void h8300snmode (int); 49 static void h8300sxmode (int); 50 static void h8300sxnmode (int); 51 static void pint (int); 52 53 int Hmode; 54 int Smode; 55 int Nmode; 56 int SXmode; 57 58 static int default_mach = bfd_mach_h8300; 59 60 #define PSIZE (Hmode && !Nmode ? L_32 : L_16) 61 62 static int bsize = L_8; /* Default branch displacement. */ 63 64 struct h8_instruction 65 { 66 int length; 67 int noperands; 68 int idx; 69 int size; 70 const struct h8_opcode *opcode; 71 }; 72 73 static struct h8_instruction *h8_instructions; 74 75 static void 76 h8300hmode (int arg ATTRIBUTE_UNUSED) 77 { 78 Hmode = 1; 79 Smode = 0; 80 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300h)) 81 as_warn (_("could not set architecture and machine")); 82 } 83 84 static void 85 h8300smode (int arg ATTRIBUTE_UNUSED) 86 { 87 Smode = 1; 88 Hmode = 1; 89 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300s)) 90 as_warn (_("could not set architecture and machine")); 91 } 92 93 static void 94 h8300hnmode (int arg ATTRIBUTE_UNUSED) 95 { 96 Hmode = 1; 97 Smode = 0; 98 Nmode = 1; 99 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300hn)) 100 as_warn (_("could not set architecture and machine")); 101 } 102 103 static void 104 h8300snmode (int arg ATTRIBUTE_UNUSED) 105 { 106 Smode = 1; 107 Hmode = 1; 108 Nmode = 1; 109 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sn)) 110 as_warn (_("could not set architecture and machine")); 111 } 112 113 static void 114 h8300sxmode (int arg ATTRIBUTE_UNUSED) 115 { 116 Smode = 1; 117 Hmode = 1; 118 SXmode = 1; 119 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sx)) 120 as_warn (_("could not set architecture and machine")); 121 } 122 123 static void 124 h8300sxnmode (int arg ATTRIBUTE_UNUSED) 125 { 126 Smode = 1; 127 Hmode = 1; 128 SXmode = 1; 129 Nmode = 1; 130 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sxn)) 131 as_warn (_("could not set architecture and machine")); 132 } 133 134 static void 135 sbranch (int size) 136 { 137 bsize = size; 138 } 139 140 static void 141 pint (int arg ATTRIBUTE_UNUSED) 142 { 143 cons (Hmode ? 4 : 2); 144 } 145 146 /* Like obj_elf_section, but issues a warning for new 147 sections which do not have an attribute specification. */ 148 149 static void 150 h8300_elf_section (int push) 151 { 152 static const char * known_data_sections [] = { ".rodata", ".tdata", ".tbss" }; 153 static const char * known_data_prefixes [] = { ".debug", ".zdebug", ".gnu.warning" }; 154 char * saved_ilp = input_line_pointer; 155 const char * name; 156 157 name = obj_elf_section_name (); 158 if (name == NULL) 159 return; 160 161 if (* input_line_pointer != ',' 162 && bfd_get_section_by_name (stdoutput, name) == NULL) 163 { 164 signed int i; 165 166 /* Ignore this warning for well known data sections. */ 167 for (i = ARRAY_SIZE (known_data_sections); i--;) 168 if (strcmp (name, known_data_sections[i]) == 0) 169 break; 170 171 if (i < 0) 172 for (i = ARRAY_SIZE (known_data_prefixes); i--;) 173 if (strncmp (name, known_data_prefixes[i], 174 strlen (known_data_prefixes[i])) == 0) 175 break; 176 177 if (i < 0) 178 as_warn (_("new section '%s' defined without attributes - this might cause problems"), name); 179 } 180 181 /* FIXME: We ought to free the memory allocated by obj_elf_section_name() 182 for 'name', but we do not know if it was taken from the obstack, via 183 demand_copy_C_string(), or xmalloc()ed. */ 184 input_line_pointer = saved_ilp; 185 obj_elf_section (push); 186 } 187 188 /* This table describes all the machine specific pseudo-ops the assembler 189 has to support. The fields are: 190 pseudo-op name without dot 191 function to call to execute this pseudo-op 192 Integer arg to pass to the function. */ 193 194 const pseudo_typeS md_pseudo_table[] = 195 { 196 {"h8300h", h8300hmode, 0}, 197 {"h8300hn", h8300hnmode, 0}, 198 {"h8300s", h8300smode, 0}, 199 {"h8300sn", h8300snmode, 0}, 200 {"h8300sx", h8300sxmode, 0}, 201 {"h8300sxn", h8300sxnmode, 0}, 202 {"sbranch", sbranch, L_8}, 203 {"lbranch", sbranch, L_16}, 204 205 {"int", pint, 0}, 206 {"data.b", cons, 1}, 207 {"data.w", cons, 2}, 208 {"data.l", cons, 4}, 209 {"form", listing_psize, 0}, 210 {"heading", listing_title, 0}, 211 {"import", s_ignore, 0}, 212 {"page", listing_eject, 0}, 213 {"program", s_ignore, 0}, 214 215 #ifdef OBJ_ELF 216 {"section", h8300_elf_section, 0}, 217 {"section.s", h8300_elf_section, 0}, 218 {"sect", h8300_elf_section, 0}, 219 {"sect.s", h8300_elf_section, 0}, 220 #endif 221 222 {0, 0, 0} 223 }; 224 225 const char EXP_CHARS[] = "eE"; 226 227 /* Chars that mean this number is a floating point constant 228 As in 0f12.456 229 or 0d1.2345e12. */ 230 const char FLT_CHARS[] = "rRsSfFdDxXpP"; 231 232 static struct hash_control *opcode_hash_control; /* Opcode mnemonics. */ 233 234 /* This function is called once, at assembler startup time. This 235 should set up all the tables, etc. that the MD part of the assembler 236 needs. */ 237 238 void 239 md_begin (void) 240 { 241 unsigned int nopcodes; 242 struct h8_opcode *p, *p1; 243 struct h8_instruction *pi; 244 char prev_buffer[100]; 245 int idx = 0; 246 247 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, default_mach)) 248 as_warn (_("could not set architecture and machine")); 249 250 opcode_hash_control = hash_new (); 251 prev_buffer[0] = 0; 252 253 nopcodes = sizeof (h8_opcodes) / sizeof (struct h8_opcode); 254 255 h8_instructions = XNEWVEC (struct h8_instruction, nopcodes); 256 257 pi = h8_instructions; 258 p1 = h8_opcodes; 259 /* We do a minimum amount of sorting on the opcode table; this is to 260 make it easy to describe the mova instructions without unnecessary 261 code duplication. 262 Sorting only takes place inside blocks of instructions of the form 263 X/Y, so for example mova/b, mova/w and mova/l can be intermixed. */ 264 while (p1) 265 { 266 struct h8_opcode *first_skipped = 0; 267 int len, cmplen = 0; 268 const char *src = p1->name; 269 char *dst, *buffer; 270 271 if (p1->name == 0) 272 break; 273 /* Strip off any . part when inserting the opcode and only enter 274 unique codes into the hash table. */ 275 dst = buffer = XNEWVEC (char, strlen (src) + 1); 276 while (*src) 277 { 278 if (*src == '.') 279 { 280 src++; 281 break; 282 } 283 if (*src == '/') 284 cmplen = src - p1->name + 1; 285 *dst++ = *src++; 286 } 287 *dst = 0; 288 len = dst - buffer; 289 if (cmplen == 0) 290 cmplen = len; 291 hash_insert (opcode_hash_control, buffer, (char *) pi); 292 strcpy (prev_buffer, buffer); 293 idx++; 294 295 for (p = p1; p->name; p++) 296 { 297 /* A negative TIME is used to indicate that we've added this opcode 298 already. */ 299 if (p->time == -1) 300 continue; 301 if (strncmp (p->name, buffer, cmplen) != 0 302 || (p->name[cmplen] != '\0' && p->name[cmplen] != '.' 303 && p->name[cmplen - 1] != '/')) 304 { 305 if (first_skipped == 0) 306 first_skipped = p; 307 break; 308 } 309 if (strncmp (p->name, buffer, len) != 0) 310 { 311 if (first_skipped == 0) 312 first_skipped = p; 313 continue; 314 } 315 316 p->time = -1; 317 pi->size = p->name[len] == '.' ? p->name[len + 1] : 0; 318 pi->idx = idx; 319 320 /* Find the number of operands. */ 321 pi->noperands = 0; 322 while (pi->noperands < 3 && p->args.nib[pi->noperands] != (op_type) E) 323 pi->noperands++; 324 325 /* Find the length of the opcode in bytes. */ 326 pi->length = 0; 327 while (p->data.nib[pi->length * 2] != (op_type) E) 328 pi->length++; 329 330 pi->opcode = p; 331 pi++; 332 } 333 p1 = first_skipped; 334 } 335 336 /* Add entry for the NULL vector terminator. */ 337 pi->length = 0; 338 pi->noperands = 0; 339 pi->idx = 0; 340 pi->size = 0; 341 pi->opcode = 0; 342 343 linkrelax = 1; 344 } 345 346 struct h8_op 347 { 348 op_type mode; 349 unsigned reg; 350 expressionS exp; 351 }; 352 353 static void clever_message (const struct h8_instruction *, struct h8_op *); 354 static void fix_operand_size (struct h8_op *, int); 355 static void build_bytes (const struct h8_instruction *, struct h8_op *); 356 static void do_a_fix_imm (int, int, struct h8_op *, int, const struct h8_instruction *); 357 static void check_operand (struct h8_op *, unsigned int, const char *); 358 static const struct h8_instruction * get_specific (const struct h8_instruction *, struct h8_op *, int) ; 359 static char *get_operands (unsigned, char *, struct h8_op *); 360 static void get_operand (char **, struct h8_op *, int); 361 static int parse_reg (char *, op_type *, unsigned *, int); 362 static char *skip_colonthing (char *, int *); 363 static char *parse_exp (char *, struct h8_op *); 364 365 static int constant_fits_size_p (struct h8_op *, int, int); 366 367 /* 368 parse operands 369 WREG r0,r1,r2,r3,r4,r5,r6,r7,fp,sp 370 r0l,r0h,..r7l,r7h 371 @WREG 372 @WREG+ 373 @-WREG 374 #const 375 ccr 376 */ 377 378 /* Try to parse a reg name. Return the number of chars consumed. */ 379 380 static int 381 parse_reg (char *src, op_type *mode, unsigned int *reg, int direction) 382 { 383 char *end; 384 int len; 385 386 /* Cribbed from get_symbol_name. */ 387 if (!is_name_beginner (*src) || *src == '\001') 388 return 0; 389 end = src + 1; 390 while ((is_part_of_name (*end) && *end != '.') || *end == '\001') 391 end++; 392 len = end - src; 393 394 if (len == 2 && TOLOWER (src[0]) == 's' && TOLOWER (src[1]) == 'p') 395 { 396 *mode = PSIZE | REG | direction; 397 *reg = 7; 398 return len; 399 } 400 if (len == 3 && 401 TOLOWER (src[0]) == 'c' && 402 TOLOWER (src[1]) == 'c' && 403 TOLOWER (src[2]) == 'r') 404 { 405 *mode = CCR; 406 *reg = 0; 407 return len; 408 } 409 if (len == 3 && 410 TOLOWER (src[0]) == 'e' && 411 TOLOWER (src[1]) == 'x' && 412 TOLOWER (src[2]) == 'r') 413 { 414 *mode = EXR; 415 *reg = 1; 416 return len; 417 } 418 if (len == 3 && 419 TOLOWER (src[0]) == 'v' && 420 TOLOWER (src[1]) == 'b' && 421 TOLOWER (src[2]) == 'r') 422 { 423 *mode = VBR; 424 *reg = 6; 425 return len; 426 } 427 if (len == 3 && 428 TOLOWER (src[0]) == 's' && 429 TOLOWER (src[1]) == 'b' && 430 TOLOWER (src[2]) == 'r') 431 { 432 *mode = SBR; 433 *reg = 7; 434 return len; 435 } 436 if (len == 2 && TOLOWER (src[0]) == 'f' && TOLOWER (src[1]) == 'p') 437 { 438 *mode = PSIZE | REG | direction; 439 *reg = 6; 440 return len; 441 } 442 if (len == 3 && TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' && 443 src[2] >= '0' && src[2] <= '7') 444 { 445 *mode = L_32 | REG | direction; 446 *reg = src[2] - '0'; 447 if (!Hmode) 448 as_warn (_("Reg not valid for H8/300")); 449 return len; 450 } 451 if (len == 2 && TOLOWER (src[0]) == 'e' && src[1] >= '0' && src[1] <= '7') 452 { 453 *mode = L_16 | REG | direction; 454 *reg = src[1] - '0' + 8; 455 if (!Hmode) 456 as_warn (_("Reg not valid for H8/300")); 457 return len; 458 } 459 460 if (TOLOWER (src[0]) == 'r') 461 { 462 if (src[1] >= '0' && src[1] <= '7') 463 { 464 if (len == 3 && TOLOWER (src[2]) == 'l') 465 { 466 *mode = L_8 | REG | direction; 467 *reg = (src[1] - '0') + 8; 468 return len; 469 } 470 if (len == 3 && TOLOWER (src[2]) == 'h') 471 { 472 *mode = L_8 | REG | direction; 473 *reg = (src[1] - '0'); 474 return len; 475 } 476 if (len == 2) 477 { 478 *mode = L_16 | REG | direction; 479 *reg = (src[1] - '0'); 480 return len; 481 } 482 } 483 } 484 485 return 0; 486 } 487 488 489 /* Parse an immediate or address-related constant and store it in OP. 490 If the user also specifies the operand's size, store that size 491 in OP->MODE, otherwise leave it for later code to decide. */ 492 493 static char * 494 parse_exp (char *src, struct h8_op *op) 495 { 496 char *save; 497 498 save = input_line_pointer; 499 input_line_pointer = src; 500 expression (&op->exp); 501 if (op->exp.X_op == O_absent) 502 as_bad (_("missing operand")); 503 src = input_line_pointer; 504 input_line_pointer = save; 505 506 return skip_colonthing (src, &op->mode); 507 } 508 509 510 /* If SRC starts with an explicit operand size, skip it and store the size 511 in *MODE. Leave *MODE unchanged otherwise. */ 512 513 static char * 514 skip_colonthing (char *src, int *mode) 515 { 516 if (*src == ':') 517 { 518 src++; 519 *mode &= ~SIZE; 520 if (src[0] == '8' && !ISDIGIT (src[1])) 521 *mode |= L_8; 522 else if (src[0] == '2' && !ISDIGIT (src[1])) 523 *mode |= L_2; 524 else if (src[0] == '3' && !ISDIGIT (src[1])) 525 *mode |= L_3; 526 else if (src[0] == '4' && !ISDIGIT (src[1])) 527 *mode |= L_4; 528 else if (src[0] == '5' && !ISDIGIT (src[1])) 529 *mode |= L_5; 530 else if (src[0] == '2' && src[1] == '4' && !ISDIGIT (src[2])) 531 *mode |= L_24; 532 else if (src[0] == '3' && src[1] == '2' && !ISDIGIT (src[2])) 533 *mode |= L_32; 534 else if (src[0] == '1' && src[1] == '6' && !ISDIGIT (src[2])) 535 *mode |= L_16; 536 else 537 as_bad (_("invalid operand size requested")); 538 539 while (ISDIGIT (*src)) 540 src++; 541 } 542 return src; 543 } 544 545 /* The many forms of operand: 546 547 Rn Register direct 548 @Rn Register indirect 549 @(exp[:16], Rn) Register indirect with displacement 550 @Rn+ 551 @-Rn 552 @aa:8 absolute 8 bit 553 @aa:16 absolute 16 bit 554 @aa absolute 16 bit 555 556 #xx[:size] immediate data 557 @(exp:[8], pc) pc rel 558 @@aa[:8] memory indirect. */ 559 560 static int 561 constant_fits_width_p (struct h8_op *operand, offsetT width) 562 { 563 offsetT num; 564 565 num = ((operand->exp.X_add_number & 0xffffffff) ^ 0x80000000) - 0x80000000; 566 return (num & ~width) == 0 || (num | width) == ~0; 567 } 568 569 static int 570 constant_fits_size_p (struct h8_op *operand, int size, int no_symbols) 571 { 572 offsetT num; 573 574 if (no_symbols 575 && (operand->exp.X_add_symbol != 0 || operand->exp.X_op_symbol != 0)) 576 return 0; 577 num = operand->exp.X_add_number & 0xffffffff; 578 switch (size) 579 { 580 case L_2: 581 return (num & ~3) == 0; 582 case L_3: 583 return (num & ~7) == 0; 584 case L_3NZ: 585 return num >= 1 && num < 8; 586 case L_4: 587 return (num & ~15) == 0; 588 case L_5: 589 return num >= 1 && num < 32; 590 case L_8: 591 num = (num ^ 0x80000000) - 0x80000000; 592 return (num & ~0xFF) == 0 || (num | 0x7F) == ~0; 593 case L_8U: 594 return (num & ~0xFF) == 0; 595 case L_16: 596 num = (num ^ 0x80000000) - 0x80000000; 597 return (num & ~0xFFFF) == 0 || (num | 0x7FFF) == ~0; 598 case L_16U: 599 return (num & ~0xFFFF) == 0; 600 case L_32: 601 return 1; 602 default: 603 abort (); 604 } 605 } 606 607 static void 608 get_operand (char **ptr, struct h8_op *op, int direction) 609 { 610 char *src = *ptr; 611 op_type mode; 612 unsigned int num; 613 unsigned int len; 614 615 op->mode = 0; 616 617 /* Check for '(' and ')' for instructions ldm and stm. */ 618 if (src[0] == '(' && src[8] == ')') 619 ++ src; 620 621 /* Gross. Gross. ldm and stm have a format not easily handled 622 by get_operand. We deal with it explicitly here. */ 623 if (TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' && 624 ISDIGIT (src[2]) && src[3] == '-' && 625 TOLOWER (src[4]) == 'e' && TOLOWER (src[5]) == 'r' && ISDIGIT (src[6])) 626 { 627 int low, high; 628 629 low = src[2] - '0'; 630 high = src[6] - '0'; 631 632 /* Check register pair's validity as per tech note TN-H8*-193A/E 633 from Renesas for H8S and H8SX hardware manual. */ 634 if ( !(low == 0 && (high == 1 || high == 2 || high == 3)) 635 && !(low == 1 && (high == 2 || high == 3 || high == 4) && SXmode) 636 && !(low == 2 && (high == 3 || ((high == 4 || high == 5) && SXmode))) 637 && !(low == 3 && (high == 4 || high == 5 || high == 6) && SXmode) 638 && !(low == 4 && (high == 5 || high == 6)) 639 && !(low == 4 && high == 7 && SXmode) 640 && !(low == 5 && (high == 6 || high == 7) && SXmode) 641 && !(low == 6 && high == 7 && SXmode)) 642 as_bad (_("Invalid register list for ldm/stm\n")); 643 644 /* Even sicker. We encode two registers into op->reg. One 645 for the low register to save, the other for the high 646 register to save; we also set the high bit in op->reg 647 so we know this is "very special". */ 648 op->reg = 0x80000000 | (high << 8) | low; 649 op->mode = REG; 650 if (src[7] == ')') 651 *ptr = src + 8; 652 else 653 *ptr = src + 7; 654 return; 655 } 656 657 len = parse_reg (src, &op->mode, &op->reg, direction); 658 if (len) 659 { 660 src += len; 661 if (*src == '.') 662 { 663 int size = op->mode & SIZE; 664 switch (src[1]) 665 { 666 case 'l': case 'L': 667 if (size != L_32) 668 as_warn (_("mismatch between register and suffix")); 669 op->mode = (op->mode & ~MODE) | LOWREG; 670 break; 671 case 'w': case 'W': 672 if (size != L_32 && size != L_16) 673 as_warn (_("mismatch between register and suffix")); 674 op->mode = (op->mode & ~MODE) | LOWREG; 675 op->mode = (op->mode & ~SIZE) | L_16; 676 break; 677 case 'b': case 'B': 678 op->mode = (op->mode & ~MODE) | LOWREG; 679 if (size != L_32 && size != L_8) 680 as_warn (_("mismatch between register and suffix")); 681 op->mode = (op->mode & ~MODE) | LOWREG; 682 op->mode = (op->mode & ~SIZE) | L_8; 683 break; 684 default: 685 as_warn (_("invalid suffix after register.")); 686 break; 687 } 688 src += 2; 689 } 690 *ptr = src; 691 return; 692 } 693 694 if (*src == '@') 695 { 696 src++; 697 if (*src == '@') 698 { 699 *ptr = parse_exp (src + 1, op); 700 if (op->exp.X_add_number >= 0x100) 701 { 702 int divisor = 1; 703 704 op->mode = VECIND; 705 /* FIXME : 2? or 4? */ 706 if (op->exp.X_add_number >= 0x400) 707 as_bad (_("address too high for vector table jmp/jsr")); 708 else if (op->exp.X_add_number >= 0x200) 709 divisor = 4; 710 else 711 divisor = 2; 712 713 op->exp.X_add_number = op->exp.X_add_number / divisor - 0x80; 714 } 715 else 716 op->mode = MEMIND; 717 return; 718 } 719 720 if (*src == '-' || *src == '+') 721 { 722 len = parse_reg (src + 1, &mode, &num, direction); 723 if (len == 0) 724 { 725 /* Oops, not a reg after all, must be ordinary exp. */ 726 op->mode = ABS | direction; 727 *ptr = parse_exp (src, op); 728 return; 729 } 730 731 if (((mode & SIZE) != PSIZE) 732 /* For Normal mode accept 16 bit and 32 bit pointer registers. */ 733 && (!Nmode || ((mode & SIZE) != L_32))) 734 as_bad (_("Wrong size pointer register for architecture.")); 735 736 op->mode = src[0] == '-' ? RDPREDEC : RDPREINC; 737 op->reg = num; 738 *ptr = src + 1 + len; 739 return; 740 } 741 if (*src == '(') 742 { 743 src++; 744 745 /* See if this is @(ERn.x, PC). */ 746 len = parse_reg (src, &mode, &op->reg, direction); 747 if (len != 0 && (mode & MODE) == REG && src[len] == '.') 748 { 749 switch (TOLOWER (src[len + 1])) 750 { 751 case 'b': 752 mode = PCIDXB | direction; 753 break; 754 case 'w': 755 mode = PCIDXW | direction; 756 break; 757 case 'l': 758 mode = PCIDXL | direction; 759 break; 760 default: 761 mode = 0; 762 break; 763 } 764 if (mode 765 && src[len + 2] == ',' 766 && TOLOWER (src[len + 3]) != 'p' 767 && TOLOWER (src[len + 4]) != 'c' 768 && src[len + 5] != ')') 769 { 770 *ptr = src + len + 6; 771 op->mode |= mode; 772 return; 773 } 774 /* Fall through into disp case - the grammar is somewhat 775 ambiguous, so we should try whether it's a DISP operand 776 after all ("ER3.L" might be a poorly named label...). */ 777 } 778 779 /* Disp. */ 780 781 /* Start off assuming a 16 bit offset. */ 782 783 src = parse_exp (src, op); 784 if (*src == ')') 785 { 786 op->mode |= ABS | direction; 787 *ptr = src + 1; 788 return; 789 } 790 791 if (*src != ',') 792 { 793 as_bad (_("expected @(exp, reg16)")); 794 return; 795 } 796 src++; 797 798 len = parse_reg (src, &mode, &op->reg, direction); 799 if (len == 0 || (mode & MODE) != REG) 800 { 801 as_bad (_("expected @(exp, reg16)")); 802 return; 803 } 804 src += len; 805 if (src[0] == '.') 806 { 807 switch (TOLOWER (src[1])) 808 { 809 case 'b': 810 op->mode |= INDEXB | direction; 811 break; 812 case 'w': 813 op->mode |= INDEXW | direction; 814 break; 815 case 'l': 816 op->mode |= INDEXL | direction; 817 break; 818 default: 819 as_bad (_("expected .L, .W or .B for register in indexed addressing mode")); 820 } 821 src += 2; 822 op->reg &= 7; 823 } 824 else 825 op->mode |= DISP | direction; 826 src = skip_colonthing (src, &op->mode); 827 828 if (*src != ')') 829 { 830 as_bad (_("expected @(exp, reg16)")); 831 return; 832 } 833 *ptr = src + 1; 834 return; 835 } 836 len = parse_reg (src, &mode, &num, direction); 837 838 if (len) 839 { 840 src += len; 841 if (*src == '+' || *src == '-') 842 { 843 if (((mode & SIZE) != PSIZE) 844 /* For Normal mode accept 16 bit and 32 bit pointer registers. */ 845 && (!Nmode || ((mode & SIZE) != L_32))) 846 as_bad (_("Wrong size pointer register for architecture.")); 847 op->mode = *src == '+' ? RSPOSTINC : RSPOSTDEC; 848 op->reg = num; 849 src++; 850 *ptr = src; 851 return; 852 } 853 if (((mode & SIZE) != PSIZE) 854 /* For Normal mode accept 16 bit and 32 bit pointer registers. */ 855 && (!Nmode || ((mode & SIZE) != L_32))) 856 as_bad (_("Wrong size pointer register for architecture.")); 857 858 op->mode = direction | IND | PSIZE; 859 op->reg = num; 860 *ptr = src; 861 862 return; 863 } 864 else 865 { 866 /* must be a symbol */ 867 868 op->mode = ABS | direction; 869 *ptr = parse_exp (src, op); 870 return; 871 } 872 } 873 874 if (*src == '#') 875 { 876 op->mode = IMM; 877 *ptr = parse_exp (src + 1, op); 878 return; 879 } 880 else if (strncmp (src, "mach", 4) == 0 || 881 strncmp (src, "macl", 4) == 0 || 882 strncmp (src, "MACH", 4) == 0 || 883 strncmp (src, "MACL", 4) == 0) 884 { 885 op->reg = TOLOWER (src[3]) == 'l'; 886 op->mode = MACREG; 887 *ptr = src + 4; 888 return; 889 } 890 else 891 { 892 op->mode = PCREL; 893 *ptr = parse_exp (src, op); 894 } 895 } 896 897 static char * 898 get_operands (unsigned int noperands, char *op_end, struct h8_op *operand) 899 { 900 char *ptr = op_end; 901 902 switch (noperands) 903 { 904 case 0: 905 break; 906 907 case 1: 908 ptr++; 909 get_operand (&ptr, operand + 0, SRC); 910 if (*ptr == ',') 911 { 912 ptr++; 913 get_operand (&ptr, operand + 1, DST); 914 } 915 break; 916 917 case 2: 918 ptr++; 919 get_operand (&ptr, operand + 0, SRC); 920 if (*ptr == ',') 921 ptr++; 922 get_operand (&ptr, operand + 1, DST); 923 break; 924 925 case 3: 926 ptr++; 927 get_operand (&ptr, operand + 0, SRC); 928 if (*ptr == ',') 929 ptr++; 930 get_operand (&ptr, operand + 1, DST); 931 if (*ptr == ',') 932 ptr++; 933 get_operand (&ptr, operand + 2, OP3); 934 break; 935 936 default: 937 abort (); 938 } 939 940 return ptr; 941 } 942 943 /* MOVA has special requirements. Rather than adding twice the amount of 944 addressing modes, we simply special case it a bit. */ 945 static void 946 get_mova_operands (char *op_end, struct h8_op *operand) 947 { 948 char *ptr = op_end; 949 950 if (ptr[1] != '@' || ptr[2] != '(') 951 goto error; 952 ptr += 3; 953 operand[0].mode = 0; 954 ptr = parse_exp (ptr, &operand[0]); 955 956 if (*ptr !=',') 957 goto error; 958 ptr++; 959 get_operand (&ptr, operand + 1, DST); 960 961 if (*ptr =='.') 962 { 963 ptr++; 964 switch (*ptr++) 965 { 966 case 'b': case 'B': 967 operand[0].mode = (operand[0].mode & ~MODE) | INDEXB; 968 break; 969 case 'w': case 'W': 970 operand[0].mode = (operand[0].mode & ~MODE) | INDEXW; 971 break; 972 case 'l': case 'L': 973 operand[0].mode = (operand[0].mode & ~MODE) | INDEXL; 974 break; 975 default: 976 goto error; 977 } 978 } 979 else if ((operand[1].mode & MODE) == LOWREG) 980 { 981 switch (operand[1].mode & SIZE) 982 { 983 case L_8: 984 operand[0].mode = (operand[0].mode & ~MODE) | INDEXB; 985 break; 986 case L_16: 987 operand[0].mode = (operand[0].mode & ~MODE) | INDEXW; 988 break; 989 case L_32: 990 operand[0].mode = (operand[0].mode & ~MODE) | INDEXL; 991 break; 992 default: 993 goto error; 994 } 995 } 996 else 997 goto error; 998 999 if (*ptr++ != ')' || *ptr++ != ',') 1000 goto error; 1001 get_operand (&ptr, operand + 2, OP3); 1002 /* See if we can use the short form of MOVA. */ 1003 if (((operand[1].mode & MODE) == REG || (operand[1].mode & MODE) == LOWREG) 1004 && (operand[2].mode & MODE) == REG 1005 && (operand[1].reg & 7) == (operand[2].reg & 7)) 1006 { 1007 operand[1].mode = operand[2].mode = 0; 1008 operand[0].reg = operand[2].reg & 7; 1009 } 1010 return; 1011 1012 error: 1013 as_bad (_("expected valid addressing mode for mova: \"@(disp, ea.sz),ERn\"")); 1014 } 1015 1016 static void 1017 get_rtsl_operands (char *ptr, struct h8_op *operand) 1018 { 1019 int mode, len, type = 0; 1020 unsigned int num, num2; 1021 1022 ptr++; 1023 if (*ptr == '(') 1024 { 1025 ptr++; 1026 type = 1; 1027 } 1028 len = parse_reg (ptr, &mode, &num, SRC); 1029 if (len == 0 || (mode & MODE) != REG) 1030 { 1031 as_bad (_("expected register")); 1032 return; 1033 } 1034 ptr += len; 1035 if (*ptr == '-') 1036 { 1037 len = parse_reg (++ptr, &mode, &num2, SRC); 1038 if (len == 0 || (mode & MODE) != REG) 1039 { 1040 as_bad (_("expected register")); 1041 return; 1042 } 1043 ptr += len; 1044 /* CONST_xxx are used as placeholders in the opcode table. */ 1045 num = num2 - num; 1046 if (num > 3) 1047 { 1048 as_bad (_("invalid register list")); 1049 return; 1050 } 1051 } 1052 else 1053 num2 = num, num = 0; 1054 if (type == 1 && *ptr++ != ')') 1055 { 1056 as_bad (_("expected closing paren")); 1057 return; 1058 } 1059 operand[0].mode = RS32; 1060 operand[1].mode = RD32; 1061 operand[0].reg = num; 1062 operand[1].reg = num2; 1063 } 1064 1065 /* Passed a pointer to a list of opcodes which use different 1066 addressing modes, return the opcode which matches the opcodes 1067 provided. */ 1068 1069 static const struct h8_instruction * 1070 get_specific (const struct h8_instruction *instruction, 1071 struct h8_op *operands, int size) 1072 { 1073 const struct h8_instruction *this_try = instruction; 1074 const struct h8_instruction *found_other = 0, *found_mismatched = 0; 1075 int found = 0; 1076 int this_index = instruction->idx; 1077 int noperands = 0; 1078 1079 /* There's only one ldm/stm and it's easier to just 1080 get out quick for them. */ 1081 if (OP_KIND (instruction->opcode->how) == O_LDM 1082 || OP_KIND (instruction->opcode->how) == O_STM) 1083 return this_try; 1084 1085 while (noperands < 3 && operands[noperands].mode != 0) 1086 noperands++; 1087 1088 while (this_index == instruction->idx && !found) 1089 { 1090 int this_size; 1091 1092 found = 1; 1093 this_try = instruction++; 1094 this_size = this_try->opcode->how & SN; 1095 1096 if (this_try->noperands != noperands) 1097 found = 0; 1098 else if (this_try->noperands > 0) 1099 { 1100 int i; 1101 1102 for (i = 0; i < this_try->noperands && found; i++) 1103 { 1104 op_type op = this_try->opcode->args.nib[i]; 1105 int op_mode = op & MODE; 1106 int op_size = op & SIZE; 1107 int x = operands[i].mode; 1108 int x_mode = x & MODE; 1109 int x_size = x & SIZE; 1110 1111 if (op_mode == LOWREG && (x_mode == REG || x_mode == LOWREG)) 1112 { 1113 if ((x_size == L_8 && (operands[i].reg & 8) == 0) 1114 || (x_size == L_16 && (operands[i].reg & 8) == 8)) 1115 as_warn (_("can't use high part of register in operand %d"), i); 1116 1117 if (x_size != op_size) 1118 found = 0; 1119 } 1120 else if (op_mode == REG) 1121 { 1122 if (x_mode == LOWREG) 1123 x_mode = REG; 1124 if (x_mode != REG) 1125 found = 0; 1126 1127 if (x_size == L_P) 1128 x_size = (Hmode ? L_32 : L_16); 1129 if (op_size == L_P) 1130 op_size = (Hmode ? L_32 : L_16); 1131 1132 /* The size of the reg is v important. */ 1133 if (op_size != x_size) 1134 found = 0; 1135 } 1136 else if (op_mode & CTRL) /* control register */ 1137 { 1138 if (!(x_mode & CTRL)) 1139 found = 0; 1140 1141 switch (x_mode) 1142 { 1143 case CCR: 1144 if (op_mode != CCR && 1145 op_mode != CCR_EXR && 1146 op_mode != CC_EX_VB_SB) 1147 found = 0; 1148 break; 1149 case EXR: 1150 if (op_mode != EXR && 1151 op_mode != CCR_EXR && 1152 op_mode != CC_EX_VB_SB) 1153 found = 0; 1154 break; 1155 case MACH: 1156 if (op_mode != MACH && 1157 op_mode != MACREG) 1158 found = 0; 1159 break; 1160 case MACL: 1161 if (op_mode != MACL && 1162 op_mode != MACREG) 1163 found = 0; 1164 break; 1165 case VBR: 1166 if (op_mode != VBR && 1167 op_mode != VBR_SBR && 1168 op_mode != CC_EX_VB_SB) 1169 found = 0; 1170 break; 1171 case SBR: 1172 if (op_mode != SBR && 1173 op_mode != VBR_SBR && 1174 op_mode != CC_EX_VB_SB) 1175 found = 0; 1176 break; 1177 } 1178 } 1179 else if ((op & ABSJMP) && (x_mode == ABS || x_mode == PCREL)) 1180 { 1181 operands[i].mode &= ~MODE; 1182 operands[i].mode |= ABSJMP; 1183 /* But it may not be 24 bits long. */ 1184 if (x_mode == ABS && !Hmode) 1185 { 1186 operands[i].mode &= ~SIZE; 1187 operands[i].mode |= L_16; 1188 } 1189 if ((operands[i].mode & SIZE) == L_32 1190 && (op_mode & SIZE) != L_32) 1191 found = 0; 1192 } 1193 else if (x_mode == IMM && op_mode != IMM) 1194 { 1195 offsetT num = operands[i].exp.X_add_number & 0xffffffff; 1196 if (op_mode == KBIT || op_mode == DBIT) 1197 /* This is ok if the immediate value is sensible. */; 1198 else if (op_mode == CONST_2) 1199 found = num == 2; 1200 else if (op_mode == CONST_4) 1201 found = num == 4; 1202 else if (op_mode == CONST_8) 1203 found = num == 8; 1204 else if (op_mode == CONST_16) 1205 found = num == 16; 1206 else 1207 found = 0; 1208 } 1209 else if (op_mode == PCREL && op_mode == x_mode) 1210 { 1211 /* movsd, bsr/bc and bsr/bs only come in PCREL16 flavour: 1212 If x_size is L_8, promote it. */ 1213 if (OP_KIND (this_try->opcode->how) == O_MOVSD 1214 || OP_KIND (this_try->opcode->how) == O_BSRBC 1215 || OP_KIND (this_try->opcode->how) == O_BSRBS) 1216 if (x_size == L_8) 1217 x_size = L_16; 1218 1219 /* The size of the displacement is important. */ 1220 if (op_size != x_size) 1221 found = 0; 1222 } 1223 else if ((op_mode == DISP || op_mode == IMM || op_mode == ABS 1224 || op_mode == INDEXB || op_mode == INDEXW 1225 || op_mode == INDEXL) 1226 && op_mode == x_mode) 1227 { 1228 /* Promote a L_24 to L_32 if it makes us match. */ 1229 if (x_size == L_24 && op_size == L_32) 1230 { 1231 x &= ~SIZE; 1232 x |= x_size = L_32; 1233 } 1234 1235 if (((x_size == L_16 && op_size == L_16U) 1236 || (x_size == L_8 && op_size == L_8U) 1237 || (x_size == L_3 && op_size == L_3NZ)) 1238 /* We're deliberately more permissive for ABS modes. */ 1239 && (op_mode == ABS 1240 || constant_fits_size_p (operands + i, op_size, 1241 op & NO_SYMBOLS))) 1242 x_size = op_size; 1243 1244 if (x_size != 0 && op_size != x_size) 1245 found = 0; 1246 else if (x_size == 0 1247 && ! constant_fits_size_p (operands + i, op_size, 1248 op & NO_SYMBOLS)) 1249 found = 0; 1250 } 1251 else if (op_mode != x_mode) 1252 { 1253 found = 0; 1254 } 1255 } 1256 } 1257 if (found) 1258 { 1259 if ((this_try->opcode->available == AV_H8SX && ! SXmode) 1260 || (this_try->opcode->available == AV_H8S && ! Smode) 1261 || (this_try->opcode->available == AV_H8H && ! Hmode)) 1262 found = 0, found_other = this_try; 1263 else if (this_size != size && (this_size != SN && size != SN)) 1264 found_mismatched = this_try, found = 0; 1265 1266 } 1267 } 1268 if (found) 1269 return this_try; 1270 if (found_other) 1271 { 1272 as_warn (_("Opcode `%s' with these operand types not available in %s mode"), 1273 found_other->opcode->name, 1274 (! Hmode && ! Smode ? "H8/300" 1275 : SXmode ? "H8sx" 1276 : Smode ? "H8/300S" 1277 : "H8/300H")); 1278 } 1279 else if (found_mismatched) 1280 { 1281 as_warn (_("mismatch between opcode size and operand size")); 1282 return found_mismatched; 1283 } 1284 return 0; 1285 } 1286 1287 static void 1288 check_operand (struct h8_op *operand, unsigned int width, const char *string) 1289 { 1290 if (operand->exp.X_add_symbol == 0 1291 && operand->exp.X_op_symbol == 0) 1292 { 1293 /* No symbol involved, let's look at offset, it's dangerous if 1294 any of the high bits are not 0 or ff's, find out by oring or 1295 anding with the width and seeing if the answer is 0 or all 1296 fs. */ 1297 1298 if (! constant_fits_width_p (operand, width)) 1299 { 1300 if (width == 255 1301 && (operand->exp.X_add_number & 0xff00) == 0xff00) 1302 { 1303 /* Just ignore this one - which happens when trying to 1304 fit a 16 bit address truncated into an 8 bit address 1305 of something like bset. */ 1306 } 1307 else if (strcmp (string, "@") == 0 1308 && width == 0xffff 1309 && (operand->exp.X_add_number & 0xff8000) == 0xff8000) 1310 { 1311 /* Just ignore this one - which happens when trying to 1312 fit a 24 bit address truncated into a 16 bit address 1313 of something like mov.w. */ 1314 } 1315 else 1316 { 1317 as_warn (_("operand %s0x%lx out of range."), string, 1318 (unsigned long) operand->exp.X_add_number); 1319 } 1320 } 1321 } 1322 } 1323 1324 /* RELAXMODE has one of 3 values: 1325 1326 0 Output a "normal" reloc, no relaxing possible for this insn/reloc 1327 1328 1 Output a relaxable 24bit absolute mov.w address relocation 1329 (may relax into a 16bit absolute address). 1330 1331 2 Output a relaxable 16/24 absolute mov.b address relocation 1332 (may relax into an 8bit absolute address). */ 1333 1334 static void 1335 do_a_fix_imm (int offset, int nibble, struct h8_op *operand, int relaxmode, const struct h8_instruction *this_try) 1336 { 1337 int idx; 1338 int size; 1339 int where; 1340 char *bytes = frag_now->fr_literal + offset; 1341 1342 const char *t = ((operand->mode & MODE) == IMM) ? "#" : "@"; 1343 1344 if (operand->exp.X_add_symbol == 0) 1345 { 1346 switch (operand->mode & SIZE) 1347 { 1348 case L_2: 1349 check_operand (operand, 0x3, t); 1350 bytes[0] |= (operand->exp.X_add_number & 3) << (nibble ? 0 : 4); 1351 break; 1352 case L_3: 1353 case L_3NZ: 1354 check_operand (operand, 0x7, t); 1355 bytes[0] |= (operand->exp.X_add_number & 7) << (nibble ? 0 : 4); 1356 break; 1357 case L_4: 1358 check_operand (operand, 0xF, t); 1359 bytes[0] |= (operand->exp.X_add_number & 15) << (nibble ? 0 : 4); 1360 break; 1361 case L_5: 1362 check_operand (operand, 0x1F, t); 1363 bytes[0] |= operand->exp.X_add_number & 31; 1364 break; 1365 case L_8: 1366 case L_8U: 1367 check_operand (operand, 0xff, t); 1368 bytes[0] |= operand->exp.X_add_number; 1369 break; 1370 case L_16: 1371 case L_16U: 1372 check_operand (operand, 0xffff, t); 1373 bytes[0] |= operand->exp.X_add_number >> 8; 1374 bytes[1] |= operand->exp.X_add_number >> 0; 1375 #ifdef OBJ_ELF 1376 /* MOVA needs both relocs to relax the second operand properly. */ 1377 if (relaxmode != 0 1378 && (OP_KIND(this_try->opcode->how) == O_MOVAB 1379 || OP_KIND(this_try->opcode->how) == O_MOVAW 1380 || OP_KIND(this_try->opcode->how) == O_MOVAL)) 1381 { 1382 idx = BFD_RELOC_16; 1383 fix_new_exp (frag_now, offset, 2, &operand->exp, 0, idx); 1384 } 1385 #endif 1386 break; 1387 case L_24: 1388 check_operand (operand, 0xffffff, t); 1389 bytes[0] |= operand->exp.X_add_number >> 16; 1390 bytes[1] |= operand->exp.X_add_number >> 8; 1391 bytes[2] |= operand->exp.X_add_number >> 0; 1392 break; 1393 1394 case L_32: 1395 /* This should be done with bfd. */ 1396 bytes[0] |= operand->exp.X_add_number >> 24; 1397 bytes[1] |= operand->exp.X_add_number >> 16; 1398 bytes[2] |= operand->exp.X_add_number >> 8; 1399 bytes[3] |= operand->exp.X_add_number >> 0; 1400 if (relaxmode != 0) 1401 { 1402 #ifdef OBJ_ELF 1403 if ((operand->mode & MODE) == DISP && relaxmode == 1) 1404 idx = BFD_RELOC_H8_DISP32A16; 1405 else 1406 #endif 1407 idx = (relaxmode == 2) ? R_MOV24B1 : R_MOVL1; 1408 fix_new_exp (frag_now, offset, 4, &operand->exp, 0, idx); 1409 } 1410 break; 1411 } 1412 } 1413 else 1414 { 1415 switch (operand->mode & SIZE) 1416 { 1417 case L_24: 1418 case L_32: 1419 size = 4; 1420 where = (operand->mode & SIZE) == L_24 ? -1 : 0; 1421 #ifdef OBJ_ELF 1422 if ((operand->mode & MODE) == DISP && relaxmode == 1) 1423 idx = BFD_RELOC_H8_DISP32A16; 1424 else 1425 #endif 1426 if (relaxmode == 2) 1427 idx = R_MOV24B1; 1428 else if (relaxmode == 1) 1429 idx = R_MOVL1; 1430 else 1431 idx = R_RELLONG; 1432 break; 1433 default: 1434 as_bad (_("Can't work out size of operand.\n")); 1435 case L_16: 1436 case L_16U: 1437 size = 2; 1438 where = 0; 1439 if (relaxmode == 2) 1440 idx = R_MOV16B1; 1441 else 1442 idx = R_RELWORD; 1443 operand->exp.X_add_number = 1444 ((operand->exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; 1445 operand->exp.X_add_number |= (bytes[0] << 8) | bytes[1]; 1446 break; 1447 case L_8: 1448 size = 1; 1449 where = 0; 1450 idx = R_RELBYTE; 1451 operand->exp.X_add_number = 1452 ((operand->exp.X_add_number & 0xff) ^ 0x80) - 0x80; 1453 operand->exp.X_add_number |= bytes[0]; 1454 } 1455 1456 fix_new_exp (frag_now, 1457 offset + where, 1458 size, 1459 &operand->exp, 1460 0, 1461 idx); 1462 } 1463 } 1464 1465 /* Now we know what sort of opcodes it is, let's build the bytes. */ 1466 1467 static void 1468 build_bytes (const struct h8_instruction *this_try, struct h8_op *operand) 1469 { 1470 int i; 1471 char *output = frag_more (this_try->length); 1472 const op_type *nibble_ptr = this_try->opcode->data.nib; 1473 op_type c; 1474 unsigned int nibble_count = 0; 1475 int op_at[3]; 1476 int nib = 0; 1477 int movb = 0; 1478 char asnibbles[100]; 1479 char *p = asnibbles; 1480 int high, low; 1481 1482 if (!Hmode && this_try->opcode->available != AV_H8) 1483 as_warn (_("Opcode `%s' with these operand types not available in H8/300 mode"), 1484 this_try->opcode->name); 1485 else if (!Smode 1486 && this_try->opcode->available != AV_H8 1487 && this_try->opcode->available != AV_H8H) 1488 as_warn (_("Opcode `%s' with these operand types not available in H8/300H mode"), 1489 this_try->opcode->name); 1490 else if (!SXmode 1491 && this_try->opcode->available != AV_H8 1492 && this_try->opcode->available != AV_H8H 1493 && this_try->opcode->available != AV_H8S) 1494 as_warn (_("Opcode `%s' with these operand types not available in H8/300S mode"), 1495 this_try->opcode->name); 1496 1497 while (*nibble_ptr != (op_type) E) 1498 { 1499 int d; 1500 1501 nib = 0; 1502 c = *nibble_ptr++; 1503 1504 d = (c & OP3) == OP3 ? 2 : (c & DST) == DST ? 1 : 0; 1505 1506 if (c < 16) 1507 nib = c; 1508 else 1509 { 1510 int c2 = c & MODE; 1511 1512 if (c2 == REG || c2 == LOWREG 1513 || c2 == IND || c2 == PREINC || c2 == PREDEC 1514 || c2 == POSTINC || c2 == POSTDEC) 1515 { 1516 nib = operand[d].reg; 1517 if (c2 == LOWREG) 1518 nib &= 7; 1519 } 1520 1521 else if (c & CTRL) /* Control reg operand. */ 1522 nib = operand[d].reg; 1523 1524 else if ((c & DISPREG) == (DISPREG)) 1525 { 1526 nib = operand[d].reg; 1527 } 1528 else if (c2 == ABS) 1529 { 1530 operand[d].mode = c; 1531 op_at[d] = nibble_count; 1532 nib = 0; 1533 } 1534 else if (c2 == IMM || c2 == PCREL || c2 == ABS 1535 || (c & ABSJMP) || c2 == DISP) 1536 { 1537 operand[d].mode = c; 1538 op_at[d] = nibble_count; 1539 nib = 0; 1540 } 1541 else if ((c & IGNORE) || (c & DATA)) 1542 nib = 0; 1543 1544 else if (c2 == DBIT) 1545 { 1546 switch (operand[0].exp.X_add_number) 1547 { 1548 case 1: 1549 nib = c; 1550 break; 1551 case 2: 1552 nib = 0x8 | c; 1553 break; 1554 default: 1555 as_bad (_("Need #1 or #2 here")); 1556 } 1557 } 1558 else if (c2 == KBIT) 1559 { 1560 switch (operand[0].exp.X_add_number) 1561 { 1562 case 1: 1563 nib = 0; 1564 break; 1565 case 2: 1566 nib = 8; 1567 break; 1568 case 4: 1569 if (!Hmode) 1570 as_warn (_("#4 not valid on H8/300.")); 1571 nib = 9; 1572 break; 1573 1574 default: 1575 as_bad (_("Need #1 or #2 here")); 1576 break; 1577 } 1578 /* Stop it making a fix. */ 1579 operand[0].mode = 0; 1580 } 1581 1582 if (c & MEMRELAX) 1583 operand[d].mode |= MEMRELAX; 1584 1585 if (c & B31) 1586 nib |= 0x8; 1587 1588 if (c & B21) 1589 nib |= 0x4; 1590 1591 if (c & B11) 1592 nib |= 0x2; 1593 1594 if (c & B01) 1595 nib |= 0x1; 1596 1597 if (c2 == MACREG) 1598 { 1599 if (operand[0].mode == MACREG) 1600 /* stmac has mac[hl] as the first operand. */ 1601 nib = 2 + operand[0].reg; 1602 else 1603 /* ldmac has mac[hl] as the second operand. */ 1604 nib = 2 + operand[1].reg; 1605 } 1606 } 1607 nibble_count++; 1608 1609 *p++ = nib; 1610 } 1611 1612 /* Disgusting. Why, oh why didn't someone ask us for advice 1613 on the assembler format. */ 1614 if (OP_KIND (this_try->opcode->how) == O_LDM) 1615 { 1616 high = (operand[1].reg >> 8) & 0xf; 1617 low = (operand[1].reg) & 0xf; 1618 asnibbles[2] = high - low; 1619 asnibbles[7] = high; 1620 } 1621 else if (OP_KIND (this_try->opcode->how) == O_STM) 1622 { 1623 high = (operand[0].reg >> 8) & 0xf; 1624 low = (operand[0].reg) & 0xf; 1625 asnibbles[2] = high - low; 1626 asnibbles[7] = low; 1627 } 1628 1629 for (i = 0; i < this_try->length; i++) 1630 output[i] = (asnibbles[i * 2] << 4) | asnibbles[i * 2 + 1]; 1631 1632 /* Note if this is a mov.b or a bit manipulation instruction 1633 there is a special relaxation which only applies. */ 1634 if ( this_try->opcode->how == O (O_MOV, SB) 1635 || this_try->opcode->how == O (O_BCLR, SB) 1636 || this_try->opcode->how == O (O_BAND, SB) 1637 || this_try->opcode->how == O (O_BIAND, SB) 1638 || this_try->opcode->how == O (O_BILD, SB) 1639 || this_try->opcode->how == O (O_BIOR, SB) 1640 || this_try->opcode->how == O (O_BIST, SB) 1641 || this_try->opcode->how == O (O_BIXOR, SB) 1642 || this_try->opcode->how == O (O_BLD, SB) 1643 || this_try->opcode->how == O (O_BNOT, SB) 1644 || this_try->opcode->how == O (O_BOR, SB) 1645 || this_try->opcode->how == O (O_BSET, SB) 1646 || this_try->opcode->how == O (O_BST, SB) 1647 || this_try->opcode->how == O (O_BTST, SB) 1648 || this_try->opcode->how == O (O_BXOR, SB)) 1649 movb = 1; 1650 1651 /* Output any fixes. */ 1652 for (i = 0; i < this_try->noperands; i++) 1653 { 1654 int x = operand[i].mode; 1655 int x_mode = x & MODE; 1656 1657 if (x_mode == IMM || x_mode == DISP) 1658 { 1659 #ifndef OBJ_ELF 1660 /* Remove MEMRELAX flag added in h8300.h on mov with 1661 addressing mode "register indirect with displacement". */ 1662 if (x_mode == DISP) 1663 x &= ~MEMRELAX; 1664 #endif 1665 do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2, 1666 op_at[i] & 1, operand + i, (x & MEMRELAX) != 0, 1667 this_try); 1668 } 1669 else if (x_mode == ABS) 1670 do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2, 1671 op_at[i] & 1, operand + i, 1672 (x & MEMRELAX) ? movb + 1 : 0, 1673 this_try); 1674 1675 else if (x_mode == PCREL) 1676 { 1677 int size16 = (x & SIZE) == L_16; 1678 int size = size16 ? 2 : 1; 1679 int type = size16 ? R_PCRWORD : R_PCRBYTE; 1680 fixS *fixP; 1681 1682 check_operand (operand + i, size16 ? 0x7fff : 0x7f, "@"); 1683 1684 if (operand[i].exp.X_add_number & 1) 1685 as_warn (_("branch operand has odd offset (%lx)\n"), 1686 (unsigned long) operand->exp.X_add_number); 1687 #ifndef OBJ_ELF 1688 /* The COFF port has always been off by one, changing it 1689 now would be an incompatible change, so we leave it as-is. 1690 1691 We don't want to do this for ELF as we want to be 1692 compatible with the proposed ELF format from Hitachi. */ 1693 operand[i].exp.X_add_number -= 1; 1694 #endif 1695 if (size16) 1696 { 1697 operand[i].exp.X_add_number = 1698 ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; 1699 } 1700 else 1701 { 1702 operand[i].exp.X_add_number = 1703 ((operand[i].exp.X_add_number & 0xff) ^ 0x80) - 0x80; 1704 } 1705 1706 /* For BRA/S. */ 1707 if (! size16) 1708 operand[i].exp.X_add_number |= output[op_at[i] / 2]; 1709 1710 fixP = fix_new_exp (frag_now, 1711 output - frag_now->fr_literal + op_at[i] / 2, 1712 size, 1713 &operand[i].exp, 1714 1, 1715 type); 1716 fixP->fx_signed = 1; 1717 } 1718 else if (x_mode == MEMIND) 1719 { 1720 check_operand (operand + i, 0xff, "@@"); 1721 fix_new_exp (frag_now, 1722 output - frag_now->fr_literal + 1, 1723 1, 1724 &operand[i].exp, 1725 0, 1726 R_MEM_INDIRECT); 1727 } 1728 else if (x_mode == VECIND) 1729 { 1730 check_operand (operand + i, 0x7f, "@@"); 1731 /* FIXME: approximating the effect of "B31" here... 1732 This is very hackish, and ought to be done a better way. */ 1733 operand[i].exp.X_add_number |= 0x80; 1734 fix_new_exp (frag_now, 1735 output - frag_now->fr_literal + 1, 1736 1, 1737 &operand[i].exp, 1738 0, 1739 R_MEM_INDIRECT); 1740 } 1741 else if (x & ABSJMP) 1742 { 1743 int where = 0; 1744 bfd_reloc_code_real_type reloc_type = R_JMPL1; 1745 1746 #ifdef OBJ_ELF 1747 /* To be compatible with the proposed H8 ELF format, we 1748 want the relocation's offset to point to the first byte 1749 that will be modified, not to the start of the instruction. */ 1750 1751 if ((operand->mode & SIZE) == L_32) 1752 { 1753 where = 2; 1754 reloc_type = R_RELLONG; 1755 } 1756 else 1757 where = 1; 1758 #endif 1759 1760 /* This jmp may be a jump or a branch. */ 1761 1762 check_operand (operand + i, 1763 SXmode ? 0xffffffff : Hmode ? 0xffffff : 0xffff, 1764 "@"); 1765 1766 if (operand[i].exp.X_add_number & 1) 1767 as_warn (_("branch operand has odd offset (%lx)\n"), 1768 (unsigned long) operand->exp.X_add_number); 1769 1770 if (!Hmode) 1771 operand[i].exp.X_add_number = 1772 ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; 1773 fix_new_exp (frag_now, 1774 output - frag_now->fr_literal + where, 1775 4, 1776 &operand[i].exp, 1777 0, 1778 reloc_type); 1779 } 1780 } 1781 } 1782 1783 /* Try to give an intelligent error message for common and simple to 1784 detect errors. */ 1785 1786 static void 1787 clever_message (const struct h8_instruction *instruction, 1788 struct h8_op *operand) 1789 { 1790 /* Find out if there was more than one possible opcode. */ 1791 1792 if ((instruction + 1)->idx != instruction->idx) 1793 { 1794 int argn; 1795 1796 /* Only one opcode of this flavour, try to guess which operand 1797 didn't match. */ 1798 for (argn = 0; argn < instruction->noperands; argn++) 1799 { 1800 switch (instruction->opcode->args.nib[argn]) 1801 { 1802 case RD16: 1803 if (operand[argn].mode != RD16) 1804 { 1805 as_bad (_("destination operand must be 16 bit register")); 1806 return; 1807 1808 } 1809 break; 1810 1811 case RS8: 1812 if (operand[argn].mode != RS8) 1813 { 1814 as_bad (_("source operand must be 8 bit register")); 1815 return; 1816 } 1817 break; 1818 1819 case ABS16DST: 1820 if (operand[argn].mode != ABS16DST) 1821 { 1822 as_bad (_("destination operand must be 16bit absolute address")); 1823 return; 1824 } 1825 break; 1826 case RD8: 1827 if (operand[argn].mode != RD8) 1828 { 1829 as_bad (_("destination operand must be 8 bit register")); 1830 return; 1831 } 1832 break; 1833 1834 case ABS16SRC: 1835 if (operand[argn].mode != ABS16SRC) 1836 { 1837 as_bad (_("source operand must be 16bit absolute address")); 1838 return; 1839 } 1840 break; 1841 1842 } 1843 } 1844 } 1845 as_bad (_("invalid operands")); 1846 } 1847 1848 1849 /* If OPERAND is part of an address, adjust its size and value given 1850 that it addresses SIZE bytes. 1851 1852 This function decides how big non-immediate constants are when no 1853 size was explicitly given. It also scales down the assembly-level 1854 displacement in an @(d:2,ERn) operand. */ 1855 1856 static void 1857 fix_operand_size (struct h8_op *operand, int size) 1858 { 1859 if (SXmode && (operand->mode & MODE) == DISP) 1860 { 1861 /* If the user didn't specify an operand width, see if we 1862 can use @(d:2,ERn). */ 1863 if ((operand->mode & SIZE) == 0 1864 && operand->exp.X_add_symbol == 0 1865 && operand->exp.X_op_symbol == 0 1866 && (operand->exp.X_add_number == size 1867 || operand->exp.X_add_number == size * 2 1868 || operand->exp.X_add_number == size * 3)) 1869 operand->mode |= L_2; 1870 1871 /* Scale down the displacement in an @(d:2,ERn) operand. 1872 X_add_number then contains the desired field value. */ 1873 if ((operand->mode & SIZE) == L_2) 1874 { 1875 if (operand->exp.X_add_number % size != 0) 1876 as_warn (_("operand/size mis-match")); 1877 operand->exp.X_add_number /= size; 1878 } 1879 } 1880 1881 if ((operand->mode & SIZE) == 0) 1882 switch (operand->mode & MODE) 1883 { 1884 case DISP: 1885 case INDEXB: 1886 case INDEXW: 1887 case INDEXL: 1888 case ABS: 1889 /* Pick a 24-bit address unless we know that a 16-bit address 1890 is safe. get_specific() will relax L_24 into L_32 where 1891 necessary. */ 1892 if (Hmode 1893 && !Nmode 1894 && ((((addressT) operand->exp.X_add_number + 0x8000) 1895 & 0xffffffff) > 0xffff 1896 || operand->exp.X_add_symbol != 0 1897 || operand->exp.X_op_symbol != 0)) 1898 operand->mode |= L_24; 1899 else 1900 operand->mode |= L_16; 1901 break; 1902 1903 case PCREL: 1904 if ((((addressT) operand->exp.X_add_number + 0x80) 1905 & 0xffffffff) <= 0xff) 1906 { 1907 if (operand->exp.X_add_symbol != NULL) 1908 operand->mode |= bsize; 1909 else 1910 operand->mode |= L_8; 1911 } 1912 else 1913 operand->mode |= L_16; 1914 break; 1915 } 1916 } 1917 1918 1919 /* This is the guts of the machine-dependent assembler. STR points to 1920 a machine dependent instruction. This function is supposed to emit 1921 the frags/bytes it assembles. */ 1922 1923 void 1924 md_assemble (char *str) 1925 { 1926 char *op_start; 1927 char *op_end; 1928 struct h8_op operand[3]; 1929 const struct h8_instruction *instruction; 1930 const struct h8_instruction *prev_instruction; 1931 1932 char *dot = 0; 1933 char *slash = 0; 1934 char c; 1935 int size, i; 1936 1937 /* Drop leading whitespace. */ 1938 while (*str == ' ') 1939 str++; 1940 1941 /* Find the op code end. */ 1942 for (op_start = op_end = str; 1943 *op_end != 0 && *op_end != ' '; 1944 op_end++) 1945 { 1946 if (*op_end == '.') 1947 { 1948 dot = op_end + 1; 1949 *op_end = 0; 1950 op_end += 2; 1951 break; 1952 } 1953 else if (*op_end == '/' && ! slash) 1954 slash = op_end; 1955 } 1956 1957 if (op_end == op_start) 1958 { 1959 as_bad (_("can't find opcode ")); 1960 } 1961 c = *op_end; 1962 1963 *op_end = 0; 1964 1965 /* The assembler stops scanning the opcode at slashes, so it fails 1966 to make characters following them lower case. Fix them. */ 1967 if (slash) 1968 while (*++slash) 1969 *slash = TOLOWER (*slash); 1970 1971 instruction = (const struct h8_instruction *) 1972 hash_find (opcode_hash_control, op_start); 1973 1974 if (instruction == NULL) 1975 { 1976 as_bad (_("unknown opcode")); 1977 return; 1978 } 1979 1980 /* We used to set input_line_pointer to the result of get_operands, 1981 but that is wrong. Our caller assumes we don't change it. */ 1982 1983 operand[0].mode = 0; 1984 operand[1].mode = 0; 1985 operand[2].mode = 0; 1986 1987 if (OP_KIND (instruction->opcode->how) == O_MOVAB 1988 || OP_KIND (instruction->opcode->how) == O_MOVAW 1989 || OP_KIND (instruction->opcode->how) == O_MOVAL) 1990 get_mova_operands (op_end, operand); 1991 else if (OP_KIND (instruction->opcode->how) == O_RTEL 1992 || OP_KIND (instruction->opcode->how) == O_RTSL) 1993 get_rtsl_operands (op_end, operand); 1994 else 1995 get_operands (instruction->noperands, op_end, operand); 1996 1997 *op_end = c; 1998 prev_instruction = instruction; 1999 2000 /* Now we have operands from instruction. 2001 Let's check them out for ldm and stm. */ 2002 if (OP_KIND (instruction->opcode->how) == O_LDM) 2003 { 2004 /* The first operand must be @er7+, and the 2005 second operand must be a register pair. */ 2006 if ((operand[0].mode != RSINC) 2007 || (operand[0].reg != 7) 2008 || ((operand[1].reg & 0x80000000) == 0)) 2009 as_bad (_("invalid operand in ldm")); 2010 } 2011 else if (OP_KIND (instruction->opcode->how) == O_STM) 2012 { 2013 /* The first operand must be a register pair, 2014 and the second operand must be @-er7. */ 2015 if (((operand[0].reg & 0x80000000) == 0) 2016 || (operand[1].mode != RDDEC) 2017 || (operand[1].reg != 7)) 2018 as_bad (_("invalid operand in stm")); 2019 } 2020 2021 size = SN; 2022 if (dot) 2023 { 2024 switch (TOLOWER (*dot)) 2025 { 2026 case 'b': 2027 size = SB; 2028 break; 2029 2030 case 'w': 2031 size = SW; 2032 break; 2033 2034 case 'l': 2035 size = SL; 2036 break; 2037 } 2038 } 2039 if (OP_KIND (instruction->opcode->how) == O_MOVAB || 2040 OP_KIND (instruction->opcode->how) == O_MOVAW || 2041 OP_KIND (instruction->opcode->how) == O_MOVAL) 2042 { 2043 switch (operand[0].mode & MODE) 2044 { 2045 case INDEXB: 2046 default: 2047 fix_operand_size (&operand[1], 1); 2048 break; 2049 case INDEXW: 2050 fix_operand_size (&operand[1], 2); 2051 break; 2052 case INDEXL: 2053 fix_operand_size (&operand[1], 4); 2054 break; 2055 } 2056 } 2057 else 2058 { 2059 for (i = 0; i < 3 && operand[i].mode != 0; i++) 2060 switch (size) 2061 { 2062 case SN: 2063 case SB: 2064 default: 2065 fix_operand_size (&operand[i], 1); 2066 break; 2067 case SW: 2068 fix_operand_size (&operand[i], 2); 2069 break; 2070 case SL: 2071 fix_operand_size (&operand[i], 4); 2072 break; 2073 } 2074 } 2075 2076 instruction = get_specific (instruction, operand, size); 2077 2078 if (instruction == 0) 2079 { 2080 /* Couldn't find an opcode which matched the operands. */ 2081 char *where = frag_more (2); 2082 2083 where[0] = 0x0; 2084 where[1] = 0x0; 2085 clever_message (prev_instruction, operand); 2086 2087 return; 2088 } 2089 2090 build_bytes (instruction, operand); 2091 2092 dwarf2_emit_insn (instruction->length); 2093 } 2094 2095 symbolS * 2096 md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 2097 { 2098 return 0; 2099 } 2100 2101 /* Various routines to kill one day. */ 2102 2103 const char * 2104 md_atof (int type, char *litP, int *sizeP) 2105 { 2106 return ieee_md_atof (type, litP, sizeP, TRUE); 2107 } 2108 2109 #define OPTION_H_TICK_HEX (OPTION_MD_BASE) 2111 #define OPTION_MACH (OPTION_MD_BASE+1) 2112 2113 const char *md_shortopts = ""; 2114 struct option md_longopts[] = 2115 { 2116 { "h-tick-hex", no_argument, NULL, OPTION_H_TICK_HEX }, 2117 { "mach", required_argument, NULL, OPTION_MACH }, 2118 {NULL, no_argument, NULL, 0} 2119 }; 2120 2121 size_t md_longopts_size = sizeof (md_longopts); 2122 2123 struct mach_func 2124 { 2125 const char *name; 2126 void (*func) (void); 2127 }; 2128 2129 static void 2130 mach_h8300h (void) 2131 { 2132 Hmode = 1; 2133 Smode = 0; 2134 Nmode = 0; 2135 SXmode = 0; 2136 default_mach = bfd_mach_h8300h; 2137 } 2138 2139 static void 2140 mach_h8300hn (void) 2141 { 2142 Hmode = 1; 2143 Smode = 0; 2144 Nmode = 1; 2145 SXmode = 0; 2146 default_mach = bfd_mach_h8300hn; 2147 } 2148 2149 static void 2150 mach_h8300s (void) 2151 { 2152 Hmode = 1; 2153 Smode = 1; 2154 Nmode = 0; 2155 SXmode = 0; 2156 default_mach = bfd_mach_h8300s; 2157 } 2158 2159 static void 2160 mach_h8300sn (void) 2161 { 2162 Hmode = 1; 2163 Smode = 1; 2164 Nmode = 1; 2165 SXmode = 0; 2166 default_mach = bfd_mach_h8300sn; 2167 } 2168 2169 static void 2170 mach_h8300sx (void) 2171 { 2172 Hmode = 1; 2173 Smode = 1; 2174 Nmode = 0; 2175 SXmode = 1; 2176 default_mach = bfd_mach_h8300sx; 2177 } 2178 2179 static void 2180 mach_h8300sxn (void) 2181 { 2182 Hmode = 1; 2183 Smode = 1; 2184 Nmode = 1; 2185 SXmode = 1; 2186 default_mach = bfd_mach_h8300sxn; 2187 } 2188 2189 const struct mach_func mach_table[] = 2190 { 2191 {"h8300h", mach_h8300h}, 2192 {"h8300hn", mach_h8300hn}, 2193 {"h8300s", mach_h8300s}, 2194 {"h8300sn", mach_h8300sn}, 2195 {"h8300sx", mach_h8300sx}, 2196 {"h8300sxn", mach_h8300sxn} 2197 }; 2198 2199 int 2200 md_parse_option (int c ATTRIBUTE_UNUSED, const char *arg ATTRIBUTE_UNUSED) 2201 { 2202 unsigned int i; 2203 switch (c) 2204 { 2205 case OPTION_H_TICK_HEX: 2206 enable_h_tick_hex = 1; 2207 break; 2208 case OPTION_MACH: 2209 for (i = 0; i < sizeof(mach_table) / sizeof(struct mach_func); i++) 2210 { 2211 if (strcasecmp (arg, mach_table[i].name) == 0) 2212 { 2213 mach_table[i].func(); 2214 break; 2215 } 2216 } 2217 if (i >= sizeof(mach_table) / sizeof(struct mach_func)) 2218 as_bad (_("Invalid argument to --mach option: %s"), arg); 2219 break; 2220 default: 2221 return 0; 2222 } 2223 return 1; 2224 } 2225 2226 void 2227 md_show_usage (FILE *stream) 2228 { 2229 fprintf (stream, _(" H8300-specific assembler options:\n")); 2230 fprintf (stream, _("\ 2231 -mach=<name> Set the H8300 machine type to one of:\n\ 2232 h8300h, h8300hn, h8300s, h8300sn, h8300sx, h8300sxn\n")); 2233 fprintf (stream, _("\ 2234 -h-tick-hex Support H'00 style hex constants\n")); 2235 } 2236 2237 void tc_aout_fix_to_chars (void); 2239 2240 void 2241 tc_aout_fix_to_chars (void) 2242 { 2243 printf (_("call to tc_aout_fix_to_chars \n")); 2244 abort (); 2245 } 2246 2247 void 2248 md_convert_frag (bfd *headers ATTRIBUTE_UNUSED, 2249 segT seg ATTRIBUTE_UNUSED, 2250 fragS *fragP ATTRIBUTE_UNUSED) 2251 { 2252 printf (_("call to md_convert_frag \n")); 2253 abort (); 2254 } 2255 2256 valueT 2257 md_section_align (segT segment, valueT size) 2258 { 2259 int align = bfd_get_section_alignment (stdoutput, segment); 2260 return ((size + (1 << align) - 1) & (-1U << align)); 2261 } 2262 2263 void 2264 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) 2265 { 2266 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; 2267 long val = *valP; 2268 2269 switch (fixP->fx_size) 2270 { 2271 case 1: 2272 *buf++ = val; 2273 break; 2274 case 2: 2275 *buf++ = (val >> 8); 2276 *buf++ = val; 2277 break; 2278 case 4: 2279 *buf++ = (val >> 24); 2280 *buf++ = (val >> 16); 2281 *buf++ = (val >> 8); 2282 *buf++ = val; 2283 break; 2284 case 8: 2285 /* This can arise when the .quad or .8byte pseudo-ops are used. 2286 Returning here (without setting fx_done) will cause the code 2287 to attempt to generate a reloc which will then fail with the 2288 slightly more helpful error message: "Cannot represent 2289 relocation type BFD_RELOC_64". */ 2290 return; 2291 default: 2292 abort (); 2293 } 2294 2295 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0) 2296 fixP->fx_done = 1; 2297 } 2298 2299 int 2300 md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED, 2301 segT segment_type ATTRIBUTE_UNUSED) 2302 { 2303 printf (_("call to md_estimate_size_before_relax \n")); 2304 abort (); 2305 } 2306 2307 /* Put number into target byte order. */ 2308 void 2309 md_number_to_chars (char *ptr, valueT use, int nbytes) 2310 { 2311 number_to_chars_bigendian (ptr, use, nbytes); 2312 } 2313 2314 long 2315 md_pcrel_from (fixS *fixp) 2316 { 2317 as_bad_where (fixp->fx_file, fixp->fx_line, 2318 _("Unexpected reference to a symbol in a non-code section")); 2319 return 0; 2320 } 2321 2322 arelent * 2323 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) 2324 { 2325 arelent *rel; 2326 bfd_reloc_code_real_type r_type; 2327 2328 if (fixp->fx_addsy && fixp->fx_subsy) 2329 { 2330 if ((S_GET_SEGMENT (fixp->fx_addsy) != S_GET_SEGMENT (fixp->fx_subsy)) 2331 || S_GET_SEGMENT (fixp->fx_addsy) == undefined_section) 2332 { 2333 as_bad_where (fixp->fx_file, fixp->fx_line, 2334 _("Difference of symbols in different sections is not supported")); 2335 return NULL; 2336 } 2337 } 2338 2339 rel = XNEW (arelent); 2340 rel->sym_ptr_ptr = XNEW (asymbol *); 2341 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 2342 rel->address = fixp->fx_frag->fr_address + fixp->fx_where; 2343 rel->addend = fixp->fx_offset; 2344 2345 r_type = fixp->fx_r_type; 2346 2347 #define DEBUG 0 2348 #if DEBUG 2349 fprintf (stderr, "%s\n", bfd_get_reloc_code_name (r_type)); 2350 fflush (stderr); 2351 #endif 2352 rel->howto = bfd_reloc_type_lookup (stdoutput, r_type); 2353 if (rel->howto == NULL) 2354 { 2355 as_bad_where (fixp->fx_file, fixp->fx_line, 2356 _("Cannot represent relocation type %s"), 2357 bfd_get_reloc_code_name (r_type)); 2358 return NULL; 2359 } 2360 2361 return rel; 2362 } 2363
Indexes created Fri Mar 20 00:23:26 UTC 2026