tc-h8300.c revision 1.9
1 /* tc-h8300.c -- Assemble code for the Renesas H8/300 2 Copyright (C) 1991-2024 Free Software Foundation, Inc. 3 4 This file is part of GAS, the GNU Assembler. 5 6 GAS is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GAS is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GAS; see the file COPYING. If not, write to the Free 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 19 02110-1301, USA. */ 20 21 /* Written By Steve Chamberlain <sac (at) cygnus.com>. */ 22 23 #include "as.h" 24 #include "subsegs.h" 25 #include "dwarf2dbg.h" 26 27 #define DEFINE_TABLE 28 #define h8_opcodes ops 29 #include "opcode/h8300.h" 30 #include "safe-ctype.h" 31 #include "elf/h8.h" 32 33 const char comment_chars[] = ";"; 34 const char line_comment_chars[] = "#"; 35 #ifdef TE_LINUX 36 const char line_separator_chars[] = "!"; 37 #else 38 const char line_separator_chars[] = ""; 39 #endif 40 41 static void sbranch (int); 42 static void h8300hmode (int); 43 static void h8300smode (int); 44 static void h8300hnmode (int); 45 static void h8300snmode (int); 46 static void h8300sxmode (int); 47 static void h8300sxnmode (int); 48 static void pint (int); 49 50 int Hmode; 51 int Smode; 52 int Nmode; 53 int SXmode; 54 55 static int default_mach = bfd_mach_h8300; 56 57 #define PSIZE (Hmode && !Nmode ? L_32 : L_16) 58 59 static int bsize = L_8; /* Default branch displacement. */ 60 61 struct h8_instruction 62 { 63 int length; 64 int noperands; 65 int idx; 66 int size; 67 const struct h8_opcode *opcode; 68 }; 69 70 static struct h8_instruction *h8_instructions; 71 72 static void 73 h8300hmode (int arg ATTRIBUTE_UNUSED) 74 { 75 Hmode = 1; 76 Smode = 0; 77 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300h)) 78 as_warn (_("could not set architecture and machine")); 79 } 80 81 static void 82 h8300smode (int arg ATTRIBUTE_UNUSED) 83 { 84 Smode = 1; 85 Hmode = 1; 86 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300s)) 87 as_warn (_("could not set architecture and machine")); 88 } 89 90 static void 91 h8300hnmode (int arg ATTRIBUTE_UNUSED) 92 { 93 Hmode = 1; 94 Smode = 0; 95 Nmode = 1; 96 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300hn)) 97 as_warn (_("could not set architecture and machine")); 98 } 99 100 static void 101 h8300snmode (int arg ATTRIBUTE_UNUSED) 102 { 103 Smode = 1; 104 Hmode = 1; 105 Nmode = 1; 106 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sn)) 107 as_warn (_("could not set architecture and machine")); 108 } 109 110 static void 111 h8300sxmode (int arg ATTRIBUTE_UNUSED) 112 { 113 Smode = 1; 114 Hmode = 1; 115 SXmode = 1; 116 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sx)) 117 as_warn (_("could not set architecture and machine")); 118 } 119 120 static void 121 h8300sxnmode (int arg ATTRIBUTE_UNUSED) 122 { 123 Smode = 1; 124 Hmode = 1; 125 SXmode = 1; 126 Nmode = 1; 127 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sxn)) 128 as_warn (_("could not set architecture and machine")); 129 } 130 131 static void 132 sbranch (int size) 133 { 134 bsize = size; 135 } 136 137 static void 138 pint (int arg ATTRIBUTE_UNUSED) 139 { 140 cons (Hmode ? 4 : 2); 141 } 142 143 /* Like obj_elf_section, but issues a warning for new 144 sections which do not have an attribute specification. */ 145 146 static void 147 h8300_elf_section (int push) 148 { 149 static const char * known_data_sections [] = { ".rodata", ".tdata", ".tbss" }; 150 static const char * known_data_prefixes [] = { ".debug", ".zdebug", ".gnu.warning" }; 151 char * saved_ilp = input_line_pointer; 152 const char * name; 153 154 name = obj_elf_section_name (); 155 if (name == NULL) 156 return; 157 158 if (* input_line_pointer != ',' 159 && bfd_get_section_by_name (stdoutput, name) == NULL) 160 { 161 signed int i; 162 163 /* Ignore this warning for well known data sections. */ 164 for (i = ARRAY_SIZE (known_data_sections); i--;) 165 if (strcmp (name, known_data_sections[i]) == 0) 166 break; 167 168 if (i < 0) 169 for (i = ARRAY_SIZE (known_data_prefixes); i--;) 170 if (startswith (name, known_data_prefixes[i])) 171 break; 172 173 if (i < 0) 174 as_warn (_("new section '%s' defined without attributes - this might cause problems"), name); 175 } 176 177 /* FIXME: We ought to free the memory allocated by obj_elf_section_name() 178 for 'name', but we do not know if it was taken from the obstack, via 179 demand_copy_C_string(), or xmalloc()ed. */ 180 input_line_pointer = saved_ilp; 181 obj_elf_section (push); 182 } 183 184 /* This table describes all the machine specific pseudo-ops the assembler 185 has to support. The fields are: 186 pseudo-op name without dot 187 function to call to execute this pseudo-op 188 Integer arg to pass to the function. */ 189 190 const pseudo_typeS md_pseudo_table[] = 191 { 192 {"h8300h", h8300hmode, 0}, 193 {"h8300hn", h8300hnmode, 0}, 194 {"h8300s", h8300smode, 0}, 195 {"h8300sn", h8300snmode, 0}, 196 {"h8300sx", h8300sxmode, 0}, 197 {"h8300sxn", h8300sxnmode, 0}, 198 {"sbranch", sbranch, L_8}, 199 {"lbranch", sbranch, L_16}, 200 201 {"int", pint, 0}, 202 {"data.b", cons, 1}, 203 {"data.w", cons, 2}, 204 {"data.l", cons, 4}, 205 {"form", listing_psize, 0}, 206 {"heading", listing_title, 0}, 207 {"import", s_ignore, 0}, 208 {"page", listing_eject, 0}, 209 {"program", s_ignore, 0}, 210 211 {"section", h8300_elf_section, 0}, 212 {"section.s", h8300_elf_section, 0}, 213 {"sect", h8300_elf_section, 0}, 214 {"sect.s", h8300_elf_section, 0}, 215 216 {0, 0, 0} 217 }; 218 219 const char EXP_CHARS[] = "eE"; 220 221 /* Chars that mean this number is a floating point constant 222 As in 0f12.456 223 or 0d1.2345e12. */ 224 const char FLT_CHARS[] = "rRsSfFdDxXpP"; 225 226 static htab_t opcode_hash_control; /* Opcode mnemonics. */ 227 228 /* This function is called once, at assembler startup time. This 229 should set up all the tables, etc. that the MD part of the assembler 230 needs. */ 231 232 void 233 md_begin (void) 234 { 235 unsigned int nopcodes; 236 struct h8_opcode *p, *p1; 237 struct h8_instruction *pi; 238 int idx = 0; 239 240 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, default_mach)) 241 as_warn (_("could not set architecture and machine")); 242 243 opcode_hash_control = str_htab_create (); 244 245 nopcodes = sizeof (h8_opcodes) / sizeof (struct h8_opcode); 246 247 h8_instructions = XNEWVEC (struct h8_instruction, nopcodes); 248 249 pi = h8_instructions; 250 p1 = h8_opcodes; 251 /* We do a minimum amount of sorting on the opcode table; this is to 252 make it easy to describe the mova instructions without unnecessary 253 code duplication. 254 Sorting only takes place inside blocks of instructions of the form 255 X/Y, so for example mova/b, mova/w and mova/l can be intermixed. */ 256 while (p1) 257 { 258 struct h8_opcode *first_skipped = 0; 259 int len, cmplen = 0; 260 const char *src = p1->name; 261 char *dst, *buffer; 262 263 if (p1->name == 0) 264 break; 265 /* Strip off any . part when inserting the opcode and only enter 266 unique codes into the hash table. */ 267 dst = buffer = notes_alloc (strlen (src) + 1); 268 while (*src) 269 { 270 if (*src == '.') 271 { 272 src++; 273 break; 274 } 275 if (*src == '/') 276 cmplen = src - p1->name + 1; 277 *dst++ = *src++; 278 } 279 *dst = 0; 280 len = dst - buffer; 281 if (cmplen == 0) 282 cmplen = len; 283 str_hash_insert (opcode_hash_control, buffer, pi, 0); 284 idx++; 285 286 for (p = p1; p->name; p++) 287 { 288 /* A negative TIME is used to indicate that we've added this opcode 289 already. */ 290 if (p->time == -1) 291 continue; 292 if (strncmp (p->name, buffer, cmplen) != 0 293 || (p->name[cmplen] != '\0' && p->name[cmplen] != '.' 294 && p->name[cmplen - 1] != '/')) 295 { 296 if (first_skipped == 0) 297 first_skipped = p; 298 break; 299 } 300 if (strncmp (p->name, buffer, len) != 0) 301 { 302 if (first_skipped == 0) 303 first_skipped = p; 304 continue; 305 } 306 307 p->time = -1; 308 pi->size = p->name[len] == '.' ? p->name[len + 1] : 0; 309 pi->idx = idx; 310 311 /* Find the number of operands. */ 312 pi->noperands = 0; 313 while (pi->noperands < 3 && p->args.nib[pi->noperands] != (op_type) E) 314 pi->noperands++; 315 316 /* Find the length of the opcode in bytes. */ 317 pi->length = 0; 318 while (p->data.nib[pi->length * 2] != (op_type) E) 319 pi->length++; 320 321 pi->opcode = p; 322 pi++; 323 } 324 p1 = first_skipped; 325 } 326 327 /* Add entry for the NULL vector terminator. */ 328 pi->length = 0; 329 pi->noperands = 0; 330 pi->idx = 0; 331 pi->size = 0; 332 pi->opcode = 0; 333 334 linkrelax = 1; 335 } 336 337 struct h8_op 338 { 339 op_type mode; 340 unsigned reg; 341 expressionS exp; 342 }; 343 344 static void clever_message (const struct h8_instruction *, struct h8_op *); 345 static void fix_operand_size (struct h8_op *, int); 346 static void build_bytes (const struct h8_instruction *, struct h8_op *); 347 static void do_a_fix_imm (int, int, struct h8_op *, int, const struct h8_instruction *); 348 static void check_operand (struct h8_op *, unsigned int, const char *); 349 static const struct h8_instruction * get_specific (const struct h8_instruction *, struct h8_op *, int) ; 350 static char *get_operands (unsigned, char *, struct h8_op *); 351 static void get_operand (char **, struct h8_op *, int); 352 static int parse_reg (char *, op_type *, unsigned *, int); 353 static char *skip_colonthing (char *, int *); 354 static char *parse_exp (char *, struct h8_op *); 355 356 static int constant_fits_size_p (struct h8_op *, int, int); 357 358 /* 359 parse operands 360 WREG r0,r1,r2,r3,r4,r5,r6,r7,fp,sp 361 r0l,r0h,..r7l,r7h 362 @WREG 363 @WREG+ 364 @-WREG 365 #const 366 ccr 367 */ 368 369 /* Try to parse a reg name. Return the number of chars consumed. */ 370 371 static int 372 parse_reg (char *src, op_type *mode, unsigned int *reg, int direction) 373 { 374 char *end; 375 int len; 376 377 /* Cribbed from get_symbol_name. */ 378 if (!is_name_beginner (*src) || *src == '\001') 379 return 0; 380 end = src + 1; 381 while ((is_part_of_name (*end) && *end != '.') || *end == '\001') 382 end++; 383 len = end - src; 384 385 if (len == 2 && TOLOWER (src[0]) == 's' && TOLOWER (src[1]) == 'p') 386 { 387 *mode = PSIZE | REG | direction; 388 *reg = 7; 389 return len; 390 } 391 if (len == 3 && 392 TOLOWER (src[0]) == 'c' && 393 TOLOWER (src[1]) == 'c' && 394 TOLOWER (src[2]) == 'r') 395 { 396 *mode = CCR; 397 *reg = 0; 398 return len; 399 } 400 if (len == 3 && 401 TOLOWER (src[0]) == 'e' && 402 TOLOWER (src[1]) == 'x' && 403 TOLOWER (src[2]) == 'r') 404 { 405 *mode = EXR; 406 *reg = 1; 407 return len; 408 } 409 if (len == 3 && 410 TOLOWER (src[0]) == 'v' && 411 TOLOWER (src[1]) == 'b' && 412 TOLOWER (src[2]) == 'r') 413 { 414 *mode = VBR; 415 *reg = 6; 416 return len; 417 } 418 if (len == 3 && 419 TOLOWER (src[0]) == 's' && 420 TOLOWER (src[1]) == 'b' && 421 TOLOWER (src[2]) == 'r') 422 { 423 *mode = SBR; 424 *reg = 7; 425 return len; 426 } 427 if (len == 2 && TOLOWER (src[0]) == 'f' && TOLOWER (src[1]) == 'p') 428 { 429 *mode = PSIZE | REG | direction; 430 *reg = 6; 431 return len; 432 } 433 if (len == 3 && TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' && 434 src[2] >= '0' && src[2] <= '7') 435 { 436 *mode = L_32 | REG | direction; 437 *reg = src[2] - '0'; 438 if (!Hmode) 439 as_warn (_("Reg not valid for H8/300")); 440 return len; 441 } 442 if (len == 2 && TOLOWER (src[0]) == 'e' && src[1] >= '0' && src[1] <= '7') 443 { 444 *mode = L_16 | REG | direction; 445 *reg = src[1] - '0' + 8; 446 if (!Hmode) 447 as_warn (_("Reg not valid for H8/300")); 448 return len; 449 } 450 451 if (TOLOWER (src[0]) == 'r') 452 { 453 if (src[1] >= '0' && src[1] <= '7') 454 { 455 if (len == 3 && TOLOWER (src[2]) == 'l') 456 { 457 *mode = L_8 | REG | direction; 458 *reg = (src[1] - '0') + 8; 459 return len; 460 } 461 if (len == 3 && TOLOWER (src[2]) == 'h') 462 { 463 *mode = L_8 | REG | direction; 464 *reg = (src[1] - '0'); 465 return len; 466 } 467 if (len == 2) 468 { 469 *mode = L_16 | REG | direction; 470 *reg = (src[1] - '0'); 471 return len; 472 } 473 } 474 } 475 476 return 0; 477 } 478 479 480 /* Parse an immediate or address-related constant and store it in OP. 481 If the user also specifies the operand's size, store that size 482 in OP->MODE, otherwise leave it for later code to decide. */ 483 484 static char * 485 parse_exp (char *src, struct h8_op *op) 486 { 487 char *save; 488 489 save = input_line_pointer; 490 input_line_pointer = src; 491 expression (&op->exp); 492 if (op->exp.X_op == O_absent) 493 as_bad (_("missing operand")); 494 src = input_line_pointer; 495 input_line_pointer = save; 496 497 return skip_colonthing (src, &op->mode); 498 } 499 500 501 /* If SRC starts with an explicit operand size, skip it and store the size 502 in *MODE. Leave *MODE unchanged otherwise. */ 503 504 static char * 505 skip_colonthing (char *src, int *mode) 506 { 507 if (*src == ':') 508 { 509 src++; 510 *mode &= ~SIZE; 511 if (src[0] == '8' && !ISDIGIT (src[1])) 512 *mode |= L_8; 513 else if (src[0] == '2' && !ISDIGIT (src[1])) 514 *mode |= L_2; 515 else if (src[0] == '3' && !ISDIGIT (src[1])) 516 *mode |= L_3; 517 else if (src[0] == '4' && !ISDIGIT (src[1])) 518 *mode |= L_4; 519 else if (src[0] == '5' && !ISDIGIT (src[1])) 520 *mode |= L_5; 521 else if (src[0] == '2' && src[1] == '4' && !ISDIGIT (src[2])) 522 *mode |= L_24; 523 else if (src[0] == '3' && src[1] == '2' && !ISDIGIT (src[2])) 524 *mode |= L_32; 525 else if (src[0] == '1' && src[1] == '6' && !ISDIGIT (src[2])) 526 *mode |= L_16; 527 else 528 as_bad (_("invalid operand size requested")); 529 530 while (ISDIGIT (*src)) 531 src++; 532 } 533 return src; 534 } 535 536 /* The many forms of operand: 537 538 Rn Register direct 539 @Rn Register indirect 540 @(exp[:16], Rn) Register indirect with displacement 541 @Rn+ 542 @-Rn 543 @aa:8 absolute 8 bit 544 @aa:16 absolute 16 bit 545 @aa absolute 16 bit 546 547 #xx[:size] immediate data 548 @(exp:[8], pc) pc rel 549 @@aa[:8] memory indirect. */ 550 551 static int 552 constant_fits_width_p (struct h8_op *operand, offsetT width) 553 { 554 offsetT num; 555 556 num = ((operand->exp.X_add_number & 0xffffffff) ^ 0x80000000) - 0x80000000; 557 return (num & ~width) == 0 || (num | width) == ~0; 558 } 559 560 static int 561 constant_fits_size_p (struct h8_op *operand, int size, int no_symbols) 562 { 563 offsetT num; 564 565 if (no_symbols 566 && (operand->exp.X_add_symbol != 0 || operand->exp.X_op_symbol != 0)) 567 return 0; 568 num = operand->exp.X_add_number & 0xffffffff; 569 switch (size) 570 { 571 case L_2: 572 return (num & ~3) == 0; 573 case L_3: 574 return (num & ~7) == 0; 575 case L_3NZ: 576 return num >= 1 && num < 8; 577 case L_4: 578 return (num & ~15) == 0; 579 case L_5: 580 return num >= 1 && num < 32; 581 case L_8: 582 num = (num ^ 0x80000000) - 0x80000000; 583 return (num & ~0xFF) == 0 || (num | 0x7F) == ~0; 584 case L_8U: 585 return (num & ~0xFF) == 0; 586 case L_16: 587 num = (num ^ 0x80000000) - 0x80000000; 588 return (num & ~0xFFFF) == 0 || (num | 0x7FFF) == ~0; 589 case L_16U: 590 return (num & ~0xFFFF) == 0; 591 case L_32: 592 return 1; 593 default: 594 abort (); 595 } 596 } 597 598 static void 599 get_operand (char **ptr, struct h8_op *op, int direction) 600 { 601 char *src = *ptr; 602 op_type mode; 603 unsigned int num; 604 unsigned int len; 605 606 op->mode = 0; 607 608 /* Check for '(' and ')' for instructions ldm and stm. */ 609 if (src[0] == '(' && src[8] == ')') 610 ++ src; 611 612 /* Gross. Gross. ldm and stm have a format not easily handled 613 by get_operand. We deal with it explicitly here. */ 614 if (TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' && 615 ISDIGIT (src[2]) && src[3] == '-' && 616 TOLOWER (src[4]) == 'e' && TOLOWER (src[5]) == 'r' && ISDIGIT (src[6])) 617 { 618 int low, high; 619 620 low = src[2] - '0'; 621 high = src[6] - '0'; 622 623 /* Check register pair's validity as per tech note TN-H8*-193A/E 624 from Renesas for H8S and H8SX hardware manual. */ 625 if ( !(low == 0 && (high == 1 || high == 2 || high == 3)) 626 && !(low == 1 && (high == 2 || high == 3 || high == 4) && SXmode) 627 && !(low == 2 && (high == 3 || ((high == 4 || high == 5) && SXmode))) 628 && !(low == 3 && (high == 4 || high == 5 || high == 6) && SXmode) 629 && !(low == 4 && (high == 5 || high == 6)) 630 && !(low == 4 && high == 7 && SXmode) 631 && !(low == 5 && (high == 6 || high == 7) && SXmode) 632 && !(low == 6 && high == 7 && SXmode)) 633 as_bad (_("Invalid register list for ldm/stm\n")); 634 635 /* Even sicker. We encode two registers into op->reg. One 636 for the low register to save, the other for the high 637 register to save; we also set the high bit in op->reg 638 so we know this is "very special". */ 639 op->reg = 0x80000000 | (high << 8) | low; 640 op->mode = REG; 641 if (src[7] == ')') 642 *ptr = src + 8; 643 else 644 *ptr = src + 7; 645 return; 646 } 647 648 len = parse_reg (src, &op->mode, &op->reg, direction); 649 if (len) 650 { 651 src += len; 652 if (*src == '.') 653 { 654 int size = op->mode & SIZE; 655 switch (src[1]) 656 { 657 case 'l': case 'L': 658 if (size != L_32) 659 as_warn (_("mismatch between register and suffix")); 660 op->mode = (op->mode & ~MODE) | LOWREG; 661 break; 662 case 'w': case 'W': 663 if (size != L_32 && size != L_16) 664 as_warn (_("mismatch between register and suffix")); 665 op->mode = (op->mode & ~MODE) | LOWREG; 666 op->mode = (op->mode & ~SIZE) | L_16; 667 break; 668 case 'b': case 'B': 669 op->mode = (op->mode & ~MODE) | LOWREG; 670 if (size != L_32 && size != L_8) 671 as_warn (_("mismatch between register and suffix")); 672 op->mode = (op->mode & ~MODE) | LOWREG; 673 op->mode = (op->mode & ~SIZE) | L_8; 674 break; 675 default: 676 as_warn (_("invalid suffix after register.")); 677 break; 678 } 679 src += 2; 680 } 681 *ptr = src; 682 return; 683 } 684 685 if (*src == '@') 686 { 687 src++; 688 if (*src == '@') 689 { 690 *ptr = parse_exp (src + 1, op); 691 if (op->exp.X_add_number >= 0x100) 692 { 693 int divisor = 1; 694 695 op->mode = VECIND; 696 /* FIXME : 2? or 4? */ 697 if (op->exp.X_add_number >= 0x400) 698 as_bad (_("address too high for vector table jmp/jsr")); 699 else if (op->exp.X_add_number >= 0x200) 700 divisor = 4; 701 else 702 divisor = 2; 703 704 op->exp.X_add_number = op->exp.X_add_number / divisor - 0x80; 705 } 706 else 707 op->mode = MEMIND; 708 return; 709 } 710 711 if (*src == '-' || *src == '+') 712 { 713 len = parse_reg (src + 1, &mode, &num, direction); 714 if (len == 0) 715 { 716 /* Oops, not a reg after all, must be ordinary exp. */ 717 op->mode = ABS | direction; 718 *ptr = parse_exp (src, op); 719 return; 720 } 721 722 if (((mode & SIZE) != PSIZE) 723 /* For Normal mode accept 16 bit and 32 bit pointer registers. */ 724 && (!Nmode || ((mode & SIZE) != L_32))) 725 as_bad (_("Wrong size pointer register for architecture.")); 726 727 op->mode = src[0] == '-' ? RDPREDEC : RDPREINC; 728 op->reg = num; 729 *ptr = src + 1 + len; 730 return; 731 } 732 if (*src == '(') 733 { 734 src++; 735 736 /* See if this is @(ERn.x, PC). */ 737 len = parse_reg (src, &mode, &op->reg, direction); 738 if (len != 0 && (mode & MODE) == REG && src[len] == '.') 739 { 740 switch (TOLOWER (src[len + 1])) 741 { 742 case 'b': 743 mode = PCIDXB | direction; 744 break; 745 case 'w': 746 mode = PCIDXW | direction; 747 break; 748 case 'l': 749 mode = PCIDXL | direction; 750 break; 751 default: 752 mode = 0; 753 break; 754 } 755 if (mode 756 && src[len + 2] == ',' 757 && TOLOWER (src[len + 3]) != 'p' 758 && TOLOWER (src[len + 4]) != 'c' 759 && src[len + 5] != ')') 760 { 761 *ptr = src + len + 6; 762 op->mode |= mode; 763 return; 764 } 765 /* Fall through into disp case - the grammar is somewhat 766 ambiguous, so we should try whether it's a DISP operand 767 after all ("ER3.L" might be a poorly named label...). */ 768 } 769 770 /* Disp. */ 771 772 /* Start off assuming a 16 bit offset. */ 773 774 src = parse_exp (src, op); 775 if (*src == ')') 776 { 777 op->mode |= ABS | direction; 778 *ptr = src + 1; 779 return; 780 } 781 782 if (*src != ',') 783 { 784 as_bad (_("expected @(exp, reg16)")); 785 return; 786 } 787 src++; 788 789 len = parse_reg (src, &mode, &op->reg, direction); 790 if (len == 0 || (mode & MODE) != REG) 791 { 792 as_bad (_("expected @(exp, reg16)")); 793 return; 794 } 795 src += len; 796 if (src[0] == '.') 797 { 798 switch (TOLOWER (src[1])) 799 { 800 case 'b': 801 op->mode |= INDEXB | direction; 802 break; 803 case 'w': 804 op->mode |= INDEXW | direction; 805 break; 806 case 'l': 807 op->mode |= INDEXL | direction; 808 break; 809 default: 810 as_bad (_("expected .L, .W or .B for register in indexed addressing mode")); 811 } 812 src += 2; 813 op->reg &= 7; 814 } 815 else 816 op->mode |= DISP | direction; 817 src = skip_colonthing (src, &op->mode); 818 819 if (*src != ')') 820 { 821 as_bad (_("expected @(exp, reg16)")); 822 return; 823 } 824 *ptr = src + 1; 825 return; 826 } 827 len = parse_reg (src, &mode, &num, direction); 828 829 if (len) 830 { 831 src += len; 832 if (*src == '+' || *src == '-') 833 { 834 if (((mode & SIZE) != PSIZE) 835 /* For Normal mode accept 16 bit and 32 bit pointer registers. */ 836 && (!Nmode || ((mode & SIZE) != L_32))) 837 as_bad (_("Wrong size pointer register for architecture.")); 838 op->mode = *src == '+' ? RSPOSTINC : RSPOSTDEC; 839 op->reg = num; 840 src++; 841 *ptr = src; 842 return; 843 } 844 if (((mode & SIZE) != PSIZE) 845 /* For Normal mode accept 16 bit and 32 bit pointer registers. */ 846 && (!Nmode || ((mode & SIZE) != L_32))) 847 as_bad (_("Wrong size pointer register for architecture.")); 848 849 op->mode = direction | IND | PSIZE; 850 op->reg = num; 851 *ptr = src; 852 853 return; 854 } 855 else 856 { 857 /* must be a symbol */ 858 859 op->mode = ABS | direction; 860 *ptr = parse_exp (src, op); 861 return; 862 } 863 } 864 865 if (*src == '#') 866 { 867 op->mode = IMM; 868 *ptr = parse_exp (src + 1, op); 869 return; 870 } 871 else if (startswith (src, "mach") || 872 startswith (src, "macl") || 873 startswith (src, "MACH") || 874 startswith (src, "MACL")) 875 { 876 op->reg = TOLOWER (src[3]) == 'l'; 877 op->mode = MACREG; 878 *ptr = src + 4; 879 return; 880 } 881 else 882 { 883 op->mode = PCREL; 884 *ptr = parse_exp (src, op); 885 } 886 } 887 888 static char * 889 get_operands (unsigned int noperands, char *op_end, struct h8_op *operand) 890 { 891 char *ptr = op_end; 892 893 switch (noperands) 894 { 895 case 0: 896 break; 897 898 case 1: 899 ptr++; 900 get_operand (&ptr, operand + 0, SRC); 901 if (*ptr == ',') 902 { 903 ptr++; 904 get_operand (&ptr, operand + 1, DST); 905 } 906 break; 907 908 case 2: 909 ptr++; 910 get_operand (&ptr, operand + 0, SRC); 911 if (*ptr == ',') 912 ptr++; 913 get_operand (&ptr, operand + 1, DST); 914 break; 915 916 case 3: 917 ptr++; 918 get_operand (&ptr, operand + 0, SRC); 919 if (*ptr == ',') 920 ptr++; 921 get_operand (&ptr, operand + 1, DST); 922 if (*ptr == ',') 923 ptr++; 924 get_operand (&ptr, operand + 2, OP3); 925 break; 926 927 default: 928 abort (); 929 } 930 931 return ptr; 932 } 933 934 /* MOVA has special requirements. Rather than adding twice the amount of 935 addressing modes, we simply special case it a bit. */ 936 static void 937 get_mova_operands (char *op_end, struct h8_op *operand) 938 { 939 char *ptr = op_end; 940 941 if (ptr[1] != '@' || ptr[2] != '(') 942 goto error; 943 ptr += 3; 944 operand[0].mode = 0; 945 ptr = parse_exp (ptr, &operand[0]); 946 947 if (*ptr !=',') 948 goto error; 949 ptr++; 950 get_operand (&ptr, operand + 1, DST); 951 952 if (*ptr =='.') 953 { 954 ptr++; 955 switch (*ptr++) 956 { 957 case 'b': case 'B': 958 operand[0].mode = (operand[0].mode & ~MODE) | INDEXB; 959 break; 960 case 'w': case 'W': 961 operand[0].mode = (operand[0].mode & ~MODE) | INDEXW; 962 break; 963 case 'l': case 'L': 964 operand[0].mode = (operand[0].mode & ~MODE) | INDEXL; 965 break; 966 default: 967 goto error; 968 } 969 } 970 else if ((operand[1].mode & MODE) == LOWREG) 971 { 972 switch (operand[1].mode & SIZE) 973 { 974 case L_8: 975 operand[0].mode = (operand[0].mode & ~MODE) | INDEXB; 976 break; 977 case L_16: 978 operand[0].mode = (operand[0].mode & ~MODE) | INDEXW; 979 break; 980 case L_32: 981 operand[0].mode = (operand[0].mode & ~MODE) | INDEXL; 982 break; 983 default: 984 goto error; 985 } 986 } 987 else 988 goto error; 989 990 if (*ptr++ != ')' || *ptr++ != ',') 991 goto error; 992 get_operand (&ptr, operand + 2, OP3); 993 /* See if we can use the short form of MOVA. */ 994 if (((operand[1].mode & MODE) == REG || (operand[1].mode & MODE) == LOWREG) 995 && (operand[2].mode & MODE) == REG 996 && (operand[1].reg & 7) == (operand[2].reg & 7)) 997 { 998 operand[1].mode = operand[2].mode = 0; 999 operand[0].reg = operand[2].reg & 7; 1000 } 1001 return; 1002 1003 error: 1004 as_bad (_("expected valid addressing mode for mova: \"@(disp, ea.sz),ERn\"")); 1005 } 1006 1007 static void 1008 get_rtsl_operands (char *ptr, struct h8_op *operand) 1009 { 1010 int mode, len, type = 0; 1011 unsigned int num, num2; 1012 1013 ptr++; 1014 if (*ptr == '(') 1015 { 1016 ptr++; 1017 type = 1; 1018 } 1019 len = parse_reg (ptr, &mode, &num, SRC); 1020 if (len == 0 || (mode & MODE) != REG) 1021 { 1022 as_bad (_("expected register")); 1023 return; 1024 } 1025 ptr += len; 1026 if (*ptr == '-') 1027 { 1028 len = parse_reg (++ptr, &mode, &num2, SRC); 1029 if (len == 0 || (mode & MODE) != REG) 1030 { 1031 as_bad (_("expected register")); 1032 return; 1033 } 1034 ptr += len; 1035 /* CONST_xxx are used as placeholders in the opcode table. */ 1036 num = num2 - num; 1037 if (num > 3) 1038 { 1039 as_bad (_("invalid register list")); 1040 return; 1041 } 1042 } 1043 else 1044 num2 = num, num = 0; 1045 if (type == 1 && *ptr++ != ')') 1046 { 1047 as_bad (_("expected closing paren")); 1048 return; 1049 } 1050 operand[0].mode = RS32; 1051 operand[1].mode = RD32; 1052 operand[0].reg = num; 1053 operand[1].reg = num2; 1054 } 1055 1056 /* Passed a pointer to a list of opcodes which use different 1057 addressing modes, return the opcode which matches the opcodes 1058 provided. */ 1059 1060 static const struct h8_instruction * 1061 get_specific (const struct h8_instruction *instruction, 1062 struct h8_op *operands, int size) 1063 { 1064 const struct h8_instruction *this_try = instruction; 1065 const struct h8_instruction *found_other = 0, *found_mismatched = 0; 1066 int found = 0; 1067 int this_index = instruction->idx; 1068 int noperands = 0; 1069 1070 /* There's only one ldm/stm and it's easier to just 1071 get out quick for them. */ 1072 if (OP_KIND (instruction->opcode->how) == O_LDM 1073 || OP_KIND (instruction->opcode->how) == O_STM) 1074 return this_try; 1075 1076 while (noperands < 3 && operands[noperands].mode != 0) 1077 noperands++; 1078 1079 while (this_index == instruction->idx && !found) 1080 { 1081 int this_size; 1082 1083 found = 1; 1084 this_try = instruction++; 1085 this_size = this_try->opcode->how & SN; 1086 1087 if (this_try->noperands != noperands) 1088 found = 0; 1089 else if (this_try->noperands > 0) 1090 { 1091 int i; 1092 1093 for (i = 0; i < this_try->noperands && found; i++) 1094 { 1095 op_type op = this_try->opcode->args.nib[i]; 1096 int op_mode = op & MODE; 1097 int op_size = op & SIZE; 1098 int x = operands[i].mode; 1099 int x_mode = x & MODE; 1100 int x_size = x & SIZE; 1101 1102 if (op_mode == LOWREG && (x_mode == REG || x_mode == LOWREG)) 1103 { 1104 if ((x_size == L_8 && (operands[i].reg & 8) == 0) 1105 || (x_size == L_16 && (operands[i].reg & 8) == 8)) 1106 as_warn (_("can't use high part of register in operand %d"), i); 1107 1108 if (x_size != op_size) 1109 found = 0; 1110 } 1111 else if (op_mode == REG) 1112 { 1113 if (x_mode == LOWREG) 1114 x_mode = REG; 1115 if (x_mode != REG) 1116 found = 0; 1117 1118 if (x_size == L_P) 1119 x_size = (Hmode ? L_32 : L_16); 1120 if (op_size == L_P) 1121 op_size = (Hmode ? L_32 : L_16); 1122 1123 /* The size of the reg is v important. */ 1124 if (op_size != x_size) 1125 found = 0; 1126 } 1127 else if (op_mode & CTRL) /* control register */ 1128 { 1129 if (!(x_mode & CTRL)) 1130 found = 0; 1131 1132 switch (x_mode) 1133 { 1134 case CCR: 1135 if (op_mode != CCR && 1136 op_mode != CCR_EXR && 1137 op_mode != CC_EX_VB_SB) 1138 found = 0; 1139 break; 1140 case EXR: 1141 if (op_mode != EXR && 1142 op_mode != CCR_EXR && 1143 op_mode != CC_EX_VB_SB) 1144 found = 0; 1145 break; 1146 case MACH: 1147 if (op_mode != MACH && 1148 op_mode != MACREG) 1149 found = 0; 1150 break; 1151 case MACL: 1152 if (op_mode != MACL && 1153 op_mode != MACREG) 1154 found = 0; 1155 break; 1156 case VBR: 1157 if (op_mode != VBR && 1158 op_mode != VBR_SBR && 1159 op_mode != CC_EX_VB_SB) 1160 found = 0; 1161 break; 1162 case SBR: 1163 if (op_mode != SBR && 1164 op_mode != VBR_SBR && 1165 op_mode != CC_EX_VB_SB) 1166 found = 0; 1167 break; 1168 } 1169 } 1170 else if ((op & ABSJMP) && (x_mode == ABS || x_mode == PCREL)) 1171 { 1172 operands[i].mode &= ~MODE; 1173 operands[i].mode |= ABSJMP; 1174 /* But it may not be 24 bits long. */ 1175 if (x_mode == ABS && !Hmode) 1176 { 1177 operands[i].mode &= ~SIZE; 1178 operands[i].mode |= L_16; 1179 } 1180 if ((operands[i].mode & SIZE) == L_32 1181 && (op_mode & SIZE) != L_32) 1182 found = 0; 1183 } 1184 else if (x_mode == IMM && op_mode != IMM) 1185 { 1186 offsetT num = operands[i].exp.X_add_number & 0xffffffff; 1187 if (op_mode == KBIT || op_mode == DBIT) 1188 /* This is ok if the immediate value is sensible. */; 1189 else if (op_mode == CONST_2) 1190 found = num == 2; 1191 else if (op_mode == CONST_4) 1192 found = num == 4; 1193 else if (op_mode == CONST_8) 1194 found = num == 8; 1195 else if (op_mode == CONST_16) 1196 found = num == 16; 1197 else 1198 found = 0; 1199 } 1200 else if (op_mode == PCREL && op_mode == x_mode) 1201 { 1202 /* movsd, bsr/bc and bsr/bs only come in PCREL16 flavour: 1203 If x_size is L_8, promote it. */ 1204 if (OP_KIND (this_try->opcode->how) == O_MOVSD 1205 || OP_KIND (this_try->opcode->how) == O_BSRBC 1206 || OP_KIND (this_try->opcode->how) == O_BSRBS) 1207 if (x_size == L_8) 1208 x_size = L_16; 1209 1210 /* The size of the displacement is important. */ 1211 if (op_size != x_size) 1212 found = 0; 1213 } 1214 else if ((op_mode == DISP || op_mode == IMM || op_mode == ABS 1215 || op_mode == INDEXB || op_mode == INDEXW 1216 || op_mode == INDEXL) 1217 && op_mode == x_mode) 1218 { 1219 /* Promote a L_24 to L_32 if it makes us match. */ 1220 if (x_size == L_24 && op_size == L_32) 1221 { 1222 x &= ~SIZE; 1223 x |= x_size = L_32; 1224 } 1225 1226 if (((x_size == L_16 && op_size == L_16U) 1227 || (x_size == L_8 && op_size == L_8U) 1228 || (x_size == L_3 && op_size == L_3NZ)) 1229 /* We're deliberately more permissive for ABS modes. */ 1230 && (op_mode == ABS 1231 || constant_fits_size_p (operands + i, op_size, 1232 op & NO_SYMBOLS))) 1233 x_size = op_size; 1234 1235 if (x_size != 0 && op_size != x_size) 1236 found = 0; 1237 else if (x_size == 0 1238 && ! constant_fits_size_p (operands + i, op_size, 1239 op & NO_SYMBOLS)) 1240 found = 0; 1241 } 1242 else if (op_mode != x_mode) 1243 { 1244 found = 0; 1245 } 1246 } 1247 } 1248 if (found) 1249 { 1250 if ((this_try->opcode->available == AV_H8SX && ! SXmode) 1251 || (this_try->opcode->available == AV_H8S && ! Smode) 1252 || (this_try->opcode->available == AV_H8H && ! Hmode)) 1253 found = 0, found_other = this_try; 1254 else if (this_size != size && (this_size != SN && size != SN)) 1255 found_mismatched = this_try, found = 0; 1256 1257 } 1258 } 1259 if (found) 1260 return this_try; 1261 if (found_other) 1262 { 1263 as_warn (_("Opcode `%s' with these operand types not available in %s mode"), 1264 found_other->opcode->name, 1265 (! Hmode && ! Smode ? "H8/300" 1266 : SXmode ? "H8sx" 1267 : Smode ? "H8/300S" 1268 : "H8/300H")); 1269 } 1270 else if (found_mismatched) 1271 { 1272 as_warn (_("mismatch between opcode size and operand size")); 1273 return found_mismatched; 1274 } 1275 return 0; 1276 } 1277 1278 static void 1279 check_operand (struct h8_op *operand, unsigned int width, const char *string) 1280 { 1281 if (operand->exp.X_add_symbol == 0 1282 && operand->exp.X_op_symbol == 0) 1283 { 1284 /* No symbol involved, let's look at offset, it's dangerous if 1285 any of the high bits are not 0 or ff's, find out by oring or 1286 anding with the width and seeing if the answer is 0 or all 1287 fs. */ 1288 1289 if (! constant_fits_width_p (operand, width)) 1290 { 1291 if (width == 255 1292 && (operand->exp.X_add_number & 0xff00) == 0xff00) 1293 { 1294 /* Just ignore this one - which happens when trying to 1295 fit a 16 bit address truncated into an 8 bit address 1296 of something like bset. */ 1297 } 1298 else if (strcmp (string, "@") == 0 1299 && width == 0xffff 1300 && (operand->exp.X_add_number & 0xff8000) == 0xff8000) 1301 { 1302 /* Just ignore this one - which happens when trying to 1303 fit a 24 bit address truncated into a 16 bit address 1304 of something like mov.w. */ 1305 } 1306 else 1307 { 1308 as_warn (_("operand %s0x%lx out of range."), string, 1309 (unsigned long) operand->exp.X_add_number); 1310 } 1311 } 1312 } 1313 } 1314 1315 /* RELAXMODE has one of 3 values: 1316 1317 0 Output a "normal" reloc, no relaxing possible for this insn/reloc 1318 1319 1 Output a relaxable 24bit absolute mov.w address relocation 1320 (may relax into a 16bit absolute address). 1321 1322 2 Output a relaxable 16/24 absolute mov.b address relocation 1323 (may relax into an 8bit absolute address). */ 1324 1325 static void 1326 do_a_fix_imm (int offset, int nibble, struct h8_op *operand, int relaxmode, const struct h8_instruction *this_try) 1327 { 1328 int idx; 1329 int size; 1330 int where; 1331 char *bytes = frag_now->fr_literal + offset; 1332 1333 const char *t = ((operand->mode & MODE) == IMM) ? "#" : "@"; 1334 1335 if (operand->exp.X_add_symbol == 0) 1336 { 1337 switch (operand->mode & SIZE) 1338 { 1339 case L_2: 1340 check_operand (operand, 0x3, t); 1341 bytes[0] |= (operand->exp.X_add_number & 3) << (nibble ? 0 : 4); 1342 break; 1343 case L_3: 1344 case L_3NZ: 1345 check_operand (operand, 0x7, t); 1346 bytes[0] |= (operand->exp.X_add_number & 7) << (nibble ? 0 : 4); 1347 break; 1348 case L_4: 1349 check_operand (operand, 0xF, t); 1350 bytes[0] |= (operand->exp.X_add_number & 15) << (nibble ? 0 : 4); 1351 break; 1352 case L_5: 1353 check_operand (operand, 0x1F, t); 1354 bytes[0] |= operand->exp.X_add_number & 31; 1355 break; 1356 case L_8: 1357 case L_8U: 1358 check_operand (operand, 0xff, t); 1359 bytes[0] |= operand->exp.X_add_number; 1360 break; 1361 case L_16: 1362 case L_16U: 1363 check_operand (operand, 0xffff, t); 1364 bytes[0] |= operand->exp.X_add_number >> 8; 1365 bytes[1] |= operand->exp.X_add_number >> 0; 1366 /* MOVA needs both relocs to relax the second operand properly. */ 1367 if (relaxmode != 0 1368 && (OP_KIND(this_try->opcode->how) == O_MOVAB 1369 || OP_KIND(this_try->opcode->how) == O_MOVAW 1370 || OP_KIND(this_try->opcode->how) == O_MOVAL)) 1371 { 1372 idx = BFD_RELOC_16; 1373 fix_new_exp (frag_now, offset, 2, &operand->exp, 0, idx); 1374 } 1375 break; 1376 case L_24: 1377 check_operand (operand, 0xffffff, t); 1378 bytes[0] |= operand->exp.X_add_number >> 16; 1379 bytes[1] |= operand->exp.X_add_number >> 8; 1380 bytes[2] |= operand->exp.X_add_number >> 0; 1381 break; 1382 1383 case L_32: 1384 /* This should be done with bfd. */ 1385 bytes[0] |= operand->exp.X_add_number >> 24; 1386 bytes[1] |= operand->exp.X_add_number >> 16; 1387 bytes[2] |= operand->exp.X_add_number >> 8; 1388 bytes[3] |= operand->exp.X_add_number >> 0; 1389 if (relaxmode != 0) 1390 { 1391 if ((operand->mode & MODE) == DISP && relaxmode == 1) 1392 idx = BFD_RELOC_H8_DISP32A16; 1393 else 1394 idx = (relaxmode == 2) ? R_MOV24B1 : R_MOVL1; 1395 fix_new_exp (frag_now, offset, 4, &operand->exp, 0, idx); 1396 } 1397 break; 1398 } 1399 } 1400 else 1401 { 1402 switch (operand->mode & SIZE) 1403 { 1404 case L_24: 1405 case L_32: 1406 size = 4; 1407 where = (operand->mode & SIZE) == L_24 ? -1 : 0; 1408 if ((operand->mode & MODE) == DISP && relaxmode == 1) 1409 idx = BFD_RELOC_H8_DISP32A16; 1410 else if (relaxmode == 2) 1411 idx = R_MOV24B1; 1412 else if (relaxmode == 1) 1413 idx = R_MOVL1; 1414 else 1415 idx = R_RELLONG; 1416 break; 1417 default: 1418 as_bad (_("Can't work out size of operand.\n")); 1419 /* Fall through. */ 1420 case L_16: 1421 case L_16U: 1422 size = 2; 1423 where = 0; 1424 if (relaxmode == 2) 1425 idx = R_MOV16B1; 1426 else 1427 idx = R_RELWORD; 1428 operand->exp.X_add_number = 1429 ((operand->exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; 1430 operand->exp.X_add_number |= (bytes[0] << 8) | bytes[1]; 1431 break; 1432 case L_8: 1433 size = 1; 1434 where = 0; 1435 idx = R_RELBYTE; 1436 operand->exp.X_add_number = 1437 ((operand->exp.X_add_number & 0xff) ^ 0x80) - 0x80; 1438 operand->exp.X_add_number |= bytes[0]; 1439 } 1440 1441 fix_new_exp (frag_now, 1442 offset + where, 1443 size, 1444 &operand->exp, 1445 0, 1446 idx); 1447 } 1448 } 1449 1450 /* Now we know what sort of opcodes it is, let's build the bytes. */ 1451 1452 static void 1453 build_bytes (const struct h8_instruction *this_try, struct h8_op *operand) 1454 { 1455 int i; 1456 char *output = frag_more (this_try->length); 1457 const op_type *nibble_ptr = this_try->opcode->data.nib; 1458 op_type c; 1459 unsigned int nibble_count = 0; 1460 int op_at[3]; 1461 int nib = 0; 1462 int movb = 0; 1463 char asnibbles[100]; 1464 char *p = asnibbles; 1465 int high, low; 1466 1467 if (!Hmode && this_try->opcode->available != AV_H8) 1468 as_warn (_("Opcode `%s' with these operand types not available in H8/300 mode"), 1469 this_try->opcode->name); 1470 else if (!Smode 1471 && this_try->opcode->available != AV_H8 1472 && this_try->opcode->available != AV_H8H) 1473 as_warn (_("Opcode `%s' with these operand types not available in H8/300H mode"), 1474 this_try->opcode->name); 1475 else if (!SXmode 1476 && this_try->opcode->available != AV_H8 1477 && this_try->opcode->available != AV_H8H 1478 && this_try->opcode->available != AV_H8S) 1479 as_warn (_("Opcode `%s' with these operand types not available in H8/300S mode"), 1480 this_try->opcode->name); 1481 1482 while (*nibble_ptr != (op_type) E) 1483 { 1484 int d; 1485 1486 nib = 0; 1487 c = *nibble_ptr++; 1488 1489 d = (c & OP3) == OP3 ? 2 : (c & DST) == DST ? 1 : 0; 1490 1491 if (c < 16) 1492 nib = c; 1493 else 1494 { 1495 int c2 = c & MODE; 1496 1497 if (c2 == REG || c2 == LOWREG 1498 || c2 == IND || c2 == PREINC || c2 == PREDEC 1499 || c2 == POSTINC || c2 == POSTDEC) 1500 { 1501 nib = operand[d].reg; 1502 if (c2 == LOWREG) 1503 nib &= 7; 1504 } 1505 1506 else if (c & CTRL) /* Control reg operand. */ 1507 nib = operand[d].reg; 1508 1509 else if ((c & DISPREG) == (DISPREG)) 1510 { 1511 nib = operand[d].reg; 1512 } 1513 else if (c2 == ABS) 1514 { 1515 operand[d].mode = c; 1516 op_at[d] = nibble_count; 1517 nib = 0; 1518 } 1519 else if (c2 == IMM || c2 == PCREL || c2 == ABS 1520 || (c & ABSJMP) || c2 == DISP) 1521 { 1522 operand[d].mode = c; 1523 op_at[d] = nibble_count; 1524 nib = 0; 1525 } 1526 else if ((c & IGNORE) || (c & DATA)) 1527 nib = 0; 1528 1529 else if (c2 == DBIT) 1530 { 1531 switch (operand[0].exp.X_add_number) 1532 { 1533 case 1: 1534 nib = c; 1535 break; 1536 case 2: 1537 nib = 0x8 | c; 1538 break; 1539 default: 1540 as_bad (_("Need #1 or #2 here")); 1541 } 1542 } 1543 else if (c2 == KBIT) 1544 { 1545 switch (operand[0].exp.X_add_number) 1546 { 1547 case 1: 1548 nib = 0; 1549 break; 1550 case 2: 1551 nib = 8; 1552 break; 1553 case 4: 1554 if (!Hmode) 1555 as_warn (_("#4 not valid on H8/300.")); 1556 nib = 9; 1557 break; 1558 1559 default: 1560 as_bad (_("Need #1 or #2 here")); 1561 break; 1562 } 1563 /* Stop it making a fix. */ 1564 operand[0].mode = 0; 1565 } 1566 1567 if (c & MEMRELAX) 1568 operand[d].mode |= MEMRELAX; 1569 1570 if (c & B31) 1571 nib |= 0x8; 1572 1573 if (c & B21) 1574 nib |= 0x4; 1575 1576 if (c & B11) 1577 nib |= 0x2; 1578 1579 if (c & B01) 1580 nib |= 0x1; 1581 1582 if (c2 == MACREG) 1583 { 1584 if (operand[0].mode == MACREG) 1585 /* stmac has mac[hl] as the first operand. */ 1586 nib = 2 + operand[0].reg; 1587 else 1588 /* ldmac has mac[hl] as the second operand. */ 1589 nib = 2 + operand[1].reg; 1590 } 1591 } 1592 nibble_count++; 1593 1594 *p++ = nib; 1595 } 1596 1597 /* Disgusting. Why, oh why didn't someone ask us for advice 1598 on the assembler format. */ 1599 if (OP_KIND (this_try->opcode->how) == O_LDM) 1600 { 1601 high = (operand[1].reg >> 8) & 0xf; 1602 low = (operand[1].reg) & 0xf; 1603 asnibbles[2] = high - low; 1604 asnibbles[7] = high; 1605 } 1606 else if (OP_KIND (this_try->opcode->how) == O_STM) 1607 { 1608 high = (operand[0].reg >> 8) & 0xf; 1609 low = (operand[0].reg) & 0xf; 1610 asnibbles[2] = high - low; 1611 asnibbles[7] = low; 1612 } 1613 1614 for (i = 0; i < this_try->length; i++) 1615 output[i] = (asnibbles[i * 2] << 4) | asnibbles[i * 2 + 1]; 1616 1617 /* Note if this is a mov.b or a bit manipulation instruction 1618 there is a special relaxation which only applies. */ 1619 if ( this_try->opcode->how == O (O_MOV, SB) 1620 || this_try->opcode->how == O (O_BCLR, SB) 1621 || this_try->opcode->how == O (O_BAND, SB) 1622 || this_try->opcode->how == O (O_BIAND, SB) 1623 || this_try->opcode->how == O (O_BILD, SB) 1624 || this_try->opcode->how == O (O_BIOR, SB) 1625 || this_try->opcode->how == O (O_BIST, SB) 1626 || this_try->opcode->how == O (O_BIXOR, SB) 1627 || this_try->opcode->how == O (O_BLD, SB) 1628 || this_try->opcode->how == O (O_BNOT, SB) 1629 || this_try->opcode->how == O (O_BOR, SB) 1630 || this_try->opcode->how == O (O_BSET, SB) 1631 || this_try->opcode->how == O (O_BST, SB) 1632 || this_try->opcode->how == O (O_BTST, SB) 1633 || this_try->opcode->how == O (O_BXOR, SB)) 1634 movb = 1; 1635 1636 /* Output any fixes. */ 1637 for (i = 0; i < this_try->noperands; i++) 1638 { 1639 int x = operand[i].mode; 1640 int x_mode = x & MODE; 1641 1642 if (x_mode == IMM || x_mode == DISP) 1643 do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2, 1644 op_at[i] & 1, operand + i, (x & MEMRELAX) != 0, 1645 this_try); 1646 else if (x_mode == ABS) 1647 do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2, 1648 op_at[i] & 1, operand + i, 1649 (x & MEMRELAX) ? movb + 1 : 0, 1650 this_try); 1651 1652 else if (x_mode == PCREL) 1653 { 1654 int size16 = (x & SIZE) == L_16; 1655 int size = size16 ? 2 : 1; 1656 int type = size16 ? R_PCRWORD : R_PCRBYTE; 1657 fixS *fixP; 1658 1659 check_operand (operand + i, size16 ? 0x7fff : 0x7f, "@"); 1660 1661 if (operand[i].exp.X_add_number & 1) 1662 as_warn (_("branch operand has odd offset (%lx)\n"), 1663 (unsigned long) operand->exp.X_add_number); 1664 if (size16) 1665 { 1666 operand[i].exp.X_add_number = 1667 ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; 1668 } 1669 else 1670 { 1671 operand[i].exp.X_add_number = 1672 ((operand[i].exp.X_add_number & 0xff) ^ 0x80) - 0x80; 1673 } 1674 1675 /* For BRA/S. */ 1676 if (! size16) 1677 operand[i].exp.X_add_number |= output[op_at[i] / 2]; 1678 1679 fixP = fix_new_exp (frag_now, 1680 output - frag_now->fr_literal + op_at[i] / 2, 1681 size, 1682 &operand[i].exp, 1683 1, 1684 type); 1685 fixP->fx_signed = 1; 1686 } 1687 else if (x_mode == MEMIND) 1688 { 1689 check_operand (operand + i, 0xff, "@@"); 1690 fix_new_exp (frag_now, 1691 output - frag_now->fr_literal + 1, 1692 1, 1693 &operand[i].exp, 1694 0, 1695 R_MEM_INDIRECT); 1696 } 1697 else if (x_mode == VECIND) 1698 { 1699 check_operand (operand + i, 0x7f, "@@"); 1700 /* FIXME: approximating the effect of "B31" here... 1701 This is very hackish, and ought to be done a better way. */ 1702 operand[i].exp.X_add_number |= 0x80; 1703 fix_new_exp (frag_now, 1704 output - frag_now->fr_literal + 1, 1705 1, 1706 &operand[i].exp, 1707 0, 1708 R_MEM_INDIRECT); 1709 } 1710 else if (x & ABSJMP) 1711 { 1712 int where = 0; 1713 bfd_reloc_code_real_type reloc_type = R_JMPL1; 1714 1715 /* To be compatible with the proposed H8 ELF format, we 1716 want the relocation's offset to point to the first byte 1717 that will be modified, not to the start of the instruction. */ 1718 1719 if ((operand->mode & SIZE) == L_32) 1720 { 1721 where = 2; 1722 reloc_type = R_RELLONG; 1723 } 1724 else 1725 where = 1; 1726 1727 /* This jmp may be a jump or a branch. */ 1728 1729 check_operand (operand + i, 1730 SXmode ? 0xffffffff : Hmode ? 0xffffff : 0xffff, 1731 "@"); 1732 1733 if (operand[i].exp.X_add_number & 1) 1734 as_warn (_("branch operand has odd offset (%lx)\n"), 1735 (unsigned long) operand->exp.X_add_number); 1736 1737 if (!Hmode) 1738 operand[i].exp.X_add_number = 1739 ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; 1740 fix_new_exp (frag_now, 1741 output - frag_now->fr_literal + where, 1742 4, 1743 &operand[i].exp, 1744 0, 1745 reloc_type); 1746 } 1747 } 1748 } 1749 1750 /* Try to give an intelligent error message for common and simple to 1751 detect errors. */ 1752 1753 static void 1754 clever_message (const struct h8_instruction *instruction, 1755 struct h8_op *operand) 1756 { 1757 /* Find out if there was more than one possible opcode. */ 1758 1759 if ((instruction + 1)->idx != instruction->idx) 1760 { 1761 int argn; 1762 1763 /* Only one opcode of this flavour, try to guess which operand 1764 didn't match. */ 1765 for (argn = 0; argn < instruction->noperands; argn++) 1766 { 1767 switch (instruction->opcode->args.nib[argn]) 1768 { 1769 case RD16: 1770 if (operand[argn].mode != RD16) 1771 { 1772 as_bad (_("destination operand must be 16 bit register")); 1773 return; 1774 1775 } 1776 break; 1777 1778 case RS8: 1779 if (operand[argn].mode != RS8) 1780 { 1781 as_bad (_("source operand must be 8 bit register")); 1782 return; 1783 } 1784 break; 1785 1786 case ABS16DST: 1787 if (operand[argn].mode != ABS16DST) 1788 { 1789 as_bad (_("destination operand must be 16bit absolute address")); 1790 return; 1791 } 1792 break; 1793 case RD8: 1794 if (operand[argn].mode != RD8) 1795 { 1796 as_bad (_("destination operand must be 8 bit register")); 1797 return; 1798 } 1799 break; 1800 1801 case ABS16SRC: 1802 if (operand[argn].mode != ABS16SRC) 1803 { 1804 as_bad (_("source operand must be 16bit absolute address")); 1805 return; 1806 } 1807 break; 1808 1809 } 1810 } 1811 } 1812 as_bad (_("invalid operands")); 1813 } 1814 1815 1816 /* If OPERAND is part of an address, adjust its size and value given 1817 that it addresses SIZE bytes. 1818 1819 This function decides how big non-immediate constants are when no 1820 size was explicitly given. It also scales down the assembly-level 1821 displacement in an @(d:2,ERn) operand. */ 1822 1823 static void 1824 fix_operand_size (struct h8_op *operand, int size) 1825 { 1826 if (SXmode && (operand->mode & MODE) == DISP) 1827 { 1828 /* If the user didn't specify an operand width, see if we 1829 can use @(d:2,ERn). */ 1830 if ((operand->mode & SIZE) == 0 1831 && operand->exp.X_add_symbol == 0 1832 && operand->exp.X_op_symbol == 0 1833 && (operand->exp.X_add_number == size 1834 || operand->exp.X_add_number == size * 2 1835 || operand->exp.X_add_number == size * 3)) 1836 operand->mode |= L_2; 1837 1838 /* Scale down the displacement in an @(d:2,ERn) operand. 1839 X_add_number then contains the desired field value. */ 1840 if ((operand->mode & SIZE) == L_2) 1841 { 1842 if (operand->exp.X_add_number % size != 0) 1843 as_warn (_("operand/size mis-match")); 1844 operand->exp.X_add_number /= size; 1845 } 1846 } 1847 1848 if ((operand->mode & SIZE) == 0) 1849 switch (operand->mode & MODE) 1850 { 1851 case DISP: 1852 case INDEXB: 1853 case INDEXW: 1854 case INDEXL: 1855 case ABS: 1856 /* Pick a 24-bit address unless we know that a 16-bit address 1857 is safe. get_specific() will relax L_24 into L_32 where 1858 necessary. */ 1859 if (Hmode 1860 && !Nmode 1861 && ((((addressT) operand->exp.X_add_number + 0x8000) 1862 & 0xffffffff) > 0xffff 1863 || operand->exp.X_add_symbol != 0 1864 || operand->exp.X_op_symbol != 0)) 1865 operand->mode |= L_24; 1866 else 1867 operand->mode |= L_16; 1868 break; 1869 1870 case PCREL: 1871 if ((((addressT) operand->exp.X_add_number + 0x80) 1872 & 0xffffffff) <= 0xff) 1873 { 1874 if (operand->exp.X_add_symbol != NULL) 1875 operand->mode |= bsize; 1876 else 1877 operand->mode |= L_8; 1878 } 1879 else 1880 operand->mode |= L_16; 1881 break; 1882 } 1883 } 1884 1885 1886 /* This is the guts of the machine-dependent assembler. STR points to 1887 a machine dependent instruction. This function is supposed to emit 1888 the frags/bytes it assembles. */ 1889 1890 void 1891 md_assemble (char *str) 1892 { 1893 char *op_start; 1894 char *op_end; 1895 struct h8_op operand[3]; 1896 const struct h8_instruction *instruction; 1897 const struct h8_instruction *prev_instruction; 1898 1899 char *dot = 0; 1900 char *slash = 0; 1901 char c; 1902 int size, i; 1903 1904 /* Drop leading whitespace. */ 1905 while (*str == ' ') 1906 str++; 1907 1908 /* Find the op code end. */ 1909 for (op_start = op_end = str; 1910 *op_end != 0 && *op_end != ' '; 1911 op_end++) 1912 { 1913 if (*op_end == '.') 1914 { 1915 dot = op_end + 1; 1916 *op_end = 0; 1917 op_end += 2; 1918 break; 1919 } 1920 else if (*op_end == '/' && ! slash) 1921 slash = op_end; 1922 } 1923 1924 if (op_end == op_start) 1925 { 1926 as_bad (_("can't find opcode ")); 1927 } 1928 c = *op_end; 1929 1930 *op_end = 0; 1931 1932 /* The assembler stops scanning the opcode at slashes, so it fails 1933 to make characters following them lower case. Fix them. */ 1934 if (slash) 1935 while (*++slash) 1936 *slash = TOLOWER (*slash); 1937 1938 instruction = (const struct h8_instruction *) 1939 str_hash_find (opcode_hash_control, op_start); 1940 1941 if (instruction == NULL) 1942 { 1943 as_bad (_("unknown opcode")); 1944 return; 1945 } 1946 1947 /* We used to set input_line_pointer to the result of get_operands, 1948 but that is wrong. Our caller assumes we don't change it. */ 1949 1950 operand[0].mode = 0; 1951 operand[1].mode = 0; 1952 operand[2].mode = 0; 1953 1954 if (OP_KIND (instruction->opcode->how) == O_MOVAB 1955 || OP_KIND (instruction->opcode->how) == O_MOVAW 1956 || OP_KIND (instruction->opcode->how) == O_MOVAL) 1957 get_mova_operands (op_end, operand); 1958 else if (OP_KIND (instruction->opcode->how) == O_RTEL 1959 || OP_KIND (instruction->opcode->how) == O_RTSL) 1960 get_rtsl_operands (op_end, operand); 1961 else 1962 get_operands (instruction->noperands, op_end, operand); 1963 1964 *op_end = c; 1965 prev_instruction = instruction; 1966 1967 /* Now we have operands from instruction. 1968 Let's check them out for ldm and stm. */ 1969 if (OP_KIND (instruction->opcode->how) == O_LDM) 1970 { 1971 /* The first operand must be @er7+, and the 1972 second operand must be a register pair. */ 1973 if ((operand[0].mode != RSINC) 1974 || (operand[0].reg != 7) 1975 || ((operand[1].reg & 0x80000000) == 0)) 1976 as_bad (_("invalid operand in ldm")); 1977 } 1978 else if (OP_KIND (instruction->opcode->how) == O_STM) 1979 { 1980 /* The first operand must be a register pair, 1981 and the second operand must be @-er7. */ 1982 if (((operand[0].reg & 0x80000000) == 0) 1983 || (operand[1].mode != RDDEC) 1984 || (operand[1].reg != 7)) 1985 as_bad (_("invalid operand in stm")); 1986 } 1987 1988 size = SN; 1989 if (dot) 1990 { 1991 switch (TOLOWER (*dot)) 1992 { 1993 case 'b': 1994 size = SB; 1995 break; 1996 1997 case 'w': 1998 size = SW; 1999 break; 2000 2001 case 'l': 2002 size = SL; 2003 break; 2004 } 2005 } 2006 if (OP_KIND (instruction->opcode->how) == O_MOVAB || 2007 OP_KIND (instruction->opcode->how) == O_MOVAW || 2008 OP_KIND (instruction->opcode->how) == O_MOVAL) 2009 { 2010 switch (operand[0].mode & MODE) 2011 { 2012 case INDEXB: 2013 default: 2014 fix_operand_size (&operand[1], 1); 2015 break; 2016 case INDEXW: 2017 fix_operand_size (&operand[1], 2); 2018 break; 2019 case INDEXL: 2020 fix_operand_size (&operand[1], 4); 2021 break; 2022 } 2023 } 2024 else 2025 { 2026 for (i = 0; i < 3 && operand[i].mode != 0; i++) 2027 switch (size) 2028 { 2029 case SN: 2030 case SB: 2031 default: 2032 fix_operand_size (&operand[i], 1); 2033 break; 2034 case SW: 2035 fix_operand_size (&operand[i], 2); 2036 break; 2037 case SL: 2038 fix_operand_size (&operand[i], 4); 2039 break; 2040 } 2041 } 2042 2043 instruction = get_specific (instruction, operand, size); 2044 2045 if (instruction == 0) 2046 { 2047 /* Couldn't find an opcode which matched the operands. */ 2048 char *where = frag_more (2); 2049 2050 where[0] = 0x0; 2051 where[1] = 0x0; 2052 clever_message (prev_instruction, operand); 2053 2054 return; 2055 } 2056 2057 build_bytes (instruction, operand); 2058 2059 dwarf2_emit_insn (instruction->length); 2060 } 2061 2062 symbolS * 2063 md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 2064 { 2065 return 0; 2066 } 2067 2068 /* Various routines to kill one day. */ 2069 2070 const char * 2071 md_atof (int type, char *litP, int *sizeP) 2072 { 2073 return ieee_md_atof (type, litP, sizeP, true); 2074 } 2075 2076 #define OPTION_H_TICK_HEX (OPTION_MD_BASE) 2078 #define OPTION_MACH (OPTION_MD_BASE+1) 2079 2080 const char *md_shortopts = ""; 2081 struct option md_longopts[] = 2082 { 2083 { "h-tick-hex", no_argument, NULL, OPTION_H_TICK_HEX }, 2084 { "mach", required_argument, NULL, OPTION_MACH }, 2085 {NULL, no_argument, NULL, 0} 2086 }; 2087 2088 size_t md_longopts_size = sizeof (md_longopts); 2089 2090 struct mach_func 2091 { 2092 const char *name; 2093 void (*func) (void); 2094 }; 2095 2096 static void 2097 mach_h8300h (void) 2098 { 2099 Hmode = 1; 2100 Smode = 0; 2101 Nmode = 0; 2102 SXmode = 0; 2103 default_mach = bfd_mach_h8300h; 2104 } 2105 2106 static void 2107 mach_h8300hn (void) 2108 { 2109 Hmode = 1; 2110 Smode = 0; 2111 Nmode = 1; 2112 SXmode = 0; 2113 default_mach = bfd_mach_h8300hn; 2114 } 2115 2116 static void 2117 mach_h8300s (void) 2118 { 2119 Hmode = 1; 2120 Smode = 1; 2121 Nmode = 0; 2122 SXmode = 0; 2123 default_mach = bfd_mach_h8300s; 2124 } 2125 2126 static void 2127 mach_h8300sn (void) 2128 { 2129 Hmode = 1; 2130 Smode = 1; 2131 Nmode = 1; 2132 SXmode = 0; 2133 default_mach = bfd_mach_h8300sn; 2134 } 2135 2136 static void 2137 mach_h8300sx (void) 2138 { 2139 Hmode = 1; 2140 Smode = 1; 2141 Nmode = 0; 2142 SXmode = 1; 2143 default_mach = bfd_mach_h8300sx; 2144 } 2145 2146 static void 2147 mach_h8300sxn (void) 2148 { 2149 Hmode = 1; 2150 Smode = 1; 2151 Nmode = 1; 2152 SXmode = 1; 2153 default_mach = bfd_mach_h8300sxn; 2154 } 2155 2156 const struct mach_func mach_table[] = 2157 { 2158 {"h8300h", mach_h8300h}, 2159 {"h8300hn", mach_h8300hn}, 2160 {"h8300s", mach_h8300s}, 2161 {"h8300sn", mach_h8300sn}, 2162 {"h8300sx", mach_h8300sx}, 2163 {"h8300sxn", mach_h8300sxn} 2164 }; 2165 2166 int 2167 md_parse_option (int c ATTRIBUTE_UNUSED, const char *arg ATTRIBUTE_UNUSED) 2168 { 2169 unsigned int i; 2170 switch (c) 2171 { 2172 case OPTION_H_TICK_HEX: 2173 enable_h_tick_hex = 1; 2174 break; 2175 case OPTION_MACH: 2176 for (i = 0; i < sizeof(mach_table) / sizeof(struct mach_func); i++) 2177 { 2178 if (strcasecmp (arg, mach_table[i].name) == 0) 2179 { 2180 mach_table[i].func(); 2181 break; 2182 } 2183 } 2184 if (i >= sizeof(mach_table) / sizeof(struct mach_func)) 2185 as_bad (_("Invalid argument to --mach option: %s"), arg); 2186 break; 2187 default: 2188 return 0; 2189 } 2190 return 1; 2191 } 2192 2193 void 2194 md_show_usage (FILE *stream) 2195 { 2196 fprintf (stream, _(" H8300-specific assembler options:\n")); 2197 fprintf (stream, _("\ 2198 -mach=<name> Set the H8300 machine type to one of:\n\ 2199 h8300h, h8300hn, h8300s, h8300sn, h8300sx, h8300sxn\n")); 2200 fprintf (stream, _("\ 2201 -h-tick-hex Support H'00 style hex constants\n")); 2202 } 2203 2204 void tc_aout_fix_to_chars (void); 2206 2207 void 2208 tc_aout_fix_to_chars (void) 2209 { 2210 printf (_("call to tc_aout_fix_to_chars \n")); 2211 abort (); 2212 } 2213 2214 void 2215 md_convert_frag (bfd *headers ATTRIBUTE_UNUSED, 2216 segT seg ATTRIBUTE_UNUSED, 2217 fragS *fragP ATTRIBUTE_UNUSED) 2218 { 2219 printf (_("call to md_convert_frag \n")); 2220 abort (); 2221 } 2222 2223 valueT 2224 md_section_align (segT segment, valueT size) 2225 { 2226 int align = bfd_section_alignment (segment); 2227 return ((size + (1 << align) - 1) & (-1U << align)); 2228 } 2229 2230 void 2231 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) 2232 { 2233 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; 2234 long val = *valP; 2235 2236 switch (fixP->fx_size) 2237 { 2238 case 1: 2239 *buf++ = val; 2240 break; 2241 case 2: 2242 *buf++ = (val >> 8); 2243 *buf++ = val; 2244 break; 2245 case 4: 2246 *buf++ = (val >> 24); 2247 *buf++ = (val >> 16); 2248 *buf++ = (val >> 8); 2249 *buf++ = val; 2250 break; 2251 case 8: 2252 /* This can arise when the .quad or .8byte pseudo-ops are used. 2253 Returning here (without setting fx_done) will cause the code 2254 to attempt to generate a reloc which will then fail with the 2255 slightly more helpful error message: "Cannot represent 2256 relocation type BFD_RELOC_64". */ 2257 return; 2258 default: 2259 abort (); 2260 } 2261 2262 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0) 2263 fixP->fx_done = 1; 2264 } 2265 2266 int 2267 md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED, 2268 segT segment_type ATTRIBUTE_UNUSED) 2269 { 2270 printf (_("call to md_estimate_size_before_relax \n")); 2271 abort (); 2272 } 2273 2274 /* Put number into target byte order. */ 2275 void 2276 md_number_to_chars (char *ptr, valueT use, int nbytes) 2277 { 2278 number_to_chars_bigendian (ptr, use, nbytes); 2279 } 2280 2281 long 2282 md_pcrel_from (fixS *fixp) 2283 { 2284 as_bad_where (fixp->fx_file, fixp->fx_line, 2285 _("Unexpected reference to a symbol in a non-code section")); 2286 return 0; 2287 } 2288 2289 arelent * 2290 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) 2291 { 2292 arelent *rel; 2293 bfd_reloc_code_real_type r_type; 2294 2295 if (fixp->fx_addsy && fixp->fx_subsy) 2296 { 2297 if ((S_GET_SEGMENT (fixp->fx_addsy) != S_GET_SEGMENT (fixp->fx_subsy)) 2298 || S_GET_SEGMENT (fixp->fx_addsy) == undefined_section) 2299 { 2300 as_bad_subtract (fixp); 2301 return NULL; 2302 } 2303 } 2304 2305 rel = XNEW (arelent); 2306 rel->sym_ptr_ptr = XNEW (asymbol *); 2307 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 2308 rel->address = fixp->fx_frag->fr_address + fixp->fx_where; 2309 rel->addend = fixp->fx_offset; 2310 2311 r_type = fixp->fx_r_type; 2312 2313 #define DEBUG 0 2314 #if DEBUG 2315 fprintf (stderr, "%s\n", bfd_get_reloc_code_name (r_type)); 2316 fflush (stderr); 2317 #endif 2318 rel->howto = bfd_reloc_type_lookup (stdoutput, r_type); 2319 if (rel->howto == NULL) 2320 { 2321 as_bad_where (fixp->fx_file, fixp->fx_line, 2322 _("Cannot represent relocation type %s"), 2323 bfd_get_reloc_code_name (r_type)); 2324 return NULL; 2325 } 2326 2327 return rel; 2328 } 2329
Indexes created Fri Mar 20 00:23:26 UTC 2026