tc-z80.c revision 1.10
1 /* tc-z80.c -- Assemble code for the Zilog Z80, Z180, EZ80 and ASCII R800 2 Copyright (C) 2005-2025 Free Software Foundation, Inc. 3 Contributed by Arnold Metselaar <arnold_m (at) operamail.com> 4 5 This file is part of GAS, the GNU Assembler. 6 7 GAS is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GAS is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GAS; see the file COPYING. If not, write to the Free 19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 20 02110-1301, USA. */ 21 22 #include "as.h" 23 #include "safe-ctype.h" 24 #include "subsegs.h" 25 #include "elf/z80.h" 26 #include "dwarf2dbg.h" 27 #include "dw2gencfi.h" 28 29 /* Exported constants. */ 30 const char comment_chars[] = ";\0"; 31 const char line_comment_chars[] = "#;\0"; 32 const char line_separator_chars[] = "\0"; 33 const char EXP_CHARS[] = "eE\0"; 34 const char FLT_CHARS[] = "RrDdFfSsHh\0"; 35 36 /* For machine specific options. */ 37 const char md_shortopts[] = ""; /* None yet. */ 38 39 enum options 40 { 41 OPTION_MARCH = OPTION_MD_BASE, 42 OPTION_MACH_Z80, 43 OPTION_MACH_R800, 44 OPTION_MACH_Z180, 45 OPTION_MACH_EZ80_Z80, 46 OPTION_MACH_EZ80_ADL, 47 OPTION_MACH_INST, 48 OPTION_MACH_NO_INST, 49 OPTION_MACH_IUD, 50 OPTION_MACH_WUD, 51 OPTION_MACH_FUD, 52 OPTION_MACH_IUP, 53 OPTION_MACH_WUP, 54 OPTION_MACH_FUP, 55 OPTION_FP_SINGLE_FORMAT, 56 OPTION_FP_DOUBLE_FORMAT, 57 OPTION_COMPAT_LL_PREFIX, 58 OPTION_COMPAT_COLONLESS, 59 OPTION_COMPAT_SDCC 60 }; 61 62 #define INS_Z80 (1 << 0) 63 #define INS_R800 (1 << 1) 64 #define INS_GBZ80 (1 << 2) 65 #define INS_Z180 (1 << 3) 66 #define INS_EZ80 (1 << 4) 67 #define INS_Z80N (1 << 5) 68 #define INS_MARCH_MASK 0xffff 69 70 #define INS_IDX_HALF (1 << 16) 71 #define INS_IN_F_C (1 << 17) 72 #define INS_OUT_C_0 (1 << 18) 73 #define INS_SLI (1 << 19) 74 #define INS_ROT_II_LD (1 << 20) /* instructions like SLA (ii+d),r; which is: LD r,(ii+d); SLA r; LD (ii+d),r */ 75 #define INS_TUNE_MASK 0xffff0000 76 77 #define INS_NOT_GBZ80 (INS_Z80 | INS_Z180 | INS_R800 | INS_EZ80 | INS_Z80N) 78 79 #define INS_ALL 0 80 #define INS_UNDOC (INS_IDX_HALF | INS_IN_F_C) 81 #define INS_UNPORT (INS_OUT_C_0 | INS_SLI | INS_ROT_II_LD) 82 83 const struct option md_longopts[] = 84 { 85 { "march", required_argument, NULL, OPTION_MARCH}, 86 { "z80", no_argument, NULL, OPTION_MACH_Z80}, 87 { "r800", no_argument, NULL, OPTION_MACH_R800}, 88 { "z180", no_argument, NULL, OPTION_MACH_Z180}, 89 { "ez80", no_argument, NULL, OPTION_MACH_EZ80_Z80}, 90 { "ez80-adl", no_argument, NULL, OPTION_MACH_EZ80_ADL}, 91 { "fp-s", required_argument, NULL, OPTION_FP_SINGLE_FORMAT}, 92 { "fp-d", required_argument, NULL, OPTION_FP_DOUBLE_FORMAT}, 93 { "strict", no_argument, NULL, OPTION_MACH_FUD}, 94 { "full", no_argument, NULL, OPTION_MACH_IUP}, 95 { "with-inst", required_argument, NULL, OPTION_MACH_INST}, 96 { "Wnins", required_argument, NULL, OPTION_MACH_INST}, 97 { "without-inst", required_argument, NULL, OPTION_MACH_NO_INST}, 98 { "local-prefix", required_argument, NULL, OPTION_COMPAT_LL_PREFIX}, 99 { "colonless", no_argument, NULL, OPTION_COMPAT_COLONLESS}, 100 { "sdcc", no_argument, NULL, OPTION_COMPAT_SDCC}, 101 { "Fins", required_argument, NULL, OPTION_MACH_NO_INST}, 102 { "ignore-undocumented-instructions", no_argument, NULL, OPTION_MACH_IUD }, 103 { "Wnud", no_argument, NULL, OPTION_MACH_IUD }, 104 { "warn-undocumented-instructions", no_argument, NULL, OPTION_MACH_WUD }, 105 { "Wud", no_argument, NULL, OPTION_MACH_WUD }, 106 { "forbid-undocumented-instructions", no_argument, NULL, OPTION_MACH_FUD }, 107 { "Fud", no_argument, NULL, OPTION_MACH_FUD }, 108 { "ignore-unportable-instructions", no_argument, NULL, OPTION_MACH_IUP }, 109 { "Wnup", no_argument, NULL, OPTION_MACH_IUP }, 110 { "warn-unportable-instructions", no_argument, NULL, OPTION_MACH_WUP }, 111 { "Wup", no_argument, NULL, OPTION_MACH_WUP }, 112 { "forbid-unportable-instructions", no_argument, NULL, OPTION_MACH_FUP }, 113 { "Fup", no_argument, NULL, OPTION_MACH_FUP }, 114 115 { NULL, no_argument, NULL, 0 } 116 } ; 117 118 const size_t md_longopts_size = sizeof (md_longopts); 119 120 extern int coff_flags; 121 /* Instruction classes that silently assembled. */ 122 static int ins_ok = INS_Z80 | INS_UNDOC; 123 /* Instruction classes that generate errors. */ 124 static int ins_err = ~(INS_Z80 | INS_UNDOC); 125 /* eZ80 CPU mode (ADL or Z80) */ 126 static int cpu_mode = 0; /* 0 - Z80, 1 - ADL */ 127 /* accept SDCC specific instruction encoding */ 128 static int sdcc_compat = 0; 129 /* accept colonless labels */ 130 static int colonless_labels = 0; 131 /* local label prefix (NULL - default) */ 132 static const char *local_label_prefix = NULL; 133 /* floating point support */ 134 typedef const char *(*str_to_float_t)(char *litP, int *sizeP); 135 static str_to_float_t str_to_float; 136 static str_to_float_t str_to_double; 137 138 /* mode of current instruction */ 139 #define INST_MODE_S 0 /* short data mode */ 140 #define INST_MODE_IS 0 /* short instruction mode */ 141 #define INST_MODE_L 2 /* long data mode */ 142 #define INST_MODE_IL 1 /* long instruction mode */ 143 #define INST_MODE_FORCED 4 /* CPU mode changed by instruction suffix*/ 144 static char inst_mode; 145 146 struct match_info 147 { 148 const char *name; 149 int ins_ok; 150 int ins_err; 151 int cpu_mode; 152 const char *comment; 153 }; 154 155 static const struct match_info 156 match_cpu_table [] = 157 { 158 {"z80", INS_Z80, 0, 0, "Zilog Z80" }, 159 {"ez80", INS_EZ80, 0, 0, "Zilog eZ80" }, 160 {"gbz80", INS_GBZ80, INS_UNDOC|INS_UNPORT, 0, "GameBoy Z80" }, 161 {"r800", INS_R800, INS_UNPORT, 0, "Ascii R800" }, 162 {"z180", INS_Z180, INS_UNDOC|INS_UNPORT, 0, "Zilog Z180" }, 163 {"z80n", INS_Z80N, 0, 0, "Z80 Next" } 164 }; 165 166 static const struct match_info 167 match_ext_table [] = 168 { 169 {"full", INS_UNDOC|INS_UNPORT, 0, 0, "assemble all known instructions" }, 170 {"adl", 0, 0, 1, "eZ80 ADL mode by default" }, 171 {"xyhl", INS_IDX_HALF, 0, 0, "instructions with halves of index registers" }, 172 {"infc", INS_IN_F_C, 0, 0, "instruction IN F,(C)" }, 173 {"outc0", INS_OUT_C_0, 0, 0, "instruction OUT (C),0" }, 174 {"sli", INS_SLI, 0, 0, "instruction known as SLI, SLL, or SL1" }, 175 {"xdcb", INS_ROT_II_LD, 0, 0, "instructions like RL (IX+d),R (DD/FD CB dd oo)" } 176 }; 177 178 179 static int signed_overflow (signed long value, unsigned bitsize); 180 static int unsigned_overflow (unsigned long value, unsigned bitsize); 181 static int is_overflow (long value, unsigned bitsize); 182 183 static void 184 setup_march (const char *name, int *ok, int *err, int *mode) 185 { 186 unsigned i; 187 size_t len = strcspn (name, "+-"); 188 for (i = 0; i < ARRAY_SIZE (match_cpu_table); ++i) 189 if (!strncasecmp (name, match_cpu_table[i].name, len) 190 && strlen (match_cpu_table[i].name) == len) 191 { 192 *ok = match_cpu_table[i].ins_ok; 193 *err = match_cpu_table[i].ins_err; 194 *mode = match_cpu_table[i].cpu_mode; 195 break; 196 } 197 198 if (i >= ARRAY_SIZE (match_cpu_table)) 199 as_fatal (_("Invalid CPU is specified: %s"), name); 200 201 while (name[len]) 202 { 203 name = &name[len + 1]; 204 len = strcspn (name, "+-"); 205 for (i = 0; i < ARRAY_SIZE (match_ext_table); ++i) 206 if (!strncasecmp (name, match_ext_table[i].name, len) 207 && strlen (match_ext_table[i].name) == len) 208 { 209 if (name[-1] == '+') 210 { 211 *ok |= match_ext_table[i].ins_ok; 212 *err &= ~match_ext_table[i].ins_ok; 213 *mode |= match_ext_table[i].cpu_mode; 214 } 215 else 216 { 217 *ok &= ~match_ext_table[i].ins_ok; 218 *err |= match_ext_table[i].ins_ok; 219 *mode &= ~match_ext_table[i].cpu_mode; 220 } 221 break; 222 } 223 if (i >= ARRAY_SIZE (match_ext_table)) 224 as_fatal (_("Invalid EXTENSION is specified: %s"), name); 225 } 226 } 227 228 static int 229 setup_instruction (const char *inst, int *add, int *sub) 230 { 231 int n; 232 if (!strcmp (inst, "idx-reg-halves")) 233 n = INS_IDX_HALF; 234 else if (!strcmp (inst, "sli")) 235 n = INS_SLI; 236 else if (!strcmp (inst, "op-ii-ld")) 237 n = INS_ROT_II_LD; 238 else if (!strcmp (inst, "in-f-c")) 239 n = INS_IN_F_C; 240 else if (!strcmp (inst, "out-c-0")) 241 n = INS_OUT_C_0; 242 else 243 return 0; 244 *add |= n; 245 *sub &= ~n; 246 return 1; 247 } 248 249 static const char * 250 str_to_zeda32 (char *litP, int *sizeP); 251 static const char * 252 str_to_float48 (char *litP, int *sizeP); 253 static const char * 254 str_to_ieee754_h (char *litP, int *sizeP); 255 static const char * 256 str_to_ieee754_s (char *litP, int *sizeP); 257 static const char * 258 str_to_ieee754_d (char *litP, int *sizeP); 259 260 static str_to_float_t 261 get_str_to_float (const char *arg) 262 { 263 if (strcasecmp (arg, "zeda32") == 0) 264 return str_to_zeda32; 265 266 if (strcasecmp (arg, "math48") == 0) 267 return str_to_float48; 268 269 if (strcasecmp (arg, "half") != 0) 270 return str_to_ieee754_h; 271 272 if (strcasecmp (arg, "single") != 0) 273 return str_to_ieee754_s; 274 275 if (strcasecmp (arg, "double") != 0) 276 return str_to_ieee754_d; 277 278 if (strcasecmp (arg, "ieee754") == 0) 279 as_fatal (_("invalid floating point numbers type `%s'"), arg); 280 return NULL; 281 } 282 283 static int 284 setup_instruction_list (const char *list, int *add, int *sub) 285 { 286 char buf[16]; 287 const char *b; 288 const char *e; 289 int sz; 290 int res = 0; 291 for (b = list; *b != '\0';) 292 { 293 e = strchr (b, ','); 294 if (e == NULL) 295 sz = strlen (b); 296 else 297 sz = e - b; 298 if (sz == 0 || sz >= (int)sizeof (buf)) 299 { 300 as_bad (_("invalid INST in command line: %s"), b); 301 return 0; 302 } 303 memcpy (buf, b, sz); 304 buf[sz] = '\0'; 305 if (setup_instruction (buf, add, sub)) 306 res++; 307 else 308 { 309 as_bad (_("invalid INST in command line: %s"), buf); 310 return 0; 311 } 312 b = &b[sz]; 313 if (*b == ',') 314 ++b; 315 } 316 return res; 317 } 318 319 int 320 md_parse_option (int c, const char* arg) 321 { 322 switch (c) 323 { 324 default: 325 return 0; 326 case OPTION_MARCH: 327 setup_march (arg, & ins_ok, & ins_err, & cpu_mode); 328 break; 329 case OPTION_MACH_Z80: 330 setup_march ("z80", & ins_ok, & ins_err, & cpu_mode); 331 break; 332 case OPTION_MACH_R800: 333 setup_march ("r800", & ins_ok, & ins_err, & cpu_mode); 334 break; 335 case OPTION_MACH_Z180: 336 setup_march ("z180", & ins_ok, & ins_err, & cpu_mode); 337 break; 338 case OPTION_MACH_EZ80_Z80: 339 setup_march ("ez80", & ins_ok, & ins_err, & cpu_mode); 340 break; 341 case OPTION_MACH_EZ80_ADL: 342 setup_march ("ez80+adl", & ins_ok, & ins_err, & cpu_mode); 343 break; 344 case OPTION_FP_SINGLE_FORMAT: 345 str_to_float = get_str_to_float (arg); 346 break; 347 case OPTION_FP_DOUBLE_FORMAT: 348 str_to_double = get_str_to_float (arg); 349 break; 350 case OPTION_MACH_INST: 351 if ((ins_ok & INS_GBZ80) == 0) 352 return setup_instruction_list (arg, & ins_ok, & ins_err); 353 break; 354 case OPTION_MACH_NO_INST: 355 if ((ins_ok & INS_GBZ80) == 0) 356 return setup_instruction_list (arg, & ins_err, & ins_ok); 357 break; 358 case OPTION_MACH_WUD: 359 case OPTION_MACH_IUD: 360 if ((ins_ok & INS_GBZ80) == 0) 361 { 362 ins_ok |= INS_UNDOC; 363 ins_err &= ~INS_UNDOC; 364 } 365 break; 366 case OPTION_MACH_WUP: 367 case OPTION_MACH_IUP: 368 if ((ins_ok & INS_GBZ80) == 0) 369 { 370 ins_ok |= INS_UNDOC | INS_UNPORT; 371 ins_err &= ~(INS_UNDOC | INS_UNPORT); 372 } 373 break; 374 case OPTION_MACH_FUD: 375 if ((ins_ok & (INS_R800 | INS_GBZ80)) == 0) 376 { 377 ins_ok &= (INS_UNDOC | INS_UNPORT); 378 ins_err |= INS_UNDOC | INS_UNPORT; 379 } 380 break; 381 case OPTION_MACH_FUP: 382 ins_ok &= ~INS_UNPORT; 383 ins_err |= INS_UNPORT; 384 break; 385 case OPTION_COMPAT_LL_PREFIX: 386 local_label_prefix = (arg && *arg) ? arg : NULL; 387 break; 388 case OPTION_COMPAT_SDCC: 389 sdcc_compat = 1; 390 break; 391 case OPTION_COMPAT_COLONLESS: 392 colonless_labels = 1; 393 break; 394 } 395 396 return 1; 397 } 398 399 void 400 md_show_usage (FILE * f) 401 { 402 unsigned i; 403 fprintf (f, _("\n\ 404 CPU model options:\n\ 405 -march=CPU[+EXT...][-EXT...]\n\ 406 \t\t\t generate code for CPU, where CPU is one of:\n")); 407 for (i = 0; i < ARRAY_SIZE(match_cpu_table); ++i) 408 fprintf (f, " %-8s\t\t %s\n", match_cpu_table[i].name, match_cpu_table[i].comment); 409 fprintf (f, _("And EXT is combination (+EXT - add, -EXT - remove) of:\n")); 410 for (i = 0; i < ARRAY_SIZE(match_ext_table); ++i) 411 fprintf (f, " %-8s\t\t %s\n", match_ext_table[i].name, match_ext_table[i].comment); 412 fprintf (f, _("\n\ 413 Compatibility options:\n\ 414 -local-prefix=TEXT\t treat labels prefixed by TEXT as local\n\ 415 -colonless\t\t permit colonless labels\n\ 416 -sdcc\t\t\t accept SDCC specific instruction syntax\n\ 417 -fp-s=FORMAT\t\t set single precision FP numbers format\n\ 418 -fp-d=FORMAT\t\t set double precision FP numbers format\n\ 419 Where FORMAT one of:\n\ 420 ieee754\t\t IEEE754 compatible (depends on directive)\n\ 421 half\t\t\t IEEE754 half precision (16 bit)\n\ 422 single\t\t IEEE754 single precision (32 bit)\n\ 423 double\t\t IEEE754 double precision (64 bit)\n\ 424 zeda32\t\t Zeda z80float library 32 bit format\n\ 425 math48\t\t 48 bit format from Math48 library\n\ 426 \n\ 427 Default: -march=z80+xyhl+infc\n")); 428 } 429 430 static symbolS * zero; 431 432 struct reg_entry 433 { 434 const char* name; 435 int number; 436 int isa; 437 }; 438 #define R_STACKABLE (0x80) 439 #define R_ARITH (0x40) 440 #define R_IX (0x20) 441 #define R_IY (0x10) 442 #define R_INDEX (R_IX | R_IY) 443 444 #define REG_A (7) 445 #define REG_B (0) 446 #define REG_C (1) 447 #define REG_D (2) 448 #define REG_E (3) 449 #define REG_H (4) 450 #define REG_L (5) 451 #define REG_F (6 | 8) 452 #define REG_I (9) 453 #define REG_R (10) 454 #define REG_MB (11) 455 456 #define REG_AF (3 | R_STACKABLE) 457 #define REG_BC (0 | R_STACKABLE | R_ARITH) 458 #define REG_DE (1 | R_STACKABLE | R_ARITH) 459 #define REG_HL (2 | R_STACKABLE | R_ARITH) 460 #define REG_IX (REG_HL | R_IX) 461 #define REG_IY (REG_HL | R_IY) 462 #define REG_SP (3 | R_ARITH) 463 464 static const struct reg_entry regtable[] = 465 { 466 {"a", REG_A, INS_ALL }, 467 {"af", REG_AF, INS_ALL }, 468 {"b", REG_B, INS_ALL }, 469 {"bc", REG_BC, INS_ALL }, 470 {"c", REG_C, INS_ALL }, 471 {"d", REG_D, INS_ALL }, 472 {"de", REG_DE, INS_ALL }, 473 {"e", REG_E, INS_ALL }, 474 {"f", REG_F, INS_IN_F_C | INS_Z80N | INS_R800 }, 475 {"h", REG_H, INS_ALL }, 476 {"hl", REG_HL, INS_ALL }, 477 {"i", REG_I, INS_NOT_GBZ80 }, 478 {"ix", REG_IX, INS_NOT_GBZ80 }, 479 {"ixh", REG_H | R_IX, INS_IDX_HALF | INS_EZ80 | INS_R800 | INS_Z80N }, 480 {"ixl", REG_L | R_IX, INS_IDX_HALF | INS_EZ80 | INS_R800 | INS_Z80N }, 481 {"iy", REG_IY, INS_NOT_GBZ80 }, 482 {"iyh", REG_H | R_IY, INS_IDX_HALF | INS_EZ80 | INS_R800 | INS_Z80N }, 483 {"iyl", REG_L | R_IY, INS_IDX_HALF | INS_EZ80 | INS_R800 | INS_Z80N }, 484 {"l", REG_L, INS_ALL }, 485 {"mb", REG_MB, INS_EZ80 }, 486 {"r", REG_R, INS_NOT_GBZ80 }, 487 {"sp", REG_SP, INS_ALL }, 488 } ; 489 490 #define BUFLEN 8 /* Large enough for any keyword. */ 491 492 void 493 md_begin (void) 494 { 495 expressionS nul, reg; 496 char * p; 497 unsigned int i, j, k; 498 char buf[BUFLEN]; 499 500 memset (®, 0, sizeof (reg)); 501 memset (&nul, 0, sizeof (nul)); 502 503 if (ins_ok & INS_EZ80) /* if select EZ80 cpu then */ 504 listing_lhs_width = 6; /* use 6 bytes per line in the listing */ 505 506 reg.X_op = O_register; 507 reg.X_md = 0; 508 reg.X_add_symbol = reg.X_op_symbol = 0; 509 for ( i = 0 ; i < ARRAY_SIZE ( regtable ) ; ++i ) 510 { 511 if (regtable[i].isa && !(regtable[i].isa & ins_ok)) 512 continue; 513 reg.X_add_number = regtable[i].number; 514 k = strlen ( regtable[i].name ); 515 buf[k] = 0; 516 if ( k+1 < BUFLEN ) 517 { 518 for ( j = ( 1<<k ) ; j ; --j ) 519 { 520 for ( k = 0 ; regtable[i].name[k] ; ++k ) 521 { 522 buf[k] = ( j & ( 1<<k ) ) ? TOUPPER (regtable[i].name[k]) : regtable[i].name[k]; 523 } 524 symbolS * psym = symbol_find_or_make (buf); 525 S_SET_SEGMENT (psym, reg_section); 526 symbol_set_value_expression (psym, ®); 527 } 528 } 529 } 530 p = input_line_pointer; 531 input_line_pointer = (char *) "0"; 532 nul.X_md=0; 533 expression (& nul); 534 input_line_pointer = p; 535 zero = make_expr_symbol (& nul); 536 /* We do not use relaxation (yet). */ 537 linkrelax = 0; 538 } 539 540 void 541 z80_md_finish (void) 542 { 543 int mach_type; 544 545 switch (ins_ok & INS_MARCH_MASK) 546 { 547 case INS_Z80: 548 mach_type = bfd_mach_z80; 549 break; 550 case INS_R800: 551 mach_type = bfd_mach_r800; 552 break; 553 case INS_Z180: 554 mach_type = bfd_mach_z180; 555 break; 556 case INS_GBZ80: 557 mach_type = bfd_mach_gbz80; 558 break; 559 case INS_EZ80: 560 mach_type = cpu_mode ? bfd_mach_ez80_adl : bfd_mach_ez80_z80; 561 break; 562 case INS_Z80N: 563 mach_type = bfd_mach_z80n; 564 break; 565 default: 566 mach_type = 0; 567 } 568 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach_type); 569 } 570 571 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 572 void 573 z80_elf_final_processing (void) 574 {/* nothing to do, all is done by BFD itself */ 575 /* 576 unsigned elf_flags; 577 elf_elfheader (stdoutput)->e_flags = elf_flags; 578 */ 579 } 580 #endif 581 582 static const char * 583 skip_space (const char *s) 584 { 585 while (is_whitespace (*s)) 586 ++s; 587 return s; 588 } 589 590 /* A non-zero return-value causes a continue in the 591 function read_a_source_file () in ../read.c. */ 592 int 593 z80_start_line_hook (void) 594 { 595 char *p, quote; 596 char buf[4]; 597 598 /* Convert one character constants. */ 599 for (p = input_line_pointer; *p && *p != '\n'; ++p) 600 { 601 switch (*p) 602 { 603 case '\'': 604 if (p[1] != 0 && p[1] != '\'' && p[2] == '\'') 605 { 606 snprintf (buf, 4, "%3d", (unsigned char)p[1]); 607 *p++ = buf[0]; 608 *p++ = buf[1]; 609 *p++ = buf[2]; 610 break; 611 } 612 /* Fall through. */ 613 case '"': 614 for (quote = *p++; quote != *p && '\n' != *p; ++p) 615 /* No escapes. */ ; 616 if (quote != *p) 617 { 618 as_bad (_("-- unterminated string")); 619 ignore_rest_of_line (); 620 return 1; 621 } 622 break; 623 case '#': /* force to use next expression as immediate value in SDCC */ 624 if (!sdcc_compat) 625 break; 626 if (is_whitespace (p[1]) && *skip_space (p + 1) == '(') 627 { /* ld a,# (expr)... -> ld a,0+(expr)... */ 628 *p++ = '0'; 629 *p = '+'; 630 } 631 else /* ld a,#(expr)... -> ld a,+(expr); ld a,#expr -> ld a, expr */ 632 *p = (p[1] == '(') ? '+' : ' '; 633 break; 634 } 635 } 636 /* Remove leading zeros from dollar local labels if SDCC compat enabled. */ 637 if (sdcc_compat && *input_line_pointer == '0') 638 { 639 char *dollar; 640 641 /* SDCC emits at most one label definition per line, so it is 642 enough to look at only the first label. Hand-written asm 643 might use more, but then it is unlikely to use leading zeros 644 on dollar local labels. */ 645 646 /* Place p at the first character after [0-9]+. */ 647 for (p = input_line_pointer; *p >= '0' && *p <= '9'; ++p) 648 ; 649 650 /* Is this a dollar sign label? 651 GAS allows spaces between $ and :, but SDCC does not. */ 652 if (p[0] == '$' && p[1] == ':') 653 { 654 dollar = p; 655 /* Replace zeros with spaces until the first non-zero, 656 but leave the last character before $ intact (for e.g. 0$:). */ 657 for (p = input_line_pointer; *p == '0' && p < dollar - 1; ++p) 658 { 659 *p = ' '; 660 } 661 } 662 } 663 /* Check for <label>[:] =|([.](EQU|DEFL)) <value>. */ 664 if (is_name_beginner (*input_line_pointer)) 665 { 666 char *name; 667 char c, *rest, *line_start; 668 int len; 669 670 line_start = input_line_pointer; 671 if (ignore_input ()) 672 return 0; 673 c = get_symbol_name (&name); 674 rest = input_line_pointer + 1; 675 if (c == ':' && *rest == ':') 676 { 677 /* remove second colon if SDCC compatibility enabled */ 678 if (sdcc_compat) 679 *rest = ' '; 680 ++rest; 681 } 682 rest = (char*)skip_space (rest); 683 if (*rest == '=') 684 len = (rest[1] == '=') ? 2 : 1; 685 else 686 { 687 if (*rest == '.') 688 ++rest; 689 if (strncasecmp (rest, "EQU", 3) == 0) 690 len = 3; 691 else if (strncasecmp (rest, "DEFL", 4) == 0) 692 len = 4; 693 else 694 len = 0; 695 } 696 if (len && (len <= 2 || !ISALPHA (rest[len]))) 697 { 698 /* Handle assignment here. */ 699 if (line_start[-1] == '\n') 700 { 701 bump_line_counters (); 702 LISTING_NEWLINE (); 703 } 704 input_line_pointer = rest + len - 1; 705 /* Allow redefining with "DEFL" (len == 4), but not with "EQU". */ 706 switch (len) 707 { 708 case 1: /* label = expr */ 709 case 4: /* label DEFL expr */ 710 equals (name, 1); 711 break; 712 case 2: /* label == expr */ 713 case 3: /* label EQU expr */ 714 equals (name, 0); 715 break; 716 } 717 return 1; 718 } 719 else 720 { 721 /* Restore line and pointer. */ 722 (void) restore_line_pointer (c); 723 input_line_pointer = line_start; 724 } 725 } 726 return 0; 727 } 728 729 symbolS * 730 md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 731 { 732 return NULL; 733 } 734 735 const char * 736 md_atof (int type, char *litP, int *sizeP) 737 { 738 switch (type) 739 { 740 case 'f': 741 case 'F': 742 case 's': 743 case 'S': 744 if (str_to_float) 745 return str_to_float (litP, sizeP); 746 break; 747 case 'd': 748 case 'D': 749 case 'r': 750 case 'R': 751 if (str_to_double) 752 return str_to_double (litP, sizeP); 753 break; 754 } 755 return ieee_md_atof (type, litP, sizeP, false); 756 } 757 758 valueT 759 md_section_align (segT seg ATTRIBUTE_UNUSED, valueT size) 760 { 761 return size; 762 } 763 764 long 765 md_pcrel_from (fixS * fixp) 766 { 767 return fixp->fx_where + fixp->fx_frag->fr_address; 768 } 769 770 typedef const char * (asfunc)(char, char, const char*); 771 772 typedef struct _table_t 773 { 774 const char* name; 775 unsigned char prefix; 776 unsigned char opcode; 777 asfunc * fp; 778 unsigned inss; /*0 - all CPU types or list of supported INS_* */ 779 } table_t; 780 781 /* Compares the key for structs that start with a char * to the key. */ 782 static int 783 key_cmp (const void * a, const void * b) 784 { 785 const char *str_a, *str_b; 786 787 str_a = *((const char**)a); 788 str_b = *((const char**)b); 789 return strcmp (str_a, str_b); 790 } 791 792 char buf[BUFLEN]; 793 const char *key = buf; 794 795 /* Prevent an error on a line from also generating 796 a "junk at end of line" error message. */ 797 static char err_flag; 798 799 static void 800 error (const char * message) 801 { 802 if (err_flag) 803 return; 804 805 as_bad ("%s", message); 806 err_flag = 1; 807 } 808 809 static void 810 ill_op (void) 811 { 812 error (_("illegal operand")); 813 } 814 815 static void 816 wrong_mach (int ins_type) 817 { 818 if (ins_type & ins_err) 819 ill_op (); 820 else 821 as_warn (_("undocumented instruction")); 822 } 823 824 static void 825 check_mach (int ins_type) 826 { 827 if ((ins_type & ins_ok) == 0) 828 wrong_mach (ins_type); 829 } 830 831 /* Check whether an expression is indirect. */ 832 static int 833 is_indir (const char *s) 834 { 835 char quote; 836 const char *p; 837 int indir, depth; 838 839 /* Indirection is indicated with parentheses. */ 840 indir = (*s == '('); 841 842 for (p = s, depth = 0; *p && *p != ','; ++p) 843 { 844 switch (*p) 845 { 846 case '"': 847 case '\'': 848 for (quote = *p++; quote != *p && *p != '\n'; ++p) 849 if (*p == '\\' && p[1]) 850 ++p; 851 break; 852 case '(': 853 ++ depth; 854 break; 855 case ')': 856 -- depth; 857 if (depth == 0) 858 { 859 p = skip_space (p + 1); 860 if (*p && *p != ',') 861 indir = 0; 862 --p; 863 } 864 if (depth < 0) 865 error (_("mismatched parentheses")); 866 break; 867 } 868 } 869 870 if (depth != 0) 871 error (_("mismatched parentheses")); 872 873 return indir; 874 } 875 876 /* Check whether a symbol involves a register. */ 877 static bool 878 contains_register (symbolS *sym) 879 { 880 if (sym) 881 { 882 expressionS * ex = symbol_get_value_expression (sym); 883 884 switch (ex->X_op) 885 { 886 case O_register: 887 return true; 888 889 case O_add: 890 case O_subtract: 891 if (ex->X_op_symbol && contains_register (ex->X_op_symbol)) 892 return true; 893 /* Fall through. */ 894 case O_uminus: 895 case O_symbol: 896 if (ex->X_add_symbol && contains_register (ex->X_add_symbol)) 897 return true; 898 break; 899 900 default: 901 break; 902 } 903 } 904 905 return false; 906 } 907 908 /* Parse general expression, not looking for indexed addressing. */ 909 static const char * 910 parse_exp_not_indexed (const char *s, expressionS *op) 911 { 912 const char *p; 913 int indir; 914 int make_shift = -1; 915 916 memset (op, 0, sizeof (*op)); 917 p = skip_space (s); 918 if (sdcc_compat && (*p == '<' || *p == '>')) 919 { 920 switch (*p) 921 { 922 case '<': /* LSB request */ 923 make_shift = 0; 924 break; 925 case '>': /* MSB request */ 926 make_shift = cpu_mode ? 16 : 8; 927 break; 928 } 929 s = ++p; 930 p = skip_space (p); 931 } 932 933 if (make_shift == -1) 934 indir = is_indir (p); 935 else 936 indir = 0; 937 op->X_md = indir; 938 if (indir && (ins_ok & INS_GBZ80)) 939 { /* check for instructions like ld a,(hl+), ld (hl-),a */ 940 p = skip_space (p+1); 941 if (!strncasecmp (p, "hl", 2)) 942 { 943 p = skip_space(p+2); 944 if (*skip_space(p+1) == ')' && (*p == '+' || *p == '-')) 945 { 946 op->X_op = O_md1; 947 op->X_add_symbol = NULL; 948 op->X_add_number = (*p == '+') ? REG_HL : -REG_HL; 949 input_line_pointer = (char*)skip_space(p + 1) + 1; 950 return input_line_pointer; 951 } 952 } 953 } 954 input_line_pointer = (char*) s ; 955 expression (op); 956 resolve_register (op); 957 switch (op->X_op) 958 { 959 case O_absent: 960 error (_("missing operand")); 961 break; 962 case O_illegal: 963 error (_("bad expression syntax")); 964 break; 965 default: 966 break; 967 } 968 969 if (make_shift >= 0) 970 { 971 /* replace [op] by [op >> shift] */ 972 expressionS data; 973 op->X_add_symbol = make_expr_symbol (op); 974 op->X_add_number = 0; 975 op->X_op = O_right_shift; 976 memset (&data, 0, sizeof (data)); 977 data.X_op = O_constant; 978 data.X_add_number = make_shift; 979 op->X_op_symbol = make_expr_symbol (&data); 980 } 981 return input_line_pointer; 982 } 983 984 static int 985 unify_indexed (expressionS *op) 986 { 987 if (O_register != symbol_get_value_expression (op->X_add_symbol)->X_op) 988 return 0; 989 990 int rnum = symbol_get_value_expression (op->X_add_symbol)->X_add_number; 991 if ( ((REG_IX != rnum) && (REG_IY != rnum)) || contains_register (op->X_op_symbol)) 992 { 993 ill_op (); 994 return 0; 995 } 996 997 /* Convert subtraction to addition of negative value. */ 998 if (O_subtract == op->X_op) 999 { 1000 expressionS minus; 1001 memset (&minus, 0, sizeof (minus)); 1002 minus.X_op = O_uminus; 1003 minus.X_add_symbol = op->X_op_symbol; 1004 op->X_op_symbol = make_expr_symbol (&minus); 1005 op->X_op = O_add; 1006 } 1007 1008 /* Clear X_add_number of the expression. */ 1009 if (op->X_add_number != 0) 1010 { 1011 expressionS add; 1012 memset (&add, 0, sizeof (add)); 1013 add.X_op = O_symbol; 1014 add.X_add_number = op->X_add_number; 1015 add.X_add_symbol = op->X_op_symbol; 1016 op->X_add_symbol = make_expr_symbol (&add); 1017 } 1018 else 1019 op->X_add_symbol = op->X_op_symbol; 1020 1021 op->X_add_number = rnum; 1022 op->X_op_symbol = 0; 1023 return 1; 1024 } 1025 1026 /* Parse expression, change operator to O_md1 for indexed addressing. */ 1027 static const char * 1028 parse_exp (const char *s, expressionS *op) 1029 { 1030 const char* res = parse_exp_not_indexed (s, op); 1031 switch (op->X_op) 1032 { 1033 case O_add: 1034 case O_subtract: 1035 if (unify_indexed (op) && op->X_md) 1036 op->X_op = O_md1; 1037 break; 1038 case O_register: 1039 if (op->X_md && ((REG_IX == op->X_add_number) || (REG_IY == op->X_add_number))) 1040 { 1041 op->X_add_symbol = zero; 1042 op->X_op = O_md1; 1043 } 1044 break; 1045 case O_constant: 1046 /* parse SDCC syntax where index register offset placed before parentheses */ 1047 if (sdcc_compat && is_indir (res)) 1048 { 1049 expressionS off; 1050 off = *op; 1051 res = parse_exp (res, op); 1052 if (op->X_op != O_md1 || op->X_add_symbol != zero) 1053 ill_op (); 1054 else 1055 op->X_add_symbol = make_expr_symbol (&off); 1056 } 1057 break; 1058 default: 1059 break; 1060 } 1061 return res; 1062 } 1063 1064 /* Condition codes, including some synonyms provided by HiTech zas. */ 1065 static const struct reg_entry cc_tab[] = 1066 { 1067 { "age", 6 << 3, INS_ALL }, 1068 { "alt", 7 << 3, INS_ALL }, 1069 { "c", 3 << 3, INS_ALL }, 1070 { "di", 4 << 3, INS_ALL }, 1071 { "ei", 5 << 3, INS_ALL }, 1072 { "lge", 2 << 3, INS_ALL }, 1073 { "llt", 3 << 3, INS_ALL }, 1074 { "m", 7 << 3, INS_ALL }, 1075 { "nc", 2 << 3, INS_ALL }, 1076 { "nz", 0 << 3, INS_ALL }, 1077 { "p", 6 << 3, INS_ALL }, 1078 { "pe", 5 << 3, INS_ALL }, 1079 { "po", 4 << 3, INS_ALL }, 1080 { "z", 1 << 3, INS_ALL }, 1081 } ; 1082 1083 /* Parse condition code. */ 1084 static const char * 1085 parse_cc (const char *s, char * op) 1086 { 1087 const char *p; 1088 int i; 1089 struct reg_entry * cc_p; 1090 1091 for (i = 0; i < BUFLEN; ++i) 1092 { 1093 if (!ISALPHA (s[i])) /* Condition codes consist of letters only. */ 1094 break; 1095 buf[i] = TOLOWER (s[i]); 1096 } 1097 1098 if ((i < BUFLEN) 1099 && ((s[i] == 0) || (s[i] == ','))) 1100 { 1101 buf[i] = 0; 1102 cc_p = bsearch (&key, cc_tab, ARRAY_SIZE (cc_tab), 1103 sizeof (cc_tab[0]), key_cmp); 1104 } 1105 else 1106 cc_p = NULL; 1107 1108 if (cc_p) 1109 { 1110 *op = cc_p->number; 1111 p = s + i; 1112 } 1113 else 1114 p = NULL; 1115 1116 return p; 1117 } 1118 1119 static const char * 1120 emit_insn (char prefix, char opcode, const char * args) 1121 { 1122 char *p; 1123 1124 if (prefix) 1125 { 1126 p = frag_more (2); 1127 *p++ = prefix; 1128 } 1129 else 1130 p = frag_more (1); 1131 *p = opcode; 1132 return args; 1133 } 1134 1135 void z80_cons_fix_new (fragS *frag_p, int offset, int nbytes, expressionS *exp) 1136 { 1137 bfd_reloc_code_real_type r[4] = 1138 { 1139 BFD_RELOC_8, 1140 BFD_RELOC_16, 1141 BFD_RELOC_24, 1142 BFD_RELOC_32 1143 }; 1144 1145 if (nbytes < 1 || nbytes > 4) 1146 { 1147 as_bad (_("unsupported BFD relocation size %u"), nbytes); 1148 } 1149 else 1150 { 1151 fix_new_exp (frag_p, offset, nbytes, exp, 0, r[nbytes-1]); 1152 } 1153 } 1154 1155 static void 1156 emit_data_val (expressionS * val, int size) 1157 { 1158 char *p; 1159 bfd_reloc_code_real_type r_type; 1160 1161 p = frag_more (size); 1162 if (val->X_op == O_constant) 1163 { 1164 int i; 1165 1166 /* PR 28791: 1167 Check for overflow, but ignore values that were generated by bit 1168 manipulation operators (eg ~0xe6 and -7). This does mean that 1169 manipluated overlarge values will not be reported (eg ~0x1234), 1170 but it does help to maintain compatibility with earlier versions 1171 of the assembler. */ 1172 if (! val->X_extrabit 1173 && is_overflow (val->X_add_number, size * 8)) 1174 as_warn ( _("%d-bit overflow (%+" PRId64 ")"), size * 8, 1175 (int64_t) val->X_add_number); 1176 for (i = 0; i < size; ++i) 1177 p[i] = (val->X_add_number >> (i * 8)) & 0xff; 1178 return; 1179 } 1180 1181 switch (size) 1182 { 1183 case 1: r_type = BFD_RELOC_8; break; 1184 case 2: r_type = BFD_RELOC_16; break; 1185 case 3: r_type = BFD_RELOC_24; break; 1186 case 4: r_type = BFD_RELOC_32; break; 1187 case 8: r_type = BFD_RELOC_64; break; 1188 default: 1189 as_fatal (_("invalid data size %d"), size); 1190 } 1191 1192 if ( (val->X_op == O_register) 1193 || (val->X_op == O_md1) 1194 || contains_register (val->X_add_symbol) 1195 || contains_register (val->X_op_symbol)) 1196 ill_op (); 1197 1198 if (size <= 2 && val->X_op_symbol) 1199 { 1200 bool simplify = true; 1201 int shift = symbol_get_value_expression (val->X_op_symbol)->X_add_number; 1202 if (val->X_op == O_bit_and && shift == (1 << (size*8))-1) 1203 shift = 0; 1204 else if (val->X_op != O_right_shift) 1205 shift = -1; 1206 1207 if (size == 1) 1208 { 1209 switch (shift) 1210 { 1211 case 0: r_type = BFD_RELOC_Z80_BYTE0; break; 1212 case 8: r_type = BFD_RELOC_Z80_BYTE1; break; 1213 case 16: r_type = BFD_RELOC_Z80_BYTE2; break; 1214 case 24: r_type = BFD_RELOC_Z80_BYTE3; break; 1215 default: simplify = false; 1216 } 1217 } 1218 else /* if (size == 2) */ 1219 { 1220 switch (shift) 1221 { 1222 case 0: r_type = BFD_RELOC_Z80_WORD0; break; 1223 case 16: r_type = BFD_RELOC_Z80_WORD1; break; 1224 case 8: 1225 case 24: /* add two byte fixups */ 1226 val->X_op = O_symbol; 1227 val->X_op_symbol = NULL; 1228 val->X_add_number = 0; 1229 if (shift == 8) 1230 { 1231 fix_new_exp (frag_now, p++ - frag_now->fr_literal, 1, val, false, 1232 BFD_RELOC_Z80_BYTE1); 1233 /* prepare to next byte */ 1234 r_type = BFD_RELOC_Z80_BYTE2; 1235 } 1236 else 1237 r_type = BFD_RELOC_Z80_BYTE3; /* high byte will be 0 */ 1238 size = 1; 1239 simplify = false; 1240 break; 1241 default: simplify = false; 1242 } 1243 } 1244 1245 if (simplify) 1246 { 1247 val->X_op = O_symbol; 1248 val->X_op_symbol = NULL; 1249 val->X_add_number = 0; 1250 } 1251 } 1252 1253 fix_new_exp (frag_now, p - frag_now->fr_literal, size, val, false, r_type); 1254 } 1255 1256 static void 1257 emit_byte (expressionS * val, bfd_reloc_code_real_type r_type) 1258 { 1259 char *p; 1260 1261 if (r_type == BFD_RELOC_8) 1262 { 1263 emit_data_val (val, 1); 1264 return; 1265 } 1266 p = frag_more (1); 1267 *p = val->X_add_number; 1268 if (contains_register (val->X_add_symbol) || contains_register (val->X_op_symbol)) 1269 { 1270 ill_op (); 1271 } 1272 else if ((r_type == BFD_RELOC_8_PCREL) && (val->X_op == O_constant)) 1273 { 1274 as_bad (_("cannot make a relative jump to an absolute location")); 1275 } 1276 else if (val->X_op == O_constant) 1277 { 1278 if ((val->X_add_number < -128) || (val->X_add_number >= 128)) 1279 { 1280 if (r_type == BFD_RELOC_Z80_DISP8) 1281 as_bad (_("index overflow (%+" PRId64 ")"), 1282 (int64_t) val->X_add_number); 1283 else 1284 as_bad (_("offset overflow (%+" PRId64 ")"), 1285 (int64_t) val->X_add_number); 1286 } 1287 } 1288 else 1289 { 1290 /* For symbols only, constants are stored at begin of function. */ 1291 fix_new_exp (frag_now, p - frag_now->fr_literal, 1, val, 1292 r_type == BFD_RELOC_8_PCREL, r_type); 1293 } 1294 } 1295 1296 static void 1297 emit_word (expressionS * val) 1298 { 1299 emit_data_val (val, (inst_mode & INST_MODE_IL) ? 3 : 2); 1300 } 1301 1302 static void 1303 emit_mx (char prefix, char opcode, int shift, expressionS * arg) 1304 /* The operand m may be r, (hl), (ix+d), (iy+d), 1305 if 0 == prefix m may also be ixl, ixh, iyl, iyh. */ 1306 { 1307 char *q; 1308 int rnum; 1309 1310 rnum = arg->X_add_number; 1311 switch (arg->X_op) 1312 { 1313 case O_register: 1314 if (arg->X_md) 1315 { 1316 if (rnum != REG_HL) 1317 { 1318 ill_op (); 1319 break; 1320 } 1321 else 1322 rnum = 6; 1323 } 1324 else 1325 { 1326 if ((prefix == 0) && (rnum & R_INDEX)) 1327 { 1328 prefix = (rnum & R_IX) ? 0xDD : 0xFD; 1329 if (!(ins_ok & (INS_EZ80|INS_R800|INS_Z80N))) 1330 check_mach (INS_IDX_HALF); 1331 rnum &= ~R_INDEX; 1332 } 1333 if (rnum > 7) 1334 { 1335 ill_op (); 1336 break; 1337 } 1338 } 1339 q = frag_more (prefix ? 2 : 1); 1340 if (prefix) 1341 * q ++ = prefix; 1342 * q ++ = opcode + (rnum << shift); 1343 break; 1344 case O_md1: 1345 if (ins_ok & INS_GBZ80) 1346 { 1347 ill_op (); 1348 break; 1349 } 1350 q = frag_more (2); 1351 *q++ = (rnum & R_IX) ? 0xDD : 0xFD; 1352 *q = (prefix) ? prefix : (opcode + (6 << shift)); 1353 { 1354 expressionS offset = *arg; 1355 offset.X_op = O_symbol; 1356 offset.X_add_number = 0; 1357 emit_byte (&offset, BFD_RELOC_Z80_DISP8); 1358 } 1359 if (prefix) 1360 { 1361 q = frag_more (1); 1362 *q = opcode+(6<<shift); 1363 } 1364 break; 1365 default: 1366 abort (); 1367 } 1368 } 1369 1370 /* The operand m may be r, (hl), (ix+d), (iy+d), 1371 if 0 = prefix m may also be ixl, ixh, iyl, iyh. */ 1372 static const char * 1373 emit_m (char prefix, char opcode, const char *args) 1374 { 1375 expressionS arg_m; 1376 const char *p; 1377 1378 p = parse_exp (args, &arg_m); 1379 switch (arg_m.X_op) 1380 { 1381 case O_md1: 1382 case O_register: 1383 emit_mx (prefix, opcode, 0, &arg_m); 1384 break; 1385 default: 1386 ill_op (); 1387 } 1388 return p; 1389 } 1390 1391 /* The operand m may be as above or one of the undocumented 1392 combinations (ix+d),r and (iy+d),r (if unportable instructions 1393 are allowed). */ 1394 1395 static const char * 1396 emit_mr (char prefix, char opcode, const char *args) 1397 { 1398 expressionS arg_m, arg_r; 1399 const char *p; 1400 1401 p = parse_exp (args, & arg_m); 1402 1403 switch (arg_m.X_op) 1404 { 1405 case O_md1: 1406 if (*p == ',') 1407 { 1408 p = parse_exp (p + 1, & arg_r); 1409 1410 if ((arg_r.X_md == 0) 1411 && (arg_r.X_op == O_register) 1412 && (arg_r.X_add_number < 8)) 1413 opcode += arg_r.X_add_number - 6; /* Emit_mx () will add 6. */ 1414 else 1415 { 1416 ill_op (); 1417 break; 1418 } 1419 if (!(ins_ok & INS_Z80N)) 1420 check_mach (INS_ROT_II_LD); 1421 } 1422 /* Fall through. */ 1423 case O_register: 1424 emit_mx (prefix, opcode, 0, & arg_m); 1425 break; 1426 default: 1427 ill_op (); 1428 } 1429 return p; 1430 } 1431 1432 static void 1433 emit_sx (char prefix, char opcode, expressionS * arg_p) 1434 { 1435 char *q; 1436 1437 switch (arg_p->X_op) 1438 { 1439 case O_register: 1440 case O_md1: 1441 emit_mx (prefix, opcode, 0, arg_p); 1442 break; 1443 default: 1444 if (arg_p->X_md) 1445 ill_op (); 1446 else 1447 { 1448 q = frag_more (prefix ? 2 : 1); 1449 if (prefix) 1450 *q++ = prefix; 1451 *q = opcode ^ 0x46; 1452 emit_byte (arg_p, BFD_RELOC_8); 1453 } 1454 } 1455 } 1456 1457 /* The operand s may be r, (hl), (ix+d), (iy+d), n. */ 1458 static const char * 1459 emit_s (char prefix, char opcode, const char *args) 1460 { 1461 expressionS arg_s; 1462 const char *p; 1463 1464 p = parse_exp (args, & arg_s); 1465 if (*p == ',' && arg_s.X_md == 0 && arg_s.X_op == O_register && arg_s.X_add_number == REG_A) 1466 { /* possible instruction in generic format op A,x */ 1467 if (!(ins_ok & INS_EZ80) && !sdcc_compat) 1468 ill_op (); 1469 ++p; 1470 p = parse_exp (p, & arg_s); 1471 } 1472 emit_sx (prefix, opcode, & arg_s); 1473 return p; 1474 } 1475 1476 static const char * 1477 emit_sub (char prefix, char opcode, const char *args) 1478 { 1479 expressionS arg_s; 1480 const char *p; 1481 1482 if (!(ins_ok & INS_GBZ80)) 1483 return emit_s (prefix, opcode, args); 1484 p = parse_exp (args, & arg_s); 1485 if (*p++ != ',') 1486 { 1487 error (_("bad instruction syntax")); 1488 return p; 1489 } 1490 1491 if (arg_s.X_md != 0 || arg_s.X_op != O_register || arg_s.X_add_number != REG_A) 1492 ill_op (); 1493 1494 p = parse_exp (p, & arg_s); 1495 1496 emit_sx (prefix, opcode, & arg_s); 1497 return p; 1498 } 1499 1500 static const char * 1501 emit_swap (char prefix, char opcode, const char *args) 1502 { 1503 expressionS reg; 1504 const char *p; 1505 char *q; 1506 1507 if (!(ins_ok & INS_Z80N)) 1508 return emit_mr (prefix, opcode, args); 1509 1510 /* check for alias swap a for swapnib of Z80N */ 1511 p = parse_exp (args, ®); 1512 if (reg.X_md != 0 || reg.X_op != O_register || reg.X_add_number != REG_A) 1513 ill_op (); 1514 1515 q = frag_more (2); 1516 *q++ = 0xED; 1517 *q = 0x23; 1518 return p; 1519 } 1520 1521 static const char * 1522 emit_call (char prefix ATTRIBUTE_UNUSED, char opcode, const char * args) 1523 { 1524 expressionS addr; 1525 const char *p; char *q; 1526 1527 p = parse_exp_not_indexed (args, &addr); 1528 if (addr.X_md) 1529 ill_op (); 1530 else 1531 { 1532 q = frag_more (1); 1533 *q = opcode; 1534 emit_word (& addr); 1535 } 1536 return p; 1537 } 1538 1539 /* Operand may be rr, r, (hl), (ix+d), (iy+d). */ 1540 static const char * 1541 emit_incdec (char prefix, char opcode, const char * args) 1542 { 1543 expressionS operand; 1544 int rnum; 1545 const char *p; char *q; 1546 1547 p = parse_exp (args, &operand); 1548 rnum = operand.X_add_number; 1549 if ((! operand.X_md) 1550 && (operand.X_op == O_register) 1551 && (R_ARITH&rnum)) 1552 { 1553 q = frag_more ((rnum & R_INDEX) ? 2 : 1); 1554 if (rnum & R_INDEX) 1555 *q++ = (rnum & R_IX) ? 0xDD : 0xFD; 1556 *q = prefix + ((rnum & 3) << 4); 1557 } 1558 else 1559 { 1560 if ((operand.X_op == O_md1) || (operand.X_op == O_register)) 1561 emit_mx (0, opcode, 3, & operand); 1562 else 1563 ill_op (); 1564 } 1565 return p; 1566 } 1567 1568 static const char * 1569 emit_jr (char prefix ATTRIBUTE_UNUSED, char opcode, const char * args) 1570 { 1571 expressionS addr; 1572 const char *p; 1573 char *q; 1574 1575 p = parse_exp_not_indexed (args, &addr); 1576 if (addr.X_md) 1577 ill_op (); 1578 else 1579 { 1580 q = frag_more (1); 1581 *q = opcode; 1582 addr.X_add_number--; /* pcrel computes after offset code */ 1583 emit_byte (&addr, BFD_RELOC_8_PCREL); 1584 } 1585 return p; 1586 } 1587 1588 static const char * 1589 emit_jp (char prefix, char opcode, const char * args) 1590 { 1591 expressionS addr; 1592 const char *p; 1593 char *q; 1594 int rnum; 1595 1596 p = parse_exp_not_indexed (args, & addr); 1597 if (addr.X_md) 1598 { 1599 rnum = addr.X_add_number; 1600 if ((O_register == addr.X_op) && (REG_HL == (rnum & ~R_INDEX))) 1601 { 1602 q = frag_more ((rnum & R_INDEX) ? 2 : 1); 1603 if (rnum & R_INDEX) 1604 *q++ = (rnum & R_IX) ? 0xDD : 0xFD; 1605 *q = prefix; 1606 } 1607 else if (addr.X_op == O_register && rnum == REG_C && (ins_ok & INS_Z80N)) 1608 { 1609 q = frag_more (2); 1610 *q++ = 0xED; 1611 *q = 0x98; 1612 } 1613 else 1614 ill_op (); 1615 } 1616 else 1617 { 1618 q = frag_more (1); 1619 *q = opcode; 1620 emit_word (& addr); 1621 } 1622 return p; 1623 } 1624 1625 static const char * 1626 emit_im (char prefix, char opcode, const char * args) 1627 { 1628 expressionS mode; 1629 const char *p; 1630 char *q; 1631 1632 p = parse_exp (args, & mode); 1633 if (mode.X_md || (mode.X_op != O_constant)) 1634 ill_op (); 1635 else 1636 switch (mode.X_add_number) 1637 { 1638 case 1: 1639 case 2: 1640 ++mode.X_add_number; 1641 /* Fall through. */ 1642 case 0: 1643 q = frag_more (2); 1644 *q++ = prefix; 1645 *q = opcode + 8*mode.X_add_number; 1646 break; 1647 default: 1648 ill_op (); 1649 } 1650 return p; 1651 } 1652 1653 static const char * 1654 emit_pop (char prefix ATTRIBUTE_UNUSED, char opcode, const char * args) 1655 { 1656 expressionS regp; 1657 const char *p; 1658 char *q; 1659 1660 p = parse_exp (args, & regp); 1661 if ((!regp.X_md) 1662 && (regp.X_op == O_register) 1663 && (regp.X_add_number & R_STACKABLE)) 1664 { 1665 int rnum; 1666 1667 rnum = regp.X_add_number; 1668 if (rnum&R_INDEX) 1669 { 1670 q = frag_more (2); 1671 *q++ = (rnum&R_IX)?0xDD:0xFD; 1672 } 1673 else 1674 q = frag_more (1); 1675 *q = opcode + ((rnum & 3) << 4); 1676 } 1677 else 1678 ill_op (); 1679 1680 return p; 1681 } 1682 1683 static const char * 1684 emit_push (char prefix, char opcode, const char * args) 1685 { 1686 expressionS arg; 1687 const char *p; 1688 char *q; 1689 1690 p = parse_exp (args, & arg); 1691 if (arg.X_op == O_register) 1692 return emit_pop (prefix, opcode, args); 1693 1694 if (arg.X_md || arg.X_op == O_md1 || !(ins_ok & INS_Z80N)) 1695 ill_op (); 1696 1697 q = frag_more (2); 1698 *q++ = 0xED; 1699 *q = 0x8A; 1700 1701 q = frag_more (2); 1702 fix_new_exp (frag_now, q - frag_now->fr_literal, 2, &arg, false, 1703 BFD_RELOC_Z80_16_BE); 1704 1705 return p; 1706 } 1707 1708 static const char * 1709 emit_retcc (char prefix ATTRIBUTE_UNUSED, char opcode, const char * args) 1710 { 1711 char cc, *q; 1712 const char *p; 1713 1714 p = parse_cc (args, &cc); 1715 q = frag_more (1); 1716 if (p) 1717 *q = opcode + cc; 1718 else 1719 *q = prefix; 1720 return p ? p : args; 1721 } 1722 1723 static const char * 1724 emit_adc (char prefix, char opcode, const char * args) 1725 { 1726 expressionS term; 1727 int rnum; 1728 const char *p; 1729 char *q; 1730 1731 p = parse_exp (args, &term); 1732 if (*p++ != ',') 1733 { 1734 error (_("bad instruction syntax")); 1735 return p; 1736 } 1737 1738 if ((term.X_md) || (term.X_op != O_register)) 1739 ill_op (); 1740 else 1741 switch (term.X_add_number) 1742 { 1743 case REG_A: 1744 p = emit_s (0, prefix, p); 1745 break; 1746 case REG_HL: 1747 p = parse_exp (p, &term); 1748 if ((!term.X_md) && (term.X_op == O_register)) 1749 { 1750 rnum = term.X_add_number; 1751 if (R_ARITH == (rnum & (R_ARITH | R_INDEX))) 1752 { 1753 q = frag_more (2); 1754 *q++ = 0xED; 1755 *q = opcode + ((rnum & 3) << 4); 1756 break; 1757 } 1758 } 1759 /* Fall through. */ 1760 default: 1761 ill_op (); 1762 } 1763 return p; 1764 } 1765 1766 static const char * 1767 emit_add (char prefix, char opcode, const char * args) 1768 { 1769 expressionS term; 1770 int lhs, rhs; 1771 const char *p; 1772 char *q; 1773 1774 p = parse_exp (args, &term); 1775 if (*p++ != ',') 1776 { 1777 error (_("bad instruction syntax")); 1778 return p; 1779 } 1780 1781 if ((term.X_md) || (term.X_op != O_register)) 1782 ill_op (); 1783 else 1784 switch (term.X_add_number) 1785 { 1786 case REG_A: 1787 p = emit_s (0, prefix, p); 1788 break; 1789 case REG_SP: 1790 p = parse_exp (p, &term); 1791 if (!(ins_ok & INS_GBZ80) || term.X_md || term.X_op == O_register) 1792 ill_op (); 1793 q = frag_more (1); 1794 *q = 0xE8; 1795 emit_byte (&term, BFD_RELOC_Z80_DISP8); 1796 break; 1797 case REG_BC: 1798 case REG_DE: 1799 if (!(ins_ok & INS_Z80N)) 1800 { 1801 ill_op (); 1802 break; 1803 } 1804 /* Fall through. */ 1805 case REG_HL: 1806 case REG_IX: 1807 case REG_IY: 1808 lhs = term.X_add_number; 1809 p = parse_exp (p, &term); 1810 rhs = term.X_add_number; 1811 if (term.X_md != 0 || term.X_op == O_md1) 1812 ill_op (); 1813 else if ((term.X_op == O_register) && (rhs & R_ARITH) && (rhs == lhs || (rhs & ~R_INDEX) != REG_HL)) 1814 { 1815 if (1) 1816 { 1817 q = frag_more ((lhs & R_INDEX) ? 2 : 1); 1818 if (lhs & R_INDEX) 1819 *q++ = (lhs & R_IX) ? 0xDD : 0xFD; 1820 *q = opcode + ((rhs & 3) << 4); 1821 break; 1822 } 1823 } 1824 else if (!(lhs & R_INDEX) && (ins_ok & INS_Z80N)) 1825 { 1826 if (term.X_op == O_register && rhs == REG_A) 1827 { /* ADD BC/DE/HL,A */ 1828 q = frag_more (2); 1829 *q++ = 0xED; 1830 *q = 0x33 - (lhs & 3); 1831 break; 1832 } 1833 else if (term.X_op != O_register && term.X_op != O_md1) 1834 { /* ADD BC/DE/HL,nn */ 1835 q = frag_more (2); 1836 *q++ = 0xED; 1837 *q = 0x36 - (lhs & 3); 1838 emit_word (&term); 1839 break; 1840 } 1841 } 1842 /* Fall through. */ 1843 default: 1844 ill_op (); 1845 } 1846 return p; 1847 } 1848 1849 static const char * 1850 emit_bit (char prefix, char opcode, const char * args) 1851 { 1852 expressionS b; 1853 int bn; 1854 const char *p; 1855 1856 p = parse_exp (args, &b); 1857 if (*p++ != ',') 1858 error (_("bad instruction syntax")); 1859 1860 bn = b.X_add_number; 1861 if ((!b.X_md) 1862 && (b.X_op == O_constant) 1863 && (0 <= bn) 1864 && (bn < 8)) 1865 { 1866 if (opcode == 0x40) 1867 /* Bit : no optional third operand. */ 1868 p = emit_m (prefix, opcode + (bn << 3), p); 1869 else 1870 /* Set, res : resulting byte can be copied to register. */ 1871 p = emit_mr (prefix, opcode + (bn << 3), p); 1872 } 1873 else 1874 ill_op (); 1875 return p; 1876 } 1877 1878 /* BSLA DE,B; BSRA DE,B; BSRL DE,B; BSRF DE,B; BRLC DE,B (Z80N only) */ 1879 static const char * 1880 emit_bshft (char prefix, char opcode, const char * args) 1881 { 1882 expressionS r1, r2; 1883 const char *p; 1884 char *q; 1885 1886 p = parse_exp (args, & r1); 1887 if (*p++ != ',') 1888 error (_("bad instruction syntax")); 1889 p = parse_exp (p, & r2); 1890 if (r1.X_md || r1.X_op != O_register || r1.X_add_number != REG_DE || 1891 r2.X_md || r2.X_op != O_register || r2.X_add_number != REG_B) 1892 ill_op (); 1893 q = frag_more (2); 1894 *q++ = prefix; 1895 *q = opcode; 1896 return p; 1897 } 1898 1899 static const char * 1900 emit_jpcc (char prefix, char opcode, const char * args) 1901 { 1902 char cc; 1903 const char *p; 1904 1905 p = parse_cc (args, & cc); 1906 if (p && *p++ == ',') 1907 p = emit_call (0, opcode + cc, p); 1908 else 1909 p = (prefix == (char)0xC3) 1910 ? emit_jp (0xE9, prefix, args) 1911 : emit_call (0, prefix, args); 1912 return p; 1913 } 1914 1915 static const char * 1916 emit_jrcc (char prefix, char opcode, const char * args) 1917 { 1918 char cc; 1919 const char *p; 1920 1921 p = parse_cc (args, &cc); 1922 if (p && *p++ == ',') 1923 { 1924 if (cc > (3 << 3)) 1925 error (_("condition code invalid for jr")); 1926 else 1927 p = emit_jr (0, opcode + cc, p); 1928 } 1929 else 1930 p = emit_jr (0, prefix, args); 1931 1932 return p; 1933 } 1934 1935 static const char * 1936 emit_ex (char prefix_in ATTRIBUTE_UNUSED, 1937 char opcode_in ATTRIBUTE_UNUSED, const char * args) 1938 { 1939 expressionS op; 1940 const char * p; 1941 char prefix, opcode; 1942 1943 p = parse_exp_not_indexed (args, &op); 1944 p = skip_space (p); 1945 if (*p++ != ',') 1946 { 1947 error (_("bad instruction syntax")); 1948 return p; 1949 } 1950 1951 prefix = opcode = 0; 1952 if (op.X_op == O_register) 1953 switch (op.X_add_number | (op.X_md ? 0x8000 : 0)) 1954 { 1955 case REG_AF: 1956 if (TOLOWER (*p++) == 'a' && TOLOWER (*p++) == 'f') 1957 { 1958 /* The scrubber changes '\'' to '`' in this context. */ 1959 if (*p == '`') 1960 ++p; 1961 opcode = 0x08; 1962 } 1963 break; 1964 case REG_DE: 1965 if (TOLOWER (*p++) == 'h' && TOLOWER (*p++) == 'l') 1966 opcode = 0xEB; 1967 break; 1968 case REG_SP|0x8000: 1969 p = parse_exp (p, & op); 1970 if (op.X_op == O_register 1971 && op.X_md == 0 1972 && (op.X_add_number & ~R_INDEX) == REG_HL) 1973 { 1974 opcode = 0xE3; 1975 if (R_INDEX & op.X_add_number) 1976 prefix = (R_IX & op.X_add_number) ? 0xDD : 0xFD; 1977 } 1978 break; 1979 } 1980 if (opcode) 1981 emit_insn (prefix, opcode, p); 1982 else 1983 ill_op (); 1984 1985 return p; 1986 } 1987 1988 static const char * 1989 emit_in (char prefix ATTRIBUTE_UNUSED, char opcode ATTRIBUTE_UNUSED, 1990 const char * args) 1991 { 1992 expressionS reg, port; 1993 const char *p; 1994 char *q; 1995 1996 p = parse_exp (args, ®); 1997 if (reg.X_md && reg.X_op == O_register && reg.X_add_number == REG_C) 1998 { /* permit instruction in (c) as alias for in f,(c) */ 1999 port = reg; 2000 reg.X_md = 0; 2001 reg.X_add_number = REG_F; 2002 } 2003 else 2004 { 2005 if (*p++ != ',') 2006 { 2007 error (_("bad instruction syntax")); 2008 return p; 2009 } 2010 p = parse_exp (p, &port); 2011 } 2012 if (reg.X_md == 0 2013 && reg.X_op == O_register 2014 && (reg.X_add_number <= 7 || reg.X_add_number == REG_F) 2015 && (port.X_md)) 2016 { 2017 if (port.X_op != O_md1 && port.X_op != O_register) 2018 { 2019 if (REG_A == reg.X_add_number) 2020 { 2021 q = frag_more (1); 2022 *q = 0xDB; 2023 emit_byte (&port, BFD_RELOC_8); 2024 } 2025 else 2026 ill_op (); 2027 } 2028 else 2029 { 2030 if (port.X_add_number == REG_C || port.X_add_number == REG_BC) 2031 { 2032 if (port.X_add_number == REG_BC && !(ins_ok & INS_EZ80)) 2033 ill_op (); 2034 else if (reg.X_add_number == REG_F && !(ins_ok & (INS_R800|INS_Z80N))) 2035 check_mach (INS_IN_F_C); 2036 q = frag_more (2); 2037 *q++ = 0xED; 2038 *q = 0x40|((reg.X_add_number&7)<<3); 2039 } 2040 else 2041 ill_op (); 2042 } 2043 } 2044 else 2045 ill_op (); 2046 return p; 2047 } 2048 2049 static const char * 2050 emit_in0 (char prefix ATTRIBUTE_UNUSED, char opcode ATTRIBUTE_UNUSED, 2051 const char * args) 2052 { 2053 expressionS reg, port; 2054 const char *p; 2055 char *q; 2056 2057 p = parse_exp (args, ®); 2058 if (*p++ != ',') 2059 { 2060 error (_("bad instruction syntax")); 2061 return p; 2062 } 2063 2064 p = parse_exp (p, &port); 2065 if (reg.X_md == 0 2066 && reg.X_op == O_register 2067 && reg.X_add_number <= 7 2068 && port.X_md 2069 && port.X_op != O_md1 2070 && port.X_op != O_register) 2071 { 2072 q = frag_more (2); 2073 *q++ = 0xED; 2074 *q = 0x00|(reg.X_add_number << 3); 2075 emit_byte (&port, BFD_RELOC_8); 2076 } 2077 else 2078 ill_op (); 2079 return p; 2080 } 2081 2082 static const char * 2083 emit_out (char prefix ATTRIBUTE_UNUSED, char opcode ATTRIBUTE_UNUSED, 2084 const char * args) 2085 { 2086 expressionS reg, port; 2087 const char *p; 2088 char *q; 2089 2090 p = parse_exp (args, & port); 2091 if (*p++ != ',') 2092 { 2093 error (_("bad instruction syntax")); 2094 return p; 2095 } 2096 p = parse_exp (p, ®); 2097 if (!port.X_md) 2098 { ill_op (); return p; } 2099 /* Allow "out (c), 0" as unportable instruction. */ 2100 if (reg.X_op == O_constant && reg.X_add_number == 0) 2101 { 2102 if (!(ins_ok & INS_Z80N)) 2103 check_mach (INS_OUT_C_0); 2104 reg.X_op = O_register; 2105 reg.X_add_number = 6; 2106 } 2107 if (reg.X_md 2108 || reg.X_op != O_register 2109 || reg.X_add_number > 7) 2110 ill_op (); 2111 else 2112 if (port.X_op != O_register && port.X_op != O_md1) 2113 { 2114 if (REG_A == reg.X_add_number) 2115 { 2116 q = frag_more (1); 2117 *q = 0xD3; 2118 emit_byte (&port, BFD_RELOC_8); 2119 } 2120 else 2121 ill_op (); 2122 } 2123 else 2124 { 2125 if (REG_C == port.X_add_number || port.X_add_number == REG_BC) 2126 { 2127 if (port.X_add_number == REG_BC && !(ins_ok & INS_EZ80)) 2128 ill_op (); 2129 q = frag_more (2); 2130 *q++ = 0xED; 2131 *q = 0x41 | (reg.X_add_number << 3); 2132 } 2133 else 2134 ill_op (); 2135 } 2136 return p; 2137 } 2138 2139 static const char * 2140 emit_out0 (char prefix ATTRIBUTE_UNUSED, char opcode ATTRIBUTE_UNUSED, 2141 const char * args) 2142 { 2143 expressionS reg, port; 2144 const char *p; 2145 char *q; 2146 2147 p = parse_exp (args, & port); 2148 if (*p++ != ',') 2149 { 2150 error (_("bad instruction syntax")); 2151 return p; 2152 } 2153 p = parse_exp (p, ®); 2154 if (port.X_md != 0 2155 && port.X_op != O_register 2156 && port.X_op != O_md1 2157 && reg.X_md == 0 2158 && reg.X_op == O_register 2159 && reg.X_add_number <= 7) 2160 { 2161 q = frag_more (2); 2162 *q++ = 0xED; 2163 *q = 0x01 | (reg.X_add_number << 3); 2164 emit_byte (&port, BFD_RELOC_8); 2165 } 2166 else 2167 ill_op (); 2168 return p; 2169 } 2170 2171 static const char * 2172 emit_rst (char prefix ATTRIBUTE_UNUSED, char opcode, const char * args) 2173 { 2174 expressionS addr; 2175 const char *p; 2176 char *q; 2177 2178 p = parse_exp_not_indexed (args, &addr); 2179 if (addr.X_op != O_constant) 2180 { 2181 error ("rst needs constant address"); 2182 return p; 2183 } 2184 2185 if (addr.X_add_number & ~(7 << 3)) 2186 ill_op (); 2187 else 2188 { 2189 q = frag_more (1); 2190 *q = opcode + (addr.X_add_number & (7 << 3)); 2191 } 2192 return p; 2193 } 2194 2195 /* For 8-bit indirect load to memory instructions like: LD (HL),n or LD (ii+d),n. */ 2196 static void 2197 emit_ld_m_n (expressionS *dst, expressionS *src) 2198 { 2199 char *q; 2200 char prefix; 2201 expressionS dst_offset; 2202 2203 switch (dst->X_add_number) 2204 { 2205 case REG_HL: prefix = 0x00; break; 2206 case REG_IX: prefix = 0xDD; break; 2207 case REG_IY: prefix = 0xFD; break; 2208 default: 2209 ill_op (); 2210 return; 2211 } 2212 2213 q = frag_more (prefix ? 2 : 1); 2214 if (prefix) 2215 *q++ = prefix; 2216 *q = 0x36; 2217 if (prefix) 2218 { 2219 dst_offset = *dst; 2220 dst_offset.X_op = O_symbol; 2221 dst_offset.X_add_number = 0; 2222 emit_byte (& dst_offset, BFD_RELOC_Z80_DISP8); 2223 } 2224 emit_byte (src, BFD_RELOC_8); 2225 } 2226 2227 /* For 8-bit load register to memory instructions: LD (<expression>),r. */ 2228 static void 2229 emit_ld_m_r (expressionS *dst, expressionS *src) 2230 { 2231 char *q; 2232 char prefix = 0; 2233 expressionS dst_offset; 2234 2235 switch (dst->X_op) 2236 { 2237 case O_md1: 2238 if (ins_ok & INS_GBZ80) 2239 { /* LD (HL+),A or LD (HL-),A */ 2240 if (src->X_op != O_register || src->X_add_number != REG_A) 2241 break; 2242 *frag_more (1) = (dst->X_add_number == REG_HL) ? 0x22 : 0x32; 2243 return; 2244 } 2245 else 2246 prefix = (dst->X_add_number == REG_IX) ? 0xDD : 0xFD; 2247 /* Fall through. */ 2248 case O_register: 2249 switch (dst->X_add_number) 2250 { 2251 case REG_BC: /* LD (BC),A */ 2252 case REG_DE: /* LD (DE),A */ 2253 if (src->X_add_number == REG_A) 2254 { 2255 q = frag_more (1); 2256 *q = 0x02 | ((dst->X_add_number & 3) << 4); 2257 return; 2258 } 2259 break; 2260 case REG_IX: 2261 case REG_IY: 2262 case REG_HL: /* LD (HL),r or LD (ii+d),r */ 2263 if (src->X_add_number <= 7) 2264 { 2265 q = frag_more (prefix ? 2 : 1); 2266 if (prefix) 2267 *q++ = prefix; 2268 *q = 0x70 | src->X_add_number; 2269 if (prefix) 2270 { 2271 dst_offset = *dst; 2272 dst_offset.X_op = O_symbol; 2273 dst_offset.X_add_number = 0; 2274 emit_byte (& dst_offset, BFD_RELOC_Z80_DISP8); 2275 } 2276 return; 2277 } 2278 break; 2279 default:; 2280 } 2281 break; 2282 default: /* LD (nn),A */ 2283 if (src->X_add_number == REG_A) 2284 { 2285 q = frag_more (1); 2286 *q = (ins_ok & INS_GBZ80) ? 0xEA : 0x32; 2287 emit_word (dst); 2288 return; 2289 } 2290 break; 2291 } 2292 ill_op (); 2293 } 2294 2295 /* For 16-bit load register to memory instructions: LD (<expression>),rr. */ 2296 static void 2297 emit_ld_m_rr (expressionS *dst, expressionS *src) 2298 { 2299 char *q; 2300 int prefix = 0; 2301 int opcode = 0; 2302 expressionS dst_offset; 2303 2304 switch (dst->X_op) 2305 { 2306 case O_md1: /* eZ80 instructions LD (ii+d),rr */ 2307 case O_register: /* eZ80 instructions LD (HL),rr */ 2308 if (!(ins_ok & INS_EZ80)) /* 16-bit indirect load group is supported by eZ80 only */ 2309 ill_op (); 2310 switch (dst->X_add_number) 2311 { 2312 case REG_IX: prefix = 0xDD; break; 2313 case REG_IY: prefix = 0xFD; break; 2314 case REG_HL: prefix = 0xED; break; 2315 default: 2316 ill_op (); 2317 } 2318 switch (src->X_add_number) 2319 { 2320 case REG_BC: opcode = 0x0F; break; 2321 case REG_DE: opcode = 0x1F; break; 2322 case REG_HL: opcode = 0x2F; break; 2323 case REG_IX: opcode = (prefix != 0xFD) ? 0x3F : 0x3E; break; 2324 case REG_IY: opcode = (prefix != 0xFD) ? 0x3E : 0x3F; break; 2325 default: 2326 ill_op (); 2327 } 2328 q = frag_more (prefix ? 2 : 1); 2329 *q++ = prefix; 2330 *q = opcode; 2331 if (prefix == 0xFD || prefix == 0xDD) 2332 { 2333 dst_offset = *dst; 2334 dst_offset.X_op = O_symbol; 2335 dst_offset.X_add_number = 0; 2336 emit_byte (& dst_offset, BFD_RELOC_Z80_DISP8); 2337 } 2338 break; 2339 default: /* LD (nn),rr */ 2340 if (ins_ok & INS_GBZ80) 2341 { 2342 /* GBZ80 supports only LD (nn),SP */ 2343 if (src->X_add_number == REG_SP) 2344 { 2345 prefix = 0x00; 2346 opcode = 0x08; 2347 } 2348 else 2349 ill_op (); 2350 } 2351 else 2352 { 2353 switch (src->X_add_number) 2354 { 2355 case REG_BC: prefix = 0xED; opcode = 0x43; break; 2356 case REG_DE: prefix = 0xED; opcode = 0x53; break; 2357 case REG_HL: prefix = 0x00; opcode = 0x22; break; 2358 case REG_IX: prefix = 0xDD; opcode = 0x22; break; 2359 case REG_IY: prefix = 0xFD; opcode = 0x22; break; 2360 case REG_SP: prefix = 0xED; opcode = 0x73; break; 2361 default: 2362 ill_op (); 2363 } 2364 } 2365 q = frag_more (prefix ? 2 : 1); 2366 if (prefix) 2367 *q++ = prefix; 2368 *q = opcode; 2369 emit_word (dst); 2370 } 2371 } 2372 2373 static void 2374 emit_ld_r_m (expressionS *dst, expressionS *src) 2375 { /* for 8-bit memory load to register: LD r,(xxx) */ 2376 char *q; 2377 char prefix = 0; 2378 char opcode = 0; 2379 expressionS src_offset; 2380 2381 if (dst->X_add_number == REG_A && src->X_op == O_register) 2382 { /* LD A,(BC) or LD A,(DE) */ 2383 switch (src->X_add_number) 2384 { 2385 case REG_BC: opcode = 0x0A; break; 2386 case REG_DE: opcode = 0x1A; break; 2387 default: break; 2388 } 2389 if (opcode != 0) 2390 { 2391 q = frag_more (1); 2392 *q = opcode; 2393 return; 2394 } 2395 } 2396 2397 switch (src->X_op) 2398 { 2399 case O_md1: 2400 if (ins_ok & INS_GBZ80) 2401 { /* LD A,(HL+) or LD A,(HL-) */ 2402 if (dst->X_op == O_register && dst->X_add_number == REG_A) 2403 *frag_more (1) = (src->X_add_number == REG_HL) ? 0x2A : 0x3A; 2404 else 2405 ill_op (); 2406 break; 2407 } 2408 /* Fall through. */ 2409 case O_register: 2410 if (dst->X_add_number > 7) 2411 ill_op (); 2412 opcode = 0x46; /* LD B,(HL) */ 2413 switch (src->X_add_number) 2414 { 2415 case REG_HL: prefix = 0x00; break; 2416 case REG_IX: prefix = 0xDD; break; 2417 case REG_IY: prefix = 0xFD; break; 2418 default: 2419 ill_op (); 2420 } 2421 q = frag_more (prefix ? 2 : 1); 2422 if (prefix) 2423 *q++ = prefix; 2424 *q = opcode | ((dst->X_add_number & 7) << 3); 2425 if (prefix) 2426 { 2427 src_offset = *src; 2428 src_offset.X_op = O_symbol; 2429 src_offset.X_add_number = 0; 2430 emit_byte (& src_offset, BFD_RELOC_Z80_DISP8); 2431 } 2432 break; 2433 default: /* LD A,(nn) */ 2434 if (dst->X_add_number == REG_A) 2435 { 2436 q = frag_more (1); 2437 *q = (ins_ok & INS_GBZ80) ? 0xFA : 0x3A; 2438 emit_word (src); 2439 } 2440 else 2441 ill_op (); 2442 } 2443 } 2444 2445 static void 2446 emit_ld_r_n (expressionS *dst, expressionS *src) 2447 { /* for 8-bit immediate value load to register: LD r,n */ 2448 char *q; 2449 char prefix = 0; 2450 2451 switch (dst->X_add_number) 2452 { 2453 case REG_H|R_IX: 2454 case REG_L|R_IX: 2455 prefix = 0xDD; 2456 break; 2457 case REG_H|R_IY: 2458 case REG_L|R_IY: 2459 prefix = 0xFD; 2460 break; 2461 case REG_A: 2462 case REG_B: 2463 case REG_C: 2464 case REG_D: 2465 case REG_E: 2466 case REG_H: 2467 case REG_L: 2468 break; 2469 default: 2470 ill_op (); 2471 } 2472 2473 q = frag_more (prefix ? 2 : 1); 2474 if (prefix) 2475 { 2476 if (ins_ok & INS_GBZ80) 2477 ill_op (); 2478 else if (!(ins_ok & (INS_EZ80|INS_R800|INS_Z80N))) 2479 check_mach (INS_IDX_HALF); 2480 *q++ = prefix; 2481 } 2482 *q = 0x06 | ((dst->X_add_number & 7) << 3); 2483 emit_byte (src, BFD_RELOC_8); 2484 } 2485 2486 static void 2487 emit_ld_r_r (expressionS *dst, expressionS *src) 2488 { /* mostly 8-bit load register from register instructions: LD r,r */ 2489 /* there are some exceptions: LD SP,HL/IX/IY; LD I,HL and LD HL,I */ 2490 char *q; 2491 int prefix = 0; 2492 int opcode = 0; 2493 int ii_halves = 0; 2494 2495 switch (dst->X_add_number) 2496 { 2497 case REG_SP: 2498 switch (src->X_add_number) 2499 { 2500 case REG_HL: prefix = 0x00; break; 2501 case REG_IX: prefix = 0xDD; break; 2502 case REG_IY: prefix = 0xFD; break; 2503 default: 2504 ill_op (); 2505 } 2506 opcode = 0xF9; 2507 break; 2508 case REG_HL: 2509 if (!(ins_ok & INS_EZ80)) 2510 ill_op (); 2511 if (src->X_add_number != REG_I) 2512 ill_op (); 2513 if (cpu_mode < 1) 2514 error (_("ADL mode instruction")); 2515 /* LD HL,I */ 2516 prefix = 0xED; 2517 opcode = 0xD7; 2518 break; 2519 case REG_I: 2520 if (src->X_add_number == REG_HL) 2521 { 2522 if (!(ins_ok & INS_EZ80)) 2523 ill_op (); 2524 if (cpu_mode < 1) 2525 error (_("ADL mode instruction")); 2526 prefix = 0xED; 2527 opcode = 0xC7; 2528 } 2529 else if (src->X_add_number == REG_A) 2530 { 2531 prefix = 0xED; 2532 opcode = 0x47; 2533 } 2534 else 2535 ill_op (); 2536 break; 2537 case REG_MB: 2538 if (!(ins_ok & INS_EZ80) || (src->X_add_number != REG_A)) 2539 ill_op (); 2540 if (cpu_mode < 1) 2541 error (_("ADL mode instruction")); 2542 prefix = 0xED; 2543 opcode = 0x6D; 2544 break; 2545 case REG_R: 2546 if (src->X_add_number == REG_A) /* LD R,A */ 2547 { 2548 prefix = 0xED; 2549 opcode = 0x4F; 2550 } 2551 else 2552 ill_op (); 2553 break; 2554 case REG_A: 2555 if (src->X_add_number == REG_I) /* LD A,I */ 2556 { 2557 prefix = 0xED; 2558 opcode = 0x57; 2559 break; 2560 } 2561 else if (src->X_add_number == REG_R) /* LD A,R */ 2562 { 2563 prefix = 0xED; 2564 opcode = 0x5F; 2565 break; 2566 } 2567 else if (src->X_add_number == REG_MB) /* LD A,MB */ 2568 { 2569 if (!(ins_ok & INS_EZ80)) 2570 ill_op (); 2571 else 2572 { 2573 if (cpu_mode < 1) 2574 error (_("ADL mode instruction")); 2575 prefix = 0xED; 2576 opcode = 0x6E; 2577 } 2578 break; 2579 } 2580 /* Fall through. */ 2581 case REG_B: 2582 case REG_C: 2583 case REG_D: 2584 case REG_E: 2585 case REG_H: 2586 case REG_L: 2587 prefix = 0x00; 2588 break; 2589 case REG_H|R_IX: 2590 case REG_L|R_IX: 2591 prefix = 0xDD; 2592 ii_halves = 1; 2593 break; 2594 case REG_H|R_IY: 2595 case REG_L|R_IY: 2596 prefix = 0xFD; 2597 ii_halves = 1; 2598 break; 2599 default: 2600 ill_op (); 2601 } 2602 2603 if (opcode == 0) 2604 { 2605 switch (src->X_add_number) 2606 { 2607 case REG_A: 2608 case REG_B: 2609 case REG_C: 2610 case REG_D: 2611 case REG_E: 2612 break; 2613 case REG_H: 2614 case REG_L: 2615 if (prefix != 0) 2616 ill_op (); /* LD iiH/L,H/L are not permitted */ 2617 break; 2618 case REG_H|R_IX: 2619 case REG_L|R_IX: 2620 if (prefix == 0xFD || dst->X_add_number == REG_H || dst->X_add_number == REG_L) 2621 ill_op (); /* LD IYL,IXL and LD H,IXH are not permitted */ 2622 prefix = 0xDD; 2623 ii_halves = 1; 2624 break; 2625 case REG_H|R_IY: 2626 case REG_L|R_IY: 2627 if (prefix == 0xDD || dst->X_add_number == REG_H || dst->X_add_number == REG_L) 2628 ill_op (); /* LD IXH,IYH and LD L,IYL are not permitted */ 2629 prefix = 0xFD; 2630 ii_halves = 1; 2631 break; 2632 default: 2633 ill_op (); 2634 } 2635 opcode = 0x40 + ((dst->X_add_number & 7) << 3) + (src->X_add_number & 7); 2636 } 2637 if ((ins_ok & INS_GBZ80) && prefix != 0) 2638 ill_op (); 2639 if (ii_halves && !(ins_ok & (INS_EZ80|INS_R800|INS_Z80N))) 2640 check_mach (INS_IDX_HALF); 2641 if (prefix == 0 && (ins_ok & INS_EZ80)) 2642 { 2643 switch (opcode) 2644 { 2645 case 0x40: /* SIS prefix, in Z80 it is LD B,B */ 2646 case 0x49: /* LIS prefix, in Z80 it is LD C,C */ 2647 case 0x52: /* SIL prefix, in Z80 it is LD D,D */ 2648 case 0x5B: /* LIL prefix, in Z80 it is LD E,E */ 2649 as_warn (_("unsupported instruction, assembled as NOP")); 2650 opcode = 0x00; 2651 break; 2652 default:; 2653 } 2654 } 2655 q = frag_more (prefix ? 2 : 1); 2656 if (prefix) 2657 *q++ = prefix; 2658 *q = opcode; 2659 } 2660 2661 static void 2662 emit_ld_rr_m (expressionS *dst, expressionS *src) 2663 { /* for 16-bit indirect load from memory to register: LD rr,(xxx) */ 2664 char *q; 2665 int prefix = 0; 2666 int opcode = 0; 2667 expressionS src_offset; 2668 2669 /* GBZ80 has no support for 16-bit load from memory instructions */ 2670 if (ins_ok & INS_GBZ80) 2671 ill_op (); 2672 2673 prefix = 0xED; 2674 switch (src->X_op) 2675 { 2676 case O_md1: /* LD rr,(ii+d) */ 2677 prefix = (src->X_add_number == REG_IX) ? 0xDD : 0xFD; 2678 /* Fall through. */ 2679 case O_register: /* LD rr,(HL) */ 2680 /* currently only EZ80 has support for 16bit indirect memory load instructions */ 2681 if (!(ins_ok & INS_EZ80)) 2682 ill_op (); 2683 switch (dst->X_add_number) 2684 { 2685 case REG_BC: opcode = 0x07; break; 2686 case REG_DE: opcode = 0x17; break; 2687 case REG_HL: opcode = 0x27; break; 2688 case REG_IX: opcode = (prefix == 0xED || prefix == 0xDD) ? 0x37 : 0x31; break; 2689 case REG_IY: opcode = (prefix == 0xED || prefix == 0xDD) ? 0x31 : 0x37; break; 2690 default: 2691 ill_op (); 2692 } 2693 q = frag_more (2); 2694 *q++ = prefix; 2695 *q = opcode; 2696 if (prefix != 0xED) 2697 { 2698 src_offset = *src; 2699 src_offset.X_op = O_symbol; 2700 src_offset.X_add_number = 0; 2701 emit_byte (& src_offset, BFD_RELOC_Z80_DISP8); 2702 } 2703 break; 2704 default: /* LD rr,(nn) */ 2705 switch (dst->X_add_number) 2706 { 2707 case REG_BC: prefix = 0xED; opcode = 0x4B; break; 2708 case REG_DE: prefix = 0xED; opcode = 0x5B; break; 2709 case REG_HL: prefix = 0x00; opcode = 0x2A; break; 2710 case REG_SP: prefix = 0xED; opcode = 0x7B; break; 2711 case REG_IX: prefix = 0xDD; opcode = 0x2A; break; 2712 case REG_IY: prefix = 0xFD; opcode = 0x2A; break; 2713 default: 2714 ill_op (); 2715 } 2716 q = frag_more (prefix ? 2 : 1); 2717 if (prefix) 2718 *q++ = prefix; 2719 *q = opcode; 2720 emit_word (src); 2721 } 2722 return; 2723 } 2724 2725 static void 2726 emit_ld_rr_nn (expressionS *dst, expressionS *src) 2727 { /* mostly load imediate value to multibyte register instructions: LD rr,nn */ 2728 char *q; 2729 int prefix = 0x00; 2730 int opcode = 0x21; /* LD HL,nn */ 2731 switch (dst->X_add_number) 2732 { 2733 case REG_IX: 2734 prefix = 0xDD; 2735 break; 2736 case REG_IY: 2737 prefix = 0xFD; 2738 break; 2739 case REG_HL: 2740 break; 2741 case REG_BC: 2742 case REG_DE: 2743 case REG_SP: 2744 opcode = 0x01 + ((dst->X_add_number & 3) << 4); 2745 break; 2746 default: 2747 ill_op (); 2748 return; 2749 } 2750 if (prefix && (ins_ok & INS_GBZ80)) 2751 ill_op (); 2752 q = frag_more (prefix ? 2 : 1); 2753 if (prefix) 2754 *q++ = prefix; 2755 *q = opcode; 2756 emit_word (src); 2757 } 2758 2759 static const char * 2760 emit_ld (char prefix_in ATTRIBUTE_UNUSED, char opcode_in ATTRIBUTE_UNUSED, 2761 const char * args) 2762 { 2763 expressionS dst, src; 2764 const char *p; 2765 2766 p = parse_exp (args, & dst); 2767 if (*p++ != ',') 2768 error (_("bad instruction syntax")); 2769 p = parse_exp (p, & src); 2770 2771 if (dst.X_md) 2772 { 2773 if (src.X_op == O_register) 2774 { 2775 if (src.X_add_number <= 7) 2776 emit_ld_m_r (& dst, & src); /* LD (xxx),r */ 2777 else 2778 emit_ld_m_rr (& dst, & src); /* LD (xxx),rr */ 2779 } 2780 else 2781 emit_ld_m_n (& dst, & src); /* LD (hl),n or LD (ix/y+r),n */ 2782 } 2783 else if (dst.X_op == O_register) 2784 { 2785 if (src.X_md) 2786 { 2787 if (dst.X_add_number <= 7) 2788 emit_ld_r_m (& dst, & src); 2789 else 2790 emit_ld_rr_m (& dst, & src); 2791 } 2792 else if (src.X_op == O_register) 2793 emit_ld_r_r (& dst, & src); 2794 else if ((dst.X_add_number & ~R_INDEX) <= 7) 2795 emit_ld_r_n (& dst, & src); 2796 else 2797 emit_ld_rr_nn (& dst, & src); 2798 } 2799 else 2800 ill_op (); 2801 2802 return p; 2803 } 2804 2805 static const char * 2806 emit_lddldi (char prefix, char opcode, const char * args) 2807 { 2808 expressionS dst, src; 2809 const char *p; 2810 char *q; 2811 2812 if (!(ins_ok & INS_GBZ80)) 2813 return emit_insn (prefix, opcode, args); 2814 2815 p = parse_exp (args, & dst); 2816 if (*p++ != ',') 2817 error (_("bad instruction syntax")); 2818 p = parse_exp (p, & src); 2819 2820 if (dst.X_op != O_register || src.X_op != O_register) 2821 ill_op (); 2822 2823 /* convert opcode 0xA0 . 0x22, 0xA8 . 0x32 */ 2824 opcode = (opcode & 0x08) * 2 + 0x22; 2825 2826 if (dst.X_md != 0 2827 && dst.X_add_number == REG_HL 2828 && src.X_md == 0 2829 && src.X_add_number == REG_A) 2830 opcode |= 0x00; /* LDx (HL),A */ 2831 else if (dst.X_md == 0 2832 && dst.X_add_number == REG_A 2833 && src.X_md != 0 2834 && src.X_add_number == REG_HL) 2835 opcode |= 0x08; /* LDx A,(HL) */ 2836 else 2837 ill_op (); 2838 2839 q = frag_more (1); 2840 *q = opcode; 2841 return p; 2842 } 2843 2844 static const char * 2845 emit_ldh (char prefix ATTRIBUTE_UNUSED, char opcode ATTRIBUTE_UNUSED, 2846 const char * args) 2847 { 2848 expressionS dst, src; 2849 const char *p; 2850 char *q; 2851 2852 p = parse_exp (args, & dst); 2853 if (*p++ != ',') 2854 { 2855 error (_("bad instruction syntax")); 2856 return p; 2857 } 2858 2859 p = parse_exp (p, & src); 2860 if (dst.X_md == 0 2861 && dst.X_op == O_register 2862 && dst.X_add_number == REG_A 2863 && src.X_md != 0 2864 && src.X_op != O_md1) 2865 { 2866 if (src.X_op != O_register) 2867 { 2868 q = frag_more (1); 2869 *q = 0xF0; 2870 emit_byte (& src, BFD_RELOC_8); 2871 } 2872 else if (src.X_add_number == REG_C) 2873 *frag_more (1) = 0xF2; 2874 else 2875 ill_op (); 2876 } 2877 else if (dst.X_md != 0 2878 && dst.X_op != O_md1 2879 && src.X_md == 0 2880 && src.X_op == O_register 2881 && src.X_add_number == REG_A) 2882 { 2883 if (dst.X_op == O_register) 2884 { 2885 if (dst.X_add_number == REG_C) 2886 { 2887 q = frag_more (1); 2888 *q = 0xE2; 2889 } 2890 else 2891 ill_op (); 2892 } 2893 else 2894 { 2895 q = frag_more (1); 2896 *q = 0xE0; 2897 emit_byte (& dst, BFD_RELOC_8); 2898 } 2899 } 2900 else 2901 ill_op (); 2902 2903 return p; 2904 } 2905 2906 static const char * 2907 emit_ldhl (char prefix ATTRIBUTE_UNUSED, char opcode, const char * args) 2908 { 2909 expressionS dst, src; 2910 const char *p; 2911 char *q; 2912 p = parse_exp (args, & dst); 2913 if (*p++ != ',') 2914 { 2915 error (_("bad instruction syntax")); 2916 return p; 2917 } 2918 2919 p = parse_exp (p, & src); 2920 if (dst.X_md || dst.X_op != O_register || dst.X_add_number != REG_SP 2921 || src.X_md || src.X_op == O_register || src.X_op == O_md1) 2922 ill_op (); 2923 q = frag_more (1); 2924 *q = opcode; 2925 emit_byte (& src, BFD_RELOC_Z80_DISP8); 2926 return p; 2927 } 2928 2929 static const char * 2930 parse_lea_pea_args (const char * args, expressionS *op) 2931 { 2932 const char *p; 2933 p = parse_exp (args, op); 2934 if (sdcc_compat && *p == ',' && op->X_op == O_register) 2935 { 2936 expressionS off; 2937 p = parse_exp (p + 1, &off); 2938 op->X_op = O_add; 2939 op->X_add_symbol = make_expr_symbol (&off); 2940 } 2941 return p; 2942 } 2943 2944 static const char * 2945 emit_lea (char prefix, char opcode, const char * args) 2946 { 2947 expressionS dst, src; 2948 const char *p; 2949 char *q; 2950 int rnum; 2951 2952 p = parse_exp (args, & dst); 2953 if (dst.X_md != 0 || dst.X_op != O_register) 2954 ill_op (); 2955 2956 rnum = dst.X_add_number; 2957 switch (rnum) 2958 { 2959 case REG_BC: 2960 case REG_DE: 2961 case REG_HL: 2962 opcode = 0x02 | ((rnum & 0x03) << 4); 2963 break; 2964 case REG_IX: 2965 opcode = 0x32; /* lea ix,ix+d has opcode 0x32; lea ix,iy+d has opcode 0x54 */ 2966 break; 2967 case REG_IY: 2968 opcode = 0x33; /* lea iy,iy+d has opcode 0x33; lea iy,ix+d has opcode 0x55 */ 2969 break; 2970 default: 2971 ill_op (); 2972 } 2973 2974 if (*p++ != ',') 2975 error (_("bad instruction syntax")); 2976 2977 p = parse_lea_pea_args (p, & src); 2978 if (src.X_md != 0 || src.X_op != O_add /*&& src.X_op != O_register*/) 2979 ill_op (); 2980 2981 rnum = src.X_add_number; 2982 switch (src.X_op) 2983 { 2984 case O_add: 2985 break; 2986 case O_register: /* permit instructions like LEA rr,IX without displacement specified */ 2987 src.X_add_symbol = zero; 2988 break; 2989 default: 2990 ill_op (); 2991 } 2992 2993 switch (rnum) 2994 { 2995 case REG_IX: 2996 opcode = opcode == 0x33 ? 0x55 : opcode | 0x00; 2997 break; 2998 case REG_IY: 2999 opcode = opcode == 0x32 ? 0x54 : opcode | 0x01; 3000 } 3001 3002 q = frag_more (2); 3003 *q++ = prefix; 3004 *q = opcode; 3005 3006 src.X_op = O_symbol; 3007 src.X_add_number = 0; 3008 emit_byte (& src, BFD_RELOC_Z80_DISP8); 3009 3010 return p; 3011 } 3012 3013 static const char * 3014 emit_mlt (char prefix, char opcode, const char * args) 3015 { 3016 expressionS arg; 3017 const char *p; 3018 char *q; 3019 3020 p = parse_exp (args, & arg); 3021 if (arg.X_md != 0 || arg.X_op != O_register || !(arg.X_add_number & R_ARITH)) 3022 ill_op (); 3023 3024 q = frag_more (2); 3025 if (ins_ok & INS_Z80N) 3026 { 3027 if (arg.X_add_number != REG_DE) 3028 ill_op (); 3029 *q++ = 0xED; 3030 *q = 0x30; 3031 } 3032 else 3033 { 3034 *q++ = prefix; 3035 *q = opcode | ((arg.X_add_number & 3) << 4); 3036 } 3037 3038 return p; 3039 } 3040 3041 /* MUL D,E (Z80N only) */ 3042 static const char * 3043 emit_mul (char prefix, char opcode, const char * args) 3044 { 3045 expressionS r1, r2; 3046 const char *p; 3047 char *q; 3048 3049 p = parse_exp (args, & r1); 3050 if (*p++ != ',') 3051 error (_("bad instruction syntax")); 3052 p = parse_exp (p, & r2); 3053 3054 if (r1.X_md != 0 || r1.X_op != O_register || r1.X_add_number != REG_D || 3055 r2.X_md != 0 || r2.X_op != O_register || r2.X_add_number != REG_E) 3056 ill_op (); 3057 3058 q = frag_more (2); 3059 *q++ = prefix; 3060 *q = opcode; 3061 3062 return p; 3063 } 3064 3065 static const char * 3066 emit_nextreg (char prefix, char opcode ATTRIBUTE_UNUSED, const char * args) 3067 { 3068 expressionS rr, nn; 3069 const char *p; 3070 char *q; 3071 3072 p = parse_exp (args, & rr); 3073 if (*p++ != ',') 3074 error (_("bad instruction syntax")); 3075 p = parse_exp (p, & nn); 3076 if (rr.X_md != 0 || rr.X_op == O_register || rr.X_op == O_md1 || 3077 nn.X_md != 0 || nn.X_op == O_md1) 3078 ill_op (); 3079 q = frag_more (2); 3080 *q++ = prefix; 3081 emit_byte (&rr, BFD_RELOC_8); 3082 if (nn.X_op == O_register && nn.X_add_number == REG_A) 3083 *q = 0x92; 3084 else if (nn.X_op != O_register) 3085 { 3086 *q = 0x91; 3087 emit_byte (&nn, BFD_RELOC_8); 3088 } 3089 else 3090 ill_op (); 3091 return p; 3092 } 3093 3094 static const char * 3095 emit_pea (char prefix, char opcode, const char * args) 3096 { 3097 expressionS arg; 3098 const char *p; 3099 char *q; 3100 3101 p = parse_lea_pea_args (args, & arg); 3102 if (arg.X_md != 0 3103 || (/*arg.X_op != O_register &&*/ arg.X_op != O_add) 3104 || !(arg.X_add_number & R_INDEX)) 3105 ill_op (); 3106 /* PEA ii without displacement is mostly typo, 3107 because there is PUSH instruction which is shorter and faster */ 3108 /*if (arg.X_op == O_register) 3109 as_warn (_("PEA is used without displacement, use PUSH instead"));*/ 3110 3111 q = frag_more (2); 3112 *q++ = prefix; 3113 *q = opcode + (arg.X_add_number == REG_IY ? 1 : 0); 3114 3115 arg.X_op = O_symbol; 3116 arg.X_add_number = 0; 3117 emit_byte (& arg, BFD_RELOC_Z80_DISP8); 3118 3119 return p; 3120 } 3121 3122 static const char * 3123 emit_reti (char prefix, char opcode, const char * args) 3124 { 3125 if (ins_ok & INS_GBZ80) 3126 return emit_insn (0x00, 0xD9, args); 3127 3128 return emit_insn (prefix, opcode, args); 3129 } 3130 3131 static const char * 3132 emit_tst (char prefix, char opcode, const char *args) 3133 { 3134 expressionS arg_s; 3135 const char *p; 3136 char *q; 3137 int rnum; 3138 3139 p = parse_exp (args, & arg_s); 3140 if (*p == ',' && arg_s.X_md == 0 && arg_s.X_op == O_register && arg_s.X_add_number == REG_A) 3141 { 3142 if (!(ins_ok & INS_EZ80)) 3143 ill_op (); 3144 ++p; 3145 p = parse_exp (p, & arg_s); 3146 } 3147 3148 rnum = arg_s.X_add_number; 3149 switch (arg_s.X_op) 3150 { 3151 case O_md1: 3152 ill_op (); 3153 break; 3154 case O_register: 3155 rnum = arg_s.X_add_number; 3156 if (arg_s.X_md != 0) 3157 { 3158 if (rnum != REG_HL) 3159 ill_op (); 3160 else 3161 rnum = 6; 3162 } 3163 q = frag_more (2); 3164 *q++ = prefix; 3165 *q = opcode | (rnum << 3); 3166 break; 3167 default: 3168 if (arg_s.X_md) 3169 ill_op (); 3170 q = frag_more (2); 3171 if (ins_ok & INS_Z80N) 3172 { 3173 *q++ = 0xED; 3174 *q = 0x27; 3175 } 3176 else 3177 { 3178 *q++ = prefix; 3179 *q = opcode | 0x60; 3180 } 3181 emit_byte (& arg_s, BFD_RELOC_8); 3182 } 3183 return p; 3184 } 3185 3186 static const char * 3187 emit_insn_n (char prefix, char opcode, const char *args) 3188 { 3189 expressionS arg; 3190 const char *p; 3191 char *q; 3192 3193 p = parse_exp (args, & arg); 3194 if (arg.X_md || arg.X_op == O_register || arg.X_op == O_md1) 3195 ill_op (); 3196 3197 q = frag_more (2); 3198 *q++ = prefix; 3199 *q = opcode; 3200 emit_byte (& arg, BFD_RELOC_8); 3201 3202 return p; 3203 } 3204 3205 static void 3206 emit_data (int size ATTRIBUTE_UNUSED) 3207 { 3208 const char *p, *q; 3209 char *u, quote; 3210 int cnt; 3211 expressionS exp; 3212 3213 if (is_it_end_of_statement ()) 3214 { 3215 demand_empty_rest_of_line (); 3216 return; 3217 } 3218 p = skip_space (input_line_pointer); 3219 3220 do 3221 { 3222 if (*p == '\"' || *p == '\'') 3223 { 3224 for (quote = *p, q = ++p, cnt = 0; *p && quote != *p; ++p, ++cnt) 3225 ; 3226 u = frag_more (cnt); 3227 memcpy (u, q, cnt); 3228 if (!*p) 3229 as_warn (_("unterminated string")); 3230 else 3231 p = skip_space (p+1); 3232 } 3233 else 3234 { 3235 p = parse_exp (p, &exp); 3236 if (exp.X_op == O_md1 || exp.X_op == O_register) 3237 { 3238 ill_op (); 3239 break; 3240 } 3241 if (exp.X_md) 3242 as_warn (_("parentheses ignored")); 3243 emit_byte (&exp, BFD_RELOC_8); 3244 p = skip_space (p); 3245 } 3246 } 3247 while (*p++ == ',') ; 3248 input_line_pointer = (char *)(p-1); 3249 } 3250 3251 static void 3252 z80_cons (int size) 3253 { 3254 const char *p; 3255 expressionS exp; 3256 3257 if (is_it_end_of_statement ()) 3258 { 3259 demand_empty_rest_of_line (); 3260 return; 3261 } 3262 p = skip_space (input_line_pointer); 3263 3264 do 3265 { 3266 p = parse_exp (p, &exp); 3267 if (exp.X_op == O_md1 || exp.X_op == O_register) 3268 { 3269 ill_op (); 3270 break; 3271 } 3272 if (exp.X_md) 3273 as_warn (_("parentheses ignored")); 3274 emit_data_val (&exp, size); 3275 p = skip_space (p); 3276 } while (*p++ == ',') ; 3277 input_line_pointer = (char *)(p-1); 3278 } 3279 3280 /* next functions were commented out because it is difficult to mix 3281 both ADL and Z80 mode instructions within one COFF file: 3282 objdump cannot recognize point of mode switching. 3283 */ 3284 static void 3285 set_cpu_mode (int mode) 3286 { 3287 if (ins_ok & INS_EZ80) 3288 cpu_mode = mode; 3289 else 3290 error (_("CPU mode is unsupported by target")); 3291 } 3292 3293 static void 3294 assume (int arg ATTRIBUTE_UNUSED) 3295 { 3296 char *name; 3297 char c; 3298 int n; 3299 3300 input_line_pointer = (char*)skip_space (input_line_pointer); 3301 c = get_symbol_name (& name); 3302 if (strncasecmp (name, "ADL", 4) != 0) 3303 { 3304 ill_op (); 3305 return; 3306 } 3307 3308 restore_line_pointer (c); 3309 input_line_pointer = (char*)skip_space (input_line_pointer); 3310 if (*input_line_pointer++ != '=') 3311 { 3312 error (_("assignment expected")); 3313 return; 3314 } 3315 input_line_pointer = (char*)skip_space (input_line_pointer); 3316 n = get_single_number (); 3317 3318 set_cpu_mode (n); 3319 } 3320 3321 static const char * 3322 emit_mulub (char prefix ATTRIBUTE_UNUSED, char opcode, const char * args) 3323 { 3324 const char *p; 3325 3326 p = skip_space (args); 3327 if (TOLOWER (*p++) != 'a' || *p++ != ',') 3328 ill_op (); 3329 else 3330 { 3331 char *q, reg; 3332 3333 reg = TOLOWER (*p++); 3334 switch (reg) 3335 { 3336 case 'b': 3337 case 'c': 3338 case 'd': 3339 case 'e': 3340 check_mach (INS_R800); 3341 if (!*skip_space (p)) 3342 { 3343 q = frag_more (2); 3344 *q++ = prefix; 3345 *q = opcode + ((reg - 'b') << 3); 3346 break; 3347 } 3348 /* Fall through. */ 3349 default: 3350 ill_op (); 3351 } 3352 } 3353 return p; 3354 } 3355 3356 static const char * 3357 emit_muluw (char prefix ATTRIBUTE_UNUSED, char opcode, const char * args) 3358 { 3359 const char *p; 3360 3361 p = skip_space (args); 3362 if (TOLOWER (*p++) != 'h' || TOLOWER (*p++) != 'l' || *p++ != ',') 3363 ill_op (); 3364 else 3365 { 3366 expressionS reg; 3367 char *q; 3368 3369 p = parse_exp (p, & reg); 3370 3371 if ((!reg.X_md) && reg.X_op == O_register) 3372 switch (reg.X_add_number) 3373 { 3374 case REG_BC: 3375 case REG_SP: 3376 check_mach (INS_R800); 3377 q = frag_more (2); 3378 *q++ = prefix; 3379 *q = opcode + ((reg.X_add_number & 3) << 4); 3380 break; 3381 default: 3382 ill_op (); 3383 } 3384 } 3385 return p; 3386 } 3387 3388 static int 3389 assemble_suffix (const char **suffix) 3390 { 3391 static 3392 const char sf[8][4] = 3393 { 3394 "il", 3395 "is", 3396 "l", 3397 "lil", 3398 "lis", 3399 "s", 3400 "sil", 3401 "sis" 3402 }; 3403 const char *p; 3404 const char (*t)[4]; 3405 char sbuf[4]; 3406 int i; 3407 3408 p = *suffix; 3409 if (*p++ != '.') 3410 return 0; 3411 3412 for (i = 0; (i < 3) && (ISALPHA (*p)); i++) 3413 sbuf[i] = TOLOWER (*p++); 3414 if (*p && !is_whitespace (*p)) 3415 return 0; 3416 *suffix = p; 3417 sbuf[i] = 0; 3418 3419 t = bsearch (sbuf, sf, ARRAY_SIZE (sf), sizeof (sf[0]), (int(*)(const void*, const void*)) strcmp); 3420 if (t == NULL) 3421 return 0; 3422 i = t - sf; 3423 switch (i) 3424 { 3425 case 0: /* IL */ 3426 i = cpu_mode ? 0x5B : 0x52; 3427 break; 3428 case 1: /* IS */ 3429 i = cpu_mode ? 0x49 : 0x40; 3430 break; 3431 case 2: /* L */ 3432 i = cpu_mode ? 0x5B : 0x49; 3433 break; 3434 case 3: /* LIL */ 3435 i = 0x5B; 3436 break; 3437 case 4: /* LIS */ 3438 i = 0x49; 3439 break; 3440 case 5: /* S */ 3441 i = cpu_mode ? 0x52 : 0x40; 3442 break; 3443 case 6: /* SIL */ 3444 i = 0x52; 3445 break; 3446 case 7: /* SIS */ 3447 i = 0x40; 3448 break; 3449 } 3450 *frag_more (1) = i; 3451 switch (i) 3452 { 3453 case 0x40: inst_mode = INST_MODE_FORCED | INST_MODE_S | INST_MODE_IS; break; 3454 case 0x49: inst_mode = INST_MODE_FORCED | INST_MODE_L | INST_MODE_IS; break; 3455 case 0x52: inst_mode = INST_MODE_FORCED | INST_MODE_S | INST_MODE_IL; break; 3456 case 0x5B: inst_mode = INST_MODE_FORCED | INST_MODE_L | INST_MODE_IL; break; 3457 } 3458 return 1; 3459 } 3460 3461 static void 3462 psect (int arg) 3463 { 3464 #if defined(OBJ_ELF) 3465 return obj_elf_section (arg); 3466 #elif defined(OBJ_COFF) 3467 return obj_coff_section (arg); 3468 #else 3469 #error Unknown object format 3470 #endif 3471 } 3472 3473 static void 3474 set_inss (int inss) 3475 { 3476 int old_ins; 3477 3478 if (!sdcc_compat) 3479 as_fatal (_("Invalid directive")); 3480 3481 old_ins = ins_ok; 3482 ins_ok &= INS_MARCH_MASK; 3483 ins_ok |= inss; 3484 if (old_ins != ins_ok) 3485 cpu_mode = 0; 3486 } 3487 3488 static void 3489 ignore (int arg ATTRIBUTE_UNUSED) 3490 { 3491 ignore_rest_of_line (); 3492 } 3493 3494 static void 3495 area (int arg) 3496 { 3497 char *p; 3498 if (!sdcc_compat) 3499 as_fatal (_("Invalid directive")); 3500 for (p = input_line_pointer; *p && *p != '(' && *p != '\n'; p++) 3501 ; 3502 if (*p == '(') 3503 { 3504 *p = '\n'; 3505 psect (arg); 3506 *p++ = '('; 3507 ignore_rest_of_line (); 3508 } 3509 else 3510 psect (arg); 3511 } 3512 3513 /* Port specific pseudo ops. */ 3514 const pseudo_typeS md_pseudo_table[] = 3515 { 3516 { ".area", area, 0}, 3517 { ".assume", assume, 0}, 3518 { ".ez80", set_inss, INS_EZ80}, 3519 { ".gbz80", set_inss, INS_GBZ80}, 3520 { ".module", ignore, 0}, 3521 { ".optsdcc", ignore, 0}, 3522 { ".r800", set_inss, INS_R800}, 3523 { ".set", s_set, 0}, 3524 { ".z180", set_inss, INS_Z180}, 3525 { ".hd64", set_inss, INS_Z180}, 3526 { ".z80", set_inss, INS_Z80}, 3527 { ".z80n", set_inss, INS_Z80N}, 3528 { "db" , emit_data, 1}, 3529 { "d24", z80_cons, 3}, 3530 { "d32", z80_cons, 4}, 3531 { "def24", z80_cons, 3}, 3532 { "def32", z80_cons, 4}, 3533 { "defb", emit_data, 1}, 3534 { "defm", emit_data, 1}, 3535 { "defs", s_space, 1}, /* Synonym for ds on some assemblers. */ 3536 { "defw", z80_cons, 2}, 3537 { "ds", s_space, 1}, /* Fill with bytes rather than words. */ 3538 { "dw", z80_cons, 2}, 3539 { "psect", psect, 0}, /* TODO: Translate attributes. */ 3540 { "set", 0, 0}, /* Real instruction on z80. */ 3541 { "xdef", s_globl, 0}, /* Synonym for .GLOBAL */ 3542 { "xref", s_ignore, 0}, /* Synonym for .EXTERN */ 3543 { NULL, 0, 0 } 3544 } ; 3545 3546 static table_t instab[] = 3547 { 3548 { "adc", 0x88, 0x4A, emit_adc, INS_ALL }, 3549 { "add", 0x80, 0x09, emit_add, INS_ALL }, 3550 { "and", 0x00, 0xA0, emit_s, INS_ALL }, 3551 { "bit", 0xCB, 0x40, emit_bit, INS_ALL }, 3552 { "brlc", 0xED, 0x2C, emit_bshft,INS_Z80N }, 3553 { "bsla", 0xED, 0x28, emit_bshft,INS_Z80N }, 3554 { "bsra", 0xED, 0x29, emit_bshft,INS_Z80N }, 3555 { "bsrf", 0xED, 0x2B, emit_bshft,INS_Z80N }, 3556 { "bsrl", 0xED, 0x2A, emit_bshft,INS_Z80N }, 3557 { "call", 0xCD, 0xC4, emit_jpcc, INS_ALL }, 3558 { "ccf", 0x00, 0x3F, emit_insn, INS_ALL }, 3559 { "cp", 0x00, 0xB8, emit_s, INS_ALL }, 3560 { "cpd", 0xED, 0xA9, emit_insn, INS_NOT_GBZ80 }, 3561 { "cpdr", 0xED, 0xB9, emit_insn, INS_NOT_GBZ80 }, 3562 { "cpi", 0xED, 0xA1, emit_insn, INS_NOT_GBZ80 }, 3563 { "cpir", 0xED, 0xB1, emit_insn, INS_NOT_GBZ80 }, 3564 { "cpl", 0x00, 0x2F, emit_insn, INS_ALL }, 3565 { "daa", 0x00, 0x27, emit_insn, INS_ALL }, 3566 { "dec", 0x0B, 0x05, emit_incdec,INS_ALL }, 3567 { "di", 0x00, 0xF3, emit_insn, INS_ALL }, 3568 { "djnz", 0x00, 0x10, emit_jr, INS_NOT_GBZ80 }, 3569 { "ei", 0x00, 0xFB, emit_insn, INS_ALL }, 3570 { "ex", 0x00, 0x00, emit_ex, INS_NOT_GBZ80 }, 3571 { "exx", 0x00, 0xD9, emit_insn, INS_NOT_GBZ80 }, 3572 { "halt", 0x00, 0x76, emit_insn, INS_ALL }, 3573 { "im", 0xED, 0x46, emit_im, INS_NOT_GBZ80 }, 3574 { "in", 0x00, 0x00, emit_in, INS_NOT_GBZ80 }, 3575 { "in0", 0xED, 0x00, emit_in0, INS_Z180|INS_EZ80 }, 3576 { "inc", 0x03, 0x04, emit_incdec,INS_ALL }, 3577 { "ind", 0xED, 0xAA, emit_insn, INS_NOT_GBZ80 }, 3578 { "ind2", 0xED, 0x8C, emit_insn, INS_EZ80 }, 3579 { "ind2r",0xED, 0x9C, emit_insn, INS_EZ80 }, 3580 { "indm", 0xED, 0x8A, emit_insn, INS_EZ80 }, 3581 { "indmr",0xED, 0x9A, emit_insn, INS_EZ80 }, 3582 { "indr", 0xED, 0xBA, emit_insn, INS_NOT_GBZ80 }, 3583 { "indrx",0xED, 0xCA, emit_insn, INS_EZ80 }, 3584 { "ini", 0xED, 0xA2, emit_insn, INS_NOT_GBZ80 }, 3585 { "ini2", 0xED, 0x84, emit_insn, INS_EZ80 }, 3586 { "ini2r",0xED, 0x94, emit_insn, INS_EZ80 }, 3587 { "inim", 0xED, 0x82, emit_insn, INS_EZ80 }, 3588 { "inimr",0xED, 0x92, emit_insn, INS_EZ80 }, 3589 { "inir", 0xED, 0xB2, emit_insn, INS_NOT_GBZ80 }, 3590 { "inirx",0xED, 0xC2, emit_insn, INS_EZ80 }, 3591 { "jp", 0xC3, 0xC2, emit_jpcc, INS_ALL }, 3592 { "jr", 0x18, 0x20, emit_jrcc, INS_ALL }, 3593 { "ld", 0x00, 0x00, emit_ld, INS_ALL }, 3594 { "ldd", 0xED, 0xA8, emit_lddldi,INS_ALL }, /* GBZ80 has special meaning */ 3595 { "lddr", 0xED, 0xB8, emit_insn, INS_NOT_GBZ80 }, 3596 { "lddrx",0xED, 0xBC, emit_insn, INS_Z80N }, 3597 { "lddx", 0xED, 0xAC, emit_insn, INS_Z80N }, 3598 { "ldh", 0xE0, 0x00, emit_ldh, INS_GBZ80 }, 3599 { "ldhl", 0x00, 0xF8, emit_ldhl, INS_GBZ80 }, 3600 { "ldi", 0xED, 0xA0, emit_lddldi,INS_ALL }, /* GBZ80 has special meaning */ 3601 { "ldir", 0xED, 0xB0, emit_insn, INS_NOT_GBZ80 }, 3602 { "ldirx",0xED, 0xB4, emit_insn, INS_Z80N }, 3603 { "ldix", 0xED, 0xA4, emit_insn, INS_Z80N }, 3604 { "ldpirx",0xED,0xB7, emit_insn, INS_Z80N }, 3605 { "ldws", 0xED, 0xA5, emit_insn, INS_Z80N }, 3606 { "lea", 0xED, 0x02, emit_lea, INS_EZ80 }, 3607 { "mirror",0xED,0x24, emit_insn, INS_Z80N }, 3608 { "mlt", 0xED, 0x4C, emit_mlt, INS_Z180|INS_EZ80|INS_Z80N }, 3609 { "mul", 0xED, 0x30, emit_mul, INS_Z80N }, 3610 { "mulub",0xED, 0xC5, emit_mulub,INS_R800 }, 3611 { "muluw",0xED, 0xC3, emit_muluw,INS_R800 }, 3612 { "neg", 0xED, 0x44, emit_insn, INS_NOT_GBZ80 }, 3613 { "nextreg",0xED,0x91,emit_nextreg,INS_Z80N }, 3614 { "nop", 0x00, 0x00, emit_insn, INS_ALL }, 3615 { "or", 0x00, 0xB0, emit_s, INS_ALL }, 3616 { "otd2r",0xED, 0xBC, emit_insn, INS_EZ80 }, 3617 { "otdm", 0xED, 0x8B, emit_insn, INS_Z180|INS_EZ80 }, 3618 { "otdmr",0xED, 0x9B, emit_insn, INS_Z180|INS_EZ80 }, 3619 { "otdr", 0xED, 0xBB, emit_insn, INS_NOT_GBZ80 }, 3620 { "otdrx",0xED, 0xCB, emit_insn, INS_EZ80 }, 3621 { "oti2r",0xED, 0xB4, emit_insn, INS_EZ80 }, 3622 { "otim", 0xED, 0x83, emit_insn, INS_Z180|INS_EZ80 }, 3623 { "otimr",0xED, 0x93, emit_insn, INS_Z180|INS_EZ80 }, 3624 { "otir", 0xED, 0xB3, emit_insn, INS_NOT_GBZ80 }, 3625 { "otirx",0xED, 0xC3, emit_insn, INS_EZ80 }, 3626 { "out", 0x00, 0x00, emit_out, INS_NOT_GBZ80 }, 3627 { "out0", 0xED, 0x01, emit_out0, INS_Z180|INS_EZ80 }, 3628 { "outd", 0xED, 0xAB, emit_insn, INS_NOT_GBZ80 }, 3629 { "outd2",0xED, 0xAC, emit_insn, INS_EZ80 }, 3630 { "outi", 0xED, 0xA3, emit_insn, INS_NOT_GBZ80 }, 3631 { "outi2",0xED, 0xA4, emit_insn, INS_EZ80 }, 3632 { "outinb",0xED,0x90, emit_insn, INS_Z80N }, 3633 { "pea", 0xED, 0x65, emit_pea, INS_EZ80 }, 3634 { "pixelad",0xED,0x94,emit_insn, INS_Z80N }, 3635 { "pixeldn",0xED,0x93,emit_insn, INS_Z80N }, 3636 { "pop", 0x00, 0xC1, emit_pop, INS_ALL }, 3637 { "push", 0x00, 0xC5, emit_push, INS_ALL }, 3638 { "res", 0xCB, 0x80, emit_bit, INS_ALL }, 3639 { "ret", 0xC9, 0xC0, emit_retcc,INS_ALL }, 3640 { "reti", 0xED, 0x4D, emit_reti, INS_ALL }, /*GBZ80 has its own opcode for it*/ 3641 { "retn", 0xED, 0x45, emit_insn, INS_NOT_GBZ80 }, 3642 { "rl", 0xCB, 0x10, emit_mr, INS_ALL }, 3643 { "rla", 0x00, 0x17, emit_insn, INS_ALL }, 3644 { "rlc", 0xCB, 0x00, emit_mr, INS_ALL }, 3645 { "rlca", 0x00, 0x07, emit_insn, INS_ALL }, 3646 { "rld", 0xED, 0x6F, emit_insn, INS_NOT_GBZ80 }, 3647 { "rr", 0xCB, 0x18, emit_mr, INS_ALL }, 3648 { "rra", 0x00, 0x1F, emit_insn, INS_ALL }, 3649 { "rrc", 0xCB, 0x08, emit_mr, INS_ALL }, 3650 { "rrca", 0x00, 0x0F, emit_insn, INS_ALL }, 3651 { "rrd", 0xED, 0x67, emit_insn, INS_NOT_GBZ80 }, 3652 { "rsmix",0xED, 0x7E, emit_insn, INS_EZ80 }, 3653 { "rst", 0x00, 0xC7, emit_rst, INS_ALL }, 3654 { "sbc", 0x98, 0x42, emit_adc, INS_ALL }, 3655 { "scf", 0x00, 0x37, emit_insn, INS_ALL }, 3656 { "set", 0xCB, 0xC0, emit_bit, INS_ALL }, 3657 { "setae",0xED, 0x95, emit_insn, INS_Z80N }, 3658 { "sl1", 0xCB, 0x30, emit_mr, INS_SLI|INS_Z80N }, 3659 { "sla", 0xCB, 0x20, emit_mr, INS_ALL }, 3660 { "sli", 0xCB, 0x30, emit_mr, INS_SLI|INS_Z80N }, 3661 { "sll", 0xCB, 0x30, emit_mr, INS_SLI|INS_Z80N }, 3662 { "slp", 0xED, 0x76, emit_insn, INS_Z180|INS_EZ80 }, 3663 { "sra", 0xCB, 0x28, emit_mr, INS_ALL }, 3664 { "srl", 0xCB, 0x38, emit_mr, INS_ALL }, 3665 { "stmix",0xED, 0x7D, emit_insn, INS_EZ80 }, 3666 { "stop", 0x00, 0x10, emit_insn, INS_GBZ80 }, 3667 { "sub", 0x00, 0x90, emit_sub, INS_ALL }, 3668 { "swap", 0xCB, 0x30, emit_swap, INS_GBZ80|INS_Z80N }, 3669 { "swapnib",0xED,0x23,emit_insn, INS_Z80N }, 3670 { "test", 0xED, 0x27, emit_insn_n, INS_Z80N }, 3671 { "tst", 0xED, 0x04, emit_tst, INS_Z180|INS_EZ80|INS_Z80N }, 3672 { "tstio",0xED, 0x74, emit_insn_n,INS_Z180|INS_EZ80 }, 3673 { "xor", 0x00, 0xA8, emit_s, INS_ALL }, 3674 } ; 3675 3676 void 3677 md_assemble (char *str) 3678 { 3679 const char *p; 3680 char * old_ptr; 3681 int i; 3682 table_t *insp; 3683 3684 err_flag = 0; 3685 inst_mode = cpu_mode ? (INST_MODE_L | INST_MODE_IL) : (INST_MODE_S | INST_MODE_IS); 3686 old_ptr = input_line_pointer; 3687 p = skip_space (str); 3688 for (i = 0; (i < BUFLEN) && (ISALPHA (*p) || ISDIGIT (*p));) 3689 buf[i++] = TOLOWER (*p++); 3690 3691 if (i == BUFLEN) 3692 { 3693 buf[BUFLEN-3] = buf[BUFLEN-2] = '.'; /* Mark opcode as abbreviated. */ 3694 buf[BUFLEN-1] = 0; 3695 as_bad (_("Unknown instruction '%s'"), buf); 3696 } 3697 else 3698 { 3699 dwarf2_emit_insn (0); 3700 if ((*p) && !is_whitespace (*p)) 3701 { 3702 if (*p != '.' || !(ins_ok & INS_EZ80) || !assemble_suffix (&p)) 3703 { 3704 as_bad (_("syntax error")); 3705 goto end; 3706 } 3707 } 3708 buf[i] = 0; 3709 p = skip_space (p); 3710 key = buf; 3711 3712 insp = bsearch (&key, instab, ARRAY_SIZE (instab), 3713 sizeof (instab[0]), key_cmp); 3714 if (!insp || (insp->inss && !(insp->inss & ins_ok))) 3715 { 3716 *frag_more (1) = 0; 3717 as_bad (_("Unknown instruction `%s'"), buf); 3718 } 3719 else 3720 { 3721 p = insp->fp (insp->prefix, insp->opcode, p); 3722 p = skip_space (p); 3723 if ((!err_flag) && *p) 3724 as_bad (_("junk at end of line, " 3725 "first unrecognized character is `%c'"), *p); 3726 } 3727 } 3728 end: 3729 input_line_pointer = old_ptr; 3730 } 3731 3732 static int 3733 signed_overflow (signed long value, unsigned bitsize) 3734 { 3735 signed long max = (signed long) ((1UL << (bitsize - 1)) - 1); 3736 return value < -max - 1 || value > max; 3737 } 3738 3739 static int 3740 unsigned_overflow (unsigned long value, unsigned bitsize) 3741 { 3742 return value >> (bitsize - 1) >> 1 != 0; 3743 } 3744 3745 static int 3746 is_overflow (long value, unsigned bitsize) 3747 { 3748 if (value < 0) 3749 return signed_overflow (value, bitsize); 3750 return unsigned_overflow (value, bitsize); 3751 } 3752 3753 void 3754 md_apply_fix (fixS * fixP, valueT* valP, segT seg) 3755 { 3756 long val = *valP; 3757 char *p_lit = fixP->fx_where + fixP->fx_frag->fr_literal; 3758 3759 if (fixP->fx_addsy == NULL) 3760 fixP->fx_done = 1; 3761 else if (fixP->fx_pcrel) 3762 { 3763 segT s = S_GET_SEGMENT (fixP->fx_addsy); 3764 if (s == seg || s == absolute_section) 3765 { 3766 val += S_GET_VALUE (fixP->fx_addsy); 3767 fixP->fx_done = 1; 3768 } 3769 } 3770 3771 switch (fixP->fx_r_type) 3772 { 3773 case BFD_RELOC_8_PCREL: 3774 case BFD_RELOC_Z80_DISP8: 3775 case BFD_RELOC_8: 3776 case BFD_RELOC_16: 3777 case BFD_RELOC_24: 3778 case BFD_RELOC_32: 3779 case BFD_RELOC_Z80_16_BE: 3780 fixP->fx_no_overflow = 0; 3781 break; 3782 default: 3783 fixP->fx_no_overflow = 1; 3784 break; 3785 } 3786 3787 switch (fixP->fx_r_type) 3788 { 3789 case BFD_RELOC_8_PCREL: 3790 case BFD_RELOC_Z80_DISP8: 3791 if (fixP->fx_done && signed_overflow (val, 8)) 3792 as_bad_where (fixP->fx_file, fixP->fx_line, 3793 _("8-bit signed offset out of range (%+ld)"), val); 3794 *p_lit++ = val; 3795 break; 3796 3797 case BFD_RELOC_Z80_BYTE0: 3798 *p_lit++ = val; 3799 break; 3800 3801 case BFD_RELOC_Z80_BYTE1: 3802 *p_lit++ = (val >> 8); 3803 break; 3804 3805 case BFD_RELOC_Z80_BYTE2: 3806 *p_lit++ = (val >> 16); 3807 break; 3808 3809 case BFD_RELOC_Z80_BYTE3: 3810 *p_lit++ = (val >> 24); 3811 break; 3812 3813 case BFD_RELOC_8: 3814 if (fixP->fx_done && is_overflow(val, 8)) 3815 as_warn_where (fixP->fx_file, fixP->fx_line, 3816 _("8-bit overflow (%+ld)"), val); 3817 *p_lit++ = val; 3818 break; 3819 3820 case BFD_RELOC_Z80_WORD1: 3821 *p_lit++ = (val >> 16); 3822 *p_lit++ = (val >> 24); 3823 break; 3824 3825 case BFD_RELOC_Z80_WORD0: 3826 *p_lit++ = val; 3827 *p_lit++ = (val >> 8); 3828 break; 3829 3830 case BFD_RELOC_16: 3831 if (fixP->fx_done && is_overflow(val, 16)) 3832 as_warn_where (fixP->fx_file, fixP->fx_line, 3833 _("16-bit overflow (%+ld)"), val); 3834 *p_lit++ = val; 3835 *p_lit++ = (val >> 8); 3836 break; 3837 3838 case BFD_RELOC_24: /* Def24 may produce this. */ 3839 if (fixP->fx_done && is_overflow(val, 24)) 3840 as_warn_where (fixP->fx_file, fixP->fx_line, 3841 _("24-bit overflow (%+ld)"), val); 3842 *p_lit++ = val; 3843 *p_lit++ = (val >> 8); 3844 *p_lit++ = (val >> 16); 3845 break; 3846 3847 case BFD_RELOC_32: /* Def32 and .long may produce this. */ 3848 if (fixP->fx_done && is_overflow(val, 32)) 3849 as_warn_where (fixP->fx_file, fixP->fx_line, 3850 _("32-bit overflow (%+ld)"), val); 3851 *p_lit++ = val; 3852 *p_lit++ = (val >> 8); 3853 *p_lit++ = (val >> 16); 3854 *p_lit++ = (val >> 24); 3855 break; 3856 3857 case BFD_RELOC_Z80_16_BE: /* Z80N PUSH nn instruction produce this. */ 3858 *p_lit++ = val >> 8; 3859 *p_lit++ = val; 3860 break; 3861 3862 default: 3863 printf (_("md_apply_fix: unknown reloc type 0x%x\n"), fixP->fx_r_type); 3864 abort (); 3865 } 3866 } 3867 3868 /* GAS will call this to generate a reloc. GAS will pass the 3869 resulting reloc to `bfd_install_relocation'. This currently works 3870 poorly, as `bfd_install_relocation' often does the wrong thing, and 3871 instances of `tc_gen_reloc' have been written to work around the 3872 problems, which in turns makes it difficult to fix 3873 `bfd_install_relocation'. */ 3874 3875 /* If while processing a fixup, a reloc really 3876 needs to be created then it is done here. */ 3877 3878 arelent * 3879 tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED , fixS *fixp) 3880 { 3881 arelent *reloc; 3882 3883 if (fixp->fx_subsy != NULL) 3884 { 3885 as_bad_subtract (fixp); 3886 return NULL; 3887 } 3888 3889 reloc = notes_alloc (sizeof (arelent)); 3890 reloc->sym_ptr_ptr = notes_alloc (sizeof (asymbol *)); 3891 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 3892 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 3893 reloc->addend = fixp->fx_offset; 3894 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); 3895 if (reloc->howto == NULL) 3896 { 3897 as_bad_where (fixp->fx_file, fixp->fx_line, 3898 _("reloc %d not supported by object file format"), 3899 (int) fixp->fx_r_type); 3900 return NULL; 3901 } 3902 3903 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT 3904 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 3905 reloc->address = fixp->fx_offset; 3906 3907 return reloc; 3908 } 3909 3910 int 3911 z80_tc_labels_without_colon (void) 3912 { 3913 return colonless_labels; 3914 } 3915 3916 int 3917 z80_tc_label_is_local (const char *name) 3918 { 3919 const char *n; 3920 const char *p; 3921 if (local_label_prefix == NULL) 3922 return 0; 3923 for (p = local_label_prefix, n = name; *p && *n && *n == *p; p++, n++) 3924 ; 3925 return *p == '\0'; 3926 } 3927 3928 /* Parse floating point number from string and compute mantissa and 3929 exponent. Mantissa is normalized. 3930 */ 3931 #define EXP_MIN -0x10000 3932 #define EXP_MAX 0x10000 3933 static int 3934 str_to_broken_float (bool *signP, uint64_t *mantissaP, int *expP) 3935 { 3936 char *p; 3937 bool sign; 3938 uint64_t mantissa = 0; 3939 int exponent = 0; 3940 int i; 3941 3942 p = (char*)skip_space (input_line_pointer); 3943 sign = (*p == '-'); 3944 *signP = sign; 3945 if (sign || *p == '+') 3946 ++p; 3947 if (strncasecmp (p, "NaN", 3) == 0) 3948 { 3949 *mantissaP = 0; 3950 *expP = 0; 3951 input_line_pointer = p + 3; 3952 return 1; 3953 } 3954 if (strncasecmp (p, "inf", 3) == 0) 3955 { 3956 *mantissaP = 1ull << 63; 3957 *expP = EXP_MAX; 3958 input_line_pointer = p + 3; 3959 return 1; 3960 } 3961 for (; ISDIGIT (*p); ++p) 3962 { 3963 if (mantissa >> 60) 3964 { 3965 if (*p >= '5') 3966 mantissa++; 3967 break; 3968 } 3969 mantissa = mantissa * 10 + (*p - '0'); 3970 } 3971 /* skip non-significant digits */ 3972 for (; ISDIGIT (*p); ++p) 3973 exponent++; 3974 3975 if (*p == '.') 3976 { 3977 p++; 3978 if (!exponent) /* If no precision overflow. */ 3979 { 3980 for (; ISDIGIT (*p); ++p, --exponent) 3981 { 3982 if (mantissa >> 60) 3983 { 3984 if (*p >= '5') 3985 mantissa++; 3986 break; 3987 } 3988 mantissa = mantissa * 10 + (*p - '0'); 3989 } 3990 } 3991 for (; ISDIGIT (*p); ++p) 3992 ; 3993 } 3994 if (*p == 'e' || *p == 'E') 3995 { 3996 int es; 3997 int t = 0; 3998 ++p; 3999 es = (*p == '-'); 4000 if (es || *p == '+') 4001 p++; 4002 for (; ISDIGIT (*p); ++p) 4003 { 4004 if (t < 100) 4005 t = t * 10 + (*p - '0'); 4006 } 4007 exponent += (es) ? -t : t; 4008 } 4009 if (ISALNUM (*p) || *p == '.') 4010 return 0; 4011 input_line_pointer = p; 4012 if (mantissa == 0) 4013 { 4014 *mantissaP = 1ull << 63; 4015 *expP = EXP_MIN; 4016 return 1; /* result is 0 */ 4017 } 4018 /* normalization */ 4019 for (; mantissa <= ~0ull/10; --exponent) 4020 mantissa *= 10; 4021 /* Now we have sign, mantissa, and signed decimal exponent 4022 need to recompute to binary exponent. */ 4023 for (i = 64; exponent > 0; --exponent) 4024 { 4025 /* be sure that no integer overflow */ 4026 while (mantissa > ~0ull/10) 4027 { 4028 mantissa >>= 1; 4029 i += 1; 4030 } 4031 mantissa *= 10; 4032 } 4033 for (; exponent < 0; ++exponent) 4034 { 4035 while (!(mantissa >> 63)) 4036 { 4037 mantissa <<= 1; 4038 i -= 1; 4039 } 4040 mantissa /= 10; 4041 } 4042 /* normalization */ 4043 for (; !(mantissa >> 63); --i) 4044 mantissa <<= 1; 4045 *mantissaP = mantissa; 4046 *expP = i; 4047 return 1; 4048 } 4049 4050 static const char * 4051 str_to_zeda32(char *litP, int *sizeP) 4052 { 4053 uint64_t mantissa; 4054 bool sign; 4055 int exponent; 4056 unsigned i; 4057 4058 *sizeP = 4; 4059 if (!str_to_broken_float (&sign, &mantissa, &exponent)) 4060 return _("invalid syntax"); 4061 /* I do not know why decrement is needed */ 4062 --exponent; 4063 /* shift by 39 bits right keeping 25 bit mantissa for rounding */ 4064 mantissa >>= 39; 4065 /* do rounding */ 4066 ++mantissa; 4067 /* make 24 bit mantissa */ 4068 mantissa >>= 1; 4069 /* check for overflow */ 4070 if (mantissa >> 24) 4071 { 4072 mantissa >>= 1; 4073 ++exponent; 4074 } 4075 /* check for 0 */ 4076 if (exponent < -127) 4077 { 4078 exponent = -128; 4079 mantissa = 0; 4080 } 4081 else if (exponent > 127) 4082 { 4083 exponent = -128; 4084 mantissa = sign ? 0xc00000 : 0x400000; 4085 } 4086 else if (mantissa == 0) 4087 { 4088 exponent = -128; 4089 mantissa = 0x200000; 4090 } 4091 else if (!sign) 4092 mantissa &= (1ull << 23) - 1; 4093 for (i = 0; i < 24; i += 8) 4094 *litP++ = mantissa >> i; 4095 *litP = 0x80 + exponent; 4096 return NULL; 4097 } 4098 4099 /* 4100 Math48 by Anders Hejlsberg support. 4101 Mantissa is 39 bits wide, exponent 8 bit wide. 4102 Format is: 4103 bit 47: sign 4104 bit 46-8: normalized mantissa (bits 38-0, bit39 assumed to be 1) 4105 bit 7-0: exponent+128 (0 - value is null) 4106 MIN: 2.938735877e-39 4107 MAX: 1.701411835e+38 4108 */ 4109 static const char * 4110 str_to_float48(char *litP, int *sizeP) 4111 { 4112 uint64_t mantissa; 4113 bool sign; 4114 int exponent; 4115 unsigned i; 4116 4117 *sizeP = 6; 4118 if (!str_to_broken_float (&sign, &mantissa, &exponent)) 4119 return _("invalid syntax"); 4120 /* shift by 23 bits right keeping 41 bit mantissa for rounding */ 4121 mantissa >>= 23; 4122 /* do rounding */ 4123 ++mantissa; 4124 /* make 40 bit mantissa */ 4125 mantissa >>= 1; 4126 /* check for overflow */ 4127 if (mantissa >> 40) 4128 { 4129 mantissa >>= 1; 4130 ++exponent; 4131 } 4132 if (exponent < -127) 4133 { 4134 memset (litP, 0, 6); 4135 return NULL; 4136 } 4137 if (exponent > 127) 4138 return _("overflow"); 4139 if (!sign) 4140 mantissa &= (1ull << 39) - 1; 4141 *litP++ = 0x80 + exponent; 4142 for (i = 0; i < 40; i += 8) 4143 *litP++ = mantissa >> i; 4144 return NULL; 4145 } 4146 4147 static const char * 4148 str_to_ieee754_h(char *litP, int *sizeP) 4149 { 4150 return ieee_md_atof ('h', litP, sizeP, false); 4151 } 4152 4153 static const char * 4154 str_to_ieee754_s(char *litP, int *sizeP) 4155 { 4156 return ieee_md_atof ('s', litP, sizeP, false); 4157 } 4158 4159 static const char * 4160 str_to_ieee754_d(char *litP, int *sizeP) 4161 { 4162 return ieee_md_atof ('d', litP, sizeP, false); 4163 } 4164 4165 #ifdef TARGET_USE_CFIPOP 4166 /* Initialize the DWARF-2 unwind information for this procedure. */ 4167 void 4168 z80_tc_frame_initial_instructions (void) 4169 { 4170 static int sp_regno = -1; 4171 4172 if (sp_regno < 0) 4173 sp_regno = z80_tc_regname_to_dw2regnum ("sp"); 4174 4175 cfi_add_CFA_def_cfa (sp_regno, 0); 4176 } 4177 4178 int 4179 z80_tc_regname_to_dw2regnum (const char *regname) 4180 { 4181 static const char *regs[] = 4182 { /* same registers as for GDB */ 4183 "af", "bc", "de", "hl", 4184 "sp", "pc", "ix", "iy", 4185 "af_", "bc_", "de_", "hl_", 4186 "ir" 4187 }; 4188 unsigned i; 4189 4190 for (i = 0; i < ARRAY_SIZE(regs); ++i) 4191 if (!strcasecmp (regs[i], regname)) 4192 return i; 4193 4194 return -1; 4195 } 4196 #endif 4197 4198 /* Implement DWARF2_ADDR_SIZE. */ 4199 int 4200 z80_dwarf2_addr_size (const bfd *abfd) 4201 { 4202 switch (bfd_get_mach (abfd)) 4203 { 4204 case bfd_mach_ez80_adl: 4205 return 3; 4206 default: 4207 return 2; 4208 } 4209 } 4210
Indexes created Tue May 05 00:25:04 UTC 2026