nds32.h revision 1.5
1 /* nds32.h -- Header file for nds32 opcode table 2 Copyright (C) 2012-2020 Free Software Foundation, Inc. 3 Contributed by Andes Technology Corporation. 4 5 This program is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 3, or (at your option) 8 any later version. 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public License 16 along with this program; if not, write to the Free Software 17 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 18 02110-1301, USA. */ 19 20 #ifndef OPCODE_NDS32_H 21 #define OPCODE_NDS32_H 22 23 /* Registers. */ 24 #define REG_R0 (0) 25 #define REG_R5 (5) 26 #define REG_R8 (8) 27 #define REG_R10 (10) 28 #define REG_R12 (12) 29 #define REG_R15 (15) 30 #define REG_R16 (16) 31 #define REG_R20 (20) 32 #define REG_TA (15) 33 #define REG_TP (25) 34 #define REG_FP (28) 35 #define REG_GP (29) 36 #define REG_LP (30) 37 #define REG_SP (31) 38 39 /* Macros for extracting fields or making an instruction. */ 41 static const int nds32_r45map[] ATTRIBUTE_UNUSED = 42 { 43 0, 1, 2, 3, 4, 5, 6, 7, 44 8, 9, 10, 11, 16, 17, 18, 19 45 }; 46 47 static const int nds32_r54map[] ATTRIBUTE_UNUSED = 48 { 49 0, 1, 2, 3, 4, 5, 6, 7, 50 8, 9, 10, 11, -1, -1, -1, -1, 51 12, 13, 14, 15, -1, -1, -1, -1, 52 -1, -1, -1, -1, -1, -1, -1, -1 53 }; 54 55 #define N32_BIT(n) (1u << (n)) 56 #define __MASK(n) (N32_BIT (n) - 1) 57 #define __MF(v, off, bs) (((v) & __MASK (bs)) << (off)) 58 #define __GF(v, off, bs) (((v) >> off) & __MASK (bs)) 59 #define __SEXT(v, bs) \ 60 ((((v) & __MASK ((bs))) ^ N32_BIT ((bs) - 1)) - N32_BIT ((bs) - 1)) 61 62 /* Make nds32 instructions. */ 63 64 #define N32_TYPE4(op6, rt5, ra5, rb5, rd5, sub5) \ 65 (__MF (N32_OP6_##op6, 25, 6) | __MF (rt5, 20, 5) \ 66 | __MF (ra5, 15, 5) | __MF (rb5, 10, 5) \ 67 | __MF (rd5, 5, 5) | __MF (sub5, 0, 5)) 68 #define N32_TYPE3(op6, rt5, ra5, rb5, sub10) \ 69 (N32_TYPE4 (op6, rt5, ra5, rb5, 0, 0) \ 70 | __MF (sub10, 0, 10)) 71 #define N32_TYPE2(op6, rt5, ra5, imm15) \ 72 (N32_TYPE3 (op6, rt5, ra5, 0, 0) | __MF (imm15, 0, 15)) 73 #define N32_TYPE1(op6, rt5, imm20) \ 74 (N32_TYPE2 (op6, rt5, 0, 0) | __MF (imm20, 0, 20)) 75 #define N32_TYPE0(op6, imm25) \ 76 (N32_TYPE1 (op6, 0, 0) | __MF (imm25, 0, 25)) 77 #define N32_ALU1(sub, rt, ra, rb) \ 78 N32_TYPE4 (ALU1, rt, ra, rb, 0, N32_ALU1_##sub) 79 #define N32_ALU1_SH(sub, rt, ra, rb, rd) \ 80 N32_TYPE4 (ALU1, rt, ra, rb, rd, N32_ALU1_##sub) 81 #define N32_ALU2(sub, rt, ra, rb) \ 82 N32_TYPE3 (ALU2, rt, ra, rb, N32_ALU2_##sub) 83 #define N32_BR1(sub, rt, ra, imm14s) \ 84 N32_TYPE2 (BR1, rt, ra, (N32_BR1_##sub << 14) | (imm14s & __MASK (14))) 85 #define N32_BR2(sub, rt, imm16s) \ 86 N32_TYPE1 (BR2, rt, (N32_BR2_##sub << 16) | (imm16s & __MASK (16))) 87 #define N32_BR3(sub, rt, imm11s, imm8s) \ 88 N32_TYPE1 (BR3, rt, (N32_BR3_##sub << 19) \ 89 | ((imm11s & __MASK (11)) << 8) \ 90 | (imm8s & __MASK (8))) 91 #define N32_JI(sub, imm24s) \ 92 N32_TYPE0 (JI, (N32_JI_##sub << 24) | (imm24s & __MASK (24))) 93 #define N32_JREG(sub, rt, rb, dtit, hint) \ 94 N32_TYPE4(JREG, rt, 0, rb, (dtit << 3) | (hint & 7), N32_JREG_##sub) 95 #define N32_MEM(sub, rt, ra, rb, sv) \ 96 N32_TYPE3 (MEM, rt, ra, rb, (sv << 8) | N32_MEM_##sub) 97 98 #define N16_TYPE55(op5, rt5, ra5) \ 99 (0x8000 | __MF (N16_T55_##op5, 10, 5) | __MF (rt5, 5, 5) \ 100 | __MF (ra5, 0, 5)) 101 #define N16_TYPE45(op6, rt4, ra5) \ 102 (0x8000 | __MF (N16_T45_##op6, 9, 6) | __MF (rt4, 5, 4) \ 103 | __MF (ra5, 0, 5)) 104 #define N16_TYPE333(op6, rt3, ra3, rb3) \ 105 (0x8000 | __MF (N16_T333_##op6, 9, 6) | __MF (rt3, 6, 3) \ 106 | __MF (ra3, 3, 3) | __MF (rb3, 0, 3)) 107 #define N16_TYPE36(op6, rt3, imm6) \ 108 (0x8000 | __MF (N16_T36_##op6, 9, 6) | __MF (rt3, 6, 3) \ 109 | __MF (imm6, 0, 6)) 110 #define N16_TYPE38(op4, rt3, imm8) \ 111 (0x8000 | __MF (N16_T38_##op4, 11, 4) | __MF (rt3, 8, 3) \ 112 | __MF (imm8, 0, 8)) 113 #define N16_TYPE37(op4, rt3, ls, imm7) \ 114 (0x8000 | __MF (N16_T37_##op4, 11, 4) | __MF (rt3, 8, 3) \ 115 | __MF (imm7, 0, 7) | __MF (ls, 7, 1)) 116 #define N16_TYPE5(op10, imm5) \ 117 (0x8000 | __MF (N16_T5_##op10, 5, 10) | __MF (imm5, 0, 5)) 118 #define N16_TYPE8(op7, imm8) \ 119 (0x8000 | __MF (N16_T8_##op7, 8, 7) | __MF (imm8, 0, 8)) 120 #define N16_TYPE9(op6, imm9) \ 121 (0x8000 | __MF (N16_T9_##op6, 9, 6) | __MF (imm9, 0, 9)) 122 #define N16_TYPE10(op5, imm10) \ 123 (0x8000 | __MF (N16_T10_##op5, 10, 5) | __MF (imm10, 0, 10)) 124 #define N16_TYPE25(op8, re, imm5) \ 125 (0x8000 | __MF (N16_T25_##op8, 7, 8) | __MF (re, 5, 2) \ 126 | __MF (imm5, 0, 5)) 127 128 #define N16_MISC33(sub, rt, ra) \ 129 N16_TYPE333 (MISC33, rt, ra, N16_MISC33_##sub) 130 #define N16_BFMI333(sub, rt, ra) \ 131 N16_TYPE333 (BFMI333, rt, ra, N16_BFMI333_##sub) 132 133 /* Get instruction fields. 134 135 Macros used for handling 32-bit and 16-bit instructions are 136 prefixed with N32_ and N16_ respectively. */ 137 138 #define N32_OP6(insn) (((insn) >> 25) & 0x3f) 139 #define N32_RT5(insn) (((insn) >> 20) & 0x1f) 140 #define N32_RT53(insn) (N32_RT5 (insn) & 0x7) 141 #define N32_RT54(insn) nds32_r54map[N32_RT5 (insn)] 142 #define N32_RA5(insn) (((insn) >> 15) & 0x1f) 143 #define N32_RA53(insn) (N32_RA5 (insn) & 0x7) 144 #define N32_RA54(insn) nds32_r54map[N32_RA5 (insn)] 145 #define N32_RB5(insn) (((insn) >> 10) & 0x1f) 146 #define N32_UB5(insn) (((insn) >> 10) & 0x1f) 147 #define N32_RB53(insn) (N32_RB5 (insn) & 0x7) 148 #define N32_RB54(insn) nds32_r54map[N32_RB5 (insn)] 149 #define N32_RD5(insn) (((insn) >> 5) & 0x1f) 150 #define N32_SH5(insn) (((insn) >> 5) & 0x1f) 151 #define N32_SUB5(insn) (((insn) >> 0) & 0x1f) 152 #define N32_SUB6(insn) (((insn) >> 0) & 0x3f) 153 #define N32_SWID(insn) (((insn) >> 5) & 0x3ff) 154 #define N32_IMMU(insn, bs) ((insn) & __MASK (bs)) 155 #define N32_IMMS(insn, bs) ((signed) __SEXT ((insn), (bs))) 156 #define N32_IMM5U(insn) N32_IMMU (insn, 5) 157 #define N32_IMM12S(insn) N32_IMMS (insn, 12) 158 #define N32_IMM14S(insn) N32_IMMS (insn, 14) 159 #define N32_IMM15U(insn) N32_IMMU (insn, 15) 160 #define N32_IMM15S(insn) N32_IMMS (insn, 15) 161 #define N32_IMM16S(insn) N32_IMMS (insn, 16) 162 #define N32_IMM17S(insn) N32_IMMS (insn, 17) 163 #define N32_IMM20S(insn) N32_IMMS (insn, 20) 164 #define N32_IMM20U(insn) N32_IMMU (insn, 20) 165 #define N32_IMM24S(insn) N32_IMMS (insn, 24) 166 167 #define N16_RT5(insn) (((insn) >> 5) & 0x1f) 168 #define N16_RT4(insn) nds32_r45map[(((insn) >> 5) & 0xf)] 169 #define N16_RT3(insn) (((insn) >> 6) & 0x7) 170 #define N16_RT38(insn) (((insn) >> 8) & 0x7) 171 #define N16_RT8(insn) (((insn) >> 8) & 0x7) 172 #define N16_RA5(insn) ((insn) & 0x1f) 173 #define N16_RA3(insn) (((insn) >> 3) & 0x7) 174 #define N16_RB3(insn) ((insn) & 0x7) 175 #define N16_IMM3U(insn) N32_IMMU (insn, 3) 176 #define N16_IMM5U(insn) N32_IMMU (insn, 5) 177 #define N16_IMM5S(insn) N32_IMMS (insn, 5) 178 #define N16_IMM6U(insn) N32_IMMU (insn, 6) 179 #define N16_IMM7U(insn) N32_IMMU (insn, 7) 180 #define N16_IMM8S(insn) N32_IMMS (insn, 8) 181 #define N16_IMM9U(insn) N32_IMMU (insn, 9) 182 #define N16_IMM10S(insn) N32_IMMS (insn, 10) 183 184 #define IS_WITHIN_U(v, n) (((v) >> n) == 0) 185 #define IS_WITHIN_S(v, n) IS_WITHIN_U ((v) + (1 << ((n) - 1)), n) 186 187 /* Get fields for specific instruction. */ 188 #define N32_JREG_T(insn) (((insn) >> 8) & 0x3) 189 #define N32_JREG_HINT(insn) (((insn) >> 5) & 0x7) 190 #define N32_BR2_SUB(insn) (((insn) >> 16) & 0xf) 191 #define N32_COP_SUB(insn) ((insn) & 0xf) 192 #define N32_COP_CP(insn) (((insn) >> 4) & 0x3) 193 194 /* Check fields. */ 195 #define N32_IS_RT3(insn) (N32_RT5 (insn) < 8) 196 #define N32_IS_RA3(insn) (N32_RA5 (insn) < 8) 197 #define N32_IS_RB3(insn) (N32_RB5 (insn) < 8) 198 #define N32_IS_RT4(insn) (nds32_r54map[N32_RT5 (insn)] != -1) 199 #define N32_IS_RA4(insn) (nds32_r54map[N32_RA5 (insn)] != -1) 200 #define N32_IS_RB4(insn) (nds32_r54map[N32_RB5 (insn)] != -1) 201 202 203 /* These are opcodes for Nxx_TYPE macros. 204 They are prefixed by corresponding TYPE to avoid misusing. */ 205 206 enum n32_opcodes 207 { 208 /* Main opcodes (OP6). */ 209 210 N32_OP6_LBI = 0x0, 211 N32_OP6_LHI, 212 N32_OP6_LWI, 213 N32_OP6_LDI, 214 N32_OP6_LBI_BI, 215 N32_OP6_LHI_BI, 216 N32_OP6_LWI_BI, 217 N32_OP6_LDI_BI, 218 219 N32_OP6_SBI = 0x8, 220 N32_OP6_SHI, 221 N32_OP6_SWI, 222 N32_OP6_SDI, 223 N32_OP6_SBI_BI, 224 N32_OP6_SHI_BI, 225 N32_OP6_SWI_BI, 226 N32_OP6_SDI_BI, 227 228 N32_OP6_LBSI = 0x10, 229 N32_OP6_LHSI, 230 N32_OP6_LWSI, 231 N32_OP6_DPREFI, 232 N32_OP6_LBSI_BI, 233 N32_OP6_LHSI_BI, 234 N32_OP6_LWSI_BI, 235 N32_OP6_LBGP, 236 237 N32_OP6_LWC = 0x18, 238 N32_OP6_SWC, 239 N32_OP6_LDC, 240 N32_OP6_SDC, 241 N32_OP6_MEM, 242 N32_OP6_LSMW, 243 N32_OP6_HWGP, 244 N32_OP6_SBGP, 245 246 N32_OP6_ALU1 = 0x20, 247 N32_OP6_ALU2, 248 N32_OP6_MOVI, 249 N32_OP6_SETHI, 250 N32_OP6_JI, 251 N32_OP6_JREG, 252 N32_OP6_BR1, 253 N32_OP6_BR2, 254 255 N32_OP6_ADDI = 0x28, 256 N32_OP6_SUBRI, 257 N32_OP6_ANDI, 258 N32_OP6_XORI, 259 N32_OP6_ORI, 260 N32_OP6_BR3, 261 N32_OP6_SLTI, 262 N32_OP6_SLTSI, 263 264 N32_OP6_AEXT = 0x30, 265 N32_OP6_CEXT, 266 N32_OP6_MISC, 267 N32_OP6_BITCI, 268 N32_OP6_0x34, 269 N32_OP6_COP, 270 N32_OP6_0x36, 271 N32_OP6_0x37, 272 273 N32_OP6_SIMD = 0x38, 274 275 /* Sub-opcodes of specific opcode. */ 276 277 /* bit-24 */ 278 N32_BR1_BEQ = 0, 279 N32_BR1_BNE = 1, 280 281 /* bit[16:19] */ 282 N32_BR2_SOP0 = 0, 283 N32_BR2_BEQZ = 2, 284 N32_BR2_BNEZ = 3, 285 N32_BR2_BGEZ = 4, 286 N32_BR2_BLTZ = 5, 287 N32_BR2_BGTZ = 6, 288 N32_BR2_BLEZ = 7, 289 N32_BR2_BGEZAL = 0xc, 290 N32_BR2_BLTZAL = 0xd, 291 292 /* bit-19 */ 293 N32_BR3_BEQC = 0, 294 N32_BR3_BNEC = 1, 295 296 /* bit-24 */ 297 N32_JI_J = 0, 298 N32_JI_JAL = 1, 299 300 /* bit[0:4] */ 301 N32_JREG_JR = 0, 302 N32_JREG_JRAL = 1, 303 N32_JREG_JRNEZ = 2, 304 N32_JREG_JRALNEZ = 3, 305 306 /* bit[0:4] */ 307 N32_ALU1_ADD_SLLI = 0x0, 308 N32_ALU1_SUB_SLLI, 309 N32_ALU1_AND_SLLI, 310 N32_ALU1_XOR_SLLI, 311 N32_ALU1_OR_SLLI, 312 N32_ALU1_ADD = 0x0, 313 N32_ALU1_SUB, 314 N32_ALU1_AND, 315 N32_ALU1_XOR, 316 N32_ALU1_OR, 317 N32_ALU1_NOR, 318 N32_ALU1_SLT, 319 N32_ALU1_SLTS, 320 N32_ALU1_SLLI = 0x8, 321 N32_ALU1_SRLI, 322 N32_ALU1_SRAI, 323 N32_ALU1_ROTRI, 324 N32_ALU1_SLL, 325 N32_ALU1_SRL, 326 N32_ALU1_SRA, 327 N32_ALU1_ROTR, 328 N32_ALU1_SEB = 0x10, 329 N32_ALU1_SEH, 330 N32_ALU1_BITC, 331 N32_ALU1_ZEH, 332 N32_ALU1_WSBH, 333 N32_ALU1_OR_SRLI, 334 N32_ALU1_DIVSR, 335 N32_ALU1_DIVR, 336 N32_ALU1_SVA = 0x18, 337 N32_ALU1_SVS, 338 N32_ALU1_CMOVZ, 339 N32_ALU1_CMOVN, 340 N32_ALU1_ADD_SRLI, 341 N32_ALU1_SUB_SRLI, 342 N32_ALU1_AND_SRLI, 343 N32_ALU1_XOR_SRLI, 344 345 /* bit[0:5], where bit[6:9] == 0 */ 346 N32_ALU2_MAX = 0, 347 N32_ALU2_MIN, 348 N32_ALU2_AVE, 349 N32_ALU2_ABS, 350 N32_ALU2_CLIPS, 351 N32_ALU2_CLIP, 352 N32_ALU2_CLO, 353 N32_ALU2_CLZ, 354 N32_ALU2_BSET = 0x8, 355 N32_ALU2_BCLR, 356 N32_ALU2_BTGL, 357 N32_ALU2_BTST, 358 N32_ALU2_BSE, 359 N32_ALU2_BSP, 360 N32_ALU2_FFB, 361 N32_ALU2_FFMISM, 362 N32_ALU2_ADD_SC = 0x10, 363 N32_ALU2_SUB_SC, 364 N32_ALU2_ADD_WC, 365 N32_ALU2_SUB_WC, 366 N32_ALU2_KMxy, 367 N32_ALU2_0x15, 368 N32_ALU2_0x16, 369 N32_ALU2_FFZMISM, 370 N32_ALU2_KADD = 0x18, 371 N32_ALU2_KSUB, 372 N32_ALU2_KSLRAW, 373 N32_ALU2_KSLRAWu, 374 N32_ALU2_MFUSR = 0x20, 375 N32_ALU2_MTUSR, 376 N32_ALU2_0x22, 377 N32_ALU2_0x23, 378 N32_ALU2_MUL, 379 N32_ALU2_0x25, 380 N32_ALU2_0x26, 381 N32_ALU2_MULTS64 = 0x28, 382 N32_ALU2_MULT64, 383 N32_ALU2_MADDS64, 384 N32_ALU2_MADD64, 385 N32_ALU2_MSUBS64, 386 N32_ALU2_MSUB64, 387 N32_ALU2_DIVS, 388 N32_ALU2_DIV, 389 N32_ALU2_ADD64 = 0x30, 390 N32_ALU2_MULT32, 391 N32_ALU2_SMAL, 392 N32_ALU2_MADD32, 393 N32_ALU2_SUB64, 394 N32_ALU2_MSUB32, 395 N32_ALU2_0x36, 396 N32_ALU2_0x37, 397 N32_ALU2_RADD64 = 0x38, 398 N32_ALU2_URADD64, 399 N32_ALU2_KADD64, 400 N32_ALU2_UKADD64, 401 N32_ALU2_RSUB64, 402 N32_ALU2_URSUB64, 403 N32_ALU2_KSUB64, 404 N32_ALU2_UKSUB64, 405 406 /* bit[0:5], where bit[6:9] = 0001 */ 407 N32_ALU2_SMAR64 = 0x0, 408 N32_ALU2_UMAR64, 409 N32_ALU2_SMSR64, 410 N32_ALU2_UMSR64, 411 N32_ALU2_KMAR64, 412 N32_ALU2_UKMAR64, 413 N32_ALU2_KMSR64, 414 N32_ALU2_UKMSR64, 415 N32_ALU2_SMALDA = 0x8, 416 N32_ALU2_SMSLDA, 417 N32_ALU2_SMALDS, 418 N32_ALU2_SMALBB, 419 N32_ALU2_FFBI = 0xe, 420 N32_ALU2_FLMISM = 0xf, 421 N32_ALU2_SMALXDA = 0x10, 422 N32_ALU2_SMSLXDA, 423 N32_ALU2_SMALXDS, 424 N32_ALU2_SMALBT, 425 N32_ALU2_SMALDRS = 0x1a, 426 N32_ALU2_SMALTT, 427 N32_ALU2_RDOV = 0x20, 428 N32_ALU2_CLROV, 429 N32_ALU2_MULSR64 = 0x28, 430 N32_ALU2_MULR64 = 0x29, 431 N32_ALU2_SMDS = 0x30, 432 N32_ALU2_SMXDS, 433 N32_ALU2_SMDRS, 434 N32_ALU2_MADDR32, 435 N32_ALU2_KMADRS, 436 N32_ALU2_MSUBR32, 437 N32_ALU2_KMADS, 438 N32_ALU2_KMAXDS, 439 440 /* bit[0:5], where bit[6:9] = 0010 */ 441 N32_ALU2_KADD16 = 0x0, 442 N32_ALU2_KSUB16, 443 N32_ALU2_KCRAS16, 444 N32_ALU2_KCRSA16, 445 N32_ALU2_KADD8, 446 N32_ALU2_KSUB8, 447 N32_ALU2_WEXT, 448 N32_ALU2_WEXTI, 449 N32_ALU2_UKADD16 = 0x8, 450 N32_ALU2_UKSUB16, 451 N32_ALU2_UKCRAS16, 452 N32_ALU2_UKCRSA16, 453 N32_ALU2_UKADD8, 454 N32_ALU2_UKSUB8, 455 N32_ALU2_ONEOP = 0xf, 456 N32_ALU2_SMBB = 0x10, 457 N32_ALU2_SMBT, 458 N32_ALU2_SMTT, 459 N32_ALU2_KMABB = 0x15, 460 N32_ALU2_KMABT, 461 N32_ALU2_KMATT, 462 N32_ALU2_KMDA = 0x18, 463 N32_ALU2_KMXDA, 464 N32_ALU2_KMADA, 465 N32_ALU2_KMAXDA, 466 N32_ALU2_KMSDA, 467 N32_ALU2_KMSXDA, 468 N32_ALU2_RADD16 = 0x20, 469 N32_ALU2_RSUB16, 470 N32_ALU2_RCRAS16, 471 N32_ALU2_RCRSA16, 472 N32_ALU2_RADD8, 473 N32_ALU2_RSUB8, 474 N32_ALU2_RADDW, 475 N32_ALU2_RSUBW, 476 N32_ALU2_URADD16 = 0x28, 477 N32_ALU2_URSUB16, 478 N32_ALU2_URCRAS16, 479 N32_ALU2_URCRSA16, 480 N32_ALU2_URADD8, 481 N32_ALU2_URSUB8, 482 N32_ALU2_URADDW, 483 N32_ALU2_URSUBW, 484 N32_ALU2_ADD16 = 0x30, 485 N32_ALU2_SUB16, 486 N32_ALU2_CRAS16, 487 N32_ALU2_CRSA16, 488 N32_ALU2_ADD8, 489 N32_ALU2_SUB8, 490 N32_ALU2_BITREV, 491 N32_ALU2_BITREVI, 492 N32_ALU2_SMMUL = 0x38, 493 N32_ALU2_SMMULu, 494 N32_ALU2_KMMAC, 495 N32_ALU2_KMMACu, 496 N32_ALU2_KMMSB, 497 N32_ALU2_KMMSBu, 498 N32_ALU2_KWMMUL, 499 N32_ALU2_KWMMULu, 500 501 /* bit[0:5], where bit[6:9] = 0011 */ 502 N32_ALU2_SMMWB = 0x0, 503 N32_ALU2_SMMWBu, 504 N32_ALU2_SMMWT, 505 N32_ALU2_SMMWTu, 506 N32_ALU2_KMMAWB, 507 N32_ALU2_KMMAWBu, 508 N32_ALU2_KMMAWT, 509 N32_ALU2_KMMAWTu, 510 N32_ALU2_PKTT16 = 0x8, 511 N32_ALU2_PKTB16, 512 N32_ALU2_PKBT16, 513 N32_ALU2_PKBB16, 514 N32_ALU2_0x10 = 0x10, 515 N32_ALU2_SCLIP16, 516 N32_ALU2_0x12, 517 N32_ALU2_SMAX16, 518 N32_ALU2_SMAX8 = 0x17, 519 N32_ALU2_0x18 = 0x18, 520 N32_ALU2_UCLIP16, 521 N32_ALU2_0x1a, 522 N32_ALU2_UMAX16, 523 N32_ALU2_UMAX8 = 0x1f, 524 N32_ALU2_SRA16 = 0x20, 525 N32_ALU2_SRA16u, 526 N32_ALU2_SRL16, 527 N32_ALU2_SRL16u, 528 N32_ALU2_SLL16, 529 N32_ALU2_KSLRA16, 530 N32_ALU2_KSLRA16u, 531 N32_ALU2_SRAu, 532 N32_ALU2_SRAI16 = 0x28, 533 N32_ALU2_SRAI16u, 534 N32_ALU2_SRLI16, 535 N32_ALU2_SRLI16u, 536 N32_ALU2_SLLI16, 537 N32_ALU2_KSLLI16, 538 N32_ALU2_KSLLI, 539 N32_ALU2_SRAIu, 540 N32_ALU2_CMPEQ16 = 0x30, 541 N32_ALU2_SCMPLT16, 542 N32_ALU2_SCMPLE16, 543 N32_ALU2_SMIN16, 544 N32_ALU2_CMPEQ8, 545 N32_ALU2_SCMPLT8, 546 N32_ALU2_SCMPLE8, 547 N32_ALU2_SMIN8, 548 N32_ALU2_0x38, 549 N32_ALU2_UCMPLT16 = 0x39, 550 N32_ALU2_UCMPLE16, 551 N32_ALU2_UMIN16, 552 N32_ALU2_0x3c, 553 N32_ALU2_UCMPLT8, 554 N32_ALU2_UCMPLE8, 555 N32_ALU2_UMIN8, 556 557 /* bit[0:5] */ 558 N32_MEM_LB = 0, 559 N32_MEM_LH, 560 N32_MEM_LW, 561 N32_MEM_LD, 562 N32_MEM_LB_BI, 563 N32_MEM_LH_BI, 564 N32_MEM_LW_BI, 565 N32_MEM_LD_BI, 566 N32_MEM_SB, 567 N32_MEM_SH, 568 N32_MEM_SW, 569 N32_MEM_SD, 570 N32_MEM_SB_BI, 571 N32_MEM_SH_BI, 572 N32_MEM_SW_BI, 573 N32_MEM_SD_BI, 574 N32_MEM_LBS, 575 N32_MEM_LHS, 576 N32_MEM_LWS, /* Not used. */ 577 N32_MEM_DPREF, 578 N32_MEM_LBS_BI, 579 N32_MEM_LHS_BI, 580 N32_MEM_LWS_BI, /* Not used. */ 581 N32_MEM_0x17, /* Not used. */ 582 N32_MEM_LLW, 583 N32_MEM_SCW, 584 N32_MEM_LBUP = 0x20, 585 N32_MEM_LWUP = 0x22, 586 N32_MEM_SBUP = 0x28, 587 N32_MEM_SWUP = 0x2a, 588 589 /* bit[0:1] */ 590 N32_LSMW_LSMW = 0, 591 N32_LSMW_LSMWA, 592 N32_LSMW_LSMWZB, 593 594 /* bit[2:4] */ 595 N32_LSMW_BI = 0, 596 N32_LSMW_BIM, 597 N32_LSMW_BD, 598 N32_LSMW_BDM, 599 N32_LSMW_AI, 600 N32_LSMW_AIM, 601 N32_LSMW_AD, 602 N32_LSMW_ADM, 603 604 /* bit[0:4] */ 605 N32_MISC_STANDBY = 0, 606 N32_MISC_CCTL, 607 N32_MISC_MFSR, 608 N32_MISC_MTSR, 609 N32_MISC_IRET, 610 N32_MISC_TRAP, 611 N32_MISC_TEQZ, 612 N32_MISC_TNEZ, 613 N32_MISC_DSB = 0x8, 614 N32_MISC_ISB, 615 N32_MISC_BREAK, 616 N32_MISC_SYSCALL, 617 N32_MISC_MSYNC, 618 N32_MISC_ISYNC, 619 N32_MISC_TLBOP, 620 N32_MISC_SPECL, 621 N32_MISC_BPICK = 0x10, 622 623 /* bit[0:4] */ 624 N32_SIMD_PBSAD = 0, 625 N32_SIMD_PBSADA = 1, 626 627 /* bit[0:3] */ 628 N32_COP_CPE1 = 0, 629 N32_COP_MFCP, 630 N32_COP_CPLW, 631 N32_COP_CPLD, 632 N32_COP_CPE2, 633 N32_COP_CPE3 = 8, 634 N32_COP_MTCP, 635 N32_COP_CPSW, 636 N32_COP_CPSD, 637 N32_COP_CPE4, 638 639 /* cop/0 b[3:0] */ 640 N32_FPU_FS1 = 0, 641 N32_FPU_MFCP, 642 N32_FPU_FLS, 643 N32_FPU_FLD, 644 N32_FPU_FS2, 645 N32_FPU_FD1 = 8, 646 N32_FPU_MTCP, 647 N32_FPU_FSS, 648 N32_FPU_FSD, 649 N32_FPU_FD2, 650 651 /* FS1 b[9:6] */ 652 N32_FPU_FS1_FADDS = 0, 653 N32_FPU_FS1_FSUBS, 654 N32_FPU_FS1_FCPYNSS, 655 N32_FPU_FS1_FCPYSS, 656 N32_FPU_FS1_FMADDS, 657 N32_FPU_FS1_FMSUBS, 658 N32_FPU_FS1_FCMOVNS, 659 N32_FPU_FS1_FCMOVZS, 660 N32_FPU_FS1_FNMADDS, 661 N32_FPU_FS1_FNMSUBS, 662 N32_FPU_FS1_10, 663 N32_FPU_FS1_11, 664 N32_FPU_FS1_FMULS = 12, 665 N32_FPU_FS1_FDIVS, 666 N32_FPU_FS1_14, 667 N32_FPU_FS1_F2OP = 15, 668 669 /* FS1/F2OP b[14:10] */ 670 N32_FPU_FS1_F2OP_FS2D = 0x00, 671 N32_FPU_FS1_F2OP_FSQRTS = 0x01, 672 N32_FPU_FS1_F2OP_FABSS = 0x05, 673 N32_FPU_FS1_F2OP_FUI2S = 0x08, 674 N32_FPU_FS1_F2OP_FSI2S = 0x0c, 675 N32_FPU_FS1_F2OP_FS2UI = 0x10, 676 N32_FPU_FS1_F2OP_FS2UI_Z = 0x14, 677 N32_FPU_FS1_F2OP_FS2SI = 0x18, 678 N32_FPU_FS1_F2OP_FS2SI_Z = 0x1c, 679 680 /* FS2 b[9:6] */ 681 N32_FPU_FS2_FCMPEQS = 0x0, 682 N32_FPU_FS2_FCMPLTS = 0x2, 683 N32_FPU_FS2_FCMPLES = 0x4, 684 N32_FPU_FS2_FCMPUNS = 0x6, 685 N32_FPU_FS2_FCMPEQS_E = 0x1, 686 N32_FPU_FS2_FCMPLTS_E = 0x3, 687 N32_FPU_FS2_FCMPLES_E = 0x5, 688 N32_FPU_FS2_FCMPUNS_E = 0x7, 689 690 /* FD1 b[9:6] */ 691 N32_FPU_FD1_FADDD = 0, 692 N32_FPU_FD1_FSUBD, 693 N32_FPU_FD1_FCPYNSD, 694 N32_FPU_FD1_FCPYSD, 695 N32_FPU_FD1_FMADDD, 696 N32_FPU_FD1_FMSUBD, 697 N32_FPU_FD1_FCMOVND, 698 N32_FPU_FD1_FCMOVZD, 699 N32_FPU_FD1_FNMADDD, 700 N32_FPU_FD1_FNMSUBD, 701 N32_FPU_FD1_10, 702 N32_FPU_FD1_11, 703 N32_FPU_FD1_FMULD = 12, 704 N32_FPU_FD1_FDIVD, 705 N32_FPU_FD1_14, 706 N32_FPU_FD1_F2OP = 15, 707 708 /* FD1/F2OP b[14:10] */ 709 N32_FPU_FD1_F2OP_FD2S = 0x00, 710 N32_FPU_FD1_F2OP_FSQRTD = 0x01, 711 N32_FPU_FD1_F2OP_FABSD = 0x05, 712 N32_FPU_FD1_F2OP_FUI2D = 0x08, 713 N32_FPU_FD1_F2OP_FSI2D = 0x0c, 714 N32_FPU_FD1_F2OP_FD2UI = 0x10, 715 N32_FPU_FD1_F2OP_FD2UI_Z = 0x14, 716 N32_FPU_FD1_F2OP_FD2SI = 0x18, 717 N32_FPU_FD1_F2OP_FD2SI_Z = 0x1c, 718 719 /* FD2 b[9:6] */ 720 N32_FPU_FD2_FCMPEQD = 0x0, 721 N32_FPU_FD2_FCMPLTD = 0x2, 722 N32_FPU_FD2_FCMPLED = 0x4, 723 N32_FPU_FD2_FCMPUND = 0x6, 724 N32_FPU_FD2_FCMPEQD_E = 0x1, 725 N32_FPU_FD2_FCMPLTD_E = 0x3, 726 N32_FPU_FD2_FCMPLED_E = 0x5, 727 N32_FPU_FD2_FCMPUND_E = 0x7, 728 729 /* MFCP b[9:6] */ 730 N32_FPU_MFCP_FMFSR = 0x0, 731 N32_FPU_MFCP_FMFDR = 0x1, 732 N32_FPU_MFCP_XR = 0xc, 733 734 /* MFCP/XR b[14:10] */ 735 N32_FPU_MFCP_XR_FMFCFG = 0x0, 736 N32_FPU_MFCP_XR_FMFCSR = 0x1, 737 738 /* MTCP b[9:6] */ 739 N32_FPU_MTCP_FMTSR = 0x0, 740 N32_FPU_MTCP_FMTDR = 0x1, 741 N32_FPU_MTCP_XR = 0xc, 742 743 /* MTCP/XR b[14:10] */ 744 N32_FPU_MTCP_XR_FMTCSR = 0x1 745 }; 746 747 enum n16_opcodes 748 { 749 N16_T55_MOV55 = 0x0, 750 N16_T55_MOVI55 = 0x1, 751 752 N16_T45_0 = 0, 753 N16_T45_ADD45 = 0x4, 754 N16_T45_SUB45 = 0x5, 755 N16_T45_ADDI45 = 0x6, 756 N16_T45_SUBI45 = 0x7, 757 N16_T45_SRAI45 = 0x8, 758 N16_T45_SRLI45 = 0x9, 759 N16_T45_LWI45_FE = 0x19, 760 N16_T45_LWI450 = 0x1a, 761 N16_T45_SWI450 = 0x1b, 762 N16_T45_SLTS45 = 0x30, 763 N16_T45_SLT45 = 0x31, 764 N16_T45_SLTSI45 = 0x32, 765 N16_T45_SLTI45 = 0x33, 766 N16_T45_MOVPI45 = 0x3d, 767 768 N15_T44_MOVD44 = 0x7d, 769 770 N16_T333_0 = 0, 771 N16_T333_SLLI333 = 0xa, 772 N16_T333_BFMI333 = 0xb, 773 N16_T333_ADD333 = 0xc, 774 N16_T333_SUB333 = 0xd, 775 N16_T333_ADDI333 = 0xe, 776 N16_T333_SUBI333 = 0xf, 777 N16_T333_LWI333 = 0x10, 778 N16_T333_LWI333_BI = 0x11, 779 N16_T333_LHI333 = 0x12, 780 N16_T333_LBI333 = 0x13, 781 N16_T333_SWI333 = 0x14, 782 N16_T333_SWI333_BI = 0x15, 783 N16_T333_SHI333 = 0x16, 784 N16_T333_SBI333 = 0x17, 785 N16_T333_MISC33 = 0x3f, 786 787 N16_T36_ADDRI36_SP = 0x18, 788 789 N16_T37_XWI37 = 0x7, 790 N16_T37_XWI37SP = 0xe, 791 792 N16_T38_BEQZ38 = 0x8, 793 N16_T38_BNEZ38 = 0x9, 794 N16_T38_BEQS38 = 0xa, 795 N16_T38_BNES38 = 0xb, 796 797 N16_T5_JR5 = 0x2e8, 798 N16_T5_JRAL5 = 0x2e9, 799 N16_T5_EX9IT = 0x2ea, 800 /* 0x2eb reserved. */ 801 N16_T5_RET5 = 0x2ec, 802 N16_T5_ADD5PC = 0x2ed, 803 /* 0x2e[ef] reserved. */ 804 N16_T5_BREAK16 = 0x350, 805 806 N16_T8_J8 = 0x55, 807 N16_T8_BEQZS8 = 0x68, 808 N16_T8_BNEZS8 = 0x69, 809 810 /* N16_T9_BREAK16 = 0x35 811 Since v3, SWID of BREAK16 above 32 are used for encoding EX9.IT. */ 812 N16_T9_EX9IT = 0x35, 813 N16_T9_IFCALL9 = 0x3c, 814 815 N16_T10_ADDI10S = 0x1b, 816 817 N16_T25_PUSH25 = 0xf8, 818 N16_T25_POP25 = 0xf9, 819 820 /* Sub-opcodes. */ 821 N16_MISC33_0 = 0, 822 N16_MISC33_1 = 1, 823 N16_MISC33_NEG33 = 2, 824 N16_MISC33_NOT33 = 3, 825 N16_MISC33_MUL33 = 4, 826 N16_MISC33_XOR33 = 5, 827 N16_MISC33_AND33 = 6, 828 N16_MISC33_OR33 = 7, 829 830 N16_BFMI333_ZEB33 = 0, 831 N16_BFMI333_ZEH33 = 1, 832 N16_BFMI333_SEB33 = 2, 833 N16_BFMI333_SEH33 = 3, 834 N16_BFMI333_XLSB33 = 4, 835 N16_BFMI333_X11B33 = 5, 836 N16_BFMI333_BMSKI33 = 6, 837 N16_BFMI333_FEXTI33 = 7 838 }; 839 840 /* These macros a deprecated. DO NOT use them anymore. 842 And please help rewrite code used them. */ 843 844 /* 32-bit instructions without operands. */ 845 #define INSN_SETHI 0x46000000 846 #define INSN_ORI 0x58000000 847 #define INSN_JR 0x4a000000 848 #define INSN_RET 0x4a000020 849 #define INSN_JAL 0x49000000 850 #define INSN_J 0x48000000 851 #define INSN_JRAL 0x4a000001 852 #define INSN_BGEZAL 0x4e0c0000 853 #define INSN_BLTZAL 0x4e0d0000 854 #define INSN_BEQ 0x4c000000 855 #define INSN_BNE 0x4c004000 856 #define INSN_BEQZ 0x4e020000 857 #define INSN_BNEZ 0x4e030000 858 #define INSN_BGEZ 0x4e040000 859 #define INSN_BLTZ 0x4e050000 860 #define INSN_BGTZ 0x4e060000 861 #define INSN_BLEZ 0x4e070000 862 #define INSN_MOVI 0x44000000 863 #define INSN_ADDI 0x50000000 864 #define INSN_ANDI 0x54000000 865 #define INSN_LDI 0x06000000 866 #define INSN_SDI 0x16000000 867 #define INSN_LW 0x38000002 868 #define INSN_LWI 0x04000000 869 #define INSN_LWSI 0x24000000 870 #define INSN_LWIP 0x0c000000 871 #define INSN_LHI 0x02000000 872 #define INSN_LHSI 0x22000000 873 #define INSN_LBI 0x00000000 874 #define INSN_LBSI 0x20000000 875 #define INSN_SWI 0x14000000 876 #define INSN_SWIP 0x1c000000 877 #define INSN_SHI 0x12000000 878 #define INSN_SBI 0x10000000 879 #define INSN_SLTI 0x5c000000 880 #define INSN_SLTSI 0x5e000000 881 #define INSN_ADD 0x40000000 882 #define INSN_SUB 0x40000001 883 #define INSN_SLT 0x40000006 884 #define INSN_SLTS 0x40000007 885 #define INSN_SLLI 0x40000008 886 #define INSN_SRLI 0x40000009 887 #define INSN_SRAI 0x4000000a 888 #define INSN_SEB 0x40000010 889 #define INSN_SEH 0x40000011 890 #define INSN_ZEB INSN_ANDI + 0xFF 891 #define INSN_ZEH 0x40000013 892 #define INSN_BREAK 0x6400000a 893 #define INSN_NOP 0x40000009 894 #define INSN_FLSI 0x30000000 895 #define INSN_FSSI 0x32000000 896 #define INSN_FLDI 0x34000000 897 #define INSN_FSDI 0x36000000 898 #define INSN_BEQC 0x5a000000 899 #define INSN_BNEC 0x5a080000 900 #define INSN_DSB 0x64000008 901 #define INSN_IFCALL 0x4e000000 902 #define INSN_IFRET 0x4a000060 903 #define INSN_BR1 0x4c000000 904 #define INSN_BR2 0x4e000000 905 906 /* 16-bit instructions without operand. */ 907 #define INSN_MOV55 0x8000 908 #define INSN_MOVI55 0x8400 909 #define INSN_ADD45 0x8800 910 #define INSN_SUB45 0x8a00 911 #define INSN_ADDI45 0x8c00 912 #define INSN_SUBI45 0x8e00 913 #define INSN_SRAI45 0x9000 914 #define INSN_SRLI45 0x9200 915 #define INSN_SLLI333 0x9400 916 #define INSN_BFMI333 0x9600 917 #define INSN_ADD333 0x9800 918 #define INSN_SUB333 0x9a00 919 #define INSN_ADDI333 0x9c00 920 #define INSN_SUBI333 0x9e00 921 #define INSN_LWI333 0xa000 922 #define INSN_LWI333P 0xa200 923 #define INSN_LHI333 0xa400 924 #define INSN_LBI333 0xa600 925 #define INSN_SWI333 0xa800 926 #define INSN_SWI333P 0xaa00 927 #define INSN_SHI333 0xac00 928 #define INSN_SBI333 0xae00 929 #define INSN_RSV01 0xb000 930 #define INSN_RSV02 0xb200 931 #define INSN_LWI450 0xb400 932 #define INSN_SWI450 0xb600 933 #define INSN_LWI37 0xb800 934 #define INSN_SWI37 0xb880 935 #define INSN_BEQZ38 0xc000 936 #define INSN_BNEZ38 0xc800 937 #define INSN_BEQS38 0xd000 938 #define INSN_J8 0xd500 939 #define INSN_BNES38 0xd800 940 #define INSN_JR5 0xdd00 941 #define INSN_RET5 0xdd80 942 #define INSN_JRAL5 0xdd20 943 #define INSN_EX9_IT_2 0xdd40 944 #define INSN_SLTS45 0xe000 945 #define INSN_SLT45 0xe200 946 #define INSN_SLTSI45 0xe400 947 #define INSN_SLTI45 0xe600 948 #define INSN_BEQZS8 0xe800 949 #define INSN_BNEZS8 0xe900 950 #define INSN_BREAK16 0xea00 951 #define INSN_EX9_IT_1 0xea00 952 #define INSN_NOP16 0x9200 953 /* 16-bit version 2. */ 954 #define INSN_ADDI10_SP 0xec00 955 #define INSN_LWI37SP 0xf000 956 #define INSN_SWI37SP 0xf080 957 /* 16-bit version 3. */ 958 #define INSN_IFRET16 0x83ff 959 #define INSN_ADDRI36_SP 0xb000 960 #define INSN_LWI45_FE 0xb200 961 #define INSN_IFCALL9 0xf800 962 #define INSN_MISC33 0xfe00 963 964 /* Instruction with specific operands. */ 965 #define INSN_ADDI_GP_TO_FP 0x51cd8000 /* BASELINE_V1. */ 966 #define INSN_ADDIGP_TO_FP 0x3fc80000 /* BASELINE_V2. */ 967 #define INSN_MOVI_TO_FP 0x45c00000 968 #define INSN_MFUSR_PC 0x420F8020 969 #define INSN_MFUSR_PC_MASK 0xFE0FFFFF 970 971 /* Instructions use $ta register as operand. */ 972 #define INSN_SETHI_TA (INSN_SETHI | (REG_TA << 20)) 973 #define INSN_ORI_TA (INSN_ORI | (REG_TA << 20) | (REG_TA << 15)) 974 #define INSN_ADD_TA (INSN_ADD | (REG_TA << 20)) 975 #define INSN_ADD45_TA (INSN_ADD45 | (REG_TA << 5)) 976 #define INSN_JR5_TA (INSN_JR5 | (REG_TA << 0)) 977 #define INSN_RET5_TA (INSN_RET5 | (REG_TA << 0)) 978 #define INSN_JR_TA (INSN_JR | (REG_TA << 10)) 979 #define INSN_RET_TA (INSN_RET | (REG_TA << 10)) 980 #define INSN_JRAL_TA (INSN_JRAL | (REG_LP << 20) | (REG_TA << 10)) 981 #define INSN_JRAL5_TA (INSN_JRAL5 | (REG_TA << 0)) 982 #define INSN_BEQZ_TA (INSN_BEQZ | (REG_TA << 20)) 983 #define INSN_BNEZ_TA (INSN_BNEZ | (REG_TA << 20)) 984 #define INSN_MOVI_TA (INSN_MOVI | (REG_TA << 20)) 985 #define INSN_BEQ_TA (INSN_BEQ | (REG_TA << 15)) 986 #define INSN_BNE_TA (INSN_BNE | (REG_TA << 15)) 987 988 /* Instructions use $r5 register as operand. */ 989 #define INSN_BNE_R5 (INSN_BNE | (REG_R5 << 15)) 990 #define INSN_BEQ_R5 (INSN_BEQ | (REG_R5 << 15)) 991 992 #endif 993
Indexes created Wed Oct 07 00:25:59 UTC 2026