crx-opc.c revision 1.1
1 /* crx-opc.c -- Table of opcodes for the CRX processor. 2 Copyright 2004, 2005, 2007, 2012 Free Software Foundation, Inc. 3 Contributed by Tomer Levi NSC, Israel. 4 Originally written for GAS 2.12 by Tomer Levi. 5 6 This file is part of the GNU opcodes library. 7 8 This library is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 It is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 21 MA 02110-1301, USA. */ 22 23 #include <stdio.h> 24 #include "libiberty.h" 25 #include "symcat.h" 26 #include "opcode/crx.h" 27 28 const inst crx_instruction[] = 29 { 30 /* Create an arithmetic instruction - INST[bw]. */ 31 #define ARITH_BYTE_INST(NAME, OPC) \ 32 /* opc8 cst4 r */ \ 33 {NAME, 1, OPC, 24, ARITH_BYTE_INS | CST4MAP, {{cst4,20}, {regr,16}}}, \ 34 /* opc8 i16 r */ \ 35 {NAME, 2, (OPC<<4)+0xE, 20, ARITH_BYTE_INS | CST4MAP, {{i16,0}, {regr,16}}}, \ 36 /* opc8 r r */ \ 37 {NAME, 1, OPC+0x40, 24, ARITH_BYTE_INS, {{regr,20}, {regr,16}}} 38 39 ARITH_BYTE_INST ("addub", 0x0), 40 ARITH_BYTE_INST ("addb", 0x1), 41 ARITH_BYTE_INST ("addcb", 0x2), 42 ARITH_BYTE_INST ("andb", 0x3), 43 ARITH_BYTE_INST ("cmpb", 0x4), 44 ARITH_BYTE_INST ("movb", 0x5), 45 ARITH_BYTE_INST ("orb", 0x6), 46 ARITH_BYTE_INST ("subb", 0x7), 47 ARITH_BYTE_INST ("subcb", 0x8), 48 ARITH_BYTE_INST ("xorb", 0x9), 49 ARITH_BYTE_INST ("mulb", 0xA), 50 51 ARITH_BYTE_INST ("adduw", 0x10), 52 ARITH_BYTE_INST ("addw", 0x11), 53 ARITH_BYTE_INST ("addcw", 0x12), 54 ARITH_BYTE_INST ("andw", 0x13), 55 ARITH_BYTE_INST ("cmpw", 0x14), 56 ARITH_BYTE_INST ("movw", 0x15), 57 ARITH_BYTE_INST ("orw", 0x16), 58 ARITH_BYTE_INST ("subw", 0x17), 59 ARITH_BYTE_INST ("subcw", 0x18), 60 ARITH_BYTE_INST ("xorw", 0x19), 61 ARITH_BYTE_INST ("mulw", 0x1A), 62 63 /* Create an arithmetic instruction - INST[d]. */ 64 #define ARITH_INST(NAME, OPC) \ 65 /* opc8 cst4 r */ \ 66 {NAME, 1, OPC, 24, ARITH_INS | CST4MAP, {{cst4,20}, {regr,16}}}, \ 67 /* opc8 i16 r */ \ 68 {NAME, 2, (OPC<<4)+0xE, 20, ARITH_INS | CST4MAP, {{i16,0}, {regr,16}}}, \ 69 /* opc8 i32 r */ \ 70 {NAME, 3, (OPC<<4)+0xF, 20, ARITH_INS, {{i32,0}, {regr,16}}}, \ 71 /* opc8 r r */ \ 72 {NAME, 1, OPC+0x40, 24, ARITH_INS, {{regr,20}, {regr,16}}} 73 74 ARITH_INST ("addud", 0x20), 75 ARITH_INST ("addd", 0x21), 76 ARITH_INST ("addcd", 0x22), 77 ARITH_INST ("andd", 0x23), 78 ARITH_INST ("cmpd", 0x24), 79 ARITH_INST ("movd", 0x25), 80 ARITH_INST ("ord", 0x26), 81 ARITH_INST ("subd", 0x27), 82 ARITH_INST ("subcd", 0x28), 83 ARITH_INST ("xord", 0x29), 84 ARITH_INST ("muld", 0x2A), 85 86 /* Create a shift instruction. */ 87 #define SHIFT_INST(NAME, OPRD, OPC1, SHIFT1, OPC2) \ 88 /* OPRD=ui3 -->> opc9 ui3 r */ \ 89 /* OPRD=ui4 -->> opc8 ui4 r */ \ 90 /* OPRD=ui5 -->> opc7 ui5 r */ \ 91 {NAME, 1, OPC1, SHIFT1, SHIFT_INS, {{OPRD,20}, {regr,16}}}, \ 92 /* opc8 r r */ \ 93 {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {regr,16}}} 94 95 SHIFT_INST ("sllb", ui3, 0x1F8, 23, 0x4D), 96 SHIFT_INST ("srlb", ui3, 0x1F9, 23, 0x4E), 97 SHIFT_INST ("srab", ui3, 0x1FA, 23, 0x4F), 98 99 SHIFT_INST ("sllw", ui4, 0xB6, 24, 0x5D), 100 SHIFT_INST ("srlw", ui4, 0xB7, 24, 0x5E), 101 SHIFT_INST ("sraw", ui4, 0xB8, 24, 0x5F), 102 103 SHIFT_INST ("slld", ui5, 0x78, 25, 0x6D), 104 SHIFT_INST ("srld", ui5, 0x79, 25, 0x6E), 105 SHIFT_INST ("srad", ui5, 0x7A, 25, 0x6F), 106 107 /* Create a conditional branch instruction. */ 108 #define BRANCH_INST(NAME, OPC) \ 109 /* opc4 c4 dispe9 */ \ 110 {NAME, 1, OPC, 24, BRANCH_INS | RELAXABLE, {{dispe9,16}}}, \ 111 /* opc4 c4 disps17 */ \ 112 {NAME, 2, (OPC<<8)+0x7E, 16, BRANCH_INS | RELAXABLE, {{disps17,0}}}, \ 113 /* opc4 c4 disps32 */ \ 114 {NAME, 3, (OPC<<8)+0x7F, 16, BRANCH_INS | RELAXABLE, {{disps32,0}}} 115 116 BRANCH_INST ("beq", 0x70), 117 BRANCH_INST ("bne", 0x71), 118 BRANCH_INST ("bcs", 0x72), 119 BRANCH_INST ("bcc", 0x73), 120 BRANCH_INST ("bhi", 0x74), 121 BRANCH_INST ("bls", 0x75), 122 BRANCH_INST ("bgt", 0x76), 123 BRANCH_INST ("ble", 0x77), 124 BRANCH_INST ("bfs", 0x78), 125 BRANCH_INST ("bfc", 0x79), 126 BRANCH_INST ("blo", 0x7A), 127 BRANCH_INST ("bhs", 0x7B), 128 BRANCH_INST ("blt", 0x7C), 129 BRANCH_INST ("bge", 0x7D), 130 BRANCH_INST ("br", 0x7E), 131 132 /* Create a 'Branch if Equal to 0' instruction. */ 133 #define BRANCH_NEQ_INST(NAME, OPC) \ 134 /* opc8 dispu5 r */ \ 135 {NAME, 1, OPC, 24, BRANCH_NEQ_INS, {{regr,16}, {dispu5,20}}} 136 137 BRANCH_NEQ_INST ("beq0b", 0xB0), 138 BRANCH_NEQ_INST ("bne0b", 0xB1), 139 BRANCH_NEQ_INST ("beq0w", 0xB2), 140 BRANCH_NEQ_INST ("bne0w", 0xB3), 141 BRANCH_NEQ_INST ("beq0d", 0xB4), 142 BRANCH_NEQ_INST ("bne0d", 0xB5), 143 144 /* Create instruction with no operands. */ 145 #define NO_OP_INST(NAME, OPC) \ 146 /* opc16 */ \ 147 {NAME, 1, OPC, 16, 0, {{0, 0}}} 148 149 NO_OP_INST ("nop", 0x3002), 150 NO_OP_INST ("retx", 0x3003), 151 NO_OP_INST ("di", 0x3004), 152 NO_OP_INST ("ei", 0x3005), 153 NO_OP_INST ("wait", 0x3006), 154 NO_OP_INST ("eiwait", 0x3007), 155 156 /* Create a 'Compare & Branch' instruction. */ 157 #define CMPBR_INST(NAME, OPC1, OPC2, C4) \ 158 /* opc12 r r c4 disps9 */ \ 159 {NAME, 2, ((0x300+OPC1)<<12)+C4, 8, CMPBR_INS | FMT_3| RELAXABLE, \ 160 {{regr,16}, {regr,12}, {disps9,0}}}, \ 161 /* opc12 r r c4 disps25 */ \ 162 {NAME, 3, ((0x310+OPC1)<<12)+C4, 8, CMPBR_INS | FMT_3 | RELAXABLE, \ 163 {{regr,16}, {regr,12}, {disps25,0}}}, \ 164 /* opc12 i4cst4 r c4 disps9 */ \ 165 {NAME, 2, ((0x300+OPC2)<<12)+C4, 8, CMPBR_INS | FMT_3 | RELAXABLE, \ 166 {{cst4,16}, {regr,12}, {disps9,0}}}, \ 167 /* opc12 i4cst4 r c4 disps25 */ \ 168 {NAME, 3, ((0x310+OPC2)<<12)+C4, 8, CMPBR_INS | FMT_3 | RELAXABLE, \ 169 {{cst4,16}, {regr,12}, {disps25,0}}} 170 171 CMPBR_INST ("cmpbeqb", 0x8, 0xC, 0x0), 172 CMPBR_INST ("cmpbneb", 0x8, 0xC, 0x1), 173 CMPBR_INST ("cmpbhib", 0x8, 0xC, 0x4), 174 CMPBR_INST ("cmpblsb", 0x8, 0xC, 0x5), 175 CMPBR_INST ("cmpbgtb", 0x8, 0xC, 0x6), 176 CMPBR_INST ("cmpbleb", 0x8, 0xC, 0x7), 177 CMPBR_INST ("cmpblob", 0x8, 0xC, 0xA), 178 CMPBR_INST ("cmpbhsb", 0x8, 0xC, 0xB), 179 CMPBR_INST ("cmpbltb", 0x8, 0xC, 0xC), 180 CMPBR_INST ("cmpbgeb", 0x8, 0xC, 0xD), 181 182 CMPBR_INST ("cmpbeqw", 0x9, 0xD, 0x0), 183 CMPBR_INST ("cmpbnew", 0x9, 0xD, 0x1), 184 CMPBR_INST ("cmpbhiw", 0x9, 0xD, 0x4), 185 CMPBR_INST ("cmpblsw", 0x9, 0xD, 0x5), 186 CMPBR_INST ("cmpbgtw", 0x9, 0xD, 0x6), 187 CMPBR_INST ("cmpblew", 0x9, 0xD, 0x7), 188 CMPBR_INST ("cmpblow", 0x9, 0xD, 0xA), 189 CMPBR_INST ("cmpbhsw", 0x9, 0xD, 0xB), 190 CMPBR_INST ("cmpbltw", 0x9, 0xD, 0xC), 191 CMPBR_INST ("cmpbgew", 0x9, 0xD, 0xD), 192 193 CMPBR_INST ("cmpbeqd", 0xA, 0xE, 0x0), 194 CMPBR_INST ("cmpbned", 0xA, 0xE, 0x1), 195 CMPBR_INST ("cmpbhid", 0xA, 0xE, 0x4), 196 CMPBR_INST ("cmpblsd", 0xA, 0xE, 0x5), 197 CMPBR_INST ("cmpbgtd", 0xA, 0xE, 0x6), 198 CMPBR_INST ("cmpbled", 0xA, 0xE, 0x7), 199 CMPBR_INST ("cmpblod", 0xA, 0xE, 0xA), 200 CMPBR_INST ("cmpbhsd", 0xA, 0xE, 0xB), 201 CMPBR_INST ("cmpbltd", 0xA, 0xE, 0xC), 202 CMPBR_INST ("cmpbged", 0xA, 0xE, 0xD), 203 204 /* Create an instruction using a single register operand. */ 205 #define REG1_INST(NAME, OPC) \ 206 /* opc8 c4 r */ \ 207 {NAME, 1, OPC, 20, NO_TYPE_INS, {{regr,16}}} 208 209 /* Same as REG1_INST, with additional FLAGS. */ 210 #define REG1_FLAG_INST(NAME, OPC, FLAGS) \ 211 /* opc8 c4 r */ \ 212 {NAME, 1, OPC, 20, NO_TYPE_INS | FLAGS, {{regr,16}}} 213 214 /* JCond instructions */ 215 REG1_INST ("jeq", 0xBA0), 216 REG1_INST ("jne", 0xBA1), 217 REG1_INST ("jcs", 0xBA2), 218 REG1_INST ("jcc", 0xBA3), 219 REG1_INST ("jhi", 0xBA4), 220 REG1_INST ("jls", 0xBA5), 221 REG1_INST ("jgt", 0xBA6), 222 REG1_INST ("jle", 0xBA7), 223 REG1_INST ("jfs", 0xBA8), 224 REG1_INST ("jfc", 0xBA9), 225 REG1_INST ("jlo", 0xBAA), 226 REG1_INST ("jhs", 0xBAB), 227 REG1_INST ("jlt", 0xBAC), 228 REG1_INST ("jge", 0xBAD), 229 REG1_INST ("jump", 0xBAE), 230 231 /* SCond instructions */ 232 REG1_INST ("seq", 0xBB0), 233 REG1_INST ("sne", 0xBB1), 234 REG1_INST ("scs", 0xBB2), 235 REG1_INST ("scc", 0xBB3), 236 REG1_INST ("shi", 0xBB4), 237 REG1_INST ("sls", 0xBB5), 238 REG1_INST ("sgt", 0xBB6), 239 REG1_INST ("sle", 0xBB7), 240 REG1_INST ("sfs", 0xBB8), 241 REG1_INST ("sfc", 0xBB9), 242 REG1_INST ("slo", 0xBBA), 243 REG1_INST ("shs", 0xBBB), 244 REG1_INST ("slt", 0xBBC), 245 REG1_INST ("sge", 0xBBD), 246 247 /* Create an instruction using two register operands. */ 248 #define REG2_INST(NAME, OPC) \ 249 /* opc24 r r OR opc20 c4 r r */ \ 250 {NAME, 2, 0x300800+OPC, 8, NO_TYPE_INS, {{regr,4}, {regr,0}}} 251 252 /* MULTIPLY INSTRUCTIONS */ 253 REG2_INST ("macsb", 0x40), 254 REG2_INST ("macub", 0x41), 255 REG2_INST ("macqb", 0x42), 256 257 REG2_INST ("macsw", 0x50), 258 REG2_INST ("macuw", 0x51), 259 REG2_INST ("macqw", 0x52), 260 261 REG2_INST ("macsd", 0x60), 262 REG2_INST ("macud", 0x61), 263 REG2_INST ("macqd", 0x62), 264 265 REG2_INST ("mullsd", 0x65), 266 REG2_INST ("mullud", 0x66), 267 268 REG2_INST ("mulsbw", 0x3B), 269 REG2_INST ("mulubw", 0x3C), 270 REG2_INST ("mulswd", 0x3D), 271 REG2_INST ("muluwd", 0x3E), 272 273 /* SIGNEXTEND STUFF */ 274 REG2_INST ("sextbw", 0x30), 275 REG2_INST ("sextbd", 0x31), 276 REG2_INST ("sextwd", 0x32), 277 REG2_INST ("zextbw", 0x34), 278 REG2_INST ("zextbd", 0x35), 279 REG2_INST ("zextwd", 0x36), 280 281 REG2_INST ("bswap", 0x3F), 282 283 REG2_INST ("maxsb", 0x80), 284 REG2_INST ("minsb", 0x81), 285 REG2_INST ("maxub", 0x82), 286 REG2_INST ("minub", 0x83), 287 REG2_INST ("absb", 0x84), 288 REG2_INST ("negb", 0x85), 289 REG2_INST ("cntl0b", 0x86), 290 REG2_INST ("cntl1b", 0x87), 291 REG2_INST ("popcntb",0x88), 292 REG2_INST ("rotlb", 0x89), 293 REG2_INST ("rotrb", 0x8A), 294 REG2_INST ("mulqb", 0x8B), 295 REG2_INST ("addqb", 0x8C), 296 REG2_INST ("subqb", 0x8D), 297 REG2_INST ("cntlsb", 0x8E), 298 299 REG2_INST ("maxsw", 0x90), 300 REG2_INST ("minsw", 0x91), 301 REG2_INST ("maxuw", 0x92), 302 REG2_INST ("minuw", 0x93), 303 REG2_INST ("absw", 0x94), 304 REG2_INST ("negw", 0x95), 305 REG2_INST ("cntl0w", 0x96), 306 REG2_INST ("cntl1w", 0x97), 307 REG2_INST ("popcntw",0x98), 308 REG2_INST ("rotlw", 0x99), 309 REG2_INST ("rotrw", 0x9A), 310 REG2_INST ("mulqw", 0x9B), 311 REG2_INST ("addqw", 0x9C), 312 REG2_INST ("subqw", 0x9D), 313 REG2_INST ("cntlsw", 0x9E), 314 315 REG2_INST ("maxsd", 0xA0), 316 REG2_INST ("minsd", 0xA1), 317 REG2_INST ("maxud", 0xA2), 318 REG2_INST ("minud", 0xA3), 319 REG2_INST ("absd", 0xA4), 320 REG2_INST ("negd", 0xA5), 321 REG2_INST ("cntl0d", 0xA6), 322 REG2_INST ("cntl1d", 0xA7), 323 REG2_INST ("popcntd",0xA8), 324 REG2_INST ("rotld", 0xA9), 325 REG2_INST ("rotrd", 0xAA), 326 REG2_INST ("mulqd", 0xAB), 327 REG2_INST ("addqd", 0xAC), 328 REG2_INST ("subqd", 0xAD), 329 REG2_INST ("cntlsd", 0xAE), 330 331 /* Conditional move instructions */ 332 REG2_INST ("cmoveqd", 0x70), 333 REG2_INST ("cmovned", 0x71), 334 REG2_INST ("cmovcsd", 0x72), 335 REG2_INST ("cmovccd", 0x73), 336 REG2_INST ("cmovhid", 0x74), 337 REG2_INST ("cmovlsd", 0x75), 338 REG2_INST ("cmovgtd", 0x76), 339 REG2_INST ("cmovled", 0x77), 340 REG2_INST ("cmovfsd", 0x78), 341 REG2_INST ("cmovfcd", 0x79), 342 REG2_INST ("cmovlod", 0x7A), 343 REG2_INST ("cmovhsd", 0x7B), 344 REG2_INST ("cmovltd", 0x7C), 345 REG2_INST ("cmovged", 0x7D), 346 347 /* Load instructions (from memory to register). */ 348 #define LD_REG_INST(NAME, OPC1, OPC2, DISP) \ 349 /* opc12 r abs16 */ \ 350 {NAME, 2, 0x320+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, \ 351 {{abs16,0}, {regr,16}}}, \ 352 /* opc12 r abs32 */ \ 353 {NAME, 3, 0x330+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, \ 354 {{abs32,0}, {regr,16}}}, \ 355 /* opc4 r rbase dispu[bwd]4 */ \ 356 {NAME, 1, 0x8+OPC2, 28, LD_STOR_INS | DISP | REVERSE_MATCH, \ 357 {{rbase_dispu4,16}, {regr,24}}}, \ 358 /* opc4 r rbase disps16 */ \ 359 {NAME, 2, ((0x8+OPC2)<<8)+0xE, 20, LD_STOR_INS | FMT_1 | REVERSE_MATCH, \ 360 {{rbase_disps16,16}, {regr,24}}}, \ 361 /* opc4 r rbase disps32 */ \ 362 {NAME, 3, ((0x8+OPC2)<<8)+0xF, 20, LD_STOR_INS | FMT_1 | REVERSE_MATCH, \ 363 {{rbase_disps32,16}, {regr,24}}}, \ 364 /* opc12 r rbase ridx scl2 disps6 */ \ 365 {NAME, 2, 0x32C+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, \ 366 {{rindex_disps6,0}, {regr,16}}}, \ 367 /* opc12 r rbase ridx scl2 disps22 */ \ 368 {NAME, 3, 0x33C+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, \ 369 {{rindex_disps22,0}, {regr,16}}}, \ 370 /* opc12 r rbase disps12 */ \ 371 {NAME, 2, 0x328+OPC1, 20, LD_STOR_INS_INC | REVERSE_MATCH, \ 372 {{rbase_disps12,12}, {regr,16}}} 373 374 LD_REG_INST ("loadb", 0x0, 0x0, DISPUB4), 375 LD_REG_INST ("loadw", 0x1, 0x1, DISPUW4), 376 LD_REG_INST ("loadd", 0x2, 0x2, DISPUD4), 377 378 /* Store instructions (from Register to Memory). */ 379 #define ST_REG_INST(NAME, OPC1, OPC2, DISP) \ 380 /* opc12 r abs16 */ \ 381 {NAME, 2, 0x320+OPC1, 20, LD_STOR_INS, {{regr,16}, {abs16,0}}}, \ 382 /* opc12 r abs32 */ \ 383 {NAME, 3, 0x330+OPC1, 20, LD_STOR_INS, {{regr,16}, {abs32,0}}}, \ 384 /* opc4 r rbase dispu[bwd]4 */ \ 385 {NAME, 1, 0x8+OPC2, 28, LD_STOR_INS | DISP, \ 386 {{regr,24}, {rbase_dispu4,16}}}, \ 387 /* opc4 r rbase disps16 */ \ 388 {NAME, 2, ((0x8+OPC2)<<8)+0xE, 20, LD_STOR_INS | FMT_1, \ 389 {{regr,24}, {rbase_disps16,16}}}, \ 390 /* opc4 r rbase disps32 */ \ 391 {NAME, 3, ((0x8+OPC2)<<8)+0xF, 20, LD_STOR_INS | FMT_1, \ 392 {{regr,24}, {rbase_disps32,16}}}, \ 393 /* opc12 r rbase ridx scl2 disps6 */ \ 394 {NAME, 2, 0x32C+OPC1, 20, LD_STOR_INS, \ 395 {{regr,16}, {rindex_disps6,0}}}, \ 396 /* opc12 r rbase ridx scl2 disps22 */ \ 397 {NAME, 3, 0x33C+OPC1, 20, LD_STOR_INS, {{regr,16}, {rindex_disps22,0}}}, \ 398 /* opc12 r rbase disps12 */ \ 399 {NAME, 2, 0x328+OPC1, 20, LD_STOR_INS_INC, {{regr,16}, {rbase_disps12,12}}} 400 401 /* Store instructions (Immediate to Memory). */ 402 #define ST_I_INST(NAME, OPC) \ 403 /* opc12 ui4 rbase disps12 */ \ 404 {NAME, 2, 0x368+OPC, 20, LD_STOR_INS_INC, {{ui4,16}, {rbase_disps12,12}}}, \ 405 /* opc12 ui4 abs16 */ \ 406 {NAME, 2, 0x360+OPC, 20, STOR_IMM_INS, {{ui4,16}, {abs16,0}}}, \ 407 /* opc12 ui4 abs32 */ \ 408 {NAME, 3, 0x370+OPC, 20, STOR_IMM_INS, {{ui4,16}, {abs32,0}}}, \ 409 /* opc12 ui4 rbase disps12 */ \ 410 {NAME, 2, 0x364+OPC, 20, STOR_IMM_INS, {{ui4,16}, {rbase_disps12,12}}}, \ 411 /* opc12 ui4 rbase disps28 */ \ 412 {NAME, 3, 0x374+OPC, 20, STOR_IMM_INS, {{ui4,16}, {rbase_disps28,12}}}, \ 413 /* opc12 ui4 rbase ridx scl2 disps6 */ \ 414 {NAME, 2, 0x36C+OPC, 20, STOR_IMM_INS, {{ui4,16}, {rindex_disps6,0}}}, \ 415 /* opc12 ui4 rbase ridx scl2 disps22 */ \ 416 {NAME, 3, 0x37C+OPC, 20, STOR_IMM_INS, {{ui4,16}, {rindex_disps22,0}}} 417 418 ST_REG_INST ("storb", 0x20, 0x4, DISPUB4), 419 ST_I_INST ("storb", 0x0), 420 421 ST_REG_INST ("storw", 0x21, 0x5, DISPUW4), 422 ST_I_INST ("storw", 0x1), 423 424 ST_REG_INST ("stord", 0x22, 0x6, DISPUD4), 425 ST_I_INST ("stord", 0x2), 426 427 /* Create a bit instruction. */ 428 #define CSTBIT_INST(NAME, OP, OPC1, DIFF, SHIFT, OPC2) \ 429 /* OP=ui3 -->> opc13 ui3 */ \ 430 /* OP=ui4 -->> opc12 ui4 */ \ 431 /* OP=ui5 -->> opc11 ui5 */ \ 432 \ 433 /* opcNN iN abs16 */ \ 434 {NAME, 2, OPC1+0*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {abs16,0}}}, \ 435 /* opcNN iN abs32 */ \ 436 {NAME, 3, OPC1+1*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {abs32,0}}}, \ 437 /* opcNN iN rbase */ \ 438 {NAME, 1, OPC2, SHIFT+4, CSTBIT_INS, {{OP,20}, {rbase,16}}}, \ 439 /* opcNN iN rbase disps12 */ \ 440 {NAME, 2, OPC1+2*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {rbase_disps12,12}}}, \ 441 /* opcNN iN rbase disps28 */ \ 442 {NAME, 3, OPC1+3*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {rbase_disps28,12}}}, \ 443 /* opcNN iN rbase ridx scl2 disps6 */ \ 444 {NAME, 2, OPC1+4*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {rindex_disps6,0}}}, \ 445 /* opcNN iN rbase ridx scl2 disps22 */ \ 446 {NAME, 3, OPC1+5*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {rindex_disps22,0}}} 447 448 CSTBIT_INST ("cbitb", ui3, 0x700, 0x20, 19, 0x1FC), 449 CSTBIT_INST ("cbitw", ui4, 0x382, 0x10, 20, 0xBD), 450 CSTBIT_INST ("cbitd", ui5, 0x1C3, 0x8, 21, 0x7B), 451 {"cbitd", 2, 0x300838, 8, CSTBIT_INS, {{regr,4}, {regr,0}}}, 452 {"cbitd", 2, 0x18047B, 9, CSTBIT_INS, {{ui5,4}, {regr,0}}}, 453 454 CSTBIT_INST ("sbitb", ui3, 0x701, 0x20, 19, 0x1FD), 455 CSTBIT_INST ("sbitw", ui4, 0x383, 0x10, 20, 0xBE), 456 CSTBIT_INST ("sbitd", ui5, 0x1C4, 0x8, 21, 0x7C), 457 {"sbitd", 2, 0x300839, 8, CSTBIT_INS, {{regr,4}, {regr,0}}}, 458 {"sbitd", 2, 0x18047C, 9, CSTBIT_INS, {{ui5,4}, {regr,0}}}, 459 460 CSTBIT_INST ("tbitb", ui3, 0x702, 0x20, 19, 0x1FE), 461 CSTBIT_INST ("tbitw", ui4, 0x384, 0x10, 20, 0xBF), 462 CSTBIT_INST ("tbitd", ui5, 0x1C5, 0x8, 21, 0x7D), 463 {"tbitd", 2, 0x30083A, 8, CSTBIT_INS, {{regr,4}, {regr,0}}}, 464 {"tbitd", 2, 0x18047D, 9, CSTBIT_INS, {{ui5,4}, {regr,0}}}, 465 466 /* Instructions including a register list (opcode is represented as a mask). */ 467 #define REGLIST_INST(NAME, OPC, FLAG) \ 468 /* opc12 r mask16 */ \ 469 {NAME, 2, OPC, 20, NO_TYPE_INS | REG_LIST | FLAG, {{regr,16}, {ui16,0}}} 470 471 REG1_INST ("getrfid", 0xFF9), 472 REG1_INST ("setrfid", 0xFFA), 473 474 REGLIST_INST ("push", 0x346, NO_RPTR), 475 REG1_FLAG_INST ("push", 0xFFB, NO_SP), 476 REGLIST_INST ("pushx", 0x347, NO_RPTR), 477 478 REGLIST_INST ("pop", 0x324, NO_RPTR), 479 REG1_FLAG_INST ("pop", 0xFFC, NO_SP), 480 REGLIST_INST ("popx", 0x327, NO_RPTR), 481 482 REGLIST_INST ("popret", 0x326, NO_RPTR), 483 REG1_FLAG_INST ("popret",0xFFD,NO_SP), 484 485 REGLIST_INST ("loadm", 0x324, NO_RPTR), 486 REGLIST_INST ("loadma", 0x325, USER_REG), 487 488 REGLIST_INST ("storm", 0x344, NO_RPTR), 489 REGLIST_INST ("storma", 0x345, USER_REG), 490 491 /* Create a branch instruction. */ 492 #define BR_INST(NAME, OPC1, OPC2, INS_TYPE) \ 493 /* opc12 r disps17 */ \ 494 {NAME, 2, OPC1, 20, INS_TYPE | RELAXABLE, {{regr,16}, {disps17,0}}}, \ 495 /* opc12 r disps32 */ \ 496 {NAME, 3, OPC2, 20, INS_TYPE | RELAXABLE, {{regr,16}, {disps32,0}}} 497 498 BR_INST ("bal", 0x307, 0x317, NO_TYPE_INS), 499 500 /* Decrement and Branch instructions. */ 501 BR_INST ("dbnzb", 0x304, 0x314, DCR_BRANCH_INS), 502 BR_INST ("dbnzw", 0x305, 0x315, DCR_BRANCH_INS), 503 BR_INST ("dbnzd", 0x306, 0x316, DCR_BRANCH_INS), 504 505 /* Jump and link instructions. */ 506 REG1_INST ("jal", 0xFF8), 507 REG2_INST ("jal", 0x37), 508 REG2_INST ("jalid", 0x33), 509 510 /* Create a CO-processor instruction. */ 511 /* esc12 c4 ui16 */ 512 {"cpi", 2, 0x301, 20, COP_REG_INS, {{ui4,16}, {ui16,0}}}, 513 /* esc12 c4 ui16 ui16 */ 514 {"cpi", 3, 0x311, 20, COP_REG_INS, {{ui4,16}, {ui16,0}, {ui16,16}}}, 515 516 #define COP_INST(NAME, OPC, TYPE, REG1, REG2) \ 517 /* opc12 c4 opc8 REG1 REG2 */ \ 518 {NAME, 2, 0x301030+OPC, 8, TYPE | FMT_2, {{ui4,16}, {REG1,4}, {REG2,0}}} 519 /* A reverse form of the above macro. */ 520 #define REV_COP_INST(NAME, OPC, TYPE, REG1, REG2) \ 521 /* opc12 c4 opc8 REG2 REG1 */ \ 522 {NAME, 2, 0x301030+OPC, 8, TYPE | FMT_2, {{ui4,16}, {REG1,0}, {REG2,4}}} 523 524 COP_INST ("mtcr", 0, COP_REG_INS, regr, copregr), 525 COP_INST ("mfcr", 1, COP_REG_INS, copregr, regr), 526 COP_INST ("mtcsr", 2, COPS_REG_INS, regr, copsregr), 527 COP_INST ("mfcsr", 3, COPS_REG_INS, copsregr, regr), 528 COP_INST ("ldcr", 4, COP_REG_INS, regr, copregr), 529 REV_COP_INST ("stcr", 5, COP_REG_INS, copregr, regr), 530 COP_INST ("ldcsr", 6, COPS_REG_INS, regr, copsregr), 531 REV_COP_INST ("stcsr", 7, COPS_REG_INS, copsregr, regr), 532 533 /* Create a memory-related CO-processor instruction. */ 534 #define COPMEM_INST(NAME, OPC, TYPE) \ 535 /* opc12 c4 opc12 r mask16 */ \ 536 {NAME, 3, 0x3110300+OPC, 4, TYPE | REG_LIST | FMT_5, \ 537 {{ui4,16}, {regr,0}, {ui16,16}}} 538 539 COPMEM_INST("loadmcr", 0, COP_REG_INS), 540 COPMEM_INST("stormcr", 1, COP_REG_INS), 541 COPMEM_INST("loadmcsr", 2, COPS_REG_INS), 542 COPMEM_INST("stormcsr", 3, COPS_REG_INS), 543 544 /* CO-processor extensions. */ 545 /* opc12 c4 opc4 ui4 disps9 */ 546 {"bcop", 2, 0x30107, 12, COP_BRANCH_INS | FMT_4 | RELAXABLE, 547 {{ui4,8}, {ui4,16}, {disps9,0}}}, 548 /* opc12 c4 opc4 ui4 disps25 */ 549 {"bcop", 3, 0x31107, 12, COP_BRANCH_INS | FMT_4 | RELAXABLE, 550 {{ui4,8}, {ui4,16}, {disps25,0}}}, 551 /* opc12 c4 opc4 cpdo r r */ 552 {"cpdop", 2, 0x3010B, 12, COP_REG_INS | FMT_4, 553 {{ui4,16}, {ui4,8}, {regr,4}, {regr,0}}}, 554 /* opc12 c4 opc4 cpdo r r cpdo16 */ 555 {"cpdop", 3, 0x3110B, 12, COP_REG_INS | FMT_4, 556 {{ui4,16}, {ui4,8}, {regr,4}, {regr,0}, {ui16,16}}}, 557 /* esc16 r procreg */ 558 {"mtpr", 2, 0x3009, 16, NO_TYPE_INS, {{regr8,8}, {regr8,0}}}, 559 /* esc16 procreg r */ 560 {"mfpr", 2, 0x300A, 16, NO_TYPE_INS, {{regr8,8}, {regr8,0}}}, 561 562 /* Miscellaneous. */ 563 /* opc12 ui4 */ 564 {"excp", 1, 0xFFF, 20, NO_TYPE_INS, {{ui4,16}}}, 565 /* opc28 ui4 */ 566 {"cinv", 2, 0x3010000, 4, NO_TYPE_INS, {{ui4,0}}}, 567 568 /* opc9 ui5 ui5 ui5 r r */ 569 {"ram", 2, 0x7C, 23, NO_TYPE_INS, 570 {{ui5,18}, {ui5,13}, {ui5,8}, {regr,4}, {regr,0}}}, 571 {"rim", 2, 0x7D, 23, NO_TYPE_INS, 572 {{ui5,18}, {ui5,13}, {ui5,8}, {regr,4}, {regr,0}}}, 573 574 /* opc9 ui3 r */ 575 {"rotb", 1, 0x1FB, 23, NO_TYPE_INS, {{ui3,20}, {regr,16}}}, 576 /* opc8 ui4 r */ 577 {"rotw", 1, 0xB9, 24, NO_TYPE_INS, {{ui4,20}, {regr,16}}}, 578 /* opc23 ui5 r */ 579 {"rotd", 2, 0x180478, 9, NO_TYPE_INS, {{ui5,4}, {regr,0}}}, 580 581 {NULL, 0, 0, 0, 0, {{0, 0}}} 582 }; 583 584 const int crx_num_opcodes = ARRAY_SIZE (crx_instruction); 585 586 /* Macro to build a reg_entry, which have an opcode image : 587 For example : 588 REG(u4, 0x84, CRX_U_REGTYPE) 589 is interpreted as : 590 {"u4", u4, 0x84, CRX_U_REGTYPE} */ 591 #define REG(NAME, N, TYPE) {STRINGX(NAME), {NAME}, N, TYPE} 592 593 const reg_entry crx_regtab[] = 594 { 595 /* Build a general purpose register r<N>. */ 596 #define REG_R(N) REG(CONCAT2(r,N), N, CRX_R_REGTYPE) 597 598 REG_R(0), REG_R(1), REG_R(2), REG_R(3), 599 REG_R(4), REG_R(5), REG_R(6), REG_R(7), 600 REG_R(8), REG_R(9), REG_R(10), REG_R(11), 601 REG_R(12), REG_R(13), REG_R(14), REG_R(15), 602 REG(ra, 0xe, CRX_R_REGTYPE), 603 REG(sp, 0xf, CRX_R_REGTYPE), 604 605 /* Build a user register u<N>. */ 606 #define REG_U(N) REG(CONCAT2(u,N), 0x80 + N, CRX_U_REGTYPE) 607 608 REG_U(0), REG_U(1), REG_U(2), REG_U(3), 609 REG_U(4), REG_U(5), REG_U(6), REG_U(7), 610 REG_U(8), REG_U(9), REG_U(10), REG_U(11), 611 REG_U(12), REG_U(13), REG_U(14), REG_U(15), 612 REG(ura, 0x8e, CRX_U_REGTYPE), 613 REG(usp, 0x8f, CRX_U_REGTYPE), 614 615 /* Build a configuration register. */ 616 #define REG_CFG(NAME, N) REG(NAME, N, CRX_CFG_REGTYPE) 617 618 REG_CFG(hi, 0x10), 619 REG_CFG(lo, 0x11), 620 REG_CFG(uhi, 0x90), 621 REG_CFG(ulo, 0x91), 622 REG_CFG(psr, 0x12), 623 REG_CFG(intbase, 0x13), 624 REG_CFG(isp, 0x14), 625 REG_CFG(cfg, 0x15), 626 REG_CFG(cpcfg, 0x16), 627 REG_CFG(cen, 0x17) 628 }; 629 630 const int crx_num_regs = ARRAY_SIZE (crx_regtab); 631 632 const reg_entry crx_copregtab[] = 633 { 634 /* Build a Coprocessor register c<N>. */ 635 #define REG_C(N) REG(CONCAT2(c,N), N, CRX_C_REGTYPE) 636 637 REG_C(0), REG_C(1), REG_C(2), REG_C(3), 638 REG_C(4), REG_C(5), REG_C(6), REG_C(7), 639 REG_C(8), REG_C(9), REG_C(10), REG_C(11), 640 REG_C(12), REG_C(13), REG_C(14), REG_C(15), 641 642 /* Build a Coprocessor Special register cs<N>. */ 643 #define REG_CS(N) REG(CONCAT2(cs,N), N, CRX_CS_REGTYPE) 644 645 REG_CS(0), REG_CS(1), REG_CS(2), REG_CS(3), 646 REG_CS(4), REG_CS(5), REG_CS(6), REG_CS(7), 647 REG_CS(8), REG_CS(9), REG_CS(10), REG_CS(11), 648 REG_CS(12), REG_CS(13), REG_CS(14), REG_CS(15) 649 }; 650 651 const int crx_num_copregs = ARRAY_SIZE (crx_copregtab); 652 653 /* CRX operands table. */ 654 const operand_entry crx_optab[] = 655 { 656 /* Index 0 is dummy, so we can count the instruction's operands. */ 657 {0, nullargs, 0}, /* dummy */ 658 {4, arg_ic, OP_CST4}, /* cst4 */ 659 {16, arg_ic, OP_SIGNED}, /* i16 */ 660 {32, arg_ic, OP_SIGNED}, /* i32 */ 661 {3, arg_ic, OP_UNSIGNED}, /* ui3 */ 662 {4, arg_ic, OP_UNSIGNED}, /* ui4 */ 663 {5, arg_ic, OP_UNSIGNED}, /* ui5 */ 664 {16, arg_ic, OP_UNSIGNED}, /* ui16 */ 665 {8, arg_c, OP_EVEN|OP_SHIFT|OP_SIGNED}, /* disps9 */ 666 {16, arg_c, OP_EVEN|OP_SHIFT|OP_SIGNED}, /* disps17 */ 667 {24, arg_c, OP_EVEN|OP_SHIFT|OP_SIGNED}, /* disps25 */ 668 {32, arg_c, OP_EVEN|OP_SHIFT|OP_SIGNED}, /* disps32 */ 669 {4, arg_c, OP_EVEN|OP_SHIFT_DEC|OP_UNSIGNED}, /* dispu5 */ 670 {8, arg_c, OP_EVEN|OP_SHIFT|OP_SIGNED|OP_ESC}, /* dispe9 */ 671 {16, arg_c, OP_UNSIGNED|OP_UPPER_64KB}, /* abs16 */ 672 {32, arg_c, OP_UNSIGNED}, /* abs32 */ 673 {4, arg_rbase, 0}, /* rbase */ 674 {4, arg_cr, OP_DISPU4}, /* rbase_dispu4 */ 675 {12, arg_cr, OP_SIGNED}, /* rbase_disps12 */ 676 {16, arg_cr, OP_SIGNED}, /* rbase_disps16 */ 677 {28, arg_cr, OP_SIGNED}, /* rbase_disps28 */ 678 {32, arg_cr, OP_SIGNED}, /* rbase_disps32 */ 679 {6, arg_idxr, OP_SIGNED}, /* rindex_disps6 */ 680 {22, arg_idxr, OP_SIGNED}, /* rindex_disps22 */ 681 {4, arg_r, 0}, /* regr */ 682 {8, arg_r, 0}, /* regr8 */ 683 {4, arg_copr, 0}, /* copregr */ 684 {4, arg_copsr, 0} /* copsregr */ 685 }; 686 687 /* CRX traps/interrupts. */ 688 const trap_entry crx_traps[] = 689 { 690 {"nmi", 1}, {"svc", 5}, {"dvz", 6}, {"flg", 7}, 691 {"bpt", 8}, {"und", 10}, {"prv", 11}, {"iberr", 12} 692 }; 693 694 const int crx_num_traps = ARRAY_SIZE (crx_traps); 695 696 /* cst4 operand mapping: 697 The value in entry <N> is mapped to the value <N> 698 Value Binary mapping 699 cst4_map[N] -->> N 700 701 Example (for N=5): 702 703 cst4_map[5]=-4 -->> 5 */ 704 const int cst4_map[] = 705 { 706 0, 1, 2, 3, 4, -4, -1, 7, 8, 16, 32, 20, 12, 48 707 }; 708 709 const int cst4_maps = ARRAY_SIZE (cst4_map); 710 711 /* CRX instructions that don't have arguments. */ 712 const char* no_op_insn[] = 713 { 714 "di", "ei", "eiwait", "nop", "retx", "wait", NULL 715 }; 716
Indexes created Sat May 02 00:23:24 UTC 2026