ppc-opc.c revision 1.6
1 /* ppc-opc.c -- PowerPC opcode list 2 Copyright (C) 1994-2018 Free Software Foundation, Inc. 3 Written by Ian Lance Taylor, Cygnus Support 4 5 This file is part of the GNU opcodes library. 6 7 This library is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 It is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this file; see the file COPYING. If not, write to the 19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 20 MA 02110-1301, USA. */ 21 22 #include "sysdep.h" 23 #include <stdio.h> 24 #include "opcode/ppc.h" 25 #include "opintl.h" 26 27 /* This file holds the PowerPC opcode table. The opcode table 28 includes almost all of the extended instruction mnemonics. This 29 permits the disassembler to use them, and simplifies the assembler 30 logic, at the cost of increasing the table size. The table is 31 strictly constant data, so the compiler should be able to put it in 32 the text segment. 33 34 This file also holds the operand table. All knowledge about 35 inserting operands into instructions and vice-versa is kept in this 36 file. */ 37 38 /* The functions used to insert and extract complicated operands. */ 39 40 /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */ 41 42 static uint64_t 43 insert_arx (uint64_t insn, 44 int64_t value, 45 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 46 const char **errmsg ATTRIBUTE_UNUSED) 47 { 48 if (value >= 8 && value < 24) 49 return insn | ((value - 8) & 0xf); 50 else 51 { 52 *errmsg = _("invalid register"); 53 return 0; 54 } 55 } 56 57 static int64_t 58 extract_arx (uint64_t insn, 59 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 60 int *invalid ATTRIBUTE_UNUSED) 61 { 62 return (insn & 0xf) + 8; 63 } 64 65 static uint64_t 66 insert_ary (uint64_t insn, 67 int64_t value, 68 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 69 const char **errmsg ATTRIBUTE_UNUSED) 70 { 71 if (value >= 8 && value < 24) 72 return insn | (((value - 8) & 0xf) << 4); 73 else 74 { 75 *errmsg = _("invalid register"); 76 return 0; 77 } 78 } 79 80 static int64_t 81 extract_ary (uint64_t insn, 82 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 83 int *invalid ATTRIBUTE_UNUSED) 84 { 85 return ((insn >> 4) & 0xf) + 8; 86 } 87 88 static uint64_t 89 insert_rx (uint64_t insn, 90 int64_t value, 91 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 92 const char **errmsg) 93 { 94 if (value >= 0 && value < 8) 95 return insn | value; 96 else if (value >= 24 && value <= 31) 97 return insn | (value - 16); 98 else 99 { 100 *errmsg = _("invalid register"); 101 return 0; 102 } 103 } 104 105 static int64_t 106 extract_rx (uint64_t insn, 107 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 108 int *invalid ATTRIBUTE_UNUSED) 109 { 110 int64_t value = insn & 0xf; 111 if (value >= 0 && value < 8) 112 return value; 113 else 114 return value + 16; 115 } 116 117 static uint64_t 118 insert_ry (uint64_t insn, 119 int64_t value, 120 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 121 const char **errmsg) 122 { 123 if (value >= 0 && value < 8) 124 return insn | (value << 4); 125 else if (value >= 24 && value <= 31) 126 return insn | ((value - 16) << 4); 127 else 128 { 129 *errmsg = _("invalid register"); 130 return 0; 131 } 132 } 133 134 static int64_t 135 extract_ry (uint64_t insn, 136 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 137 int *invalid ATTRIBUTE_UNUSED) 138 { 139 int64_t value = (insn >> 4) & 0xf; 140 if (value >= 0 && value < 8) 141 return value; 142 else 143 return value + 16; 144 } 145 146 /* The BA and BB fields in an XL form instruction or the RA and RB fields or 147 VRA and VRB fields in a VX form instruction when they must be the same. 148 This is used for extended mnemonics like crclr. The extraction function 149 enforces that the fields are the same. */ 150 151 static uint64_t 152 insert_bab (uint64_t insn, 153 int64_t value, 154 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 155 const char **errmsg ATTRIBUTE_UNUSED) 156 { 157 value &= 0x1f; 158 return insn | (value << 16) | (value << 11); 159 } 160 161 static int64_t 162 extract_bab (uint64_t insn, 163 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 164 int *invalid) 165 { 166 int64_t ba = (insn >> 16) & 0x1f; 167 int64_t bb = (insn >> 11) & 0x1f; 168 169 if (ba != bb) 170 *invalid = 1; 171 return ba; 172 } 173 174 /* The BT, BA and BB fields in an XL form instruction when they must all be 175 the same. This is used for extended mnemonics like crclr. The extraction 176 function enforces that the fields are the same. */ 177 178 static uint64_t 179 insert_btab (uint64_t insn, 180 int64_t value, 181 ppc_cpu_t dialect, 182 const char **errmsg) 183 { 184 value &= 0x1f; 185 return (value << 21) | insert_bab (insn, value, dialect, errmsg); 186 } 187 188 static int64_t 189 extract_btab (uint64_t insn, 190 ppc_cpu_t dialect, 191 int *invalid) 192 { 193 int64_t bt = (insn >> 21) & 0x1f; 194 int64_t bab = extract_bab (insn, dialect, invalid); 195 196 if (bt != bab) 197 *invalid = 1; 198 return bt; 199 } 200 201 /* The BD field in a B form instruction when the - modifier is used. 202 This modifier means that the branch is not expected to be taken. 203 For chips built to versions of the architecture prior to version 2 204 (ie. not Power4 compatible), we set the y bit of the BO field to 1 205 if the offset is negative. When extracting, we require that the y 206 bit be 1 and that the offset be positive, since if the y bit is 0 207 we just want to print the normal form of the instruction. 208 Power4 compatible targets use two bits, "a", and "t", instead of 209 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable, 210 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001 211 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000 212 for branch on CTR. We only handle the taken/not-taken hint here. 213 Note that we don't relax the conditions tested here when 214 disassembling with -Many because insns using extract_bdm and 215 extract_bdp always occur in pairs. One or the other will always 216 be valid. */ 217 218 #define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN) 219 220 static uint64_t 221 insert_bdm (uint64_t insn, 222 int64_t value, 223 ppc_cpu_t dialect, 224 const char **errmsg ATTRIBUTE_UNUSED) 225 { 226 if ((dialect & ISA_V2) == 0) 227 { 228 if ((value & 0x8000) != 0) 229 insn |= 1 << 21; 230 } 231 else 232 { 233 if ((insn & (0x14 << 21)) == (0x04 << 21)) 234 insn |= 0x02 << 21; 235 else if ((insn & (0x14 << 21)) == (0x10 << 21)) 236 insn |= 0x08 << 21; 237 } 238 return insn | (value & 0xfffc); 239 } 240 241 static int64_t 242 extract_bdm (uint64_t insn, 243 ppc_cpu_t dialect, 244 int *invalid) 245 { 246 if ((dialect & ISA_V2) == 0) 247 { 248 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0)) 249 *invalid = 1; 250 } 251 else 252 { 253 if ((insn & (0x17 << 21)) != (0x06 << 21) 254 && (insn & (0x1d << 21)) != (0x18 << 21)) 255 *invalid = 1; 256 } 257 258 return ((insn & 0xfffc) ^ 0x8000) - 0x8000; 259 } 260 261 /* The BD field in a B form instruction when the + modifier is used. 262 This is like BDM, above, except that the branch is expected to be 263 taken. */ 264 265 static uint64_t 266 insert_bdp (uint64_t insn, 267 int64_t value, 268 ppc_cpu_t dialect, 269 const char **errmsg ATTRIBUTE_UNUSED) 270 { 271 if ((dialect & ISA_V2) == 0) 272 { 273 if ((value & 0x8000) == 0) 274 insn |= 1 << 21; 275 } 276 else 277 { 278 if ((insn & (0x14 << 21)) == (0x04 << 21)) 279 insn |= 0x03 << 21; 280 else if ((insn & (0x14 << 21)) == (0x10 << 21)) 281 insn |= 0x09 << 21; 282 } 283 return insn | (value & 0xfffc); 284 } 285 286 static int64_t 287 extract_bdp (uint64_t insn, 288 ppc_cpu_t dialect, 289 int *invalid) 290 { 291 if ((dialect & ISA_V2) == 0) 292 { 293 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0)) 294 *invalid = 1; 295 } 296 else 297 { 298 if ((insn & (0x17 << 21)) != (0x07 << 21) 299 && (insn & (0x1d << 21)) != (0x19 << 21)) 300 *invalid = 1; 301 } 302 303 return ((insn & 0xfffc) ^ 0x8000) - 0x8000; 304 } 305 306 static inline int 307 valid_bo_pre_v2 (int64_t value) 308 { 309 /* Certain encodings have bits that are required to be zero. 310 These are (z must be zero, y may be anything): 311 0000y 312 0001y 313 001zy 314 0100y 315 0101y 316 011zy 317 1z00y 318 1z01y 319 1z1zz 320 */ 321 if ((value & 0x14) == 0) 322 return 1; 323 else if ((value & 0x14) == 0x4) 324 return (value & 0x2) == 0; 325 else if ((value & 0x14) == 0x10) 326 return (value & 0x8) == 0; 327 else 328 return value == 0x14; 329 } 330 331 static inline int 332 valid_bo_post_v2 (int64_t value) 333 { 334 /* Certain encodings have bits that are required to be zero. 335 These are (z must be zero, a & t may be anything): 336 0000z 337 0001z 338 001at 339 0100z 340 0101z 341 011at 342 1a00t 343 1a01t 344 1z1zz 345 */ 346 if ((value & 0x14) == 0) 347 return (value & 0x1) == 0; 348 else if ((value & 0x14) == 0x14) 349 return value == 0x14; 350 else 351 return 1; 352 } 353 354 /* Check for legal values of a BO field. */ 355 356 static int 357 valid_bo (int64_t value, ppc_cpu_t dialect, int extract) 358 { 359 int valid_y = valid_bo_pre_v2 (value); 360 int valid_at = valid_bo_post_v2 (value); 361 362 /* When disassembling with -Many, accept either encoding on the 363 second pass through opcodes. */ 364 if (extract && dialect == ~(ppc_cpu_t) PPC_OPCODE_ANY) 365 return valid_y || valid_at; 366 if ((dialect & ISA_V2) == 0) 367 return valid_y; 368 else 369 return valid_at; 370 } 371 372 /* The BO field in a B form instruction. Warn about attempts to set 373 the field to an illegal value. */ 374 375 static uint64_t 376 insert_bo (uint64_t insn, 377 int64_t value, 378 ppc_cpu_t dialect, 379 const char **errmsg) 380 { 381 if (!valid_bo (value, dialect, 0)) 382 *errmsg = _("invalid conditional option"); 383 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4)) 384 *errmsg = _("invalid counter access"); 385 return insn | ((value & 0x1f) << 21); 386 } 387 388 static int64_t 389 extract_bo (uint64_t insn, 390 ppc_cpu_t dialect, 391 int *invalid) 392 { 393 int64_t value = (insn >> 21) & 0x1f; 394 if (!valid_bo (value, dialect, 1)) 395 *invalid = 1; 396 return value; 397 } 398 399 /* The BO field in a B form instruction when the + or - modifier is 400 used. This is like the BO field, but it must be even. When 401 extracting it, we force it to be even. */ 402 403 static uint64_t 404 insert_boe (uint64_t insn, 405 int64_t value, 406 ppc_cpu_t dialect, 407 const char **errmsg) 408 { 409 if (!valid_bo (value, dialect, 0)) 410 *errmsg = _("invalid conditional option"); 411 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4)) 412 *errmsg = _("invalid counter access"); 413 else if ((value & 1) != 0) 414 *errmsg = _("attempt to set y bit when using + or - modifier"); 415 416 return insn | ((value & 0x1f) << 21); 417 } 418 419 static int64_t 420 extract_boe (uint64_t insn, 421 ppc_cpu_t dialect, 422 int *invalid) 423 { 424 int64_t value = (insn >> 21) & 0x1f; 425 if (!valid_bo (value, dialect, 1)) 426 *invalid = 1; 427 return value & 0x1e; 428 } 429 430 /* The DCMX field in a X form instruction when the field is split 431 into separate DC, DM and DX fields. */ 432 433 static uint64_t 434 insert_dcmxs (uint64_t insn, 435 int64_t value, 436 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 437 const char **errmsg ATTRIBUTE_UNUSED) 438 { 439 return (insn 440 | ((value & 0x1f) << 16) 441 | ((value & 0x20) >> 3) 442 | (value & 0x40)); 443 } 444 445 static int64_t 446 extract_dcmxs (uint64_t insn, 447 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 448 int *invalid ATTRIBUTE_UNUSED) 449 { 450 return (insn & 0x40) | ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f); 451 } 452 453 /* The D field in a DX form instruction when the field is split 454 into separate D0, D1 and D2 fields. */ 455 456 static uint64_t 457 insert_dxd (uint64_t insn, 458 int64_t value, 459 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 460 const char **errmsg ATTRIBUTE_UNUSED) 461 { 462 return insn | (value & 0xffc1) | ((value & 0x3e) << 15); 463 } 464 465 static int64_t 466 extract_dxd (uint64_t insn, 467 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 468 int *invalid ATTRIBUTE_UNUSED) 469 { 470 uint64_t dxd = (insn & 0xffc1) | ((insn >> 15) & 0x3e); 471 return (dxd ^ 0x8000) - 0x8000; 472 } 473 474 static uint64_t 475 insert_dxdn (uint64_t insn, 476 int64_t value, 477 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 478 const char **errmsg ATTRIBUTE_UNUSED) 479 { 480 return insert_dxd (insn, -value, dialect, errmsg); 481 } 482 483 static int64_t 484 extract_dxdn (uint64_t insn, 485 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 486 int *invalid ATTRIBUTE_UNUSED) 487 { 488 return -extract_dxd (insn, dialect, invalid); 489 } 490 491 /* FXM mask in mfcr and mtcrf instructions. */ 492 493 static uint64_t 494 insert_fxm (uint64_t insn, 495 int64_t value, 496 ppc_cpu_t dialect, 497 const char **errmsg) 498 { 499 /* If we're handling the mfocrf and mtocrf insns ensure that exactly 500 one bit of the mask field is set. */ 501 if ((insn & (1 << 20)) != 0) 502 { 503 if (value == 0 || (value & -value) != value) 504 { 505 *errmsg = _("invalid mask field"); 506 value = 0; 507 } 508 } 509 510 /* If only one bit of the FXM field is set, we can use the new form 511 of the instruction, which is faster. Unlike the Power4 branch hint 512 encoding, this is not backward compatible. Do not generate the 513 new form unless -mpower4 has been given, or -many and the two 514 operand form of mfcr was used. */ 515 else if (value > 0 516 && (value & -value) == value 517 && ((dialect & PPC_OPCODE_POWER4) != 0 518 || ((dialect & PPC_OPCODE_ANY) != 0 519 && (insn & (0x3ff << 1)) == 19 << 1))) 520 insn |= 1 << 20; 521 522 /* Any other value on mfcr is an error. */ 523 else if ((insn & (0x3ff << 1)) == 19 << 1) 524 { 525 /* A value of -1 means we used the one operand form of 526 mfcr which is valid. */ 527 if (value != -1) 528 *errmsg = _("invalid mfcr mask"); 529 value = 0; 530 } 531 532 return insn | ((value & 0xff) << 12); 533 } 534 535 static int64_t 536 extract_fxm (uint64_t insn, 537 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 538 int *invalid) 539 { 540 int64_t mask = (insn >> 12) & 0xff; 541 542 /* Is this a Power4 insn? */ 543 if ((insn & (1 << 20)) != 0) 544 { 545 /* Exactly one bit of MASK should be set. */ 546 if (mask == 0 || (mask & -mask) != mask) 547 *invalid = 1; 548 } 549 550 /* Check that non-power4 form of mfcr has a zero MASK. */ 551 else if ((insn & (0x3ff << 1)) == 19 << 1) 552 { 553 if (mask != 0) 554 *invalid = 1; 555 else 556 mask = -1; 557 } 558 559 return mask; 560 } 561 562 static uint64_t 563 insert_li20 (uint64_t insn, 564 int64_t value, 565 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 566 const char **errmsg ATTRIBUTE_UNUSED) 567 { 568 return (insn 569 | ((value & 0xf0000) >> 5) 570 | ((value & 0x0f800) << 5) 571 | (value & 0x7ff)); 572 } 573 574 static int64_t 575 extract_li20 (uint64_t insn, 576 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 577 int *invalid ATTRIBUTE_UNUSED) 578 { 579 return ((((insn << 5) & 0xf0000) 580 | ((insn >> 5) & 0xf800) 581 | (insn & 0x7ff)) ^ 0x80000) - 0x80000; 582 } 583 584 /* The 2-bit L field in a SYNC or WC field in a WAIT instruction. 585 For SYNC, some L values are reserved: 586 * Value 3 is reserved on newer server cpus. 587 * Values 2 and 3 are reserved on all other cpus. */ 588 589 static uint64_t 590 insert_ls (uint64_t insn, 591 int64_t value, 592 ppc_cpu_t dialect, 593 const char **errmsg) 594 { 595 /* For SYNC, some L values are illegal. */ 596 if (((insn >> 1) & 0x3ff) == 598) 597 { 598 int64_t max_lvalue = (dialect & PPC_OPCODE_POWER4) ? 2 : 1; 599 if (value > max_lvalue) 600 { 601 *errmsg = _("illegal L operand value"); 602 return insn; 603 } 604 } 605 606 return insn | ((value & 0x3) << 21); 607 } 608 609 static int64_t 610 extract_ls (uint64_t insn, 611 ppc_cpu_t dialect, 612 int *invalid) 613 { 614 uint64_t lvalue = (insn >> 21) & 3; 615 616 if (((insn >> 1) & 0x3ff) == 598) 617 { 618 uint64_t max_lvalue = (dialect & PPC_OPCODE_POWER4) ? 2 : 1; 619 if (lvalue > max_lvalue) 620 *invalid = 1; 621 } 622 return lvalue; 623 } 624 625 /* The 4-bit E field in a sync instruction that accepts 2 operands. 626 If ESYNC is non-zero, then the L field must be either 0 or 1 and 627 the complement of ESYNC-bit2. */ 628 629 static uint64_t 630 insert_esync (uint64_t insn, 631 int64_t value, 632 ppc_cpu_t dialect, 633 const char **errmsg) 634 { 635 uint64_t ls = (insn >> 21) & 0x03; 636 637 if (value == 0) 638 { 639 if (((dialect & PPC_OPCODE_E6500) != 0 && ls > 1) 640 || ((dialect & PPC_OPCODE_POWER9) != 0 && ls > 2)) 641 *errmsg = _("illegal L operand value"); 642 return insn; 643 } 644 645 if ((ls & ~0x1) 646 || (((value >> 1) & 0x1) ^ ls) == 0) 647 *errmsg = _("incompatible L operand value"); 648 649 return insn | ((value & 0xf) << 16); 650 } 651 652 static int64_t 653 extract_esync (uint64_t insn, 654 ppc_cpu_t dialect, 655 int *invalid) 656 { 657 uint64_t ls = (insn >> 21) & 0x3; 658 uint64_t lvalue = (insn >> 16) & 0xf; 659 660 if (lvalue == 0) 661 { 662 if (((dialect & PPC_OPCODE_E6500) != 0 && ls > 1) 663 || ((dialect & PPC_OPCODE_POWER9) != 0 && ls > 2)) 664 *invalid = 1; 665 } 666 else if ((ls & ~0x1) 667 || (((lvalue >> 1) & 0x1) ^ ls) == 0) 668 *invalid = 1; 669 670 return lvalue; 671 } 672 673 /* The MB and ME fields in an M form instruction expressed as a single 674 operand which is itself a bitmask. The extraction function always 675 marks it as invalid, since we never want to recognize an 676 instruction which uses a field of this type. */ 677 678 static uint64_t 679 insert_mbe (uint64_t insn, 680 int64_t value, 681 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 682 const char **errmsg) 683 { 684 uint64_t uval, mask; 685 long mb, me, mx, count, last; 686 687 uval = value; 688 689 if (uval == 0) 690 { 691 *errmsg = _("illegal bitmask"); 692 return insn; 693 } 694 695 mb = 0; 696 me = 32; 697 if ((uval & 1) != 0) 698 last = 1; 699 else 700 last = 0; 701 count = 0; 702 703 /* mb: location of last 0->1 transition */ 704 /* me: location of last 1->0 transition */ 705 /* count: # transitions */ 706 707 for (mx = 0, mask = (uint64_t) 1 << 31; mx < 32; ++mx, mask >>= 1) 708 { 709 if ((uval & mask) && !last) 710 { 711 ++count; 712 mb = mx; 713 last = 1; 714 } 715 else if (!(uval & mask) && last) 716 { 717 ++count; 718 me = mx; 719 last = 0; 720 } 721 } 722 if (me == 0) 723 me = 32; 724 725 if (count != 2 && (count != 0 || ! last)) 726 *errmsg = _("illegal bitmask"); 727 728 return insn | (mb << 6) | ((me - 1) << 1); 729 } 730 731 static int64_t 732 extract_mbe (uint64_t insn, 733 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 734 int *invalid) 735 { 736 int64_t ret; 737 long mb, me; 738 long i; 739 740 *invalid = 1; 741 742 mb = (insn >> 6) & 0x1f; 743 me = (insn >> 1) & 0x1f; 744 if (mb < me + 1) 745 { 746 ret = 0; 747 for (i = mb; i <= me; i++) 748 ret |= (uint64_t) 1 << (31 - i); 749 } 750 else if (mb == me + 1) 751 ret = ~0; 752 else /* (mb > me + 1) */ 753 { 754 ret = ~0; 755 for (i = me + 1; i < mb; i++) 756 ret &= ~((uint64_t) 1 << (31 - i)); 757 } 758 return ret; 759 } 760 761 /* The MB or ME field in an MD or MDS form instruction. The high bit 762 is wrapped to the low end. */ 763 764 static uint64_t 765 insert_mb6 (uint64_t insn, 766 int64_t value, 767 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 768 const char **errmsg ATTRIBUTE_UNUSED) 769 { 770 return insn | ((value & 0x1f) << 6) | (value & 0x20); 771 } 772 773 static int64_t 774 extract_mb6 (uint64_t insn, 775 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 776 int *invalid ATTRIBUTE_UNUSED) 777 { 778 return ((insn >> 6) & 0x1f) | (insn & 0x20); 779 } 780 781 /* The NB field in an X form instruction. The value 32 is stored as 782 0. */ 783 784 static int64_t 785 extract_nb (uint64_t insn, 786 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 787 int *invalid ATTRIBUTE_UNUSED) 788 { 789 int64_t ret; 790 791 ret = (insn >> 11) & 0x1f; 792 if (ret == 0) 793 ret = 32; 794 return ret; 795 } 796 797 /* The NB field in an lswi instruction, which has special value 798 restrictions. The value 32 is stored as 0. */ 799 800 static uint64_t 801 insert_nbi (uint64_t insn, 802 int64_t value, 803 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 804 const char **errmsg ATTRIBUTE_UNUSED) 805 { 806 int64_t rtvalue = (insn >> 21) & 0x1f; 807 int64_t ravalue = (insn >> 16) & 0x1f; 808 809 if (value == 0) 810 value = 32; 811 if (rtvalue + (value + 3) / 4 > (rtvalue > ravalue ? ravalue + 32 812 : ravalue)) 813 *errmsg = _("address register in load range"); 814 return insn | ((value & 0x1f) << 11); 815 } 816 817 /* The NSI field in a D form instruction. This is the same as the SI 818 field, only negated. The extraction function always marks it as 819 invalid, since we never want to recognize an instruction which uses 820 a field of this type. */ 821 822 static uint64_t 823 insert_nsi (uint64_t insn, 824 int64_t value, 825 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 826 const char **errmsg ATTRIBUTE_UNUSED) 827 { 828 return insn | (-value & 0xffff); 829 } 830 831 static int64_t 832 extract_nsi (uint64_t insn, 833 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 834 int *invalid) 835 { 836 *invalid = 1; 837 return -(((insn & 0xffff) ^ 0x8000) - 0x8000); 838 } 839 840 /* The RA field in a D or X form instruction which is an updating 841 load, which means that the RA field may not be zero and may not 842 equal the RT field. */ 843 844 static uint64_t 845 insert_ral (uint64_t insn, 846 int64_t value, 847 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 848 const char **errmsg) 849 { 850 if (value == 0 851 || (uint64_t) value == ((insn >> 21) & 0x1f)) 852 *errmsg = "invalid register operand when updating"; 853 return insn | ((value & 0x1f) << 16); 854 } 855 856 static int64_t 857 extract_ral (uint64_t insn, 858 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 859 int *invalid) 860 { 861 int64_t rtvalue = (insn >> 21) & 0x1f; 862 int64_t ravalue = (insn >> 16) & 0x1f; 863 864 if (rtvalue == ravalue || ravalue == 0) 865 *invalid = 1; 866 return ravalue; 867 } 868 869 /* The RA field in an lmw instruction, which has special value 870 restrictions. */ 871 872 static uint64_t 873 insert_ram (uint64_t insn, 874 int64_t value, 875 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 876 const char **errmsg) 877 { 878 if ((uint64_t) value >= ((insn >> 21) & 0x1f)) 879 *errmsg = _("index register in load range"); 880 return insn | ((value & 0x1f) << 16); 881 } 882 883 static int64_t 884 extract_ram (uint64_t insn, 885 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 886 int *invalid) 887 { 888 uint64_t rtvalue = (insn >> 21) & 0x1f; 889 uint64_t ravalue = (insn >> 16) & 0x1f; 890 891 if (ravalue >= rtvalue) 892 *invalid = 1; 893 return ravalue; 894 } 895 896 /* The RA field in the DQ form lq or an lswx instruction, which have special 897 value restrictions. */ 898 899 static uint64_t 900 insert_raq (uint64_t insn, 901 int64_t value, 902 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 903 const char **errmsg) 904 { 905 int64_t rtvalue = (insn >> 21) & 0x1f; 906 907 if (value == rtvalue) 908 *errmsg = _("source and target register operands must be different"); 909 return insn | ((value & 0x1f) << 16); 910 } 911 912 static int64_t 913 extract_raq (uint64_t insn, 914 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 915 int *invalid) 916 { 917 uint64_t rtvalue = (insn >> 21) & 0x1f; 918 uint64_t ravalue = (insn >> 16) & 0x1f; 919 920 if (ravalue == rtvalue) 921 *invalid = 1; 922 return ravalue; 923 } 924 925 /* The RA field in a D or X form instruction which is an updating 926 store or an updating floating point load, which means that the RA 927 field may not be zero. */ 928 929 static uint64_t 930 insert_ras (uint64_t insn, 931 int64_t value, 932 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 933 const char **errmsg) 934 { 935 if (value == 0) 936 *errmsg = _("invalid register operand when updating"); 937 return insn | ((value & 0x1f) << 16); 938 } 939 940 static int64_t 941 extract_ras (uint64_t insn, 942 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 943 int *invalid) 944 { 945 uint64_t ravalue = (insn >> 16) & 0x1f; 946 947 if (ravalue == 0) 948 *invalid = 1; 949 return ravalue; 950 } 951 952 /* The RS and RB fields in an X form instruction when they must be the same. 953 This is used for extended mnemonics like mr. The extraction function 954 enforces that the fields are the same. */ 955 956 static uint64_t 957 insert_rsb (uint64_t insn, 958 int64_t value, 959 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 960 const char **errmsg ATTRIBUTE_UNUSED) 961 { 962 value &= 0x1f; 963 return insn | (value << 21) | (value << 11); 964 } 965 966 static int64_t 967 extract_rsb (uint64_t insn, 968 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 969 int *invalid) 970 { 971 int64_t rs = (insn >> 21) & 0x1f; 972 int64_t rb = (insn >> 11) & 0x1f; 973 974 if (rs != rb) 975 *invalid = 1; 976 return rs; 977 } 978 979 /* The RB field in an lswx instruction, which has special value 980 restrictions. */ 981 982 static uint64_t 983 insert_rbx (uint64_t insn, 984 int64_t value, 985 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 986 const char **errmsg) 987 { 988 int64_t rtvalue = (insn >> 21) & 0x1f; 989 990 if (value == rtvalue) 991 *errmsg = _("source and target register operands must be different"); 992 return insn | ((value & 0x1f) << 11); 993 } 994 995 static int64_t 996 extract_rbx (uint64_t insn, 997 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 998 int *invalid) 999 { 1000 uint64_t rtvalue = (insn >> 21) & 0x1f; 1001 uint64_t rbvalue = (insn >> 11) & 0x1f; 1002 1003 if (rbvalue == rtvalue) 1004 *invalid = 1; 1005 return rbvalue; 1006 } 1007 1008 /* The SCI8 field is made up of SCL and {U,N}I8 fields. */ 1009 static uint64_t 1010 insert_sci8 (uint64_t insn, 1011 int64_t value, 1012 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1013 const char **errmsg) 1014 { 1015 uint64_t fill_scale = 0; 1016 uint64_t ui8 = value; 1017 1018 if ((ui8 & 0xffffff00) == 0) 1019 ; 1020 else if ((ui8 & 0xffffff00) == 0xffffff00) 1021 fill_scale = 0x400; 1022 else if ((ui8 & 0xffff00ff) == 0) 1023 { 1024 fill_scale = 1 << 8; 1025 ui8 >>= 8; 1026 } 1027 else if ((ui8 & 0xffff00ff) == 0xffff00ff) 1028 { 1029 fill_scale = 0x400 | (1 << 8); 1030 ui8 >>= 8; 1031 } 1032 else if ((ui8 & 0xff00ffff) == 0) 1033 { 1034 fill_scale = 2 << 8; 1035 ui8 >>= 16; 1036 } 1037 else if ((ui8 & 0xff00ffff) == 0xff00ffff) 1038 { 1039 fill_scale = 0x400 | (2 << 8); 1040 ui8 >>= 16; 1041 } 1042 else if ((ui8 & 0x00ffffff) == 0) 1043 { 1044 fill_scale = 3 << 8; 1045 ui8 >>= 24; 1046 } 1047 else if ((ui8 & 0x00ffffff) == 0x00ffffff) 1048 { 1049 fill_scale = 0x400 | (3 << 8); 1050 ui8 >>= 24; 1051 } 1052 else 1053 { 1054 *errmsg = _("illegal immediate value"); 1055 ui8 = 0; 1056 } 1057 1058 return insn | fill_scale | (ui8 & 0xff); 1059 } 1060 1061 static int64_t 1062 extract_sci8 (uint64_t insn, 1063 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1064 int *invalid ATTRIBUTE_UNUSED) 1065 { 1066 int64_t fill = insn & 0x400; 1067 int64_t scale_factor = (insn & 0x300) >> 5; 1068 int64_t value = (insn & 0xff) << scale_factor; 1069 1070 if (fill != 0) 1071 value |= ~((int64_t) 0xff << scale_factor); 1072 return value; 1073 } 1074 1075 static uint64_t 1076 insert_sci8n (uint64_t insn, 1077 int64_t value, 1078 ppc_cpu_t dialect, 1079 const char **errmsg) 1080 { 1081 return insert_sci8 (insn, -value, dialect, errmsg); 1082 } 1083 1084 static int64_t 1085 extract_sci8n (uint64_t insn, 1086 ppc_cpu_t dialect, 1087 int *invalid) 1088 { 1089 return -extract_sci8 (insn, dialect, invalid); 1090 } 1091 1092 static uint64_t 1093 insert_sd4h (uint64_t insn, 1094 int64_t value, 1095 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1096 const char **errmsg ATTRIBUTE_UNUSED) 1097 { 1098 return insn | ((value & 0x1e) << 7); 1099 } 1100 1101 static int64_t 1102 extract_sd4h (uint64_t insn, 1103 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1104 int *invalid ATTRIBUTE_UNUSED) 1105 { 1106 return ((insn >> 8) & 0xf) << 1; 1107 } 1108 1109 static uint64_t 1110 insert_sd4w (uint64_t insn, 1111 int64_t value, 1112 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1113 const char **errmsg ATTRIBUTE_UNUSED) 1114 { 1115 return insn | ((value & 0x3c) << 6); 1116 } 1117 1118 static int64_t 1119 extract_sd4w (uint64_t insn, 1120 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1121 int *invalid ATTRIBUTE_UNUSED) 1122 { 1123 return ((insn >> 8) & 0xf) << 2; 1124 } 1125 1126 static uint64_t 1127 insert_oimm (uint64_t insn, 1128 int64_t value, 1129 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1130 const char **errmsg ATTRIBUTE_UNUSED) 1131 { 1132 return insn | (((value - 1) & 0x1f) << 4); 1133 } 1134 1135 static int64_t 1136 extract_oimm (uint64_t insn, 1137 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1138 int *invalid ATTRIBUTE_UNUSED) 1139 { 1140 return ((insn >> 4) & 0x1f) + 1; 1141 } 1142 1143 /* The SH field in an MD form instruction. This is split. */ 1144 1145 static uint64_t 1146 insert_sh6 (uint64_t insn, 1147 int64_t value, 1148 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1149 const char **errmsg ATTRIBUTE_UNUSED) 1150 { 1151 /* SH6 operand in the rldixor instructions. */ 1152 if (PPC_OP (insn) == 4) 1153 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 5); 1154 else 1155 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); 1156 } 1157 1158 static int64_t 1159 extract_sh6 (uint64_t insn, 1160 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1161 int *invalid ATTRIBUTE_UNUSED) 1162 { 1163 /* SH6 operand in the rldixor instructions. */ 1164 if (PPC_OP (insn) == 4) 1165 return ((insn >> 6) & 0x1f) | ((insn << 5) & 0x20); 1166 else 1167 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); 1168 } 1169 1170 /* The SPR field in an XFX form instruction. This is flipped--the 1171 lower 5 bits are stored in the upper 5 and vice- versa. */ 1172 1173 static uint64_t 1174 insert_spr (uint64_t insn, 1175 int64_t value, 1176 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1177 const char **errmsg ATTRIBUTE_UNUSED) 1178 { 1179 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); 1180 } 1181 1182 static int64_t 1183 extract_spr (uint64_t insn, 1184 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1185 int *invalid ATTRIBUTE_UNUSED) 1186 { 1187 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); 1188 } 1189 1190 /* Some dialects have 8 SPRG registers instead of the standard 4. */ 1191 #define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405) 1192 1193 static uint64_t 1194 insert_sprg (uint64_t insn, 1195 int64_t value, 1196 ppc_cpu_t dialect, 1197 const char **errmsg) 1198 { 1199 if (value > 7 1200 || (value > 3 && (dialect & ALLOW8_SPRG) == 0)) 1201 *errmsg = _("invalid sprg number"); 1202 1203 /* If this is mfsprg4..7 then use spr 260..263 which can be read in 1204 user mode. Anything else must use spr 272..279. */ 1205 if (value <= 3 || (insn & 0x100) != 0) 1206 value |= 0x10; 1207 1208 return insn | ((value & 0x17) << 16); 1209 } 1210 1211 static int64_t 1212 extract_sprg (uint64_t insn, 1213 ppc_cpu_t dialect, 1214 int *invalid) 1215 { 1216 uint64_t val = (insn >> 16) & 0x1f; 1217 1218 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279 1219 If not BOOKE, 405 or VLE, then both use only 272..275. */ 1220 if ((val - 0x10 > 3 && (dialect & ALLOW8_SPRG) == 0) 1221 || (val - 0x10 > 7 && (insn & 0x100) != 0) 1222 || val <= 3 1223 || (val & 8) != 0) 1224 *invalid = 1; 1225 return val & 7; 1226 } 1227 1228 /* The TBR field in an XFX instruction. This is just like SPR, but it 1229 is optional. */ 1230 1231 static uint64_t 1232 insert_tbr (uint64_t insn, 1233 int64_t value, 1234 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1235 const char **errmsg) 1236 { 1237 if (value != 268 && value != 269) 1238 *errmsg = _("invalid tbr number"); 1239 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); 1240 } 1241 1242 static int64_t 1243 extract_tbr (uint64_t insn, 1244 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1245 int *invalid) 1246 { 1247 int64_t ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); 1248 if (ret != 268 && ret != 269) 1249 *invalid = 1; 1250 return ret; 1251 } 1252 1253 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */ 1254 1255 static uint64_t 1256 insert_xt6 (uint64_t insn, 1257 int64_t value, 1258 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1259 const char **errmsg ATTRIBUTE_UNUSED) 1260 { 1261 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5); 1262 } 1263 1264 static int64_t 1265 extract_xt6 (uint64_t insn, 1266 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1267 int *invalid ATTRIBUTE_UNUSED) 1268 { 1269 return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f); 1270 } 1271 1272 /* The XT and XS fields in an DQ form VSX instruction. This is split. */ 1273 static uint64_t 1274 insert_xtq6 (uint64_t insn, 1275 int64_t value, 1276 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1277 const char **errmsg ATTRIBUTE_UNUSED) 1278 { 1279 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 2); 1280 } 1281 1282 static int64_t 1283 extract_xtq6 (uint64_t insn, 1284 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1285 int *invalid ATTRIBUTE_UNUSED) 1286 { 1287 return ((insn << 2) & 0x20) | ((insn >> 21) & 0x1f); 1288 } 1289 1290 /* The XA field in an XX3 form instruction. This is split. */ 1291 1292 static uint64_t 1293 insert_xa6 (uint64_t insn, 1294 int64_t value, 1295 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1296 const char **errmsg ATTRIBUTE_UNUSED) 1297 { 1298 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3); 1299 } 1300 1301 static int64_t 1302 extract_xa6 (uint64_t insn, 1303 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1304 int *invalid ATTRIBUTE_UNUSED) 1305 { 1306 return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f); 1307 } 1308 1309 /* The XB field in an XX3 form instruction. This is split. */ 1310 1311 static uint64_t 1312 insert_xb6 (uint64_t insn, 1313 int64_t value, 1314 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1315 const char **errmsg ATTRIBUTE_UNUSED) 1316 { 1317 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); 1318 } 1319 1320 static int64_t 1321 extract_xb6 (uint64_t insn, 1322 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1323 int *invalid ATTRIBUTE_UNUSED) 1324 { 1325 return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f); 1326 } 1327 1328 /* The XA and XB fields in an XX3 form instruction when they must be the same. 1329 This is used for extended mnemonics like xvmovdp. The extraction function 1330 enforces that the fields are the same. */ 1331 1332 static uint64_t 1333 insert_xab6 (uint64_t insn, 1334 int64_t value, 1335 ppc_cpu_t dialect, 1336 const char **errmsg) 1337 { 1338 return insert_xa6 (insn, value, dialect, errmsg) 1339 | insert_xb6 (insn, value, dialect, errmsg); 1340 } 1341 1342 static int64_t 1343 extract_xab6 (uint64_t insn, 1344 ppc_cpu_t dialect, 1345 int *invalid) 1346 { 1347 int64_t xa6 = extract_xa6 (insn, dialect, invalid); 1348 int64_t xb6 = extract_xb6 (insn, dialect, invalid); 1349 1350 if (xa6 != xb6) 1351 *invalid = 1; 1352 return xa6; 1353 } 1354 1355 /* The XC field in an XX4 form instruction. This is split. */ 1356 1357 static uint64_t 1358 insert_xc6 (uint64_t insn, 1359 int64_t value, 1360 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1361 const char **errmsg ATTRIBUTE_UNUSED) 1362 { 1363 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2); 1364 } 1365 1366 static int64_t 1367 extract_xc6 (uint64_t insn, 1368 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1369 int *invalid ATTRIBUTE_UNUSED) 1370 { 1371 return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f); 1372 } 1373 1374 static uint64_t 1375 insert_dm (uint64_t insn, 1376 int64_t value, 1377 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1378 const char **errmsg) 1379 { 1380 if (value != 0 && value != 1) 1381 *errmsg = _("invalid constant"); 1382 return insn | (((value) ? 3 : 0) << 8); 1383 } 1384 1385 static int64_t 1386 extract_dm (uint64_t insn, 1387 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1388 int *invalid) 1389 { 1390 int64_t value = (insn >> 8) & 3; 1391 if (value != 0 && value != 3) 1392 *invalid = 1; 1393 return (value) ? 1 : 0; 1394 } 1395 1396 /* The VLESIMM field in an I16A form instruction. This is split. */ 1397 1398 static uint64_t 1399 insert_vlesi (uint64_t insn, 1400 int64_t value, 1401 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1402 const char **errmsg ATTRIBUTE_UNUSED) 1403 { 1404 return insn | ((value & 0xf800) << 10) | (value & 0x7ff); 1405 } 1406 1407 static int64_t 1408 extract_vlesi (uint64_t insn, 1409 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1410 int *invalid ATTRIBUTE_UNUSED) 1411 { 1412 int64_t value = ((insn >> 10) & 0xf800) | (insn & 0x7ff); 1413 value = (value ^ 0x8000) - 0x8000; 1414 return value; 1415 } 1416 1417 static uint64_t 1418 insert_vlensi (uint64_t insn, 1419 int64_t value, 1420 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1421 const char **errmsg ATTRIBUTE_UNUSED) 1422 { 1423 value = -value; 1424 return insn | ((value & 0xf800) << 10) | (value & 0x7ff); 1425 } 1426 static int64_t 1427 extract_vlensi (uint64_t insn, 1428 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1429 int *invalid ATTRIBUTE_UNUSED) 1430 { 1431 int64_t value = ((insn >> 10) & 0xf800) | (insn & 0x7ff); 1432 value = (value ^ 0x8000) - 0x8000; 1433 /* Don't use for disassembly. */ 1434 *invalid = 1; 1435 return -value; 1436 } 1437 1438 /* The VLEUIMM field in an I16A form instruction. This is split. */ 1439 1440 static uint64_t 1441 insert_vleui (uint64_t insn, 1442 int64_t value, 1443 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1444 const char **errmsg ATTRIBUTE_UNUSED) 1445 { 1446 return insn | ((value & 0xf800) << 10) | (value & 0x7ff); 1447 } 1448 1449 static int64_t 1450 extract_vleui (uint64_t insn, 1451 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1452 int *invalid ATTRIBUTE_UNUSED) 1453 { 1454 return ((insn >> 10) & 0xf800) | (insn & 0x7ff); 1455 } 1456 1457 /* The VLEUIMML field in an I16L form instruction. This is split. */ 1458 1459 static uint64_t 1460 insert_vleil (uint64_t insn, 1461 int64_t value, 1462 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1463 const char **errmsg ATTRIBUTE_UNUSED) 1464 { 1465 return insn | ((value & 0xf800) << 5) | (value & 0x7ff); 1466 } 1467 1468 static int64_t 1469 extract_vleil (uint64_t insn, 1470 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1471 int *invalid ATTRIBUTE_UNUSED) 1472 { 1473 return ((insn >> 5) & 0xf800) | (insn & 0x7ff); 1474 } 1475 1476 static uint64_t 1477 insert_evuimm1_ex0 (uint64_t insn, 1478 int64_t value, 1479 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1480 const char **errmsg) 1481 { 1482 if (value > 0 && value <= 0x1f) 1483 return insn | ((value & 0x1f) << 11); 1484 else 1485 { 1486 *errmsg = _("UIMM = 00000 is illegal"); 1487 return 0; 1488 } 1489 } 1490 1491 static int64_t 1492 extract_evuimm1_ex0 (uint64_t insn, 1493 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1494 int *invalid) 1495 { 1496 int64_t value = ((insn >> 11) & 0x1f); 1497 if (value == 0) 1498 *invalid = 1; 1499 1500 return value; 1501 } 1502 1503 static uint64_t 1504 insert_evuimm2_ex0 (uint64_t insn, 1505 int64_t value, 1506 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1507 const char **errmsg) 1508 { 1509 if (value > 0 && value <= 0x3e) 1510 return insn | ((value & 0x3e) << 10); 1511 else 1512 { 1513 *errmsg = _("UIMM = 00000 is illegal"); 1514 return 0; 1515 } 1516 } 1517 1518 static int64_t 1519 extract_evuimm2_ex0 (uint64_t insn, 1520 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1521 int *invalid) 1522 { 1523 int64_t value = ((insn >> 10) & 0x3e); 1524 if (value == 0) 1525 *invalid = 1; 1526 1527 return value; 1528 } 1529 1530 static uint64_t 1531 insert_evuimm4_ex0 (uint64_t insn, 1532 int64_t value, 1533 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1534 const char **errmsg) 1535 { 1536 if (value > 0 && value <= 0x7c) 1537 return insn | ((value & 0x7c) << 9); 1538 else 1539 { 1540 *errmsg = _("UIMM = 00000 is illegal"); 1541 return 0; 1542 } 1543 } 1544 1545 static int64_t 1546 extract_evuimm4_ex0 (uint64_t insn, 1547 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1548 int *invalid) 1549 { 1550 int64_t value = ((insn >> 9) & 0x7c); 1551 if (value == 0) 1552 *invalid = 1; 1553 1554 return value; 1555 } 1556 1557 static uint64_t 1558 insert_evuimm8_ex0 (uint64_t insn, 1559 int64_t value, 1560 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1561 const char **errmsg) 1562 { 1563 if (value > 0 && value <= 0xf8) 1564 return insn | ((value & 0xf8) << 8); 1565 else 1566 { 1567 *errmsg = _("UIMM = 00000 is illegal"); 1568 return 0; 1569 } 1570 } 1571 1572 static int64_t 1573 extract_evuimm8_ex0 (uint64_t insn, 1574 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1575 int *invalid) 1576 { 1577 int64_t value = ((insn >> 8) & 0xf8); 1578 if (value == 0) 1579 *invalid = 1; 1580 1581 return value; 1582 } 1583 1584 static uint64_t 1585 insert_evuimm_lt8 (uint64_t insn, 1586 int64_t value, 1587 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1588 const char **errmsg) 1589 { 1590 if (value >= 0 && value <= 7) 1591 return insn | ((value & 0x7) << 11); 1592 else 1593 { 1594 *errmsg = _("UIMM values >7 are illegal"); 1595 return 0; 1596 } 1597 } 1598 1599 static int64_t 1600 extract_evuimm_lt8 (uint64_t insn, 1601 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1602 int *invalid) 1603 { 1604 int64_t value = ((insn >> 11) & 0x1f); 1605 if (value > 7) 1606 *invalid = 1; 1607 1608 return value; 1609 } 1610 1611 static uint64_t 1612 insert_evuimm_lt16 (uint64_t insn, 1613 int64_t value, 1614 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1615 const char **errmsg) 1616 { 1617 if (value >= 0 && value <= 15) 1618 return insn | ((value & 0xf) << 11); 1619 else 1620 { 1621 *errmsg = _("UIMM values >15 are illegal"); 1622 return 0; 1623 } 1624 } 1625 1626 static int64_t 1627 extract_evuimm_lt16 (uint64_t insn, 1628 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1629 int *invalid) 1630 { 1631 int64_t value = ((insn >> 11) & 0x1f); 1632 if (value > 15) 1633 *invalid = 1; 1634 1635 return value; 1636 } 1637 1638 static uint64_t 1639 insert_rD_rS_even (uint64_t insn, 1640 int64_t value, 1641 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1642 const char **errmsg) 1643 { 1644 if ((value & 0x1) == 0) 1645 return insn | ((value & 0x1e) << 21); 1646 else 1647 { 1648 *errmsg = _("GPR odd is illegal"); 1649 return 0; 1650 } 1651 } 1652 1653 static int64_t 1654 extract_rD_rS_even (uint64_t insn, 1655 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1656 int *invalid) 1657 { 1658 int64_t value = ((insn >> 21) & 0x1f); 1659 if ((value & 0x1) != 0) 1660 *invalid = 1; 1661 1662 return value; 1663 } 1664 1665 static uint64_t 1666 insert_off_lsp (uint64_t insn, 1667 int64_t value, 1668 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1669 const char **errmsg) 1670 { 1671 if (value > 0 && value <= 0x3) 1672 return insn | (value & 0x3); 1673 else 1674 { 1675 *errmsg = _("invalid offset"); 1676 return 0; 1677 } 1678 } 1679 1680 static int64_t 1681 extract_off_lsp (uint64_t insn, 1682 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1683 int *invalid) 1684 { 1685 int64_t value = (insn & 0x3); 1686 if (value == 0) 1687 *invalid = 1; 1688 1689 return value; 1690 } 1691 1692 static uint64_t 1693 insert_off_spe2 (uint64_t insn, 1694 int64_t value, 1695 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1696 const char **errmsg) 1697 { 1698 if (value > 0 && value <= 0x7) 1699 return insn | (value & 0x7); 1700 else 1701 { 1702 *errmsg = _("invalid offset"); 1703 return 0; 1704 } 1705 } 1706 1707 static int64_t 1708 extract_off_spe2 (uint64_t insn, 1709 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1710 int *invalid) 1711 { 1712 int64_t value = (insn & 0x7); 1713 if (value == 0) 1714 *invalid = 1; 1715 1716 return value; 1717 } 1718 1719 static uint64_t 1720 insert_Ddd (uint64_t insn, 1721 int64_t value, 1722 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1723 const char **errmsg) 1724 { 1725 if (value >= 0 && value <= 0x7) 1726 return insn | ((value & 0x3) << 11) | ((value & 0x4) >> 2); 1727 else 1728 { 1729 *errmsg = _("invalid Ddd value"); 1730 return 0; 1731 } 1732 } 1733 1734 static int64_t 1735 extract_Ddd (uint64_t insn, 1736 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1737 int *invalid ATTRIBUTE_UNUSED) 1738 { 1739 return ((insn >> 11) & 0x3) | ((insn << 2) & 0x4); 1740 } 1741 1742 /* The operands table. 1744 1745 The fields are bitm, shift, insert, extract, flags. 1746 1747 We used to put parens around the various additions, like the one 1748 for BA just below. However, that caused trouble with feeble 1749 compilers with a limit on depth of a parenthesized expression, like 1750 (reportedly) the compiler in Microsoft Developer Studio 5. So we 1751 omit the parens, since the macros are never used in a context where 1752 the addition will be ambiguous. */ 1753 1754 const struct powerpc_operand powerpc_operands[] = 1755 { 1756 /* The zero index is used to indicate the end of the list of 1757 operands. */ 1758 #define UNUSED 0 1759 { 0, 0, NULL, NULL, 0 }, 1760 1761 /* The BA field in an XL form instruction. */ 1762 #define BA UNUSED + 1 1763 /* The BI field in a B form or XL form instruction. */ 1764 #define BI BA 1765 #define BI_MASK (0x1f << 16) 1766 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT }, 1767 1768 /* The BT, BA and BB fields in a XL form instruction when they must all 1769 be the same. */ 1770 #define BTAB BA + 1 1771 { 0x1f, 21, insert_btab, extract_btab, PPC_OPERAND_CR_BIT }, 1772 1773 /* The BB field in an XL form instruction. */ 1774 #define BB BTAB + 1 1775 #define BB_MASK (0x1f << 11) 1776 { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR_BIT }, 1777 1778 /* The BA and BB fields in a XL form instruction when they must be 1779 the same. */ 1780 #define BAB BB + 1 1781 { 0x1f, 16, insert_bab, extract_bab, PPC_OPERAND_CR_BIT }, 1782 1783 /* The VRA and VRB fields in a VX form instruction when they must be the same. 1784 This is used for extended mnemonics like vmr. */ 1785 #define VAB BAB + 1 1786 { 0x1f, 16, insert_bab, extract_bab, PPC_OPERAND_VR }, 1787 1788 /* The RA and RB fields in a VX form instruction when they must be the same. 1789 This is used for extended mnemonics like evmr. */ 1790 #define RAB VAB + 1 1791 { 0x1f, 16, insert_bab, extract_bab, PPC_OPERAND_GPR }, 1792 1793 /* The BD field in a B form instruction. The lower two bits are 1794 forced to zero. */ 1795 #define BD RAB + 1 1796 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 1797 1798 /* The BD field in a B form instruction when absolute addressing is 1799 used. */ 1800 #define BDA BD + 1 1801 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 1802 1803 /* The BD field in a B form instruction when the - modifier is used. 1804 This sets the y bit of the BO field appropriately. */ 1805 #define BDM BDA + 1 1806 { 0xfffc, 0, insert_bdm, extract_bdm, 1807 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 1808 1809 /* The BD field in a B form instruction when the - modifier is used 1810 and absolute address is used. */ 1811 #define BDMA BDM + 1 1812 { 0xfffc, 0, insert_bdm, extract_bdm, 1813 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 1814 1815 /* The BD field in a B form instruction when the + modifier is used. 1816 This sets the y bit of the BO field appropriately. */ 1817 #define BDP BDMA + 1 1818 { 0xfffc, 0, insert_bdp, extract_bdp, 1819 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 1820 1821 /* The BD field in a B form instruction when the + modifier is used 1822 and absolute addressing is used. */ 1823 #define BDPA BDP + 1 1824 { 0xfffc, 0, insert_bdp, extract_bdp, 1825 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 1826 1827 /* The BF field in an X or XL form instruction. */ 1828 #define BF BDPA + 1 1829 /* The CRFD field in an X form instruction. */ 1830 #define CRFD BF 1831 /* The CRD field in an XL form instruction. */ 1832 #define CRD BF 1833 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG }, 1834 1835 /* The BF field in an X or XL form instruction. */ 1836 #define BFF BF + 1 1837 { 0x7, 23, NULL, NULL, 0 }, 1838 1839 /* An optional BF field. This is used for comparison instructions, 1840 in which an omitted BF field is taken as zero. */ 1841 #define OBF BFF + 1 1842 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, 1843 1844 /* The BFA field in an X or XL form instruction. */ 1845 #define BFA OBF + 1 1846 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG }, 1847 1848 /* The BO field in a B form instruction. Certain values are 1849 illegal. */ 1850 #define BO BFA + 1 1851 #define BO_MASK (0x1f << 21) 1852 { 0x1f, 21, insert_bo, extract_bo, 0 }, 1853 1854 /* The BO field in a B form instruction when the + or - modifier is 1855 used. This is like the BO field, but it must be even. */ 1856 #define BOE BO + 1 1857 { 0x1e, 21, insert_boe, extract_boe, 0 }, 1858 1859 /* The RM field in an X form instruction. */ 1860 #define RM BOE + 1 1861 #define DD RM 1862 { 0x3, 11, NULL, NULL, 0 }, 1863 1864 #define BH RM + 1 1865 { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, 1866 1867 /* The BT field in an X or XL form instruction. */ 1868 #define BT BH + 1 1869 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT }, 1870 1871 /* The BI16 field in a BD8 form instruction. */ 1872 #define BI16 BT + 1 1873 { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT }, 1874 1875 /* The BI32 field in a BD15 form instruction. */ 1876 #define BI32 BI16 + 1 1877 { 0xf, 16, NULL, NULL, PPC_OPERAND_CR_BIT }, 1878 1879 /* The BO32 field in a BD15 form instruction. */ 1880 #define BO32 BI32 + 1 1881 { 0x3, 20, NULL, NULL, 0 }, 1882 1883 /* The B8 field in a BD8 form instruction. */ 1884 #define B8 BO32 + 1 1885 { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 1886 1887 /* The B15 field in a BD15 form instruction. The lowest bit is 1888 forced to zero. */ 1889 #define B15 B8 + 1 1890 { 0xfffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 1891 1892 /* The B24 field in a BD24 form instruction. The lowest bit is 1893 forced to zero. */ 1894 #define B24 B15 + 1 1895 { 0x1fffffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 1896 1897 /* The condition register number portion of the BI field in a B form 1898 or XL form instruction. This is used for the extended 1899 conditional branch mnemonics, which set the lower two bits of the 1900 BI field. This field is optional. */ 1901 #define CR B24 + 1 1902 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, 1903 1904 /* The CRB field in an X form instruction. */ 1905 #define CRB CR + 1 1906 /* The MB field in an M form instruction. */ 1907 #define MB CRB 1908 #define MB_MASK (0x1f << 6) 1909 { 0x1f, 6, NULL, NULL, 0 }, 1910 1911 /* The CRD32 field in an XL form instruction. */ 1912 #define CRD32 CRB + 1 1913 { 0x3, 21, NULL, NULL, PPC_OPERAND_CR_REG }, 1914 1915 /* The CRFS field in an X form instruction. */ 1916 #define CRFS CRD32 + 1 1917 { 0x7, 0, NULL, NULL, PPC_OPERAND_CR_REG }, 1918 1919 #define CRS CRFS + 1 1920 { 0x3, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, 1921 1922 /* The CT field in an X form instruction. */ 1923 #define CT CRS + 1 1924 /* The MO field in an mbar instruction. */ 1925 #define MO CT 1926 { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 1927 1928 /* The D field in a D form instruction. This is a displacement off 1929 a register, and implies that the next operand is a register in 1930 parentheses. */ 1931 #define D CT + 1 1932 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, 1933 1934 /* The D8 field in a D form instruction. This is a displacement off 1935 a register, and implies that the next operand is a register in 1936 parentheses. */ 1937 #define D8 D + 1 1938 { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, 1939 1940 /* The DCMX field in an X form instruction. */ 1941 #define DCMX D8 + 1 1942 { 0x7f, 16, NULL, NULL, 0 }, 1943 1944 /* The split DCMX field in an X form instruction. */ 1945 #define DCMXS DCMX + 1 1946 { 0x7f, PPC_OPSHIFT_INV, insert_dcmxs, extract_dcmxs, 0 }, 1947 1948 /* The DQ field in a DQ form instruction. This is like D, but the 1949 lower four bits are forced to zero. */ 1950 #define DQ DCMXS + 1 1951 { 0xfff0, 0, NULL, NULL, 1952 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ }, 1953 1954 /* The DS field in a DS form instruction. This is like D, but the 1955 lower two bits are forced to zero. */ 1956 #define DS DQ + 1 1957 { 0xfffc, 0, NULL, NULL, 1958 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS }, 1959 1960 /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits 1961 unsigned imediate */ 1962 #define DUIS DS + 1 1963 #define BHRBE DUIS 1964 { 0x3ff, 11, NULL, NULL, 0 }, 1965 1966 /* The split D field in a DX form instruction. */ 1967 #define DXD DUIS + 1 1968 { 0xffff, PPC_OPSHIFT_INV, insert_dxd, extract_dxd, 1969 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT}, 1970 1971 /* The split ND field in a DX form instruction. 1972 This is the same as the DX field, only negated. */ 1973 #define NDXD DXD + 1 1974 { 0xffff, PPC_OPSHIFT_INV, insert_dxdn, extract_dxdn, 1975 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT}, 1976 1977 /* The E field in a wrteei instruction. */ 1978 /* And the W bit in the pair singles instructions. */ 1979 /* And the ST field in a VX form instruction. */ 1980 #define E NDXD + 1 1981 #define PSW E 1982 #define ST E 1983 { 0x1, 15, NULL, NULL, 0 }, 1984 1985 /* The FL1 field in a POWER SC form instruction. */ 1986 #define FL1 E + 1 1987 /* The U field in an X form instruction. */ 1988 #define U FL1 1989 { 0xf, 12, NULL, NULL, 0 }, 1990 1991 /* The FL2 field in a POWER SC form instruction. */ 1992 #define FL2 FL1 + 1 1993 { 0x7, 2, NULL, NULL, 0 }, 1994 1995 /* The FLM field in an XFL form instruction. */ 1996 #define FLM FL2 + 1 1997 { 0xff, 17, NULL, NULL, 0 }, 1998 1999 /* The FRA field in an X or A form instruction. */ 2000 #define FRA FLM + 1 2001 #define FRA_MASK (0x1f << 16) 2002 { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR }, 2003 2004 /* The FRAp field of DFP instructions. */ 2005 #define FRAp FRA + 1 2006 { 0x1e, 16, NULL, NULL, PPC_OPERAND_FPR }, 2007 2008 /* The FRB field in an X or A form instruction. */ 2009 #define FRB FRAp + 1 2010 #define FRB_MASK (0x1f << 11) 2011 { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR }, 2012 2013 /* The FRBp field of DFP instructions. */ 2014 #define FRBp FRB + 1 2015 { 0x1e, 11, NULL, NULL, PPC_OPERAND_FPR }, 2016 2017 /* The FRC field in an A form instruction. */ 2018 #define FRC FRBp + 1 2019 #define FRC_MASK (0x1f << 6) 2020 { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR }, 2021 2022 /* The FRS field in an X form instruction or the FRT field in a D, X 2023 or A form instruction. */ 2024 #define FRS FRC + 1 2025 #define FRT FRS 2026 { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR }, 2027 2028 /* The FRSp field of stfdp or the FRTp field of lfdp and DFP 2029 instructions. */ 2030 #define FRSp FRS + 1 2031 #define FRTp FRSp 2032 { 0x1e, 21, NULL, NULL, PPC_OPERAND_FPR }, 2033 2034 /* The FXM field in an XFX instruction. */ 2035 #define FXM FRSp + 1 2036 { 0xff, 12, insert_fxm, extract_fxm, 0 }, 2037 2038 /* Power4 version for mfcr. */ 2039 #define FXM4 FXM + 1 2040 { 0xff, 12, insert_fxm, extract_fxm, 2041 PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE}, 2042 /* If the FXM4 operand is ommitted, use the sentinel value -1. */ 2043 { -1, -1, NULL, NULL, 0}, 2044 2045 /* The IMM20 field in an LI instruction. */ 2046 #define IMM20 FXM4 + 2 2047 { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED}, 2048 2049 /* The L field in a D or X form instruction. */ 2050 #define L IMM20 + 1 2051 { 0x1, 21, NULL, NULL, 0 }, 2052 2053 /* The optional L field in tlbie and tlbiel instructions. */ 2054 #define LOPT L + 1 2055 /* The R field in a HTM X form instruction. */ 2056 #define HTM_R LOPT 2057 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 2058 2059 /* The optional (for 32-bit) L field in cmp[l][i] instructions. */ 2060 #define L32OPT LOPT + 1 2061 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL32 }, 2062 2063 /* The L field in dcbf instruction. */ 2064 #define L2OPT L32OPT + 1 2065 { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 2066 2067 /* The LEV field in a POWER SVC / POWER9 SCV form instruction. */ 2068 #define SVC_LEV L2OPT + 1 2069 { 0x7f, 5, NULL, NULL, 0 }, 2070 2071 /* The LEV field in an SC form instruction. */ 2072 #define LEV SVC_LEV + 1 2073 { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL }, 2074 2075 /* The LI field in an I form instruction. The lower two bits are 2076 forced to zero. */ 2077 #define LI LEV + 1 2078 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 2079 2080 /* The LI field in an I form instruction when used as an absolute 2081 address. */ 2082 #define LIA LI + 1 2083 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 2084 2085 /* The LS or WC field in an X (sync or wait) form instruction. */ 2086 #define LS LIA + 1 2087 #define WC LS 2088 { 0x3, 21, insert_ls, extract_ls, PPC_OPERAND_OPTIONAL }, 2089 2090 /* The ME field in an M form instruction. */ 2091 #define ME LS + 1 2092 #define ME_MASK (0x1f << 1) 2093 { 0x1f, 1, NULL, NULL, 0 }, 2094 2095 /* The MB and ME fields in an M form instruction expressed a single 2096 operand which is a bitmask indicating which bits to select. This 2097 is a two operand form using PPC_OPERAND_NEXT. See the 2098 description in opcode/ppc.h for what this means. */ 2099 #define MBE ME + 1 2100 { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT }, 2101 { -1, 0, insert_mbe, extract_mbe, 0 }, 2102 2103 /* The MB or ME field in an MD or MDS form instruction. The high 2104 bit is wrapped to the low end. */ 2105 #define MB6 MBE + 2 2106 #define ME6 MB6 2107 #define MB6_MASK (0x3f << 5) 2108 { 0x3f, 5, insert_mb6, extract_mb6, 0 }, 2109 2110 /* The NB field in an X form instruction. The value 32 is stored as 2111 0. */ 2112 #define NB MB6 + 1 2113 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 }, 2114 2115 /* The NBI field in an lswi instruction, which has special value 2116 restrictions. The value 32 is stored as 0. */ 2117 #define NBI NB + 1 2118 { 0x1f, 11, insert_nbi, extract_nb, PPC_OPERAND_PLUS1 }, 2119 2120 /* The NSI field in a D form instruction. This is the same as the 2121 SI field, only negated. */ 2122 #define NSI NBI + 1 2123 { 0xffff, 0, insert_nsi, extract_nsi, 2124 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, 2125 2126 /* The NSI field in a D form instruction when we accept a wide range 2127 of positive values. */ 2128 #define NSISIGNOPT NSI + 1 2129 { 0xffff, 0, insert_nsi, extract_nsi, 2130 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, 2131 2132 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */ 2133 #define RA NSISIGNOPT + 1 2134 #define RA_MASK (0x1f << 16) 2135 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR }, 2136 2137 /* As above, but 0 in the RA field means zero, not r0. */ 2138 #define RA0 RA + 1 2139 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 }, 2140 2141 /* The RA field in the DQ form lq or an lswx instruction, which have 2142 special value restrictions. */ 2143 #define RAQ RA0 + 1 2144 #define RAX RAQ 2145 { 0x1f, 16, insert_raq, extract_raq, PPC_OPERAND_GPR_0 }, 2146 2147 /* The RA field in a D or X form instruction which is an updating 2148 load, which means that the RA field may not be zero and may not 2149 equal the RT field. */ 2150 #define RAL RAQ + 1 2151 { 0x1f, 16, insert_ral, extract_ral, PPC_OPERAND_GPR_0 }, 2152 2153 /* The RA field in an lmw instruction, which has special value 2154 restrictions. */ 2155 #define RAM RAL + 1 2156 { 0x1f, 16, insert_ram, extract_ram, PPC_OPERAND_GPR_0 }, 2157 2158 /* The RA field in a D or X form instruction which is an updating 2159 store or an updating floating point load, which means that the RA 2160 field may not be zero. */ 2161 #define RAS RAM + 1 2162 { 0x1f, 16, insert_ras, extract_ras, PPC_OPERAND_GPR_0 }, 2163 2164 /* The RA field of the tlbwe, dccci and iccci instructions, 2165 which are optional. */ 2166 #define RAOPT RAS + 1 2167 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, 2168 2169 /* The RB field in an X, XO, M, or MDS form instruction. */ 2170 #define RB RAOPT + 1 2171 #define RB_MASK (0x1f << 11) 2172 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR }, 2173 2174 /* The RS and RB fields in an X form instruction when they must be the same. 2175 This is used for extended mnemonics like mr. */ 2176 #define RSB RB + 1 2177 { 0x1f, 11, insert_rsb, extract_rsb, PPC_OPERAND_GPR }, 2178 2179 /* The RB field in an lswx instruction, which has special value 2180 restrictions. */ 2181 #define RBX RSB + 1 2182 { 0x1f, 11, insert_rbx, extract_rbx, PPC_OPERAND_GPR }, 2183 2184 /* The RB field of the dccci and iccci instructions, which are optional. */ 2185 #define RBOPT RBX + 1 2186 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, 2187 2188 /* The RC register field in an maddld, maddhd or maddhdu instruction. */ 2189 #define RC RBOPT + 1 2190 { 0x1f, 6, NULL, NULL, PPC_OPERAND_GPR }, 2191 2192 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form 2193 instruction or the RT field in a D, DS, X, XFX or XO form 2194 instruction. */ 2195 #define RS RC + 1 2196 #define RT RS 2197 #define RT_MASK (0x1f << 21) 2198 #define RD RS 2199 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR }, 2200 2201 #define RD_EVEN RS + 1 2202 #define RS_EVEN RD_EVEN 2203 { 0x1f, 21, insert_rD_rS_even, extract_rD_rS_even, PPC_OPERAND_GPR }, 2204 2205 /* The RS and RT fields of the DS form stq and DQ form lq instructions, 2206 which have special value restrictions. */ 2207 #define RSQ RS_EVEN + 1 2208 #define RTQ RSQ 2209 #define Q_MASK (1 << 21) 2210 { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR }, 2211 2212 /* The RS field of the tlbwe instruction, which is optional. */ 2213 #define RSO RSQ + 1 2214 #define RTO RSO 2215 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, 2216 2217 /* The RX field of the SE_RR form instruction. */ 2218 #define RX RSO + 1 2219 { 0x1f, PPC_OPSHIFT_INV, insert_rx, extract_rx, PPC_OPERAND_GPR }, 2220 2221 /* The ARX field of the SE_RR form instruction. */ 2222 #define ARX RX + 1 2223 { 0x1f, PPC_OPSHIFT_INV, insert_arx, extract_arx, PPC_OPERAND_GPR }, 2224 2225 /* The RY field of the SE_RR form instruction. */ 2226 #define RY ARX + 1 2227 #define RZ RY 2228 { 0x1f, PPC_OPSHIFT_INV, insert_ry, extract_ry, PPC_OPERAND_GPR }, 2229 2230 /* The ARY field of the SE_RR form instruction. */ 2231 #define ARY RY + 1 2232 { 0x1f, PPC_OPSHIFT_INV, insert_ary, extract_ary, PPC_OPERAND_GPR }, 2233 2234 /* The SCLSCI8 field in a D form instruction. */ 2235 #define SCLSCI8 ARY + 1 2236 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8, extract_sci8, 0 }, 2237 2238 /* The SCLSCI8N field in a D form instruction. This is the same as the 2239 SCLSCI8 field, only negated. */ 2240 #define SCLSCI8N SCLSCI8 + 1 2241 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n, 2242 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, 2243 2244 /* The SD field of the SD4 form instruction. */ 2245 #define SE_SD SCLSCI8N + 1 2246 { 0xf, 8, NULL, NULL, PPC_OPERAND_PARENS }, 2247 2248 /* The SD field of the SD4 form instruction, for halfword. */ 2249 #define SE_SDH SE_SD + 1 2250 { 0x1e, PPC_OPSHIFT_INV, insert_sd4h, extract_sd4h, PPC_OPERAND_PARENS }, 2251 2252 /* The SD field of the SD4 form instruction, for word. */ 2253 #define SE_SDW SE_SDH + 1 2254 { 0x3c, PPC_OPSHIFT_INV, insert_sd4w, extract_sd4w, PPC_OPERAND_PARENS }, 2255 2256 /* The SH field in an X or M form instruction. */ 2257 #define SH SE_SDW + 1 2258 #define SH_MASK (0x1f << 11) 2259 /* The other UIMM field in a EVX form instruction. */ 2260 #define EVUIMM SH 2261 /* The FC field in an atomic X form instruction. */ 2262 #define FC SH 2263 { 0x1f, 11, NULL, NULL, 0 }, 2264 2265 #define EVUIMM_LT8 SH + 1 2266 { 0x1f, 11, insert_evuimm_lt8, extract_evuimm_lt8, 0 }, 2267 2268 #define EVUIMM_LT16 EVUIMM_LT8 + 1 2269 { 0x1f, 11, insert_evuimm_lt16, extract_evuimm_lt16, 0 }, 2270 2271 /* The SI field in a HTM X form instruction. */ 2272 #define HTM_SI EVUIMM_LT16 + 1 2273 { 0x1f, 11, NULL, NULL, PPC_OPERAND_SIGNED }, 2274 2275 /* The SH field in an MD form instruction. This is split. */ 2276 #define SH6 HTM_SI + 1 2277 #define SH6_MASK ((0x1f << 11) | (1 << 1)) 2278 { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 }, 2279 2280 /* The SH field of some variants of the tlbre and tlbwe 2281 instructions, and the ELEV field of the e_sc instruction. */ 2282 #define SHO SH6 + 1 2283 #define ELEV SHO 2284 { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, 2285 2286 /* The SI field in a D form instruction. */ 2287 #define SI SHO + 1 2288 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED }, 2289 2290 /* The SI field in a D form instruction when we accept a wide range 2291 of positive values. */ 2292 #define SISIGNOPT SI + 1 2293 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, 2294 2295 /* The SI8 field in a D form instruction. */ 2296 #define SI8 SISIGNOPT + 1 2297 { 0xff, 0, NULL, NULL, PPC_OPERAND_SIGNED }, 2298 2299 /* The SPR field in an XFX form instruction. This is flipped--the 2300 lower 5 bits are stored in the upper 5 and vice- versa. */ 2301 #define SPR SI8 + 1 2302 #define PMR SPR 2303 #define TMR SPR 2304 #define SPR_MASK (0x3ff << 11) 2305 { 0x3ff, 11, insert_spr, extract_spr, PPC_OPERAND_SPR }, 2306 2307 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ 2308 #define SPRBAT SPR + 1 2309 #define SPRBAT_MASK (0x3 << 17) 2310 { 0x3, 17, NULL, NULL, 0 }, 2311 2312 /* The SPRG register number in an XFX form m[ft]sprg instruction. */ 2313 #define SPRG SPRBAT + 1 2314 { 0x1f, 16, insert_sprg, extract_sprg, PPC_OPERAND_SPR }, 2315 2316 /* The SR field in an X form instruction. */ 2317 #define SR SPRG + 1 2318 /* The 4-bit UIMM field in a VX form instruction. */ 2319 #define UIMM4 SR 2320 { 0xf, 16, NULL, NULL, 0 }, 2321 2322 /* The STRM field in an X AltiVec form instruction. */ 2323 #define STRM SR + 1 2324 /* The T field in a tlbilx form instruction. */ 2325 #define T STRM 2326 /* The L field in wclr instructions. */ 2327 #define L2 STRM 2328 { 0x3, 21, NULL, NULL, 0 }, 2329 2330 /* The ESYNC field in an X (sync) form instruction. */ 2331 #define ESYNC STRM + 1 2332 { 0xf, 16, insert_esync, extract_esync, PPC_OPERAND_OPTIONAL }, 2333 2334 /* The SV field in a POWER SC form instruction. */ 2335 #define SV ESYNC + 1 2336 { 0x3fff, 2, NULL, NULL, 0 }, 2337 2338 /* The TBR field in an XFX form instruction. This is like the SPR 2339 field, but it is optional. */ 2340 #define TBR SV + 1 2341 { 0x3ff, 11, insert_tbr, extract_tbr, 2342 PPC_OPERAND_SPR | PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE}, 2343 /* If the TBR operand is ommitted, use the value 268. */ 2344 { -1, 268, NULL, NULL, 0}, 2345 2346 /* The TO field in a D or X form instruction. */ 2347 #define TO TBR + 2 2348 #define DUI TO 2349 #define TO_MASK (0x1f << 21) 2350 { 0x1f, 21, NULL, NULL, 0 }, 2351 2352 /* The UI field in a D form instruction. */ 2353 #define UI TO + 1 2354 { 0xffff, 0, NULL, NULL, 0 }, 2355 2356 #define UISIGNOPT UI + 1 2357 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNOPT }, 2358 2359 /* The IMM field in an SE_IM5 instruction. */ 2360 #define UI5 UISIGNOPT + 1 2361 { 0x1f, 4, NULL, NULL, 0 }, 2362 2363 /* The OIMM field in an SE_OIM5 instruction. */ 2364 #define OIMM5 UI5 + 1 2365 { 0x1f, PPC_OPSHIFT_INV, insert_oimm, extract_oimm, PPC_OPERAND_PLUS1 }, 2366 2367 /* The UI7 field in an SE_LI instruction. */ 2368 #define UI7 OIMM5 + 1 2369 { 0x7f, 4, NULL, NULL, 0 }, 2370 2371 /* The VA field in a VA, VX or VXR form instruction. */ 2372 #define VA UI7 + 1 2373 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR }, 2374 2375 /* The VB field in a VA, VX or VXR form instruction. */ 2376 #define VB VA + 1 2377 { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR }, 2378 2379 /* The VC field in a VA form instruction. */ 2380 #define VC VB + 1 2381 { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR }, 2382 2383 /* The VD or VS field in a VA, VX, VXR or X form instruction. */ 2384 #define VD VC + 1 2385 #define VS VD 2386 { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR }, 2387 2388 /* The SIMM field in a VX form instruction, and TE in Z form. */ 2389 #define SIMM VD + 1 2390 #define TE SIMM 2391 { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED}, 2392 2393 /* The UIMM field in a VX form instruction. */ 2394 #define UIMM SIMM + 1 2395 #define DCTL UIMM 2396 { 0x1f, 16, NULL, NULL, 0 }, 2397 2398 /* The 3-bit UIMM field in a VX form instruction. */ 2399 #define UIMM3 UIMM + 1 2400 { 0x7, 16, NULL, NULL, 0 }, 2401 2402 /* The 6-bit UIM field in a X form instruction. */ 2403 #define UIM6 UIMM3 + 1 2404 { 0x3f, 16, NULL, NULL, 0 }, 2405 2406 /* The SIX field in a VX form instruction. */ 2407 #define SIX UIM6 + 1 2408 #define MMMM SIX 2409 { 0xf, 11, NULL, NULL, 0 }, 2410 2411 /* The PS field in a VX form instruction. */ 2412 #define PS SIX + 1 2413 { 0x1, 9, NULL, NULL, 0 }, 2414 2415 /* The SHB field in a VA form instruction. */ 2416 #define SHB PS + 1 2417 { 0xf, 6, NULL, NULL, 0 }, 2418 2419 /* The other UIMM field in a half word EVX form instruction. */ 2420 #define EVUIMM_1 SHB + 1 2421 { 0x1f, 11, NULL, NULL, PPC_OPERAND_PARENS }, 2422 2423 #define EVUIMM_1_EX0 EVUIMM_1 + 1 2424 { 0x1f, 11, insert_evuimm1_ex0, extract_evuimm1_ex0, PPC_OPERAND_PARENS }, 2425 2426 #define EVUIMM_2 EVUIMM_1_EX0 + 1 2427 { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS }, 2428 2429 #define EVUIMM_2_EX0 EVUIMM_2 + 1 2430 { 0x3e, 10, insert_evuimm2_ex0, extract_evuimm2_ex0, PPC_OPERAND_PARENS }, 2431 2432 /* The other UIMM field in a word EVX form instruction. */ 2433 #define EVUIMM_4 EVUIMM_2_EX0 + 1 2434 { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS }, 2435 2436 #define EVUIMM_4_EX0 EVUIMM_4 + 1 2437 { 0x7c, 9, insert_evuimm4_ex0, extract_evuimm4_ex0, PPC_OPERAND_PARENS }, 2438 2439 /* The other UIMM field in a double EVX form instruction. */ 2440 #define EVUIMM_8 EVUIMM_4_EX0 + 1 2441 { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS }, 2442 2443 #define EVUIMM_8_EX0 EVUIMM_8 + 1 2444 { 0xf8, 8, insert_evuimm8_ex0, extract_evuimm8_ex0, PPC_OPERAND_PARENS }, 2445 2446 /* The WS or DRM field in an X form instruction. */ 2447 #define WS EVUIMM_8_EX0 + 1 2448 #define DRM WS 2449 /* The NNN field in a VX form instruction for SPE2 */ 2450 #define NNN WS 2451 { 0x7, 11, NULL, NULL, 0 }, 2452 2453 /* PowerPC paired singles extensions. */ 2454 /* W bit in the pair singles instructions for x type instructions. */ 2455 #define PSWM WS + 1 2456 /* The BO16 field in a BD8 form instruction. */ 2457 #define BO16 PSWM 2458 { 0x1, 10, 0, 0, 0 }, 2459 2460 /* IDX bits for quantization in the pair singles instructions. */ 2461 #define PSQ PSWM + 1 2462 { 0x7, 12, 0, 0, PPC_OPERAND_GQR }, 2463 2464 /* IDX bits for quantization in the pair singles x-type instructions. */ 2465 #define PSQM PSQ + 1 2466 { 0x7, 7, 0, 0, PPC_OPERAND_GQR }, 2467 2468 /* Smaller D field for quantization in the pair singles instructions. */ 2469 #define PSD PSQM + 1 2470 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, 2471 2472 /* The L field in an mtmsrd or A form instruction or R or W in an 2473 X form. */ 2474 #define A_L PSD + 1 2475 #define W A_L 2476 #define X_R A_L 2477 { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL }, 2478 2479 /* The RMC or CY field in a Z23 form instruction. */ 2480 #define RMC A_L + 1 2481 #define CY RMC 2482 { 0x3, 9, NULL, NULL, 0 }, 2483 2484 #define R RMC + 1 2485 { 0x1, 16, NULL, NULL, 0 }, 2486 2487 #define RIC R + 1 2488 { 0x3, 18, NULL, NULL, PPC_OPERAND_OPTIONAL }, 2489 2490 #define PRS RIC + 1 2491 { 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL }, 2492 2493 #define SP PRS + 1 2494 { 0x3, 19, NULL, NULL, 0 }, 2495 2496 #define S SP + 1 2497 { 0x1, 20, NULL, NULL, 0 }, 2498 2499 /* The S field in a XL form instruction. */ 2500 #define SXL S + 1 2501 { 0x1, 11, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE}, 2502 /* If the SXL operand is ommitted, use the value 1. */ 2503 { -1, 1, NULL, NULL, 0}, 2504 2505 /* SH field starting at bit position 16. */ 2506 #define SH16 SXL + 2 2507 /* The DCM and DGM fields in a Z form instruction. */ 2508 #define DCM SH16 2509 #define DGM DCM 2510 { 0x3f, 10, NULL, NULL, 0 }, 2511 2512 /* The EH field in larx instruction. */ 2513 #define EH SH16 + 1 2514 { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL }, 2515 2516 /* The L field in an mtfsf or XFL form instruction. */ 2517 /* The A field in a HTM X form instruction. */ 2518 #define XFL_L EH + 1 2519 #define HTM_A XFL_L 2520 { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL}, 2521 2522 /* Xilinx APU related masks and macros */ 2523 #define FCRT XFL_L + 1 2524 #define FCRT_MASK (0x1f << 21) 2525 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR }, 2526 2527 /* Xilinx FSL related masks and macros */ 2528 #define FSL FCRT + 1 2529 #define FSL_MASK (0x1f << 11) 2530 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL }, 2531 2532 /* Xilinx UDI related masks and macros */ 2533 #define URT FSL + 1 2534 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI }, 2535 2536 #define URA URT + 1 2537 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI }, 2538 2539 #define URB URA + 1 2540 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI }, 2541 2542 #define URC URB + 1 2543 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI }, 2544 2545 /* The VLESIMM field in a D form instruction. */ 2546 #define VLESIMM URC + 1 2547 { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi, 2548 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, 2549 2550 /* The VLENSIMM field in a D form instruction. */ 2551 #define VLENSIMM VLESIMM + 1 2552 { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi, 2553 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, 2554 2555 /* The VLEUIMM field in a D form instruction. */ 2556 #define VLEUIMM VLENSIMM + 1 2557 { 0xffff, PPC_OPSHIFT_INV, insert_vleui, extract_vleui, 0 }, 2558 2559 /* The VLEUIMML field in a D form instruction. */ 2560 #define VLEUIMML VLEUIMM + 1 2561 { 0xffff, PPC_OPSHIFT_INV, insert_vleil, extract_vleil, 0 }, 2562 2563 /* The XT and XS fields in an XX1 or XX3 form instruction. This is 2564 split. */ 2565 #define XS6 VLEUIMML + 1 2566 #define XT6 XS6 2567 { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR }, 2568 2569 /* The XT and XS fields in an DQ form VSX instruction. This is split. */ 2570 #define XSQ6 XT6 + 1 2571 #define XTQ6 XSQ6 2572 { 0x3f, PPC_OPSHIFT_INV, insert_xtq6, extract_xtq6, PPC_OPERAND_VSR }, 2573 2574 /* The XA field in an XX3 form instruction. This is split. */ 2575 #define XA6 XTQ6 + 1 2576 { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR }, 2577 2578 /* The XB field in an XX2 or XX3 form instruction. This is split. */ 2579 #define XB6 XA6 + 1 2580 { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR }, 2581 2582 /* The XA and XB fields in an XX3 form instruction when they must be the same. 2583 This is used in extended mnemonics like xvmovdp. This is split. */ 2584 #define XAB6 XB6 + 1 2585 { 0x3f, PPC_OPSHIFT_INV, insert_xab6, extract_xab6, PPC_OPERAND_VSR }, 2586 2587 /* The XC field in an XX4 form instruction. This is split. */ 2588 #define XC6 XAB6 + 1 2589 { 0x3f, PPC_OPSHIFT_INV, insert_xc6, extract_xc6, PPC_OPERAND_VSR }, 2590 2591 /* The DM or SHW field in an XX3 form instruction. */ 2592 #define DM XC6 + 1 2593 #define SHW DM 2594 { 0x3, 8, NULL, NULL, 0 }, 2595 2596 /* The DM field in an extended mnemonic XX3 form instruction. */ 2597 #define DMEX DM + 1 2598 { 0x3, 8, insert_dm, extract_dm, 0 }, 2599 2600 /* The UIM field in an XX2 form instruction. */ 2601 #define UIM DMEX + 1 2602 /* The 2-bit UIMM field in a VX form instruction. */ 2603 #define UIMM2 UIM 2604 /* The 2-bit L field in a darn instruction. */ 2605 #define LRAND UIM 2606 { 0x3, 16, NULL, NULL, 0 }, 2607 2608 #define ERAT_T UIM + 1 2609 { 0x7, 21, NULL, NULL, 0 }, 2610 2611 #define IH ERAT_T + 1 2612 { 0x7, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 2613 2614 /* The 8-bit IMM8 field in a XX1 form instruction. */ 2615 #define IMM8 IH + 1 2616 { 0xff, 11, NULL, NULL, PPC_OPERAND_SIGNOPT }, 2617 2618 #define VX_OFF IMM8 + 1 2619 { 0x3, 0, insert_off_lsp, extract_off_lsp, 0 }, 2620 2621 #define VX_OFF_SPE2 VX_OFF + 1 2622 { 0x7, 0, insert_off_spe2, extract_off_spe2, 0 }, 2623 2624 #define BBB VX_OFF_SPE2 + 1 2625 { 0x7, 13, NULL, NULL, 0 }, 2626 2627 #define DDD BBB + 1 2628 #define VX_MASK_DDD (VX_MASK & ~0x1) 2629 { 0x7, PPC_OPSHIFT_INV, insert_Ddd, extract_Ddd, 0 }, 2630 2631 #define HH DDD + 1 2632 { 0x3, 13, NULL, NULL, 0 }, 2633 }; 2634 2635 const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) 2636 / sizeof (powerpc_operands[0])); 2637 2638 /* Macros used to form opcodes. */ 2640 2641 /* The main opcode. */ 2642 #define OP(x) ((((uint64_t)(x)) & 0x3f) << 26) 2643 #define OP_MASK OP (0x3f) 2644 2645 /* The main opcode combined with a trap code in the TO field of a D 2646 form instruction. Used for extended mnemonics for the trap 2647 instructions. */ 2648 #define OPTO(x,to) (OP (x) | ((((uint64_t)(to)) & 0x1f) << 21)) 2649 #define OPTO_MASK (OP_MASK | TO_MASK) 2650 2651 /* The main opcode combined with a comparison size bit in the L field 2652 of a D form or X form instruction. Used for extended mnemonics for 2653 the comparison instructions. */ 2654 #define OPL(x,l) (OP (x) | ((((uint64_t)(l)) & 1) << 21)) 2655 #define OPL_MASK OPL (0x3f,1) 2656 2657 /* The main opcode combined with an update code in D form instruction. 2658 Used for extended mnemonics for VLE memory instructions. */ 2659 #define OPVUP(x,vup) (OP (x) | ((((uint64_t)(vup)) & 0xff) << 8)) 2660 #define OPVUP_MASK OPVUP (0x3f, 0xff) 2661 2662 /* The main opcode combined with an update code and the RT fields 2663 specified in D form instruction. Used for VLE volatile context 2664 save/restore instructions. */ 2665 #define OPVUPRT(x,vup,rt) \ 2666 (OPVUP (x, vup) \ 2667 | ((((uint64_t)(rt)) & 0x1f) << 21)) 2668 #define OPVUPRT_MASK OPVUPRT (0x3f, 0xff, 0x1f) 2669 2670 /* An A form instruction. */ 2671 #define A(op, xop, rc) \ 2672 (OP (op) \ 2673 | ((((uint64_t)(xop)) & 0x1f) << 1) \ 2674 | (((uint64_t)(rc)) & 1)) 2675 #define A_MASK A (0x3f, 0x1f, 1) 2676 2677 /* An A_MASK with the FRB field fixed. */ 2678 #define AFRB_MASK (A_MASK | FRB_MASK) 2679 2680 /* An A_MASK with the FRC field fixed. */ 2681 #define AFRC_MASK (A_MASK | FRC_MASK) 2682 2683 /* An A_MASK with the FRA and FRC fields fixed. */ 2684 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK) 2685 2686 /* An AFRAFRC_MASK, but with L bit clear. */ 2687 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((uint64_t) 1 << 16)) 2688 2689 /* A B form instruction. */ 2690 #define B(op, aa, lk) \ 2691 (OP (op) \ 2692 | ((((uint64_t)(aa)) & 1) << 1) \ 2693 | ((lk) & 1)) 2694 #define B_MASK B (0x3f, 1, 1) 2695 2696 /* A BD8 form instruction. This is a 16-bit instruction. */ 2697 #define BD8(op, aa, lk) \ 2698 (((((uint64_t)(op)) & 0x3f) << 10) \ 2699 | (((aa) & 1) << 9) \ 2700 | (((lk) & 1) << 8)) 2701 #define BD8_MASK BD8 (0x3f, 1, 1) 2702 2703 /* Another BD8 form instruction. This is a 16-bit instruction. */ 2704 #define BD8IO(op) ((((uint64_t)(op)) & 0x1f) << 11) 2705 #define BD8IO_MASK BD8IO (0x1f) 2706 2707 /* A BD8 form instruction for simplified mnemonics. */ 2708 #define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8)) 2709 /* A mask that excludes BO32 and BI32. */ 2710 #define EBD8IO1_MASK 0xf800 2711 /* A mask that includes BO32 and excludes BI32. */ 2712 #define EBD8IO2_MASK 0xfc00 2713 /* A mask that include BO32 AND BI32. */ 2714 #define EBD8IO3_MASK 0xff00 2715 2716 /* A BD15 form instruction. */ 2717 #define BD15(op, aa, lk) \ 2718 (OP (op) \ 2719 | ((((uint64_t)(aa)) & 0xf) << 22) \ 2720 | ((lk) & 1)) 2721 #define BD15_MASK BD15 (0x3f, 0xf, 1) 2722 2723 /* A BD15 form instruction for extended conditional branch mnemonics. */ 2724 #define EBD15(op, aa, bo, lk) \ 2725 (((op) & 0x3f) << 26) \ 2726 | (((aa) & 0xf) << 22) \ 2727 | (((bo) & 0x3) << 20) \ 2728 | ((lk) & 1) 2729 #define EBD15_MASK 0xfff00001 2730 2731 /* A BD15 form instruction for extended conditional branch mnemonics 2732 with BI. */ 2733 #define EBD15BI(op, aa, bo, bi, lk) \ 2734 ((((op) & 0x3f) << 26) \ 2735 | (((aa) & 0xf) << 22) \ 2736 | (((bo) & 0x3) << 20) \ 2737 | (((bi) & 0x3) << 16) \ 2738 | ((lk) & 1)) 2739 2740 #define EBD15BI_MASK 0xfff30001 2741 2742 /* A BD24 form instruction. */ 2743 #define BD24(op, aa, lk) \ 2744 (OP (op) \ 2745 | ((((uint64_t)(aa)) & 1) << 25) \ 2746 | ((lk) & 1)) 2747 #define BD24_MASK BD24 (0x3f, 1, 1) 2748 2749 /* A B form instruction setting the BO field. */ 2750 #define BBO(op, bo, aa, lk) \ 2751 (B ((op), (aa), (lk)) \ 2752 | ((((uint64_t)(bo)) & 0x1f) << 21)) 2753 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1) 2754 2755 /* A BBO_MASK with the y bit of the BO field removed. This permits 2756 matching a conditional branch regardless of the setting of the y 2757 bit. Similarly for the 'at' bits used for power4 branch hints. */ 2758 #define Y_MASK (((uint64_t) 1) << 21) 2759 #define AT1_MASK (((uint64_t) 3) << 21) 2760 #define AT2_MASK (((uint64_t) 9) << 21) 2761 #define BBOY_MASK (BBO_MASK &~ Y_MASK) 2762 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK) 2763 2764 /* A B form instruction setting the BO field and the condition bits of 2765 the BI field. */ 2766 #define BBOCB(op, bo, cb, aa, lk) \ 2767 (BBO ((op), (bo), (aa), (lk)) | ((((uint64_t)(cb)) & 0x3) << 16)) 2768 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1) 2769 2770 /* A BBOCB_MASK with the y bit of the BO field removed. */ 2771 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK) 2772 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK) 2773 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK) 2774 2775 /* A BBOYCB_MASK in which the BI field is fixed. */ 2776 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK) 2777 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK) 2778 2779 /* A VLE C form instruction. */ 2780 #define C_LK(x, lk) (((((uint64_t)(x)) & 0x7fff) << 1) | ((lk) & 1)) 2781 #define C_LK_MASK C_LK(0x7fff, 1) 2782 #define C(x) ((((uint64_t)(x)) & 0xffff)) 2783 #define C_MASK C(0xffff) 2784 2785 /* An Context form instruction. */ 2786 #define CTX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7)) 2787 #define CTX_MASK CTX(0x3f, 0x7) 2788 2789 /* An User Context form instruction. */ 2790 #define UCTX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f)) 2791 #define UCTX_MASK UCTX(0x3f, 0x1f) 2792 2793 /* The main opcode mask with the RA field clear. */ 2794 #define DRA_MASK (OP_MASK | RA_MASK) 2795 2796 /* A DQ form VSX instruction. */ 2797 #define DQX(op, xop) (OP (op) | ((xop) & 0x7)) 2798 #define DQX_MASK DQX (0x3f, 7) 2799 2800 /* A DS form instruction. */ 2801 #define DSO(op, xop) (OP (op) | ((xop) & 0x3)) 2802 #define DS_MASK DSO (0x3f, 3) 2803 2804 /* An DX form instruction. */ 2805 #define DX(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 1)) 2806 #define DX_MASK DX (0x3f, 0x1f) 2807 /* An DX form instruction with the D bits specified. */ 2808 #define NODX_MASK (DX_MASK | 0x1fffc1) 2809 2810 /* An EVSEL form instruction. */ 2811 #define EVSEL(op, xop) (OP (op) | (((uint64_t)(xop)) & 0xff) << 3) 2812 #define EVSEL_MASK EVSEL(0x3f, 0xff) 2813 2814 /* An IA16 form instruction. */ 2815 #define IA16(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11) 2816 #define IA16_MASK IA16(0x3f, 0x1f) 2817 2818 /* An I16A form instruction. */ 2819 #define I16A(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11) 2820 #define I16A_MASK I16A(0x3f, 0x1f) 2821 2822 /* An I16L form instruction. */ 2823 #define I16L(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11) 2824 #define I16L_MASK I16L(0x3f, 0x1f) 2825 2826 /* An IM7 form instruction. */ 2827 #define IM7(op) ((((uint64_t)(op)) & 0x1f) << 11) 2828 #define IM7_MASK IM7(0x1f) 2829 2830 /* An M form instruction. */ 2831 #define M(op, rc) (OP (op) | ((rc) & 1)) 2832 #define M_MASK M (0x3f, 1) 2833 2834 /* An LI20 form instruction. */ 2835 #define LI20(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1) << 15) 2836 #define LI20_MASK LI20(0x3f, 0x1) 2837 2838 /* An M form instruction with the ME field specified. */ 2839 #define MME(op, me, rc) \ 2840 (M ((op), (rc)) \ 2841 | ((((uint64_t)(me)) & 0x1f) << 1)) 2842 2843 /* An M_MASK with the MB and ME fields fixed. */ 2844 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK) 2845 2846 /* An M_MASK with the SH and ME fields fixed. */ 2847 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) 2848 2849 /* An MD form instruction. */ 2850 #define MD(op, xop, rc) \ 2851 (OP (op) \ 2852 | ((((uint64_t)(xop)) & 0x7) << 2) \ 2853 | ((rc) & 1)) 2854 #define MD_MASK MD (0x3f, 0x7, 1) 2855 2856 /* An MD_MASK with the MB field fixed. */ 2857 #define MDMB_MASK (MD_MASK | MB6_MASK) 2858 2859 /* An MD_MASK with the SH field fixed. */ 2860 #define MDSH_MASK (MD_MASK | SH6_MASK) 2861 2862 /* An MDS form instruction. */ 2863 #define MDS(op, xop, rc) \ 2864 (OP (op) \ 2865 | ((((uint64_t)(xop)) & 0xf) << 1) \ 2866 | ((rc) & 1)) 2867 #define MDS_MASK MDS (0x3f, 0xf, 1) 2868 2869 /* An MDS_MASK with the MB field fixed. */ 2870 #define MDSMB_MASK (MDS_MASK | MB6_MASK) 2871 2872 /* An SC form instruction. */ 2873 #define SC(op, sa, lk) \ 2874 (OP (op) \ 2875 | ((((uint64_t)(sa)) & 1) << 1) \ 2876 | ((lk) & 1)) 2877 #define SC_MASK \ 2878 (OP_MASK \ 2879 | (((uint64_t) 0x3ff) << 16) \ 2880 | (((uint64_t) 1) << 1) \ 2881 | 1) 2882 2883 /* An SCI8 form instruction. */ 2884 #define SCI8(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 11)) 2885 #define SCI8_MASK SCI8(0x3f, 0x1f) 2886 2887 /* An SCI8 form instruction. */ 2888 #define SCI8BF(op, fop, xop) \ 2889 (OP (op) \ 2890 | ((((uint64_t)(xop)) & 0x1f) << 11) \ 2891 | (((fop) & 7) << 23)) 2892 #define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f) 2893 2894 /* An SD4 form instruction. This is a 16-bit instruction. */ 2895 #define SD4(op) ((((uint64_t)(op)) & 0xf) << 12) 2896 #define SD4_MASK SD4(0xf) 2897 2898 /* An SE_IM5 form instruction. This is a 16-bit instruction. */ 2899 #define SE_IM5(op, xop) \ 2900 (((((uint64_t)(op)) & 0x3f) << 10) \ 2901 | (((xop) & 0x1) << 9)) 2902 #define SE_IM5_MASK SE_IM5(0x3f, 1) 2903 2904 /* An SE_R form instruction. This is a 16-bit instruction. */ 2905 #define SE_R(op, xop) \ 2906 (((((uint64_t)(op)) & 0x3f) << 10) \ 2907 | (((xop) & 0x3f) << 4)) 2908 #define SE_R_MASK SE_R(0x3f, 0x3f) 2909 2910 /* An SE_RR form instruction. This is a 16-bit instruction. */ 2911 #define SE_RR(op, xop) \ 2912 (((((uint64_t)(op)) & 0x3f) << 10) \ 2913 | (((xop) & 0x3) << 8)) 2914 #define SE_RR_MASK SE_RR(0x3f, 3) 2915 2916 /* A VX form instruction. */ 2917 #define VX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7ff)) 2918 2919 /* The mask for an VX form instruction. */ 2920 #define VX_MASK VX(0x3f, 0x7ff) 2921 2922 /* A VX LSP form instruction. */ 2923 #define VX_LSP(op, xop) (OP (op) | (((uint64_t)(xop)) & 0xffff)) 2924 2925 /* The mask for an VX LSP form instruction. */ 2926 #define VX_LSP_MASK VX_LSP(0x3f, 0xffff) 2927 #define VX_LSP_OFF_MASK VX_LSP(0x3f, 0x7fc) 2928 2929 /* Additional format of VX SPE2 form instruction. */ 2930 #define VX_RA_CONST(op, xop, bits11_15) \ 2931 (OP (op) \ 2932 | (((uint64_t)(bits11_15) & 0x1f) << 16) \ 2933 | (((uint64_t)(xop)) & 0x7ff)) 2934 #define VX_RA_CONST_MASK VX_RA_CONST(0x3f, 0x7ff, 0x1f) 2935 2936 #define VX_RB_CONST(op, xop, bits16_20) \ 2937 (OP (op) \ 2938 | (((uint64_t)(bits16_20) & 0x1f) << 11) \ 2939 | (((uint64_t)(xop)) & 0x7ff)) 2940 #define VX_RB_CONST_MASK VX_RB_CONST(0x3f, 0x7ff, 0x1f) 2941 2942 #define VX_OFF_SPE2_MASK VX(0x3f, 0x7f8) 2943 2944 #define VX_SPE_CRFD(op, xop, bits9_10) \ 2945 (OP (op) \ 2946 | (((uint64_t)(bits9_10) & 0x3) << 21) \ 2947 | (((uint64_t)(xop)) & 0x7ff)) 2948 #define VX_SPE_CRFD_MASK VX_SPE_CRFD(0x3f, 0x7ff, 0x3) 2949 2950 #define VX_SPE2_CLR(op, xop, bit16) \ 2951 (OP (op) \ 2952 | (((uint64_t)(bit16) & 0x1) << 15) \ 2953 | (((uint64_t)(xop)) & 0x7ff)) 2954 #define VX_SPE2_CLR_MASK VX_SPE2_CLR(0x3f, 0x7ff, 0x1) 2955 2956 #define VX_SPE2_SPLATB(op, xop, bits19_20) \ 2957 (OP (op) \ 2958 | (((uint64_t)(bits19_20) & 0x3) << 11) \ 2959 | (((uint64_t)(xop)) & 0x7ff)) 2960 #define VX_SPE2_SPLATB_MASK VX_SPE2_SPLATB(0x3f, 0x7ff, 0x3) 2961 2962 #define VX_SPE2_OCTET(op, xop, bits16_17) \ 2963 (OP (op) \ 2964 | (((uint64_t)(bits16_17) & 0x3) << 14) \ 2965 | (((uint64_t)(xop)) & 0x7ff)) 2966 #define VX_SPE2_OCTET_MASK VX_SPE2_OCTET(0x3f, 0x7ff, 0x7) 2967 2968 #define VX_SPE2_DDHH(op, xop, bit16) \ 2969 (OP (op) \ 2970 | (((uint64_t)(bit16) & 0x1) << 15) \ 2971 | (((uint64_t)(xop)) & 0x7ff)) 2972 #define VX_SPE2_DDHH_MASK VX_SPE2_DDHH(0x3f, 0x7ff, 0x1) 2973 2974 #define VX_SPE2_HH(op, xop, bit16, bits19_20) \ 2975 (OP (op) \ 2976 | (((uint64_t)(bit16) & 0x1) << 15) \ 2977 | (((uint64_t)(bits19_20) & 0x3) << 11) \ 2978 | (((uint64_t)(xop)) & 0x7ff)) 2979 #define VX_SPE2_HH_MASK VX_SPE2_HH(0x3f, 0x7ff, 0x1, 0x3) 2980 2981 #define VX_SPE2_EVMAR(op, xop) \ 2982 (OP (op) \ 2983 | ((uint64_t)(0x1) << 11) \ 2984 | (((uint64_t)(xop)) & 0x7ff)) 2985 #define VX_SPE2_EVMAR_MASK \ 2986 (VX_SPE2_EVMAR(0x3f, 0x7ff) \ 2987 | ((uint64_t)(0x1) << 11)) 2988 2989 /* A VX_MASK with the VA field fixed. */ 2990 #define VXVA_MASK (VX_MASK | (0x1f << 16)) 2991 2992 /* A VX_MASK with the VB field fixed. */ 2993 #define VXVB_MASK (VX_MASK | (0x1f << 11)) 2994 2995 /* A VX_MASK with the VA and VB fields fixed. */ 2996 #define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11)) 2997 2998 /* A VX_MASK with the VD and VA fields fixed. */ 2999 #define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16)) 3000 3001 /* A VX_MASK with a UIMM4 field. */ 3002 #define VXUIMM4_MASK (VX_MASK | (0x1 << 20)) 3003 3004 /* A VX_MASK with a UIMM3 field. */ 3005 #define VXUIMM3_MASK (VX_MASK | (0x3 << 19)) 3006 3007 /* A VX_MASK with a UIMM2 field. */ 3008 #define VXUIMM2_MASK (VX_MASK | (0x7 << 18)) 3009 3010 /* A VX_MASK with a PS field. */ 3011 #define VXPS_MASK (VX_MASK & ~(0x1 << 9)) 3012 3013 /* A VX_MASK with the VA field fixed with a PS field. */ 3014 #define VXVAPS_MASK ((VX_MASK | (0x1f << 16)) & ~(0x1 << 9)) 3015 3016 /* A VA form instruction. */ 3017 #define VXA(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x03f)) 3018 3019 /* The mask for an VA form instruction. */ 3020 #define VXA_MASK VXA(0x3f, 0x3f) 3021 3022 /* A VXA_MASK with a SHB field. */ 3023 #define VXASHB_MASK (VXA_MASK | (1 << 10)) 3024 3025 /* A VXR form instruction. */ 3026 #define VXR(op, xop, rc) \ 3027 (OP (op) \ 3028 | (((uint64_t)(rc) & 1) << 10) \ 3029 | (((uint64_t)(xop)) & 0x3ff)) 3030 3031 /* The mask for a VXR form instruction. */ 3032 #define VXR_MASK VXR(0x3f, 0x3ff, 1) 3033 3034 /* A VX form instruction with a VA tertiary opcode. */ 3035 #define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16)) 3036 3037 #define VXASH(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 1)) 3038 #define VXASH_MASK VXASH (0x3f, 0x1f) 3039 3040 /* An X form instruction. */ 3041 #define X(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3ff) << 1)) 3042 3043 /* A X form instruction for Quad-Precision FP Instructions. */ 3044 #define XVA(op, xop, vaop) (X(op,xop) | (((vaop) & 0x1f) << 16)) 3045 3046 /* An EX form instruction. */ 3047 #define EX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7ff)) 3048 3049 /* The mask for an EX form instruction. */ 3050 #define EX_MASK EX (0x3f, 0x7ff) 3051 3052 /* An XX2 form instruction. */ 3053 #define XX2(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1ff) << 2)) 3054 3055 /* A XX2 form instruction with the VA bits specified. */ 3056 #define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16)) 3057 3058 /* An XX3 form instruction. */ 3059 #define XX3(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0xff) << 3)) 3060 3061 /* An XX3 form instruction with the RC bit specified. */ 3062 #define XX3RC(op, xop, rc) \ 3063 (OP (op) \ 3064 | (((uint64_t)(rc) & 1) << 10) \ 3065 | ((((uint64_t)(xop)) & 0x7f) << 3)) 3066 3067 /* An XX4 form instruction. */ 3068 #define XX4(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3) << 4)) 3069 3070 /* A Z form instruction. */ 3071 #define Z(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1ff) << 1)) 3072 3073 /* An X form instruction with the RC bit specified. */ 3074 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1)) 3075 3076 /* A X form instruction for Quad-Precision FP Instructions with RC bit. */ 3077 #define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1)) 3078 3079 /* An X form instruction with the RA bits specified as two ops. */ 3080 #define XMMF(op, xop, mop0, mop1) \ 3081 (X ((op), (xop)) \ 3082 | ((mop0) & 3) << 19 \ 3083 | ((mop1) & 7) << 16) 3084 3085 /* A Z form instruction with the RC bit specified. */ 3086 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) 3087 3088 /* The mask for an X form instruction. */ 3089 #define X_MASK XRC (0x3f, 0x3ff, 1) 3090 3091 /* The mask for an X form instruction with the BF bits specified. */ 3092 #define XBF_MASK (X_MASK | (3 << 21)) 3093 3094 /* An X form wait instruction with everything filled in except the WC 3095 field. */ 3096 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK) 3097 3098 /* The mask for an XX1 form instruction. */ 3099 #define XX1_MASK X (0x3f, 0x3ff) 3100 3101 /* An XX1_MASK with the RB field fixed. */ 3102 #define XX1RB_MASK (XX1_MASK | RB_MASK) 3103 3104 /* The mask for an XX2 form instruction. */ 3105 #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16)) 3106 3107 /* The mask for an XX2 form instruction with the UIM bits specified. */ 3108 #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18)) 3109 3110 /* The mask for an XX2 form instruction with the 4 UIM bits specified. */ 3111 #define XX2UIM4_MASK (XX2 (0x3f, 0x1ff) | (1 << 20)) 3112 3113 /* The mask for an XX2 form instruction with the BF bits specified. */ 3114 #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1)) 3115 3116 /* The mask for an XX2 form instruction with the BF and DCMX bits 3117 specified. */ 3118 #define XX2BFD_MASK (XX2 (0x3f, 0x1ff) | 1) 3119 3120 /* The mask for an XX2 form instruction with a split DCMX bits 3121 specified. */ 3122 #define XX2DCMXS_MASK XX2 (0x3f, 0x1ee) 3123 3124 /* The mask for an XX3 form instruction. */ 3125 #define XX3_MASK XX3 (0x3f, 0xff) 3126 3127 /* The mask for an XX3 form instruction with the BF bits specified. */ 3128 #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1)) 3129 3130 /* The mask for an XX3 form instruction with the DM or SHW bits 3131 specified. */ 3132 #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10)) 3133 #define XX3SHW_MASK XX3DM_MASK 3134 3135 /* The mask for an XX4 form instruction. */ 3136 #define XX4_MASK XX4 (0x3f, 0x3) 3137 3138 /* An X form wait instruction with everything filled in except the WC 3139 field. */ 3140 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK) 3141 3142 /* The mask for an XMMF form instruction. */ 3143 #define XMMF_MASK (XMMF (0x3f, 0x3ff, 3, 7) | (1)) 3144 3145 /* The mask for a Z form instruction. */ 3146 #define Z_MASK ZRC (0x3f, 0x1ff, 1) 3147 #define Z2_MASK ZRC (0x3f, 0xff, 1) 3148 3149 /* An X_MASK with the RA/VA field fixed. */ 3150 #define XRA_MASK (X_MASK | RA_MASK) 3151 #define XVA_MASK XRA_MASK 3152 3153 /* An XRA_MASK with the A_L/W field clear. */ 3154 #define XWRA_MASK (XRA_MASK & ~((uint64_t) 1 << 16)) 3155 #define XRLA_MASK XWRA_MASK 3156 3157 /* An X_MASK with the RB field fixed. */ 3158 #define XRB_MASK (X_MASK | RB_MASK) 3159 3160 /* An X_MASK with the RT field fixed. */ 3161 #define XRT_MASK (X_MASK | RT_MASK) 3162 3163 /* An XRT_MASK mask with the L bits clear. */ 3164 #define XLRT_MASK (XRT_MASK & ~((uint64_t) 0x3 << 21)) 3165 3166 /* An X_MASK with the RA and RB fields fixed. */ 3167 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK) 3168 3169 /* An XBF_MASK with the RA and RB fields fixed. */ 3170 #define XBFRARB_MASK (XBF_MASK | RA_MASK | RB_MASK) 3171 3172 /* An XRARB_MASK, but with the L bit clear. */ 3173 #define XRLARB_MASK (XRARB_MASK & ~((uint64_t) 1 << 16)) 3174 3175 /* An XRARB_MASK, but with the L bits in a darn instruction clear. */ 3176 #define XLRAND_MASK (XRARB_MASK & ~((uint64_t) 3 << 16)) 3177 3178 /* An X_MASK with the RT and RA fields fixed. */ 3179 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK) 3180 3181 /* An X_MASK with the RT and RB fields fixed. */ 3182 #define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK) 3183 3184 /* An XRTRA_MASK, but with L bit clear. */ 3185 #define XRTLRA_MASK (XRTRA_MASK & ~((uint64_t) 1 << 21)) 3186 3187 /* An X_MASK with the RT, RA and RB fields fixed. */ 3188 #define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK) 3189 3190 /* An XRTRARB_MASK, but with L bit clear. */ 3191 #define XRTLRARB_MASK (XRTRARB_MASK & ~((uint64_t) 1 << 21)) 3192 3193 /* An XRTRARB_MASK, but with A bit clear. */ 3194 #define XRTARARB_MASK (XRTRARB_MASK & ~((uint64_t) 1 << 25)) 3195 3196 /* An XRTRARB_MASK, but with BF bits clear. */ 3197 #define XRTBFRARB_MASK (XRTRARB_MASK & ~((uint64_t) 7 << 23)) 3198 3199 /* An X form instruction with the L bit specified. */ 3200 #define XOPL(op, xop, l) \ 3201 (X ((op), (xop)) \ 3202 | ((((uint64_t)(l)) & 1) << 21)) 3203 3204 /* An X form instruction with the L bits specified. */ 3205 #define XOPL2(op, xop, l) \ 3206 (X ((op), (xop)) \ 3207 | ((((uint64_t)(l)) & 3) << 21)) 3208 3209 /* An X form instruction with the L bit and RC bit specified. */ 3210 #define XRCL(op, xop, l, rc) \ 3211 (XRC ((op), (xop), (rc)) \ 3212 | ((((uint64_t)(l)) & 1) << 21)) 3213 3214 /* An X form instruction with RT fields specified */ 3215 #define XRT(op, xop, rt) \ 3216 (X ((op), (xop)) \ 3217 | ((((uint64_t)(rt)) & 0x1f) << 21)) 3218 3219 /* An X form instruction with RT and RA fields specified */ 3220 #define XRTRA(op, xop, rt, ra) \ 3221 (X ((op), (xop)) \ 3222 | ((((uint64_t)(rt)) & 0x1f) << 21) \ 3223 | ((((uint64_t)(ra)) & 0x1f) << 16)) 3224 3225 /* The mask for an X form comparison instruction. */ 3226 #define XCMP_MASK (X_MASK | (((uint64_t)1) << 22)) 3227 3228 /* The mask for an X form comparison instruction with the L field 3229 fixed. */ 3230 #define XCMPL_MASK (XCMP_MASK | (((uint64_t)1) << 21)) 3231 3232 /* An X form trap instruction with the TO field specified. */ 3233 #define XTO(op, xop, to) \ 3234 (X ((op), (xop)) \ 3235 | ((((uint64_t)(to)) & 0x1f) << 21)) 3236 #define XTO_MASK (X_MASK | TO_MASK) 3237 3238 /* An X form tlb instruction with the SH field specified. */ 3239 #define XTLB(op, xop, sh) \ 3240 (X ((op), (xop)) \ 3241 | ((((uint64_t)(sh)) & 0x1f) << 11)) 3242 #define XTLB_MASK (X_MASK | SH_MASK) 3243 3244 /* An X form sync instruction. */ 3245 #define XSYNC(op, xop, l) \ 3246 (X ((op), (xop)) \ 3247 | ((((uint64_t)(l)) & 3) << 21)) 3248 3249 /* An X form sync instruction with everything filled in except the LS 3250 field. */ 3251 #define XSYNC_MASK (0xff9fffff) 3252 3253 /* An X form sync instruction with everything filled in except the L 3254 and E fields. */ 3255 #define XSYNCLE_MASK (0xff90ffff) 3256 3257 /* An X_MASK, but with the EH bit clear. */ 3258 #define XEH_MASK (X_MASK & ~((uint64_t )1)) 3259 3260 /* An X form AltiVec dss instruction. */ 3261 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((uint64_t)(a)) & 1) << 25)) 3262 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1) 3263 3264 /* An XFL form instruction. */ 3265 #define XFL(op, xop, rc) \ 3266 (OP (op) \ 3267 | ((((uint64_t)(xop)) & 0x3ff) << 1) \ 3268 | (((uint64_t)(rc)) & 1)) 3269 #define XFL_MASK XFL (0x3f, 0x3ff, 1) 3270 3271 /* An X form isel instruction. */ 3272 #define XISEL(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 1)) 3273 #define XISEL_MASK XISEL(0x3f, 0x1f) 3274 3275 /* An XL form instruction with the LK field set to 0. */ 3276 #define XL(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3ff) << 1)) 3277 3278 /* An XL form instruction which uses the LK field. */ 3279 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1)) 3280 3281 /* The mask for an XL form instruction. */ 3282 #define XL_MASK XLLK (0x3f, 0x3ff, 1) 3283 3284 /* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear. */ 3285 #define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11)) 3286 3287 /* An XL form instruction which explicitly sets the BO field. */ 3288 #define XLO(op, bo, xop, lk) \ 3289 (XLLK ((op), (xop), (lk)) | ((((uint64_t)(bo)) & 0x1f) << 21)) 3290 #define XLO_MASK (XL_MASK | BO_MASK) 3291 3292 /* An XL form instruction which explicitly sets the y bit of the BO 3293 field. */ 3294 #define XLYLK(op, xop, y, lk) \ 3295 (XLLK ((op), (xop), (lk)) \ 3296 | ((((uint64_t)(y)) & 1) << 21)) 3297 #define XLYLK_MASK (XL_MASK | Y_MASK) 3298 3299 /* An XL form instruction which sets the BO field and the condition 3300 bits of the BI field. */ 3301 #define XLOCB(op, bo, cb, xop, lk) \ 3302 (XLO ((op), (bo), (xop), (lk)) | ((((uint64_t)(cb)) & 3) << 16)) 3303 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1) 3304 3305 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */ 3306 #define XLBB_MASK (XL_MASK | BB_MASK) 3307 #define XLYBB_MASK (XLYLK_MASK | BB_MASK) 3308 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK) 3309 3310 /* A mask for branch instructions using the BH field. */ 3311 #define XLBH_MASK (XL_MASK | (0x1c << 11)) 3312 3313 /* An XL_MASK with the BO and BB fields fixed. */ 3314 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK) 3315 3316 /* An XL_MASK with the BO, BI and BB fields fixed. */ 3317 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK) 3318 3319 /* An X form mbar instruction with MO field. */ 3320 #define XMBAR(op, xop, mo) \ 3321 (X ((op), (xop)) \ 3322 | ((((uint64_t)(mo)) & 1) << 21)) 3323 3324 /* An XO form instruction. */ 3325 #define XO(op, xop, oe, rc) \ 3326 (OP (op) \ 3327 | ((((uint64_t)(xop)) & 0x1ff) << 1) \ 3328 | ((((uint64_t)(oe)) & 1) << 10) \ 3329 | (((unsigned long)(rc)) & 1)) 3330 #define XO_MASK XO (0x3f, 0x1ff, 1, 1) 3331 3332 /* An XO_MASK with the RB field fixed. */ 3333 #define XORB_MASK (XO_MASK | RB_MASK) 3334 3335 /* An XOPS form instruction for paired singles. */ 3336 #define XOPS(op, xop, rc) \ 3337 (OP (op) \ 3338 | ((((uint64_t)(xop)) & 0x3ff) << 1) \ 3339 | (((uint64_t)(rc)) & 1)) 3340 #define XOPS_MASK XOPS (0x3f, 0x3ff, 1) 3341 3342 3343 /* An XS form instruction. */ 3344 #define XS(op, xop, rc) \ 3345 (OP (op) \ 3346 | ((((uint64_t)(xop)) & 0x1ff) << 2) \ 3347 | (((uint64_t)(rc)) & 1)) 3348 #define XS_MASK XS (0x3f, 0x1ff, 1) 3349 3350 /* A mask for the FXM version of an XFX form instruction. */ 3351 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20)) 3352 3353 /* An XFX form instruction with the FXM field filled in. */ 3354 #define XFXM(op, xop, fxm, p4) \ 3355 (X ((op), (xop)) \ 3356 | ((((uint64_t)(fxm)) & 0xff) << 12) \ 3357 | ((uint64_t)(p4) << 20)) 3358 3359 /* An XFX form instruction with the SPR field filled in. */ 3360 #define XSPR(op, xop, spr) \ 3361 (X ((op), (xop)) \ 3362 | ((((uint64_t)(spr)) & 0x1f) << 16) \ 3363 | ((((uint64_t)(spr)) & 0x3e0) << 6)) 3364 #define XSPR_MASK (X_MASK | SPR_MASK) 3365 3366 /* An XFX form instruction with the SPR field filled in except for the 3367 SPRBAT field. */ 3368 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK) 3369 3370 /* An XFX form instruction with the SPR field filled in except for the 3371 SPRG field. */ 3372 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16)) 3373 3374 /* An X form instruction with everything filled in except the E field. */ 3375 #define XE_MASK (0xffff7fff) 3376 3377 /* An X form user context instruction. */ 3378 #define XUC(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f)) 3379 #define XUC_MASK XUC(0x3f, 0x1f) 3380 3381 /* An XW form instruction. */ 3382 #define XW(op, xop, rc) \ 3383 (OP (op) \ 3384 | ((((uint64_t)(xop)) & 0x3f) << 1) \ 3385 | ((rc) & 1)) 3386 /* The mask for a G form instruction. rc not supported at present. */ 3387 #define XW_MASK XW (0x3f, 0x3f, 0) 3388 3389 /* An APU form instruction. */ 3390 #define APU(op, xop, rc) \ 3391 (OP (op) \ 3392 | (((uint64_t)(xop)) & 0x3ff) << 1 \ 3393 | ((rc) & 1)) 3394 3395 /* The mask for an APU form instruction. */ 3396 #define APU_MASK APU (0x3f, 0x3ff, 1) 3397 #define APU_RT_MASK (APU_MASK | RT_MASK) 3398 #define APU_RA_MASK (APU_MASK | RA_MASK) 3399 3400 /* The BO encodings used in extended conditional branch mnemonics. */ 3401 #define BODNZF (0x0) 3402 #define BODNZFP (0x1) 3403 #define BODZF (0x2) 3404 #define BODZFP (0x3) 3405 #define BODNZT (0x8) 3406 #define BODNZTP (0x9) 3407 #define BODZT (0xa) 3408 #define BODZTP (0xb) 3409 3410 #define BOF (0x4) 3411 #define BOFP (0x5) 3412 #define BOFM4 (0x6) 3413 #define BOFP4 (0x7) 3414 #define BOT (0xc) 3415 #define BOTP (0xd) 3416 #define BOTM4 (0xe) 3417 #define BOTP4 (0xf) 3418 3419 #define BODNZ (0x10) 3420 #define BODNZP (0x11) 3421 #define BODZ (0x12) 3422 #define BODZP (0x13) 3423 #define BODNZM4 (0x18) 3424 #define BODNZP4 (0x19) 3425 #define BODZM4 (0x1a) 3426 #define BODZP4 (0x1b) 3427 3428 #define BOU (0x14) 3429 3430 /* The BO16 encodings used in extended VLE conditional branch mnemonics. */ 3431 #define BO16F (0x0) 3432 #define BO16T (0x1) 3433 3434 /* The BO32 encodings used in extended VLE conditional branch mnemonics. */ 3435 #define BO32F (0x0) 3436 #define BO32T (0x1) 3437 #define BO32DNZ (0x2) 3438 #define BO32DZ (0x3) 3439 3440 /* The BI condition bit encodings used in extended conditional branch 3441 mnemonics. */ 3442 #define CBLT (0) 3443 #define CBGT (1) 3444 #define CBEQ (2) 3445 #define CBSO (3) 3446 3447 /* The TO encodings used in extended trap mnemonics. */ 3448 #define TOLGT (0x1) 3449 #define TOLLT (0x2) 3450 #define TOEQ (0x4) 3451 #define TOLGE (0x5) 3452 #define TOLNL (0x5) 3453 #define TOLLE (0x6) 3454 #define TOLNG (0x6) 3455 #define TOGT (0x8) 3456 #define TOGE (0xc) 3457 #define TONL (0xc) 3458 #define TOLT (0x10) 3459 #define TOLE (0x14) 3460 #define TONG (0x14) 3461 #define TONE (0x18) 3462 #define TOU (0x1f) 3463 3464 /* Smaller names for the flags so each entry in the opcodes table will 3466 fit on a single line. */ 3467 #undef PPC 3468 #define PPC PPC_OPCODE_PPC 3469 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON 3470 #define POWER4 PPC_OPCODE_POWER4 3471 #define POWER5 PPC_OPCODE_POWER5 3472 #define POWER6 PPC_OPCODE_POWER6 3473 #define POWER7 PPC_OPCODE_POWER7 3474 #define POWER8 PPC_OPCODE_POWER8 3475 #define POWER9 PPC_OPCODE_POWER9 3476 #define CELL PPC_OPCODE_CELL 3477 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE 3478 #define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \ 3479 | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN) 3480 #define PPC403 PPC_OPCODE_403 3481 #define PPC405 PPC_OPCODE_405 3482 #define PPC440 PPC_OPCODE_440 3483 #define PPC464 PPC440 3484 #define PPC476 PPC_OPCODE_476 3485 #define PPC750 PPC_OPCODE_750 3486 #define PPC7450 PPC_OPCODE_7450 3487 #define PPC860 PPC_OPCODE_860 3488 #define PPCPS PPC_OPCODE_PPCPS 3489 #define PPCVEC PPC_OPCODE_ALTIVEC 3490 #define PPCVEC2 (PPC_OPCODE_POWER8 | PPC_OPCODE_E6500) 3491 #define PPCVEC3 PPC_OPCODE_POWER9 3492 #define PPCVSX PPC_OPCODE_VSX 3493 #define PPCVSX2 PPC_OPCODE_POWER8 3494 #define PPCVSX3 PPC_OPCODE_POWER9 3495 #define POWER PPC_OPCODE_POWER 3496 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 3497 #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON 3498 #define PPCPWR2 (PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 \ 3499 | PPC_OPCODE_COMMON) 3500 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON 3501 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 3502 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON 3503 #define MFDEC1 PPC_OPCODE_POWER 3504 #define MFDEC2 (PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE \ 3505 | PPC_OPCODE_TITAN) 3506 #define BOOKE PPC_OPCODE_BOOKE 3507 #define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS 3508 #define PPCE300 PPC_OPCODE_E300 3509 #define PPCSPE PPC_OPCODE_SPE 3510 #define PPCSPE2 PPC_OPCODE_SPE2 3511 #define PPCISEL PPC_OPCODE_ISEL 3512 #define PPCEFS PPC_OPCODE_EFS 3513 #define PPCEFS2 PPC_OPCODE_EFS2 3514 #define PPCBRLK PPC_OPCODE_BRLOCK 3515 #define PPCPMR PPC_OPCODE_PMR 3516 #define PPCTMR PPC_OPCODE_TMR 3517 #define PPCCHLK PPC_OPCODE_CACHELCK 3518 #define PPCRFMCI PPC_OPCODE_RFMCI 3519 #define E500MC PPC_OPCODE_E500MC 3520 #define PPCA2 PPC_OPCODE_A2 3521 #define TITAN PPC_OPCODE_TITAN 3522 #define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | PPC_OPCODE_476 | TITAN 3523 #define E500 PPC_OPCODE_E500 3524 #define E6500 PPC_OPCODE_E6500 3525 #define PPCVLE PPC_OPCODE_VLE 3526 #define PPCHTM PPC_OPCODE_POWER8 3527 #define E200Z4 PPC_OPCODE_E200Z4 3528 #define PPCLSP PPC_OPCODE_LSP 3529 /* The list of embedded processors that use the embedded operand ordering 3530 for the 3 operand dcbt and dcbtst instructions. */ 3531 #define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \ 3532 | PPC_OPCODE_A2) 3533 3534 3535 3536 /* The opcode table. 3538 3539 The format of the opcode table is: 3540 3541 NAME OPCODE MASK FLAGS ANTI {OPERANDS} 3542 3543 NAME is the name of the instruction. 3544 OPCODE is the instruction opcode. 3545 MASK is the opcode mask; this is used to tell the disassembler 3546 which bits in the actual opcode must match OPCODE. 3547 FLAGS are flags indicating which processors support the instruction. 3548 ANTI indicates which processors don't support the instruction. 3549 OPERANDS is the list of operands. 3550 3551 The disassembler reads the table in order and prints the first 3552 instruction which matches, so this table is sorted to put more 3553 specific instructions before more general instructions. 3554 3555 This table must be sorted by major opcode. Please try to keep it 3556 vaguely sorted within major opcode too, except of course where 3557 constrained otherwise by disassembler operation. */ 3558 3559 const struct powerpc_opcode powerpc_opcodes[] = { 3560 {"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476|PPCVLE, {0}}, 3561 {"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3562 {"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3563 {"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3564 {"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3565 {"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3566 {"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3567 {"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3568 {"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3569 {"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3570 {"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3571 {"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3572 {"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3573 {"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3574 {"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3575 {"tdui", OPTO(2,TOU), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3576 {"tdi", OP(2), OP_MASK, PPC64, PPCVLE, {TO, RA, SI}}, 3577 3578 {"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3579 {"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3580 {"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3581 {"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3582 {"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3583 {"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3584 {"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3585 {"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3586 {"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3587 {"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3588 {"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3589 {"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3590 {"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3591 {"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3592 {"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3593 {"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3594 {"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3595 {"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3596 {"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3597 {"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3598 {"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3599 {"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3600 {"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3601 {"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3602 {"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3603 {"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3604 {"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3605 {"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3606 {"twui", OPTO(3,TOU), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3607 {"tui", OPTO(3,TOU), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3608 {"twi", OP(3), OP_MASK, PPCCOM, PPCVLE, {TO, RA, SI}}, 3609 {"ti", OP(3), OP_MASK, PWRCOM, PPCVLE, {TO, RA, SI}}, 3610 3611 {"ps_cmpu0", X (4, 0), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, 3612 {"vaddubm", VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3613 {"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, 0, {VD, VA}}, 3614 {"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3615 {"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3616 {"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3617 {"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3618 {"vmuloub", VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3619 {"vaddfp", VX (4, 10), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3620 {"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}}, 3621 {"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3622 {"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}}, 3623 {"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3624 {"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}}, 3625 {"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}}, 3626 {"ps_sum0", A (4, 10,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3627 {"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3628 {"ps_sum1", A (4, 11,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3629 {"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3630 {"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, 3631 {"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3632 {"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, 3633 {"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3634 {"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, 3635 {"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, 3636 {"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3637 {"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3638 {"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3639 {"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3640 {"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3641 {"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3642 {"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3643 {"vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}}, 3644 {"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3645 {"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3646 {"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3647 {"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3648 {"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3649 {"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3650 {"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3651 {"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3652 {"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3653 {"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3654 {"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3655 {"vsel", VXA(4, 42), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3656 {"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3657 {"vperm", VXA(4, 43), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3658 {"vsldoi", VXA(4, 44), VXASHB_MASK, PPCVEC, 0, {VD, VA, VB, SHB}}, 3659 {"vpermxor", VXA(4, 45), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, 3660 {"ps_sel", A (4, 23,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3661 {"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}}, 3662 {"ps_sel.", A (4, 23,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3663 {"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}}, 3664 {"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, 3665 {"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, 3666 {"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, 3667 {"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, 3668 {"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, 3669 {"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, 3670 {"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, 3671 {"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, 3672 {"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, 3673 {"ps_msub", A (4, 28,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3674 {"ps_msub.", A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3675 {"ps_madd", A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3676 {"ps_madd.", A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3677 {"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}}, 3678 {"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3679 {"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, 3680 {"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3681 {"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, 3682 {"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3683 {"vsubeuqm", VXA(4, 62), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, 3684 {"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3685 {"vsubecuq", VXA(4, 63), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, 3686 {"ps_cmpo0", X (4, 32), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, 3687 {"vadduhm", VX (4, 64), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3688 {"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3689 {"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3690 {"vrlh", VX (4, 68), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3691 {"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3692 {"vcmpneh", VXR(4, 71,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3693 {"vmulouh", VX (4, 72), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3694 {"vsubfp", VX (4, 74), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3695 {"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}}, 3696 {"vmrghh", VX (4, 76), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3697 {"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}}, 3698 {"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3699 {"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3700 {"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}}, 3701 {"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3702 {"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}}, 3703 {"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3704 {"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3705 {"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3706 {"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3707 {"ps_cmpu1", X (4, 64), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, 3708 {"vadduwm", VX (4, 128), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3709 {"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3710 {"vrlw", VX (4, 132), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3711 {"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3712 {"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3713 {"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3714 {"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3715 {"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3716 {"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3717 {"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3718 {"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3719 {"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3720 {"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3721 {"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3722 {"ps_cmpo1", X (4, 96), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, 3723 {"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3724 {"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3725 {"vrld", VX (4, 196), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3726 {"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3727 {"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3728 {"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3729 {"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3730 {"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3731 {"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3732 {"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3733 {"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3734 {"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3735 {"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3736 {"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3737 {"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3738 {"vmulosb", VX (4, 264), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3739 {"vrefp", VX (4, 266), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3740 {"vmrglb", VX (4, 268), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3741 {"vpkshus", VX (4, 270), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3742 {"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3743 {"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}}, 3744 {"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3745 {"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}}, 3746 {"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3747 {"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3748 {"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3749 {"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3750 {"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3751 {"vcmpnezh", VXR(4, 327,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3752 {"vmulosh", VX (4, 328), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3753 {"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3754 {"vmrglh", VX (4, 332), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3755 {"vpkswus", VX (4, 334), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3756 {"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}}, 3757 {"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}}, 3758 {"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3759 {"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3760 {"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3761 {"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3762 {"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3763 {"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3764 {"vslw", VX (4, 388), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3765 {"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3766 {"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3767 {"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3768 {"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3769 {"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3770 {"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3771 {"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3772 {"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3773 {"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3774 {"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3775 {"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3776 {"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3777 {"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3778 {"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3779 {"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3780 {"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3781 {"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3782 {"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3783 {"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3784 {"vaddubs", VX (4, 512), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3785 {"vmul10uq", VX (4, 513), VXVB_MASK, PPCVEC3, 0, {VD, VA}}, 3786 {"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}}, 3787 {"vminub", VX (4, 514), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3788 {"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3789 {"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}}, 3790 {"vsrb", VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3791 {"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}}, 3792 {"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}}, 3793 {"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3794 {"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}}, 3795 {"vmuleub", VX (4, 520), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3796 {"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}}, 3797 {"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}}, 3798 {"vrfin", VX (4, 522), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3799 {"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}}, 3800 {"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}}, 3801 {"vspltb", VX (4, 524), VXUIMM4_MASK, PPCVEC, 0, {VD, VB, UIMM4}}, 3802 {"vextractub", VX (4, 525), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, 3803 {"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}}, 3804 {"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}}, 3805 {"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3806 {"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3807 {"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3808 {"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3809 {"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3810 {"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3811 {"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3812 {"evmr", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RAB}}, 3813 {"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3814 {"evnot", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RAB}}, 3815 {"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3816 {"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, 3817 {"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3818 {"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3819 {"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3820 {"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3821 {"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3822 {"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, 3823 {"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, 3824 {"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3825 {"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, 3826 {"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3827 {"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}}, 3828 {"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, 3829 {"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}}, 3830 {"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3831 {"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3832 {"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3833 {"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3834 {"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3835 {"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3836 {"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3837 {"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3838 {"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3839 {"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, 3840 {"vadduhs", VX (4, 576), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3841 {"vmul10euq", VX (4, 577), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3842 {"vminuh", VX (4, 578), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3843 {"vsrh", VX (4, 580), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3844 {"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3845 {"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3846 {"vrfiz", VX (4, 586), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3847 {"vsplth", VX (4, 588), VXUIMM3_MASK, PPCVEC, 0, {VD, VB, UIMM3}}, 3848 {"vextractuh", VX (4, 589), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, 3849 {"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3850 {"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, 3851 {"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}}, 3852 {"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, 3853 {"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3854 {"vadduws", VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3855 {"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3856 {"evfsmadd", VX (4, 642), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3857 {"vminuw", VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3858 {"evfsmsub", VX (4, 643), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3859 {"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}}, 3860 {"vsrw", VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3861 {"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}}, 3862 {"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}}, 3863 {"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3864 {"evfssqrt", VX_RB_CONST(4, 647, 0), VX_RB_CONST_MASK, PPCEFS2, 0, {RD, RA}}, 3865 {"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3866 {"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3867 {"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3868 {"evfsnmadd", VX (4, 650), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3869 {"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3870 {"evfsnmsub", VX (4, 651), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3871 {"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3872 {"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}}, 3873 {"vextractuw", VX (4, 653), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, 3874 {"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3875 {"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3876 {"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3877 {"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}}, 3878 {"evfscfh", VX_RA_CONST(4, 657, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, 3879 {"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}}, 3880 {"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}}, 3881 {"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}}, 3882 {"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}}, 3883 {"evfscth", VX_RA_CONST(4, 661, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, 3884 {"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}}, 3885 {"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}}, 3886 {"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}}, 3887 {"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}}, 3888 {"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, 3889 {"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}}, 3890 {"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3891 {"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3892 {"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3893 {"evfsmax", VX (4, 672), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 3894 {"evfsmin", VX (4, 673), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 3895 {"evfsaddsub", VX (4, 674), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 3896 {"evfssubadd", VX (4, 675), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 3897 {"evfssum", VX (4, 676), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 3898 {"evfsdiff", VX (4, 677), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 3899 {"evfssumdiff", VX (4, 678), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 3900 {"evfsdiffsum", VX (4, 679), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 3901 {"evfsaddx", VX (4, 680), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 3902 {"evfssubx", VX (4, 681), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 3903 {"evfsaddsubx", VX (4, 682), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 3904 {"evfssubaddx", VX (4, 683), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 3905 {"evfsmulx", VX (4, 684), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 3906 {"evfsmule", VX (4, 686), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 3907 {"evfsmulo", VX (4, 687), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 3908 {"efsmax", VX (4, 688), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 3909 {"efsmin", VX (4, 689), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 3910 {"efdmax", VX (4, 696), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 3911 {"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, 3912 {"efdmin", VX (4, 697), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 3913 {"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 3914 {"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 3915 {"efsmadd", VX (4, 706), VX_MASK, PPCEFS2, 0, {RS, RA, RB}}, 3916 {"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3917 {"efsmsub", VX (4, 707), VX_MASK, PPCEFS2, 0, {RS, RA, RB}}, 3918 {"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}}, 3919 {"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3920 {"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}}, 3921 {"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}}, 3922 {"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3923 {"efssqrt", VX_RB_CONST(4, 711, 0), VX_RB_CONST_MASK,PPCEFS2, 0, {RD, RA}}, 3924 {"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3925 {"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 3926 {"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 3927 {"efsnmadd", VX (4, 714), VX_MASK, PPCEFS2, 0, {RS, RA, RB}}, 3928 {"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3929 {"efsnmsub", VX (4, 715), VX_MASK, PPCEFS2, 0, {RS, RA, RB}}, 3930 {"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3931 {"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, 3932 {"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3933 {"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3934 {"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3935 {"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}}, 3936 {"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}}, 3937 {"efscfh", VX_RA_CONST(4, 721, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, 3938 {"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}}, 3939 {"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}}, 3940 {"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}}, 3941 {"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}}, 3942 {"efscth", VX_RA_CONST(4, 725, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, 3943 {"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}}, 3944 {"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}}, 3945 {"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}}, 3946 {"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}}, 3947 {"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, 3948 {"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}}, 3949 {"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3950 {"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3951 {"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3952 {"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 3953 {"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 3954 {"efdmadd", VX (4, 738), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}}, 3955 {"efdcfuid", VX (4, 738), VX_MASK, E500|E500MC,0, {RS, RB}}, 3956 {"efdmsub", VX (4, 739), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}}, 3957 {"efdcfsid", VX (4, 739), VX_MASK, E500|E500MC,0, {RS, RB}}, 3958 {"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}}, 3959 {"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}}, 3960 {"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}}, 3961 {"efdsqrt", VX_RB_CONST(4, 743, 0), VX_RB_CONST_MASK, PPCEFS2, 0, {RD, RA}}, 3962 {"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 3963 {"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 3964 {"efdnmadd", VX (4, 746), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}}, 3965 {"efdctuidz", VX (4, 746), VX_MASK, E500|E500MC,0, {RS, RB}}, 3966 {"efdnmsub", VX (4, 747), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}}, 3967 {"efdctsidz", VX (4, 747), VX_MASK, E500|E500MC,0, {RS, RB}}, 3968 {"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3969 {"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3970 {"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3971 {"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}}, 3972 {"efdcfui", VX_RA_CONST(4, 752, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}}, 3973 {"efdcfuid", VX_RA_CONST(4, 752, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}}, 3974 {"efdcfsi", VX_RA_CONST(4, 753, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}}, 3975 {"efdcfsid", VX_RA_CONST(4, 753, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}}, 3976 {"efdcfh", VX_RA_CONST(4, 753, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, 3977 {"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}}, 3978 {"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}}, 3979 {"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}}, 3980 {"efdcth", VX_RA_CONST(4, 757, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, 3981 {"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}}, 3982 {"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}}, 3983 {"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}}, 3984 {"efdctuiz", VX_RA_CONST(4, 760, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}}, 3985 {"efdctuidz", VX_RA_CONST(4, 760, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}}, 3986 {"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, 3987 {"efdctsiz", VX_RA_CONST(4, 762, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}}, 3988 {"efdctsidz", VX_RA_CONST(4, 762, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}}, 3989 {"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3990 {"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3991 {"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3992 {"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3993 {"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3994 {"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, 3995 {"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3996 {"vminsb", VX (4, 770), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3997 {"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, 3998 {"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3999 {"vsrab", VX (4, 772), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4000 {"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, 4001 {"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 4002 {"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4003 {"vmulesb", VX (4, 776), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4004 {"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, 4005 {"vcfux", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, 4006 {"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, 4007 {"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4008 {"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, 4009 {"vinsertb", VX (4, 781), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, 4010 {"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, 4011 {"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4012 {"vpkpx", VX (4, 782), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4013 {"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, 4014 {"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}}, 4015 {"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4016 {"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}}, 4017 {"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 4018 {"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4019 {"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 4020 {"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4021 {"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 4022 {"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, 4023 {"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4024 {"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, 4025 {"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 4026 {"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4027 {"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 4028 {"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4029 {"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, 4030 {"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4031 {"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, 4032 {"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4033 {"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, 4034 {"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4035 {"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 4036 {"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4037 {"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 4038 {"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4039 {"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 4040 {"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4041 {"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 4042 {"vaddshs", VX (4, 832), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4043 {"bcdcpsgn.", VX (4, 833), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 4044 {"vminsh", VX (4, 834), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4045 {"vsrah", VX (4, 836), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4046 {"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 4047 {"vmulesh", VX (4, 840), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4048 {"vcfsx", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, 4049 {"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, 4050 {"vspltish", VX (4, 844), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, 4051 {"vinserth", VX (4, 845), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, 4052 {"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 4053 {"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}}, 4054 {"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}}, 4055 {"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, 4056 {"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, 4057 {"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, 4058 {"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, 4059 {"vaddsws", VX (4, 896), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4060 {"vminsw", VX (4, 898), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4061 {"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4062 {"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 4063 {"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4064 {"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, 4065 {"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, 4066 {"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, 4067 {"vinsertw", VX (4, 909), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, 4068 {"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4069 {"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4070 {"vminsd", VX (4, 962), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4071 {"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4072 {"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 4073 {"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4074 {"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, 4075 {"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, 4076 {"vinsertd", VX (4, 973), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, 4077 {"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 4078 {"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4079 {"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4080 {"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4081 {"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4082 {"vsububm", VX (4,1024), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4083 {"bcdadd.", VX (4,1025), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}}, 4084 {"vavgub", VX (4,1026), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4085 {"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4086 {"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4087 {"vand", VX (4,1028), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4088 {"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 4089 {"vcmpneb.", VXR(4, 7,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 4090 {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, 4091 {"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, 4092 {"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4093 {"vpmsumb", VX (4,1032), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4094 {"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4095 {"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4096 {"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4097 {"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4098 {"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4099 {"vslo", VX (4,1036), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4100 {"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4101 {"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4102 {"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4103 {"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4104 {"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 4105 {"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 4106 {"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4107 {"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4108 {"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4109 {"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4110 {"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4111 {"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4112 {"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4113 {"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4114 {"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4115 {"bcdsub.", VX (4,1089), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}}, 4116 {"vavguh", VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4117 {"evmwlssf", VX (4,1091), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 4118 {"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4119 {"vandc", VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4120 {"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 4121 {"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, 4122 {"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, 4123 {"vcmpneh.", VXR(4, 71,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 4124 {"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4125 {"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4126 {"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4127 {"vminfp", VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4128 {"evmwlsmf", VX (4,1099), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 4129 {"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4130 {"vsro", VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4131 {"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4132 {"vpkudum", VX (4,1102), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4133 {"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4134 {"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4135 {"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4136 {"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4137 {"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4138 {"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4139 {"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4140 {"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4141 {"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4142 {"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 4143 {"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 4144 {"evmwlssfa", VX (4,1123), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 4145 {"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4146 {"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4147 {"evmwlsmfa", VX (4,1131), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 4148 {"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4149 {"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4150 {"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4151 {"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4152 {"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4153 {"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4154 {"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4155 {"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4156 {"bcdus.", VX (4,1153), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 4157 {"vavguw", VX (4,1154), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4158 {"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4159 {"vmr", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VAB}}, 4160 {"vor", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4161 {"vcmpnew.", VXR(4, 135,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 4162 {"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4163 {"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 4164 {"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, 4165 {"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, 4166 {"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4167 {"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4168 {"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 4169 {"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 4170 {"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4171 {"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}}, 4172 {"bcds.", VX (4,1217), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}}, 4173 {"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}}, 4174 {"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}}, 4175 {"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}}, 4176 {"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}}, 4177 {"vxor", VX (4,1220), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4178 {"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4179 {"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 4180 {"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, 4181 {"vcmpequd.", VXR(4, 199,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4182 {"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, 4183 {"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4184 {"vpmsumd", VX (4,1224), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4185 {"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}}, 4186 {"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}}, 4187 {"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}}, 4188 {"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}}, 4189 {"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4190 {"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4191 {"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4192 {"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4193 {"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4194 {"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 4195 {"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 4196 {"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4197 {"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4198 {"bcdtrunc.", VX (4,1281), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}}, 4199 {"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4200 {"vavgsb", VX (4,1282), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4201 {"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4202 {"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4203 {"vnot", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VAB}}, 4204 {"vnor", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4205 {"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4206 {"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, 4207 {"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, 4208 {"vcmpnezb.", VXR(4, 263,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 4209 {"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4210 {"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4211 {"vcipher", VX (4,1288), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4212 {"vcipherlast", VX (4,1289), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4213 {"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4214 {"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4215 {"vgbbd", VX (4,1292), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 4216 {"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4217 {"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4218 {"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4219 {"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4220 {"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4221 {"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4222 {"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4223 {"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4224 {"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4225 {"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4226 {"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4227 {"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4228 {"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4229 {"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 4230 {"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4231 {"vavgsh", VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4232 {"evmwlssfaaw", VX (4,1347), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 4233 {"evmwhusiaa", VX (4,1348), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 4234 {"vorc", VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4235 {"evmwhssmaa", VX (4,1349), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 4236 {"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, 4237 {"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, 4238 {"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 4239 {"evmwhssfaa", VX (4,1351), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 4240 {"vncipher", VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4241 {"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4242 {"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4243 {"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4244 {"evmwlsmfaaw", VX (4,1355), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 4245 {"evmwhumiaa", VX (4,1356), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 4246 {"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4247 {"evmwhsmiaa", VX (4,1357), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 4248 {"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4249 {"evmwhsmfaa", VX (4,1359), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 4250 {"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4251 {"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4252 {"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4253 {"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4254 {"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4255 {"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4256 {"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4257 {"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4258 {"evmwhgumiaa", VX (4,1380), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 4259 {"evmwhgsmiaa", VX (4,1381), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 4260 {"evmwhgssfaa", VX (4,1383), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 4261 {"evmwhgsmfaa", VX (4,1391), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 4262 {"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4263 {"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4264 {"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4265 {"bcdctsq.", VXVA(4,1409,0), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 4266 {"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, 4267 {"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, 4268 {"bcdctn.", VXVA(4,1409,5), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 4269 {"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, 4270 {"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, 4271 {"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, 4272 {"vavgsw", VX (4,1410), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4273 {"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4274 {"vnand", VX (4,1412), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4275 {"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4276 {"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4277 {"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, 4278 {"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, 4279 {"vcmpnezw.", VXR(4, 391,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 4280 {"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4281 {"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4282 {"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4283 {"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4284 {"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4285 {"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4286 {"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4287 {"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4288 {"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4289 {"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4290 {"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4291 {"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4292 {"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4293 {"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4294 {"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4295 {"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4296 {"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}}, 4297 {"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4298 {"evmwlssfanw", VX (4,1475), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 4299 {"evmwhusian", VX (4,1476), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 4300 {"vsld", VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4301 {"evmwhssian", VX (4,1477), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 4302 {"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 4303 {"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, 4304 {"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, 4305 {"evmwhssfan", VX (4,1479), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 4306 {"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, 0, {VD, VA}}, 4307 {"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4308 {"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4309 {"evmwlsmfanw", VX (4,1483), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 4310 {"evmwhumian", VX (4,1484), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 4311 {"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 4312 {"evmwhsmian", VX (4,1485), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 4313 {"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4314 {"evmwhsmfan", VX (4,1487), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 4315 {"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4316 {"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4317 {"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4318 {"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4319 {"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4320 {"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 4321 {"evmwhgumian", VX (4,1508), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 4322 {"evmwhgsmian", VX (4,1509), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 4323 {"evmwhgssfan", VX (4,1511), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 4324 {"evmwhgsmfan", VX (4,1519), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 4325 {"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4326 {"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4327 {"vsububs", VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4328 {"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, 0, {RT, VB}}, 4329 {"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, 0, {RT, VB}}, 4330 {"vnegw", VXVA(4,1538,6), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 4331 {"vnegd", VXVA(4,1538,7), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 4332 {"vprtybw", VXVA(4,1538,8), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 4333 {"vprtybd", VXVA(4,1538,9), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 4334 {"vprtybq", VXVA(4,1538,10), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 4335 {"vextsb2w", VXVA(4,1538,16), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 4336 {"vextsh2w", VXVA(4,1538,17), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 4337 {"vextsb2d", VXVA(4,1538,24), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 4338 {"vextsh2d", VXVA(4,1538,25), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 4339 {"vextsw2d", VXVA(4,1538,26), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 4340 {"vctzb", VXVA(4,1538,28), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 4341 {"vctzh", VXVA(4,1538,29), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 4342 {"vctzw", VXVA(4,1538,30), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 4343 {"vctzd", VXVA(4,1538,31), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 4344 {"mfvscr", VX (4,1540), VXVAVB_MASK, PPCVEC, 0, {VD}}, 4345 {"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 4346 {"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, 4347 {"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, 4348 {"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4349 {"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, 4350 {"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4351 {"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC, 0, {VB}}, 4352 {"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 4353 {"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4354 {"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, 4355 {"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, 4356 {"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, 4357 {"vupkhsw", VX (4,1614), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 4358 {"vsubuws", VX (4,1664), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4359 {"vshasigmaw", VX (4,1666), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}}, 4360 {"veqv", VX (4,1668), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4361 {"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 4362 {"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, 4363 {"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, 4364 {"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4365 {"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4366 {"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, 4367 {"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}}, 4368 {"vsrd", VX (4,1732), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4369 {"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 4370 {"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, 4371 {"vcmpgtud.", VXR(4, 711,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4372 {"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, 4373 {"vupklsw", VX (4,1742), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 4374 {"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4375 {"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 4376 {"vpopcntb", VX (4,1795), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 4377 {"vsrv", VX (4,1796), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 4378 {"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 4379 {"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, 4380 {"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, 4381 {"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4382 {"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, 4383 {"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4384 {"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4385 {"vsubshs", VX (4,1856), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4386 {"vclzh", VX (4,1858), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 4387 {"vpopcnth", VX (4,1859), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 4388 {"vslv", VX (4,1860), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 4389 {"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 4390 {"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, 4391 {"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, 4392 {"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, 4393 {"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4394 {"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4395 {"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4396 {"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4397 {"vsubsws", VX (4,1920), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4398 {"vclzw", VX (4,1922), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 4399 {"vpopcntw", VX (4,1923), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 4400 {"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 4401 {"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, 4402 {"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, 4403 {"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4404 {"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4405 {"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, 4406 {"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4407 {"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4408 {"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 4409 {"vpopcntd", VX (4,1987), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 4410 {"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 4411 {"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, 4412 {"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, 4413 {"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, 4414 {"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4415 {"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4416 {"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4417 {"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4418 {"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}}, 4419 4420 {"mulli", OP(7), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, 4421 {"muli", OP(7), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, 4422 4423 {"subfic", OP(8), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, 4424 {"sfi", OP(8), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, 4425 4426 {"dozi", OP(9), OP_MASK, M601, PPCVLE, {RT, RA, SI}}, 4427 4428 {"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, UISIGNOPT}}, 4429 {"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, UISIGNOPT}}, 4430 {"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, UISIGNOPT}}, 4431 {"cmpli", OP(10), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, UISIGNOPT}}, 4432 4433 {"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, SI}}, 4434 {"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, SI}}, 4435 {"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, SI}}, 4436 {"cmpi", OP(11), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, SI}}, 4437 4438 {"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, 4439 {"ai", OP(12), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, 4440 {"subic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}}, 4441 4442 {"addic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, 4443 {"ai.", OP(13), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, 4444 {"subic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}}, 4445 4446 {"li", OP(14), DRA_MASK, PPCCOM, PPCVLE, {RT, SI}}, 4447 {"lil", OP(14), DRA_MASK, PWRCOM, PPCVLE, {RT, SI}}, 4448 {"addi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SI}}, 4449 {"cal", OP(14), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, 4450 {"subi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSI}}, 4451 {"la", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}}, 4452 4453 {"lis", OP(15), DRA_MASK, PPCCOM, PPCVLE, {RT, SISIGNOPT}}, 4454 {"liu", OP(15), DRA_MASK, PWRCOM, PPCVLE, {RT, SISIGNOPT}}, 4455 {"addis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SISIGNOPT}}, 4456 {"cau", OP(15), OP_MASK, PWRCOM, PPCVLE, {RT, RA0, SISIGNOPT}}, 4457 {"subis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSISIGNOPT}}, 4458 4459 {"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}}, 4460 {"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}}, 4461 {"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}}, 4462 {"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}}, 4463 {"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}}, 4464 {"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}}, 4465 {"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}}, 4466 {"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}}, 4467 {"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}}, 4468 {"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}}, 4469 {"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}}, 4470 {"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}}, 4471 {"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}}, 4472 {"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}}, 4473 {"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}}, 4474 {"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}}, 4475 {"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}}, 4476 {"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}}, 4477 {"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, PPCVLE, {BD}}, 4478 {"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}}, 4479 {"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}}, 4480 {"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, PPCVLE, {BD}}, 4481 {"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}}, 4482 {"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}}, 4483 {"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, PPCVLE, {BDA}}, 4484 {"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}}, 4485 {"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}}, 4486 {"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, PPCVLE, {BDA}}, 4487 4488 {"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4489 {"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4490 {"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4491 {"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4492 {"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4493 {"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4494 {"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4495 {"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4496 {"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4497 {"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4498 {"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4499 {"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4500 {"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4501 {"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4502 {"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4503 {"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4504 {"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4505 {"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4506 {"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4507 {"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4508 {"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4509 {"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4510 {"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4511 {"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4512 {"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4513 {"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4514 {"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4515 {"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4516 {"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4517 {"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4518 {"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4519 {"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4520 {"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4521 {"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4522 {"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4523 {"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4524 {"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4525 {"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4526 {"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4527 {"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4528 {"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4529 {"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4530 {"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4531 {"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4532 {"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4533 {"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4534 {"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4535 {"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4536 {"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4537 {"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4538 {"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4539 {"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4540 {"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4541 {"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4542 {"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4543 {"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4544 {"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4545 {"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4546 {"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4547 {"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4548 {"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4549 {"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4550 {"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4551 {"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4552 {"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4553 {"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}}, 4554 {"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4555 {"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4556 {"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4557 {"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4558 {"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4559 {"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}}, 4560 {"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4561 {"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4562 {"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4563 {"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4564 {"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4565 {"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}}, 4566 {"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4567 {"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4568 {"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4569 {"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4570 {"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4571 {"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}}, 4572 4573 {"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4574 {"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4575 {"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4576 {"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4577 {"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4578 {"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4579 {"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4580 {"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4581 {"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4582 {"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4583 {"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4584 {"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4585 {"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4586 {"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4587 {"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4588 {"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4589 {"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4590 {"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4591 {"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4592 {"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4593 {"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4594 {"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4595 {"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4596 {"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4597 {"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4598 {"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4599 {"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4600 {"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4601 {"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4602 {"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4603 {"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4604 {"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4605 {"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4606 {"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4607 {"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4608 {"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4609 {"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4610 {"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4611 {"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4612 {"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4613 {"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4614 {"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}}, 4615 {"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4616 {"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4617 {"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4618 {"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4619 {"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4620 {"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}}, 4621 {"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4622 {"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4623 {"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4624 {"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4625 {"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4626 {"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}}, 4627 {"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4628 {"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4629 {"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4630 {"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4631 {"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4632 {"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}}, 4633 4634 {"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, 4635 {"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, 4636 {"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4637 {"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, 4638 {"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, 4639 {"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4640 {"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, 4641 {"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, 4642 {"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4643 {"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, 4644 {"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, 4645 {"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4646 {"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, 4647 {"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, 4648 {"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4649 {"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, 4650 {"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, 4651 {"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4652 {"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, 4653 {"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, 4654 {"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4655 {"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, 4656 {"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, 4657 {"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4658 4659 {"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}}, 4660 {"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}}, 4661 {"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4662 {"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}}, 4663 {"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}}, 4664 {"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}}, 4665 {"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4666 {"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}}, 4667 {"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}}, 4668 {"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}}, 4669 {"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4670 {"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}}, 4671 {"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}}, 4672 {"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}}, 4673 {"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4674 {"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}}, 4675 4676 {"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, 4677 {"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, 4678 {"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4679 {"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, 4680 {"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, 4681 {"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4682 {"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, 4683 {"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, 4684 {"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4685 {"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, 4686 {"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, 4687 {"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4688 {"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, 4689 {"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, 4690 {"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4691 {"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, 4692 {"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, 4693 {"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4694 {"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, 4695 {"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, 4696 {"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4697 {"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, 4698 {"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, 4699 {"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4700 4701 {"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}}, 4702 {"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}}, 4703 {"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4704 {"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}}, 4705 {"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}}, 4706 {"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}}, 4707 {"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4708 {"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}}, 4709 {"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}}, 4710 {"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}}, 4711 {"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4712 {"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}}, 4713 {"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}}, 4714 {"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}}, 4715 {"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4716 {"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}}, 4717 4718 {"bc-", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}}, 4719 {"bc+", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}}, 4720 {"bc", B(16,0,0), B_MASK, COM, PPCVLE, {BO, BI, BD}}, 4721 {"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}}, 4722 {"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}}, 4723 {"bcl", B(16,0,1), B_MASK, COM, PPCVLE, {BO, BI, BD}}, 4724 {"bca-", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}}, 4725 {"bca+", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}}, 4726 {"bca", B(16,1,0), B_MASK, COM, PPCVLE, {BO, BI, BDA}}, 4727 {"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}}, 4728 {"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}}, 4729 {"bcla", B(16,1,1), B_MASK, COM, PPCVLE, {BO, BI, BDA}}, 4730 4731 {"svc", SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}}, 4732 {"scv", SC(17,0,1), SC_MASK, POWER9, PPCVLE, {SVC_LEV}}, 4733 {"svcl", SC(17,0,1), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}}, 4734 {"sc", SC(17,1,0), SC_MASK, PPC, PPCVLE, {LEV}}, 4735 {"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}}, 4736 {"svcla", SC(17,1,1), SC_MASK, POWER, PPCVLE, {SV}}, 4737 4738 {"b", B(18,0,0), B_MASK, COM, PPCVLE, {LI}}, 4739 {"bl", B(18,0,1), B_MASK, COM, PPCVLE, {LI}}, 4740 {"ba", B(18,1,0), B_MASK, COM, PPCVLE, {LIA}}, 4741 {"bla", B(18,1,1), B_MASK, COM, PPCVLE, {LIA}}, 4742 4743 {"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}}, 4744 4745 {"lnia", DX(19,2), NODX_MASK, POWER9, PPCVLE, {RT}}, 4746 {"addpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, DXD}}, 4747 {"subpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, NDXD}}, 4748 4749 {"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, 4750 {"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, 4751 {"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, 4752 {"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, 4753 {"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, 4754 {"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, 4755 {"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, 4756 {"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, 4757 {"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, 4758 {"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, 4759 {"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, 4760 {"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, 4761 {"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, 4762 {"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}}, 4763 {"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, 4764 {"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}}, 4765 {"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, 4766 {"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, 4767 {"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, 4768 {"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, 4769 {"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, 4770 {"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, 4771 {"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, 4772 {"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, 4773 4774 {"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4775 {"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4776 {"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4777 {"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4778 {"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4779 {"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4780 {"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4781 {"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4782 {"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4783 {"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4784 {"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4785 {"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4786 {"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4787 {"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4788 {"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4789 {"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4790 {"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4791 {"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4792 {"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4793 {"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4794 {"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4795 {"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4796 {"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4797 {"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4798 {"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4799 {"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4800 {"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4801 {"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4802 {"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4803 {"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4804 {"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4805 {"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4806 {"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4807 {"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4808 {"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4809 {"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4810 {"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4811 {"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4812 {"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4813 {"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4814 {"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4815 {"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4816 {"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4817 {"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4818 {"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4819 {"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4820 {"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4821 {"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4822 {"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4823 {"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4824 {"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4825 {"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4826 {"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4827 {"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4828 {"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4829 {"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4830 {"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4831 {"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4832 {"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4833 {"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4834 {"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4835 {"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4836 {"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4837 {"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4838 {"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4839 {"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4840 {"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4841 {"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4842 {"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4843 {"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4844 {"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4845 {"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4846 {"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4847 {"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4848 {"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4849 {"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4850 {"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4851 {"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4852 {"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4853 {"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4854 {"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4855 {"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4856 {"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4857 {"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4858 {"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4859 {"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4860 {"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4861 {"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4862 {"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4863 {"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4864 {"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4865 {"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4866 {"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4867 {"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4868 {"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4869 {"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4870 {"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4871 {"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4872 {"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4873 {"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4874 {"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4875 {"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4876 {"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4877 {"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4878 {"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4879 {"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4880 {"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4881 {"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4882 {"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4883 {"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4884 {"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4885 {"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4886 {"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4887 {"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4888 {"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4889 {"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4890 {"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4891 {"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4892 {"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4893 {"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4894 {"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4895 {"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4896 {"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4897 {"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4898 {"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4899 {"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4900 {"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4901 {"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4902 {"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4903 {"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4904 {"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4905 {"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4906 {"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4907 {"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4908 {"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4909 {"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4910 {"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4911 {"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4912 {"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4913 {"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4914 4915 {"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4916 {"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4917 {"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4918 {"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4919 {"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4920 {"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4921 {"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4922 {"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4923 {"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4924 {"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4925 {"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4926 {"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4927 {"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4928 {"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4929 {"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}}, 4930 {"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4931 {"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4932 {"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}}, 4933 {"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4934 {"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4935 {"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4936 {"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4937 {"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4938 {"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4939 {"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4940 {"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4941 {"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4942 {"bdnztlrl-", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4943 {"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4944 {"bdnztlrl+", XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4945 {"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4946 {"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4947 {"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4948 {"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4949 {"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4950 {"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4951 {"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4952 {"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4953 {"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}}, 4954 {"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4955 {"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4956 {"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}}, 4957 {"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4958 {"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4959 {"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4960 {"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4961 {"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4962 {"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4963 4964 {"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, 4965 {"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, 4966 {"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, 4967 {"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, 4968 {"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, 4969 {"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}}, 4970 {"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, 4971 {"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}}, 4972 4973 {"rfid", XL(19,18), 0xffffffff, PPC64, PPCVLE, {0}}, 4974 4975 {"crnot", XL(19,33), XL_MASK, PPCCOM, PPCVLE, {BT, BAB}}, 4976 {"crnor", XL(19,33), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, 4977 {"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCVLE, {0}}, 4978 4979 {"rfdi", XL(19,39), 0xffffffff, E500MC, PPCVLE, {0}}, 4980 {"rfi", XL(19,50), 0xffffffff, COM, PPCVLE, {0}}, 4981 {"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}}, 4982 4983 {"rfscv", XL(19,82), 0xffffffff, POWER9, PPCVLE, {0}}, 4984 {"rfsvc", XL(19,82), 0xffffffff, POWER, PPCVLE, {0}}, 4985 4986 {"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCVLE, {0}}, 4987 4988 {"crandc", XL(19,129), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, 4989 4990 {"rfebb", XL(19,146), XLS_MASK, POWER8, PPCVLE, {SXL}}, 4991 4992 {"isync", XL(19,150), 0xffffffff, PPCCOM, PPCVLE, {0}}, 4993 {"ics", XL(19,150), 0xffffffff, PWRCOM, PPCVLE, {0}}, 4994 4995 {"crclr", XL(19,193), XL_MASK, PPCCOM, PPCVLE, {BTAB}}, 4996 {"crxor", XL(19,193), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, 4997 4998 {"dnh", X(19,198), X_MASK, E500MC, PPCVLE, {DUI, DUIS}}, 4999 5000 {"crnand", XL(19,225), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, 5001 5002 {"crand", XL(19,257), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, 5003 5004 {"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPC476|PPCVLE, {0}}, 5005 5006 {"crset", XL(19,289), XL_MASK, PPCCOM, PPCVLE, {BTAB}}, 5007 {"creqv", XL(19,289), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, 5008 5009 {"urfid", XL(19,306), 0xffffffff, POWER9, PPCVLE, {0}}, 5010 {"stop", XL(19,370), 0xffffffff, POWER9, PPCVLE, {0}}, 5011 5012 {"doze", XL(19,402), 0xffffffff, POWER6, POWER9|PPCVLE, {0}}, 5013 5014 {"crorc", XL(19,417), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, 5015 5016 {"nap", XL(19,434), 0xffffffff, POWER6, POWER9|PPCVLE, {0}}, 5017 5018 {"crmove", XL(19,449), XL_MASK, PPCCOM, PPCVLE, {BT, BAB}}, 5019 {"cror", XL(19,449), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, 5020 5021 {"sleep", XL(19,466), 0xffffffff, POWER6, POWER9|PPCVLE, {0}}, 5022 {"rvwinkle", XL(19,498), 0xffffffff, POWER6, POWER9|PPCVLE, {0}}, 5023 5024 {"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCVLE, {0}}, 5025 {"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCVLE, {0}}, 5026 5027 {"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 5028 {"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5029 {"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 5030 {"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5031 {"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 5032 {"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5033 {"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 5034 {"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5035 {"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 5036 {"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5037 {"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 5038 {"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5039 {"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 5040 {"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5041 {"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 5042 {"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5043 {"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 5044 {"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5045 {"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 5046 {"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5047 {"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 5048 {"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5049 {"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 5050 {"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5051 {"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 5052 {"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5053 {"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 5054 {"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5055 {"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5056 {"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5057 {"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5058 {"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5059 {"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5060 {"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5061 {"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5062 {"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5063 {"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5064 {"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5065 {"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5066 {"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5067 {"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5068 {"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5069 {"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5070 {"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5071 {"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5072 {"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5073 {"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5074 {"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5075 {"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5076 {"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5077 {"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5078 {"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5079 {"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5080 {"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5081 {"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5082 {"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5083 {"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5084 {"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5085 {"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5086 {"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5087 {"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5088 {"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5089 {"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5090 {"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5091 {"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5092 {"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5093 {"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5094 {"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5095 {"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5096 {"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5097 {"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 5098 {"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5099 {"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 5100 {"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5101 {"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 5102 {"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5103 {"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 5104 {"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5105 {"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 5106 {"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5107 {"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 5108 {"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5109 {"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 5110 {"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5111 {"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 5112 {"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5113 {"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 5114 {"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5115 {"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 5116 {"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5117 {"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5118 {"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5119 {"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5120 {"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5121 {"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5122 {"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5123 {"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5124 {"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5125 {"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5126 {"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 5127 {"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5128 {"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5129 {"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5130 {"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5131 {"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5132 {"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5133 {"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5134 {"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5135 {"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5136 {"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5137 {"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5138 {"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5139 {"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5140 {"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5141 {"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5142 {"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5143 {"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5144 {"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5145 {"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5146 {"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 5147 5148 {"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 5149 {"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 5150 {"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 5151 {"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 5152 {"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 5153 {"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 5154 {"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 5155 {"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 5156 {"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 5157 {"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 5158 {"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 5159 {"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 5160 {"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 5161 {"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 5162 {"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 5163 {"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 5164 {"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 5165 {"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 5166 {"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 5167 {"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 5168 5169 {"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, 5170 {"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, 5171 {"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, 5172 {"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, 5173 {"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, 5174 {"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}}, 5175 {"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, 5176 {"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}}, 5177 5178 {"bctar-", XLYLK(19,560,0,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}}, 5179 {"bctarl-", XLYLK(19,560,0,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}}, 5180 {"bctar+", XLYLK(19,560,1,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}}, 5181 {"bctarl+", XLYLK(19,560,1,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}}, 5182 {"bctar", XLLK(19,560,0), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}}, 5183 {"bctarl", XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}}, 5184 5185 {"rlwimi", M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, 5186 {"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, 5187 5188 {"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, 5189 {"rlimi.", M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, 5190 5191 {"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}}, 5192 {"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}}, 5193 {"rlwinm", M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, 5194 {"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, 5195 {"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}}, 5196 {"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}}, 5197 {"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, 5198 {"rlinm.", M(21,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, 5199 5200 {"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}}, 5201 {"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}}, 5202 5203 {"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}}, 5204 {"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, 5205 {"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, 5206 {"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}}, 5207 {"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, 5208 {"rlnm.", M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, 5209 5210 {"nop", OP(24), 0xffffffff, PPCCOM, PPCVLE, {0}}, 5211 {"ori", OP(24), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, 5212 {"oril", OP(24), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, 5213 5214 {"oris", OP(25), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, 5215 {"oriu", OP(25), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, 5216 5217 {"xnop", OP(26), 0xffffffff, PPCCOM, PPCVLE, {0}}, 5218 {"xori", OP(26), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, 5219 {"xoril", OP(26), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, 5220 5221 {"xoris", OP(27), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, 5222 {"xoriu", OP(27), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, 5223 5224 {"andi.", OP(28), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, 5225 {"andil.", OP(28), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, 5226 5227 {"andis.", OP(29), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, 5228 {"andiu.", OP(29), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, 5229 5230 {"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}}, 5231 {"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}}, 5232 {"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, 5233 {"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}}, 5234 {"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}}, 5235 {"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, 5236 5237 {"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}}, 5238 {"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}}, 5239 5240 {"rldic", MD(30,2,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, 5241 {"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, 5242 5243 {"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, 5244 {"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, 5245 5246 {"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}}, 5247 {"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}}, 5248 {"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}}, 5249 {"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}}, 5250 5251 {"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}}, 5252 {"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}}, 5253 5254 {"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}}, 5255 {"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}}, 5256 {"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}}, 5257 {"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}}, 5258 5259 {"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, 0, {RA, RB}}, 5260 {"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, 0, {RA, RB}}, 5261 {"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, 0, {RA, RB}}, 5262 {"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, 0, {RA, RB}}, 5263 {"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, 0, {RA, RB}}, 5264 {"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, 0, {RA, RB}}, 5265 {"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, 0, {RA, RB}}, 5266 {"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, 0, {RA, RB}}, 5267 {"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, 0, {RA, RB}}, 5268 {"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, 0, {RA, RB}}, 5269 {"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, 0, {RA, RB}}, 5270 {"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, 0, {RA, RB}}, 5271 {"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, 0, {RA, RB}}, 5272 {"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, 0, {RA, RB}}, 5273 {"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, 0, {RA, RB}}, 5274 {"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, 0, {RA, RB}}, 5275 {"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, 0, {RA, RB}}, 5276 {"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, 0, {RA, RB}}, 5277 {"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, 0, {RA, RB}}, 5278 {"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, 0, {RA, RB}}, 5279 {"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, 0, {RA, RB}}, 5280 {"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, 0, {RA, RB}}, 5281 {"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, 0, {RA, RB}}, 5282 {"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, 0, {RA, RB}}, 5283 {"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, 0, {RA, RB}}, 5284 {"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, 0, {RA, RB}}, 5285 {"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, 0, {RA, RB}}, 5286 {"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, 0, {RA, RB}}, 5287 {"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, 0, {0}}, 5288 {"twu", XTO(31,4,TOU), XTO_MASK, PPCCOM, 0, {RA, RB}}, 5289 {"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, 0, {RA, RB}}, 5290 {"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}}, 5291 {"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}}, 5292 5293 {"lvsl", X(31,6), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, 5294 {"lvebx", X(31,7), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, 5295 {"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 5296 5297 {"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5298 {"sf", XO(31,8,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5299 {"subc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, 5300 {"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5301 {"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5302 {"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, 5303 5304 {"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, 5305 {"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, 5306 5307 {"addc", XO(31,10,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5308 {"a", XO(31,10,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5309 {"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5310 {"a.", XO(31,10,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5311 5312 {"mulhwu", XO(31,11,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, 5313 {"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, 5314 5315 {"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}}, 5316 5317 {"isellt", X(31,15), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, 5318 5319 {"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, 0, {0}}, 5320 {"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC|PPCA2, 0, {0}}, 5321 {"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, 0, {RA0, RB}}, 5322 {"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, 0, {T, RA0, RB}}, 5323 5324 {"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, COM, 0, {RT, FXM4}}, 5325 {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, 0, {RT, FXM}}, 5326 5327 {"lwarx", X(31,20), XEH_MASK, PPC, 0, {RT, RA0, RB, EH}}, 5328 5329 {"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}}, 5330 5331 {"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, 0, {CT, RA0, RB}}, 5332 5333 {"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}}, 5334 {"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}}, 5335 5336 {"slw", XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, 5337 {"sl", XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, 5338 {"slw.", XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, 5339 {"sl.", XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, 5340 5341 {"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, 0, {RA, RS}}, 5342 {"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, 0, {RA, RS}}, 5343 {"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, 0, {RA, RS}}, 5344 {"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, 0, {RA, RS}}, 5345 5346 {"sld", XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}}, 5347 {"sld.", XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}}, 5348 5349 {"and", XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}}, 5350 {"and.", XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}}, 5351 5352 {"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}}, 5353 {"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}}, 5354 5355 {"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, 5356 5357 {"waitasec", X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}}, 5358 {"wait", X(31,30), XWC_MASK, POWER9, 0, {WC}}, 5359 5360 {"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, 5361 5362 {"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}}, 5363 {"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}}, 5364 {"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}}, 5365 {"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}}, 5366 5367 {"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, 5368 {"lvehx", X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, 5369 {"lhfcmx", APU(31,39,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 5370 5371 {"mviwsplt", X(31,46), X_MASK, E6500, 0, {VD, RA, RB}}, 5372 5373 {"iselgt", X(31,47), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, 5374 5375 {"lvewx", X(31,71), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, 5376 5377 {"addg6s", XO(31,74,0,0), XO_MASK, POWER6, 0, {RT, RA, RB}}, 5378 5379 {"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}}, 5380 5381 {"iseleq", X(31,79), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, 5382 5383 {"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, CRB}}, 5384 5385 {"subf", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, 5386 {"sub", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RB, RA}}, 5387 {"subf.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, 5388 {"sub.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RB, RA}}, 5389 5390 {"mfvsrd", X(31,51), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}}, 5391 {"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}}, 5392 {"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}}, 5393 {"eratilx", X(31,51), X_MASK, PPCA2, 0, {ERAT_T, RA, RB}}, 5394 5395 {"lbarx", X(31,52), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}}, 5396 5397 {"ldux", X(31,53), X_MASK, PPC64, 0, {RT, RAL, RB}}, 5398 5399 {"dcbst", X(31,54), XRT_MASK, PPC, 0, {RA0, RB}}, 5400 5401 {"lwzux", X(31,55), X_MASK, PPCCOM, 0, {RT, RAL, RB}}, 5402 {"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}}, 5403 5404 {"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, 0, {RA, RS}}, 5405 {"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, 0, {RA, RS}}, 5406 5407 {"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}}, 5408 {"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}}, 5409 5410 {"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, 0, {0}}, 5411 {"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, 0, {0}}, 5412 {"wait", X(31,62), XWC_MASK, E500MC|PPCA2, 0, {WC}}, 5413 5414 {"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, 5415 5416 {"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, 0, {RA, RB}}, 5417 {"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, 0, {RA, RB}}, 5418 {"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, 0, {RA, RB}}, 5419 {"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, 0, {RA, RB}}, 5420 {"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, 0, {RA, RB}}, 5421 {"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, 0, {RA, RB}}, 5422 {"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, 0, {RA, RB}}, 5423 {"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, 0, {RA, RB}}, 5424 {"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, 0, {RA, RB}}, 5425 {"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, 0, {RA, RB}}, 5426 {"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, 0, {RA, RB}}, 5427 {"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, 0, {RA, RB}}, 5428 {"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, 0, {RA, RB}}, 5429 {"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, 0, {RA, RB}}, 5430 {"tdu", XTO(31,68,TOU), XTO_MASK, PPC64, 0, {RA, RB}}, 5431 {"td", X(31,68), X_MASK, PPC64, 0, {TO, RA, RB}}, 5432 5433 {"lwfcmx", APU(31,71,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 5434 {"mulhd", XO(31,73,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, 5435 {"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, 5436 5437 {"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, 5438 {"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, 5439 5440 {"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA, RS, RB}}, 5441 {"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA, RS, RB}}, 5442 5443 {"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, 0, {SR, RS}}, 5444 5445 {"mfmsr", X(31,83), XRARB_MASK, COM, 0, {RT}}, 5446 5447 {"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}}, 5448 5449 {"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}}, 5450 {"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L2OPT}}, 5451 5452 {"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}}, 5453 5454 {"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, 5455 5456 {"dni", XRC(31,97,1), XRB_MASK, E6500, 0, {DUI, DCTL}}, 5457 5458 {"lvx", X(31,103), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, 5459 {"lqfcmx", APU(31,103,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 5460 5461 {"neg", XO(31,104,0,0), XORB_MASK, COM, 0, {RT, RA}}, 5462 {"neg.", XO(31,104,0,1), XORB_MASK, COM, 0, {RT, RA}}, 5463 5464 {"mul", XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, 5465 {"mul.", XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, 5466 5467 {"mvidsplt", X(31,110), X_MASK, E6500, 0, {VD, RA, RB}}, 5468 5469 {"mtsrdin", X(31,114), XRA_MASK, PPC64, 0, {RS, RB}}, 5470 5471 {"mffprwz", X(31,115), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}}, 5472 {"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}}, 5473 {"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}}, 5474 5475 {"lharx", X(31,116), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}}, 5476 5477 {"clf", X(31,118), XTO_MASK, POWER, 0, {RA, RB}}, 5478 5479 {"lbzux", X(31,119), X_MASK, COM, 0, {RT, RAL, RB}}, 5480 5481 {"popcntb", X(31,122), XRB_MASK, POWER5, 0, {RA, RS}}, 5482 5483 {"not", XRC(31,124,0), X_MASK, COM, 0, {RA, RSB}}, 5484 {"nor", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}}, 5485 {"not.", XRC(31,124,1), X_MASK, COM, 0, {RA, RSB}}, 5486 {"nor.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}}, 5487 5488 {"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, 5489 5490 {"setb", X(31,128), XRB_MASK|(3<<16), POWER9, 0, {RT, BFA}}, 5491 5492 {"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RS}}, 5493 5494 {"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, 5495 5496 {"stvebx", X(31,135), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, 5497 {"stbfcmx", APU(31,135,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 5498 5499 {"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5500 {"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5501 {"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5502 {"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5503 5504 {"adde", XO(31,138,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5505 {"ae", XO(31,138,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5506 {"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5507 {"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5508 5509 {"stxsiwx", X(31,140), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}}, 5510 5511 {"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK, POWER8, 0, {RB}}, 5512 {"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}}, 5513 5514 {"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, 0, {RS}}, 5515 {"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, 0, {FXM, RS}}, 5516 {"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, 0, {FXM, RS}}, 5517 5518 {"mtmsr", X(31,146), XRLARB_MASK, COM, 0, {RS, A_L}}, 5519 5520 {"mtsle", X(31,147), XRTLRARB_MASK, POWER8, 0, {L}}, 5521 5522 {"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}}, 5523 {"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}}, 5524 5525 {"stdx", X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}}, 5526 5527 {"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}}, 5528 5529 {"stwx", X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}}, 5530 {"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}}, 5531 5532 {"slq", XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}}, 5533 {"slq.", XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}}, 5534 5535 {"sle", XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}}, 5536 {"sle.", XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}}, 5537 5538 {"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}}, 5539 5540 {"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, 5541 5542 {"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, 5543 5544 {"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {E}}, 5545 5546 {"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, 5547 5548 {"stvehx", X(31,167), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, 5549 {"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 5550 5551 {"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}}, 5552 5553 {"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, 0, {RB}}, 5554 {"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}}, 5555 5556 {"mtmsrd", X(31,178), XRLARB_MASK, PPC64, 0, {RS, A_L}}, 5557 5558 {"mtvsrd", X(31,179), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}}, 5559 {"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, 5560 {"mtvrd", X(31,179)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}}, 5561 {"eratre", X(31,179), X_MASK, PPCA2, 0, {RT, RA, WS}}, 5562 5563 {"stdux", X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}}, 5564 5565 {"stqcx.", XRC(31,182,1), X_MASK|Q_MASK, POWER8, 0, {RSQ, RA0, RB}}, 5566 {"wchkall", X(31,182), X_MASK, PPCA2, 0, {OBF}}, 5567 5568 {"stwux", X(31,183), X_MASK, PPCCOM, 0, {RS, RAS, RB}}, 5569 {"stux", X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, 5570 5571 {"sliq", XRC(31,184,0), X_MASK, M601, 0, {RA, RS, SH}}, 5572 {"sliq.", XRC(31,184,1), X_MASK, M601, 0, {RA, RS, SH}}, 5573 5574 {"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}}, 5575 5576 {"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}}, 5577 5578 {"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}}, 5579 5580 {"stvewx", X(31,199), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, 5581 {"stwfcmx", APU(31,199,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 5582 5583 {"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, 5584 {"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, 5585 {"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, 5586 {"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, 5587 5588 {"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, 5589 {"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, 5590 {"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, 5591 {"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, 5592 5593 {"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}}, 5594 5595 {"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}}, 5596 5597 {"mtfprwa", X(31,211), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, 5598 {"mtvrwa", X(31,211)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}}, 5599 {"mtvsrwa", X(31,211), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}}, 5600 {"eratwe", X(31,211), X_MASK, PPCA2, 0, {RS, RA, WS}}, 5601 5602 {"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}}, 5603 5604 {"stdcx.", XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}}, 5605 5606 {"stbx", X(31,215), X_MASK, COM, 0, {RS, RA0, RB}}, 5607 5608 {"sllq", XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}}, 5609 {"sllq.", XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}}, 5610 5611 {"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}}, 5612 {"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}}, 5613 5614 {"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, 5615 5616 {"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}}, 5617 5618 {"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, 5619 5620 {"stvx", X(31,231), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, 5621 {"stqfcmx", APU(31,231,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 5622 5623 {"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, 5624 {"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, 5625 {"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, 5626 {"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, 5627 5628 {"mulld", XO(31,233,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, 5629 {"mulld.", XO(31,233,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, 5630 5631 {"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, 5632 {"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, 5633 {"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, 5634 {"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, 5635 5636 {"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5637 {"muls", XO(31,235,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5638 {"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5639 {"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5640 5641 {"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}}, 5642 {"msgclr", XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}}, 5643 {"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}}, 5644 {"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}}, 5645 5646 {"mtfprwz", X(31,243), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, 5647 {"mtvrwz", X(31,243)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}}, 5648 {"mtvsrwz", X(31,243), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}}, 5649 5650 {"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, 0, {RA0, RB}}, 5651 {"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}}, 5652 {"dcbtst", X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}}, 5653 {"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}}, 5654 5655 {"stbux", X(31,247), X_MASK, COM, 0, {RS, RAS, RB}}, 5656 5657 {"slliq", XRC(31,248,0), X_MASK, M601, 0, {RA, RS, SH}}, 5658 {"slliq.", XRC(31,248,1), X_MASK, M601, 0, {RA, RS, SH}}, 5659 5660 {"bpermd", X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}}, 5661 5662 {"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, 5663 5664 {"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}}, 5665 {"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, 0, {RS, RA}}, 5666 5667 {"lvexbx", X(31,261), X_MASK, E6500, 0, {VD, RA0, RB}}, 5668 5669 {"icbt", X(31,262), XRT_MASK, PPC403, 0, {RA, RB}}, 5670 5671 {"lvepxl", X(31,263), X_MASK, E6500, 0, {VD, RA0, RB}}, 5672 5673 {"ldfcmx", APU(31,263,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 5674 {"doz", XO(31,264,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, 5675 {"doz.", XO(31,264,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, 5676 5677 {"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}}, 5678 5679 {"add", XO(31,266,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5680 {"cax", XO(31,266,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5681 {"add.", XO(31,266,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5682 {"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5683 5684 {"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}}, 5685 5686 {"lxvx", X(31,268), XX1_MASK|1<<6, PPCVSX3, 0, {XT6, RA0, RB}}, 5687 {"lxvl", X(31,269), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, 5688 5689 {"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, 0, {0}}, 5690 5691 {"tlbiel", X(31,274), X_MASK|1<<20,POWER9, 0, {RB, RSO, RIC, PRS, X_R}}, 5692 {"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, LOPT}}, 5693 5694 {"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}}, 5695 5696 {"lqarx", X(31,276), XEH_MASK|Q_MASK, POWER8, 0, {RTQ, RAX, RBX, EH}}, 5697 5698 {"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}}, 5699 {"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}}, 5700 5701 {"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, 0, {RA0, RB}}, 5702 {"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}}, 5703 {"dcbt", X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}}, 5704 {"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}}, 5705 5706 {"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}}, 5707 5708 {"cdtbcd", X(31,282), XRB_MASK, POWER6, 0, {RA, RS}}, 5709 5710 {"eqv", XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}}, 5711 {"eqv.", XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}}, 5712 5713 {"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, 5714 5715 {"mfdcrux", X(31,291), X_MASK, PPC464|PPC476, 0, {RS, RA}}, 5716 5717 {"lvexhx", X(31,293), X_MASK, E6500, 0, {VD, RA0, RB}}, 5718 {"lvepx", X(31,295), X_MASK, E6500, 0, {VD, RA0, RB}}, 5719 5720 {"lxvll", X(31,301), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, 5721 5722 {"mfbhrbe", X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}}, 5723 5724 {"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}}, 5725 {"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}}, 5726 {"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, LOPT}}, 5727 {"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}}, 5728 5729 {"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}}, 5730 5731 {"ldmx", X(31,309), X_MASK, POWER9, 0, {RT, RA0, RB}}, 5732 5733 {"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}}, 5734 5735 {"lhzux", X(31,311), X_MASK, COM, 0, {RT, RAL, RB}}, 5736 5737 {"cbcdtd", X(31,314), XRB_MASK, POWER6, 0, {RA, RS}}, 5738 5739 {"xor", XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}}, 5740 {"xor.", XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}}, 5741 5742 {"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, 5743 5744 {"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, 0, {RT}}, 5745 {"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, 0, {RT}}, 5746 {"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, 0, {RT}}, 5747 {"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, 0, {RT}}, 5748 {"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, 0, {RT}}, 5749 {"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, 0, {RT}}, 5750 {"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, 0, {RT}}, 5751 {"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, 0, {RT}}, 5752 {"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, 0, {RT}}, 5753 {"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, 0, {RT}}, 5754 {"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, 0, {RT}}, 5755 {"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, 0, {RT}}, 5756 {"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, 0, {RT}}, 5757 {"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, 0, {RT}}, 5758 {"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, 0, {RT}}, 5759 {"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, 0, {RT}}, 5760 {"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, 0, {RT}}, 5761 {"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, 0, {RT}}, 5762 {"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, 0, {RT}}, 5763 {"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, 0, {RT}}, 5764 {"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, 0, {RT}}, 5765 {"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, 0, {RT}}, 5766 {"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, 0, {RT}}, 5767 {"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, 0, {RT}}, 5768 {"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, 0, {RT}}, 5769 {"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, 0, {RT}}, 5770 {"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, 0, {RT}}, 5771 {"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, 0, {RT}}, 5772 {"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, 0, {RT}}, 5773 {"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, 0, {RT}}, 5774 {"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, 0, {RT}}, 5775 {"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, 0, {RT}}, 5776 {"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, 0, {RT}}, 5777 {"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, 0, {RT}}, 5778 {"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}}, 5779 {"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, 0, {RT, SPR}}, 5780 5781 {"lvexwx", X(31,325), X_MASK, E6500, 0, {VD, RA0, RB}}, 5782 5783 {"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}}, 5784 5785 {"div", XO(31,331,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, 5786 {"div.", XO(31,331,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, 5787 5788 {"lxvdsx", X(31,332), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, 5789 5790 {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}}, 5791 {"mftmr", X(31,366), X_MASK, PPCTMR, 0, {RT, TMR}}, 5792 5793 {"slbsync", X(31,338), 0xffffffff, POWER9, 0, {0}}, 5794 5795 {"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, 0, {RT}}, 5796 {"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, 0, {RT}}, 5797 {"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}}, 5798 {"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}}, 5799 {"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, 0, {RT}}, 5800 {"mflr", XSPR(31,339, 8), XSPR_MASK, COM, 0, {RT}}, 5801 {"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, 0, {RT}}, 5802 {"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, 0, {RT}}, 5803 {"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, 0, {RT}}, 5804 {"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}}, 5805 {"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}}, 5806 {"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1, {RT}}, 5807 {"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, 0, {RT}}, 5808 {"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}}, 5809 {"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, 0, {RT}}, 5810 {"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, 0, {RT}}, 5811 {"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, 0, {RT}}, 5812 {"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, 0, {RT}}, 5813 {"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, 0, {RT}}, 5814 {"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, 0, {RT}}, 5815 {"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, 0, {RT}}, 5816 {"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, 0, {RT}}, 5817 {"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, 0, {RT}}, 5818 {"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, 0, {RT}}, 5819 {"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, 0, {RT}}, 5820 {"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, 0, {RT}}, 5821 {"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, 0, {RT}}, 5822 {"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, 0, {RT}}, 5823 {"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, 0, {RT}}, 5824 {"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, 0, {RT}}, 5825 {"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, 0, {RT}}, 5826 {"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, 0, {RT}}, 5827 {"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, 0, {RT}}, 5828 {"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, 0, {RT}}, 5829 {"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, 0, {RT}}, 5830 {"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, 0, {RT}}, 5831 {"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, 0, {RT}}, 5832 {"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, 0, {RT}}, 5833 {"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, 0, {RT}}, 5834 {"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, 0, {RT}}, 5835 {"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, 0, {RT}}, 5836 {"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, 0, {RT}}, 5837 {"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, 0, {RT, SPRG}}, 5838 {"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, 5839 {"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, 5840 {"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, 5841 {"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, 5842 {"mftbu", XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE, 0, {RT}}, 5843 {"mftb", X(31,339), X_MASK, POWER4|BOOKE, 0, {RT, TBR}}, 5844 {"mftbl", XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE, 0, {RT}}, 5845 {"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, 0, {RT}}, 5846 {"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, 0, {RT}}, 5847 {"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, 0, {RT}}, 5848 {"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, 0, {RT}}, 5849 {"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, 0, {RT}}, 5850 {"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}}, 5851 {"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, 0, {RT}}, 5852 {"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, 0, {RT}}, 5853 {"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, 0, {RT}}, 5854 {"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, 0, {RT}}, 5855 {"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, 0, {RT}}, 5856 {"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, 0, {RT}}, 5857 {"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, 0, {RT}}, 5858 {"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, 0, {RT}}, 5859 {"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, 0, {RT}}, 5860 {"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, 0, {RT}}, 5861 {"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, 0, {RT}}, 5862 {"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, 0, {RT}}, 5863 {"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, 0, {RT}}, 5864 {"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, 0, {RT}}, 5865 {"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, 0, {RT}}, 5866 {"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, 0, {RT}}, 5867 {"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, 0, {RT}}, 5868 {"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, 0, {RT}}, 5869 {"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, 0, {RT}}, 5870 {"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, 0, {RT}}, 5871 {"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, 0, {RT}}, 5872 {"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, 0, {RT}}, 5873 {"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, 0, {RT}}, 5874 {"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, 0, {RT}}, 5875 {"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, 0, {RT}}, 5876 {"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, 0, {RT}}, 5877 {"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, 0, {RT}}, 5878 {"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, 0, {RT}}, 5879 {"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, 0, {RT}}, 5880 {"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, 0, {RT}}, 5881 {"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, 0, {RT}}, 5882 {"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, 0, {RT}}, 5883 {"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, 0, {RT}}, 5884 {"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, 0, {RT}}, 5885 {"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, 0, {RT}}, 5886 {"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE|E6500, 0, {RT}}, 5887 {"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE|E6500, 0, {RT}}, 5888 {"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, 0, {RT}}, 5889 {"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, 0, {RT}}, 5890 {"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, 5891 {"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, 5892 {"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, 5893 {"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, 5894 {"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, 0, {RT}}, 5895 {"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, 0, {RT}}, 5896 {"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, 0, {RT}}, 5897 {"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, 0, {RT}}, 5898 {"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, 0, {RT}}, 5899 {"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, 0, {RT}}, 5900 {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, 0, {RT}}, 5901 {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, 0, {RT}}, 5902 {"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, 0, {RT}}, 5903 {"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}}, 5904 {"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, 0, {RT}}, 5905 {"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, 0, {RT}}, 5906 {"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, 0, {RT}}, 5907 {"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, 0, {RT}}, 5908 {"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, 0, {RT}}, 5909 {"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, 0, {RT}}, 5910 {"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, 0, {RT}}, 5911 {"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, 0, {RT}}, 5912 {"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, 0, {RT}}, 5913 {"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, 0, {RT}}, 5914 {"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, 0, {RT}}, 5915 {"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, 0, {RT}}, 5916 {"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, 0, {RT}}, 5917 {"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, 0, {RT}}, 5918 {"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, 0, {RT}}, 5919 {"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, 0, {RT}}, 5920 {"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, 0, {RT}}, 5921 {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, 0, {RT}}, 5922 {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, 0, {RT}}, 5923 {"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, 0, {RT}}, 5924 {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, 0, {RT}}, 5925 {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, 0, {RT}}, 5926 {"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, 0, {RT}}, 5927 {"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, 0, {RT}}, 5928 {"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, 0, {RT}}, 5929 {"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, 0, {RT}}, 5930 {"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, 0, {RT}}, 5931 {"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, 0, {RT}}, 5932 {"mfppr", XSPR(31,339,896), XSPR_MASK, POWER7, 0, {RT}}, 5933 {"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER7, 0, {RT}}, 5934 {"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, 0, {RT}}, 5935 {"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, 0, {RT}}, 5936 {"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, 0, {RT}}, 5937 {"mficdbtr", XSPR(31,339,927), XSPR_MASK, TITAN, 0, {RT}}, 5938 {"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, 0, {RT}}, 5939 {"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, 0, {RT}}, 5940 {"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, 0, {RT}}, 5941 {"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, 0, {RT}}, 5942 {"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, 0, {RT}}, 5943 {"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, 0, {RT}}, 5944 {"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, 0, {RT}}, 5945 {"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, 0, {RT}}, 5946 {"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, 0, {RT}}, 5947 {"mfmmucr", XSPR(31,339,946), XSPR_MASK, TITAN, 0, {RT}}, 5948 {"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, 0, {RT}}, 5949 {"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, 0, {RT}}, 5950 {"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, 0, {RT}}, 5951 {"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, 0, {RT}}, 5952 {"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, 0, {RT}}, 5953 {"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, 0, {RT}}, 5954 {"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, 0, {RT}}, 5955 {"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, 0, {RT}}, 5956 {"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, 0, {RT}}, 5957 {"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, 0, {RT}}, 5958 {"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, 0, {RT}}, 5959 {"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, 0, {RT}}, 5960 {"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, 0, {RT}}, 5961 {"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, 0, {RT}}, 5962 {"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, 0, {RT}}, 5963 {"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, 0, {RT}}, 5964 {"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, 0, {RT}}, 5965 {"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, 0, {RT}}, 5966 {"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, 0, {RT}}, 5967 {"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, 0, {RT}}, 5968 {"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, 0, {RT}}, 5969 {"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, 0, {RT}}, 5970 {"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, 0, {RT}}, 5971 {"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, 0, {RT}}, 5972 {"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, 0, {RT}}, 5973 {"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, 0, {RT}}, 5974 {"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, 0, {RT}}, 5975 {"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, 0, {RT}}, 5976 {"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, 0, {RT}}, 5977 {"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, 0, {RT}}, 5978 {"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, 0, {RT}}, 5979 {"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, 0, {RS}}, 5980 {"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, 0, {RT}}, 5981 {"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, 0, {RT}}, 5982 {"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, 0, {RT}}, 5983 {"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, 0, {RT}}, 5984 {"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, 0, {RT}}, 5985 {"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, 0, {RT}}, 5986 {"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, 0, {RT}}, 5987 {"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, 0, {RT}}, 5988 {"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, 0, {RT}}, 5989 {"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, 0, {RT}}, 5990 {"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, 0, {RT}}, 5991 {"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, 0, {RT}}, 5992 {"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, 0, {RT}}, 5993 {"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, 0, {RT}}, 5994 {"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, 0, {RT}}, 5995 {"mfspr", X(31,339), X_MASK, COM, 0, {RT, SPR}}, 5996 5997 {"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}}, 5998 5999 {"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, 6000 6001 {"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}}, 6002 6003 {"lvxl", X(31,359), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, 6004 6005 {"abs", XO(31,360,0,0), XORB_MASK, M601, 0, {RT, RA}}, 6006 {"abs.", XO(31,360,0,1), XORB_MASK, M601, 0, {RT, RA}}, 6007 6008 {"divs", XO(31,363,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, 6009 {"divs.", XO(31,363,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, 6010 6011 {"lxvwsx", X(31,364), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, 6012 6013 {"tlbia", X(31,370), 0xffffffff, PPC, E500|TITAN, {0}}, 6014 6015 {"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}}, 6016 {"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}}, 6017 {"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371|POWER4, {RT}}, 6018 6019 {"lwaux", X(31,373), X_MASK, PPC64, 0, {RT, RAL, RB}}, 6020 6021 {"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, 6022 6023 {"lhaux", X(31,375), X_MASK, COM, 0, {RT, RAL, RB}}, 6024 6025 {"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}}, 6026 6027 {"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}}, 6028 {"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, 0, {RA, RS}}, 6029 6030 {"stvexbx", X(31,389), X_MASK, E6500, 0, {VS, RA0, RB}}, 6031 6032 {"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, 6033 {"stdfcmx", APU(31,391,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 6034 6035 {"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 6036 {"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 6037 {"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 6038 {"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 6039 6040 {"stxvx", X(31,396), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, 6041 {"stxvl", X(31,397), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, 6042 6043 {"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}}, 6044 6045 {"slbmte", X(31,402), XRA_MASK, PPC64, 0, {RS, RB}}, 6046 6047 {"mtvsrws", X(31,403), XX1RB_MASK, PPCVSX3, 0, {XT6, RA}}, 6048 6049 {"pbt.", XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}}, 6050 6051 {"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}}, 6052 {"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}}, 6053 6054 {"sthx", X(31,407), X_MASK, COM, 0, {RS, RA0, RB}}, 6055 6056 {"orc", XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}}, 6057 {"orc.", XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}}, 6058 6059 {"sthepx", X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, 6060 6061 {"mtdcrux", X(31,419), X_MASK, PPC464|PPC476, 0, {RA, RS}}, 6062 6063 {"stvexhx", X(31,421), X_MASK, E6500, 0, {VS, RA0, RB}}, 6064 6065 {"dcblq.", XRC(31,422,1), X_MASK, E6500, 0, {CT, RA0, RB}}, 6066 6067 {"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 6068 {"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 6069 {"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 6070 {"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 6071 6072 {"stxvll", X(31,429), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, 6073 6074 {"clrbhrb", X(31,430), 0xffffffff, POWER8, 0, {0}}, 6075 6076 {"slbie", X(31,434), XRTRA_MASK, PPC64, 0, {RB}}, 6077 6078 {"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, 6079 6080 {"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}}, 6081 6082 {"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}}, 6083 6084 {"mdors", 0x7f9ce378, 0xffffffff, E500MC, 0, {0}}, 6085 6086 {"miso", 0x7f5ad378, 0xffffffff, E6500, 0, {0}}, 6087 6088 /* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for 6089 "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */ 6090 {"yield", 0x7f7bdb78, 0xffffffff, POWER7, 0, {0}}, 6091 {"mdoio", 0x7fbdeb78, 0xffffffff, POWER7, 0, {0}}, 6092 {"mdoom", 0x7fdef378, 0xffffffff, POWER7, 0, {0}}, 6093 {"mr", XRC(31,444,0), X_MASK, COM, 0, {RA, RSB}}, 6094 {"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}}, 6095 {"mr.", XRC(31,444,1), X_MASK, COM, 0, {RA, RSB}}, 6096 {"or.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}}, 6097 6098 {"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, 0, {RS}}, 6099 {"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, 0, {RS}}, 6100 {"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, 0, {RS}}, 6101 {"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, 0, {RS}}, 6102 {"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, 0, {RS}}, 6103 {"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, 0, {RS}}, 6104 {"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, 0, {RS}}, 6105 {"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, 0, {RS}}, 6106 {"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, 0, {RS}}, 6107 {"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, 0, {RS}}, 6108 {"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, 0, {RS}}, 6109 {"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, 0, {RS}}, 6110 {"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, 0, {RS}}, 6111 {"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, 0, {RS}}, 6112 {"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, 0, {RS}}, 6113 {"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, 0, {RS}}, 6114 {"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, 0, {RS}}, 6115 {"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, 0, {RS}}, 6116 {"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, 0, {RS}}, 6117 {"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, 0, {RS}}, 6118 {"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, 0, {RS}}, 6119 {"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, 0, {RS}}, 6120 {"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, 0, {RS}}, 6121 {"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, 0, {RS}}, 6122 {"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, 0, {RS}}, 6123 {"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, 0, {RS}}, 6124 {"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, 0, {RS}}, 6125 {"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, 0, {RS}}, 6126 {"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, 0, {RS}}, 6127 {"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, 0, {RS}}, 6128 {"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, 0, {RS}}, 6129 {"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, 0, {RS}}, 6130 {"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, 0, {RS}}, 6131 {"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, 0, {RS}}, 6132 {"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}}, 6133 {"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, 0, {SPR, RS}}, 6134 6135 {"stvexwx", X(31,453), X_MASK, E6500, 0, {VS, RA0, RB}}, 6136 6137 {"dccci", X(31,454), XRT_MASK, PPC403|PPC440|PPC476|TITAN|PPCA2, 0, {RAOPT, RBOPT}}, 6138 {"dci", X(31,454), XRARB_MASK, PPCA2|PPC476, 0, {CT}}, 6139 6140 {"divdu", XO(31,457,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, 6141 {"divdu.", XO(31,457,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, 6142 6143 {"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, 6144 {"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, 6145 6146 {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}}, 6147 {"mttmr", X(31,494), X_MASK, PPCTMR, 0, {TMR, RS}}, 6148 6149 {"slbieg", X(31,466), XRA_MASK, POWER9, 0, {RS, RB}}, 6150 6151 {"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, 0, {RS}}, 6152 {"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, 0, {RS}}, 6153 {"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, 0, {RS}}, 6154 {"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, 0, {RS}}, 6155 {"mtdscr", XSPR(31,467, 17), XSPR_MASK, POWER6, 0, {RS}}, 6156 {"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, 0, {RS}}, 6157 {"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}}, 6158 {"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}}, 6159 {"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, TITAN, {RS}}, 6160 {"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, TITAN, {RS}}, 6161 {"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, 0, {RS}}, 6162 {"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, 0, {RS}}, 6163 {"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, TITAN, {RS}}, 6164 {"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, 0, {RS}}, 6165 {"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, 0, {RS}}, 6166 {"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, 0, {RS}}, 6167 {"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, 0, {RS}}, 6168 {"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, 0, {RS}}, 6169 {"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, 0, {RS}}, 6170 {"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, 0, {RS}}, 6171 {"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, 0, {RS}}, 6172 {"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, 0, {RS}}, 6173 {"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, 0, {RS}}, 6174 {"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, 0, {RS}}, 6175 {"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, 0, {RS}}, 6176 {"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, 0, {RS}}, 6177 {"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, 0, {RS}}, 6178 {"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, 0, {RS}}, 6179 {"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, 0, {RS}}, 6180 {"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, 0, {RS}}, 6181 {"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, 0, {RS}}, 6182 {"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, 0, {RS}}, 6183 {"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, 0, {RS}}, 6184 {"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, 0, {RS}}, 6185 {"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, 0, {RS}}, 6186 {"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, 0, {RS}}, 6187 {"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, 0, {RS}}, 6188 {"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, 0, {RS}}, 6189 {"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, 0, {RS}}, 6190 {"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, 0, {RS}}, 6191 {"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, 0, {RS}}, 6192 {"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, 0, {RS}}, 6193 {"mtsprg", XSPR(31,467,256), XSPRG_MASK, PPC, 0, {SPRG, RS}}, 6194 {"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, 0, {RS}}, 6195 {"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, 0, {RS}}, 6196 {"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, 0, {RS}}, 6197 {"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, 0, {RS}}, 6198 {"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, 0, {RS}}, 6199 {"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, 0, {RS}}, 6200 {"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, 0, {RS}}, 6201 {"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, 0, {RS}}, 6202 {"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, 0, {RS}}, 6203 {"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}}, 6204 {"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, 0, {RS}}, 6205 {"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, 0, {RS}}, 6206 {"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, 0, {RS}}, 6207 {"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, 0, {RS}}, 6208 {"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, 0, {RS}}, 6209 {"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, 0, {RS}}, 6210 {"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, 0, {RS}}, 6211 {"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, 0, {RS}}, 6212 {"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, 0, {RS}}, 6213 {"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, 0, {RS}}, 6214 {"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, 0, {RS}}, 6215 {"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, 0, {RS}}, 6216 {"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, 0, {RS}}, 6217 {"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, 0, {RS}}, 6218 {"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, 0, {RS}}, 6219 {"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, 0, {RS}}, 6220 {"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, 0, {RS}}, 6221 {"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, 0, {RS}}, 6222 {"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, 0, {RS}}, 6223 {"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, 0, {RS}}, 6224 {"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, 0, {RS}}, 6225 {"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, 0, {RS}}, 6226 {"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, 0, {RS}}, 6227 {"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, 0, {RS}}, 6228 {"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, 0, {RS}}, 6229 {"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, 0, {RS}}, 6230 {"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, 0, {RS}}, 6231 {"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, 0, {RS}}, 6232 {"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, 0, {RS}}, 6233 {"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, 0, {RS}}, 6234 {"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, 0, {RS}}, 6235 {"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, 0, {RS}}, 6236 {"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, 0, {RS}}, 6237 {"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, 0, {RS}}, 6238 {"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, 0, {RS}}, 6239 {"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE|E6500, 0, {RS}}, 6240 {"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE|E6500, 0, {RS}}, 6241 {"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, 0, {RS}}, 6242 {"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, 0, {RS}}, 6243 {"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, 6244 {"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, 6245 {"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, 6246 {"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, 6247 {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}}, 6248 {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}}, 6249 {"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}}, 6250 {"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, 0, {RS}}, 6251 {"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, 0, {RS}}, 6252 {"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, 0, {RS}}, 6253 {"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, 0, {RS}}, 6254 {"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, 0, {RS}}, 6255 {"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, 0, {RS}}, 6256 {"mtppr", XSPR(31,467,896), XSPR_MASK, POWER7, 0, {RS}}, 6257 {"mtppr32", XSPR(31,467,898), XSPR_MASK, POWER7, 0, {RS}}, 6258 {"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, 0, {RS}}, 6259 {"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, 0, {RS}}, 6260 {"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, 0, {RS}}, 6261 {"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, 0, {RS}}, 6262 {"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, 0, {RS}}, 6263 {"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, 0, {RS}}, 6264 {"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, 0, {RS}}, 6265 {"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, 0, {RS}}, 6266 {"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, 0, {RS}}, 6267 {"mtrmmucr", XSPR(31,467,946), XSPR_MASK, TITAN, 0, {RS}}, 6268 {"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, 0, {RS}}, 6269 {"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, 0, {RS}}, 6270 {"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, 0, {RS}}, 6271 {"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, 0, {RS}}, 6272 {"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, 0, {RS}}, 6273 {"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, 0, {RS}}, 6274 {"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, 0, {RS}}, 6275 {"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, 0, {RS}}, 6276 {"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, 0, {RS}}, 6277 {"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, 0, {RS}}, 6278 {"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, 0, {RS}}, 6279 {"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, 0, {RS}}, 6280 {"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, 0, {RS}}, 6281 {"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, 0, {RS}}, 6282 {"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, 0, {RS}}, 6283 {"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, 0, {RS}}, 6284 {"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, 0, {RS}}, 6285 {"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, 0, {RS}}, 6286 {"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, 0, {RS}}, 6287 {"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, 0, {RS}}, 6288 {"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, 0, {RS}}, 6289 {"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, 0, {RS}}, 6290 {"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, 0, {RS}}, 6291 {"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, 0, {RS}}, 6292 {"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, 0, {RS}}, 6293 {"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, 0, {RS}}, 6294 {"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, 0, {RS}}, 6295 {"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, 0, {RS}}, 6296 {"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, 0, {RS}}, 6297 {"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, 0, {RS}}, 6298 {"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, 0, {RS}}, 6299 {"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, 0, {RS}}, 6300 {"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, 0, {RS}}, 6301 {"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, 0, {RS}}, 6302 {"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, 0, {RS}}, 6303 {"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, 0, {RS}}, 6304 {"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, 0, {RS}}, 6305 {"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, 0, {RS}}, 6306 {"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, 0, {RS}}, 6307 {"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, 0, {RS}}, 6308 {"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, 0, {RS}}, 6309 {"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, 0, {RS}}, 6310 {"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, 0, {RS}}, 6311 {"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, 0, {RS}}, 6312 {"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, 0, {RS}}, 6313 {"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, 0, {RS}}, 6314 {"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, 0, {RS}}, 6315 {"mtspr", X(31,467), X_MASK, COM, 0, {SPR, RS}}, 6316 6317 {"dcbi", X(31,470), XRT_MASK, PPC, 0, {RA0, RB}}, 6318 6319 {"nand", XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}}, 6320 {"nand.", XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}}, 6321 6322 {"dsn", X(31,483), XRT_MASK, E500MC, 0, {RA, RB}}, 6323 6324 {"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2, {RT, RA0, RB}}, 6325 6326 {"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, 6327 6328 {"stvxl", X(31,487), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, 6329 6330 {"nabs", XO(31,488,0,0), XORB_MASK, M601, 0, {RT, RA}}, 6331 {"nabs.", XO(31,488,0,1), XORB_MASK, M601, 0, {RT, RA}}, 6332 6333 {"divd", XO(31,489,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, 6334 {"divd.", XO(31,489,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, 6335 6336 {"divw", XO(31,491,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, 6337 {"divw.", XO(31,491,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, 6338 6339 {"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}}, 6340 6341 {"slbia", X(31,498), 0xff1fffff, POWER6, 0, {IH}}, 6342 {"slbia", X(31,498), 0xffffffff, PPC64, POWER6, {0}}, 6343 6344 {"cli", X(31,502), XRB_MASK, POWER, 0, {RT, RA}}, 6345 6346 {"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}}, 6347 6348 {"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}}, 6349 6350 {"mcrxr", X(31,512), XBFRARB_MASK, COM, POWER7, {BF}}, 6351 6352 {"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}}, 6353 {"lbdx", X(31,515), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}}, 6354 6355 {"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}}, 6356 6357 {"lvlx", X(31,519), X_MASK, CELL, 0, {VD, RA0, RB}}, 6358 {"lbfcmux", APU(31,519,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 6359 6360 {"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 6361 {"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 6362 {"subco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, 6363 {"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 6364 {"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 6365 {"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, 6366 6367 {"addco", XO(31,10,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 6368 {"ao", XO(31,10,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 6369 {"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 6370 {"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 6371 6372 {"lxsspx", X(31,524), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}}, 6373 6374 {"clcs", X(31,531), XRB_MASK, M601, 0, {RT, RA}}, 6375 6376 {"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}}, 6377 6378 {"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, RBX}}, 6379 {"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}}, 6380 6381 {"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}}, 6382 {"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}}, 6383 6384 {"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}}, 6385 6386 {"srw", XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, 6387 {"sr", XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, 6388 {"srw.", XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, 6389 {"sr.", XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, 6390 6391 {"rrib", XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}}, 6392 {"rrib.", XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}}, 6393 6394 {"cnttzw", XRC(31,538,0), XRB_MASK, POWER9, 0, {RA, RS}}, 6395 {"cnttzw.", XRC(31,538,1), XRB_MASK, POWER9, 0, {RA, RS}}, 6396 6397 {"srd", XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}}, 6398 {"srd.", XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}}, 6399 6400 {"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}}, 6401 {"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}}, 6402 6403 {"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}}, 6404 {"lhdx", X(31,547), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}}, 6405 6406 {"lvtrx", X(31,549), X_MASK, E6500, 0, {VD, RA0, RB}}, 6407 6408 {"bbelr", X(31,550), X_MASK, PPCBRLK, 0, {0}}, 6409 6410 {"lvrx", X(31,551), X_MASK, CELL, 0, {VD, RA0, RB}}, 6411 {"lhfcmux", APU(31,551,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 6412 6413 {"subfo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, 6414 {"subo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RB, RA}}, 6415 {"subfo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, 6416 {"subo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RB, RA}}, 6417 6418 {"tlbsync", X(31,566), 0xffffffff, PPC, 0, {0}}, 6419 6420 {"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}}, 6421 6422 {"cnttzd", XRC(31,570,0), XRB_MASK, POWER9, 0, {RA, RS}}, 6423 {"cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, 0, {RA, RS}}, 6424 6425 {"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, 0, {BF}}, 6426 6427 {"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}}, 6428 {"lwdx", X(31,579), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}}, 6429 6430 {"lvtlx", X(31,581), X_MASK, E6500, 0, {VD, RA0, RB}}, 6431 6432 {"lwat", X(31,582), X_MASK, POWER9, 0, {RT, RA0, FC}}, 6433 6434 {"lwfcmux", APU(31,583,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 6435 6436 {"lxsdx", X(31,588), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, 6437 6438 {"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}}, 6439 6440 {"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, NBI}}, 6441 {"lsi", X(31,597), X_MASK, PWRCOM, 0, {RT, RA0, NB}}, 6442 6443 {"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}}, 6444 {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}}, 6445 {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, 0, {0}}, 6446 {"sync", X(31,598), XSYNCLE_MASK, E6500, 0, {LS, ESYNC}}, 6447 {"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476, {LS}}, 6448 {"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, 0, {0}}, 6449 {"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}}, 6450 {"lwsync", X(31,598), 0xffffffff, E500, 0, {0}}, 6451 {"dcs", X(31,598), 0xffffffff, PWRCOM, 0, {0}}, 6452 6453 {"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}}, 6454 6455 {"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}}, 6456 {"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, 0, {FRT, RA0, RB}}, 6457 6458 {"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}}, 6459 6460 {"lvswx", X(31,613), X_MASK, E6500, 0, {VD, RA0, RB}}, 6461 6462 {"ldat", X(31,614), X_MASK, POWER9, 0, {RT, RA0, FC}}, 6463 6464 {"lqfcmux", APU(31,615,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 6465 6466 {"nego", XO(31,104,1,0), XORB_MASK, COM, 0, {RT, RA}}, 6467 {"nego.", XO(31,104,1,1), XORB_MASK, COM, 0, {RT, RA}}, 6468 6469 {"mulo", XO(31,107,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, 6470 {"mulo.", XO(31,107,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, 6471 6472 {"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}}, 6473 6474 {"dclst", X(31,630), XRB_MASK, M601, 0, {RS, RA}}, 6475 6476 {"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}}, 6477 6478 {"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}}, 6479 {"stbdx", X(31,643), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}}, 6480 6481 {"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}}, 6482 {"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 6483 6484 {"stxsspx", X(31,652), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}}, 6485 6486 {"tbegin.", XRC(31,654,1), XRTLRARB_MASK, PPCHTM, 0, {HTM_R}}, 6487 6488 {"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 6489 {"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 6490 {"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 6491 {"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 6492 6493 {"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 6494 {"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 6495 {"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 6496 {"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 6497 6498 {"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}}, 6499 6500 {"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}}, 6501 6502 {"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}}, 6503 {"stsx", X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, 6504 6505 {"stwbrx", X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}}, 6506 {"stbrx", X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, 6507 6508 {"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}}, 6509 6510 {"srq", XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}}, 6511 {"srq.", XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}}, 6512 6513 {"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}}, 6514 {"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}}, 6515 6516 {"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}}, 6517 {"sthdx", X(31,675), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}}, 6518 6519 {"stvfrx", X(31,677), X_MASK, E6500, 0, {VS, RA0, RB}}, 6520 6521 {"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}}, 6522 {"sthfcmux", APU(31,679,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 6523 6524 {"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, 0, {0}}, 6525 {"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, 0, {HTM_A}}, 6526 6527 {"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}}, 6528 6529 {"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}, 6530 6531 {"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}}, 6532 {"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}}, 6533 6534 {"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}}, 6535 {"stwdx", X(31,707), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}}, 6536 6537 {"stvflx", X(31,709), X_MASK, E6500, 0, {VS, RA0, RB}}, 6538 6539 {"stwat", X(31,710), X_MASK, POWER9, 0, {RS, RA0, FC}}, 6540 6541 {"stwfcmux", APU(31,711,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 6542 6543 {"stxsdx", X(31,716), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}}, 6544 6545 {"tcheck", X(31,718), XRTBFRARB_MASK, PPCHTM, 0, {BF}}, 6546 6547 {"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, 6548 {"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, 6549 {"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, 6550 {"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, 6551 6552 {"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, 6553 {"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, 6554 {"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, 6555 {"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, 6556 6557 {"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}}, 6558 {"stsi", X(31,725), X_MASK, PWRCOM, 0, {RS, RA0, NB}}, 6559 6560 {"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}}, 6561 6562 {"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}}, 6563 6564 {"srlq", XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}}, 6565 {"srlq.", XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}}, 6566 6567 {"sreq", XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}}, 6568 {"sreq.", XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}}, 6569 6570 {"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}}, 6571 {"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, 0, {FRS, RA0, RB}}, 6572 6573 {"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}}, 6574 6575 {"stvswx", X(31,741), X_MASK, E6500, 0, {VS, RA0, RB}}, 6576 6577 {"stdat", X(31,742), X_MASK, POWER9, 0, {RS, RA0, FC}}, 6578 6579 {"stqfcmux", APU(31,743,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 6580 6581 {"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, 6582 {"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, 6583 {"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, 6584 {"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, 6585 6586 {"mulldo", XO(31,233,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, 6587 {"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, 6588 6589 {"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, 6590 {"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, 6591 {"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, 6592 {"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, 6593 6594 {"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 6595 {"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 6596 {"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 6597 {"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 6598 6599 {"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK,PPCHTM, 0, {0}}, 6600 {"tresume.", XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM, 0, {0}}, 6601 {"tsr.", XRC(31,750,1), XRTLRARB_MASK,PPCHTM, 0, {L}}, 6602 6603 {"darn", X(31,755), XLRAND_MASK, POWER9, 0, {RT, LRAND}}, 6604 6605 {"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, 0, {RA0, RB}}, 6606 {"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, 0, {RA0, RB}}, 6607 6608 {"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}, 6609 6610 {"srliq", XRC(31,760,0), X_MASK, M601, 0, {RA, RS, SH}}, 6611 {"srliq.", XRC(31,760,1), X_MASK, M601, 0, {RA, RS, SH}}, 6612 6613 {"lvsm", X(31,773), X_MASK, E6500, 0, {VD, RA0, RB}}, 6614 6615 {"copy", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}}, 6616 6617 {"stvepxl", X(31,775), X_MASK, E6500, 0, {VS, RA0, RB}}, 6618 {"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}}, 6619 {"ldfcmux", APU(31,775,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 6620 6621 {"dozo", XO(31,264,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, 6622 {"dozo.", XO(31,264,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, 6623 6624 {"addo", XO(31,266,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 6625 {"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 6626 {"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 6627 {"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 6628 6629 {"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}}, 6630 {"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}}, 6631 6632 {"lxvw4x", X(31,780), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, 6633 {"lxsibzx", X(31,781), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, 6634 6635 {"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, 0, {TO, RA, RB}}, 6636 6637 {"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, 0, {RA0, RB}}, 6638 6639 {"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}}, 6640 6641 {"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}}, 6642 6643 {"lfdpx", X(31,791), X_MASK|Q_MASK, POWER6, POWER7, {FRTp, RA0, RB}}, 6644 {"lfqx", X(31,791), X_MASK, POWER2, 0, {FRT, RA, RB}}, 6645 6646 {"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, 6647 {"sra", XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, 6648 {"sraw.", XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, 6649 {"sra.", XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, 6650 6651 {"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}}, 6652 {"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}}, 6653 6654 {"evlddepx", VX (31, 1598), VX_MASK, PPCSPE, 0, {RT, RA, RB}}, 6655 {"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}}, 6656 6657 {"lvtrxl", X(31,805), X_MASK, E6500, 0, {VD, RA0, RB}}, 6658 {"stvepx", X(31,807), X_MASK, E6500, 0, {VS, RA0, RB}}, 6659 {"lvrxl", X(31,807), X_MASK, CELL, 0, {VD, RA0, RB}}, 6660 6661 {"lxvh8x", X(31,812), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, 6662 {"lxsihzx", X(31,813), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, 6663 6664 {"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, 0, {TO, RA, RB}}, 6665 6666 {"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}}, 6667 6668 {"erativax", X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}}, 6669 6670 {"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}}, 6671 6672 {"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, 0, {STRM}}, 6673 6674 {"lfqux", X(31,823), X_MASK, POWER2, 0, {FRT, RA, RB}}, 6675 6676 {"srawi", XRC(31,824,0), X_MASK, PPCCOM, 0, {RA, RS, SH}}, 6677 {"srai", XRC(31,824,0), X_MASK, PWRCOM, 0, {RA, RS, SH}}, 6678 {"srawi.", XRC(31,824,1), X_MASK, PPCCOM, 0, {RA, RS, SH}}, 6679 {"srai.", XRC(31,824,1), X_MASK, PWRCOM, 0, {RA, RS, SH}}, 6680 6681 {"sradi", XS(31,413,0), XS_MASK, PPC64, 0, {RA, RS, SH6}}, 6682 {"sradi.", XS(31,413,1), XS_MASK, PPC64, 0, {RA, RS, SH6}}, 6683 6684 {"lvtlxl", X(31,837), X_MASK, E6500, 0, {VD, RA0, RB}}, 6685 6686 {"cpabort", X(31,838), XRTRARB_MASK,POWER9, 0, {0}}, 6687 6688 {"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, 6689 {"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, 6690 6691 {"lxvd2x", X(31,844), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, 6692 {"lxvx", X(31,844), XX1_MASK, POWER8, POWER9|PPCVSX3, {XT6, RA0, RB}}, 6693 6694 {"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}}, 6695 6696 {"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, 0, {RA0, RB}}, 6697 6698 {"slbiag", X(31,850), XRARB_MASK, POWER9, 0, {RS}}, 6699 {"slbmfev", X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}}, 6700 {"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}}, 6701 6702 {"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}}, 6703 6704 {"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}}, 6705 {"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, 0, {MO}}, 6706 {"eieio", XMBAR(31,854,1),0xffffffff, E500, 0, {0}}, 6707 {"eieio", X(31,854), 0xffffffff, PPCA2|PPC476, 0, {0}}, 6708 6709 {"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, 0, {FRT, RA0, RB}}, 6710 6711 {"lvswxl", X(31,869), X_MASK, E6500, 0, {VD, RA0, RB}}, 6712 6713 {"abso", XO(31,360,1,0), XORB_MASK, M601, 0, {RT, RA}}, 6714 {"abso.", XO(31,360,1,1), XORB_MASK, M601, 0, {RT, RA}}, 6715 6716 {"divso", XO(31,363,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, 6717 {"divso.", XO(31,363,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, 6718 6719 {"lxvb16x", X(31,876), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, 6720 6721 {"tabortdci.", XRC(31,878,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}}, 6722 6723 {"rmieg", X(31,882), XRTRA_MASK, POWER9, 0, {RB}}, 6724 6725 {"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}}, 6726 6727 {"msgsync", X(31,886), 0xffffffff, POWER9, 0, {0}}, 6728 6729 {"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, 0, {FRT, RA0, RB}}, 6730 6731 {"extswsli", XS(31,445,0), XS_MASK, POWER9, 0, {RA, RS, SH6}}, 6732 {"extswsli.", XS(31,445,1), XS_MASK, POWER9, 0, {RA, RS, SH6}}, 6733 6734 {"paste.", XRCL(31,902,1,1),XRT_MASK, POWER9, 0, {RA0, RB}}, 6735 6736 {"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}}, 6737 {"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 6738 6739 {"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 6740 {"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 6741 {"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 6742 {"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 6743 6744 {"stxvw4x", X(31,908), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}}, 6745 {"stxsibx", X(31,909), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, 6746 6747 {"tabort.", XRC(31,910,1), XRTRB_MASK, PPCHTM, 0, {RA}}, 6748 6749 {"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}}, 6750 {"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}}, 6751 6752 {"slbmfee", X(31,915), XRLA_MASK, POWER9, 0, {RT, RB, A_L}}, 6753 {"slbmfee", X(31,915), XRA_MASK, PPC64, POWER9, {RT, RB}}, 6754 6755 {"stwcix", X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}}, 6756 6757 {"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}}, 6758 6759 {"stfdpx", X(31,919), X_MASK|Q_MASK, POWER6, POWER7, {FRSp, RA0, RB}}, 6760 {"stfqx", X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}}, 6761 6762 {"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}}, 6763 {"sraq.", XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}}, 6764 6765 {"srea", XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}}, 6766 {"srea.", XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}}, 6767 6768 {"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, 0, {RA, RS}}, 6769 {"exts", XRC(31,922,0), XRB_MASK, PWRCOM, 0, {RA, RS}}, 6770 {"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, 0, {RA, RS}}, 6771 {"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, 0, {RA, RS}}, 6772 6773 {"evstddepx", VX (31, 1854), VX_MASK, PPCSPE, 0, {RT, RA, RB}}, 6774 {"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}}, 6775 6776 {"stvfrxl", X(31,933), X_MASK, E6500, 0, {VS, RA0, RB}}, 6777 6778 {"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, 0, {RA0, RB}}, 6779 {"wclrall", X(31,934), XRARB_MASK, PPCA2, 0, {L2}}, 6780 {"wclr", X(31,934), X_MASK, PPCA2, 0, {L2, RA0, RB}}, 6781 6782 {"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}}, 6783 6784 {"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 6785 {"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 6786 {"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 6787 {"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 6788 6789 {"stxvh8x", X(31,940), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, 6790 {"stxsihx", X(31,941), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, 6791 6792 {"treclaim.", XRC(31,942,1), XRTRB_MASK, PPCHTM, 0, {RA}}, 6793 6794 {"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}}, 6795 {"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}}, 6796 {"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}}, 6797 6798 {"sthcix", X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}}, 6799 6800 {"icswepx", XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}}, 6801 {"icswepx.", XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}}, 6802 6803 {"stfqux", X(31,951), X_MASK, POWER2, 0, {FRS, RA, RB}}, 6804 6805 {"sraiq", XRC(31,952,0), X_MASK, M601, 0, {RA, RS, SH}}, 6806 {"sraiq.", XRC(31,952,1), X_MASK, M601, 0, {RA, RS, SH}}, 6807 6808 {"extsb", XRC(31,954,0), XRB_MASK, PPC, 0, {RA, RS}}, 6809 {"extsb.", XRC(31,954,1), XRB_MASK, PPC, 0, {RA, RS}}, 6810 6811 {"stvflxl", X(31,965), X_MASK, E6500, 0, {VS, RA0, RB}}, 6812 6813 {"iccci", X(31,966), XRT_MASK, PPC403|PPC440|PPC476|TITAN|PPCA2, 0, {RAOPT, RBOPT}}, 6814 {"ici", X(31,966), XRARB_MASK, PPCA2|PPC476, 0, {CT}}, 6815 6816 {"divduo", XO(31,457,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, 6817 {"divduo.", XO(31,457,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, 6818 6819 {"divwuo", XO(31,459,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, 6820 {"divwuo.", XO(31,459,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, 6821 6822 {"stxvd2x", X(31,972), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}}, 6823 {"stxvx", X(31,972), XX1_MASK, POWER8, POWER9|PPCVSX3, {XS6, RA0, RB}}, 6824 6825 {"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}}, 6826 {"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, 0, {RT, RA}}, 6827 {"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, 0, {RT, RA}}, 6828 {"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}}, 6829 6830 {"slbfee.", XRC(31,979,1), XRA_MASK, POWER6, 0, {RT, RB}}, 6831 6832 {"stbcix", X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}}, 6833 6834 {"icbi", X(31,982), XRT_MASK, PPC, 0, {RA0, RB}}, 6835 6836 {"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}}, 6837 6838 {"extsw", XRC(31,986,0), XRB_MASK, PPC64, 0, {RA, RS}}, 6839 {"extsw.", XRC(31,986,1), XRB_MASK, PPC64, 0, {RA, RS}}, 6840 6841 {"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, 6842 6843 {"stvswxl", X(31,997), X_MASK, E6500, 0, {VS, RA0, RB}}, 6844 6845 {"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA0, RB}}, 6846 6847 {"nabso", XO(31,488,1,0), XORB_MASK, M601, 0, {RT, RA}}, 6848 {"nabso.", XO(31,488,1,1), XORB_MASK, M601, 0, {RT, RA}}, 6849 6850 {"divdo", XO(31,489,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, 6851 {"divdo.", XO(31,489,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, 6852 6853 {"divwo", XO(31,491,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, 6854 {"divwo.", XO(31,491,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, 6855 6856 {"stxvb16x", X(31,1004), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, 6857 6858 {"trechkpt.", XRC(31,1006,1), XRTRARB_MASK,PPCHTM, 0, {0}}, 6859 6860 {"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}}, 6861 6862 {"stdcix", X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}}, 6863 6864 {"dcbz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}}, 6865 {"dclz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}}, 6866 6867 {"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, 6868 6869 {"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}}, 6870 6871 {"cctpl", 0x7c210b78, 0xffffffff, CELL, 0, {0}}, 6872 {"cctpm", 0x7c421378, 0xffffffff, CELL, 0, {0}}, 6873 {"cctph", 0x7c631b78, 0xffffffff, CELL, 0, {0}}, 6874 6875 {"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, 6876 {"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, 6877 {"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, 0, {0}}, 6878 6879 {"db8cyc", 0x7f9ce378, 0xffffffff, CELL, 0, {0}}, 6880 {"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, 0, {0}}, 6881 {"db12cyc", 0x7fdef378, 0xffffffff, CELL, 0, {0}}, 6882 {"db16cyc", 0x7ffffb78, 0xffffffff, CELL, 0, {0}}, 6883 6884 {"lwz", OP(32), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}}, 6885 {"l", OP(32), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, 6886 6887 {"lwzu", OP(33), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAL}}, 6888 {"lu", OP(33), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, 6889 6890 {"lbz", OP(34), OP_MASK, COM, PPCVLE, {RT, D, RA0}}, 6891 6892 {"lbzu", OP(35), OP_MASK, COM, PPCVLE, {RT, D, RAL}}, 6893 6894 {"stw", OP(36), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}}, 6895 {"st", OP(36), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}}, 6896 6897 {"stwu", OP(37), OP_MASK, PPCCOM, PPCVLE, {RS, D, RAS}}, 6898 {"stu", OP(37), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}}, 6899 6900 {"stb", OP(38), OP_MASK, COM, PPCVLE, {RS, D, RA0}}, 6901 6902 {"stbu", OP(39), OP_MASK, COM, PPCVLE, {RS, D, RAS}}, 6903 6904 {"lhz", OP(40), OP_MASK, COM, PPCVLE, {RT, D, RA0}}, 6905 6906 {"lhzu", OP(41), OP_MASK, COM, PPCVLE, {RT, D, RAL}}, 6907 6908 {"lha", OP(42), OP_MASK, COM, PPCVLE, {RT, D, RA0}}, 6909 6910 {"lhau", OP(43), OP_MASK, COM, PPCVLE, {RT, D, RAL}}, 6911 6912 {"sth", OP(44), OP_MASK, COM, PPCVLE, {RS, D, RA0}}, 6913 6914 {"sthu", OP(45), OP_MASK, COM, PPCVLE, {RS, D, RAS}}, 6915 6916 {"lmw", OP(46), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAM}}, 6917 {"lm", OP(46), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, 6918 6919 {"stmw", OP(47), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}}, 6920 {"stm", OP(47), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}}, 6921 6922 {"lfs", OP(48), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}}, 6923 6924 {"lfsu", OP(49), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}}, 6925 6926 {"lfd", OP(50), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}}, 6927 6928 {"lfdu", OP(51), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}}, 6929 6930 {"stfs", OP(52), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}}, 6931 6932 {"stfsu", OP(53), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}}, 6933 6934 {"stfd", OP(54), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}}, 6935 6936 {"stfdu", OP(55), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}}, 6937 6938 {"lq", OP(56), OP_MASK|Q_MASK, POWER4, PPC476|PPCVLE, {RTQ, DQ, RAQ}}, 6939 {"psq_l", OP(56), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}}, 6940 {"lfq", OP(56), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}}, 6941 6942 {"lxsd", DSO(57,2), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}}, 6943 {"lxssp", DSO(57,3), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}}, 6944 {"lfdp", OP(57), OP_MASK|Q_MASK, POWER6, POWER7|PPCVLE, {FRTp, DS, RA0}}, 6945 {"psq_lu", OP(57), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}}, 6946 {"lfqu", OP(57), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}}, 6947 6948 {"ld", DSO(58,0), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}}, 6949 {"ldu", DSO(58,1), DS_MASK, PPC64, PPCVLE, {RT, DS, RAL}}, 6950 {"lwa", DSO(58,2), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}}, 6951 6952 {"dadd", XRC(59,2,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 6953 {"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 6954 6955 {"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}}, 6956 {"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}}, 6957 6958 {"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 6959 {"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 6960 6961 {"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 6962 {"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 6963 6964 {"fadds", A(59,21,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 6965 {"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 6966 6967 {"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}}, 6968 {"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}}, 6969 6970 {"fres", A(59,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, 6971 {"fres", A(59,24,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}}, 6972 {"fres.", A(59,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, 6973 {"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}}, 6974 6975 {"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}}, 6976 {"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}}, 6977 6978 {"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, 6979 {"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}}, 6980 {"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, 6981 {"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}}, 6982 6983 {"fmsubs", A(59,28,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6984 {"fmsubs.", A(59,28,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6985 6986 {"fmadds", A(59,29,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6987 {"fmadds.", A(59,29,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6988 6989 {"fnmsubs", A(59,30,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6990 {"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6991 6992 {"fnmadds", A(59,31,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6993 {"fnmadds.", A(59,31,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6994 6995 {"dmul", XRC(59,34,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 6996 {"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 6997 6998 {"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}}, 6999 {"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}}, 7000 7001 {"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}}, 7002 {"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}}, 7003 7004 {"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}}, 7005 {"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}}, 7006 7007 {"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}}, 7008 {"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}}, 7009 7010 {"drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}}, 7011 {"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}}, 7012 7013 {"dcmpo", X(59,130), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}}, 7014 7015 {"dtstex", X(59,162), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}}, 7016 {"dtstdc", Z(59,194), Z_MASK, POWER6, PPCVLE, {BF, FRA, DCM}}, 7017 {"dtstdg", Z(59,226), Z_MASK, POWER6, PPCVLE, {BF, FRA, DGM}}, 7018 7019 {"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}}, 7020 {"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}}, 7021 7022 {"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, 7023 {"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, 7024 7025 {"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, 7026 {"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, 7027 7028 {"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}}, 7029 {"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}}, 7030 7031 {"dxex", XRC(59,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, 7032 {"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, 7033 7034 {"dsub", XRC(59,514,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 7035 {"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 7036 7037 {"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 7038 {"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 7039 7040 {"dcmpu", X(59,642), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}}, 7041 7042 {"dtstsf", X(59,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}}, 7043 {"dtstsfi", X(59,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRB}}, 7044 7045 {"drsp", XRC(59,770,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, 7046 {"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, 7047 7048 {"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, 7049 {"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, 7050 7051 {"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}}, 7052 {"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}}, 7053 7054 {"fcfids", XRC(59,846,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 7055 {"fcfids.", XRC(59,846,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 7056 7057 {"diex", XRC(59,866,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 7058 {"diex.", XRC(59,866,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 7059 7060 {"fcfidus", XRC(59,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 7061 {"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 7062 7063 {"xsaddsp", XX3(60,0), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 7064 {"xsmaddasp", XX3(60,1), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 7065 {"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, SHW}}, 7066 {"xscmpeqdp", XX3(60,3), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 7067 {"xsrsqrtesp", XX2(60,10), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, 7068 {"xssqrtsp", XX2(60,11), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, 7069 {"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, XC6}}, 7070 {"xssubsp", XX3(60,8), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 7071 {"xsmaddmsp", XX3(60,9), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 7072 {"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XAB6, DMEX}}, 7073 {"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7074 {"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XAB6}}, 7075 {"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7076 {"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, DM}}, 7077 {"xscmpgtdp", XX3(60,11), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 7078 {"xsresp", XX2(60,26), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, 7079 {"xsmulsp", XX3(60,16), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 7080 {"xsmsubasp", XX3(60,17), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 7081 {"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7082 {"xscmpgedp", XX3(60,19), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 7083 {"xsdivsp", XX3(60,24), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 7084 {"xsmsubmsp", XX3(60,25), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 7085 {"xxperm", XX3(60,26), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 7086 {"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7087 {"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7088 {"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, 7089 {"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7090 {"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7091 {"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7092 {"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7093 {"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7094 {"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7095 {"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, 7096 {"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7097 {"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7098 {"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7099 {"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7100 {"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7101 {"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7102 {"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7103 {"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}}, 7104 {"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7105 {"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7106 {"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7107 {"xxpermr", XX3(60,58), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 7108 {"xscmpexpdp", XX3(60,59), XX3BF_MASK, PPCVSX3, PPCVLE, {BF, XA6, XB6}}, 7109 {"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7110 {"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, 7111 {"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7112 {"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7113 {"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7114 {"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7115 {"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7116 {"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7117 {"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7118 {"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7119 {"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7120 {"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7121 {"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7122 {"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7123 {"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7124 {"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7125 {"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7126 {"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7127 {"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7128 {"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCVLE, {XT6, XB6, UIM}}, 7129 {"xxextractuw", XX2(60,165), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}}, 7130 {"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7131 {"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7132 {"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7133 {"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7134 {"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}}, 7135 {"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7136 {"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7137 {"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7138 {"xxspltib", X(60,360), XX1_MASK|3<<19, PPCVSX3, PPCVLE, {XT6, IMM8}}, 7139 {"xxinsertw", XX2(60,181), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}}, 7140 {"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7141 {"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7142 {"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, 7143 {"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7144 {"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7145 {"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7146 {"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7147 {"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7148 {"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7149 {"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7150 {"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7151 {"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7152 {"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7153 {"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7154 {"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7155 {"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7156 {"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7157 {"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7158 {"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7159 {"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7160 {"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7161 {"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7162 {"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7163 {"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7164 {"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}}, 7165 {"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7166 {"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7167 {"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7168 {"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7169 {"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7170 {"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, 7171 {"xsmaxcdp", XX3(60,128), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 7172 {"xsnmaddasp", XX3(60,129), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 7173 {"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7174 {"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7175 {"xscvdpspn", XX2(60,267), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, 7176 {"xsmincdp", XX3(60,136), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 7177 {"xsnmaddmsp", XX3(60,137), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 7178 {"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7179 {"xsrsp", XX2(60,281), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, 7180 {"xsmaxjdp", XX3(60,144), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 7181 {"xsnmsubasp", XX3(60,145), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 7182 {"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7183 {"xscvuxdsp", XX2(60,296), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, 7184 {"xststdcsp", XX2(60,298), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}}, 7185 {"xsminjdp", XX3(60,152), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 7186 {"xsnmsubmsp", XX3(60,153), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 7187 {"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7188 {"xscvsxdsp", XX2(60,312), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, 7189 {"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7190 {"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7191 {"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7192 {"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7193 {"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7194 {"xscvspdpn", XX2(60,331), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, 7195 {"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7196 {"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7197 {"xxlorc", XX3(60,170), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 7198 {"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7199 {"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7200 {"xsxexpdp", XX2VA(60,347,0),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}}, 7201 {"xsxsigdp", XX2VA(60,347,1),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}}, 7202 {"xscvhpdp", XX2VA(60,347,16),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 7203 {"xscvdphp", XX2VA(60,347,17),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 7204 {"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7205 {"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7206 {"xxlnand", XX3(60,178), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 7207 {"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7208 {"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7209 {"xststdcdp", XX2(60,362), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}}, 7210 {"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7211 {"xxleqv", XX3(60,186), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 7212 {"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7213 {"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7214 {"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7215 {"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7216 {"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7217 {"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7218 {"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7219 {"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7220 {"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7221 {"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7222 {"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XAB6}}, 7223 {"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7224 {"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7225 {"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7226 {"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7227 {"xvtstdcsp", XX2(60,426), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}}, 7228 {"xviexpsp", XX3(60,216), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 7229 {"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7230 {"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7231 {"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7232 {"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7233 {"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7234 {"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7235 {"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7236 {"xsiexpdp", X(60,918), XX1_MASK, PPCVSX3, PPCVLE, {XT6, RA, RB}}, 7237 {"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7238 {"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7239 {"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7240 {"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7241 {"xvxexpdp", XX2VA(60,475,0),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 7242 {"xvxsigdp", XX2VA(60,475,1),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 7243 {"xxbrh", XX2VA(60,475,7),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 7244 {"xvxexpsp", XX2VA(60,475,8),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 7245 {"xvxsigsp", XX2VA(60,475,9),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 7246 {"xxbrw", XX2VA(60,475,15),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 7247 {"xxbrd", XX2VA(60,475,23),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 7248 {"xvcvhpsp", XX2VA(60,475,24),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 7249 {"xvcvsphp", XX2VA(60,475,25),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 7250 {"xxbrq", XX2VA(60,475,31),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 7251 {"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XAB6}}, 7252 {"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7253 {"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7254 {"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7255 {"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7256 {"xvtstdcdp", XX2(60,490), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}}, 7257 {"xviexpdp", XX3(60,248), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 7258 {"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 7259 {"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7260 {"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 7261 7262 {"psq_st", OP(60), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}}, 7263 {"stfq", OP(60), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}}, 7264 7265 {"lxv", DQX(61,1), DQX_MASK, PPCVSX3, PPCVLE, {XTQ6, DQ, RA0}}, 7266 {"stxv", DQX(61,5), DQX_MASK, PPCVSX3, PPCVLE, {XSQ6, DQ, RA0}}, 7267 {"stxsd", DSO(61,2), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}}, 7268 {"stxssp", DSO(61,3), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}}, 7269 {"stfdp", OP(61), OP_MASK|Q_MASK, POWER6, POWER7|PPCVLE, {FRSp, DS, RA0}}, 7270 {"psq_stu", OP(61), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}}, 7271 {"stfqu", OP(61), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}}, 7272 7273 {"std", DSO(62,0), DS_MASK, PPC64, PPCVLE, {RS, DS, RA0}}, 7274 {"stdu", DSO(62,1), DS_MASK, PPC64, PPCVLE, {RS, DS, RAS}}, 7275 {"stq", DSO(62,2), DS_MASK|Q_MASK, POWER4, PPC476|PPCVLE, {RSQ, DS, RA0}}, 7276 7277 {"fcmpu", X(63,0), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}}, 7278 7279 {"daddq", XRC(63,2,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, 7280 {"daddq.", XRC(63,2,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, 7281 7282 {"dquaq", ZRC(63,3,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}}, 7283 {"dquaq.", ZRC(63,3,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}}, 7284 7285 {"xsaddqp", XRC(63,4,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 7286 {"xsaddqpo", XRC(63,4,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 7287 7288 {"xsrqpi", ZRC(63,5,0), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}}, 7289 {"xsrqpix", ZRC(63,5,1), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}}, 7290 7291 {"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}}, 7292 {"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}}, 7293 7294 {"frsp", XRC(63,12,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 7295 {"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 7296 7297 {"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}}, 7298 {"fcir", XRC(63,14,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}}, 7299 {"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}}, 7300 {"fcir.", XRC(63,14,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}}, 7301 7302 {"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}}, 7303 {"fcirz", XRC(63,15,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}}, 7304 {"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}}, 7305 {"fcirz.", XRC(63,15,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}}, 7306 7307 {"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 7308 {"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, 7309 {"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 7310 {"fd.", A(63,18,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, 7311 7312 {"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 7313 {"fs", A(63,20,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, 7314 {"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 7315 {"fs.", A(63,20,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, 7316 7317 {"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 7318 {"fa", A(63,21,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, 7319 {"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 7320 {"fa.", A(63,21,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, 7321 7322 {"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}}, 7323 {"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}}, 7324 7325 {"fsel", A(63,23,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 7326 {"fsel.", A(63,23,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 7327 7328 {"fre", A(63,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, 7329 {"fre", A(63,24,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}}, 7330 {"fre.", A(63,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, 7331 {"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}}, 7332 7333 {"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}}, 7334 {"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}}, 7335 {"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}}, 7336 {"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}}, 7337 7338 {"frsqrte", A(63,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, 7339 {"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}}, 7340 {"frsqrte.", A(63,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, 7341 {"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}}, 7342 7343 {"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 7344 {"fms", A(63,28,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, 7345 {"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 7346 {"fms.", A(63,28,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, 7347 7348 {"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 7349 {"fma", A(63,29,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, 7350 {"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 7351 {"fma.", A(63,29,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, 7352 7353 {"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 7354 {"fnms", A(63,30,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, 7355 {"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 7356 {"fnms.", A(63,30,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, 7357 7358 {"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 7359 {"fnma", A(63,31,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, 7360 {"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 7361 {"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, 7362 7363 {"fcmpo", X(63,32), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}}, 7364 7365 {"dmulq", XRC(63,34,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, 7366 {"dmulq.", XRC(63,34,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, 7367 7368 {"drrndq", ZRC(63,35,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}}, 7369 {"drrndq.", ZRC(63,35,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}}, 7370 7371 {"xsmulqp", XRC(63,36,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 7372 {"xsmulqpo", XRC(63,36,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 7373 7374 {"xsrqpxp", Z(63,37), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}}, 7375 7376 {"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCVLE, {BT}}, 7377 {"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCVLE, {BT}}, 7378 7379 {"fneg", XRC(63,40,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 7380 {"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 7381 7382 {"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}}, 7383 7384 {"dscliq", ZRC(63,66,0), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}}, 7385 {"dscliq.", ZRC(63,66,1), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}}, 7386 7387 {"dquaiq", ZRC(63,67,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}}, 7388 {"dquaiq.", ZRC(63,67,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}}, 7389 7390 {"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCVLE, {BT}}, 7391 {"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCVLE, {BT}}, 7392 7393 {"fmr", XRC(63,72,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 7394 {"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 7395 7396 {"dscriq", ZRC(63,98,0), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}}, 7397 {"dscriq.", ZRC(63,98,1), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}}, 7398 7399 {"drintxq", ZRC(63,99,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}}, 7400 {"drintxq.", ZRC(63,99,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}}, 7401 7402 {"xscpsgnqp", X(63,100), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 7403 7404 {"ftdiv", X(63,128), XBF_MASK, POWER7, PPCVLE, {BF, FRA, FRB}}, 7405 7406 {"dcmpoq", X(63,130), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}}, 7407 7408 {"xscmpoqp", X(63,132), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}}, 7409 7410 {"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}}, 7411 {"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}}, 7412 {"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}}, 7413 {"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}}, 7414 7415 {"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 7416 {"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 7417 7418 {"fctiwu", XRC(63,142,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, 7419 {"fctiwu.", XRC(63,142,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, 7420 {"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, 7421 {"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, 7422 7423 {"ftsqrt", X(63,160), XBF_MASK|FRA_MASK, POWER7, PPCVLE, {BF, FRB}}, 7424 7425 {"dtstexq", X(63,162), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}}, 7426 7427 {"xscmpexpqp", X(63,164), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}}, 7428 7429 {"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DCM}}, 7430 {"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DGM}}, 7431 7432 {"drintnq", ZRC(63,227,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}}, 7433 {"drintnq.", ZRC(63,227,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}}, 7434 7435 {"dctqpq", XRC(63,258,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}}, 7436 {"dctqpq.", XRC(63,258,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}}, 7437 7438 {"fabs", XRC(63,264,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 7439 {"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 7440 7441 {"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, 7442 {"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, 7443 7444 {"ddedpdq", XRC(63,322,0), X_MASK|Q_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}}, 7445 {"ddedpdq.", XRC(63,322,1), X_MASK|Q_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}}, 7446 7447 {"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, 7448 {"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, 7449 7450 {"xsmaddqp", XRC(63,388,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 7451 {"xsmaddqpo", XRC(63,388,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 7452 7453 {"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, 7454 {"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, 7455 7456 {"xsmsubqp", XRC(63,420,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 7457 {"xsmsubqpo", XRC(63,420,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 7458 7459 {"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, 7460 {"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, 7461 7462 {"xsnmaddqp", XRC(63,452,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 7463 {"xsnmaddqpo", XRC(63,452,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 7464 7465 {"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, 7466 {"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, 7467 7468 {"xsnmsubqp", XRC(63,484,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 7469 {"xsnmsubqpo", XRC(63,484,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 7470 7471 {"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, 7472 {"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, 7473 7474 {"dsubq", XRC(63,514,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, 7475 {"dsubq.", XRC(63,514,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, 7476 7477 {"xssubqp", XRC(63,516,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 7478 {"xssubqpo", XRC(63,516,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 7479 7480 {"ddivq", XRC(63,546,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, 7481 {"ddivq.", XRC(63,546,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, 7482 7483 {"xsdivqp", XRC(63,548,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 7484 {"xsdivqpo", XRC(63,548,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 7485 7486 {"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}}, 7487 {"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}}, 7488 7489 {"mffsce", XMMF(63,583,0,1), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}}, 7490 {"mffscdrn", XMMF(63,583,2,4), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}}, 7491 {"mffscdrni", XMMF(63,583,2,5), XMMF_MASK|(3<<14), POWER9, PPCVLE, {FRT, DRM}}, 7492 {"mffscrn", XMMF(63,583,2,6), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}}, 7493 {"mffscrni", XMMF(63,583,2,7), XMMF_MASK|(7<<13), POWER9, PPCVLE, {FRT, RM}}, 7494 {"mffsl", XMMF(63,583,3,0), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}}, 7495 7496 {"dcmpuq", X(63,642), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}}, 7497 7498 {"xscmpuqp", X(63,644), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}}, 7499 7500 {"dtstsfq", X(63,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRBp}}, 7501 {"dtstsfiq", X(63,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRBp}}, 7502 7503 {"xststdcqp", X(63,708), X_MASK, PPCVSX3, PPCVLE, {BF, VB, DCMX}}, 7504 7505 {"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}}, 7506 {"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}}, 7507 {"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}}, 7508 {"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}}, 7509 7510 {"drdpq", XRC(63,770,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRBp}}, 7511 {"drdpq.", XRC(63,770,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRBp}}, 7512 7513 {"dcffixq", XRC(63,802,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}}, 7514 {"dcffixq.", XRC(63,802,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}}, 7515 7516 {"xsabsqp", XVA(63,804,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7517 {"xsxexpqp", XVA(63,804,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7518 {"xsnabsqp", XVA(63,804,8), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7519 {"xsnegqp", XVA(63,804,16), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7520 {"xsxsigqp", XVA(63,804,18), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7521 {"xssqrtqp", XVARC(63,804,27,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7522 {"xssqrtqpo", XVARC(63,804,27,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7523 7524 {"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, 7525 {"fctid", XRC(63,814,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, 7526 {"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, 7527 {"fctid.", XRC(63,814,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, 7528 7529 {"fctidz", XRC(63,815,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, 7530 {"fctidz", XRC(63,815,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, 7531 {"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, 7532 {"fctidz.", XRC(63,815,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, 7533 7534 {"denbcdq", XRC(63,834,0), X_MASK|Q_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}}, 7535 {"denbcdq.", XRC(63,834,1), X_MASK|Q_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}}, 7536 7537 {"xscvqpuwz", XVA(63,836,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7538 {"xscvudqp", XVA(63,836,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7539 {"xscvqpswz", XVA(63,836,9), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7540 {"xscvsdqp", XVA(63,836,10), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7541 {"xscvqpudz", XVA(63,836,17), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7542 {"xscvqpdp", XVARC(63,836,20,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7543 {"xscvqpdpo", XVARC(63,836,20,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7544 {"xscvdpqp", XVA(63,836,22), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7545 {"xscvqpsdz", XVA(63,836,25), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7546 7547 {"fmrgow", X(63,838), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}}, 7548 7549 {"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, 7550 {"fcfid", XRC(63,846,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, 7551 {"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, 7552 {"fcfid.", XRC(63,846,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, 7553 7554 {"diexq", XRC(63,866,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}}, 7555 {"diexq.", XRC(63,866,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}}, 7556 7557 {"xsiexpqp", X(63,868), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 7558 7559 {"fctidu", XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 7560 {"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 7561 7562 {"fctiduz", XRC(63,943,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 7563 {"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 7564 7565 {"fmrgew", X(63,966), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}}, 7566 7567 {"fcfidu", XRC(63,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 7568 {"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 7569 }; 7570 7571 const unsigned int powerpc_num_opcodes = 7572 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]); 7573 7574 /* The VLE opcode table. 7576 7577 The format of this opcode table is the same as the main opcode table. */ 7578 7579 const struct powerpc_opcode vle_opcodes[] = { 7580 {"se_illegal", C(0), C_MASK, PPCVLE, 0, {}}, 7581 {"se_isync", C(1), C_MASK, PPCVLE, 0, {}}, 7582 {"se_sc", C(2), C_MASK, PPCVLE, 0, {}}, 7583 {"se_blr", C_LK(2,0), C_LK_MASK, PPCVLE, 0, {}}, 7584 {"se_blrl", C_LK(2,1), C_LK_MASK, PPCVLE, 0, {}}, 7585 {"se_bctr", C_LK(3,0), C_LK_MASK, PPCVLE, 0, {}}, 7586 {"se_bctrl", C_LK(3,1), C_LK_MASK, PPCVLE, 0, {}}, 7587 {"se_rfi", C(8), C_MASK, PPCVLE, 0, {}}, 7588 {"se_rfci", C(9), C_MASK, PPCVLE, 0, {}}, 7589 {"se_rfdi", C(10), C_MASK, PPCVLE, 0, {}}, 7590 {"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}}, 7591 {"se_rfgi", C(12), C_MASK, PPCVLE, 0, {}}, 7592 {"se_not", SE_R(0,2), SE_R_MASK, PPCVLE, 0, {RX}}, 7593 {"se_neg", SE_R(0,3), SE_R_MASK, PPCVLE, 0, {RX}}, 7594 {"se_mflr", SE_R(0,8), SE_R_MASK, PPCVLE, 0, {RX}}, 7595 {"se_mtlr", SE_R(0,9), SE_R_MASK, PPCVLE, 0, {RX}}, 7596 {"se_mfctr", SE_R(0,10), SE_R_MASK, PPCVLE, 0, {RX}}, 7597 {"se_mtctr", SE_R(0,11), SE_R_MASK, PPCVLE, 0, {RX}}, 7598 {"se_extzb", SE_R(0,12), SE_R_MASK, PPCVLE, 0, {RX}}, 7599 {"se_extsb", SE_R(0,13), SE_R_MASK, PPCVLE, 0, {RX}}, 7600 {"se_extzh", SE_R(0,14), SE_R_MASK, PPCVLE, 0, {RX}}, 7601 {"se_extsh", SE_R(0,15), SE_R_MASK, PPCVLE, 0, {RX}}, 7602 {"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7603 {"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, 0, {ARX, RY}}, 7604 {"se_mfar", SE_RR(0,3), SE_RR_MASK, PPCVLE, 0, {RX, ARY}}, 7605 {"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7606 {"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7607 {"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7608 {"se_subf", SE_RR(1,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7609 {"se_cmp", SE_RR(3,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7610 {"se_cmpl", SE_RR(3,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7611 {"se_cmph", SE_RR(3,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7612 {"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7613 7614 /* by major opcode */ 7615 {"zvaddih", VX(4, 0x200), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}}, 7616 {"zvsubifh", VX(4, 0x201), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}}, 7617 {"zvaddh", VX(4, 0x204), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7618 {"zvsubfh", VX(4, 0x205), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7619 {"zvaddsubfh", VX(4, 0x206), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7620 {"zvsubfaddh", VX(4, 0x207), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7621 {"zvaddhx", VX(4, 0x20C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7622 {"zvsubfhx", VX(4, 0x20D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7623 {"zvaddsubfhx", VX(4, 0x20E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7624 {"zvsubfaddhx", VX(4, 0x20F), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7625 {"zaddwus", VX(4, 0x210), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7626 {"zsubfwus", VX(4, 0x211), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7627 {"zaddwss", VX(4, 0x212), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7628 {"zsubfwss", VX(4, 0x213), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7629 {"zvaddhus", VX(4, 0x214), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7630 {"zvsubfhus", VX(4, 0x215), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7631 {"zvaddhss", VX(4, 0x216), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7632 {"zvsubfhss", VX(4, 0x217), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7633 {"zvaddsubfhss", VX(4, 0x21A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7634 {"zvsubfaddhss", VX(4, 0x21B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7635 {"zvaddhxss", VX(4, 0x21C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7636 {"zvsubfhxss", VX(4, 0x21D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7637 {"zvaddsubfhxss", VX(4, 0x21E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7638 {"zvsubfaddhxss", VX(4, 0x21F), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7639 {"zaddheuw", VX(4, 0x220), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7640 {"zsubfheuw", VX(4, 0x221), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7641 {"zaddhesw", VX(4, 0x222), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7642 {"zsubfhesw", VX(4, 0x223), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7643 {"zaddhouw", VX(4, 0x224), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7644 {"zsubfhouw", VX(4, 0x225), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7645 {"zaddhosw", VX(4, 0x226), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7646 {"zsubfhosw", VX(4, 0x227), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7647 {"zvmergehih", VX(4, 0x22C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7648 {"zvmergeloh", VX(4, 0x22D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7649 {"zvmergehiloh", VX(4, 0x22E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7650 {"zvmergelohih", VX(4, 0x22F), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7651 {"zvcmpgthu", VX(4, 0x230), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}}, 7652 {"zvcmpgths", VX(4, 0x230), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}}, 7653 {"zvcmplthu", VX(4, 0x231), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}}, 7654 {"zvcmplths", VX(4, 0x231), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}}, 7655 {"zvcmpeqh", VX(4, 0x232), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}}, 7656 {"zpkswgshfrs", VX(4, 0x238), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7657 {"zpkswgswfrs", VX(4, 0x239), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7658 {"zvpkshgwshfrs", VX(4, 0x23A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7659 {"zvpkswshfrs", VX(4, 0x23B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7660 {"zvpkswuhs", VX(4, 0x23C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7661 {"zvpkswshs", VX(4, 0x23D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7662 {"zvpkuwuhs", VX(4, 0x23E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7663 {"zvsplatih", VX_LSP(4, 0x23F), VX_LSP_MASK, PPCLSP, 0, {RD, SIMM}}, 7664 {"zvsplatfih", VX_LSP(4, 0xA3F), VX_LSP_MASK, PPCLSP, 0, {RD, SIMM}}, 7665 {"zcntlsw", VX_LSP(4, 0x2A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 7666 {"zvcntlzh", VX_LSP(4, 0x323F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 7667 {"zvcntlsh", VX_LSP(4, 0x3A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 7668 {"znegws", VX_LSP(4, 0x4A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 7669 {"zvnegh", VX_LSP(4, 0x523F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 7670 {"zvneghs", VX_LSP(4, 0x5A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 7671 {"zvnegho", VX_LSP(4, 0x623F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 7672 {"zvneghos", VX_LSP(4, 0x6A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 7673 {"zrndwh", VX_LSP(4, 0x823F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 7674 {"zrndwhss", VX_LSP(4, 0x8A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 7675 {"zvabsh", VX_LSP(4, 0xA23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 7676 {"zvabshs", VX_LSP(4, 0xAA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 7677 {"zabsw", VX_LSP(4, 0xB23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 7678 {"zabsws", VX_LSP(4, 0xBA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 7679 {"zsatswuw", VX_LSP(4, 0xC23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 7680 {"zsatuwsw", VX_LSP(4, 0xCA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 7681 {"zsatswuh", VX_LSP(4, 0xD23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 7682 {"zsatswsh", VX_LSP(4, 0xDA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 7683 {"zvsatshuh", VX_LSP(4, 0xE23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 7684 {"zvsatuhsh", VX_LSP(4, 0xEA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 7685 {"zsatuwuh", VX_LSP(4, 0xF23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 7686 {"zsatuwsh", VX_LSP(4, 0xFA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 7687 {"zsatsduw", VX(4, 0x260), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7688 {"zsatsdsw", VX(4, 0x261), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7689 {"zsatuduw", VX(4, 0x262), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7690 {"zvselh", VX(4, 0x264), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7691 {"zxtrw", VX(4, 0x264), VX_LSP_OFF_MASK, PPCLSP, 0, {RD, RA, RB, VX_OFF}}, 7692 {"zbrminc", VX(4, 0x268), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7693 {"zcircinc", VX(4, 0x269), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7694 {"zdivwsf", VX(4, 0x26B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7695 {"zvsrhu", VX(4, 0x270), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7696 {"zvsrhs", VX(4, 0x271), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7697 {"zvsrhiu", VX(4, 0x272), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}}, 7698 {"zvsrhis", VX(4, 0x273), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}}, 7699 {"zvslh", VX(4, 0x274), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7700 {"zvrlh", VX(4, 0x275), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7701 {"zvslhi", VX(4, 0x276), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}}, 7702 {"zvrlhi", VX(4, 0x277), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}}, 7703 {"zvslhus", VX(4, 0x278), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7704 {"zvslhss", VX(4, 0x279), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7705 {"zvslhius", VX(4, 0x27A), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}}, 7706 {"zvslhiss", VX(4, 0x27B), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}}, 7707 {"zslwus", VX(4, 0x27C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7708 {"zslwss", VX(4, 0x27D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7709 {"zslwius", VX(4, 0x27E), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}}, 7710 {"zslwiss", VX(4, 0x27F), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}}, 7711 {"zaddwgui", VX(4, 0x460), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7712 {"zsubfwgui", VX(4, 0x461), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7713 {"zaddd", VX(4, 0x462), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7714 {"zsubfd", VX(4, 0x463), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7715 {"zvaddsubfw", VX(4, 0x464), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7716 {"zvsubfaddw", VX(4, 0x465), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7717 {"zvaddw", VX(4, 0x466), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7718 {"zvsubfw", VX(4, 0x467), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7719 {"zaddwgsi", VX(4, 0x468), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7720 {"zsubfwgsi", VX(4, 0x469), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7721 {"zadddss", VX(4, 0x46A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7722 {"zsubfdss", VX(4, 0x46B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7723 {"zvaddsubfwss", VX(4, 0x46C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7724 {"zvsubfaddwss", VX(4, 0x46D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7725 {"zvaddwss", VX(4, 0x46E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7726 {"zvsubfwss", VX(4, 0x46F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7727 {"zaddwgsf", VX(4, 0x470), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7728 {"zsubfwgsf", VX(4, 0x471), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7729 {"zadddus", VX(4, 0x472), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7730 {"zsubfdus", VX(4, 0x473), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7731 {"zvaddwus", VX(4, 0x476), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7732 {"zvsubfwus", VX(4, 0x477), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7733 {"zvunpkhgwsf", VX_LSP(4, 0x478), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}}, 7734 {"zvunpkhsf", VX_LSP(4, 0xC78), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}}, 7735 {"zvunpkhui", VX_LSP(4, 0x1478), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}}, 7736 {"zvunpkhsi", VX_LSP(4, 0x1C78), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}}, 7737 {"zunpkwgsf", VX_LSP(4, 0x2478), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}}, 7738 {"zvdotphgwasmf", VX(4, 0x488), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7739 {"zvdotphgwasmfr", VX(4, 0x489), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7740 {"zvdotphgwasmfaa", VX(4, 0x48A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7741 {"zvdotphgwasmfraa", VX(4, 0x48B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7742 {"zvdotphgwasmfan", VX(4, 0x48C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7743 {"zvdotphgwasmfran", VX(4, 0x48D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7744 {"zvmhulgwsmf", VX(4, 0x490), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7745 {"zvmhulgwsmfr", VX(4, 0x491), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7746 {"zvmhulgwsmfaa", VX(4, 0x492), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7747 {"zvmhulgwsmfraa", VX(4, 0x493), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7748 {"zvmhulgwsmfan", VX(4, 0x494), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7749 {"zvmhulgwsmfran", VX(4, 0x495), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7750 {"zvmhulgwsmfanp", VX(4, 0x496), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7751 {"zvmhulgwsmfranp", VX(4, 0x497), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7752 {"zmhegwsmf", VX(4, 0x498), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7753 {"zmhegwsmfr", VX(4, 0x499), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7754 {"zmhegwsmfaa", VX(4, 0x49A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7755 {"zmhegwsmfraa", VX(4, 0x49B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7756 {"zmhegwsmfan", VX(4, 0x49C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7757 {"zmhegwsmfran", VX(4, 0x49D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7758 {"zvdotphxgwasmf", VX(4, 0x4A8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7759 {"zvdotphxgwasmfr", VX(4, 0x4A9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7760 {"zvdotphxgwasmfaa", VX(4, 0x4AA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7761 {"zvdotphxgwasmfraa", VX(4, 0x4AB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7762 {"zvdotphxgwasmfan", VX(4, 0x4AC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7763 {"zvdotphxgwasmfran", VX(4, 0x4AD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7764 {"zvmhllgwsmf", VX(4, 0x4B0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7765 {"zvmhllgwsmfr", VX(4, 0x4B1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7766 {"zvmhllgwsmfaa", VX(4, 0x4B2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7767 {"zvmhllgwsmfraa", VX(4, 0x4B3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7768 {"zvmhllgwsmfan", VX(4, 0x4B4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7769 {"zvmhllgwsmfran", VX(4, 0x4B5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7770 {"zvmhllgwsmfanp", VX(4, 0x4B6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7771 {"zvmhllgwsmfranp", VX(4, 0x4B7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7772 {"zmheogwsmf", VX(4, 0x4B8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7773 {"zmheogwsmfr", VX(4, 0x4B9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7774 {"zmheogwsmfaa", VX(4, 0x4BA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7775 {"zmheogwsmfraa", VX(4, 0x4BB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7776 {"zmheogwsmfan", VX(4, 0x4BC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7777 {"zmheogwsmfran", VX(4, 0x4BD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7778 {"zvdotphgwssmf", VX(4, 0x4C8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7779 {"zvdotphgwssmfr", VX(4, 0x4C9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7780 {"zvdotphgwssmfaa", VX(4, 0x4CA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7781 {"zvdotphgwssmfraa", VX(4, 0x4CB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7782 {"zvdotphgwssmfan", VX(4, 0x4CC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7783 {"zvdotphgwssmfran", VX(4, 0x4CD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7784 {"zvmhuugwsmf", VX(4, 0x4D0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7785 {"zvmhuugwsmfr", VX(4, 0x4D1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7786 {"zvmhuugwsmfaa", VX(4, 0x4D2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7787 {"zvmhuugwsmfraa", VX(4, 0x4D3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7788 {"zvmhuugwsmfan", VX(4, 0x4D4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7789 {"zvmhuugwsmfran", VX(4, 0x4D5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7790 {"zvmhuugwsmfanp", VX(4, 0x4D6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7791 {"zvmhuugwsmfranp", VX(4, 0x4D7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7792 {"zmhogwsmf", VX(4, 0x4D8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7793 {"zmhogwsmfr", VX(4, 0x4D9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7794 {"zmhogwsmfaa", VX(4, 0x4DA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7795 {"zmhogwsmfraa", VX(4, 0x4DB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7796 {"zmhogwsmfan", VX(4, 0x4DC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7797 {"zmhogwsmfran", VX(4, 0x4DD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 7798 {"zvmhxlgwsmf", VX(4, 0x4F0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7799 {"zvmhxlgwsmfr", VX(4, 0x4F1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7800 {"zvmhxlgwsmfaa", VX(4, 0x4F2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7801 {"zvmhxlgwsmfraa", VX(4, 0x4F3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7802 {"zvmhxlgwsmfan", VX(4, 0x4F4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7803 {"zvmhxlgwsmfran", VX(4, 0x4F5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7804 {"zvmhxlgwsmfanp", VX(4, 0x4F6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7805 {"zvmhxlgwsmfranp", VX(4, 0x4F7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7806 {"zmhegui", VX(4, 0x500), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7807 {"zvdotphgaui", VX(4, 0x501), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7808 {"zmheguiaa", VX(4, 0x502), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7809 {"zvdotphgauiaa", VX(4, 0x503), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7810 {"zmheguian", VX(4, 0x504), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7811 {"zvdotphgauian", VX(4, 0x505), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7812 {"zmhegsi", VX(4, 0x508), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7813 {"zvdotphgasi", VX(4, 0x509), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7814 {"zmhegsiaa", VX(4, 0x50A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7815 {"zvdotphgasiaa", VX(4, 0x50B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7816 {"zmhegsian", VX(4, 0x50C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7817 {"zvdotphgasian", VX(4, 0x50D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7818 {"zmhegsui", VX(4, 0x510), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7819 {"zvdotphgasui", VX(4, 0x511), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7820 {"zmhegsuiaa", VX(4, 0x512), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7821 {"zvdotphgasuiaa", VX(4, 0x513), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7822 {"zmhegsuian", VX(4, 0x514), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7823 {"zvdotphgasuian", VX(4, 0x515), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7824 {"zmhegsmf", VX(4, 0x518), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7825 {"zvdotphgasmf", VX(4, 0x519), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7826 {"zmhegsmfaa", VX(4, 0x51A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7827 {"zvdotphgasmfaa", VX(4, 0x51B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7828 {"zmhegsmfan", VX(4, 0x51C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7829 {"zvdotphgasmfan", VX(4, 0x51D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7830 {"zmheogui", VX(4, 0x520), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7831 {"zvdotphxgaui", VX(4, 0x521), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7832 {"zmheoguiaa", VX(4, 0x522), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7833 {"zvdotphxgauiaa", VX(4, 0x523), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7834 {"zmheoguian", VX(4, 0x524), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7835 {"zvdotphxgauian", VX(4, 0x525), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7836 {"zmheogsi", VX(4, 0x528), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7837 {"zvdotphxgasi", VX(4, 0x529), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7838 {"zmheogsiaa", VX(4, 0x52A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7839 {"zvdotphxgasiaa", VX(4, 0x52B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7840 {"zmheogsian", VX(4, 0x52C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7841 {"zvdotphxgasian", VX(4, 0x52D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7842 {"zmheogsui", VX(4, 0x530), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7843 {"zvdotphxgasui", VX(4, 0x531), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7844 {"zmheogsuiaa", VX(4, 0x532), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7845 {"zvdotphxgasuiaa", VX(4, 0x533), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7846 {"zmheogsuian", VX(4, 0x534), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7847 {"zvdotphxgasuian", VX(4, 0x535), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7848 {"zmheogsmf", VX(4, 0x538), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7849 {"zvdotphxgasmf", VX(4, 0x539), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7850 {"zmheogsmfaa", VX(4, 0x53A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7851 {"zvdotphxgasmfaa", VX(4, 0x53B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7852 {"zmheogsmfan", VX(4, 0x53C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7853 {"zvdotphxgasmfan", VX(4, 0x53D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7854 {"zmhogui", VX(4, 0x540), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7855 {"zvdotphgsui", VX(4, 0x541), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7856 {"zmhoguiaa", VX(4, 0x542), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7857 {"zvdotphgsuiaa", VX(4, 0x543), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7858 {"zmhoguian", VX(4, 0x544), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7859 {"zvdotphgsuian", VX(4, 0x545), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7860 {"zmhogsi", VX(4, 0x548), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7861 {"zvdotphgssi", VX(4, 0x549), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7862 {"zmhogsiaa", VX(4, 0x54A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7863 {"zvdotphgssiaa", VX(4, 0x54B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7864 {"zmhogsian", VX(4, 0x54C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7865 {"zvdotphgssian", VX(4, 0x54D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7866 {"zmhogsui", VX(4, 0x550), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7867 {"zvdotphgssui", VX(4, 0x551), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7868 {"zmhogsuiaa", VX(4, 0x552), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7869 {"zvdotphgssuiaa", VX(4, 0x553), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7870 {"zmhogsuian", VX(4, 0x554), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7871 {"zvdotphgssuian", VX(4, 0x555), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7872 {"zmhogsmf", VX(4, 0x558), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7873 {"zvdotphgssmf", VX(4, 0x559), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7874 {"zmhogsmfaa", VX(4, 0x55A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7875 {"zvdotphgssmfaa", VX(4, 0x55B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7876 {"zmhogsmfan", VX(4, 0x55C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7877 {"zvdotphgssmfan", VX(4, 0x55D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7878 {"zmwgui", VX(4, 0x560), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7879 {"zmwguiaa", VX(4, 0x562), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7880 {"zmwguiaas", VX(4, 0x563), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7881 {"zmwguian", VX(4, 0x564), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7882 {"zmwguians", VX(4, 0x565), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7883 {"zmwgsi", VX(4, 0x568), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7884 {"zmwgsiaa", VX(4, 0x56A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7885 {"zmwgsiaas", VX(4, 0x56B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7886 {"zmwgsian", VX(4, 0x56C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7887 {"zmwgsians", VX(4, 0x56D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7888 {"zmwgsui", VX(4, 0x570), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7889 {"zmwgsuiaa", VX(4, 0x572), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7890 {"zmwgsuiaas", VX(4, 0x573), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7891 {"zmwgsuian", VX(4, 0x574), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7892 {"zmwgsuians", VX(4, 0x575), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7893 {"zmwgsmf", VX(4, 0x578), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7894 {"zmwgsmfr", VX(4, 0x579), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7895 {"zmwgsmfaa", VX(4, 0x57A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7896 {"zmwgsmfraa", VX(4, 0x57B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7897 {"zmwgsmfan", VX(4, 0x57C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7898 {"zmwgsmfran", VX(4, 0x57D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7899 {"zvmhului", VX(4, 0x580), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7900 {"zvmhuluiaa", VX(4, 0x582), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7901 {"zvmhuluiaas", VX(4, 0x583), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7902 {"zvmhuluian", VX(4, 0x584), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7903 {"zvmhuluians", VX(4, 0x585), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7904 {"zvmhuluianp", VX(4, 0x586), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7905 {"zvmhuluianps", VX(4, 0x587), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7906 {"zvmhulsi", VX(4, 0x588), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7907 {"zvmhulsiaa", VX(4, 0x58A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7908 {"zvmhulsiaas", VX(4, 0x58B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7909 {"zvmhulsian", VX(4, 0x58C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7910 {"zvmhulsians", VX(4, 0x58D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7911 {"zvmhulsianp", VX(4, 0x58E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7912 {"zvmhulsianps", VX(4, 0x58F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7913 {"zvmhulsui", VX(4, 0x590), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7914 {"zvmhulsuiaa", VX(4, 0x592), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7915 {"zvmhulsuiaas", VX(4, 0x593), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7916 {"zvmhulsuian", VX(4, 0x594), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7917 {"zvmhulsuians", VX(4, 0x595), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7918 {"zvmhulsuianp", VX(4, 0x596), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7919 {"zvmhulsuianps", VX(4, 0x597), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7920 {"zvmhulsf", VX(4, 0x598), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7921 {"zvmhulsfr", VX(4, 0x599), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7922 {"zvmhulsfaas", VX(4, 0x59A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7923 {"zvmhulsfraas", VX(4, 0x59B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7924 {"zvmhulsfans", VX(4, 0x59C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7925 {"zvmhulsfrans", VX(4, 0x59D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7926 {"zvmhulsfanps", VX(4, 0x59E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7927 {"zvmhulsfranps", VX(4, 0x59F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7928 {"zvmhllui", VX(4, 0x5A0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7929 {"zvmhlluiaa", VX(4, 0x5A2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7930 {"zvmhlluiaas", VX(4, 0x5A3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7931 {"zvmhlluian", VX(4, 0x5A4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7932 {"zvmhlluians", VX(4, 0x5A5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7933 {"zvmhlluianp", VX(4, 0x5A6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7934 {"zvmhlluianps", VX(4, 0x5A7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7935 {"zvmhllsi", VX(4, 0x5A8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7936 {"zvmhllsiaa", VX(4, 0x5AA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7937 {"zvmhllsiaas", VX(4, 0x5AB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7938 {"zvmhllsian", VX(4, 0x5AC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7939 {"zvmhllsians", VX(4, 0x5AD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7940 {"zvmhllsianp", VX(4, 0x5AE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7941 {"zvmhllsianps", VX(4, 0x5AF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7942 {"zvmhllsui", VX(4, 0x5B0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7943 {"zvmhllsuiaa", VX(4, 0x5B2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7944 {"zvmhllsuiaas", VX(4, 0x5B3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7945 {"zvmhllsuian", VX(4, 0x5B4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7946 {"zvmhllsuians", VX(4, 0x5B5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7947 {"zvmhllsuianp", VX(4, 0x5B6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7948 {"zvmhllsuianps", VX(4, 0x5B7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7949 {"zvmhllsf", VX(4, 0x5B8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7950 {"zvmhllsfr", VX(4, 0x5B9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7951 {"zvmhllsfaas", VX(4, 0x5BA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7952 {"zvmhllsfraas", VX(4, 0x5BB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7953 {"zvmhllsfans", VX(4, 0x5BC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7954 {"zvmhllsfrans", VX(4, 0x5BD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7955 {"zvmhllsfanps", VX(4, 0x5BE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7956 {"zvmhllsfranps", VX(4, 0x5BF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7957 {"zvmhuuui", VX(4, 0x5C0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7958 {"zvmhuuuiaa", VX(4, 0x5C2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7959 {"zvmhuuuiaas", VX(4, 0x5C3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7960 {"zvmhuuuian", VX(4, 0x5C4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7961 {"zvmhuuuians", VX(4, 0x5C5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7962 {"zvmhuuuianp", VX(4, 0x5C6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7963 {"zvmhuuuianps", VX(4, 0x5C7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7964 {"zvmhuusi", VX(4, 0x5C8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7965 {"zvmhuusiaa", VX(4, 0x5CA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7966 {"zvmhuusiaas", VX(4, 0x5CB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7967 {"zvmhuusian", VX(4, 0x5CC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7968 {"zvmhuusians", VX(4, 0x5CD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7969 {"zvmhuusianp", VX(4, 0x5CE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7970 {"zvmhuusianps", VX(4, 0x5CF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7971 {"zvmhuusui", VX(4, 0x5D0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7972 {"zvmhuusuiaa", VX(4, 0x5D2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7973 {"zvmhuusuiaas", VX(4, 0x5D3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7974 {"zvmhuusuian", VX(4, 0x5D4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7975 {"zvmhuusuians", VX(4, 0x5D5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7976 {"zvmhuusuianp", VX(4, 0x5D6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7977 {"zvmhuusuianps", VX(4, 0x5D7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7978 {"zvmhuusf", VX(4, 0x5D8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7979 {"zvmhuusfr", VX(4, 0x5D9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7980 {"zvmhuusfaas", VX(4, 0x5DA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7981 {"zvmhuusfraas", VX(4, 0x5DB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7982 {"zvmhuusfans", VX(4, 0x5DC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7983 {"zvmhuusfrans", VX(4, 0x5DD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7984 {"zvmhuusfanps", VX(4, 0x5DE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7985 {"zvmhuusfranps", VX(4, 0x5DF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7986 {"zvmhxlui", VX(4, 0x5E0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7987 {"zvmhxluiaa", VX(4, 0x5E2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7988 {"zvmhxluiaas", VX(4, 0x5E3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7989 {"zvmhxluian", VX(4, 0x5E4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7990 {"zvmhxluians", VX(4, 0x5E5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7991 {"zvmhxluianp", VX(4, 0x5E6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7992 {"zvmhxluianps", VX(4, 0x5E7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7993 {"zvmhxlsi", VX(4, 0x5E8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7994 {"zvmhxlsiaa", VX(4, 0x5EA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7995 {"zvmhxlsiaas", VX(4, 0x5EB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7996 {"zvmhxlsian", VX(4, 0x5EC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7997 {"zvmhxlsians", VX(4, 0x5ED), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7998 {"zvmhxlsianp", VX(4, 0x5EE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 7999 {"zvmhxlsianps", VX(4, 0x5EF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8000 {"zvmhxlsui", VX(4, 0x5F0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8001 {"zvmhxlsuiaa", VX(4, 0x5F2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8002 {"zvmhxlsuiaas", VX(4, 0x5F3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8003 {"zvmhxlsuian", VX(4, 0x5F4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8004 {"zvmhxlsuians", VX(4, 0x5F5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8005 {"zvmhxlsuianp", VX(4, 0x5F6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8006 {"zvmhxlsuianps", VX(4, 0x5F7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8007 {"zvmhxlsf", VX(4, 0x5F8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8008 {"zvmhxlsfr", VX(4, 0x5F9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8009 {"zvmhxlsfaas", VX(4, 0x5FA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8010 {"zvmhxlsfraas", VX(4, 0x5FB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8011 {"zvmhxlsfans", VX(4, 0x5FC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8012 {"zvmhxlsfrans", VX(4, 0x5FD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8013 {"zvmhxlsfanps", VX(4, 0x5FE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8014 {"zvmhxlsfranps", VX(4, 0x5FF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8015 {"zmheui", VX(4, 0x600), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8016 {"zmheuiaa", VX(4, 0x602), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8017 {"zmheuiaas", VX(4, 0x603), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8018 {"zmheuian", VX(4, 0x604), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8019 {"zmheuians", VX(4, 0x605), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8020 {"zmhesi", VX(4, 0x608), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8021 {"zmhesiaa", VX(4, 0x60A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8022 {"zmhesiaas", VX(4, 0x60B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8023 {"zmhesian", VX(4, 0x60C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8024 {"zmhesians", VX(4, 0x60D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8025 {"zmhesui", VX(4, 0x610), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8026 {"zmhesuiaa", VX(4, 0x612), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8027 {"zmhesuiaas", VX(4, 0x613), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8028 {"zmhesuian", VX(4, 0x614), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8029 {"zmhesuians", VX(4, 0x615), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8030 {"zmhesf", VX(4, 0x618), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8031 {"zmhesfr", VX(4, 0x619), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8032 {"zmhesfaas", VX(4, 0x61A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8033 {"zmhesfraas", VX(4, 0x61B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8034 {"zmhesfans", VX(4, 0x61C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8035 {"zmhesfrans", VX(4, 0x61D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8036 {"zmheoui", VX(4, 0x620), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8037 {"zmheouiaa", VX(4, 0x622), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8038 {"zmheouiaas", VX(4, 0x623), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8039 {"zmheouian", VX(4, 0x624), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8040 {"zmheouians", VX(4, 0x625), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8041 {"zmheosi", VX(4, 0x628), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8042 {"zmheosiaa", VX(4, 0x62A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8043 {"zmheosiaas", VX(4, 0x62B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8044 {"zmheosian", VX(4, 0x62C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8045 {"zmheosians", VX(4, 0x62D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8046 {"zmheosui", VX(4, 0x630), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8047 {"zmheosuiaa", VX(4, 0x632), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8048 {"zmheosuiaas", VX(4, 0x633), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8049 {"zmheosuian", VX(4, 0x634), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8050 {"zmheosuians", VX(4, 0x635), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8051 {"zmheosf", VX(4, 0x638), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8052 {"zmheosfr", VX(4, 0x639), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8053 {"zmheosfaas", VX(4, 0x63A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8054 {"zmheosfraas", VX(4, 0x63B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8055 {"zmheosfans", VX(4, 0x63C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8056 {"zmheosfrans", VX(4, 0x63D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8057 {"zmhoui", VX(4, 0x640), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8058 {"zmhouiaa", VX(4, 0x642), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8059 {"zmhouiaas", VX(4, 0x643), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8060 {"zmhouian", VX(4, 0x644), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8061 {"zmhouians", VX(4, 0x645), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8062 {"zmhosi", VX(4, 0x648), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8063 {"zmhosiaa", VX(4, 0x64A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8064 {"zmhosiaas", VX(4, 0x64B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8065 {"zmhosian", VX(4, 0x64C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8066 {"zmhosians", VX(4, 0x64D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8067 {"zmhosui", VX(4, 0x650), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8068 {"zmhosuiaa", VX(4, 0x652), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8069 {"zmhosuiaas", VX(4, 0x653), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8070 {"zmhosuian", VX(4, 0x654), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8071 {"zmhosuians", VX(4, 0x655), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8072 {"zmhosf", VX(4, 0x658), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8073 {"zmhosfr", VX(4, 0x659), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8074 {"zmhosfaas", VX(4, 0x65A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8075 {"zmhosfraas", VX(4, 0x65B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8076 {"zmhosfans", VX(4, 0x65C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8077 {"zmhosfrans", VX(4, 0x65D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8078 {"zvmhuih", VX(4, 0x660), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8079 {"zvmhuihs", VX(4, 0x661), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8080 {"zvmhuiaah", VX(4, 0x662), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8081 {"zvmhuiaahs", VX(4, 0x663), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8082 {"zvmhuianh", VX(4, 0x664), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8083 {"zvmhuianhs", VX(4, 0x665), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8084 {"zvmhsihs", VX(4, 0x669), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8085 {"zvmhsiaahs", VX(4, 0x66B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8086 {"zvmhsianhs", VX(4, 0x66D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8087 {"zvmhsuihs", VX(4, 0x671), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8088 {"zvmhsuiaahs", VX(4, 0x673), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8089 {"zvmhsuianhs", VX(4, 0x675), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8090 {"zvmhsfh", VX(4, 0x678), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8091 {"zvmhsfrh", VX(4, 0x679), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8092 {"zvmhsfaahs", VX(4, 0x67A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8093 {"zvmhsfraahs", VX(4, 0x67B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8094 {"zvmhsfanhs", VX(4, 0x67C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8095 {"zvmhsfranhs", VX(4, 0x67D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8096 {"zvdotphaui", VX(4, 0x680), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8097 {"zvdotphauis", VX(4, 0x681), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8098 {"zvdotphauiaa", VX(4, 0x682), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8099 {"zvdotphauiaas", VX(4, 0x683), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8100 {"zvdotphauian", VX(4, 0x684), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8101 {"zvdotphauians", VX(4, 0x685), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8102 {"zvdotphasi", VX(4, 0x688), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8103 {"zvdotphasis", VX(4, 0x689), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8104 {"zvdotphasiaa", VX(4, 0x68A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8105 {"zvdotphasiaas", VX(4, 0x68B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8106 {"zvdotphasian", VX(4, 0x68C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8107 {"zvdotphasians", VX(4, 0x68D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8108 {"zvdotphasui", VX(4, 0x690), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8109 {"zvdotphasuis", VX(4, 0x691), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8110 {"zvdotphasuiaa", VX(4, 0x692), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8111 {"zvdotphasuiaas", VX(4, 0x693), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8112 {"zvdotphasuian", VX(4, 0x694), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8113 {"zvdotphasuians", VX(4, 0x695), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8114 {"zvdotphasfs", VX(4, 0x698), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8115 {"zvdotphasfrs", VX(4, 0x699), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8116 {"zvdotphasfaas", VX(4, 0x69A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8117 {"zvdotphasfraas", VX(4, 0x69B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8118 {"zvdotphasfans", VX(4, 0x69C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8119 {"zvdotphasfrans", VX(4, 0x69D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8120 {"zvdotphxaui", VX(4, 0x6A0), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8121 {"zvdotphxauis", VX(4, 0x6A1), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8122 {"zvdotphxauiaa", VX(4, 0x6A2), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8123 {"zvdotphxauiaas", VX(4, 0x6A3), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8124 {"zvdotphxauian", VX(4, 0x6A4), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8125 {"zvdotphxauians", VX(4, 0x6A5), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8126 {"zvdotphxasi", VX(4, 0x6A8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8127 {"zvdotphxasis", VX(4, 0x6A9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8128 {"zvdotphxasiaa", VX(4, 0x6AA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8129 {"zvdotphxasiaas", VX(4, 0x6AB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8130 {"zvdotphxasian", VX(4, 0x6AC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8131 {"zvdotphxasians", VX(4, 0x6AD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8132 {"zvdotphxasui", VX(4, 0x6B0), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8133 {"zvdotphxasuis", VX(4, 0x6B1), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8134 {"zvdotphxasuiaa", VX(4, 0x6B2), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8135 {"zvdotphxasuiaas", VX(4, 0x6B3), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8136 {"zvdotphxasuian", VX(4, 0x6B4), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8137 {"zvdotphxasuians", VX(4, 0x6B5), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8138 {"zvdotphxasfs", VX(4, 0x6B8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8139 {"zvdotphxasfrs", VX(4, 0x6B9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8140 {"zvdotphxasfaas", VX(4, 0x6BA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8141 {"zvdotphxasfraas", VX(4, 0x6BB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8142 {"zvdotphxasfans", VX(4, 0x6BC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8143 {"zvdotphxasfrans", VX(4, 0x6BD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8144 {"zvdotphsui", VX(4, 0x6C0), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8145 {"zvdotphsuis", VX(4, 0x6C1), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8146 {"zvdotphsuiaa", VX(4, 0x6C2), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8147 {"zvdotphsuiaas", VX(4, 0x6C3), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8148 {"zvdotphsuian", VX(4, 0x6C4), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8149 {"zvdotphsuians", VX(4, 0x6C5), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8150 {"zvdotphssi", VX(4, 0x6C8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8151 {"zvdotphssis", VX(4, 0x6C9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8152 {"zvdotphssiaa", VX(4, 0x6CA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8153 {"zvdotphssiaas", VX(4, 0x6CB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8154 {"zvdotphssian", VX(4, 0x6CC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8155 {"zvdotphssians", VX(4, 0x6CD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8156 {"zvdotphssui", VX(4, 0x6D0), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8157 {"zvdotphssuis", VX(4, 0x6D1), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8158 {"zvdotphssuiaa", VX(4, 0x6D2), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8159 {"zvdotphssuiaas", VX(4, 0x6D3), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8160 {"zvdotphssuian", VX(4, 0x6D4), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8161 {"zvdotphssuians", VX(4, 0x6D5), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8162 {"zvdotphssfs", VX(4, 0x6D8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8163 {"zvdotphssfrs", VX(4, 0x6D9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8164 {"zvdotphssfaas", VX(4, 0x6DA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8165 {"zvdotphssfraas", VX(4, 0x6DB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8166 {"zvdotphssfans", VX(4, 0x6DC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8167 {"zvdotphssfrans", VX(4, 0x6DD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8168 {"zmwluis", VX(4, 0x6E1), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8169 {"zmwluiaa", VX(4, 0x6E2), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8170 {"zmwluiaas", VX(4, 0x6E3), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8171 {"zmwluian", VX(4, 0x6E4), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8172 {"zmwluians", VX(4, 0x6E5), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8173 {"zmwlsis", VX(4, 0x6E9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8174 {"zmwlsiaas", VX(4, 0x6EB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8175 {"zmwlsians", VX(4, 0x6ED), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8176 {"zmwlsuis", VX(4, 0x6F1), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8177 {"zmwlsuiaas", VX(4, 0x6F3), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8178 {"zmwlsuians", VX(4, 0x6F5), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8179 {"zmwsf", VX(4, 0x6F8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8180 {"zmwsfr", VX(4, 0x6F9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8181 {"zmwsfaas", VX(4, 0x6FA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8182 {"zmwsfraas", VX(4, 0x6FB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8183 {"zmwsfans", VX(4, 0x6FC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8184 {"zmwsfrans", VX(4, 0x6FD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8185 {"zlddx", VX(4, 0x300), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8186 {"zldd", VX(4, 0x301), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}}, 8187 {"zldwx", VX(4, 0x302), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8188 {"zldw", VX(4, 0x303), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}}, 8189 {"zldhx", VX(4, 0x304), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8190 {"zldh", VX(4, 0x305), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}}, 8191 {"zlwgsfdx", VX(4, 0x308), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8192 {"zlwgsfd", VX(4, 0x309), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, 8193 {"zlwwosdx", VX(4, 0x30A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8194 {"zlwwosd", VX(4, 0x30B), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, 8195 {"zlwhsplatwdx", VX(4, 0x30C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8196 {"zlwhsplatwd", VX(4, 0x30D), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, 8197 {"zlwhsplatdx", VX(4, 0x30E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8198 {"zlwhsplatd", VX(4, 0x30F), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, 8199 {"zlwhgwsfdx", VX(4, 0x310), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8200 {"zlwhgwsfd", VX(4, 0x311), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, 8201 {"zlwhedx", VX(4, 0x312), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8202 {"zlwhed", VX(4, 0x313), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, 8203 {"zlwhosdx", VX(4, 0x314), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8204 {"zlwhosd", VX(4, 0x315), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, 8205 {"zlwhoudx", VX(4, 0x316), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8206 {"zlwhoud", VX(4, 0x317), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, 8207 {"zlwhx", VX(4, 0x318), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8208 {"zlwh", VX(4, 0x319), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4, RA}}, 8209 {"zlwwx", VX(4, 0x31A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8210 {"zlww", VX(4, 0x31B), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4, RA}}, 8211 {"zlhgwsfx", VX(4, 0x31C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8212 {"zlhgwsf", VX(4, 0x31D), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}}, 8213 {"zlhhsplatx", VX(4, 0x31E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8214 {"zlhhsplat", VX(4, 0x31F), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}}, 8215 {"zstddx", VX(4, 0x320), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, 8216 {"zstdd", VX(4, 0x321), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}}, 8217 {"zstdwx", VX(4, 0x322), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, 8218 {"zstdw", VX(4, 0x323), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}}, 8219 {"zstdhx", VX(4, 0x324), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, 8220 {"zstdh", VX(4, 0x325), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}}, 8221 {"zstwhedx", VX(4, 0x328), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, 8222 {"zstwhed", VX(4, 0x329), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4, RA}}, 8223 {"zstwhodx", VX(4, 0x32A), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, 8224 {"zstwhod", VX(4, 0x32B), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4, RA}}, 8225 {"zlhhex", VX(4, 0x330), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8226 {"zlhhe", VX(4, 0x331), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}}, 8227 {"zlhhosx", VX(4, 0x332), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8228 {"zlhhos", VX(4, 0x333), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}}, 8229 {"zlhhoux", VX(4, 0x334), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8230 {"zlhhou", VX(4, 0x335), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}}, 8231 {"zsthex", VX(4, 0x338), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, 8232 {"zsthe", VX(4, 0x339), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2, RA}}, 8233 {"zsthox", VX(4, 0x33A), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, 8234 {"zstho", VX(4, 0x33B), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2, RA}}, 8235 {"zstwhx", VX(4, 0x33C), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, 8236 {"zstwh", VX(4, 0x33D), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4, RA}}, 8237 {"zstwwx", VX(4, 0x33E), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, 8238 {"zstww", VX(4, 0x33F), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4, RA}}, 8239 {"zlddmx", VX(4, 0x340), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8240 {"zlddu", VX(4, 0x341), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}}, 8241 {"zldwmx", VX(4, 0x342), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8242 {"zldwu", VX(4, 0x343), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}}, 8243 {"zldhmx", VX(4, 0x344), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8244 {"zldhu", VX(4, 0x345), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}}, 8245 {"zlwgsfdmx", VX(4, 0x348), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8246 {"zlwgsfdu", VX(4, 0x349), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, 8247 {"zlwwosdmx", VX(4, 0x34A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8248 {"zlwwosdu", VX(4, 0x34B), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, 8249 {"zlwhsplatwdmx", VX(4, 0x34C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8250 {"zlwhsplatwdu", VX(4, 0x34D), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, 8251 {"zlwhsplatdmx", VX(4, 0x34E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8252 {"zlwhsplatdu", VX(4, 0x34F), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, 8253 {"zlwhgwsfdmx", VX(4, 0x350), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8254 {"zlwhgwsfdu", VX(4, 0x351), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, 8255 {"zlwhedmx", VX(4, 0x352), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8256 {"zlwhedu", VX(4, 0x353), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, 8257 {"zlwhosdmx", VX(4, 0x354), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8258 {"zlwhosdu", VX(4, 0x355), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, 8259 {"zlwhoudmx", VX(4, 0x356), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 8260 {"zlwhoudu", VX(4, 0x357), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, 8261 {"zlwhmx", VX(4, 0x358), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8262 {"zlwhu", VX(4, 0x359), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4_EX0, RA}}, 8263 {"zlwwmx", VX(4, 0x35A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8264 {"zlwwu", VX(4, 0x35B), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4_EX0, RA}}, 8265 {"zlhgwsfmx", VX(4, 0x35C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8266 {"zlhgwsfu", VX(4, 0x35D), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}}, 8267 {"zlhhsplatmx", VX(4, 0x35E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8268 {"zlhhsplatu", VX(4, 0x35F), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}}, 8269 {"zstddmx", VX(4, 0x360), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, 8270 {"zstddu", VX(4, 0x361), VX_MASK, PPCLSP, 0, {RS, EVUIMM_8_EX0, RA}}, 8271 {"zstdwmx", VX(4, 0x362), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, 8272 {"zstdwu", VX(4, 0x363), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8_EX0, RA}}, 8273 {"zstdhmx", VX(4, 0x364), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, 8274 {"zstdhu", VX(4, 0x365), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8_EX0, RA}}, 8275 {"zstwhedmx", VX(4, 0x368), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, 8276 {"zstwhedu", VX(4, 0x369), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4_EX0, RA}}, 8277 {"zstwhodmx", VX(4, 0x36A), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, 8278 {"zstwhodu", VX(4, 0x36B), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4_EX0, RA}}, 8279 {"zlhhemx", VX(4, 0x370), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8280 {"zlhheu", VX(4, 0x371), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}}, 8281 {"zlhhosmx", VX(4, 0x372), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8282 {"zlhhosu", VX(4, 0x373), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}}, 8283 {"zlhhoumx", VX(4, 0x374), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 8284 {"zlhhouu", VX(4, 0x375), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}}, 8285 {"zsthemx", VX(4, 0x378), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, 8286 {"zstheu", VX(4, 0x379), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2_EX0, RA}}, 8287 {"zsthomx", VX(4, 0x37A), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, 8288 {"zsthou", VX(4, 0x37B), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2_EX0, RA}}, 8289 {"zstwhmx", VX(4, 0x37C), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, 8290 {"zstwhu", VX(4, 0x37D), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4_EX0, RA}}, 8291 {"zstwwmx", VX(4, 0x37E), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, 8292 {"zstwwu", VX(4, 0x37F), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4_EX0, RA}}, 8293 8294 {"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, 8295 {"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, 8296 {"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, 8297 {"e_cmplwi", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, 8298 {"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, 8299 {"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}}, 8300 {"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, 8301 {"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, 8302 {"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}}, 8303 {"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, 8304 {"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}}, 8305 {"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, 8306 {"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, 8307 {"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, 8308 {"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, 8309 {"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, 8310 {"e_nop", SCI8(6,26), 0xffffffff, PPCVLE, 0, {0}}, 8311 {"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, 8312 {"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, 8313 {"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, 8314 {"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, 8315 {"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 8316 {"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 8317 {"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 8318 {"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 8319 {"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 8320 {"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 8321 {"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 8322 {"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 8323 {"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 8324 {"e_lmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 8325 {"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 8326 {"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 8327 {"e_lmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 8328 {"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 8329 {"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 8330 {"e_lmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 8331 {"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 8332 {"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 8333 {"e_lmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 8334 {"e_ldmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 8335 {"e_stmvcsrrw", OPVUPRT(6,17,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 8336 {"e_lmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 8337 {"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 8338 {"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 8339 {"e_lmvmcsrrw", OPVUPRT(6,16,7),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 8340 {"e_stmvmcsrrw", OPVUPRT(6,17,7),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 8341 {"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}}, 8342 {"e_la", OP(7), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, 8343 {"e_sub16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, NSI}}, 8344 8345 {"se_addi", SE_IM5(8,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}}, 8346 {"se_cmpli", SE_IM5(8,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}}, 8347 {"se_subi", SE_IM5(9,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}}, 8348 {"se_subi.", SE_IM5(9,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}}, 8349 {"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 8350 {"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 8351 {"se_andi", SE_IM5(11,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 8352 8353 {"e_lbz", OP(12), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, 8354 {"e_stb", OP(13), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, 8355 {"e_lha", OP(14), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, 8356 8357 {"se_srw", SE_RR(16,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 8358 {"se_sraw", SE_RR(16,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 8359 {"se_slw", SE_RR(16,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 8360 {"se_nop", SE_RR(17,0), 0xffff, PPCVLE, 0, {0}}, 8361 {"se_or", SE_RR(17,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 8362 {"se_andc", SE_RR(17,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 8363 {"se_and", SE_RR(17,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 8364 {"se_and.", SE_RR(17,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 8365 {"se_li", IM7(9), IM7_MASK, PPCVLE, 0, {RX, UI7}}, 8366 8367 {"e_lwz", OP(20), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, 8368 {"e_stw", OP(21), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, 8369 {"e_lhz", OP(22), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, 8370 {"e_sth", OP(23), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, 8371 8372 {"se_bclri", SE_IM5(24,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 8373 {"se_bgeni", SE_IM5(24,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 8374 {"se_bseti", SE_IM5(25,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 8375 {"se_btsti", SE_IM5(25,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 8376 {"se_srwi", SE_IM5(26,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 8377 {"se_srawi", SE_IM5(26,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 8378 {"se_slwi", SE_IM5(27,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 8379 8380 {"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, 8381 {"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, 8382 {"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, 8383 {"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, 8384 {"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, 8385 {"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}}, 8386 {"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}}, 8387 {"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}}, 8388 {"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}}, 8389 {"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}}, 8390 {"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}}, 8391 {"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}}, 8392 {"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}}, 8393 {"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}}, 8394 {"e_li", LI20(28,0), LI20_MASK, PPCVLE, 0, {RT, IMM20}}, 8395 {"e_rlwimi", M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}}, 8396 {"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RT, SH, MBE, ME}}, 8397 {"e_b", BD24(30,0,0), BD24_MASK, PPCVLE, 0, {B24}}, 8398 {"e_bl", BD24(30,0,1), BD24_MASK, PPCVLE, 0, {B24}}, 8399 {"e_bdnz", EBD15(30,8,BO32DNZ,0), EBD15_MASK, PPCVLE, 0, {B15}}, 8400 {"e_bdnzl", EBD15(30,8,BO32DNZ,1), EBD15_MASK, PPCVLE, 0, {B15}}, 8401 {"e_bdz", EBD15(30,8,BO32DZ,0), EBD15_MASK, PPCVLE, 0, {B15}}, 8402 {"e_bdzl", EBD15(30,8,BO32DZ,1), EBD15_MASK, PPCVLE, 0, {B15}}, 8403 {"e_bge", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 8404 {"e_bgel", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 8405 {"e_bnl", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 8406 {"e_bnll", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 8407 {"e_blt", EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 8408 {"e_bltl", EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 8409 {"e_bgt", EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 8410 {"e_bgtl", EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 8411 {"e_ble", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 8412 {"e_blel", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 8413 {"e_bng", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 8414 {"e_bngl", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 8415 {"e_bne", EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 8416 {"e_bnel", EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 8417 {"e_beq", EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 8418 {"e_beql", EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 8419 {"e_bso", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 8420 {"e_bsol", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 8421 {"e_bun", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 8422 {"e_bunl", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 8423 {"e_bns", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 8424 {"e_bnsl", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 8425 {"e_bnu", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 8426 {"e_bnul", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 8427 {"e_bc", BD15(30,8,0), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}}, 8428 {"e_bcl", BD15(30,8,1), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}}, 8429 8430 {"e_bf", EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}}, 8431 {"e_bfl", EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}}, 8432 {"e_bt", EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}}, 8433 {"e_btl", EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}}, 8434 8435 {"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}}, 8436 {"e_sc", X(31,36), XRTRA_MASK, PPCVLE, 0, {ELEV}}, 8437 {"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}}, 8438 {"e_crandc", XL(31,129), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, 8439 {"e_crnand", XL(31,225), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, 8440 {"e_crnot", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BAB}}, 8441 {"e_crnor", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, 8442 {"e_crclr", XL(31,193), XL_MASK, PPCVLE, 0, {BTAB}}, 8443 {"e_crxor", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, 8444 {"e_mcrf", XL(31,16), XL_MASK, PPCVLE, 0, {CRD, CR}}, 8445 {"e_slwi", EX(31,112), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, 8446 {"e_slwi.", EX(31,113), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, 8447 8448 {"e_crand", XL(31,257), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, 8449 8450 {"e_rlw", EX(31,560), EX_MASK, PPCVLE, 0, {RA, RS, RB}}, 8451 {"e_rlw.", EX(31,561), EX_MASK, PPCVLE, 0, {RA, RS, RB}}, 8452 8453 {"e_crset", XL(31,289), XL_MASK, PPCVLE, 0, {BTAB}}, 8454 {"e_creqv", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, 8455 8456 {"e_rlwi", EX(31,624), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, 8457 {"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, 8458 8459 {"e_crorc", XL(31,417), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, 8460 8461 {"e_crmove", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BAB}}, 8462 {"e_cror", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, 8463 8464 {"mtmas1", XSPR(31,467,625), XSPR_MASK, PPCVLE, 0, {RS}}, 8465 8466 {"e_srwi", EX(31,1136), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, 8467 {"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, 8468 8469 {"se_lbz", SD4(8), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}}, 8470 8471 {"se_stb", SD4(9), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}}, 8472 8473 {"se_lhz", SD4(10), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}}, 8474 8475 {"se_sth", SD4(11), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}}, 8476 8477 {"se_lwz", SD4(12), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}}, 8478 8479 {"se_stw", SD4(13), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}}, 8480 8481 {"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 8482 {"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 8483 {"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 8484 {"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 8485 {"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 8486 {"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 8487 {"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 8488 {"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}}, 8489 {"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 8490 {"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 8491 {"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 8492 {"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 8493 {"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 8494 {"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}}, 8495 {"se_bc", BD8IO(28), BD8IO_MASK, PPCVLE, 0, {BO16, BI16, B8}}, 8496 {"se_b", BD8(58,0,0), BD8_MASK, PPCVLE, 0, {B8}}, 8497 {"se_bl", BD8(58,0,1), BD8_MASK, PPCVLE, 0, {B8}}, 8498 }; 8499 8500 const unsigned int vle_num_opcodes = 8501 sizeof (vle_opcodes) / sizeof (vle_opcodes[0]); 8502 8503 /* The macro table. This is only used by the assembler. */ 8505 8506 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0 8507 when x=0; 32-x when x is between 1 and 31; are negative if x is 8508 negative; and are 32 or more otherwise. This is what you want 8509 when, for instance, you are emulating a right shift by a 8510 rotate-left-and-mask, because the underlying instructions support 8511 shifts of size 0 but not shifts of size 32. By comparison, when 8512 extracting x bits from some word you want to use just 32-x, because 8513 the underlying instructions don't support extracting 0 bits but do 8514 support extracting the whole word (32 bits in this case). */ 8515 8516 const struct powerpc_macro powerpc_macros[] = { 8517 {"extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1"}, 8518 {"extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1"}, 8519 {"extrdi", 4, PPC64, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"}, 8520 {"extrdi.", 4, PPC64, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"}, 8521 {"insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3"}, 8522 {"insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3"}, 8523 {"rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"}, 8524 {"rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"}, 8525 {"sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)"}, 8526 {"sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)"}, 8527 {"srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"}, 8528 {"srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"}, 8529 {"clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)"}, 8530 {"clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)"}, 8531 {"clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)"}, 8532 {"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"}, 8533 8534 {"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"}, 8535 {"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"}, 8536 {"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"}, 8537 {"extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"}, 8538 {"inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, 8539 {"inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, 8540 {"insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, 8541 {"insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, 8542 {"rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"}, 8543 {"rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"}, 8544 {"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"}, 8545 {"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"}, 8546 {"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"}, 8547 {"sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"}, 8548 {"srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, 8549 {"sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, 8550 {"srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, 8551 {"sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, 8552 {"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"}, 8553 {"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"}, 8554 {"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"}, 8555 {"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"}, 8556 8557 {"e_extlwi", 4, PPCVLE, "e_rlwinm %0,%1,%3,0,(%2)-1"}, 8558 {"e_extrwi", 4, PPCVLE, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"}, 8559 {"e_inslwi", 4, PPCVLE, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, 8560 {"e_insrwi", 4, PPCVLE, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, 8561 {"e_rotlwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31"}, 8562 {"e_rotrwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"}, 8563 {"e_slwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31-(%2)"}, 8564 {"e_srwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, 8565 {"e_clrlwi", 3, PPCVLE, "e_rlwinm %0,%1,0,%2,31"}, 8566 {"e_clrrwi", 3, PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)"}, 8567 {"e_clrlslwi",4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"}, 8568 8569 /* old SPE instructions have new names with the same opcodes */ 8570 {"evsadd", 3, PPCSPE|PPCVLE, "efsadd %0,%1,%2"}, 8571 {"evssub", 3, PPCSPE|PPCVLE, "efssub %0,%1,%2"}, 8572 {"evsabs", 2, PPCSPE|PPCVLE, "efsabs %0,%1"}, 8573 {"evsnabs", 2, PPCSPE|PPCVLE, "efsnabs %0,%1"}, 8574 {"evsneg", 2, PPCSPE|PPCVLE, "efsneg %0,%1"}, 8575 {"evsmul", 3, PPCSPE|PPCVLE, "efsmul %0,%1,%2"}, 8576 {"evsdiv", 3, PPCSPE|PPCVLE, "efsdiv %0,%1,%2"}, 8577 {"evscmpgt", 3, PPCSPE|PPCVLE, "efscmpgt %0,%1,%2"}, 8578 {"evsgmplt", 3, PPCSPE|PPCVLE, "efscmplt %0,%1,%2"}, 8579 {"evsgmpeq", 3, PPCSPE|PPCVLE, "efscmpeq %0,%1,%2"}, 8580 {"evscfui", 2, PPCSPE|PPCVLE, "efscfui %0,%1"}, 8581 {"evscfsi", 2, PPCSPE|PPCVLE, "efscfsi %0,%1"}, 8582 {"evscfuf", 2, PPCSPE|PPCVLE, "efscfuf %0,%1"}, 8583 {"evscfsf", 2, PPCSPE|PPCVLE, "efscfsf %0,%1"}, 8584 {"evsctui", 2, PPCSPE|PPCVLE, "efsctui %0,%1"}, 8585 {"evsctsi", 2, PPCSPE|PPCVLE, "efsctsi %0,%1"}, 8586 {"evsctuf", 2, PPCSPE|PPCVLE, "efsctuf %0,%1"}, 8587 {"evsctsf", 2, PPCSPE|PPCVLE, "efsctsf %0,%1"}, 8588 {"evsctuiz", 2, PPCSPE|PPCVLE, "efsctuiz %0,%1"}, 8589 {"evsctsiz", 2, PPCSPE|PPCVLE, "efsctsiz %0,%1"}, 8590 {"evststgt", 3, PPCSPE|PPCVLE, "efststgt %0,%1,%2"}, 8591 {"evststlt", 3, PPCSPE|PPCVLE, "efststlt %0,%1,%2"}, 8592 {"evststeq", 3, PPCSPE|PPCVLE, "efststeq %0,%1,%2"}, 8593 8594 /* SPE2 instructions which just are mapped to SPE2 */ 8595 {"evdotphsssi", 3, PPCSPE2, "evdotphssmi %0,%1,%2"}, 8596 {"evdotphsssia", 3, PPCSPE2, "evdotphssmia %0,%1,%2"}, 8597 {"evdotpwsssi", 3, PPCSPE2, "evdotpwssmi %0,%1,%2"}, 8598 {"evdotpwsssia", 3, PPCSPE2, "evdotpwssmia %0,%1,%2"} 8599 }; 8600 8601 const int powerpc_num_macros = 8602 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]); 8603 8604 /* SPE v2 instruction set from SPE2PIM Rev. 2 08/2011 */ 8605 const struct powerpc_opcode spe2_opcodes[] = { 8606 {"evdotpwcssi", VX (4, 128), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8607 {"evdotpwcsmi", VX (4, 129), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8608 {"evdotpwcssfr", VX (4, 130), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8609 {"evdotpwcssf", VX (4, 131), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8610 {"evdotpwgasmf", VX (4, 136), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8611 {"evdotpwxgasmf", VX (4, 137), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8612 {"evdotpwgasmfr", VX (4, 138), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8613 {"evdotpwxgasmfr", VX (4, 139), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8614 {"evdotpwgssmf", VX (4, 140), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8615 {"evdotpwxgssmf", VX (4, 141), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8616 {"evdotpwgssmfr", VX (4, 142), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8617 {"evdotpwxgssmfr", VX (4, 143), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8618 {"evdotpwcssiaaw3", VX (4, 144), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8619 {"evdotpwcsmiaaw3", VX (4, 145), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8620 {"evdotpwcssfraaw3", VX (4, 146), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8621 {"evdotpwcssfaaw3", VX (4, 147), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8622 {"evdotpwgasmfaa3", VX (4, 152), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8623 {"evdotpwxgasmfaa3", VX (4, 153), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8624 {"evdotpwgasmfraa3", VX (4, 154), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8625 {"evdotpwxgasmfraa3", VX (4, 155), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8626 {"evdotpwgssmfaa3", VX (4, 156), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8627 {"evdotpwxgssmfaa3", VX (4, 157), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8628 {"evdotpwgssmfraa3", VX (4, 158), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8629 {"evdotpwxgssmfraa3", VX (4, 159), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8630 {"evdotpwcssia", VX (4, 160), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8631 {"evdotpwcsmia", VX (4, 161), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8632 {"evdotpwcssfra", VX (4, 162), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8633 {"evdotpwcssfa", VX (4, 163), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8634 {"evdotpwgasmfa", VX (4, 168), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8635 {"evdotpwxgasmfa", VX (4, 169), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8636 {"evdotpwgasmfra", VX (4, 170), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8637 {"evdotpwxgasmfra", VX (4, 171), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8638 {"evdotpwgssmfa", VX (4, 172), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8639 {"evdotpwxgssmfa", VX (4, 173), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8640 {"evdotpwgssmfra", VX (4, 174), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8641 {"evdotpwxgssmfra", VX (4, 175), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8642 {"evdotpwcssiaaw", VX (4, 176), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8643 {"evdotpwcsmiaaw", VX (4, 177), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8644 {"evdotpwcssfraaw", VX (4, 178), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8645 {"evdotpwcssfaaw", VX (4, 179), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8646 {"evdotpwgasmfaa", VX (4, 184), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8647 {"evdotpwxgasmfaa", VX (4, 185), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8648 {"evdotpwgasmfraa", VX (4, 186), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8649 {"evdotpwxgasmfraa", VX (4, 187), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8650 {"evdotpwgssmfaa", VX (4, 188), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8651 {"evdotpwxgssmfaa", VX (4, 189), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8652 {"evdotpwgssmfraa", VX (4, 190), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8653 {"evdotpwxgssmfraa", VX (4, 191), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8654 {"evdotphihcssi", VX (4, 256), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8655 {"evdotplohcssi", VX (4, 257), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8656 {"evdotphihcssf", VX (4, 258), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8657 {"evdotplohcssf", VX (4, 259), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8658 {"evdotphihcsmi", VX (4, 264), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8659 {"evdotplohcsmi", VX (4, 265), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8660 {"evdotphihcssfr", VX (4, 266), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8661 {"evdotplohcssfr", VX (4, 267), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8662 {"evdotphihcssiaaw3", VX (4, 272), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8663 {"evdotplohcssiaaw3", VX (4, 273), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8664 {"evdotphihcssfaaw3", VX (4, 274), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8665 {"evdotplohcssfaaw3", VX (4, 275), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8666 {"evdotphihcsmiaaw3", VX (4, 280), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8667 {"evdotplohcsmiaaw3", VX (4, 281), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8668 {"evdotphihcssfraaw3", VX (4, 282), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8669 {"evdotplohcssfraaw3", VX (4, 283), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8670 {"evdotphihcssia", VX (4, 288), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8671 {"evdotplohcssia", VX (4, 289), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8672 {"evdotphihcssfa", VX (4, 290), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8673 {"evdotplohcssfa", VX (4, 291), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8674 {"evdotphihcsmia", VX (4, 296), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8675 {"evdotplohcsmia", VX (4, 297), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8676 {"evdotphihcssfra", VX (4, 298), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8677 {"evdotplohcssfra", VX (4, 299), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8678 {"evdotphihcssiaaw", VX (4, 304), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8679 {"evdotplohcssiaaw", VX (4, 305), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8680 {"evdotphihcssfaaw", VX (4, 306), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8681 {"evdotplohcssfaaw", VX (4, 307), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8682 {"evdotphihcsmiaaw", VX (4, 312), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8683 {"evdotplohcsmiaaw", VX (4, 313), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8684 {"evdotphihcssfraaw", VX (4, 314), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8685 {"evdotplohcssfraaw", VX (4, 315), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8686 {"evdotphausi", VX (4, 320), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8687 {"evdotphassi", VX (4, 321), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8688 {"evdotphasusi", VX (4, 322), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8689 {"evdotphassf", VX (4, 323), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8690 {"evdotphsssf", VX (4, 327), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8691 {"evdotphaumi", VX (4, 328), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8692 {"evdotphasmi", VX (4, 329), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8693 {"evdotphasumi", VX (4, 330), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8694 {"evdotphassfr", VX (4, 331), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8695 {"evdotphssmi", VX (4, 333), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8696 {"evdotphsssfr", VX (4, 335), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8697 {"evdotphausiaaw3", VX (4, 336), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8698 {"evdotphassiaaw3", VX (4, 337), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8699 {"evdotphasusiaaw3", VX (4, 338), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8700 {"evdotphassfaaw3", VX (4, 339), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8701 {"evdotphsssiaaw3", VX (4, 341), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8702 {"evdotphsssfaaw3", VX (4, 343), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8703 {"evdotphaumiaaw3", VX (4, 344), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8704 {"evdotphasmiaaw3", VX (4, 345), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8705 {"evdotphasumiaaw3", VX (4, 346), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8706 {"evdotphassfraaw3", VX (4, 347), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8707 {"evdotphssmiaaw3", VX (4, 349), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8708 {"evdotphsssfraaw3", VX (4, 351), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8709 {"evdotphausia", VX (4, 352), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8710 {"evdotphassia", VX (4, 353), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8711 {"evdotphasusia", VX (4, 354), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8712 {"evdotphassfa", VX (4, 355), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8713 {"evdotphsssfa", VX (4, 359), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8714 {"evdotphaumia", VX (4, 360), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8715 {"evdotphasmia", VX (4, 361), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8716 {"evdotphasumia", VX (4, 362), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8717 {"evdotphassfra", VX (4, 363), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8718 {"evdotphssmia", VX (4, 365), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8719 {"evdotphsssfra", VX (4, 367), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8720 {"evdotphausiaaw", VX (4, 368), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8721 {"evdotphassiaaw", VX (4, 369), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8722 {"evdotphasusiaaw", VX (4, 370), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8723 {"evdotphassfaaw", VX (4, 371), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8724 {"evdotphsssiaaw", VX (4, 373), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8725 {"evdotphsssfaaw", VX (4, 375), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8726 {"evdotphaumiaaw", VX (4, 376), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8727 {"evdotphasmiaaw", VX (4, 377), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8728 {"evdotphasumiaaw", VX (4, 378), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8729 {"evdotphassfraaw", VX (4, 379), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8730 {"evdotphssmiaaw", VX (4, 381), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8731 {"evdotphsssfraaw", VX (4, 383), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8732 {"evdotp4hgaumi", VX (4, 384), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8733 {"evdotp4hgasmi", VX (4, 385), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8734 {"evdotp4hgasumi", VX (4, 386), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8735 {"evdotp4hgasmf", VX (4, 387), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8736 {"evdotp4hgssmi", VX (4, 388), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8737 {"evdotp4hgssmf", VX (4, 389), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8738 {"evdotp4hxgasmi", VX (4, 390), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8739 {"evdotp4hxgasmf", VX (4, 391), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8740 {"evdotpbaumi", VX (4, 392), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8741 {"evdotpbasmi", VX (4, 393), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8742 {"evdotpbasumi", VX (4, 394), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8743 {"evdotp4hxgssmi", VX (4, 398), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8744 {"evdotp4hxgssmf", VX (4, 399), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8745 {"evdotp4hgaumiaa3", VX (4, 400), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8746 {"evdotp4hgasmiaa3", VX (4, 401), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8747 {"evdotp4hgasumiaa3", VX (4, 402), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8748 {"evdotp4hgasmfaa3", VX (4, 403), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8749 {"evdotp4hgssmiaa3", VX (4, 404), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8750 {"evdotp4hgssmfaa3", VX (4, 405), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8751 {"evdotp4hxgasmiaa3", VX (4, 406), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8752 {"evdotp4hxgasmfaa3", VX (4, 407), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8753 {"evdotpbaumiaaw3", VX (4, 408), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8754 {"evdotpbasmiaaw3", VX (4, 409), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8755 {"evdotpbasumiaaw3", VX (4, 410), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8756 {"evdotp4hxgssmiaa3", VX (4, 414), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8757 {"evdotp4hxgssmfaa3", VX (4, 415), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8758 {"evdotp4hgaumia", VX (4, 416), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8759 {"evdotp4hgasmia", VX (4, 417), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8760 {"evdotp4hgasumia", VX (4, 418), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8761 {"evdotp4hgasmfa", VX (4, 419), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8762 {"evdotp4hgssmia", VX (4, 420), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8763 {"evdotp4hgssmfa", VX (4, 421), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8764 {"evdotp4hxgasmia", VX (4, 422), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8765 {"evdotp4hxgasmfa", VX (4, 423), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8766 {"evdotpbaumia", VX (4, 424), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8767 {"evdotpbasmia", VX (4, 425), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8768 {"evdotpbasumia", VX (4, 426), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8769 {"evdotp4hxgssmia", VX (4, 430), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8770 {"evdotp4hxgssmfa", VX (4, 431), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8771 {"evdotp4hgaumiaa", VX (4, 432), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8772 {"evdotp4hgasmiaa", VX (4, 433), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8773 {"evdotp4hgasumiaa", VX (4, 434), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8774 {"evdotp4hgasmfaa", VX (4, 435), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8775 {"evdotp4hgssmiaa", VX (4, 436), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8776 {"evdotp4hgssmfaa", VX (4, 437), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8777 {"evdotp4hxgasmiaa", VX (4, 438), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8778 {"evdotp4hxgasmfaa", VX (4, 439), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8779 {"evdotpbaumiaaw", VX (4, 440), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8780 {"evdotpbasmiaaw", VX (4, 441), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8781 {"evdotpbasumiaaw", VX (4, 442), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8782 {"evdotp4hxgssmiaa", VX (4, 446), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8783 {"evdotp4hxgssmfaa", VX (4, 447), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8784 {"evdotpwausi", VX (4, 448), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8785 {"evdotpwassi", VX (4, 449), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8786 {"evdotpwasusi", VX (4, 450), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8787 {"evdotpwaumi", VX (4, 456), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8788 {"evdotpwasmi", VX (4, 457), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8789 {"evdotpwasumi", VX (4, 458), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8790 {"evdotpwssmi", VX (4, 461), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8791 {"evdotpwausiaa3", VX (4, 464), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8792 {"evdotpwassiaa3", VX (4, 465), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8793 {"evdotpwasusiaa3", VX (4, 466), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8794 {"evdotpwsssiaa3", VX (4, 469), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8795 {"evdotpwaumiaa3", VX (4, 472), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8796 {"evdotpwasmiaa3", VX (4, 473), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8797 {"evdotpwasumiaa3", VX (4, 474), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8798 {"evdotpwssmiaa3", VX (4, 477), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8799 {"evdotpwausia", VX (4, 480), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8800 {"evdotpwassia", VX (4, 481), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8801 {"evdotpwasusia", VX (4, 482), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8802 {"evdotpwaumia", VX (4, 488), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8803 {"evdotpwasmia", VX (4, 489), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8804 {"evdotpwasumia", VX (4, 490), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8805 {"evdotpwssmia", VX (4, 493), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8806 {"evdotpwausiaa", VX (4, 496), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8807 {"evdotpwassiaa", VX (4, 497), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8808 {"evdotpwasusiaa", VX (4, 498), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8809 {"evdotpwsssiaa", VX (4, 501), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8810 {"evdotpwaumiaa", VX (4, 504), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8811 {"evdotpwasmiaa", VX (4, 505), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8812 {"evdotpwasumiaa", VX (4, 506), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8813 {"evdotpwssmiaa", VX (4, 509), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8814 {"evaddib", VX (4, 515), VX_MASK, PPCSPE2, 0, {RD, RB, UIMM}}, 8815 {"evaddih", VX (4, 513), VX_MASK, PPCSPE2, 0, {RD, RB, UIMM}}, 8816 {"evsubifh", VX (4, 517), VX_MASK, PPCSPE2, 0, {RD, UIMM, RB}}, 8817 {"evsubifb", VX (4, 519), VX_MASK, PPCSPE2, 0, {RD, UIMM, RB}}, 8818 {"evabsb", VX_RB_CONST(4, 520, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8819 {"evabsh", VX_RB_CONST(4, 520, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8820 {"evabsd", VX_RB_CONST(4, 520, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8821 {"evabss", VX_RB_CONST(4, 520, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8822 {"evabsbs", VX_RB_CONST(4, 520, 10), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8823 {"evabshs", VX_RB_CONST(4, 520, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8824 {"evabsds", VX_RB_CONST(4, 520, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8825 {"evnegwo", VX_RB_CONST(4, 521, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8826 {"evnegb", VX_RB_CONST(4, 521, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8827 {"evnegbo", VX_RB_CONST(4, 521, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8828 {"evnegh", VX_RB_CONST(4, 521, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8829 {"evnegho", VX_RB_CONST(4, 521, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8830 {"evnegd", VX_RB_CONST(4, 521, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8831 {"evnegs", VX_RB_CONST(4, 521, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8832 {"evnegwos", VX_RB_CONST(4, 521, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8833 {"evnegbs", VX_RB_CONST(4, 521, 10), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8834 {"evnegbos", VX_RB_CONST(4, 521, 11), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8835 {"evneghs", VX_RB_CONST(4, 521, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8836 {"evneghos", VX_RB_CONST(4, 521, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8837 {"evnegds", VX_RB_CONST(4, 521, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8838 {"evextzb", VX_RB_CONST(4, 522, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8839 {"evextsbh", VX_RB_CONST(4, 522, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8840 {"evextsw", VX_RB_CONST(4, 523, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8841 {"evrndwh", VX_RB_CONST(4, 524, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8842 {"evrndhb", VX_RB_CONST(4, 524, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8843 {"evrnddw", VX_RB_CONST(4, 524, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8844 {"evrndwhus", VX_RB_CONST(4, 524, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8845 {"evrndwhss", VX_RB_CONST(4, 524, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8846 {"evrndhbus", VX_RB_CONST(4, 524, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8847 {"evrndhbss", VX_RB_CONST(4, 524, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8848 {"evrnddwus", VX_RB_CONST(4, 524, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8849 {"evrnddwss", VX_RB_CONST(4, 524, 15), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8850 {"evrndwnh", VX_RB_CONST(4, 524, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8851 {"evrndhnb", VX_RB_CONST(4, 524, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8852 {"evrnddnw", VX_RB_CONST(4, 524, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8853 {"evrndwnhus", VX_RB_CONST(4, 524, 24), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8854 {"evrndwnhss", VX_RB_CONST(4, 524, 25), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8855 {"evrndhnbus", VX_RB_CONST(4, 524, 28), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8856 {"evrndhnbss", VX_RB_CONST(4, 524, 29), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8857 {"evrnddnwus", VX_RB_CONST(4, 524, 30), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8858 {"evrnddnwss", VX_RB_CONST(4, 524, 31), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8859 {"evcntlzh", VX_RB_CONST(4, 525, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8860 {"evcntlsh", VX_RB_CONST(4, 526, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8861 {"evpopcntb", VX_RB_CONST(4, 526, 26), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8862 {"circinc", VX (4, 528), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8863 {"evunpkhibui", VX_RB_CONST(4, 540, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8864 {"evunpkhibsi", VX_RB_CONST(4, 540, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8865 {"evunpkhihui", VX_RB_CONST(4, 540, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8866 {"evunpkhihsi", VX_RB_CONST(4, 540, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8867 {"evunpklobui", VX_RB_CONST(4, 540, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8868 {"evunpklobsi", VX_RB_CONST(4, 540, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8869 {"evunpklohui", VX_RB_CONST(4, 540, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8870 {"evunpklohsi", VX_RB_CONST(4, 540, 7), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8871 {"evunpklohf", VX_RB_CONST(4, 540, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8872 {"evunpkhihf", VX_RB_CONST(4, 540, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8873 {"evunpklowgsf", VX_RB_CONST(4, 540, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8874 {"evunpkhiwgsf", VX_RB_CONST(4, 540, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8875 {"evsatsduw", VX_RB_CONST(4, 540, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8876 {"evsatsdsw", VX_RB_CONST(4, 540, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8877 {"evsatshub", VX_RB_CONST(4, 540, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8878 {"evsatshsb", VX_RB_CONST(4, 540, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8879 {"evsatuwuh", VX_RB_CONST(4, 540, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8880 {"evsatswsh", VX_RB_CONST(4, 540, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8881 {"evsatswuh", VX_RB_CONST(4, 540, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8882 {"evsatuhub", VX_RB_CONST(4, 540, 23), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8883 {"evsatuduw", VX_RB_CONST(4, 540, 24), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8884 {"evsatuwsw", VX_RB_CONST(4, 540, 25), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8885 {"evsatshuh", VX_RB_CONST(4, 540, 26), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8886 {"evsatuhsh", VX_RB_CONST(4, 540, 27), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8887 {"evsatswuw", VX_RB_CONST(4, 540, 28), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8888 {"evsatswgsdf", VX_RB_CONST(4, 540, 29), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8889 {"evsatsbub", VX_RB_CONST(4, 540, 30), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8890 {"evsatubsb", VX_RB_CONST(4, 540, 31), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8891 {"evmaxhpuw", VX_RB_CONST(4, 541, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8892 {"evmaxhpsw", VX_RB_CONST(4, 541, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8893 {"evmaxbpuh", VX_RB_CONST(4, 541, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8894 {"evmaxbpsh", VX_RB_CONST(4, 541, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8895 {"evmaxwpud", VX_RB_CONST(4, 541, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8896 {"evmaxwpsd", VX_RB_CONST(4, 541, 7), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8897 {"evminhpuw", VX_RB_CONST(4, 541, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8898 {"evminhpsw", VX_RB_CONST(4, 541, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8899 {"evminbpuh", VX_RB_CONST(4, 541, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8900 {"evminbpsh", VX_RB_CONST(4, 541, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8901 {"evminwpud", VX_RB_CONST(4, 541, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8902 {"evminwpsd", VX_RB_CONST(4, 541, 15), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 8903 {"evmaxmagws", VX (4, 543), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8904 {"evsl", VX (4, 549), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8905 {"evsli", VX (4, 551), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}}, 8906 {"evsplatie", VX_RB_CONST (4, 553, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 8907 {"evsplatib", VX_RB_CONST (4, 553, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 8908 {"evsplatibe", VX_RB_CONST (4, 553, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 8909 {"evsplatih", VX_RB_CONST (4, 553, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 8910 {"evsplatihe", VX_RB_CONST (4, 553, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 8911 {"evsplatid", VX_RB_CONST (4, 553, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 8912 {"evsplatia", VX_RB_CONST (4, 553, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 8913 {"evsplatiea", VX_RB_CONST (4, 553, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 8914 {"evsplatiba", VX_RB_CONST (4, 553, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 8915 {"evsplatibea", VX_RB_CONST (4, 553, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 8916 {"evsplatiha", VX_RB_CONST (4, 553, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 8917 {"evsplatihea", VX_RB_CONST (4, 553, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 8918 {"evsplatida", VX_RB_CONST (4, 553, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 8919 {"evsplatfio", VX_RB_CONST (4, 555, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 8920 {"evsplatfib", VX_RB_CONST (4, 555, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 8921 {"evsplatfibo", VX_RB_CONST (4, 555, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 8922 {"evsplatfih", VX_RB_CONST (4, 555, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 8923 {"evsplatfiho", VX_RB_CONST (4, 555, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 8924 {"evsplatfid", VX_RB_CONST (4, 555, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 8925 {"evsplatfia", VX_RB_CONST (4, 555, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 8926 {"evsplatfioa", VX_RB_CONST (4, 555, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 8927 {"evsplatfiba", VX_RB_CONST (4, 555, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 8928 {"evsplatfiboa", VX_RB_CONST (4, 555, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 8929 {"evsplatfiha", VX_RB_CONST (4, 555, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 8930 {"evsplatfihoa", VX_RB_CONST (4, 555, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 8931 {"evsplatfida", VX_RB_CONST (4, 555, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 8932 {"evcmpgtdu", VX_SPE_CRFD (4, 560, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, 8933 {"evcmpgtds", VX_SPE_CRFD (4, 561, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, 8934 {"evcmpltdu", VX_SPE_CRFD (4, 562, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, 8935 {"evcmpltds", VX_SPE_CRFD (4, 563, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, 8936 {"evcmpeqd", VX_SPE_CRFD (4, 564, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, 8937 {"evswapbhilo", VX (4, 568), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8938 {"evswapblohi", VX (4, 569), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8939 {"evswaphhilo", VX (4, 570), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8940 {"evswaphlohi", VX (4, 571), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8941 {"evswaphe", VX (4, 572), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8942 {"evswaphhi", VX (4, 573), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8943 {"evswaphlo", VX (4, 574), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8944 {"evswapho", VX (4, 575), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8945 {"evinsb", VX (4, 584), VX_MASK_DDD, PPCSPE2, 0, {RD, RA, DDD, BBB}}, 8946 {"evxtrb", VX (4, 586), VX_MASK_DDD, PPCSPE2, 0, {RD, RA, DDD, BBB}}, 8947 {"evsplath", VX_SPE2_HH (4, 588, 0, 0), VX_SPE2_HH_MASK, PPCSPE2, 0, {RD, RA, HH}}, 8948 {"evsplatb", VX_SPE2_SPLATB (4, 588, 2), VX_SPE2_SPLATB_MASK, PPCSPE2, 0, {RD, RA, BBB}}, 8949 {"evinsh", VX_SPE2_DDHH (4, 589, 0), VX_SPE2_DDHH_MASK, PPCSPE2, 0, {RD, RA, DD, HH}}, 8950 {"evclrbe", VX_SPE2_CLR (4, 590, 0), VX_SPE2_CLR_MASK, PPCSPE2, 0, {RD, RA, MMMM}}, 8951 {"evclrbo", VX_SPE2_CLR (4, 590, 1), VX_SPE2_CLR_MASK, PPCSPE2, 0, {RD, RA, MMMM}}, 8952 {"evclrh", VX_SPE2_CLR (4, 591, 1), VX_SPE2_CLR_MASK, PPCSPE2, 0, {RD, RA, MMMM}}, 8953 {"evxtrh", VX_SPE2_DDHH (4, 591, 0), VX_SPE2_DDHH_MASK, PPCSPE2, 0, {RD, RA, DD, HH}}, 8954 {"evselbitm0", VX (4, 592), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8955 {"evselbitm1", VX (4, 593), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8956 {"evselbit", VX (4, 594), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8957 {"evperm", VX (4, 596), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8958 {"evperm2", VX (4, 597), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8959 {"evperm3", VX (4, 598), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8960 {"evxtrd", VX (4, 600), VX_OFF_SPE2_MASK, PPCSPE2, 0, {RD, RA, RB, VX_OFF_SPE2}}, 8961 {"evsrbu", VX (4, 608), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8962 {"evsrbs", VX (4, 609), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8963 {"evsrbiu", VX (4, 610), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}}, 8964 {"evsrbis", VX (4, 611), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}}, 8965 {"evslb", VX (4, 612), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8966 {"evrlb", VX (4, 613), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8967 {"evslbi", VX (4, 614), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}}, 8968 {"evrlbi", VX (4, 615), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}}, 8969 {"evsrhu", VX (4, 616), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8970 {"evsrhs", VX (4, 617), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8971 {"evsrhiu", VX (4, 618), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}}, 8972 {"evsrhis", VX (4, 619), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}}, 8973 {"evslh", VX (4, 620), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8974 {"evrlh", VX (4, 621), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8975 {"evslhi", VX (4, 622), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}}, 8976 {"evrlhi", VX (4, 623), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}}, 8977 {"evsru", VX (4, 624), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8978 {"evsrs", VX (4, 625), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8979 {"evsriu", VX (4, 626), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}}, 8980 {"evsris", VX (4, 627), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}}, 8981 {"evlvsl", VX (4, 628), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8982 {"evlvsr", VX (4, 629), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8983 {"evsroiu", VX_SPE2_OCTET (4, 631, 0), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}}, 8984 {"evsrois", VX_SPE2_OCTET (4, 631, 1), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}}, 8985 {"evsloi", VX_SPE2_OCTET (4, 631, 2), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}}, 8986 {"evldbx", VX (4, 774), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8987 {"evldb", VX (4, 775), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8, RA}}, 8988 {"evlhhsplathx", VX (4, 778), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8989 {"evlhhsplath", VX (4, 779), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2, RA}}, 8990 {"evlwbsplatwx", VX (4, 786), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8991 {"evlwbsplatw", VX (4, 787), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, 8992 {"evlwhsplatwx", VX (4, 794), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8993 {"evlwhsplatw", VX (4, 795), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, 8994 {"evlbbsplatbx", VX (4, 798), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8995 {"evlbbsplatb", VX (4, 799), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_1, RA}}, 8996 {"evstdbx", VX (4, 806), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 8997 {"evstdb", VX (4, 807), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8, RA}}, 8998 {"evlwbex", VX (4, 810), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 8999 {"evlwbe", VX (4, 811), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, 9000 {"evlwboux", VX (4, 812), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9001 {"evlwbou", VX (4, 813), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, 9002 {"evlwbosx", VX (4, 814), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9003 {"evlwbos", VX (4, 815), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, 9004 {"evstwbex", VX (4, 818), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 9005 {"evstwbe", VX (4, 819), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}}, 9006 {"evstwbox", VX (4, 822), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 9007 {"evstwbo", VX (4, 823), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}}, 9008 {"evstwbx", VX (4, 826), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 9009 {"evstwb", VX (4, 827), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}}, 9010 {"evsthbx", VX (4, 830), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 9011 {"evsthb", VX (4, 831), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_2, RA}}, 9012 {"evlddmx", VX (4, 832), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9013 {"evlddu", VX (4, 833), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}}, 9014 {"evldwmx", VX (4, 834), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9015 {"evldwu", VX (4, 835), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}}, 9016 {"evldhmx", VX (4, 836), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9017 {"evldhu", VX (4, 837), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}}, 9018 {"evldbmx", VX (4, 838), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9019 {"evldbu", VX (4, 839), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}}, 9020 {"evlhhesplatmx", VX (4, 840), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9021 {"evlhhesplatu", VX (4, 841), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}}, 9022 {"evlhhsplathmx", VX (4, 842), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9023 {"evlhhsplathu", VX (4, 843), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}}, 9024 {"evlhhousplatmx", VX (4, 844), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9025 {"evlhhousplatu", VX (4, 845), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}}, 9026 {"evlhhossplatmx", VX (4, 846), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9027 {"evlhhossplatu", VX (4, 847), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}}, 9028 {"evlwhemx", VX (4, 848), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9029 {"evlwheu", VX (4, 849), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, 9030 {"evlwbsplatwmx", VX (4, 850), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9031 {"evlwbsplatwu", VX (4, 851), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, 9032 {"evlwhoumx", VX (4, 852), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9033 {"evlwhouu", VX (4, 853), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, 9034 {"evlwhosmx", VX (4, 854), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9035 {"evlwhosu", VX (4, 855), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, 9036 {"evlwwsplatmx", VX (4, 856), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9037 {"evlwwsplatu", VX (4, 857), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, 9038 {"evlwhsplatwmx", VX (4, 858), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9039 {"evlwhsplatwu", VX (4, 859), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, 9040 {"evlwhsplatmx", VX (4, 860), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9041 {"evlwhsplatu", VX (4, 861), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, 9042 {"evlbbsplatbmx", VX (4, 862), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9043 {"evlbbsplatbu", VX (4, 863), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_1_EX0, RA}}, 9044 {"evstddmx", VX (4, 864), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 9045 {"evstddu", VX (4, 865), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}}, 9046 {"evstdwmx", VX (4, 866), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 9047 {"evstdwu", VX (4, 867), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}}, 9048 {"evstdhmx", VX (4, 868), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 9049 {"evstdhu", VX (4, 869), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}}, 9050 {"evstdbmx", VX (4, 870), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 9051 {"evstdbu", VX (4, 871), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}}, 9052 {"evlwbemx", VX (4, 874), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9053 {"evlwbeu", VX (4, 875), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, 9054 {"evlwboumx", VX (4, 876), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9055 {"evlwbouu", VX (4, 877), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, 9056 {"evlwbosmx", VX (4, 878), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9057 {"evlwbosu", VX (4, 879), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, 9058 {"evstwhemx", VX (4, 880), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 9059 {"evstwheu", VX (4, 881), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, 9060 {"evstwbemx", VX (4, 882), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 9061 {"evstwbeu", VX (4, 883), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, 9062 {"evstwhomx", VX (4, 884), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 9063 {"evstwhou", VX (4, 885), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, 9064 {"evstwbomx", VX (4, 886), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 9065 {"evstwbou", VX (4, 887), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, 9066 {"evstwwemx", VX (4, 888), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 9067 {"evstwweu", VX (4, 889), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, 9068 {"evstwbmx", VX (4, 890), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 9069 {"evstwbu", VX (4, 891), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, 9070 {"evstwwomx", VX (4, 892), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 9071 {"evstwwou", VX (4, 893), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, 9072 {"evsthbmx", VX (4, 894), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 9073 {"evsthbu", VX (4, 895), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_2_EX0, RA}}, 9074 {"evmhusi", VX (4, 1024), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9075 {"evmhssi", VX (4, 1025), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9076 {"evmhsusi", VX (4, 1026), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9077 {"evmhssf", VX (4, 1028), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9078 {"evmhumi", VX (4, 1029), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9079 {"evmhssfr", VX (4, 1030), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9080 {"evmhesumi", VX (4, 1034), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9081 {"evmhosumi", VX (4, 1038), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9082 {"evmbeumi", VX (4, 1048), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9083 {"evmbesmi", VX (4, 1049), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9084 {"evmbesumi", VX (4, 1050), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9085 {"evmboumi", VX (4, 1052), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9086 {"evmbosmi", VX (4, 1053), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9087 {"evmbosumi", VX (4, 1054), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9088 {"evmhesumia", VX (4, 1066), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9089 {"evmhosumia", VX (4, 1070), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9090 {"evmbeumia", VX (4, 1080), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9091 {"evmbesmia", VX (4, 1081), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9092 {"evmbesumia", VX (4, 1082), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9093 {"evmboumia", VX (4, 1084), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9094 {"evmbosmia", VX (4, 1085), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9095 {"evmbosumia", VX (4, 1086), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9096 {"evmwusiw", VX (4, 1088), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9097 {"evmwssiw", VX (4, 1089), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9098 {"evmwhssfr", VX (4, 1094), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9099 {"evmwehgsmfr", VX (4, 1110), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9100 {"evmwehgsmf", VX (4, 1111), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9101 {"evmwohgsmfr", VX (4, 1118), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9102 {"evmwohgsmf", VX (4, 1119), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9103 {"evmwhssfra", VX (4, 1126), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9104 {"evmwehgsmfra", VX (4, 1142), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9105 {"evmwehgsmfa", VX (4, 1143), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9106 {"evmwohgsmfra", VX (4, 1150), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9107 {"evmwohgsmfa", VX (4, 1151), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9108 {"evaddusiaa", VX_RB_CONST(4, 1152, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 9109 {"evaddssiaa", VX_RB_CONST(4, 1153, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 9110 {"evsubfusiaa", VX_RB_CONST(4, 1154, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 9111 {"evsubfssiaa", VX_RB_CONST(4, 1155, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 9112 {"evaddsmiaa", VX_RB_CONST(4, 1156, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 9113 {"evsubfsmiaa", VX_RB_CONST(4, 1158, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 9114 {"evaddh", VX (4, 1160), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9115 {"evaddhss", VX (4, 1161), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9116 {"evsubfh", VX (4, 1162), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9117 {"evsubfhss", VX (4, 1163), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9118 {"evaddhx", VX (4, 1164), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9119 {"evaddhxss", VX (4, 1165), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9120 {"evsubfhx", VX (4, 1166), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9121 {"evsubfhxss", VX (4, 1167), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9122 {"evaddd", VX (4, 1168), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9123 {"evadddss", VX (4, 1169), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9124 {"evsubfd", VX (4, 1170), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9125 {"evsubfdss", VX (4, 1171), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9126 {"evaddb", VX (4, 1172), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9127 {"evaddbss", VX (4, 1173), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9128 {"evsubfb", VX (4, 1174), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9129 {"evsubfbss", VX (4, 1175), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9130 {"evaddsubfh", VX (4, 1176), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9131 {"evaddsubfhss", VX (4, 1177), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9132 {"evsubfaddh", VX (4, 1178), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9133 {"evsubfaddhss", VX (4, 1179), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9134 {"evaddsubfhx", VX (4, 1180), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9135 {"evaddsubfhxss", VX (4, 1181), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9136 {"evsubfaddhx", VX (4, 1182), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9137 {"evsubfaddhxss", VX (4, 1183), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9138 {"evadddus", VX (4, 1184), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9139 {"evaddbus", VX (4, 1185), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9140 {"evsubfdus", VX (4, 1186), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9141 {"evsubfbus", VX (4, 1187), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9142 {"evaddwus", VX (4, 1188), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9143 {"evaddwxus", VX (4, 1189), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9144 {"evsubfwus", VX (4, 1190), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9145 {"evsubfwxus", VX (4, 1191), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9146 {"evadd2subf2h", VX (4, 1192), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9147 {"evadd2subf2hss", VX (4, 1193), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9148 {"evsubf2add2h", VX (4, 1194), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9149 {"evsubf2add2hss", VX (4, 1195), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9150 {"evaddhus", VX (4, 1196), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9151 {"evaddhxus", VX (4, 1197), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9152 {"evsubfhus", VX (4, 1198), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9153 {"evsubfhxus", VX (4, 1199), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9154 {"evaddwss", VX (4, 1201), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9155 {"evsubfwss", VX (4, 1203), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9156 {"evaddwx", VX (4, 1204), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9157 {"evaddwxss", VX (4, 1205), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9158 {"evsubfwx", VX (4, 1206), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9159 {"evsubfwxss", VX (4, 1207), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9160 {"evaddsubfw", VX (4, 1208), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9161 {"evaddsubfwss", VX (4, 1209), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9162 {"evsubfaddw", VX (4, 1210), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9163 {"evsubfaddwss", VX (4, 1211), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9164 {"evaddsubfwx", VX (4, 1212), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9165 {"evaddsubfwxss", VX (4, 1213), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9166 {"evsubfaddwx", VX (4, 1214), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9167 {"evsubfaddwxss", VX (4, 1215), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9168 {"evmar", VX_SPE2_EVMAR (4, 1220), VX_SPE2_EVMAR_MASK, PPCSPE2, 0, {RD}}, 9169 {"evsumwu", VX_RB_CONST(4, 1221, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 9170 {"evsumws", VX_RB_CONST(4, 1221, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 9171 {"evsum4bu", VX_RB_CONST(4, 1221, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 9172 {"evsum4bs", VX_RB_CONST(4, 1221, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 9173 {"evsum2hu", VX_RB_CONST(4, 1221, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 9174 {"evsum2hs", VX_RB_CONST(4, 1221, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 9175 {"evdiff2his", VX_RB_CONST(4, 1221, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 9176 {"evsum2his", VX_RB_CONST(4, 1221, 7), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 9177 {"evsumwua", VX_RB_CONST(4, 1221, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 9178 {"evsumwsa", VX_RB_CONST(4, 1221, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 9179 {"evsum4bua", VX_RB_CONST(4, 1221, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 9180 {"evsum4bsa", VX_RB_CONST(4, 1221, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 9181 {"evsum2hua", VX_RB_CONST(4, 1221, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 9182 {"evsum2hsa", VX_RB_CONST(4, 1221, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 9183 {"evdiff2hisa", VX_RB_CONST(4, 1221, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 9184 {"evsum2hisa", VX_RB_CONST(4, 1221, 23), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 9185 {"evsumwuaa", VX_RB_CONST(4, 1221, 24), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 9186 {"evsumwsaa", VX_RB_CONST(4, 1221, 25), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 9187 {"evsum4buaaw", VX_RB_CONST(4, 1221, 26), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 9188 {"evsum4bsaaw", VX_RB_CONST(4, 1221, 27), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 9189 {"evsum2huaaw", VX_RB_CONST(4, 1221, 28), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 9190 {"evsum2hsaaw", VX_RB_CONST(4, 1221, 29), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 9191 {"evdiff2hisaaw", VX_RB_CONST(4, 1221, 30), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 9192 {"evsum2hisaaw", VX_RB_CONST(4, 1221, 31), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 9193 {"evdivwsf", VX (4, 1228), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9194 {"evdivwuf", VX (4, 1229), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9195 {"evdivs", VX (4, 1230), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9196 {"evdivu", VX (4, 1231), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9197 {"evaddwegsi", VX (4, 1232), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9198 {"evaddwegsf", VX (4, 1233), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9199 {"evsubfwegsi", VX (4, 1234), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9200 {"evsubfwegsf", VX (4, 1235), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9201 {"evaddwogsi", VX (4, 1236), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9202 {"evaddwogsf", VX (4, 1237), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9203 {"evsubfwogsi", VX (4, 1238), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9204 {"evsubfwogsf", VX (4, 1239), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9205 {"evaddhhiuw", VX (4, 1240), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9206 {"evaddhhisw", VX (4, 1241), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9207 {"evsubfhhiuw", VX (4, 1242), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9208 {"evsubfhhisw", VX (4, 1243), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9209 {"evaddhlouw", VX (4, 1244), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9210 {"evaddhlosw", VX (4, 1245), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9211 {"evsubfhlouw", VX (4, 1246), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9212 {"evsubfhlosw", VX (4, 1247), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9213 {"evmhesusiaaw", VX (4, 1282), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9214 {"evmhosusiaaw", VX (4, 1286), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9215 {"evmhesumiaaw", VX (4, 1290), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9216 {"evmhosumiaaw", VX (4, 1294), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9217 {"evmbeusiaah", VX (4, 1296), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9218 {"evmbessiaah", VX (4, 1297), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9219 {"evmbesusiaah", VX (4, 1298), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9220 {"evmbousiaah", VX (4, 1300), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9221 {"evmbossiaah", VX (4, 1301), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9222 {"evmbosusiaah", VX (4, 1302), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9223 {"evmbeumiaah", VX (4, 1304), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9224 {"evmbesmiaah", VX (4, 1305), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9225 {"evmbesumiaah", VX (4, 1306), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9226 {"evmboumiaah", VX (4, 1308), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9227 {"evmbosmiaah", VX (4, 1309), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9228 {"evmbosumiaah", VX (4, 1310), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9229 {"evmwlusiaaw3", VX (4, 1346), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9230 {"evmwlssiaaw3", VX (4, 1347), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9231 {"evmwhssfraaw3", VX (4, 1348), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9232 {"evmwhssfaaw3", VX (4, 1349), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9233 {"evmwhssfraaw", VX (4, 1350), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9234 {"evmwhssfaaw", VX (4, 1351), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9235 {"evmwlumiaaw3", VX (4, 1354), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9236 {"evmwlsmiaaw3", VX (4, 1355), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9237 {"evmwusiaa", VX (4, 1360), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9238 {"evmwssiaa", VX (4, 1361), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9239 {"evmwehgsmfraa", VX (4, 1366), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9240 {"evmwehgsmfaa", VX (4, 1367), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9241 {"evmwohgsmfraa", VX (4, 1374), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9242 {"evmwohgsmfaa", VX (4, 1375), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9243 {"evmhesusianw", VX (4, 1410), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9244 {"evmhosusianw", VX (4, 1414), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9245 {"evmhesumianw", VX (4, 1418), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9246 {"evmhosumianw", VX (4, 1422), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9247 {"evmbeusianh", VX (4, 1424), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9248 {"evmbessianh", VX (4, 1425), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9249 {"evmbesusianh", VX (4, 1426), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9250 {"evmbousianh", VX (4, 1428), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9251 {"evmbossianh", VX (4, 1429), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9252 {"evmbosusianh", VX (4, 1430), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9253 {"evmbeumianh", VX (4, 1432), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9254 {"evmbesmianh", VX (4, 1433), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9255 {"evmbesumianh", VX (4, 1434), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9256 {"evmboumianh", VX (4, 1436), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9257 {"evmbosmianh", VX (4, 1437), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9258 {"evmbosumianh", VX (4, 1438), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9259 {"evmwlusianw3", VX (4, 1474), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9260 {"evmwlssianw3", VX (4, 1475), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9261 {"evmwhssfranw3", VX (4, 1476), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9262 {"evmwhssfanw3", VX (4, 1477), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9263 {"evmwhssfranw", VX (4, 1478), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9264 {"evmwhssfanw", VX (4, 1479), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9265 {"evmwlumianw3", VX (4, 1482), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9266 {"evmwlsmianw3", VX (4, 1483), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9267 {"evmwusian", VX (4, 1488), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9268 {"evmwssian", VX (4, 1489), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9269 {"evmwehgsmfran", VX (4, 1494), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9270 {"evmwehgsmfan", VX (4, 1495), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9271 {"evmwohgsmfran", VX (4, 1502), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9272 {"evmwohgsmfan", VX (4, 1503), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9273 {"evseteqb", VX (4, 1536), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9274 {"evseteqb.", VX (4, 1537), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9275 {"evseteqh", VX (4, 1538), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9276 {"evseteqh.", VX (4, 1539), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9277 {"evseteqw", VX (4, 1540), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9278 {"evseteqw.", VX (4, 1541), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9279 {"evsetgthu", VX (4, 1544), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9280 {"evsetgthu.", VX (4, 1545), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9281 {"evsetgths", VX (4, 1546), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9282 {"evsetgths.", VX (4, 1547), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9283 {"evsetgtwu", VX (4, 1548), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9284 {"evsetgtwu.", VX (4, 1549), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9285 {"evsetgtws", VX (4, 1550), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9286 {"evsetgtws.", VX (4, 1551), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9287 {"evsetgtbu", VX (4, 1552), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9288 {"evsetgtbu.", VX (4, 1553), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9289 {"evsetgtbs", VX (4, 1554), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9290 {"evsetgtbs.", VX (4, 1555), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9291 {"evsetltbu", VX (4, 1556), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9292 {"evsetltbu.", VX (4, 1557), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9293 {"evsetltbs", VX (4, 1558), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9294 {"evsetltbs.", VX (4, 1559), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9295 {"evsetlthu", VX (4, 1560), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9296 {"evsetlthu.", VX (4, 1561), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9297 {"evsetlths", VX (4, 1562), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9298 {"evsetlths.", VX (4, 1563), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9299 {"evsetltwu", VX (4, 1564), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9300 {"evsetltwu.", VX (4, 1565), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9301 {"evsetltws", VX (4, 1566), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9302 {"evsetltws.", VX (4, 1567), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9303 {"evsaduw", VX (4, 1568), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9304 {"evsadsw", VX (4, 1569), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9305 {"evsad4ub", VX (4, 1570), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9306 {"evsad4sb", VX (4, 1571), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9307 {"evsad2uh", VX (4, 1572), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9308 {"evsad2sh", VX (4, 1573), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9309 {"evsaduwa", VX (4, 1576), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9310 {"evsadswa", VX (4, 1577), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9311 {"evsad4uba", VX (4, 1578), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9312 {"evsad4sba", VX (4, 1579), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9313 {"evsad2uha", VX (4, 1580), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9314 {"evsad2sha", VX (4, 1581), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9315 {"evabsdifuw", VX (4, 1584), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9316 {"evabsdifsw", VX (4, 1585), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9317 {"evabsdifub", VX (4, 1586), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9318 {"evabsdifsb", VX (4, 1587), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9319 {"evabsdifuh", VX (4, 1588), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9320 {"evabsdifsh", VX (4, 1589), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9321 {"evsaduwaa", VX (4, 1592), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9322 {"evsadswaa", VX (4, 1593), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9323 {"evsad4ubaaw", VX (4, 1594), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9324 {"evsad4sbaaw", VX (4, 1595), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9325 {"evsad2uhaaw", VX (4, 1596), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9326 {"evsad2shaaw", VX (4, 1597), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9327 {"evpkshubs", VX (4, 1600), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9328 {"evpkshsbs", VX (4, 1601), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9329 {"evpkswuhs", VX (4, 1602), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9330 {"evpkswshs", VX (4, 1603), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9331 {"evpkuhubs", VX (4, 1604), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9332 {"evpkuwuhs", VX (4, 1605), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9333 {"evpkswshilvs", VX (4, 1606), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9334 {"evpkswgshefrs", VX (4, 1607), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9335 {"evpkswshfrs", VX (4, 1608), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9336 {"evpkswshilvfrs", VX (4, 1609), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9337 {"evpksdswfrs", VX (4, 1610), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9338 {"evpksdshefrs", VX (4, 1611), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9339 {"evpkuduws", VX (4, 1612), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9340 {"evpksdsws", VX (4, 1613), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9341 {"evpkswgswfrs", VX (4, 1614), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9342 {"evilveh", VX (4, 1616), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9343 {"evilveoh", VX (4, 1617), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9344 {"evilvhih", VX (4, 1618), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9345 {"evilvhiloh", VX (4, 1619), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9346 {"evilvloh", VX (4, 1620), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9347 {"evilvlohih", VX (4, 1621), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9348 {"evilvoeh", VX (4, 1622), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9349 {"evilvoh", VX (4, 1623), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9350 {"evdlveb", VX (4, 1624), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9351 {"evdlveh", VX (4, 1625), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9352 {"evdlveob", VX (4, 1626), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9353 {"evdlveoh", VX (4, 1627), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9354 {"evdlvob", VX (4, 1628), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9355 {"evdlvoh", VX (4, 1629), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9356 {"evdlvoeb", VX (4, 1630), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9357 {"evdlvoeh", VX (4, 1631), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9358 {"evmaxbu", VX (4, 1632), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9359 {"evmaxbs", VX (4, 1633), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9360 {"evmaxhu", VX (4, 1634), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9361 {"evmaxhs", VX (4, 1635), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9362 {"evmaxwu", VX (4, 1636), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9363 {"evmaxws", VX (4, 1637), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9364 {"evmaxdu", VX (4, 1638), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9365 {"evmaxds", VX (4, 1639), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9366 {"evminbu", VX (4, 1640), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9367 {"evminbs", VX (4, 1641), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9368 {"evminhu", VX (4, 1642), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9369 {"evminhs", VX (4, 1643), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9370 {"evminwu", VX (4, 1644), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9371 {"evminws", VX (4, 1645), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9372 {"evmindu", VX (4, 1646), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9373 {"evminds", VX (4, 1647), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9374 {"evavgwu", VX (4, 1648), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9375 {"evavgws", VX (4, 1649), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9376 {"evavgbu", VX (4, 1650), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9377 {"evavgbs", VX (4, 1651), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9378 {"evavghu", VX (4, 1652), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9379 {"evavghs", VX (4, 1653), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9380 {"evavgdu", VX (4, 1654), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9381 {"evavgds", VX (4, 1655), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9382 {"evavgwur", VX (4, 1656), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9383 {"evavgwsr", VX (4, 1657), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9384 {"evavgbur", VX (4, 1658), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9385 {"evavgbsr", VX (4, 1659), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9386 {"evavghur", VX (4, 1660), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9387 {"evavghsr", VX (4, 1661), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9388 {"evavgdur", VX (4, 1662), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9389 {"evavgdsr", VX (4, 1663), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 9390 }; 9391 9392 const unsigned int spe2_num_opcodes = 9393 sizeof (spe2_opcodes) / sizeof (spe2_opcodes[0]); 9394
Indexes created Tue Mar 03 05:31:39 UTC 2026