xtensa-modules.c revision 1.1
1 /* Xtensa configuration-specific ISA information. 2 Copyright 2003, 2004, 2005, 2007 Free Software Foundation, Inc. 3 4 This file is part of BFD, the Binary File Descriptor library. 5 6 This program is free software; you can redistribute it and/or 7 modify it under the terms of the GNU General Public License as 8 published by the Free Software Foundation; either version 3 of the 9 License, or (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 19 02110-1301, USA. */ 20 21 #include "ansidecl.h" 22 #include <xtensa-isa.h> 23 #include "xtensa-isa-internal.h" 24 25 26 /* Sysregs. */ 28 29 static xtensa_sysreg_internal sysregs[] = { 30 { "LBEG", 0, 0 }, 31 { "LEND", 1, 0 }, 32 { "LCOUNT", 2, 0 }, 33 { "PTEVADDR", 83, 0 }, 34 { "DDR", 104, 0 }, 35 { "176", 176, 0 }, 36 { "208", 208, 0 }, 37 { "INTERRUPT", 226, 0 }, 38 { "INTCLEAR", 227, 0 }, 39 { "CCOUNT", 234, 0 }, 40 { "PRID", 235, 0 }, 41 { "ICOUNT", 236, 0 }, 42 { "CCOMPARE0", 240, 0 }, 43 { "CCOMPARE1", 241, 0 }, 44 { "CCOMPARE2", 242, 0 }, 45 { "EPC1", 177, 0 }, 46 { "EPC2", 178, 0 }, 47 { "EPC3", 179, 0 }, 48 { "EPC4", 180, 0 }, 49 { "EXCSAVE1", 209, 0 }, 50 { "EXCSAVE2", 210, 0 }, 51 { "EXCSAVE3", 211, 0 }, 52 { "EXCSAVE4", 212, 0 }, 53 { "EPS2", 194, 0 }, 54 { "EPS3", 195, 0 }, 55 { "EPS4", 196, 0 }, 56 { "EXCCAUSE", 232, 0 }, 57 { "DEPC", 192, 0 }, 58 { "EXCVADDR", 238, 0 }, 59 { "WINDOWBASE", 72, 0 }, 60 { "WINDOWSTART", 73, 0 }, 61 { "SAR", 3, 0 }, 62 { "LITBASE", 5, 0 }, 63 { "PS", 230, 0 }, 64 { "MISC0", 244, 0 }, 65 { "MISC1", 245, 0 }, 66 { "INTENABLE", 228, 0 }, 67 { "DBREAKA0", 144, 0 }, 68 { "DBREAKC0", 160, 0 }, 69 { "DBREAKA1", 145, 0 }, 70 { "DBREAKC1", 161, 0 }, 71 { "IBREAKA0", 128, 0 }, 72 { "IBREAKA1", 129, 0 }, 73 { "IBREAKENABLE", 96, 0 }, 74 { "ICOUNTLEVEL", 237, 0 }, 75 { "DEBUGCAUSE", 233, 0 }, 76 { "RASID", 90, 0 }, 77 { "ITLBCFG", 91, 0 }, 78 { "DTLBCFG", 92, 0 } 79 }; 80 81 #define NUM_SYSREGS 49 82 #define MAX_SPECIAL_REG 245 83 #define MAX_USER_REG 0 84 85 86 /* Processor states. */ 88 89 static xtensa_state_internal states[] = { 90 { "LCOUNT", 32, 0 }, 91 { "PC", 32, 0 }, 92 { "ICOUNT", 32, 0 }, 93 { "DDR", 32, 0 }, 94 { "INTERRUPT", 17, 0 }, 95 { "CCOUNT", 32, 0 }, 96 { "XTSYNC", 1, 0 }, 97 { "EPC1", 32, 0 }, 98 { "EPC2", 32, 0 }, 99 { "EPC3", 32, 0 }, 100 { "EPC4", 32, 0 }, 101 { "EXCSAVE1", 32, 0 }, 102 { "EXCSAVE2", 32, 0 }, 103 { "EXCSAVE3", 32, 0 }, 104 { "EXCSAVE4", 32, 0 }, 105 { "EPS2", 15, 0 }, 106 { "EPS3", 15, 0 }, 107 { "EPS4", 15, 0 }, 108 { "EXCCAUSE", 6, 0 }, 109 { "PSINTLEVEL", 4, 0 }, 110 { "PSUM", 1, 0 }, 111 { "PSWOE", 1, 0 }, 112 { "PSRING", 2, 0 }, 113 { "PSEXCM", 1, 0 }, 114 { "DEPC", 32, 0 }, 115 { "EXCVADDR", 32, 0 }, 116 { "WindowBase", 4, 0 }, 117 { "WindowStart", 16, 0 }, 118 { "PSCALLINC", 2, 0 }, 119 { "PSOWB", 4, 0 }, 120 { "LBEG", 32, 0 }, 121 { "LEND", 32, 0 }, 122 { "SAR", 6, 0 }, 123 { "LITBADDR", 20, 0 }, 124 { "LITBEN", 1, 0 }, 125 { "MISC0", 32, 0 }, 126 { "MISC1", 32, 0 }, 127 { "InOCDMode", 1, 0 }, 128 { "INTENABLE", 17, 0 }, 129 { "DBREAKA0", 32, 0 }, 130 { "DBREAKC0", 8, 0 }, 131 { "DBREAKA1", 32, 0 }, 132 { "DBREAKC1", 8, 0 }, 133 { "IBREAKA0", 32, 0 }, 134 { "IBREAKA1", 32, 0 }, 135 { "IBREAKENABLE", 2, 0 }, 136 { "ICOUNTLEVEL", 4, 0 }, 137 { "DEBUGCAUSE", 6, 0 }, 138 { "DBNUM", 4, 0 }, 139 { "CCOMPARE0", 32, 0 }, 140 { "CCOMPARE1", 32, 0 }, 141 { "CCOMPARE2", 32, 0 }, 142 { "ASID3", 8, 0 }, 143 { "ASID2", 8, 0 }, 144 { "ASID1", 8, 0 }, 145 { "INSTPGSZID4", 2, 0 }, 146 { "DATAPGSZID4", 2, 0 }, 147 { "PTBASE", 10, 0 } 148 }; 149 150 #define NUM_STATES 58 151 152 /* Macros for xtensa_state numbers (for use in iclasses because the 153 state numbers are not available when the iclass table is generated). */ 154 155 #define STATE_LCOUNT 0 156 #define STATE_PC 1 157 #define STATE_ICOUNT 2 158 #define STATE_DDR 3 159 #define STATE_INTERRUPT 4 160 #define STATE_CCOUNT 5 161 #define STATE_XTSYNC 6 162 #define STATE_EPC1 7 163 #define STATE_EPC2 8 164 #define STATE_EPC3 9 165 #define STATE_EPC4 10 166 #define STATE_EXCSAVE1 11 167 #define STATE_EXCSAVE2 12 168 #define STATE_EXCSAVE3 13 169 #define STATE_EXCSAVE4 14 170 #define STATE_EPS2 15 171 #define STATE_EPS3 16 172 #define STATE_EPS4 17 173 #define STATE_EXCCAUSE 18 174 #define STATE_PSINTLEVEL 19 175 #define STATE_PSUM 20 176 #define STATE_PSWOE 21 177 #define STATE_PSRING 22 178 #define STATE_PSEXCM 23 179 #define STATE_DEPC 24 180 #define STATE_EXCVADDR 25 181 #define STATE_WindowBase 26 182 #define STATE_WindowStart 27 183 #define STATE_PSCALLINC 28 184 #define STATE_PSOWB 29 185 #define STATE_LBEG 30 186 #define STATE_LEND 31 187 #define STATE_SAR 32 188 #define STATE_LITBADDR 33 189 #define STATE_LITBEN 34 190 #define STATE_MISC0 35 191 #define STATE_MISC1 36 192 #define STATE_InOCDMode 37 193 #define STATE_INTENABLE 38 194 #define STATE_DBREAKA0 39 195 #define STATE_DBREAKC0 40 196 #define STATE_DBREAKA1 41 197 #define STATE_DBREAKC1 42 198 #define STATE_IBREAKA0 43 199 #define STATE_IBREAKA1 44 200 #define STATE_IBREAKENABLE 45 201 #define STATE_ICOUNTLEVEL 46 202 #define STATE_DEBUGCAUSE 47 203 #define STATE_DBNUM 48 204 #define STATE_CCOMPARE0 49 205 #define STATE_CCOMPARE1 50 206 #define STATE_CCOMPARE2 51 207 #define STATE_ASID3 52 208 #define STATE_ASID2 53 209 #define STATE_ASID1 54 210 #define STATE_INSTPGSZID4 55 211 #define STATE_DATAPGSZID4 56 212 #define STATE_PTBASE 57 213 214 215 /* Field definitions. */ 217 218 static unsigned 219 Field_t_Slot_inst_get (const xtensa_insnbuf insn) 220 { 221 unsigned tie_t = 0; 222 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); 223 return tie_t; 224 } 225 226 static void 227 Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 228 { 229 uint32 tie_t; 230 tie_t = (val << 28) >> 28; 231 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); 232 } 233 234 static unsigned 235 Field_s_Slot_inst_get (const xtensa_insnbuf insn) 236 { 237 unsigned tie_t = 0; 238 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 239 return tie_t; 240 } 241 242 static void 243 Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 244 { 245 uint32 tie_t; 246 tie_t = (val << 28) >> 28; 247 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 248 } 249 250 static unsigned 251 Field_r_Slot_inst_get (const xtensa_insnbuf insn) 252 { 253 unsigned tie_t = 0; 254 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 255 return tie_t; 256 } 257 258 static void 259 Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 260 { 261 uint32 tie_t; 262 tie_t = (val << 28) >> 28; 263 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 264 } 265 266 static unsigned 267 Field_op2_Slot_inst_get (const xtensa_insnbuf insn) 268 { 269 unsigned tie_t = 0; 270 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 271 return tie_t; 272 } 273 274 static void 275 Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 276 { 277 uint32 tie_t; 278 tie_t = (val << 28) >> 28; 279 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 280 } 281 282 static unsigned 283 Field_op1_Slot_inst_get (const xtensa_insnbuf insn) 284 { 285 unsigned tie_t = 0; 286 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 287 return tie_t; 288 } 289 290 static void 291 Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 292 { 293 uint32 tie_t; 294 tie_t = (val << 28) >> 28; 295 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 296 } 297 298 static unsigned 299 Field_op0_Slot_inst_get (const xtensa_insnbuf insn) 300 { 301 unsigned tie_t = 0; 302 tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); 303 return tie_t; 304 } 305 306 static void 307 Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 308 { 309 uint32 tie_t; 310 tie_t = (val << 28) >> 28; 311 insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); 312 } 313 314 static unsigned 315 Field_n_Slot_inst_get (const xtensa_insnbuf insn) 316 { 317 unsigned tie_t = 0; 318 tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); 319 return tie_t; 320 } 321 322 static void 323 Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 324 { 325 uint32 tie_t; 326 tie_t = (val << 30) >> 30; 327 insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); 328 } 329 330 static unsigned 331 Field_m_Slot_inst_get (const xtensa_insnbuf insn) 332 { 333 unsigned tie_t = 0; 334 tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); 335 return tie_t; 336 } 337 338 static void 339 Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 340 { 341 uint32 tie_t; 342 tie_t = (val << 30) >> 30; 343 insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); 344 } 345 346 static unsigned 347 Field_sr_Slot_inst_get (const xtensa_insnbuf insn) 348 { 349 unsigned tie_t = 0; 350 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 351 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 352 return tie_t; 353 } 354 355 static void 356 Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 357 { 358 uint32 tie_t; 359 tie_t = (val << 28) >> 28; 360 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 361 tie_t = (val << 24) >> 28; 362 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 363 } 364 365 static unsigned 366 Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) 367 { 368 unsigned tie_t = 0; 369 tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); 370 return tie_t; 371 } 372 373 static void 374 Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 375 { 376 uint32 tie_t; 377 tie_t = (val << 29) >> 29; 378 insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); 379 } 380 381 static unsigned 382 Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) 383 { 384 unsigned tie_t = 0; 385 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 386 return tie_t; 387 } 388 389 static void 390 Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 391 { 392 uint32 tie_t; 393 tie_t = (val << 28) >> 28; 394 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 395 } 396 397 static unsigned 398 Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) 399 { 400 unsigned tie_t = 0; 401 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 402 return tie_t; 403 } 404 405 static void 406 Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 407 { 408 uint32 tie_t; 409 tie_t = (val << 28) >> 28; 410 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 411 } 412 413 static unsigned 414 Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) 415 { 416 unsigned tie_t = 0; 417 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 418 return tie_t; 419 } 420 421 static void 422 Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 423 { 424 uint32 tie_t; 425 tie_t = (val << 28) >> 28; 426 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 427 } 428 429 static unsigned 430 Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) 431 { 432 unsigned tie_t = 0; 433 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 434 return tie_t; 435 } 436 437 static void 438 Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 439 { 440 uint32 tie_t; 441 tie_t = (val << 28) >> 28; 442 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 443 } 444 445 static unsigned 446 Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) 447 { 448 unsigned tie_t = 0; 449 tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); 450 return tie_t; 451 } 452 453 static void 454 Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 455 { 456 uint32 tie_t; 457 tie_t = (val << 31) >> 31; 458 insn[0] = (insn[0] & ~0x400) | (tie_t << 10); 459 } 460 461 static unsigned 462 Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) 463 { 464 unsigned tie_t = 0; 465 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); 466 return tie_t; 467 } 468 469 static void 470 Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 471 { 472 uint32 tie_t; 473 tie_t = (val << 31) >> 31; 474 insn[0] = (insn[0] & ~0x800) | (tie_t << 11); 475 } 476 477 static unsigned 478 Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) 479 { 480 unsigned tie_t = 0; 481 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 482 return tie_t; 483 } 484 485 static void 486 Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 487 { 488 uint32 tie_t; 489 tie_t = (val << 28) >> 28; 490 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 491 } 492 493 static unsigned 494 Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) 495 { 496 unsigned tie_t = 0; 497 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 498 return tie_t; 499 } 500 501 static void 502 Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 503 { 504 uint32 tie_t; 505 tie_t = (val << 28) >> 28; 506 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 507 } 508 509 static unsigned 510 Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) 511 { 512 unsigned tie_t = 0; 513 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); 514 return tie_t; 515 } 516 517 static void 518 Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 519 { 520 uint32 tie_t; 521 tie_t = (val << 31) >> 31; 522 insn[0] = (insn[0] & ~0x100) | (tie_t << 8); 523 } 524 525 static unsigned 526 Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) 527 { 528 unsigned tie_t = 0; 529 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); 530 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); 531 return tie_t; 532 } 533 534 static void 535 Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 536 { 537 uint32 tie_t; 538 tie_t = (val << 28) >> 28; 539 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); 540 tie_t = (val << 27) >> 31; 541 insn[0] = (insn[0] & ~0x100) | (tie_t << 8); 542 } 543 544 static unsigned 545 Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) 546 { 547 unsigned tie_t = 0; 548 tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20); 549 return tie_t; 550 } 551 552 static void 553 Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 554 { 555 uint32 tie_t; 556 tie_t = (val << 20) >> 20; 557 insn[0] = (insn[0] & ~0xfff) | (tie_t << 0); 558 } 559 560 static unsigned 561 Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) 562 { 563 unsigned tie_t = 0; 564 tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); 565 return tie_t; 566 } 567 568 static void 569 Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 570 { 571 uint32 tie_t; 572 tie_t = (val << 24) >> 24; 573 insn[0] = (insn[0] & ~0xff) | (tie_t << 0); 574 } 575 576 static unsigned 577 Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) 578 { 579 unsigned tie_t = 0; 580 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 581 return tie_t; 582 } 583 584 static void 585 Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 586 { 587 uint32 tie_t; 588 tie_t = (val << 28) >> 28; 589 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 590 } 591 592 static unsigned 593 Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) 594 { 595 unsigned tie_t = 0; 596 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 597 tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); 598 return tie_t; 599 } 600 601 static void 602 Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 603 { 604 uint32 tie_t; 605 tie_t = (val << 24) >> 24; 606 insn[0] = (insn[0] & ~0xff) | (tie_t << 0); 607 tie_t = (val << 20) >> 28; 608 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 609 } 610 611 static unsigned 612 Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) 613 { 614 unsigned tie_t = 0; 615 tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16); 616 return tie_t; 617 } 618 619 static void 620 Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 621 { 622 uint32 tie_t; 623 tie_t = (val << 16) >> 16; 624 insn[0] = (insn[0] & ~0xffff) | (tie_t << 0); 625 } 626 627 static unsigned 628 Field_offset_Slot_inst_get (const xtensa_insnbuf insn) 629 { 630 unsigned tie_t = 0; 631 tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); 632 return tie_t; 633 } 634 635 static void 636 Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 637 { 638 uint32 tie_t; 639 tie_t = (val << 14) >> 14; 640 insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); 641 } 642 643 static unsigned 644 Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) 645 { 646 unsigned tie_t = 0; 647 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 648 return tie_t; 649 } 650 651 static void 652 Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 653 { 654 uint32 tie_t; 655 tie_t = (val << 28) >> 28; 656 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 657 } 658 659 static unsigned 660 Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) 661 { 662 unsigned tie_t = 0; 663 tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); 664 return tie_t; 665 } 666 667 static void 668 Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 669 { 670 uint32 tie_t; 671 tie_t = (val << 31) >> 31; 672 insn[0] = (insn[0] & ~0x1) | (tie_t << 0); 673 } 674 675 static unsigned 676 Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) 677 { 678 unsigned tie_t = 0; 679 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); 680 return tie_t; 681 } 682 683 static void 684 Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 685 { 686 uint32 tie_t; 687 tie_t = (val << 31) >> 31; 688 insn[0] = (insn[0] & ~0x10) | (tie_t << 4); 689 } 690 691 static unsigned 692 Field_sae_Slot_inst_get (const xtensa_insnbuf insn) 693 { 694 unsigned tie_t = 0; 695 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); 696 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 697 return tie_t; 698 } 699 700 static void 701 Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 702 { 703 uint32 tie_t; 704 tie_t = (val << 28) >> 28; 705 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 706 tie_t = (val << 27) >> 31; 707 insn[0] = (insn[0] & ~0x10) | (tie_t << 4); 708 } 709 710 static unsigned 711 Field_sal_Slot_inst_get (const xtensa_insnbuf insn) 712 { 713 unsigned tie_t = 0; 714 tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); 715 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); 716 return tie_t; 717 } 718 719 static void 720 Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 721 { 722 uint32 tie_t; 723 tie_t = (val << 28) >> 28; 724 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); 725 tie_t = (val << 27) >> 31; 726 insn[0] = (insn[0] & ~0x1) | (tie_t << 0); 727 } 728 729 static unsigned 730 Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) 731 { 732 unsigned tie_t = 0; 733 tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); 734 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 735 return tie_t; 736 } 737 738 static void 739 Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 740 { 741 uint32 tie_t; 742 tie_t = (val << 28) >> 28; 743 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 744 tie_t = (val << 27) >> 31; 745 insn[0] = (insn[0] & ~0x1) | (tie_t << 0); 746 } 747 748 static unsigned 749 Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) 750 { 751 unsigned tie_t = 0; 752 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); 753 return tie_t; 754 } 755 756 static void 757 Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 758 { 759 uint32 tie_t; 760 tie_t = (val << 31) >> 31; 761 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); 762 } 763 764 static unsigned 765 Field_sas_Slot_inst_get (const xtensa_insnbuf insn) 766 { 767 unsigned tie_t = 0; 768 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); 769 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 770 return tie_t; 771 } 772 773 static void 774 Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 775 { 776 uint32 tie_t; 777 tie_t = (val << 28) >> 28; 778 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 779 tie_t = (val << 27) >> 31; 780 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); 781 } 782 783 static unsigned 784 Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) 785 { 786 unsigned tie_t = 0; 787 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 788 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 789 return tie_t; 790 } 791 792 static void 793 Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 794 { 795 uint32 tie_t; 796 tie_t = (val << 28) >> 28; 797 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 798 tie_t = (val << 24) >> 28; 799 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 800 } 801 802 static unsigned 803 Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) 804 { 805 unsigned tie_t = 0; 806 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 807 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 808 return tie_t; 809 } 810 811 static void 812 Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 813 { 814 uint32 tie_t; 815 tie_t = (val << 28) >> 28; 816 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 817 tie_t = (val << 24) >> 28; 818 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 819 } 820 821 static unsigned 822 Field_st_Slot_inst_get (const xtensa_insnbuf insn) 823 { 824 unsigned tie_t = 0; 825 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 826 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); 827 return tie_t; 828 } 829 830 static void 831 Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 832 { 833 uint32 tie_t; 834 tie_t = (val << 28) >> 28; 835 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); 836 tie_t = (val << 24) >> 28; 837 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 838 } 839 840 static unsigned 841 Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) 842 { 843 unsigned tie_t = 0; 844 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 845 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 846 return tie_t; 847 } 848 849 static void 850 Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 851 { 852 uint32 tie_t; 853 tie_t = (val << 28) >> 28; 854 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 855 tie_t = (val << 24) >> 28; 856 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 857 } 858 859 static unsigned 860 Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) 861 { 862 unsigned tie_t = 0; 863 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 864 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 865 return tie_t; 866 } 867 868 static void 869 Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 870 { 871 uint32 tie_t; 872 tie_t = (val << 28) >> 28; 873 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 874 tie_t = (val << 24) >> 28; 875 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 876 } 877 878 static unsigned 879 Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) 880 { 881 unsigned tie_t = 0; 882 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 883 return tie_t; 884 } 885 886 static void 887 Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 888 { 889 uint32 tie_t; 890 tie_t = (val << 28) >> 28; 891 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 892 } 893 894 static unsigned 895 Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) 896 { 897 unsigned tie_t = 0; 898 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 899 return tie_t; 900 } 901 902 static void 903 Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 904 { 905 uint32 tie_t; 906 tie_t = (val << 28) >> 28; 907 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 908 } 909 910 static unsigned 911 Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) 912 { 913 unsigned tie_t = 0; 914 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 915 return tie_t; 916 } 917 918 static void 919 Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 920 { 921 uint32 tie_t; 922 tie_t = (val << 28) >> 28; 923 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 924 } 925 926 static unsigned 927 Field_mn_Slot_inst_get (const xtensa_insnbuf insn) 928 { 929 unsigned tie_t = 0; 930 tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); 931 tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); 932 return tie_t; 933 } 934 935 static void 936 Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 937 { 938 uint32 tie_t; 939 tie_t = (val << 30) >> 30; 940 insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); 941 tie_t = (val << 28) >> 30; 942 insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); 943 } 944 945 static unsigned 946 Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) 947 { 948 unsigned tie_t = 0; 949 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); 950 return tie_t; 951 } 952 953 static void 954 Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 955 { 956 uint32 tie_t; 957 tie_t = (val << 31) >> 31; 958 insn[0] = (insn[0] & ~0x800) | (tie_t << 11); 959 } 960 961 static unsigned 962 Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) 963 { 964 unsigned tie_t = 0; 965 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 966 return tie_t; 967 } 968 969 static void 970 Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 971 { 972 uint32 tie_t; 973 tie_t = (val << 28) >> 28; 974 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 975 } 976 977 static unsigned 978 Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) 979 { 980 unsigned tie_t = 0; 981 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 982 return tie_t; 983 } 984 985 static void 986 Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 987 { 988 uint32 tie_t; 989 tie_t = (val << 28) >> 28; 990 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 991 } 992 993 static unsigned 994 Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) 995 { 996 unsigned tie_t = 0; 997 tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); 998 return tie_t; 999 } 1000 1001 static void 1002 Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1003 { 1004 uint32 tie_t; 1005 tie_t = (val << 30) >> 30; 1006 insn[0] = (insn[0] & ~0x300) | (tie_t << 8); 1007 } 1008 1009 static unsigned 1010 Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) 1011 { 1012 unsigned tie_t = 0; 1013 tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); 1014 return tie_t; 1015 } 1016 1017 static void 1018 Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1019 { 1020 uint32 tie_t; 1021 tie_t = (val << 30) >> 30; 1022 insn[0] = (insn[0] & ~0x300) | (tie_t << 8); 1023 } 1024 1025 static unsigned 1026 Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) 1027 { 1028 unsigned tie_t = 0; 1029 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 1030 return tie_t; 1031 } 1032 1033 static void 1034 Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1035 { 1036 uint32 tie_t; 1037 tie_t = (val << 28) >> 28; 1038 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 1039 } 1040 1041 static unsigned 1042 Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) 1043 { 1044 unsigned tie_t = 0; 1045 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 1046 return tie_t; 1047 } 1048 1049 static void 1050 Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1051 { 1052 uint32 tie_t; 1053 tie_t = (val << 28) >> 28; 1054 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 1055 } 1056 1057 static unsigned 1058 Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) 1059 { 1060 unsigned tie_t = 0; 1061 tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); 1062 return tie_t; 1063 } 1064 1065 static void 1066 Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1067 { 1068 uint32 tie_t; 1069 tie_t = (val << 29) >> 29; 1070 insn[0] = (insn[0] & ~0x700) | (tie_t << 8); 1071 } 1072 1073 static unsigned 1074 Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) 1075 { 1076 unsigned tie_t = 0; 1077 tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); 1078 return tie_t; 1079 } 1080 1081 static void 1082 Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1083 { 1084 uint32 tie_t; 1085 tie_t = (val << 29) >> 29; 1086 insn[0] = (insn[0] & ~0x700) | (tie_t << 8); 1087 } 1088 1089 static unsigned 1090 Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) 1091 { 1092 unsigned tie_t = 0; 1093 tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); 1094 return tie_t; 1095 } 1096 1097 static void 1098 Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1099 { 1100 uint32 tie_t; 1101 tie_t = (val << 31) >> 31; 1102 insn[0] = (insn[0] & ~0x400) | (tie_t << 10); 1103 } 1104 1105 static unsigned 1106 Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) 1107 { 1108 unsigned tie_t = 0; 1109 tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); 1110 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 1111 return tie_t; 1112 } 1113 1114 static void 1115 Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1116 { 1117 uint32 tie_t; 1118 tie_t = (val << 28) >> 28; 1119 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 1120 tie_t = (val << 26) >> 30; 1121 insn[0] = (insn[0] & ~0x300) | (tie_t << 8); 1122 } 1123 1124 static unsigned 1125 Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) 1126 { 1127 unsigned tie_t = 0; 1128 tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); 1129 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 1130 return tie_t; 1131 } 1132 1133 static void 1134 Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1135 { 1136 uint32 tie_t; 1137 tie_t = (val << 28) >> 28; 1138 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 1139 tie_t = (val << 26) >> 30; 1140 insn[0] = (insn[0] & ~0x300) | (tie_t << 8); 1141 } 1142 1143 static unsigned 1144 Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) 1145 { 1146 unsigned tie_t = 0; 1147 tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); 1148 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 1149 return tie_t; 1150 } 1151 1152 static void 1153 Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1154 { 1155 uint32 tie_t; 1156 tie_t = (val << 28) >> 28; 1157 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 1158 tie_t = (val << 25) >> 29; 1159 insn[0] = (insn[0] & ~0x700) | (tie_t << 8); 1160 } 1161 1162 static unsigned 1163 Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) 1164 { 1165 unsigned tie_t = 0; 1166 tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); 1167 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 1168 return tie_t; 1169 } 1170 1171 static void 1172 Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1173 { 1174 uint32 tie_t; 1175 tie_t = (val << 28) >> 28; 1176 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 1177 tie_t = (val << 25) >> 29; 1178 insn[0] = (insn[0] & ~0x700) | (tie_t << 8); 1179 } 1180 1181 static void 1182 Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, 1183 uint32 val ATTRIBUTE_UNUSED) 1184 { 1185 /* Do nothing. */ 1186 } 1187 1188 static unsigned 1189 Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 1190 { 1191 return 0; 1192 } 1193 1194 static unsigned 1195 Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 1196 { 1197 return 4; 1198 } 1199 1200 static unsigned 1201 Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 1202 { 1203 return 8; 1204 } 1205 1206 static unsigned 1207 Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 1208 { 1209 return 12; 1210 } 1211 1212 1213 /* Functional units. */ 1215 1216 static xtensa_funcUnit_internal funcUnits[] = { 1217 1218 }; 1219 1220 1221 /* Register files. */ 1223 1224 static xtensa_regfile_internal regfiles[] = { 1225 { "AR", "a", 0, 32, 64 } 1226 }; 1227 1228 1229 /* Interfaces. */ 1231 1232 static xtensa_interface_internal interfaces[] = { 1233 1234 }; 1235 1236 1237 /* Constant tables. */ 1239 1240 /* constant table ai4c */ 1241 static const unsigned CONST_TBL_ai4c_0[] = { 1242 0xffffffff, 1243 0x1, 1244 0x2, 1245 0x3, 1246 0x4, 1247 0x5, 1248 0x6, 1249 0x7, 1250 0x8, 1251 0x9, 1252 0xa, 1253 0xb, 1254 0xc, 1255 0xd, 1256 0xe, 1257 0xf, 1258 0 1259 }; 1260 1261 /* constant table b4c */ 1262 static const unsigned CONST_TBL_b4c_0[] = { 1263 0xffffffff, 1264 0x1, 1265 0x2, 1266 0x3, 1267 0x4, 1268 0x5, 1269 0x6, 1270 0x7, 1271 0x8, 1272 0xa, 1273 0xc, 1274 0x10, 1275 0x20, 1276 0x40, 1277 0x80, 1278 0x100, 1279 0 1280 }; 1281 1282 /* constant table b4cu */ 1283 static const unsigned CONST_TBL_b4cu_0[] = { 1284 0x8000, 1285 0x10000, 1286 0x2, 1287 0x3, 1288 0x4, 1289 0x5, 1290 0x6, 1291 0x7, 1292 0x8, 1293 0xa, 1294 0xc, 1295 0x10, 1296 0x20, 1297 0x40, 1298 0x80, 1299 0x100, 1300 0 1301 }; 1302 1303 1304 /* Instruction operands. */ 1306 1307 static int 1308 Operand_soffsetx4_decode (uint32 *valp) 1309 { 1310 unsigned soffsetx4_0, offset_0; 1311 offset_0 = *valp & 0x3ffff; 1312 soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2); 1313 *valp = soffsetx4_0; 1314 return 0; 1315 } 1316 1317 static int 1318 Operand_soffsetx4_encode (uint32 *valp) 1319 { 1320 unsigned offset_0, soffsetx4_0; 1321 soffsetx4_0 = *valp; 1322 offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff; 1323 *valp = offset_0; 1324 return 0; 1325 } 1326 1327 static int 1328 Operand_soffsetx4_ator (uint32 *valp, uint32 pc) 1329 { 1330 *valp -= (pc & ~0x3); 1331 return 0; 1332 } 1333 1334 static int 1335 Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) 1336 { 1337 *valp += (pc & ~0x3); 1338 return 0; 1339 } 1340 1341 static int 1342 Operand_uimm12x8_decode (uint32 *valp) 1343 { 1344 unsigned uimm12x8_0, imm12_0; 1345 imm12_0 = *valp & 0xfff; 1346 uimm12x8_0 = imm12_0 << 3; 1347 *valp = uimm12x8_0; 1348 return 0; 1349 } 1350 1351 static int 1352 Operand_uimm12x8_encode (uint32 *valp) 1353 { 1354 unsigned imm12_0, uimm12x8_0; 1355 uimm12x8_0 = *valp; 1356 imm12_0 = ((uimm12x8_0 >> 3) & 0xfff); 1357 *valp = imm12_0; 1358 return 0; 1359 } 1360 1361 static int 1362 Operand_simm4_decode (uint32 *valp) 1363 { 1364 unsigned simm4_0, mn_0; 1365 mn_0 = *valp & 0xf; 1366 simm4_0 = ((int) mn_0 << 28) >> 28; 1367 *valp = simm4_0; 1368 return 0; 1369 } 1370 1371 static int 1372 Operand_simm4_encode (uint32 *valp) 1373 { 1374 unsigned mn_0, simm4_0; 1375 simm4_0 = *valp; 1376 mn_0 = (simm4_0 & 0xf); 1377 *valp = mn_0; 1378 return 0; 1379 } 1380 1381 static int 1382 Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED) 1383 { 1384 return 0; 1385 } 1386 1387 static int 1388 Operand_arr_encode (uint32 *valp) 1389 { 1390 int error; 1391 error = (*valp & ~0xf) != 0; 1392 return error; 1393 } 1394 1395 static int 1396 Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED) 1397 { 1398 return 0; 1399 } 1400 1401 static int 1402 Operand_ars_encode (uint32 *valp) 1403 { 1404 int error; 1405 error = (*valp & ~0xf) != 0; 1406 return error; 1407 } 1408 1409 static int 1410 Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED) 1411 { 1412 return 0; 1413 } 1414 1415 static int 1416 Operand_art_encode (uint32 *valp) 1417 { 1418 int error; 1419 error = (*valp & ~0xf) != 0; 1420 return error; 1421 } 1422 1423 static int 1424 Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED) 1425 { 1426 return 0; 1427 } 1428 1429 static int 1430 Operand_ar0_encode (uint32 *valp) 1431 { 1432 int error; 1433 error = (*valp & ~0x3f) != 0; 1434 return error; 1435 } 1436 1437 static int 1438 Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED) 1439 { 1440 return 0; 1441 } 1442 1443 static int 1444 Operand_ar4_encode (uint32 *valp) 1445 { 1446 int error; 1447 error = (*valp & ~0x3f) != 0; 1448 return error; 1449 } 1450 1451 static int 1452 Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED) 1453 { 1454 return 0; 1455 } 1456 1457 static int 1458 Operand_ar8_encode (uint32 *valp) 1459 { 1460 int error; 1461 error = (*valp & ~0x3f) != 0; 1462 return error; 1463 } 1464 1465 static int 1466 Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED) 1467 { 1468 return 0; 1469 } 1470 1471 static int 1472 Operand_ar12_encode (uint32 *valp) 1473 { 1474 int error; 1475 error = (*valp & ~0x3f) != 0; 1476 return error; 1477 } 1478 1479 static int 1480 Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) 1481 { 1482 return 0; 1483 } 1484 1485 static int 1486 Operand_ars_entry_encode (uint32 *valp) 1487 { 1488 int error; 1489 error = (*valp & ~0x3f) != 0; 1490 return error; 1491 } 1492 1493 static int 1494 Operand_immrx4_decode (uint32 *valp) 1495 { 1496 unsigned immrx4_0, r_0; 1497 r_0 = *valp & 0xf; 1498 immrx4_0 = ((((0xfffffff)) << 4) | r_0) << 2; 1499 *valp = immrx4_0; 1500 return 0; 1501 } 1502 1503 static int 1504 Operand_immrx4_encode (uint32 *valp) 1505 { 1506 unsigned r_0, immrx4_0; 1507 immrx4_0 = *valp; 1508 r_0 = ((immrx4_0 >> 2) & 0xf); 1509 *valp = r_0; 1510 return 0; 1511 } 1512 1513 static int 1514 Operand_lsi4x4_decode (uint32 *valp) 1515 { 1516 unsigned lsi4x4_0, r_0; 1517 r_0 = *valp & 0xf; 1518 lsi4x4_0 = r_0 << 2; 1519 *valp = lsi4x4_0; 1520 return 0; 1521 } 1522 1523 static int 1524 Operand_lsi4x4_encode (uint32 *valp) 1525 { 1526 unsigned r_0, lsi4x4_0; 1527 lsi4x4_0 = *valp; 1528 r_0 = ((lsi4x4_0 >> 2) & 0xf); 1529 *valp = r_0; 1530 return 0; 1531 } 1532 1533 static int 1534 Operand_simm7_decode (uint32 *valp) 1535 { 1536 unsigned simm7_0, imm7_0; 1537 imm7_0 = *valp & 0x7f; 1538 simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0; 1539 *valp = simm7_0; 1540 return 0; 1541 } 1542 1543 static int 1544 Operand_simm7_encode (uint32 *valp) 1545 { 1546 unsigned imm7_0, simm7_0; 1547 simm7_0 = *valp; 1548 imm7_0 = (simm7_0 & 0x7f); 1549 *valp = imm7_0; 1550 return 0; 1551 } 1552 1553 static int 1554 Operand_uimm6_decode (uint32 *valp) 1555 { 1556 unsigned uimm6_0, imm6_0; 1557 imm6_0 = *valp & 0x3f; 1558 uimm6_0 = 0x4 + ((((0)) << 6) | imm6_0); 1559 *valp = uimm6_0; 1560 return 0; 1561 } 1562 1563 static int 1564 Operand_uimm6_encode (uint32 *valp) 1565 { 1566 unsigned imm6_0, uimm6_0; 1567 uimm6_0 = *valp; 1568 imm6_0 = (uimm6_0 - 0x4) & 0x3f; 1569 *valp = imm6_0; 1570 return 0; 1571 } 1572 1573 static int 1574 Operand_uimm6_ator (uint32 *valp, uint32 pc) 1575 { 1576 *valp -= pc; 1577 return 0; 1578 } 1579 1580 static int 1581 Operand_uimm6_rtoa (uint32 *valp, uint32 pc) 1582 { 1583 *valp += pc; 1584 return 0; 1585 } 1586 1587 static int 1588 Operand_ai4const_decode (uint32 *valp) 1589 { 1590 unsigned ai4const_0, t_0; 1591 t_0 = *valp & 0xf; 1592 ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf]; 1593 *valp = ai4const_0; 1594 return 0; 1595 } 1596 1597 static int 1598 Operand_ai4const_encode (uint32 *valp) 1599 { 1600 unsigned t_0, ai4const_0; 1601 ai4const_0 = *valp; 1602 switch (ai4const_0) 1603 { 1604 case 0xffffffff: t_0 = 0; break; 1605 case 0x1: t_0 = 0x1; break; 1606 case 0x2: t_0 = 0x2; break; 1607 case 0x3: t_0 = 0x3; break; 1608 case 0x4: t_0 = 0x4; break; 1609 case 0x5: t_0 = 0x5; break; 1610 case 0x6: t_0 = 0x6; break; 1611 case 0x7: t_0 = 0x7; break; 1612 case 0x8: t_0 = 0x8; break; 1613 case 0x9: t_0 = 0x9; break; 1614 case 0xa: t_0 = 0xa; break; 1615 case 0xb: t_0 = 0xb; break; 1616 case 0xc: t_0 = 0xc; break; 1617 case 0xd: t_0 = 0xd; break; 1618 case 0xe: t_0 = 0xe; break; 1619 default: t_0 = 0xf; break; 1620 } 1621 *valp = t_0; 1622 return 0; 1623 } 1624 1625 static int 1626 Operand_b4const_decode (uint32 *valp) 1627 { 1628 unsigned b4const_0, r_0; 1629 r_0 = *valp & 0xf; 1630 b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf]; 1631 *valp = b4const_0; 1632 return 0; 1633 } 1634 1635 static int 1636 Operand_b4const_encode (uint32 *valp) 1637 { 1638 unsigned r_0, b4const_0; 1639 b4const_0 = *valp; 1640 switch (b4const_0) 1641 { 1642 case 0xffffffff: r_0 = 0; break; 1643 case 0x1: r_0 = 0x1; break; 1644 case 0x2: r_0 = 0x2; break; 1645 case 0x3: r_0 = 0x3; break; 1646 case 0x4: r_0 = 0x4; break; 1647 case 0x5: r_0 = 0x5; break; 1648 case 0x6: r_0 = 0x6; break; 1649 case 0x7: r_0 = 0x7; break; 1650 case 0x8: r_0 = 0x8; break; 1651 case 0xa: r_0 = 0x9; break; 1652 case 0xc: r_0 = 0xa; break; 1653 case 0x10: r_0 = 0xb; break; 1654 case 0x20: r_0 = 0xc; break; 1655 case 0x40: r_0 = 0xd; break; 1656 case 0x80: r_0 = 0xe; break; 1657 default: r_0 = 0xf; break; 1658 } 1659 *valp = r_0; 1660 return 0; 1661 } 1662 1663 static int 1664 Operand_b4constu_decode (uint32 *valp) 1665 { 1666 unsigned b4constu_0, r_0; 1667 r_0 = *valp & 0xf; 1668 b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf]; 1669 *valp = b4constu_0; 1670 return 0; 1671 } 1672 1673 static int 1674 Operand_b4constu_encode (uint32 *valp) 1675 { 1676 unsigned r_0, b4constu_0; 1677 b4constu_0 = *valp; 1678 switch (b4constu_0) 1679 { 1680 case 0x8000: r_0 = 0; break; 1681 case 0x10000: r_0 = 0x1; break; 1682 case 0x2: r_0 = 0x2; break; 1683 case 0x3: r_0 = 0x3; break; 1684 case 0x4: r_0 = 0x4; break; 1685 case 0x5: r_0 = 0x5; break; 1686 case 0x6: r_0 = 0x6; break; 1687 case 0x7: r_0 = 0x7; break; 1688 case 0x8: r_0 = 0x8; break; 1689 case 0xa: r_0 = 0x9; break; 1690 case 0xc: r_0 = 0xa; break; 1691 case 0x10: r_0 = 0xb; break; 1692 case 0x20: r_0 = 0xc; break; 1693 case 0x40: r_0 = 0xd; break; 1694 case 0x80: r_0 = 0xe; break; 1695 default: r_0 = 0xf; break; 1696 } 1697 *valp = r_0; 1698 return 0; 1699 } 1700 1701 static int 1702 Operand_uimm8_decode (uint32 *valp) 1703 { 1704 unsigned uimm8_0, imm8_0; 1705 imm8_0 = *valp & 0xff; 1706 uimm8_0 = imm8_0; 1707 *valp = uimm8_0; 1708 return 0; 1709 } 1710 1711 static int 1712 Operand_uimm8_encode (uint32 *valp) 1713 { 1714 unsigned imm8_0, uimm8_0; 1715 uimm8_0 = *valp; 1716 imm8_0 = (uimm8_0 & 0xff); 1717 *valp = imm8_0; 1718 return 0; 1719 } 1720 1721 static int 1722 Operand_uimm8x2_decode (uint32 *valp) 1723 { 1724 unsigned uimm8x2_0, imm8_0; 1725 imm8_0 = *valp & 0xff; 1726 uimm8x2_0 = imm8_0 << 1; 1727 *valp = uimm8x2_0; 1728 return 0; 1729 } 1730 1731 static int 1732 Operand_uimm8x2_encode (uint32 *valp) 1733 { 1734 unsigned imm8_0, uimm8x2_0; 1735 uimm8x2_0 = *valp; 1736 imm8_0 = ((uimm8x2_0 >> 1) & 0xff); 1737 *valp = imm8_0; 1738 return 0; 1739 } 1740 1741 static int 1742 Operand_uimm8x4_decode (uint32 *valp) 1743 { 1744 unsigned uimm8x4_0, imm8_0; 1745 imm8_0 = *valp & 0xff; 1746 uimm8x4_0 = imm8_0 << 2; 1747 *valp = uimm8x4_0; 1748 return 0; 1749 } 1750 1751 static int 1752 Operand_uimm8x4_encode (uint32 *valp) 1753 { 1754 unsigned imm8_0, uimm8x4_0; 1755 uimm8x4_0 = *valp; 1756 imm8_0 = ((uimm8x4_0 >> 2) & 0xff); 1757 *valp = imm8_0; 1758 return 0; 1759 } 1760 1761 static int 1762 Operand_uimm4x16_decode (uint32 *valp) 1763 { 1764 unsigned uimm4x16_0, op2_0; 1765 op2_0 = *valp & 0xf; 1766 uimm4x16_0 = op2_0 << 4; 1767 *valp = uimm4x16_0; 1768 return 0; 1769 } 1770 1771 static int 1772 Operand_uimm4x16_encode (uint32 *valp) 1773 { 1774 unsigned op2_0, uimm4x16_0; 1775 uimm4x16_0 = *valp; 1776 op2_0 = ((uimm4x16_0 >> 4) & 0xf); 1777 *valp = op2_0; 1778 return 0; 1779 } 1780 1781 static int 1782 Operand_simm8_decode (uint32 *valp) 1783 { 1784 unsigned simm8_0, imm8_0; 1785 imm8_0 = *valp & 0xff; 1786 simm8_0 = ((int) imm8_0 << 24) >> 24; 1787 *valp = simm8_0; 1788 return 0; 1789 } 1790 1791 static int 1792 Operand_simm8_encode (uint32 *valp) 1793 { 1794 unsigned imm8_0, simm8_0; 1795 simm8_0 = *valp; 1796 imm8_0 = (simm8_0 & 0xff); 1797 *valp = imm8_0; 1798 return 0; 1799 } 1800 1801 static int 1802 Operand_simm8x256_decode (uint32 *valp) 1803 { 1804 unsigned simm8x256_0, imm8_0; 1805 imm8_0 = *valp & 0xff; 1806 simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8; 1807 *valp = simm8x256_0; 1808 return 0; 1809 } 1810 1811 static int 1812 Operand_simm8x256_encode (uint32 *valp) 1813 { 1814 unsigned imm8_0, simm8x256_0; 1815 simm8x256_0 = *valp; 1816 imm8_0 = ((simm8x256_0 >> 8) & 0xff); 1817 *valp = imm8_0; 1818 return 0; 1819 } 1820 1821 static int 1822 Operand_simm12b_decode (uint32 *valp) 1823 { 1824 unsigned simm12b_0, imm12b_0; 1825 imm12b_0 = *valp & 0xfff; 1826 simm12b_0 = ((int) imm12b_0 << 20) >> 20; 1827 *valp = simm12b_0; 1828 return 0; 1829 } 1830 1831 static int 1832 Operand_simm12b_encode (uint32 *valp) 1833 { 1834 unsigned imm12b_0, simm12b_0; 1835 simm12b_0 = *valp; 1836 imm12b_0 = (simm12b_0 & 0xfff); 1837 *valp = imm12b_0; 1838 return 0; 1839 } 1840 1841 static int 1842 Operand_msalp32_decode (uint32 *valp) 1843 { 1844 unsigned msalp32_0, sal_0; 1845 sal_0 = *valp & 0x1f; 1846 msalp32_0 = 0x20 - sal_0; 1847 *valp = msalp32_0; 1848 return 0; 1849 } 1850 1851 static int 1852 Operand_msalp32_encode (uint32 *valp) 1853 { 1854 unsigned sal_0, msalp32_0; 1855 msalp32_0 = *valp; 1856 sal_0 = (0x20 - msalp32_0) & 0x1f; 1857 *valp = sal_0; 1858 return 0; 1859 } 1860 1861 static int 1862 Operand_op2p1_decode (uint32 *valp) 1863 { 1864 unsigned op2p1_0, op2_0; 1865 op2_0 = *valp & 0xf; 1866 op2p1_0 = op2_0 + 0x1; 1867 *valp = op2p1_0; 1868 return 0; 1869 } 1870 1871 static int 1872 Operand_op2p1_encode (uint32 *valp) 1873 { 1874 unsigned op2_0, op2p1_0; 1875 op2p1_0 = *valp; 1876 op2_0 = (op2p1_0 - 0x1) & 0xf; 1877 *valp = op2_0; 1878 return 0; 1879 } 1880 1881 static int 1882 Operand_label8_decode (uint32 *valp) 1883 { 1884 unsigned label8_0, imm8_0; 1885 imm8_0 = *valp & 0xff; 1886 label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24); 1887 *valp = label8_0; 1888 return 0; 1889 } 1890 1891 static int 1892 Operand_label8_encode (uint32 *valp) 1893 { 1894 unsigned imm8_0, label8_0; 1895 label8_0 = *valp; 1896 imm8_0 = (label8_0 - 0x4) & 0xff; 1897 *valp = imm8_0; 1898 return 0; 1899 } 1900 1901 static int 1902 Operand_label8_ator (uint32 *valp, uint32 pc) 1903 { 1904 *valp -= pc; 1905 return 0; 1906 } 1907 1908 static int 1909 Operand_label8_rtoa (uint32 *valp, uint32 pc) 1910 { 1911 *valp += pc; 1912 return 0; 1913 } 1914 1915 static int 1916 Operand_ulabel8_decode (uint32 *valp) 1917 { 1918 unsigned ulabel8_0, imm8_0; 1919 imm8_0 = *valp & 0xff; 1920 ulabel8_0 = 0x4 + ((((0)) << 8) | imm8_0); 1921 *valp = ulabel8_0; 1922 return 0; 1923 } 1924 1925 static int 1926 Operand_ulabel8_encode (uint32 *valp) 1927 { 1928 unsigned imm8_0, ulabel8_0; 1929 ulabel8_0 = *valp; 1930 imm8_0 = (ulabel8_0 - 0x4) & 0xff; 1931 *valp = imm8_0; 1932 return 0; 1933 } 1934 1935 static int 1936 Operand_ulabel8_ator (uint32 *valp, uint32 pc) 1937 { 1938 *valp -= pc; 1939 return 0; 1940 } 1941 1942 static int 1943 Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) 1944 { 1945 *valp += pc; 1946 return 0; 1947 } 1948 1949 static int 1950 Operand_label12_decode (uint32 *valp) 1951 { 1952 unsigned label12_0, imm12_0; 1953 imm12_0 = *valp & 0xfff; 1954 label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20); 1955 *valp = label12_0; 1956 return 0; 1957 } 1958 1959 static int 1960 Operand_label12_encode (uint32 *valp) 1961 { 1962 unsigned imm12_0, label12_0; 1963 label12_0 = *valp; 1964 imm12_0 = (label12_0 - 0x4) & 0xfff; 1965 *valp = imm12_0; 1966 return 0; 1967 } 1968 1969 static int 1970 Operand_label12_ator (uint32 *valp, uint32 pc) 1971 { 1972 *valp -= pc; 1973 return 0; 1974 } 1975 1976 static int 1977 Operand_label12_rtoa (uint32 *valp, uint32 pc) 1978 { 1979 *valp += pc; 1980 return 0; 1981 } 1982 1983 static int 1984 Operand_soffset_decode (uint32 *valp) 1985 { 1986 unsigned soffset_0, offset_0; 1987 offset_0 = *valp & 0x3ffff; 1988 soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14); 1989 *valp = soffset_0; 1990 return 0; 1991 } 1992 1993 static int 1994 Operand_soffset_encode (uint32 *valp) 1995 { 1996 unsigned offset_0, soffset_0; 1997 soffset_0 = *valp; 1998 offset_0 = (soffset_0 - 0x4) & 0x3ffff; 1999 *valp = offset_0; 2000 return 0; 2001 } 2002 2003 static int 2004 Operand_soffset_ator (uint32 *valp, uint32 pc) 2005 { 2006 *valp -= pc; 2007 return 0; 2008 } 2009 2010 static int 2011 Operand_soffset_rtoa (uint32 *valp, uint32 pc) 2012 { 2013 *valp += pc; 2014 return 0; 2015 } 2016 2017 static int 2018 Operand_uimm16x4_decode (uint32 *valp) 2019 { 2020 unsigned uimm16x4_0, imm16_0; 2021 imm16_0 = *valp & 0xffff; 2022 uimm16x4_0 = ((((0xffff)) << 16) | imm16_0) << 2; 2023 *valp = uimm16x4_0; 2024 return 0; 2025 } 2026 2027 static int 2028 Operand_uimm16x4_encode (uint32 *valp) 2029 { 2030 unsigned imm16_0, uimm16x4_0; 2031 uimm16x4_0 = *valp; 2032 imm16_0 = (uimm16x4_0 >> 2) & 0xffff; 2033 *valp = imm16_0; 2034 return 0; 2035 } 2036 2037 static int 2038 Operand_uimm16x4_ator (uint32 *valp, uint32 pc) 2039 { 2040 *valp -= ((pc + 3) & ~0x3); 2041 return 0; 2042 } 2043 2044 static int 2045 Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) 2046 { 2047 *valp += ((pc + 3) & ~0x3); 2048 return 0; 2049 } 2050 2051 static int 2052 Operand_immt_decode (uint32 *valp) 2053 { 2054 unsigned immt_0, t_0; 2055 t_0 = *valp & 0xf; 2056 immt_0 = t_0; 2057 *valp = immt_0; 2058 return 0; 2059 } 2060 2061 static int 2062 Operand_immt_encode (uint32 *valp) 2063 { 2064 unsigned t_0, immt_0; 2065 immt_0 = *valp; 2066 t_0 = immt_0 & 0xf; 2067 *valp = t_0; 2068 return 0; 2069 } 2070 2071 static int 2072 Operand_imms_decode (uint32 *valp) 2073 { 2074 unsigned imms_0, s_0; 2075 s_0 = *valp & 0xf; 2076 imms_0 = s_0; 2077 *valp = imms_0; 2078 return 0; 2079 } 2080 2081 static int 2082 Operand_imms_encode (uint32 *valp) 2083 { 2084 unsigned s_0, imms_0; 2085 imms_0 = *valp; 2086 s_0 = imms_0 & 0xf; 2087 *valp = s_0; 2088 return 0; 2089 } 2090 2091 static xtensa_operand_internal operands[] = { 2092 { "soffsetx4", 10, -1, 0, 2093 XTENSA_OPERAND_IS_PCRELATIVE, 2094 Operand_soffsetx4_encode, Operand_soffsetx4_decode, 2095 Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, 2096 { "uimm12x8", 3, -1, 0, 2097 0, 2098 Operand_uimm12x8_encode, Operand_uimm12x8_decode, 2099 0, 0 }, 2100 { "simm4", 26, -1, 0, 2101 0, 2102 Operand_simm4_encode, Operand_simm4_decode, 2103 0, 0 }, 2104 { "arr", 14, 0, 1, 2105 XTENSA_OPERAND_IS_REGISTER, 2106 Operand_arr_encode, Operand_arr_decode, 2107 0, 0 }, 2108 { "ars", 5, 0, 1, 2109 XTENSA_OPERAND_IS_REGISTER, 2110 Operand_ars_encode, Operand_ars_decode, 2111 0, 0 }, 2112 { "*ars_invisible", 5, 0, 1, 2113 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2114 Operand_ars_encode, Operand_ars_decode, 2115 0, 0 }, 2116 { "art", 0, 0, 1, 2117 XTENSA_OPERAND_IS_REGISTER, 2118 Operand_art_encode, Operand_art_decode, 2119 0, 0 }, 2120 { "ar0", 35, 0, 1, 2121 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2122 Operand_ar0_encode, Operand_ar0_decode, 2123 0, 0 }, 2124 { "ar4", 36, 0, 1, 2125 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2126 Operand_ar4_encode, Operand_ar4_decode, 2127 0, 0 }, 2128 { "ar8", 37, 0, 1, 2129 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2130 Operand_ar8_encode, Operand_ar8_decode, 2131 0, 0 }, 2132 { "ar12", 38, 0, 1, 2133 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2134 Operand_ar12_encode, Operand_ar12_decode, 2135 0, 0 }, 2136 { "ars_entry", 5, 0, 1, 2137 XTENSA_OPERAND_IS_REGISTER, 2138 Operand_ars_entry_encode, Operand_ars_entry_decode, 2139 0, 0 }, 2140 { "immrx4", 14, -1, 0, 2141 0, 2142 Operand_immrx4_encode, Operand_immrx4_decode, 2143 0, 0 }, 2144 { "lsi4x4", 14, -1, 0, 2145 0, 2146 Operand_lsi4x4_encode, Operand_lsi4x4_decode, 2147 0, 0 }, 2148 { "simm7", 34, -1, 0, 2149 0, 2150 Operand_simm7_encode, Operand_simm7_decode, 2151 0, 0 }, 2152 { "uimm6", 33, -1, 0, 2153 XTENSA_OPERAND_IS_PCRELATIVE, 2154 Operand_uimm6_encode, Operand_uimm6_decode, 2155 Operand_uimm6_ator, Operand_uimm6_rtoa }, 2156 { "ai4const", 0, -1, 0, 2157 0, 2158 Operand_ai4const_encode, Operand_ai4const_decode, 2159 0, 0 }, 2160 { "b4const", 14, -1, 0, 2161 0, 2162 Operand_b4const_encode, Operand_b4const_decode, 2163 0, 0 }, 2164 { "b4constu", 14, -1, 0, 2165 0, 2166 Operand_b4constu_encode, Operand_b4constu_decode, 2167 0, 0 }, 2168 { "uimm8", 4, -1, 0, 2169 0, 2170 Operand_uimm8_encode, Operand_uimm8_decode, 2171 0, 0 }, 2172 { "uimm8x2", 4, -1, 0, 2173 0, 2174 Operand_uimm8x2_encode, Operand_uimm8x2_decode, 2175 0, 0 }, 2176 { "uimm8x4", 4, -1, 0, 2177 0, 2178 Operand_uimm8x4_encode, Operand_uimm8x4_decode, 2179 0, 0 }, 2180 { "uimm4x16", 13, -1, 0, 2181 0, 2182 Operand_uimm4x16_encode, Operand_uimm4x16_decode, 2183 0, 0 }, 2184 { "simm8", 4, -1, 0, 2185 0, 2186 Operand_simm8_encode, Operand_simm8_decode, 2187 0, 0 }, 2188 { "simm8x256", 4, -1, 0, 2189 0, 2190 Operand_simm8x256_encode, Operand_simm8x256_decode, 2191 0, 0 }, 2192 { "simm12b", 6, -1, 0, 2193 0, 2194 Operand_simm12b_encode, Operand_simm12b_decode, 2195 0, 0 }, 2196 { "msalp32", 18, -1, 0, 2197 0, 2198 Operand_msalp32_encode, Operand_msalp32_decode, 2199 0, 0 }, 2200 { "op2p1", 13, -1, 0, 2201 0, 2202 Operand_op2p1_encode, Operand_op2p1_decode, 2203 0, 0 }, 2204 { "label8", 4, -1, 0, 2205 XTENSA_OPERAND_IS_PCRELATIVE, 2206 Operand_label8_encode, Operand_label8_decode, 2207 Operand_label8_ator, Operand_label8_rtoa }, 2208 { "ulabel8", 4, -1, 0, 2209 XTENSA_OPERAND_IS_PCRELATIVE, 2210 Operand_ulabel8_encode, Operand_ulabel8_decode, 2211 Operand_ulabel8_ator, Operand_ulabel8_rtoa }, 2212 { "label12", 3, -1, 0, 2213 XTENSA_OPERAND_IS_PCRELATIVE, 2214 Operand_label12_encode, Operand_label12_decode, 2215 Operand_label12_ator, Operand_label12_rtoa }, 2216 { "soffset", 10, -1, 0, 2217 XTENSA_OPERAND_IS_PCRELATIVE, 2218 Operand_soffset_encode, Operand_soffset_decode, 2219 Operand_soffset_ator, Operand_soffset_rtoa }, 2220 { "uimm16x4", 7, -1, 0, 2221 XTENSA_OPERAND_IS_PCRELATIVE, 2222 Operand_uimm16x4_encode, Operand_uimm16x4_decode, 2223 Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, 2224 { "immt", 0, -1, 0, 2225 0, 2226 Operand_immt_encode, Operand_immt_decode, 2227 0, 0 }, 2228 { "imms", 5, -1, 0, 2229 0, 2230 Operand_imms_encode, Operand_imms_decode, 2231 0, 0 }, 2232 { "t", 0, -1, 0, 0, 0, 0, 0, 0 }, 2233 { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 }, 2234 { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 }, 2235 { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 }, 2236 { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 }, 2237 { "s", 5, -1, 0, 0, 0, 0, 0, 0 }, 2238 { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 }, 2239 { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 }, 2240 { "m", 8, -1, 0, 0, 0, 0, 0, 0 }, 2241 { "n", 9, -1, 0, 0, 0, 0, 0, 0 }, 2242 { "offset", 10, -1, 0, 0, 0, 0, 0, 0 }, 2243 { "op0", 11, -1, 0, 0, 0, 0, 0, 0 }, 2244 { "op1", 12, -1, 0, 0, 0, 0, 0, 0 }, 2245 { "op2", 13, -1, 0, 0, 0, 0, 0, 0 }, 2246 { "r", 14, -1, 0, 0, 0, 0, 0, 0 }, 2247 { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 }, 2248 { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 }, 2249 { "sae", 17, -1, 0, 0, 0, 0, 0, 0 }, 2250 { "sal", 18, -1, 0, 0, 0, 0, 0, 0 }, 2251 { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 }, 2252 { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 }, 2253 { "sas", 21, -1, 0, 0, 0, 0, 0, 0 }, 2254 { "sr", 22, -1, 0, 0, 0, 0, 0, 0 }, 2255 { "st", 23, -1, 0, 0, 0, 0, 0, 0 }, 2256 { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 }, 2257 { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 }, 2258 { "mn", 26, -1, 0, 0, 0, 0, 0, 0 }, 2259 { "i", 27, -1, 0, 0, 0, 0, 0, 0 }, 2260 { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 }, 2261 { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 }, 2262 { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 }, 2263 { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 }, 2264 { "z", 32, -1, 0, 0, 0, 0, 0, 0 }, 2265 { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 }, 2266 { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 } 2267 }; 2268 2269 2270 /* Iclass table. */ 2272 2273 static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { 2274 { { STATE_PSRING }, 'i' }, 2275 { { STATE_PSEXCM }, 'm' }, 2276 { { STATE_EPC1 }, 'i' } 2277 }; 2278 2279 static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { 2280 { { STATE_PSEXCM }, 'i' }, 2281 { { STATE_PSRING }, 'i' }, 2282 { { STATE_DEPC }, 'i' } 2283 }; 2284 2285 static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { 2286 { { 0 /* soffsetx4 */ }, 'i' }, 2287 { { 10 /* ar12 */ }, 'o' } 2288 }; 2289 2290 static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { 2291 { { STATE_PSCALLINC }, 'o' } 2292 }; 2293 2294 static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { 2295 { { 0 /* soffsetx4 */ }, 'i' }, 2296 { { 9 /* ar8 */ }, 'o' } 2297 }; 2298 2299 static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { 2300 { { STATE_PSCALLINC }, 'o' } 2301 }; 2302 2303 static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { 2304 { { 0 /* soffsetx4 */ }, 'i' }, 2305 { { 8 /* ar4 */ }, 'o' } 2306 }; 2307 2308 static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { 2309 { { STATE_PSCALLINC }, 'o' } 2310 }; 2311 2312 static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { 2313 { { 4 /* ars */ }, 'i' }, 2314 { { 10 /* ar12 */ }, 'o' } 2315 }; 2316 2317 static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { 2318 { { STATE_PSCALLINC }, 'o' } 2319 }; 2320 2321 static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { 2322 { { 4 /* ars */ }, 'i' }, 2323 { { 9 /* ar8 */ }, 'o' } 2324 }; 2325 2326 static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { 2327 { { STATE_PSCALLINC }, 'o' } 2328 }; 2329 2330 static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { 2331 { { 4 /* ars */ }, 'i' }, 2332 { { 8 /* ar4 */ }, 'o' } 2333 }; 2334 2335 static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { 2336 { { STATE_PSCALLINC }, 'o' } 2337 }; 2338 2339 static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { 2340 { { 11 /* ars_entry */ }, 's' }, 2341 { { 4 /* ars */ }, 'i' }, 2342 { { 1 /* uimm12x8 */ }, 'i' } 2343 }; 2344 2345 static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { 2346 { { STATE_PSCALLINC }, 'i' }, 2347 { { STATE_PSEXCM }, 'i' }, 2348 { { STATE_PSWOE }, 'i' }, 2349 { { STATE_WindowBase }, 'm' }, 2350 { { STATE_WindowStart }, 'm' } 2351 }; 2352 2353 static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { 2354 { { 6 /* art */ }, 'o' }, 2355 { { 4 /* ars */ }, 'i' } 2356 }; 2357 2358 static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { 2359 { { STATE_WindowBase }, 'i' }, 2360 { { STATE_WindowStart }, 'i' } 2361 }; 2362 2363 static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { 2364 { { 2 /* simm4 */ }, 'i' } 2365 }; 2366 2367 static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { 2368 { { STATE_PSEXCM }, 'i' }, 2369 { { STATE_PSRING }, 'i' }, 2370 { { STATE_WindowBase }, 'm' } 2371 }; 2372 2373 static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { 2374 { { 5 /* *ars_invisible */ }, 'i' } 2375 }; 2376 2377 static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { 2378 { { STATE_WindowBase }, 'm' }, 2379 { { STATE_WindowStart }, 'm' }, 2380 { { STATE_PSEXCM }, 'i' }, 2381 { { STATE_PSWOE }, 'i' } 2382 }; 2383 2384 static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { 2385 { { STATE_EPC1 }, 'i' }, 2386 { { STATE_PSEXCM }, 'm' }, 2387 { { STATE_PSRING }, 'i' }, 2388 { { STATE_WindowBase }, 'm' }, 2389 { { STATE_WindowStart }, 'm' }, 2390 { { STATE_PSOWB }, 'i' } 2391 }; 2392 2393 static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { 2394 { { 6 /* art */ }, 'o' }, 2395 { { 4 /* ars */ }, 'i' }, 2396 { { 12 /* immrx4 */ }, 'i' } 2397 }; 2398 2399 static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { 2400 { { STATE_PSEXCM }, 'i' }, 2401 { { STATE_PSRING }, 'i' } 2402 }; 2403 2404 static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { 2405 { { 6 /* art */ }, 'i' }, 2406 { { 4 /* ars */ }, 'i' }, 2407 { { 12 /* immrx4 */ }, 'i' } 2408 }; 2409 2410 static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { 2411 { { STATE_PSEXCM }, 'i' }, 2412 { { STATE_PSRING }, 'i' } 2413 }; 2414 2415 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { 2416 { { 6 /* art */ }, 'o' } 2417 }; 2418 2419 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { 2420 { { STATE_PSEXCM }, 'i' }, 2421 { { STATE_PSRING }, 'i' }, 2422 { { STATE_WindowBase }, 'i' } 2423 }; 2424 2425 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { 2426 { { 6 /* art */ }, 'i' } 2427 }; 2428 2429 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { 2430 { { STATE_PSEXCM }, 'i' }, 2431 { { STATE_PSRING }, 'i' }, 2432 { { STATE_WindowBase }, 'o' } 2433 }; 2434 2435 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { 2436 { { 6 /* art */ }, 'm' } 2437 }; 2438 2439 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { 2440 { { STATE_PSEXCM }, 'i' }, 2441 { { STATE_PSRING }, 'i' }, 2442 { { STATE_WindowBase }, 'm' } 2443 }; 2444 2445 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { 2446 { { 6 /* art */ }, 'o' } 2447 }; 2448 2449 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { 2450 { { STATE_PSEXCM }, 'i' }, 2451 { { STATE_PSRING }, 'i' }, 2452 { { STATE_WindowStart }, 'i' } 2453 }; 2454 2455 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { 2456 { { 6 /* art */ }, 'i' } 2457 }; 2458 2459 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { 2460 { { STATE_PSEXCM }, 'i' }, 2461 { { STATE_PSRING }, 'i' }, 2462 { { STATE_WindowStart }, 'o' } 2463 }; 2464 2465 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { 2466 { { 6 /* art */ }, 'm' } 2467 }; 2468 2469 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { 2470 { { STATE_PSEXCM }, 'i' }, 2471 { { STATE_PSRING }, 'i' }, 2472 { { STATE_WindowStart }, 'm' } 2473 }; 2474 2475 static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { 2476 { { 3 /* arr */ }, 'o' }, 2477 { { 4 /* ars */ }, 'i' }, 2478 { { 6 /* art */ }, 'i' } 2479 }; 2480 2481 static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { 2482 { { 3 /* arr */ }, 'o' }, 2483 { { 4 /* ars */ }, 'i' }, 2484 { { 16 /* ai4const */ }, 'i' } 2485 }; 2486 2487 static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { 2488 { { 4 /* ars */ }, 'i' }, 2489 { { 15 /* uimm6 */ }, 'i' } 2490 }; 2491 2492 static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { 2493 { { 6 /* art */ }, 'o' }, 2494 { { 4 /* ars */ }, 'i' }, 2495 { { 13 /* lsi4x4 */ }, 'i' } 2496 }; 2497 2498 static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { 2499 { { 6 /* art */ }, 'o' }, 2500 { { 4 /* ars */ }, 'i' } 2501 }; 2502 2503 static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { 2504 { { 4 /* ars */ }, 'o' }, 2505 { { 14 /* simm7 */ }, 'i' } 2506 }; 2507 2508 static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { 2509 { { 5 /* *ars_invisible */ }, 'i' } 2510 }; 2511 2512 static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { 2513 { { 6 /* art */ }, 'i' }, 2514 { { 4 /* ars */ }, 'i' }, 2515 { { 13 /* lsi4x4 */ }, 'i' } 2516 }; 2517 2518 static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { 2519 { { 6 /* art */ }, 'o' }, 2520 { { 4 /* ars */ }, 'i' }, 2521 { { 23 /* simm8 */ }, 'i' } 2522 }; 2523 2524 static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { 2525 { { 6 /* art */ }, 'o' }, 2526 { { 4 /* ars */ }, 'i' }, 2527 { { 24 /* simm8x256 */ }, 'i' } 2528 }; 2529 2530 static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { 2531 { { 3 /* arr */ }, 'o' }, 2532 { { 4 /* ars */ }, 'i' }, 2533 { { 6 /* art */ }, 'i' } 2534 }; 2535 2536 static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { 2537 { { 3 /* arr */ }, 'o' }, 2538 { { 4 /* ars */ }, 'i' }, 2539 { { 6 /* art */ }, 'i' } 2540 }; 2541 2542 static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { 2543 { { 4 /* ars */ }, 'i' }, 2544 { { 17 /* b4const */ }, 'i' }, 2545 { { 28 /* label8 */ }, 'i' } 2546 }; 2547 2548 static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { 2549 { { 4 /* ars */ }, 'i' }, 2550 { { 37 /* bbi */ }, 'i' }, 2551 { { 28 /* label8 */ }, 'i' } 2552 }; 2553 2554 static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { 2555 { { 4 /* ars */ }, 'i' }, 2556 { { 18 /* b4constu */ }, 'i' }, 2557 { { 28 /* label8 */ }, 'i' } 2558 }; 2559 2560 static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { 2561 { { 4 /* ars */ }, 'i' }, 2562 { { 6 /* art */ }, 'i' }, 2563 { { 28 /* label8 */ }, 'i' } 2564 }; 2565 2566 static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { 2567 { { 4 /* ars */ }, 'i' }, 2568 { { 30 /* label12 */ }, 'i' } 2569 }; 2570 2571 static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { 2572 { { 0 /* soffsetx4 */ }, 'i' }, 2573 { { 7 /* ar0 */ }, 'o' } 2574 }; 2575 2576 static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { 2577 { { 4 /* ars */ }, 'i' }, 2578 { { 7 /* ar0 */ }, 'o' } 2579 }; 2580 2581 static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { 2582 { { 3 /* arr */ }, 'o' }, 2583 { { 6 /* art */ }, 'i' }, 2584 { { 52 /* sae */ }, 'i' }, 2585 { { 27 /* op2p1 */ }, 'i' } 2586 }; 2587 2588 static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { 2589 { { 31 /* soffset */ }, 'i' } 2590 }; 2591 2592 static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { 2593 { { 4 /* ars */ }, 'i' } 2594 }; 2595 2596 static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { 2597 { { 6 /* art */ }, 'o' }, 2598 { { 4 /* ars */ }, 'i' }, 2599 { { 20 /* uimm8x2 */ }, 'i' } 2600 }; 2601 2602 static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { 2603 { { 6 /* art */ }, 'o' }, 2604 { { 4 /* ars */ }, 'i' }, 2605 { { 20 /* uimm8x2 */ }, 'i' } 2606 }; 2607 2608 static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { 2609 { { 6 /* art */ }, 'o' }, 2610 { { 4 /* ars */ }, 'i' }, 2611 { { 21 /* uimm8x4 */ }, 'i' } 2612 }; 2613 2614 static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { 2615 { { 6 /* art */ }, 'o' }, 2616 { { 32 /* uimm16x4 */ }, 'i' } 2617 }; 2618 2619 static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = { 2620 { { STATE_LITBADDR }, 'i' }, 2621 { { STATE_LITBEN }, 'i' } 2622 }; 2623 2624 static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { 2625 { { 6 /* art */ }, 'o' }, 2626 { { 4 /* ars */ }, 'i' }, 2627 { { 19 /* uimm8 */ }, 'i' } 2628 }; 2629 2630 static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { 2631 { { 4 /* ars */ }, 'i' }, 2632 { { 29 /* ulabel8 */ }, 'i' } 2633 }; 2634 2635 static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { 2636 { { STATE_LBEG }, 'o' }, 2637 { { STATE_LEND }, 'o' }, 2638 { { STATE_LCOUNT }, 'o' } 2639 }; 2640 2641 static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { 2642 { { 4 /* ars */ }, 'i' }, 2643 { { 29 /* ulabel8 */ }, 'i' } 2644 }; 2645 2646 static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { 2647 { { STATE_LBEG }, 'o' }, 2648 { { STATE_LEND }, 'o' }, 2649 { { STATE_LCOUNT }, 'o' } 2650 }; 2651 2652 static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { 2653 { { 6 /* art */ }, 'o' }, 2654 { { 25 /* simm12b */ }, 'i' } 2655 }; 2656 2657 static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { 2658 { { 3 /* arr */ }, 'm' }, 2659 { { 4 /* ars */ }, 'i' }, 2660 { { 6 /* art */ }, 'i' } 2661 }; 2662 2663 static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { 2664 { { 3 /* arr */ }, 'o' }, 2665 { { 6 /* art */ }, 'i' } 2666 }; 2667 2668 static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { 2669 { { 5 /* *ars_invisible */ }, 'i' } 2670 }; 2671 2672 static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { 2673 { { 6 /* art */ }, 'i' }, 2674 { { 4 /* ars */ }, 'i' }, 2675 { { 20 /* uimm8x2 */ }, 'i' } 2676 }; 2677 2678 static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { 2679 { { 6 /* art */ }, 'i' }, 2680 { { 4 /* ars */ }, 'i' }, 2681 { { 21 /* uimm8x4 */ }, 'i' } 2682 }; 2683 2684 static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { 2685 { { 6 /* art */ }, 'i' }, 2686 { { 4 /* ars */ }, 'i' }, 2687 { { 19 /* uimm8 */ }, 'i' } 2688 }; 2689 2690 static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { 2691 { { 4 /* ars */ }, 'i' } 2692 }; 2693 2694 static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { 2695 { { STATE_SAR }, 'o' } 2696 }; 2697 2698 static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { 2699 { { 56 /* sas */ }, 'i' } 2700 }; 2701 2702 static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { 2703 { { STATE_SAR }, 'o' } 2704 }; 2705 2706 static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { 2707 { { 3 /* arr */ }, 'o' }, 2708 { { 4 /* ars */ }, 'i' } 2709 }; 2710 2711 static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { 2712 { { STATE_SAR }, 'i' } 2713 }; 2714 2715 static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { 2716 { { 3 /* arr */ }, 'o' }, 2717 { { 4 /* ars */ }, 'i' }, 2718 { { 6 /* art */ }, 'i' } 2719 }; 2720 2721 static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { 2722 { { STATE_SAR }, 'i' } 2723 }; 2724 2725 static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { 2726 { { 3 /* arr */ }, 'o' }, 2727 { { 6 /* art */ }, 'i' } 2728 }; 2729 2730 static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { 2731 { { STATE_SAR }, 'i' } 2732 }; 2733 2734 static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { 2735 { { 3 /* arr */ }, 'o' }, 2736 { { 4 /* ars */ }, 'i' }, 2737 { { 26 /* msalp32 */ }, 'i' } 2738 }; 2739 2740 static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { 2741 { { 3 /* arr */ }, 'o' }, 2742 { { 6 /* art */ }, 'i' }, 2743 { { 54 /* sargt */ }, 'i' } 2744 }; 2745 2746 static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { 2747 { { 3 /* arr */ }, 'o' }, 2748 { { 6 /* art */ }, 'i' }, 2749 { { 40 /* s */ }, 'i' } 2750 }; 2751 2752 static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { 2753 { { STATE_XTSYNC }, 'i' } 2754 }; 2755 2756 static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { 2757 { { 6 /* art */ }, 'o' }, 2758 { { 40 /* s */ }, 'i' } 2759 }; 2760 2761 static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { 2762 { { STATE_PSWOE }, 'i' }, 2763 { { STATE_PSCALLINC }, 'i' }, 2764 { { STATE_PSOWB }, 'i' }, 2765 { { STATE_PSRING }, 'i' }, 2766 { { STATE_PSUM }, 'i' }, 2767 { { STATE_PSEXCM }, 'i' }, 2768 { { STATE_PSINTLEVEL }, 'm' } 2769 }; 2770 2771 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { 2772 { { 6 /* art */ }, 'o' } 2773 }; 2774 2775 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { 2776 { { STATE_LEND }, 'i' } 2777 }; 2778 2779 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { 2780 { { 6 /* art */ }, 'i' } 2781 }; 2782 2783 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { 2784 { { STATE_LEND }, 'o' } 2785 }; 2786 2787 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { 2788 { { 6 /* art */ }, 'm' } 2789 }; 2790 2791 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { 2792 { { STATE_LEND }, 'm' } 2793 }; 2794 2795 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { 2796 { { 6 /* art */ }, 'o' } 2797 }; 2798 2799 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { 2800 { { STATE_LCOUNT }, 'i' } 2801 }; 2802 2803 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { 2804 { { 6 /* art */ }, 'i' } 2805 }; 2806 2807 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { 2808 { { STATE_XTSYNC }, 'o' }, 2809 { { STATE_LCOUNT }, 'o' } 2810 }; 2811 2812 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { 2813 { { 6 /* art */ }, 'm' } 2814 }; 2815 2816 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { 2817 { { STATE_XTSYNC }, 'o' }, 2818 { { STATE_LCOUNT }, 'm' } 2819 }; 2820 2821 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { 2822 { { 6 /* art */ }, 'o' } 2823 }; 2824 2825 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { 2826 { { STATE_LBEG }, 'i' } 2827 }; 2828 2829 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { 2830 { { 6 /* art */ }, 'i' } 2831 }; 2832 2833 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { 2834 { { STATE_LBEG }, 'o' } 2835 }; 2836 2837 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { 2838 { { 6 /* art */ }, 'm' } 2839 }; 2840 2841 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { 2842 { { STATE_LBEG }, 'm' } 2843 }; 2844 2845 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { 2846 { { 6 /* art */ }, 'o' } 2847 }; 2848 2849 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { 2850 { { STATE_SAR }, 'i' } 2851 }; 2852 2853 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { 2854 { { 6 /* art */ }, 'i' } 2855 }; 2856 2857 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { 2858 { { STATE_SAR }, 'o' }, 2859 { { STATE_XTSYNC }, 'o' } 2860 }; 2861 2862 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { 2863 { { 6 /* art */ }, 'm' } 2864 }; 2865 2866 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { 2867 { { STATE_SAR }, 'm' } 2868 }; 2869 2870 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { 2871 { { 6 /* art */ }, 'o' } 2872 }; 2873 2874 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = { 2875 { { STATE_LITBADDR }, 'i' }, 2876 { { STATE_LITBEN }, 'i' } 2877 }; 2878 2879 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { 2880 { { 6 /* art */ }, 'i' } 2881 }; 2882 2883 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = { 2884 { { STATE_LITBADDR }, 'o' }, 2885 { { STATE_LITBEN }, 'o' } 2886 }; 2887 2888 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { 2889 { { 6 /* art */ }, 'm' } 2890 }; 2891 2892 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = { 2893 { { STATE_LITBADDR }, 'm' }, 2894 { { STATE_LITBEN }, 'm' } 2895 }; 2896 2897 static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = { 2898 { { 6 /* art */ }, 'o' } 2899 }; 2900 2901 static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = { 2902 { { STATE_PSEXCM }, 'i' }, 2903 { { STATE_PSRING }, 'i' } 2904 }; 2905 2906 static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = { 2907 { { 6 /* art */ }, 'o' } 2908 }; 2909 2910 static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = { 2911 { { STATE_PSEXCM }, 'i' }, 2912 { { STATE_PSRING }, 'i' } 2913 }; 2914 2915 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { 2916 { { 6 /* art */ }, 'o' } 2917 }; 2918 2919 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { 2920 { { STATE_PSWOE }, 'i' }, 2921 { { STATE_PSCALLINC }, 'i' }, 2922 { { STATE_PSOWB }, 'i' }, 2923 { { STATE_PSRING }, 'i' }, 2924 { { STATE_PSUM }, 'i' }, 2925 { { STATE_PSEXCM }, 'i' }, 2926 { { STATE_PSINTLEVEL }, 'i' } 2927 }; 2928 2929 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { 2930 { { 6 /* art */ }, 'i' } 2931 }; 2932 2933 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { 2934 { { STATE_PSWOE }, 'o' }, 2935 { { STATE_PSCALLINC }, 'o' }, 2936 { { STATE_PSOWB }, 'o' }, 2937 { { STATE_PSRING }, 'm' }, 2938 { { STATE_PSUM }, 'o' }, 2939 { { STATE_PSEXCM }, 'm' }, 2940 { { STATE_PSINTLEVEL }, 'o' } 2941 }; 2942 2943 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { 2944 { { 6 /* art */ }, 'm' } 2945 }; 2946 2947 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { 2948 { { STATE_PSWOE }, 'm' }, 2949 { { STATE_PSCALLINC }, 'm' }, 2950 { { STATE_PSOWB }, 'm' }, 2951 { { STATE_PSRING }, 'm' }, 2952 { { STATE_PSUM }, 'm' }, 2953 { { STATE_PSEXCM }, 'm' }, 2954 { { STATE_PSINTLEVEL }, 'm' } 2955 }; 2956 2957 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { 2958 { { 6 /* art */ }, 'o' } 2959 }; 2960 2961 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { 2962 { { STATE_PSEXCM }, 'i' }, 2963 { { STATE_PSRING }, 'i' }, 2964 { { STATE_EPC1 }, 'i' } 2965 }; 2966 2967 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { 2968 { { 6 /* art */ }, 'i' } 2969 }; 2970 2971 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { 2972 { { STATE_PSEXCM }, 'i' }, 2973 { { STATE_PSRING }, 'i' }, 2974 { { STATE_EPC1 }, 'o' } 2975 }; 2976 2977 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { 2978 { { 6 /* art */ }, 'm' } 2979 }; 2980 2981 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { 2982 { { STATE_PSEXCM }, 'i' }, 2983 { { STATE_PSRING }, 'i' }, 2984 { { STATE_EPC1 }, 'm' } 2985 }; 2986 2987 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { 2988 { { 6 /* art */ }, 'o' } 2989 }; 2990 2991 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { 2992 { { STATE_PSEXCM }, 'i' }, 2993 { { STATE_PSRING }, 'i' }, 2994 { { STATE_EXCSAVE1 }, 'i' } 2995 }; 2996 2997 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { 2998 { { 6 /* art */ }, 'i' } 2999 }; 3000 3001 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { 3002 { { STATE_PSEXCM }, 'i' }, 3003 { { STATE_PSRING }, 'i' }, 3004 { { STATE_EXCSAVE1 }, 'o' } 3005 }; 3006 3007 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { 3008 { { 6 /* art */ }, 'm' } 3009 }; 3010 3011 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { 3012 { { STATE_PSEXCM }, 'i' }, 3013 { { STATE_PSRING }, 'i' }, 3014 { { STATE_EXCSAVE1 }, 'm' } 3015 }; 3016 3017 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { 3018 { { 6 /* art */ }, 'o' } 3019 }; 3020 3021 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { 3022 { { STATE_PSEXCM }, 'i' }, 3023 { { STATE_PSRING }, 'i' }, 3024 { { STATE_EPC2 }, 'i' } 3025 }; 3026 3027 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { 3028 { { 6 /* art */ }, 'i' } 3029 }; 3030 3031 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { 3032 { { STATE_PSEXCM }, 'i' }, 3033 { { STATE_PSRING }, 'i' }, 3034 { { STATE_EPC2 }, 'o' } 3035 }; 3036 3037 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { 3038 { { 6 /* art */ }, 'm' } 3039 }; 3040 3041 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { 3042 { { STATE_PSEXCM }, 'i' }, 3043 { { STATE_PSRING }, 'i' }, 3044 { { STATE_EPC2 }, 'm' } 3045 }; 3046 3047 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { 3048 { { 6 /* art */ }, 'o' } 3049 }; 3050 3051 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { 3052 { { STATE_PSEXCM }, 'i' }, 3053 { { STATE_PSRING }, 'i' }, 3054 { { STATE_EXCSAVE2 }, 'i' } 3055 }; 3056 3057 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { 3058 { { 6 /* art */ }, 'i' } 3059 }; 3060 3061 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { 3062 { { STATE_PSEXCM }, 'i' }, 3063 { { STATE_PSRING }, 'i' }, 3064 { { STATE_EXCSAVE2 }, 'o' } 3065 }; 3066 3067 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { 3068 { { 6 /* art */ }, 'm' } 3069 }; 3070 3071 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { 3072 { { STATE_PSEXCM }, 'i' }, 3073 { { STATE_PSRING }, 'i' }, 3074 { { STATE_EXCSAVE2 }, 'm' } 3075 }; 3076 3077 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { 3078 { { 6 /* art */ }, 'o' } 3079 }; 3080 3081 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { 3082 { { STATE_PSEXCM }, 'i' }, 3083 { { STATE_PSRING }, 'i' }, 3084 { { STATE_EPC3 }, 'i' } 3085 }; 3086 3087 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { 3088 { { 6 /* art */ }, 'i' } 3089 }; 3090 3091 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { 3092 { { STATE_PSEXCM }, 'i' }, 3093 { { STATE_PSRING }, 'i' }, 3094 { { STATE_EPC3 }, 'o' } 3095 }; 3096 3097 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { 3098 { { 6 /* art */ }, 'm' } 3099 }; 3100 3101 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { 3102 { { STATE_PSEXCM }, 'i' }, 3103 { { STATE_PSRING }, 'i' }, 3104 { { STATE_EPC3 }, 'm' } 3105 }; 3106 3107 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { 3108 { { 6 /* art */ }, 'o' } 3109 }; 3110 3111 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { 3112 { { STATE_PSEXCM }, 'i' }, 3113 { { STATE_PSRING }, 'i' }, 3114 { { STATE_EXCSAVE3 }, 'i' } 3115 }; 3116 3117 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { 3118 { { 6 /* art */ }, 'i' } 3119 }; 3120 3121 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { 3122 { { STATE_PSEXCM }, 'i' }, 3123 { { STATE_PSRING }, 'i' }, 3124 { { STATE_EXCSAVE3 }, 'o' } 3125 }; 3126 3127 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { 3128 { { 6 /* art */ }, 'm' } 3129 }; 3130 3131 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { 3132 { { STATE_PSEXCM }, 'i' }, 3133 { { STATE_PSRING }, 'i' }, 3134 { { STATE_EXCSAVE3 }, 'm' } 3135 }; 3136 3137 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { 3138 { { 6 /* art */ }, 'o' } 3139 }; 3140 3141 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { 3142 { { STATE_PSEXCM }, 'i' }, 3143 { { STATE_PSRING }, 'i' }, 3144 { { STATE_EPC4 }, 'i' } 3145 }; 3146 3147 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { 3148 { { 6 /* art */ }, 'i' } 3149 }; 3150 3151 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { 3152 { { STATE_PSEXCM }, 'i' }, 3153 { { STATE_PSRING }, 'i' }, 3154 { { STATE_EPC4 }, 'o' } 3155 }; 3156 3157 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { 3158 { { 6 /* art */ }, 'm' } 3159 }; 3160 3161 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { 3162 { { STATE_PSEXCM }, 'i' }, 3163 { { STATE_PSRING }, 'i' }, 3164 { { STATE_EPC4 }, 'm' } 3165 }; 3166 3167 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { 3168 { { 6 /* art */ }, 'o' } 3169 }; 3170 3171 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { 3172 { { STATE_PSEXCM }, 'i' }, 3173 { { STATE_PSRING }, 'i' }, 3174 { { STATE_EXCSAVE4 }, 'i' } 3175 }; 3176 3177 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { 3178 { { 6 /* art */ }, 'i' } 3179 }; 3180 3181 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { 3182 { { STATE_PSEXCM }, 'i' }, 3183 { { STATE_PSRING }, 'i' }, 3184 { { STATE_EXCSAVE4 }, 'o' } 3185 }; 3186 3187 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { 3188 { { 6 /* art */ }, 'm' } 3189 }; 3190 3191 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { 3192 { { STATE_PSEXCM }, 'i' }, 3193 { { STATE_PSRING }, 'i' }, 3194 { { STATE_EXCSAVE4 }, 'm' } 3195 }; 3196 3197 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { 3198 { { 6 /* art */ }, 'o' } 3199 }; 3200 3201 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { 3202 { { STATE_PSEXCM }, 'i' }, 3203 { { STATE_PSRING }, 'i' }, 3204 { { STATE_EPS2 }, 'i' } 3205 }; 3206 3207 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { 3208 { { 6 /* art */ }, 'i' } 3209 }; 3210 3211 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { 3212 { { STATE_PSEXCM }, 'i' }, 3213 { { STATE_PSRING }, 'i' }, 3214 { { STATE_EPS2 }, 'o' } 3215 }; 3216 3217 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { 3218 { { 6 /* art */ }, 'm' } 3219 }; 3220 3221 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { 3222 { { STATE_PSEXCM }, 'i' }, 3223 { { STATE_PSRING }, 'i' }, 3224 { { STATE_EPS2 }, 'm' } 3225 }; 3226 3227 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { 3228 { { 6 /* art */ }, 'o' } 3229 }; 3230 3231 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { 3232 { { STATE_PSEXCM }, 'i' }, 3233 { { STATE_PSRING }, 'i' }, 3234 { { STATE_EPS3 }, 'i' } 3235 }; 3236 3237 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { 3238 { { 6 /* art */ }, 'i' } 3239 }; 3240 3241 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { 3242 { { STATE_PSEXCM }, 'i' }, 3243 { { STATE_PSRING }, 'i' }, 3244 { { STATE_EPS3 }, 'o' } 3245 }; 3246 3247 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { 3248 { { 6 /* art */ }, 'm' } 3249 }; 3250 3251 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { 3252 { { STATE_PSEXCM }, 'i' }, 3253 { { STATE_PSRING }, 'i' }, 3254 { { STATE_EPS3 }, 'm' } 3255 }; 3256 3257 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { 3258 { { 6 /* art */ }, 'o' } 3259 }; 3260 3261 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { 3262 { { STATE_PSEXCM }, 'i' }, 3263 { { STATE_PSRING }, 'i' }, 3264 { { STATE_EPS4 }, 'i' } 3265 }; 3266 3267 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { 3268 { { 6 /* art */ }, 'i' } 3269 }; 3270 3271 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { 3272 { { STATE_PSEXCM }, 'i' }, 3273 { { STATE_PSRING }, 'i' }, 3274 { { STATE_EPS4 }, 'o' } 3275 }; 3276 3277 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { 3278 { { 6 /* art */ }, 'm' } 3279 }; 3280 3281 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { 3282 { { STATE_PSEXCM }, 'i' }, 3283 { { STATE_PSRING }, 'i' }, 3284 { { STATE_EPS4 }, 'm' } 3285 }; 3286 3287 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { 3288 { { 6 /* art */ }, 'o' } 3289 }; 3290 3291 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { 3292 { { STATE_PSEXCM }, 'i' }, 3293 { { STATE_PSRING }, 'i' }, 3294 { { STATE_EXCVADDR }, 'i' } 3295 }; 3296 3297 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { 3298 { { 6 /* art */ }, 'i' } 3299 }; 3300 3301 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { 3302 { { STATE_PSEXCM }, 'i' }, 3303 { { STATE_PSRING }, 'i' }, 3304 { { STATE_EXCVADDR }, 'o' } 3305 }; 3306 3307 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { 3308 { { 6 /* art */ }, 'm' } 3309 }; 3310 3311 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { 3312 { { STATE_PSEXCM }, 'i' }, 3313 { { STATE_PSRING }, 'i' }, 3314 { { STATE_EXCVADDR }, 'm' } 3315 }; 3316 3317 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { 3318 { { 6 /* art */ }, 'o' } 3319 }; 3320 3321 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { 3322 { { STATE_PSEXCM }, 'i' }, 3323 { { STATE_PSRING }, 'i' }, 3324 { { STATE_DEPC }, 'i' } 3325 }; 3326 3327 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { 3328 { { 6 /* art */ }, 'i' } 3329 }; 3330 3331 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { 3332 { { STATE_PSEXCM }, 'i' }, 3333 { { STATE_PSRING }, 'i' }, 3334 { { STATE_DEPC }, 'o' } 3335 }; 3336 3337 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { 3338 { { 6 /* art */ }, 'm' } 3339 }; 3340 3341 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { 3342 { { STATE_PSEXCM }, 'i' }, 3343 { { STATE_PSRING }, 'i' }, 3344 { { STATE_DEPC }, 'm' } 3345 }; 3346 3347 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { 3348 { { 6 /* art */ }, 'o' } 3349 }; 3350 3351 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { 3352 { { STATE_PSEXCM }, 'i' }, 3353 { { STATE_PSRING }, 'i' }, 3354 { { STATE_EXCCAUSE }, 'i' }, 3355 { { STATE_XTSYNC }, 'i' } 3356 }; 3357 3358 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { 3359 { { 6 /* art */ }, 'i' } 3360 }; 3361 3362 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { 3363 { { STATE_PSEXCM }, 'i' }, 3364 { { STATE_PSRING }, 'i' }, 3365 { { STATE_EXCCAUSE }, 'o' } 3366 }; 3367 3368 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { 3369 { { 6 /* art */ }, 'm' } 3370 }; 3371 3372 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { 3373 { { STATE_PSEXCM }, 'i' }, 3374 { { STATE_PSRING }, 'i' }, 3375 { { STATE_EXCCAUSE }, 'm' } 3376 }; 3377 3378 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { 3379 { { 6 /* art */ }, 'o' } 3380 }; 3381 3382 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { 3383 { { STATE_PSEXCM }, 'i' }, 3384 { { STATE_PSRING }, 'i' }, 3385 { { STATE_MISC0 }, 'i' } 3386 }; 3387 3388 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { 3389 { { 6 /* art */ }, 'i' } 3390 }; 3391 3392 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { 3393 { { STATE_PSEXCM }, 'i' }, 3394 { { STATE_PSRING }, 'i' }, 3395 { { STATE_MISC0 }, 'o' } 3396 }; 3397 3398 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { 3399 { { 6 /* art */ }, 'm' } 3400 }; 3401 3402 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { 3403 { { STATE_PSEXCM }, 'i' }, 3404 { { STATE_PSRING }, 'i' }, 3405 { { STATE_MISC0 }, 'm' } 3406 }; 3407 3408 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { 3409 { { 6 /* art */ }, 'o' } 3410 }; 3411 3412 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { 3413 { { STATE_PSEXCM }, 'i' }, 3414 { { STATE_PSRING }, 'i' }, 3415 { { STATE_MISC1 }, 'i' } 3416 }; 3417 3418 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { 3419 { { 6 /* art */ }, 'i' } 3420 }; 3421 3422 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { 3423 { { STATE_PSEXCM }, 'i' }, 3424 { { STATE_PSRING }, 'i' }, 3425 { { STATE_MISC1 }, 'o' } 3426 }; 3427 3428 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { 3429 { { 6 /* art */ }, 'm' } 3430 }; 3431 3432 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { 3433 { { STATE_PSEXCM }, 'i' }, 3434 { { STATE_PSRING }, 'i' }, 3435 { { STATE_MISC1 }, 'm' } 3436 }; 3437 3438 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { 3439 { { 6 /* art */ }, 'o' } 3440 }; 3441 3442 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { 3443 { { STATE_PSEXCM }, 'i' }, 3444 { { STATE_PSRING }, 'i' } 3445 }; 3446 3447 static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { 3448 { { 40 /* s */ }, 'i' } 3449 }; 3450 3451 static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { 3452 { { STATE_PSWOE }, 'o' }, 3453 { { STATE_PSCALLINC }, 'o' }, 3454 { { STATE_PSOWB }, 'o' }, 3455 { { STATE_PSRING }, 'm' }, 3456 { { STATE_PSUM }, 'o' }, 3457 { { STATE_PSEXCM }, 'm' }, 3458 { { STATE_PSINTLEVEL }, 'o' }, 3459 { { STATE_EPC1 }, 'i' }, 3460 { { STATE_EPC2 }, 'i' }, 3461 { { STATE_EPC3 }, 'i' }, 3462 { { STATE_EPC4 }, 'i' }, 3463 { { STATE_EPS2 }, 'i' }, 3464 { { STATE_EPS3 }, 'i' }, 3465 { { STATE_EPS4 }, 'i' }, 3466 { { STATE_InOCDMode }, 'm' } 3467 }; 3468 3469 static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { 3470 { { 40 /* s */ }, 'i' } 3471 }; 3472 3473 static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { 3474 { { STATE_PSEXCM }, 'i' }, 3475 { { STATE_PSRING }, 'i' }, 3476 { { STATE_PSINTLEVEL }, 'o' } 3477 }; 3478 3479 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { 3480 { { 6 /* art */ }, 'o' } 3481 }; 3482 3483 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { 3484 { { STATE_PSEXCM }, 'i' }, 3485 { { STATE_PSRING }, 'i' }, 3486 { { STATE_INTERRUPT }, 'i' } 3487 }; 3488 3489 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { 3490 { { 6 /* art */ }, 'i' } 3491 }; 3492 3493 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { 3494 { { STATE_PSEXCM }, 'i' }, 3495 { { STATE_PSRING }, 'i' }, 3496 { { STATE_XTSYNC }, 'o' }, 3497 { { STATE_INTERRUPT }, 'm' } 3498 }; 3499 3500 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { 3501 { { 6 /* art */ }, 'i' } 3502 }; 3503 3504 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { 3505 { { STATE_PSEXCM }, 'i' }, 3506 { { STATE_PSRING }, 'i' }, 3507 { { STATE_XTSYNC }, 'o' }, 3508 { { STATE_INTERRUPT }, 'm' } 3509 }; 3510 3511 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { 3512 { { 6 /* art */ }, 'o' } 3513 }; 3514 3515 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { 3516 { { STATE_PSEXCM }, 'i' }, 3517 { { STATE_PSRING }, 'i' }, 3518 { { STATE_INTENABLE }, 'i' } 3519 }; 3520 3521 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { 3522 { { 6 /* art */ }, 'i' } 3523 }; 3524 3525 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { 3526 { { STATE_PSEXCM }, 'i' }, 3527 { { STATE_PSRING }, 'i' }, 3528 { { STATE_INTENABLE }, 'o' } 3529 }; 3530 3531 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { 3532 { { 6 /* art */ }, 'm' } 3533 }; 3534 3535 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { 3536 { { STATE_PSEXCM }, 'i' }, 3537 { { STATE_PSRING }, 'i' }, 3538 { { STATE_INTENABLE }, 'm' } 3539 }; 3540 3541 static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { 3542 { { 34 /* imms */ }, 'i' }, 3543 { { 33 /* immt */ }, 'i' } 3544 }; 3545 3546 static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { 3547 { { STATE_PSEXCM }, 'i' }, 3548 { { STATE_PSINTLEVEL }, 'i' } 3549 }; 3550 3551 static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { 3552 { { 34 /* imms */ }, 'i' } 3553 }; 3554 3555 static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { 3556 { { STATE_PSEXCM }, 'i' }, 3557 { { STATE_PSINTLEVEL }, 'i' } 3558 }; 3559 3560 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { 3561 { { 6 /* art */ }, 'o' } 3562 }; 3563 3564 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { 3565 { { STATE_PSEXCM }, 'i' }, 3566 { { STATE_PSRING }, 'i' }, 3567 { { STATE_DBREAKA0 }, 'i' } 3568 }; 3569 3570 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { 3571 { { 6 /* art */ }, 'i' } 3572 }; 3573 3574 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { 3575 { { STATE_PSEXCM }, 'i' }, 3576 { { STATE_PSRING }, 'i' }, 3577 { { STATE_DBREAKA0 }, 'o' }, 3578 { { STATE_XTSYNC }, 'o' } 3579 }; 3580 3581 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { 3582 { { 6 /* art */ }, 'm' } 3583 }; 3584 3585 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { 3586 { { STATE_PSEXCM }, 'i' }, 3587 { { STATE_PSRING }, 'i' }, 3588 { { STATE_DBREAKA0 }, 'm' }, 3589 { { STATE_XTSYNC }, 'o' } 3590 }; 3591 3592 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { 3593 { { 6 /* art */ }, 'o' } 3594 }; 3595 3596 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { 3597 { { STATE_PSEXCM }, 'i' }, 3598 { { STATE_PSRING }, 'i' }, 3599 { { STATE_DBREAKC0 }, 'i' } 3600 }; 3601 3602 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { 3603 { { 6 /* art */ }, 'i' } 3604 }; 3605 3606 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { 3607 { { STATE_PSEXCM }, 'i' }, 3608 { { STATE_PSRING }, 'i' }, 3609 { { STATE_DBREAKC0 }, 'o' }, 3610 { { STATE_XTSYNC }, 'o' } 3611 }; 3612 3613 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { 3614 { { 6 /* art */ }, 'm' } 3615 }; 3616 3617 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { 3618 { { STATE_PSEXCM }, 'i' }, 3619 { { STATE_PSRING }, 'i' }, 3620 { { STATE_DBREAKC0 }, 'm' }, 3621 { { STATE_XTSYNC }, 'o' } 3622 }; 3623 3624 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { 3625 { { 6 /* art */ }, 'o' } 3626 }; 3627 3628 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { 3629 { { STATE_PSEXCM }, 'i' }, 3630 { { STATE_PSRING }, 'i' }, 3631 { { STATE_DBREAKA1 }, 'i' } 3632 }; 3633 3634 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { 3635 { { 6 /* art */ }, 'i' } 3636 }; 3637 3638 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { 3639 { { STATE_PSEXCM }, 'i' }, 3640 { { STATE_PSRING }, 'i' }, 3641 { { STATE_DBREAKA1 }, 'o' }, 3642 { { STATE_XTSYNC }, 'o' } 3643 }; 3644 3645 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { 3646 { { 6 /* art */ }, 'm' } 3647 }; 3648 3649 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { 3650 { { STATE_PSEXCM }, 'i' }, 3651 { { STATE_PSRING }, 'i' }, 3652 { { STATE_DBREAKA1 }, 'm' }, 3653 { { STATE_XTSYNC }, 'o' } 3654 }; 3655 3656 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { 3657 { { 6 /* art */ }, 'o' } 3658 }; 3659 3660 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { 3661 { { STATE_PSEXCM }, 'i' }, 3662 { { STATE_PSRING }, 'i' }, 3663 { { STATE_DBREAKC1 }, 'i' } 3664 }; 3665 3666 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { 3667 { { 6 /* art */ }, 'i' } 3668 }; 3669 3670 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { 3671 { { STATE_PSEXCM }, 'i' }, 3672 { { STATE_PSRING }, 'i' }, 3673 { { STATE_DBREAKC1 }, 'o' }, 3674 { { STATE_XTSYNC }, 'o' } 3675 }; 3676 3677 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { 3678 { { 6 /* art */ }, 'm' } 3679 }; 3680 3681 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { 3682 { { STATE_PSEXCM }, 'i' }, 3683 { { STATE_PSRING }, 'i' }, 3684 { { STATE_DBREAKC1 }, 'm' }, 3685 { { STATE_XTSYNC }, 'o' } 3686 }; 3687 3688 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { 3689 { { 6 /* art */ }, 'o' } 3690 }; 3691 3692 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { 3693 { { STATE_PSEXCM }, 'i' }, 3694 { { STATE_PSRING }, 'i' }, 3695 { { STATE_IBREAKA0 }, 'i' } 3696 }; 3697 3698 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { 3699 { { 6 /* art */ }, 'i' } 3700 }; 3701 3702 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { 3703 { { STATE_PSEXCM }, 'i' }, 3704 { { STATE_PSRING }, 'i' }, 3705 { { STATE_IBREAKA0 }, 'o' } 3706 }; 3707 3708 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { 3709 { { 6 /* art */ }, 'm' } 3710 }; 3711 3712 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { 3713 { { STATE_PSEXCM }, 'i' }, 3714 { { STATE_PSRING }, 'i' }, 3715 { { STATE_IBREAKA0 }, 'm' } 3716 }; 3717 3718 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { 3719 { { 6 /* art */ }, 'o' } 3720 }; 3721 3722 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { 3723 { { STATE_PSEXCM }, 'i' }, 3724 { { STATE_PSRING }, 'i' }, 3725 { { STATE_IBREAKA1 }, 'i' } 3726 }; 3727 3728 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { 3729 { { 6 /* art */ }, 'i' } 3730 }; 3731 3732 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { 3733 { { STATE_PSEXCM }, 'i' }, 3734 { { STATE_PSRING }, 'i' }, 3735 { { STATE_IBREAKA1 }, 'o' } 3736 }; 3737 3738 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { 3739 { { 6 /* art */ }, 'm' } 3740 }; 3741 3742 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { 3743 { { STATE_PSEXCM }, 'i' }, 3744 { { STATE_PSRING }, 'i' }, 3745 { { STATE_IBREAKA1 }, 'm' } 3746 }; 3747 3748 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { 3749 { { 6 /* art */ }, 'o' } 3750 }; 3751 3752 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { 3753 { { STATE_PSEXCM }, 'i' }, 3754 { { STATE_PSRING }, 'i' }, 3755 { { STATE_IBREAKENABLE }, 'i' } 3756 }; 3757 3758 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { 3759 { { 6 /* art */ }, 'i' } 3760 }; 3761 3762 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { 3763 { { STATE_PSEXCM }, 'i' }, 3764 { { STATE_PSRING }, 'i' }, 3765 { { STATE_IBREAKENABLE }, 'o' } 3766 }; 3767 3768 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { 3769 { { 6 /* art */ }, 'm' } 3770 }; 3771 3772 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { 3773 { { STATE_PSEXCM }, 'i' }, 3774 { { STATE_PSRING }, 'i' }, 3775 { { STATE_IBREAKENABLE }, 'm' } 3776 }; 3777 3778 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { 3779 { { 6 /* art */ }, 'o' } 3780 }; 3781 3782 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { 3783 { { STATE_PSEXCM }, 'i' }, 3784 { { STATE_PSRING }, 'i' }, 3785 { { STATE_DEBUGCAUSE }, 'i' }, 3786 { { STATE_DBNUM }, 'i' } 3787 }; 3788 3789 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { 3790 { { 6 /* art */ }, 'i' } 3791 }; 3792 3793 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { 3794 { { STATE_PSEXCM }, 'i' }, 3795 { { STATE_PSRING }, 'i' }, 3796 { { STATE_DEBUGCAUSE }, 'o' }, 3797 { { STATE_DBNUM }, 'o' } 3798 }; 3799 3800 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { 3801 { { 6 /* art */ }, 'm' } 3802 }; 3803 3804 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { 3805 { { STATE_PSEXCM }, 'i' }, 3806 { { STATE_PSRING }, 'i' }, 3807 { { STATE_DEBUGCAUSE }, 'm' }, 3808 { { STATE_DBNUM }, 'm' } 3809 }; 3810 3811 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { 3812 { { 6 /* art */ }, 'o' } 3813 }; 3814 3815 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { 3816 { { STATE_PSEXCM }, 'i' }, 3817 { { STATE_PSRING }, 'i' }, 3818 { { STATE_ICOUNT }, 'i' } 3819 }; 3820 3821 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { 3822 { { 6 /* art */ }, 'i' } 3823 }; 3824 3825 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { 3826 { { STATE_PSEXCM }, 'i' }, 3827 { { STATE_PSRING }, 'i' }, 3828 { { STATE_XTSYNC }, 'o' }, 3829 { { STATE_ICOUNT }, 'o' } 3830 }; 3831 3832 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { 3833 { { 6 /* art */ }, 'm' } 3834 }; 3835 3836 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { 3837 { { STATE_PSEXCM }, 'i' }, 3838 { { STATE_PSRING }, 'i' }, 3839 { { STATE_XTSYNC }, 'o' }, 3840 { { STATE_ICOUNT }, 'm' } 3841 }; 3842 3843 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { 3844 { { 6 /* art */ }, 'o' } 3845 }; 3846 3847 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { 3848 { { STATE_PSEXCM }, 'i' }, 3849 { { STATE_PSRING }, 'i' }, 3850 { { STATE_ICOUNTLEVEL }, 'i' } 3851 }; 3852 3853 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { 3854 { { 6 /* art */ }, 'i' } 3855 }; 3856 3857 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { 3858 { { STATE_PSEXCM }, 'i' }, 3859 { { STATE_PSRING }, 'i' }, 3860 { { STATE_ICOUNTLEVEL }, 'o' } 3861 }; 3862 3863 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { 3864 { { 6 /* art */ }, 'm' } 3865 }; 3866 3867 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { 3868 { { STATE_PSEXCM }, 'i' }, 3869 { { STATE_PSRING }, 'i' }, 3870 { { STATE_ICOUNTLEVEL }, 'm' } 3871 }; 3872 3873 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { 3874 { { 6 /* art */ }, 'o' } 3875 }; 3876 3877 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { 3878 { { STATE_PSEXCM }, 'i' }, 3879 { { STATE_PSRING }, 'i' }, 3880 { { STATE_DDR }, 'i' } 3881 }; 3882 3883 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { 3884 { { 6 /* art */ }, 'i' } 3885 }; 3886 3887 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { 3888 { { STATE_PSEXCM }, 'i' }, 3889 { { STATE_PSRING }, 'i' }, 3890 { { STATE_XTSYNC }, 'o' }, 3891 { { STATE_DDR }, 'o' } 3892 }; 3893 3894 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { 3895 { { 6 /* art */ }, 'm' } 3896 }; 3897 3898 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { 3899 { { STATE_PSEXCM }, 'i' }, 3900 { { STATE_PSRING }, 'i' }, 3901 { { STATE_XTSYNC }, 'o' }, 3902 { { STATE_DDR }, 'm' } 3903 }; 3904 3905 static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { 3906 { { STATE_InOCDMode }, 'm' }, 3907 { { STATE_EPC4 }, 'i' }, 3908 { { STATE_PSWOE }, 'o' }, 3909 { { STATE_PSCALLINC }, 'o' }, 3910 { { STATE_PSOWB }, 'o' }, 3911 { { STATE_PSRING }, 'o' }, 3912 { { STATE_PSUM }, 'o' }, 3913 { { STATE_PSEXCM }, 'o' }, 3914 { { STATE_PSINTLEVEL }, 'o' }, 3915 { { STATE_EPS4 }, 'i' } 3916 }; 3917 3918 static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { 3919 { { STATE_InOCDMode }, 'm' } 3920 }; 3921 3922 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { 3923 { { 6 /* art */ }, 'o' } 3924 }; 3925 3926 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { 3927 { { STATE_PSEXCM }, 'i' }, 3928 { { STATE_PSRING }, 'i' }, 3929 { { STATE_CCOUNT }, 'i' } 3930 }; 3931 3932 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { 3933 { { 6 /* art */ }, 'i' } 3934 }; 3935 3936 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { 3937 { { STATE_PSEXCM }, 'i' }, 3938 { { STATE_PSRING }, 'i' }, 3939 { { STATE_XTSYNC }, 'o' }, 3940 { { STATE_CCOUNT }, 'o' } 3941 }; 3942 3943 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { 3944 { { 6 /* art */ }, 'm' } 3945 }; 3946 3947 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { 3948 { { STATE_PSEXCM }, 'i' }, 3949 { { STATE_PSRING }, 'i' }, 3950 { { STATE_XTSYNC }, 'o' }, 3951 { { STATE_CCOUNT }, 'm' } 3952 }; 3953 3954 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { 3955 { { 6 /* art */ }, 'o' } 3956 }; 3957 3958 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { 3959 { { STATE_PSEXCM }, 'i' }, 3960 { { STATE_PSRING }, 'i' }, 3961 { { STATE_CCOMPARE0 }, 'i' } 3962 }; 3963 3964 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { 3965 { { 6 /* art */ }, 'i' } 3966 }; 3967 3968 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { 3969 { { STATE_PSEXCM }, 'i' }, 3970 { { STATE_PSRING }, 'i' }, 3971 { { STATE_CCOMPARE0 }, 'o' }, 3972 { { STATE_INTERRUPT }, 'm' } 3973 }; 3974 3975 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { 3976 { { 6 /* art */ }, 'm' } 3977 }; 3978 3979 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { 3980 { { STATE_PSEXCM }, 'i' }, 3981 { { STATE_PSRING }, 'i' }, 3982 { { STATE_CCOMPARE0 }, 'm' }, 3983 { { STATE_INTERRUPT }, 'm' } 3984 }; 3985 3986 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { 3987 { { 6 /* art */ }, 'o' } 3988 }; 3989 3990 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { 3991 { { STATE_PSEXCM }, 'i' }, 3992 { { STATE_PSRING }, 'i' }, 3993 { { STATE_CCOMPARE1 }, 'i' } 3994 }; 3995 3996 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { 3997 { { 6 /* art */ }, 'i' } 3998 }; 3999 4000 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { 4001 { { STATE_PSEXCM }, 'i' }, 4002 { { STATE_PSRING }, 'i' }, 4003 { { STATE_CCOMPARE1 }, 'o' }, 4004 { { STATE_INTERRUPT }, 'm' } 4005 }; 4006 4007 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { 4008 { { 6 /* art */ }, 'm' } 4009 }; 4010 4011 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { 4012 { { STATE_PSEXCM }, 'i' }, 4013 { { STATE_PSRING }, 'i' }, 4014 { { STATE_CCOMPARE1 }, 'm' }, 4015 { { STATE_INTERRUPT }, 'm' } 4016 }; 4017 4018 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { 4019 { { 6 /* art */ }, 'o' } 4020 }; 4021 4022 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { 4023 { { STATE_PSEXCM }, 'i' }, 4024 { { STATE_PSRING }, 'i' }, 4025 { { STATE_CCOMPARE2 }, 'i' } 4026 }; 4027 4028 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { 4029 { { 6 /* art */ }, 'i' } 4030 }; 4031 4032 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { 4033 { { STATE_PSEXCM }, 'i' }, 4034 { { STATE_PSRING }, 'i' }, 4035 { { STATE_CCOMPARE2 }, 'o' }, 4036 { { STATE_INTERRUPT }, 'm' } 4037 }; 4038 4039 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { 4040 { { 6 /* art */ }, 'm' } 4041 }; 4042 4043 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { 4044 { { STATE_PSEXCM }, 'i' }, 4045 { { STATE_PSRING }, 'i' }, 4046 { { STATE_CCOMPARE2 }, 'm' }, 4047 { { STATE_INTERRUPT }, 'm' } 4048 }; 4049 4050 static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { 4051 { { 4 /* ars */ }, 'i' }, 4052 { { 21 /* uimm8x4 */ }, 'i' } 4053 }; 4054 4055 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { 4056 { { 4 /* ars */ }, 'i' }, 4057 { { 21 /* uimm8x4 */ }, 'i' } 4058 }; 4059 4060 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = { 4061 { { STATE_PSEXCM }, 'i' }, 4062 { { STATE_PSRING }, 'i' } 4063 }; 4064 4065 static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { 4066 { { 6 /* art */ }, 'o' }, 4067 { { 4 /* ars */ }, 'i' } 4068 }; 4069 4070 static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = { 4071 { { STATE_PSEXCM }, 'i' }, 4072 { { STATE_PSRING }, 'i' } 4073 }; 4074 4075 static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { 4076 { { 6 /* art */ }, 'i' }, 4077 { { 4 /* ars */ }, 'i' } 4078 }; 4079 4080 static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = { 4081 { { STATE_PSEXCM }, 'i' }, 4082 { { STATE_PSRING }, 'i' } 4083 }; 4084 4085 static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { 4086 { { 4 /* ars */ }, 'i' }, 4087 { { 21 /* uimm8x4 */ }, 'i' } 4088 }; 4089 4090 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { 4091 { { 4 /* ars */ }, 'i' }, 4092 { { 22 /* uimm4x16 */ }, 'i' } 4093 }; 4094 4095 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = { 4096 { { STATE_PSEXCM }, 'i' }, 4097 { { STATE_PSRING }, 'i' } 4098 }; 4099 4100 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { 4101 { { 4 /* ars */ }, 'i' }, 4102 { { 21 /* uimm8x4 */ }, 'i' } 4103 }; 4104 4105 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = { 4106 { { STATE_PSEXCM }, 'i' }, 4107 { { STATE_PSRING }, 'i' } 4108 }; 4109 4110 static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { 4111 { { 4 /* ars */ }, 'i' }, 4112 { { 21 /* uimm8x4 */ }, 'i' } 4113 }; 4114 4115 static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { 4116 { { 6 /* art */ }, 'i' }, 4117 { { 4 /* ars */ }, 'i' } 4118 }; 4119 4120 static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = { 4121 { { STATE_PSEXCM }, 'i' }, 4122 { { STATE_PSRING }, 'i' } 4123 }; 4124 4125 static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { 4126 { { 6 /* art */ }, 'o' }, 4127 { { 4 /* ars */ }, 'i' } 4128 }; 4129 4130 static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = { 4131 { { STATE_PSEXCM }, 'i' }, 4132 { { STATE_PSRING }, 'i' } 4133 }; 4134 4135 static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = { 4136 { { 6 /* art */ }, 'i' } 4137 }; 4138 4139 static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = { 4140 { { STATE_PSEXCM }, 'i' }, 4141 { { STATE_PSRING }, 'i' }, 4142 { { STATE_PTBASE }, 'o' }, 4143 { { STATE_XTSYNC }, 'o' } 4144 }; 4145 4146 static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = { 4147 { { 6 /* art */ }, 'o' } 4148 }; 4149 4150 static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = { 4151 { { STATE_PSEXCM }, 'i' }, 4152 { { STATE_PSRING }, 'i' }, 4153 { { STATE_PTBASE }, 'i' }, 4154 { { STATE_EXCVADDR }, 'i' } 4155 }; 4156 4157 static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = { 4158 { { 6 /* art */ }, 'm' } 4159 }; 4160 4161 static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = { 4162 { { STATE_PSEXCM }, 'i' }, 4163 { { STATE_PSRING }, 'i' }, 4164 { { STATE_PTBASE }, 'm' }, 4165 { { STATE_EXCVADDR }, 'i' }, 4166 { { STATE_XTSYNC }, 'o' } 4167 }; 4168 4169 static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = { 4170 { { 6 /* art */ }, 'o' } 4171 }; 4172 4173 static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = { 4174 { { STATE_PSEXCM }, 'i' }, 4175 { { STATE_PSRING }, 'i' }, 4176 { { STATE_ASID3 }, 'i' }, 4177 { { STATE_ASID2 }, 'i' }, 4178 { { STATE_ASID1 }, 'i' } 4179 }; 4180 4181 static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = { 4182 { { 6 /* art */ }, 'i' } 4183 }; 4184 4185 static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = { 4186 { { STATE_XTSYNC }, 'o' }, 4187 { { STATE_PSEXCM }, 'i' }, 4188 { { STATE_PSRING }, 'i' }, 4189 { { STATE_ASID3 }, 'o' }, 4190 { { STATE_ASID2 }, 'o' }, 4191 { { STATE_ASID1 }, 'o' } 4192 }; 4193 4194 static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = { 4195 { { 6 /* art */ }, 'm' } 4196 }; 4197 4198 static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = { 4199 { { STATE_XTSYNC }, 'o' }, 4200 { { STATE_PSEXCM }, 'i' }, 4201 { { STATE_PSRING }, 'i' }, 4202 { { STATE_ASID3 }, 'm' }, 4203 { { STATE_ASID2 }, 'm' }, 4204 { { STATE_ASID1 }, 'm' } 4205 }; 4206 4207 static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = { 4208 { { 6 /* art */ }, 'o' } 4209 }; 4210 4211 static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = { 4212 { { STATE_PSEXCM }, 'i' }, 4213 { { STATE_PSRING }, 'i' }, 4214 { { STATE_INSTPGSZID4 }, 'i' } 4215 }; 4216 4217 static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = { 4218 { { 6 /* art */ }, 'i' } 4219 }; 4220 4221 static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = { 4222 { { STATE_XTSYNC }, 'o' }, 4223 { { STATE_PSEXCM }, 'i' }, 4224 { { STATE_PSRING }, 'i' }, 4225 { { STATE_INSTPGSZID4 }, 'o' } 4226 }; 4227 4228 static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = { 4229 { { 6 /* art */ }, 'm' } 4230 }; 4231 4232 static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = { 4233 { { STATE_XTSYNC }, 'o' }, 4234 { { STATE_PSEXCM }, 'i' }, 4235 { { STATE_PSRING }, 'i' }, 4236 { { STATE_INSTPGSZID4 }, 'm' } 4237 }; 4238 4239 static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = { 4240 { { 6 /* art */ }, 'o' } 4241 }; 4242 4243 static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = { 4244 { { STATE_PSEXCM }, 'i' }, 4245 { { STATE_PSRING }, 'i' }, 4246 { { STATE_DATAPGSZID4 }, 'i' } 4247 }; 4248 4249 static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = { 4250 { { 6 /* art */ }, 'i' } 4251 }; 4252 4253 static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = { 4254 { { STATE_XTSYNC }, 'o' }, 4255 { { STATE_PSEXCM }, 'i' }, 4256 { { STATE_PSRING }, 'i' }, 4257 { { STATE_DATAPGSZID4 }, 'o' } 4258 }; 4259 4260 static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = { 4261 { { 6 /* art */ }, 'm' } 4262 }; 4263 4264 static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = { 4265 { { STATE_XTSYNC }, 'o' }, 4266 { { STATE_PSEXCM }, 'i' }, 4267 { { STATE_PSRING }, 'i' }, 4268 { { STATE_DATAPGSZID4 }, 'm' } 4269 }; 4270 4271 static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { 4272 { { 4 /* ars */ }, 'i' } 4273 }; 4274 4275 static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { 4276 { { STATE_PSEXCM }, 'i' }, 4277 { { STATE_PSRING }, 'i' }, 4278 { { STATE_XTSYNC }, 'o' } 4279 }; 4280 4281 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { 4282 { { 6 /* art */ }, 'o' }, 4283 { { 4 /* ars */ }, 'i' } 4284 }; 4285 4286 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = { 4287 { { STATE_PSEXCM }, 'i' }, 4288 { { STATE_PSRING }, 'i' } 4289 }; 4290 4291 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { 4292 { { 6 /* art */ }, 'i' }, 4293 { { 4 /* ars */ }, 'i' } 4294 }; 4295 4296 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { 4297 { { STATE_PSEXCM }, 'i' }, 4298 { { STATE_PSRING }, 'i' }, 4299 { { STATE_XTSYNC }, 'o' } 4300 }; 4301 4302 static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { 4303 { { 4 /* ars */ }, 'i' } 4304 }; 4305 4306 static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = { 4307 { { STATE_PSEXCM }, 'i' }, 4308 { { STATE_PSRING }, 'i' } 4309 }; 4310 4311 static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { 4312 { { 6 /* art */ }, 'o' }, 4313 { { 4 /* ars */ }, 'i' } 4314 }; 4315 4316 static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = { 4317 { { STATE_PSEXCM }, 'i' }, 4318 { { STATE_PSRING }, 'i' } 4319 }; 4320 4321 static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { 4322 { { 6 /* art */ }, 'i' }, 4323 { { 4 /* ars */ }, 'i' } 4324 }; 4325 4326 static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = { 4327 { { STATE_PSEXCM }, 'i' }, 4328 { { STATE_PSRING }, 'i' } 4329 }; 4330 4331 static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = { 4332 { { STATE_PTBASE }, 'i' }, 4333 { { STATE_EXCVADDR }, 'i' } 4334 }; 4335 4336 static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = { 4337 { { STATE_EXCVADDR }, 'i' } 4338 }; 4339 4340 static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = { 4341 { { STATE_EXCVADDR }, 'i' } 4342 }; 4343 4344 static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { 4345 { { 6 /* art */ }, 'o' }, 4346 { { 4 /* ars */ }, 'i' } 4347 }; 4348 4349 static xtensa_iclass_internal iclasses[] = { 4350 { 0, 0 /* xt_iclass_excw */, 4351 0, 0, 0, 0 }, 4352 { 0, 0 /* xt_iclass_rfe */, 4353 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, 4354 { 0, 0 /* xt_iclass_rfde */, 4355 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, 4356 { 0, 0 /* xt_iclass_syscall */, 4357 0, 0, 0, 0 }, 4358 { 0, 0 /* xt_iclass_simcall */, 4359 0, 0, 0, 0 }, 4360 { 2, Iclass_xt_iclass_call12_args, 4361 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, 4362 { 2, Iclass_xt_iclass_call8_args, 4363 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, 4364 { 2, Iclass_xt_iclass_call4_args, 4365 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, 4366 { 2, Iclass_xt_iclass_callx12_args, 4367 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, 4368 { 2, Iclass_xt_iclass_callx8_args, 4369 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, 4370 { 2, Iclass_xt_iclass_callx4_args, 4371 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, 4372 { 3, Iclass_xt_iclass_entry_args, 4373 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, 4374 { 2, Iclass_xt_iclass_movsp_args, 4375 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, 4376 { 1, Iclass_xt_iclass_rotw_args, 4377 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, 4378 { 1, Iclass_xt_iclass_retw_args, 4379 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, 4380 { 0, 0 /* xt_iclass_rfwou */, 4381 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, 4382 { 3, Iclass_xt_iclass_l32e_args, 4383 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, 4384 { 3, Iclass_xt_iclass_s32e_args, 4385 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, 4386 { 1, Iclass_xt_iclass_rsr_windowbase_args, 4387 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, 4388 { 1, Iclass_xt_iclass_wsr_windowbase_args, 4389 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, 4390 { 1, Iclass_xt_iclass_xsr_windowbase_args, 4391 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, 4392 { 1, Iclass_xt_iclass_rsr_windowstart_args, 4393 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, 4394 { 1, Iclass_xt_iclass_wsr_windowstart_args, 4395 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, 4396 { 1, Iclass_xt_iclass_xsr_windowstart_args, 4397 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, 4398 { 3, Iclass_xt_iclass_add_n_args, 4399 0, 0, 0, 0 }, 4400 { 3, Iclass_xt_iclass_addi_n_args, 4401 0, 0, 0, 0 }, 4402 { 2, Iclass_xt_iclass_bz6_args, 4403 0, 0, 0, 0 }, 4404 { 0, 0 /* xt_iclass_ill_n */, 4405 0, 0, 0, 0 }, 4406 { 3, Iclass_xt_iclass_loadi4_args, 4407 0, 0, 0, 0 }, 4408 { 2, Iclass_xt_iclass_mov_n_args, 4409 0, 0, 0, 0 }, 4410 { 2, Iclass_xt_iclass_movi_n_args, 4411 0, 0, 0, 0 }, 4412 { 0, 0 /* xt_iclass_nopn */, 4413 0, 0, 0, 0 }, 4414 { 1, Iclass_xt_iclass_retn_args, 4415 0, 0, 0, 0 }, 4416 { 3, Iclass_xt_iclass_storei4_args, 4417 0, 0, 0, 0 }, 4418 { 3, Iclass_xt_iclass_addi_args, 4419 0, 0, 0, 0 }, 4420 { 3, Iclass_xt_iclass_addmi_args, 4421 0, 0, 0, 0 }, 4422 { 3, Iclass_xt_iclass_addsub_args, 4423 0, 0, 0, 0 }, 4424 { 3, Iclass_xt_iclass_bit_args, 4425 0, 0, 0, 0 }, 4426 { 3, Iclass_xt_iclass_bsi8_args, 4427 0, 0, 0, 0 }, 4428 { 3, Iclass_xt_iclass_bsi8b_args, 4429 0, 0, 0, 0 }, 4430 { 3, Iclass_xt_iclass_bsi8u_args, 4431 0, 0, 0, 0 }, 4432 { 3, Iclass_xt_iclass_bst8_args, 4433 0, 0, 0, 0 }, 4434 { 2, Iclass_xt_iclass_bsz12_args, 4435 0, 0, 0, 0 }, 4436 { 2, Iclass_xt_iclass_call0_args, 4437 0, 0, 0, 0 }, 4438 { 2, Iclass_xt_iclass_callx0_args, 4439 0, 0, 0, 0 }, 4440 { 4, Iclass_xt_iclass_exti_args, 4441 0, 0, 0, 0 }, 4442 { 0, 0 /* xt_iclass_ill */, 4443 0, 0, 0, 0 }, 4444 { 1, Iclass_xt_iclass_jump_args, 4445 0, 0, 0, 0 }, 4446 { 1, Iclass_xt_iclass_jumpx_args, 4447 0, 0, 0, 0 }, 4448 { 3, Iclass_xt_iclass_l16ui_args, 4449 0, 0, 0, 0 }, 4450 { 3, Iclass_xt_iclass_l16si_args, 4451 0, 0, 0, 0 }, 4452 { 3, Iclass_xt_iclass_l32i_args, 4453 0, 0, 0, 0 }, 4454 { 2, Iclass_xt_iclass_l32r_args, 4455 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 }, 4456 { 3, Iclass_xt_iclass_l8i_args, 4457 0, 0, 0, 0 }, 4458 { 2, Iclass_xt_iclass_loop_args, 4459 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, 4460 { 2, Iclass_xt_iclass_loopz_args, 4461 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, 4462 { 2, Iclass_xt_iclass_movi_args, 4463 0, 0, 0, 0 }, 4464 { 3, Iclass_xt_iclass_movz_args, 4465 0, 0, 0, 0 }, 4466 { 2, Iclass_xt_iclass_neg_args, 4467 0, 0, 0, 0 }, 4468 { 0, 0 /* xt_iclass_nop */, 4469 0, 0, 0, 0 }, 4470 { 1, Iclass_xt_iclass_return_args, 4471 0, 0, 0, 0 }, 4472 { 3, Iclass_xt_iclass_s16i_args, 4473 0, 0, 0, 0 }, 4474 { 3, Iclass_xt_iclass_s32i_args, 4475 0, 0, 0, 0 }, 4476 { 3, Iclass_xt_iclass_s8i_args, 4477 0, 0, 0, 0 }, 4478 { 1, Iclass_xt_iclass_sar_args, 4479 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, 4480 { 1, Iclass_xt_iclass_sari_args, 4481 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, 4482 { 2, Iclass_xt_iclass_shifts_args, 4483 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, 4484 { 3, Iclass_xt_iclass_shiftst_args, 4485 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, 4486 { 2, Iclass_xt_iclass_shiftt_args, 4487 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, 4488 { 3, Iclass_xt_iclass_slli_args, 4489 0, 0, 0, 0 }, 4490 { 3, Iclass_xt_iclass_srai_args, 4491 0, 0, 0, 0 }, 4492 { 3, Iclass_xt_iclass_srli_args, 4493 0, 0, 0, 0 }, 4494 { 0, 0 /* xt_iclass_memw */, 4495 0, 0, 0, 0 }, 4496 { 0, 0 /* xt_iclass_extw */, 4497 0, 0, 0, 0 }, 4498 { 0, 0 /* xt_iclass_isync */, 4499 0, 0, 0, 0 }, 4500 { 0, 0 /* xt_iclass_sync */, 4501 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, 4502 { 2, Iclass_xt_iclass_rsil_args, 4503 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, 4504 { 1, Iclass_xt_iclass_rsr_lend_args, 4505 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, 4506 { 1, Iclass_xt_iclass_wsr_lend_args, 4507 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, 4508 { 1, Iclass_xt_iclass_xsr_lend_args, 4509 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, 4510 { 1, Iclass_xt_iclass_rsr_lcount_args, 4511 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, 4512 { 1, Iclass_xt_iclass_wsr_lcount_args, 4513 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, 4514 { 1, Iclass_xt_iclass_xsr_lcount_args, 4515 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, 4516 { 1, Iclass_xt_iclass_rsr_lbeg_args, 4517 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, 4518 { 1, Iclass_xt_iclass_wsr_lbeg_args, 4519 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, 4520 { 1, Iclass_xt_iclass_xsr_lbeg_args, 4521 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, 4522 { 1, Iclass_xt_iclass_rsr_sar_args, 4523 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, 4524 { 1, Iclass_xt_iclass_wsr_sar_args, 4525 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, 4526 { 1, Iclass_xt_iclass_xsr_sar_args, 4527 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, 4528 { 1, Iclass_xt_iclass_rsr_litbase_args, 4529 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 }, 4530 { 1, Iclass_xt_iclass_wsr_litbase_args, 4531 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 }, 4532 { 1, Iclass_xt_iclass_xsr_litbase_args, 4533 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 }, 4534 { 1, Iclass_xt_iclass_rsr_176_args, 4535 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 }, 4536 { 1, Iclass_xt_iclass_rsr_208_args, 4537 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 }, 4538 { 1, Iclass_xt_iclass_rsr_ps_args, 4539 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, 4540 { 1, Iclass_xt_iclass_wsr_ps_args, 4541 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, 4542 { 1, Iclass_xt_iclass_xsr_ps_args, 4543 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, 4544 { 1, Iclass_xt_iclass_rsr_epc1_args, 4545 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, 4546 { 1, Iclass_xt_iclass_wsr_epc1_args, 4547 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, 4548 { 1, Iclass_xt_iclass_xsr_epc1_args, 4549 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, 4550 { 1, Iclass_xt_iclass_rsr_excsave1_args, 4551 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, 4552 { 1, Iclass_xt_iclass_wsr_excsave1_args, 4553 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, 4554 { 1, Iclass_xt_iclass_xsr_excsave1_args, 4555 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, 4556 { 1, Iclass_xt_iclass_rsr_epc2_args, 4557 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, 4558 { 1, Iclass_xt_iclass_wsr_epc2_args, 4559 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, 4560 { 1, Iclass_xt_iclass_xsr_epc2_args, 4561 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, 4562 { 1, Iclass_xt_iclass_rsr_excsave2_args, 4563 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, 4564 { 1, Iclass_xt_iclass_wsr_excsave2_args, 4565 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, 4566 { 1, Iclass_xt_iclass_xsr_excsave2_args, 4567 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, 4568 { 1, Iclass_xt_iclass_rsr_epc3_args, 4569 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, 4570 { 1, Iclass_xt_iclass_wsr_epc3_args, 4571 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, 4572 { 1, Iclass_xt_iclass_xsr_epc3_args, 4573 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, 4574 { 1, Iclass_xt_iclass_rsr_excsave3_args, 4575 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, 4576 { 1, Iclass_xt_iclass_wsr_excsave3_args, 4577 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, 4578 { 1, Iclass_xt_iclass_xsr_excsave3_args, 4579 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, 4580 { 1, Iclass_xt_iclass_rsr_epc4_args, 4581 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, 4582 { 1, Iclass_xt_iclass_wsr_epc4_args, 4583 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, 4584 { 1, Iclass_xt_iclass_xsr_epc4_args, 4585 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, 4586 { 1, Iclass_xt_iclass_rsr_excsave4_args, 4587 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, 4588 { 1, Iclass_xt_iclass_wsr_excsave4_args, 4589 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, 4590 { 1, Iclass_xt_iclass_xsr_excsave4_args, 4591 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, 4592 { 1, Iclass_xt_iclass_rsr_eps2_args, 4593 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, 4594 { 1, Iclass_xt_iclass_wsr_eps2_args, 4595 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, 4596 { 1, Iclass_xt_iclass_xsr_eps2_args, 4597 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, 4598 { 1, Iclass_xt_iclass_rsr_eps3_args, 4599 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, 4600 { 1, Iclass_xt_iclass_wsr_eps3_args, 4601 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, 4602 { 1, Iclass_xt_iclass_xsr_eps3_args, 4603 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, 4604 { 1, Iclass_xt_iclass_rsr_eps4_args, 4605 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, 4606 { 1, Iclass_xt_iclass_wsr_eps4_args, 4607 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, 4608 { 1, Iclass_xt_iclass_xsr_eps4_args, 4609 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, 4610 { 1, Iclass_xt_iclass_rsr_excvaddr_args, 4611 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, 4612 { 1, Iclass_xt_iclass_wsr_excvaddr_args, 4613 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, 4614 { 1, Iclass_xt_iclass_xsr_excvaddr_args, 4615 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, 4616 { 1, Iclass_xt_iclass_rsr_depc_args, 4617 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, 4618 { 1, Iclass_xt_iclass_wsr_depc_args, 4619 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, 4620 { 1, Iclass_xt_iclass_xsr_depc_args, 4621 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, 4622 { 1, Iclass_xt_iclass_rsr_exccause_args, 4623 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, 4624 { 1, Iclass_xt_iclass_wsr_exccause_args, 4625 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, 4626 { 1, Iclass_xt_iclass_xsr_exccause_args, 4627 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, 4628 { 1, Iclass_xt_iclass_rsr_misc0_args, 4629 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, 4630 { 1, Iclass_xt_iclass_wsr_misc0_args, 4631 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, 4632 { 1, Iclass_xt_iclass_xsr_misc0_args, 4633 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, 4634 { 1, Iclass_xt_iclass_rsr_misc1_args, 4635 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, 4636 { 1, Iclass_xt_iclass_wsr_misc1_args, 4637 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, 4638 { 1, Iclass_xt_iclass_xsr_misc1_args, 4639 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, 4640 { 1, Iclass_xt_iclass_rsr_prid_args, 4641 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, 4642 { 1, Iclass_xt_iclass_rfi_args, 4643 15, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, 4644 { 1, Iclass_xt_iclass_wait_args, 4645 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, 4646 { 1, Iclass_xt_iclass_rsr_interrupt_args, 4647 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, 4648 { 1, Iclass_xt_iclass_wsr_intset_args, 4649 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, 4650 { 1, Iclass_xt_iclass_wsr_intclear_args, 4651 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, 4652 { 1, Iclass_xt_iclass_rsr_intenable_args, 4653 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, 4654 { 1, Iclass_xt_iclass_wsr_intenable_args, 4655 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, 4656 { 1, Iclass_xt_iclass_xsr_intenable_args, 4657 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, 4658 { 2, Iclass_xt_iclass_break_args, 4659 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, 4660 { 1, Iclass_xt_iclass_break_n_args, 4661 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, 4662 { 1, Iclass_xt_iclass_rsr_dbreaka0_args, 4663 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, 4664 { 1, Iclass_xt_iclass_wsr_dbreaka0_args, 4665 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, 4666 { 1, Iclass_xt_iclass_xsr_dbreaka0_args, 4667 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, 4668 { 1, Iclass_xt_iclass_rsr_dbreakc0_args, 4669 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, 4670 { 1, Iclass_xt_iclass_wsr_dbreakc0_args, 4671 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, 4672 { 1, Iclass_xt_iclass_xsr_dbreakc0_args, 4673 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, 4674 { 1, Iclass_xt_iclass_rsr_dbreaka1_args, 4675 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, 4676 { 1, Iclass_xt_iclass_wsr_dbreaka1_args, 4677 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, 4678 { 1, Iclass_xt_iclass_xsr_dbreaka1_args, 4679 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, 4680 { 1, Iclass_xt_iclass_rsr_dbreakc1_args, 4681 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, 4682 { 1, Iclass_xt_iclass_wsr_dbreakc1_args, 4683 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, 4684 { 1, Iclass_xt_iclass_xsr_dbreakc1_args, 4685 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, 4686 { 1, Iclass_xt_iclass_rsr_ibreaka0_args, 4687 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, 4688 { 1, Iclass_xt_iclass_wsr_ibreaka0_args, 4689 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, 4690 { 1, Iclass_xt_iclass_xsr_ibreaka0_args, 4691 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, 4692 { 1, Iclass_xt_iclass_rsr_ibreaka1_args, 4693 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, 4694 { 1, Iclass_xt_iclass_wsr_ibreaka1_args, 4695 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, 4696 { 1, Iclass_xt_iclass_xsr_ibreaka1_args, 4697 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, 4698 { 1, Iclass_xt_iclass_rsr_ibreakenable_args, 4699 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, 4700 { 1, Iclass_xt_iclass_wsr_ibreakenable_args, 4701 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, 4702 { 1, Iclass_xt_iclass_xsr_ibreakenable_args, 4703 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, 4704 { 1, Iclass_xt_iclass_rsr_debugcause_args, 4705 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, 4706 { 1, Iclass_xt_iclass_wsr_debugcause_args, 4707 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, 4708 { 1, Iclass_xt_iclass_xsr_debugcause_args, 4709 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, 4710 { 1, Iclass_xt_iclass_rsr_icount_args, 4711 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, 4712 { 1, Iclass_xt_iclass_wsr_icount_args, 4713 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, 4714 { 1, Iclass_xt_iclass_xsr_icount_args, 4715 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, 4716 { 1, Iclass_xt_iclass_rsr_icountlevel_args, 4717 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, 4718 { 1, Iclass_xt_iclass_wsr_icountlevel_args, 4719 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, 4720 { 1, Iclass_xt_iclass_xsr_icountlevel_args, 4721 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, 4722 { 1, Iclass_xt_iclass_rsr_ddr_args, 4723 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, 4724 { 1, Iclass_xt_iclass_wsr_ddr_args, 4725 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, 4726 { 1, Iclass_xt_iclass_xsr_ddr_args, 4727 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, 4728 { 0, 0 /* xt_iclass_rfdo */, 4729 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, 4730 { 0, 0 /* xt_iclass_rfdd */, 4731 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, 4732 { 1, Iclass_xt_iclass_rsr_ccount_args, 4733 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, 4734 { 1, Iclass_xt_iclass_wsr_ccount_args, 4735 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, 4736 { 1, Iclass_xt_iclass_xsr_ccount_args, 4737 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, 4738 { 1, Iclass_xt_iclass_rsr_ccompare0_args, 4739 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, 4740 { 1, Iclass_xt_iclass_wsr_ccompare0_args, 4741 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, 4742 { 1, Iclass_xt_iclass_xsr_ccompare0_args, 4743 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, 4744 { 1, Iclass_xt_iclass_rsr_ccompare1_args, 4745 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, 4746 { 1, Iclass_xt_iclass_wsr_ccompare1_args, 4747 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, 4748 { 1, Iclass_xt_iclass_xsr_ccompare1_args, 4749 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, 4750 { 1, Iclass_xt_iclass_rsr_ccompare2_args, 4751 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, 4752 { 1, Iclass_xt_iclass_wsr_ccompare2_args, 4753 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, 4754 { 1, Iclass_xt_iclass_xsr_ccompare2_args, 4755 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, 4756 { 2, Iclass_xt_iclass_icache_args, 4757 0, 0, 0, 0 }, 4758 { 2, Iclass_xt_iclass_icache_inv_args, 4759 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 }, 4760 { 2, Iclass_xt_iclass_licx_args, 4761 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 }, 4762 { 2, Iclass_xt_iclass_sicx_args, 4763 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 }, 4764 { 2, Iclass_xt_iclass_dcache_args, 4765 0, 0, 0, 0 }, 4766 { 2, Iclass_xt_iclass_dcache_ind_args, 4767 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 }, 4768 { 2, Iclass_xt_iclass_dcache_inv_args, 4769 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 }, 4770 { 2, Iclass_xt_iclass_dpf_args, 4771 0, 0, 0, 0 }, 4772 { 2, Iclass_xt_iclass_sdct_args, 4773 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 }, 4774 { 2, Iclass_xt_iclass_ldct_args, 4775 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 }, 4776 { 1, Iclass_xt_iclass_wsr_ptevaddr_args, 4777 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 }, 4778 { 1, Iclass_xt_iclass_rsr_ptevaddr_args, 4779 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 }, 4780 { 1, Iclass_xt_iclass_xsr_ptevaddr_args, 4781 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 }, 4782 { 1, Iclass_xt_iclass_rsr_rasid_args, 4783 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 }, 4784 { 1, Iclass_xt_iclass_wsr_rasid_args, 4785 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 }, 4786 { 1, Iclass_xt_iclass_xsr_rasid_args, 4787 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 }, 4788 { 1, Iclass_xt_iclass_rsr_itlbcfg_args, 4789 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 }, 4790 { 1, Iclass_xt_iclass_wsr_itlbcfg_args, 4791 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 }, 4792 { 1, Iclass_xt_iclass_xsr_itlbcfg_args, 4793 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 }, 4794 { 1, Iclass_xt_iclass_rsr_dtlbcfg_args, 4795 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 }, 4796 { 1, Iclass_xt_iclass_wsr_dtlbcfg_args, 4797 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 }, 4798 { 1, Iclass_xt_iclass_xsr_dtlbcfg_args, 4799 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 }, 4800 { 1, Iclass_xt_iclass_idtlb_args, 4801 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, 4802 { 2, Iclass_xt_iclass_rdtlb_args, 4803 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 }, 4804 { 2, Iclass_xt_iclass_wdtlb_args, 4805 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, 4806 { 1, Iclass_xt_iclass_iitlb_args, 4807 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 }, 4808 { 2, Iclass_xt_iclass_ritlb_args, 4809 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 }, 4810 { 2, Iclass_xt_iclass_witlb_args, 4811 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 }, 4812 { 0, 0 /* xt_iclass_ldpte */, 4813 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 }, 4814 { 0, 0 /* xt_iclass_hwwitlba */, 4815 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 }, 4816 { 0, 0 /* xt_iclass_hwwdtlba */, 4817 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 }, 4818 { 2, Iclass_xt_iclass_nsa_args, 4819 0, 0, 0, 0 } 4820 }; 4821 4822 4823 /* Opcode encodings. */ 4825 4826 static void 4827 Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) 4828 { 4829 slotbuf[0] = 0x80200; 4830 } 4831 4832 static void 4833 Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) 4834 { 4835 slotbuf[0] = 0x300; 4836 } 4837 4838 static void 4839 Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) 4840 { 4841 slotbuf[0] = 0x2300; 4842 } 4843 4844 static void 4845 Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) 4846 { 4847 slotbuf[0] = 0x500; 4848 } 4849 4850 static void 4851 Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) 4852 { 4853 slotbuf[0] = 0x1500; 4854 } 4855 4856 static void 4857 Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) 4858 { 4859 slotbuf[0] = 0x5c0000; 4860 } 4861 4862 static void 4863 Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) 4864 { 4865 slotbuf[0] = 0x580000; 4866 } 4867 4868 static void 4869 Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) 4870 { 4871 slotbuf[0] = 0x540000; 4872 } 4873 4874 static void 4875 Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) 4876 { 4877 slotbuf[0] = 0xf0000; 4878 } 4879 4880 static void 4881 Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) 4882 { 4883 slotbuf[0] = 0xb0000; 4884 } 4885 4886 static void 4887 Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) 4888 { 4889 slotbuf[0] = 0x70000; 4890 } 4891 4892 static void 4893 Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) 4894 { 4895 slotbuf[0] = 0x6c0000; 4896 } 4897 4898 static void 4899 Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) 4900 { 4901 slotbuf[0] = 0x100; 4902 } 4903 4904 static void 4905 Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) 4906 { 4907 slotbuf[0] = 0x804; 4908 } 4909 4910 static void 4911 Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) 4912 { 4913 slotbuf[0] = 0x60000; 4914 } 4915 4916 static void 4917 Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 4918 { 4919 slotbuf[0] = 0xd10f; 4920 } 4921 4922 static void 4923 Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) 4924 { 4925 slotbuf[0] = 0x4300; 4926 } 4927 4928 static void 4929 Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) 4930 { 4931 slotbuf[0] = 0x5300; 4932 } 4933 4934 static void 4935 Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) 4936 { 4937 slotbuf[0] = 0x90; 4938 } 4939 4940 static void 4941 Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) 4942 { 4943 slotbuf[0] = 0x94; 4944 } 4945 4946 static void 4947 Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 4948 { 4949 slotbuf[0] = 0x4830; 4950 } 4951 4952 static void 4953 Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 4954 { 4955 slotbuf[0] = 0x4831; 4956 } 4957 4958 static void 4959 Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 4960 { 4961 slotbuf[0] = 0x4816; 4962 } 4963 4964 static void 4965 Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) 4966 { 4967 slotbuf[0] = 0x4930; 4968 } 4969 4970 static void 4971 Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) 4972 { 4973 slotbuf[0] = 0x4931; 4974 } 4975 4976 static void 4977 Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) 4978 { 4979 slotbuf[0] = 0x4916; 4980 } 4981 4982 static void 4983 Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) 4984 { 4985 slotbuf[0] = 0xa000; 4986 } 4987 4988 static void 4989 Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) 4990 { 4991 slotbuf[0] = 0xb000; 4992 } 4993 4994 static void 4995 Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 4996 { 4997 slotbuf[0] = 0xc800; 4998 } 4999 5000 static void 5001 Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 5002 { 5003 slotbuf[0] = 0xcc00; 5004 } 5005 5006 static void 5007 Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 5008 { 5009 slotbuf[0] = 0xd60f; 5010 } 5011 5012 static void 5013 Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) 5014 { 5015 slotbuf[0] = 0x8000; 5016 } 5017 5018 static void 5019 Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 5020 { 5021 slotbuf[0] = 0xd000; 5022 } 5023 5024 static void 5025 Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 5026 { 5027 slotbuf[0] = 0xc000; 5028 } 5029 5030 static void 5031 Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 5032 { 5033 slotbuf[0] = 0xd30f; 5034 } 5035 5036 static void 5037 Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 5038 { 5039 slotbuf[0] = 0xd00f; 5040 } 5041 5042 static void 5043 Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) 5044 { 5045 slotbuf[0] = 0x9000; 5046 } 5047 5048 static void 5049 Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) 5050 { 5051 slotbuf[0] = 0x200c00; 5052 } 5053 5054 static void 5055 Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) 5056 { 5057 slotbuf[0] = 0x200d00; 5058 } 5059 5060 static void 5061 Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) 5062 { 5063 slotbuf[0] = 0x8; 5064 } 5065 5066 static void 5067 Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) 5068 { 5069 slotbuf[0] = 0xc; 5070 } 5071 5072 static void 5073 Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) 5074 { 5075 slotbuf[0] = 0x9; 5076 } 5077 5078 static void 5079 Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) 5080 { 5081 slotbuf[0] = 0xa; 5082 } 5083 5084 static void 5085 Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) 5086 { 5087 slotbuf[0] = 0xb; 5088 } 5089 5090 static void 5091 Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) 5092 { 5093 slotbuf[0] = 0xd; 5094 } 5095 5096 static void 5097 Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) 5098 { 5099 slotbuf[0] = 0xe; 5100 } 5101 5102 static void 5103 Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) 5104 { 5105 slotbuf[0] = 0xf; 5106 } 5107 5108 static void 5109 Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) 5110 { 5111 slotbuf[0] = 0x1; 5112 } 5113 5114 static void 5115 Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) 5116 { 5117 slotbuf[0] = 0x2; 5118 } 5119 5120 static void 5121 Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) 5122 { 5123 slotbuf[0] = 0x3; 5124 } 5125 5126 static void 5127 Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) 5128 { 5129 slotbuf[0] = 0x680000; 5130 } 5131 5132 static void 5133 Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) 5134 { 5135 slotbuf[0] = 0x690000; 5136 } 5137 5138 static void 5139 Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) 5140 { 5141 slotbuf[0] = 0x6b0000; 5142 } 5143 5144 static void 5145 Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) 5146 { 5147 slotbuf[0] = 0x6a0000; 5148 } 5149 5150 static void 5151 Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) 5152 { 5153 slotbuf[0] = 0x700600; 5154 } 5155 5156 static void 5157 Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) 5158 { 5159 slotbuf[0] = 0x700e00; 5160 } 5161 5162 static void 5163 Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) 5164 { 5165 slotbuf[0] = 0x6f0000; 5166 } 5167 5168 static void 5169 Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) 5170 { 5171 slotbuf[0] = 0x6e0000; 5172 } 5173 5174 static void 5175 Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) 5176 { 5177 slotbuf[0] = 0x700100; 5178 } 5179 5180 static void 5181 Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) 5182 { 5183 slotbuf[0] = 0x700900; 5184 } 5185 5186 static void 5187 Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) 5188 { 5189 slotbuf[0] = 0x700a00; 5190 } 5191 5192 static void 5193 Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) 5194 { 5195 slotbuf[0] = 0x700200; 5196 } 5197 5198 static void 5199 Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) 5200 { 5201 slotbuf[0] = 0x700b00; 5202 } 5203 5204 static void 5205 Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) 5206 { 5207 slotbuf[0] = 0x700300; 5208 } 5209 5210 static void 5211 Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) 5212 { 5213 slotbuf[0] = 0x700800; 5214 } 5215 5216 static void 5217 Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) 5218 { 5219 slotbuf[0] = 0x700000; 5220 } 5221 5222 static void 5223 Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) 5224 { 5225 slotbuf[0] = 0x700400; 5226 } 5227 5228 static void 5229 Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) 5230 { 5231 slotbuf[0] = 0x700c00; 5232 } 5233 5234 static void 5235 Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) 5236 { 5237 slotbuf[0] = 0x700500; 5238 } 5239 5240 static void 5241 Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) 5242 { 5243 slotbuf[0] = 0x700d00; 5244 } 5245 5246 static void 5247 Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) 5248 { 5249 slotbuf[0] = 0x640000; 5250 } 5251 5252 static void 5253 Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) 5254 { 5255 slotbuf[0] = 0x650000; 5256 } 5257 5258 static void 5259 Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) 5260 { 5261 slotbuf[0] = 0x670000; 5262 } 5263 5264 static void 5265 Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) 5266 { 5267 slotbuf[0] = 0x660000; 5268 } 5269 5270 static void 5271 Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) 5272 { 5273 slotbuf[0] = 0x500000; 5274 } 5275 5276 static void 5277 Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) 5278 { 5279 slotbuf[0] = 0x30000; 5280 } 5281 5282 static void 5283 Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) 5284 { 5285 slotbuf[0] = 0x40; 5286 } 5287 5288 static void 5289 Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) 5290 { 5291 slotbuf[0] = 0; 5292 } 5293 5294 static void 5295 Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) 5296 { 5297 slotbuf[0] = 0x600000; 5298 } 5299 5300 static void 5301 Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) 5302 { 5303 slotbuf[0] = 0xa0000; 5304 } 5305 5306 static void 5307 Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) 5308 { 5309 slotbuf[0] = 0x200100; 5310 } 5311 5312 static void 5313 Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) 5314 { 5315 slotbuf[0] = 0x200900; 5316 } 5317 5318 static void 5319 Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) 5320 { 5321 slotbuf[0] = 0x200200; 5322 } 5323 5324 static void 5325 Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) 5326 { 5327 slotbuf[0] = 0x100000; 5328 } 5329 5330 static void 5331 Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) 5332 { 5333 slotbuf[0] = 0x200000; 5334 } 5335 5336 static void 5337 Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) 5338 { 5339 slotbuf[0] = 0x6d0800; 5340 } 5341 5342 static void 5343 Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) 5344 { 5345 slotbuf[0] = 0x6d0900; 5346 } 5347 5348 static void 5349 Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) 5350 { 5351 slotbuf[0] = 0x6d0a00; 5352 } 5353 5354 static void 5355 Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) 5356 { 5357 slotbuf[0] = 0x200a00; 5358 } 5359 5360 static void 5361 Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) 5362 { 5363 slotbuf[0] = 0x38; 5364 } 5365 5366 static void 5367 Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) 5368 { 5369 slotbuf[0] = 0x39; 5370 } 5371 5372 static void 5373 Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) 5374 { 5375 slotbuf[0] = 0x3a; 5376 } 5377 5378 static void 5379 Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) 5380 { 5381 slotbuf[0] = 0x3b; 5382 } 5383 5384 static void 5385 Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) 5386 { 5387 slotbuf[0] = 0x6; 5388 } 5389 5390 static void 5391 Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) 5392 { 5393 slotbuf[0] = 0x1006; 5394 } 5395 5396 static void 5397 Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) 5398 { 5399 slotbuf[0] = 0xf0200; 5400 } 5401 5402 static void 5403 Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) 5404 { 5405 slotbuf[0] = 0x20000; 5406 } 5407 5408 static void 5409 Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) 5410 { 5411 slotbuf[0] = 0x200500; 5412 } 5413 5414 static void 5415 Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) 5416 { 5417 slotbuf[0] = 0x200600; 5418 } 5419 5420 static void 5421 Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) 5422 { 5423 slotbuf[0] = 0x200400; 5424 } 5425 5426 static void 5427 Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) 5428 { 5429 slotbuf[0] = 0x4; 5430 } 5431 5432 static void 5433 Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) 5434 { 5435 slotbuf[0] = 0x104; 5436 } 5437 5438 static void 5439 Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) 5440 { 5441 slotbuf[0] = 0x204; 5442 } 5443 5444 static void 5445 Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) 5446 { 5447 slotbuf[0] = 0x304; 5448 } 5449 5450 static void 5451 Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) 5452 { 5453 slotbuf[0] = 0x404; 5454 } 5455 5456 static void 5457 Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) 5458 { 5459 slotbuf[0] = 0x1a; 5460 } 5461 5462 static void 5463 Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) 5464 { 5465 slotbuf[0] = 0x18; 5466 } 5467 5468 static void 5469 Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) 5470 { 5471 slotbuf[0] = 0x19; 5472 } 5473 5474 static void 5475 Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) 5476 { 5477 slotbuf[0] = 0x1b; 5478 } 5479 5480 static void 5481 Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) 5482 { 5483 slotbuf[0] = 0x10; 5484 } 5485 5486 static void 5487 Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) 5488 { 5489 slotbuf[0] = 0x12; 5490 } 5491 5492 static void 5493 Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) 5494 { 5495 slotbuf[0] = 0x14; 5496 } 5497 5498 static void 5499 Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) 5500 { 5501 slotbuf[0] = 0xc0200; 5502 } 5503 5504 static void 5505 Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) 5506 { 5507 slotbuf[0] = 0xd0200; 5508 } 5509 5510 static void 5511 Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) 5512 { 5513 slotbuf[0] = 0x200; 5514 } 5515 5516 static void 5517 Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) 5518 { 5519 slotbuf[0] = 0x10200; 5520 } 5521 5522 static void 5523 Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) 5524 { 5525 slotbuf[0] = 0x20200; 5526 } 5527 5528 static void 5529 Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) 5530 { 5531 slotbuf[0] = 0x30200; 5532 } 5533 5534 static void 5535 Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) 5536 { 5537 slotbuf[0] = 0x600; 5538 } 5539 5540 static void 5541 Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) 5542 { 5543 slotbuf[0] = 0x130; 5544 } 5545 5546 static void 5547 Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) 5548 { 5549 slotbuf[0] = 0x131; 5550 } 5551 5552 static void 5553 Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) 5554 { 5555 slotbuf[0] = 0x116; 5556 } 5557 5558 static void 5559 Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) 5560 { 5561 slotbuf[0] = 0x230; 5562 } 5563 5564 static void 5565 Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) 5566 { 5567 slotbuf[0] = 0x231; 5568 } 5569 5570 static void 5571 Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) 5572 { 5573 slotbuf[0] = 0x216; 5574 } 5575 5576 static void 5577 Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) 5578 { 5579 slotbuf[0] = 0x30; 5580 } 5581 5582 static void 5583 Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) 5584 { 5585 slotbuf[0] = 0x31; 5586 } 5587 5588 static void 5589 Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) 5590 { 5591 slotbuf[0] = 0x16; 5592 } 5593 5594 static void 5595 Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) 5596 { 5597 slotbuf[0] = 0x330; 5598 } 5599 5600 static void 5601 Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) 5602 { 5603 slotbuf[0] = 0x331; 5604 } 5605 5606 static void 5607 Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) 5608 { 5609 slotbuf[0] = 0x316; 5610 } 5611 5612 static void 5613 Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 5614 { 5615 slotbuf[0] = 0x530; 5616 } 5617 5618 static void 5619 Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 5620 { 5621 slotbuf[0] = 0x531; 5622 } 5623 5624 static void 5625 Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 5626 { 5627 slotbuf[0] = 0x516; 5628 } 5629 5630 static void 5631 Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) 5632 { 5633 slotbuf[0] = 0xb030; 5634 } 5635 5636 static void 5637 Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf) 5638 { 5639 slotbuf[0] = 0xd030; 5640 } 5641 5642 static void 5643 Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) 5644 { 5645 slotbuf[0] = 0xe630; 5646 } 5647 5648 static void 5649 Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) 5650 { 5651 slotbuf[0] = 0xe631; 5652 } 5653 5654 static void 5655 Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) 5656 { 5657 slotbuf[0] = 0xe616; 5658 } 5659 5660 static void 5661 Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 5662 { 5663 slotbuf[0] = 0xb130; 5664 } 5665 5666 static void 5667 Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 5668 { 5669 slotbuf[0] = 0xb131; 5670 } 5671 5672 static void 5673 Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 5674 { 5675 slotbuf[0] = 0xb116; 5676 } 5677 5678 static void 5679 Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) 5680 { 5681 slotbuf[0] = 0xd130; 5682 } 5683 5684 static void 5685 Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) 5686 { 5687 slotbuf[0] = 0xd131; 5688 } 5689 5690 static void 5691 Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) 5692 { 5693 slotbuf[0] = 0xd116; 5694 } 5695 5696 static void 5697 Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) 5698 { 5699 slotbuf[0] = 0xb230; 5700 } 5701 5702 static void 5703 Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) 5704 { 5705 slotbuf[0] = 0xb231; 5706 } 5707 5708 static void 5709 Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) 5710 { 5711 slotbuf[0] = 0xb216; 5712 } 5713 5714 static void 5715 Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) 5716 { 5717 slotbuf[0] = 0xd230; 5718 } 5719 5720 static void 5721 Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) 5722 { 5723 slotbuf[0] = 0xd231; 5724 } 5725 5726 static void 5727 Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) 5728 { 5729 slotbuf[0] = 0xd216; 5730 } 5731 5732 static void 5733 Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) 5734 { 5735 slotbuf[0] = 0xb330; 5736 } 5737 5738 static void 5739 Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) 5740 { 5741 slotbuf[0] = 0xb331; 5742 } 5743 5744 static void 5745 Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) 5746 { 5747 slotbuf[0] = 0xb316; 5748 } 5749 5750 static void 5751 Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) 5752 { 5753 slotbuf[0] = 0xd330; 5754 } 5755 5756 static void 5757 Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) 5758 { 5759 slotbuf[0] = 0xd331; 5760 } 5761 5762 static void 5763 Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) 5764 { 5765 slotbuf[0] = 0xd316; 5766 } 5767 5768 static void 5769 Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) 5770 { 5771 slotbuf[0] = 0xb430; 5772 } 5773 5774 static void 5775 Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) 5776 { 5777 slotbuf[0] = 0xb431; 5778 } 5779 5780 static void 5781 Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) 5782 { 5783 slotbuf[0] = 0xb416; 5784 } 5785 5786 static void 5787 Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) 5788 { 5789 slotbuf[0] = 0xd430; 5790 } 5791 5792 static void 5793 Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) 5794 { 5795 slotbuf[0] = 0xd431; 5796 } 5797 5798 static void 5799 Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) 5800 { 5801 slotbuf[0] = 0xd416; 5802 } 5803 5804 static void 5805 Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) 5806 { 5807 slotbuf[0] = 0xc230; 5808 } 5809 5810 static void 5811 Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) 5812 { 5813 slotbuf[0] = 0xc231; 5814 } 5815 5816 static void 5817 Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) 5818 { 5819 slotbuf[0] = 0xc216; 5820 } 5821 5822 static void 5823 Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) 5824 { 5825 slotbuf[0] = 0xc330; 5826 } 5827 5828 static void 5829 Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) 5830 { 5831 slotbuf[0] = 0xc331; 5832 } 5833 5834 static void 5835 Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) 5836 { 5837 slotbuf[0] = 0xc316; 5838 } 5839 5840 static void 5841 Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) 5842 { 5843 slotbuf[0] = 0xc430; 5844 } 5845 5846 static void 5847 Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) 5848 { 5849 slotbuf[0] = 0xc431; 5850 } 5851 5852 static void 5853 Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) 5854 { 5855 slotbuf[0] = 0xc416; 5856 } 5857 5858 static void 5859 Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 5860 { 5861 slotbuf[0] = 0xee30; 5862 } 5863 5864 static void 5865 Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 5866 { 5867 slotbuf[0] = 0xee31; 5868 } 5869 5870 static void 5871 Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 5872 { 5873 slotbuf[0] = 0xee16; 5874 } 5875 5876 static void 5877 Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) 5878 { 5879 slotbuf[0] = 0xc030; 5880 } 5881 5882 static void 5883 Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) 5884 { 5885 slotbuf[0] = 0xc031; 5886 } 5887 5888 static void 5889 Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) 5890 { 5891 slotbuf[0] = 0xc016; 5892 } 5893 5894 static void 5895 Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) 5896 { 5897 slotbuf[0] = 0xe830; 5898 } 5899 5900 static void 5901 Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) 5902 { 5903 slotbuf[0] = 0xe831; 5904 } 5905 5906 static void 5907 Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) 5908 { 5909 slotbuf[0] = 0xe816; 5910 } 5911 5912 static void 5913 Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 5914 { 5915 slotbuf[0] = 0xf430; 5916 } 5917 5918 static void 5919 Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 5920 { 5921 slotbuf[0] = 0xf431; 5922 } 5923 5924 static void 5925 Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 5926 { 5927 slotbuf[0] = 0xf416; 5928 } 5929 5930 static void 5931 Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 5932 { 5933 slotbuf[0] = 0xf530; 5934 } 5935 5936 static void 5937 Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 5938 { 5939 slotbuf[0] = 0xf531; 5940 } 5941 5942 static void 5943 Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 5944 { 5945 slotbuf[0] = 0xf516; 5946 } 5947 5948 static void 5949 Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) 5950 { 5951 slotbuf[0] = 0xeb30; 5952 } 5953 5954 static void 5955 Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) 5956 { 5957 slotbuf[0] = 0x10300; 5958 } 5959 5960 static void 5961 Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) 5962 { 5963 slotbuf[0] = 0x700; 5964 } 5965 5966 static void 5967 Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) 5968 { 5969 slotbuf[0] = 0xe230; 5970 } 5971 5972 static void 5973 Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) 5974 { 5975 slotbuf[0] = 0xe231; 5976 } 5977 5978 static void 5979 Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) 5980 { 5981 slotbuf[0] = 0xe331; 5982 } 5983 5984 static void 5985 Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 5986 { 5987 slotbuf[0] = 0xe430; 5988 } 5989 5990 static void 5991 Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 5992 { 5993 slotbuf[0] = 0xe431; 5994 } 5995 5996 static void 5997 Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 5998 { 5999 slotbuf[0] = 0xe416; 6000 } 6001 6002 static void 6003 Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) 6004 { 6005 slotbuf[0] = 0x400; 6006 } 6007 6008 static void 6009 Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 6010 { 6011 slotbuf[0] = 0xd20f; 6012 } 6013 6014 static void 6015 Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 6016 { 6017 slotbuf[0] = 0x9030; 6018 } 6019 6020 static void 6021 Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 6022 { 6023 slotbuf[0] = 0x9031; 6024 } 6025 6026 static void 6027 Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 6028 { 6029 slotbuf[0] = 0x9016; 6030 } 6031 6032 static void 6033 Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 6034 { 6035 slotbuf[0] = 0xa030; 6036 } 6037 6038 static void 6039 Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 6040 { 6041 slotbuf[0] = 0xa031; 6042 } 6043 6044 static void 6045 Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 6046 { 6047 slotbuf[0] = 0xa016; 6048 } 6049 6050 static void 6051 Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 6052 { 6053 slotbuf[0] = 0x9130; 6054 } 6055 6056 static void 6057 Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 6058 { 6059 slotbuf[0] = 0x9131; 6060 } 6061 6062 static void 6063 Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 6064 { 6065 slotbuf[0] = 0x9116; 6066 } 6067 6068 static void 6069 Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 6070 { 6071 slotbuf[0] = 0xa130; 6072 } 6073 6074 static void 6075 Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 6076 { 6077 slotbuf[0] = 0xa131; 6078 } 6079 6080 static void 6081 Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 6082 { 6083 slotbuf[0] = 0xa116; 6084 } 6085 6086 static void 6087 Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 6088 { 6089 slotbuf[0] = 0x8030; 6090 } 6091 6092 static void 6093 Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 6094 { 6095 slotbuf[0] = 0x8031; 6096 } 6097 6098 static void 6099 Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 6100 { 6101 slotbuf[0] = 0x8016; 6102 } 6103 6104 static void 6105 Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 6106 { 6107 slotbuf[0] = 0x8130; 6108 } 6109 6110 static void 6111 Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 6112 { 6113 slotbuf[0] = 0x8131; 6114 } 6115 6116 static void 6117 Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 6118 { 6119 slotbuf[0] = 0x8116; 6120 } 6121 6122 static void 6123 Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 6124 { 6125 slotbuf[0] = 0x6030; 6126 } 6127 6128 static void 6129 Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 6130 { 6131 slotbuf[0] = 0x6031; 6132 } 6133 6134 static void 6135 Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 6136 { 6137 slotbuf[0] = 0x6016; 6138 } 6139 6140 static void 6141 Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) 6142 { 6143 slotbuf[0] = 0xe930; 6144 } 6145 6146 static void 6147 Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) 6148 { 6149 slotbuf[0] = 0xe931; 6150 } 6151 6152 static void 6153 Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) 6154 { 6155 slotbuf[0] = 0xe916; 6156 } 6157 6158 static void 6159 Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) 6160 { 6161 slotbuf[0] = 0xec30; 6162 } 6163 6164 static void 6165 Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) 6166 { 6167 slotbuf[0] = 0xec31; 6168 } 6169 6170 static void 6171 Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) 6172 { 6173 slotbuf[0] = 0xec16; 6174 } 6175 6176 static void 6177 Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) 6178 { 6179 slotbuf[0] = 0xed30; 6180 } 6181 6182 static void 6183 Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) 6184 { 6185 slotbuf[0] = 0xed31; 6186 } 6187 6188 static void 6189 Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) 6190 { 6191 slotbuf[0] = 0xed16; 6192 } 6193 6194 static void 6195 Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 6196 { 6197 slotbuf[0] = 0x6830; 6198 } 6199 6200 static void 6201 Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 6202 { 6203 slotbuf[0] = 0x6831; 6204 } 6205 6206 static void 6207 Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 6208 { 6209 slotbuf[0] = 0x6816; 6210 } 6211 6212 static void 6213 Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) 6214 { 6215 slotbuf[0] = 0xe1f; 6216 } 6217 6218 static void 6219 Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) 6220 { 6221 slotbuf[0] = 0x10e1f; 6222 } 6223 6224 static void 6225 Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) 6226 { 6227 slotbuf[0] = 0xea30; 6228 } 6229 6230 static void 6231 Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) 6232 { 6233 slotbuf[0] = 0xea31; 6234 } 6235 6236 static void 6237 Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) 6238 { 6239 slotbuf[0] = 0xea16; 6240 } 6241 6242 static void 6243 Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) 6244 { 6245 slotbuf[0] = 0xf030; 6246 } 6247 6248 static void 6249 Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) 6250 { 6251 slotbuf[0] = 0xf031; 6252 } 6253 6254 static void 6255 Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) 6256 { 6257 slotbuf[0] = 0xf016; 6258 } 6259 6260 static void 6261 Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) 6262 { 6263 slotbuf[0] = 0xf130; 6264 } 6265 6266 static void 6267 Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) 6268 { 6269 slotbuf[0] = 0xf131; 6270 } 6271 6272 static void 6273 Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) 6274 { 6275 slotbuf[0] = 0xf116; 6276 } 6277 6278 static void 6279 Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) 6280 { 6281 slotbuf[0] = 0xf230; 6282 } 6283 6284 static void 6285 Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) 6286 { 6287 slotbuf[0] = 0xf231; 6288 } 6289 6290 static void 6291 Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) 6292 { 6293 slotbuf[0] = 0xf216; 6294 } 6295 6296 static void 6297 Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) 6298 { 6299 slotbuf[0] = 0x2c0700; 6300 } 6301 6302 static void 6303 Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) 6304 { 6305 slotbuf[0] = 0x2e0700; 6306 } 6307 6308 static void 6309 Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) 6310 { 6311 slotbuf[0] = 0x2f0700; 6312 } 6313 6314 static void 6315 Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) 6316 { 6317 slotbuf[0] = 0x1f; 6318 } 6319 6320 static void 6321 Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) 6322 { 6323 slotbuf[0] = 0x21f; 6324 } 6325 6326 static void 6327 Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) 6328 { 6329 slotbuf[0] = 0x11f; 6330 } 6331 6332 static void 6333 Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) 6334 { 6335 slotbuf[0] = 0x31f; 6336 } 6337 6338 static void 6339 Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) 6340 { 6341 slotbuf[0] = 0x240700; 6342 } 6343 6344 static void 6345 Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) 6346 { 6347 slotbuf[0] = 0x250700; 6348 } 6349 6350 static void 6351 Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) 6352 { 6353 slotbuf[0] = 0x280740; 6354 } 6355 6356 static void 6357 Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) 6358 { 6359 slotbuf[0] = 0x280750; 6360 } 6361 6362 static void 6363 Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) 6364 { 6365 slotbuf[0] = 0x260700; 6366 } 6367 6368 static void 6369 Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) 6370 { 6371 slotbuf[0] = 0x270700; 6372 } 6373 6374 static void 6375 Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) 6376 { 6377 slotbuf[0] = 0x200700; 6378 } 6379 6380 static void 6381 Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) 6382 { 6383 slotbuf[0] = 0x210700; 6384 } 6385 6386 static void 6387 Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) 6388 { 6389 slotbuf[0] = 0x220700; 6390 } 6391 6392 static void 6393 Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) 6394 { 6395 slotbuf[0] = 0x230700; 6396 } 6397 6398 static void 6399 Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) 6400 { 6401 slotbuf[0] = 0x91f; 6402 } 6403 6404 static void 6405 Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) 6406 { 6407 slotbuf[0] = 0x81f; 6408 } 6409 6410 static void 6411 Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 6412 { 6413 slotbuf[0] = 0x5331; 6414 } 6415 6416 static void 6417 Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 6418 { 6419 slotbuf[0] = 0x5330; 6420 } 6421 6422 static void 6423 Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 6424 { 6425 slotbuf[0] = 0x5316; 6426 } 6427 6428 static void 6429 Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) 6430 { 6431 slotbuf[0] = 0x5a30; 6432 } 6433 6434 static void 6435 Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) 6436 { 6437 slotbuf[0] = 0x5a31; 6438 } 6439 6440 static void 6441 Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) 6442 { 6443 slotbuf[0] = 0x5a16; 6444 } 6445 6446 static void 6447 Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) 6448 { 6449 slotbuf[0] = 0x5b30; 6450 } 6451 6452 static void 6453 Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) 6454 { 6455 slotbuf[0] = 0x5b31; 6456 } 6457 6458 static void 6459 Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) 6460 { 6461 slotbuf[0] = 0x5b16; 6462 } 6463 6464 static void 6465 Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) 6466 { 6467 slotbuf[0] = 0x5c30; 6468 } 6469 6470 static void 6471 Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) 6472 { 6473 slotbuf[0] = 0x5c31; 6474 } 6475 6476 static void 6477 Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) 6478 { 6479 slotbuf[0] = 0x5c16; 6480 } 6481 6482 static void 6483 Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 6484 { 6485 slotbuf[0] = 0xc05; 6486 } 6487 6488 static void 6489 Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 6490 { 6491 slotbuf[0] = 0xd05; 6492 } 6493 6494 static void 6495 Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) 6496 { 6497 slotbuf[0] = 0xb05; 6498 } 6499 6500 static void 6501 Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) 6502 { 6503 slotbuf[0] = 0xf05; 6504 } 6505 6506 static void 6507 Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 6508 { 6509 slotbuf[0] = 0xe05; 6510 } 6511 6512 static void 6513 Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 6514 { 6515 slotbuf[0] = 0x405; 6516 } 6517 6518 static void 6519 Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 6520 { 6521 slotbuf[0] = 0x505; 6522 } 6523 6524 static void 6525 Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) 6526 { 6527 slotbuf[0] = 0x305; 6528 } 6529 6530 static void 6531 Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) 6532 { 6533 slotbuf[0] = 0x705; 6534 } 6535 6536 static void 6537 Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 6538 { 6539 slotbuf[0] = 0x605; 6540 } 6541 6542 static void 6543 Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf) 6544 { 6545 slotbuf[0] = 0xf1f; 6546 } 6547 6548 static void 6549 Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf) 6550 { 6551 slotbuf[0] = 0x105; 6552 } 6553 6554 static void 6555 Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf) 6556 { 6557 slotbuf[0] = 0x905; 6558 } 6559 6560 static void 6561 Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) 6562 { 6563 slotbuf[0] = 0xe04; 6564 } 6565 6566 static void 6567 Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) 6568 { 6569 slotbuf[0] = 0xf04; 6570 } 6571 6572 xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { 6573 Opcode_excw_Slot_inst_encode, 0, 0 6574 }; 6575 6576 xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { 6577 Opcode_rfe_Slot_inst_encode, 0, 0 6578 }; 6579 6580 xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { 6581 Opcode_rfde_Slot_inst_encode, 0, 0 6582 }; 6583 6584 xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { 6585 Opcode_syscall_Slot_inst_encode, 0, 0 6586 }; 6587 6588 xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { 6589 Opcode_simcall_Slot_inst_encode, 0, 0 6590 }; 6591 6592 xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { 6593 Opcode_call12_Slot_inst_encode, 0, 0 6594 }; 6595 6596 xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { 6597 Opcode_call8_Slot_inst_encode, 0, 0 6598 }; 6599 6600 xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { 6601 Opcode_call4_Slot_inst_encode, 0, 0 6602 }; 6603 6604 xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { 6605 Opcode_callx12_Slot_inst_encode, 0, 0 6606 }; 6607 6608 xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { 6609 Opcode_callx8_Slot_inst_encode, 0, 0 6610 }; 6611 6612 xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { 6613 Opcode_callx4_Slot_inst_encode, 0, 0 6614 }; 6615 6616 xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { 6617 Opcode_entry_Slot_inst_encode, 0, 0 6618 }; 6619 6620 xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { 6621 Opcode_movsp_Slot_inst_encode, 0, 0 6622 }; 6623 6624 xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { 6625 Opcode_rotw_Slot_inst_encode, 0, 0 6626 }; 6627 6628 xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { 6629 Opcode_retw_Slot_inst_encode, 0, 0 6630 }; 6631 6632 xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { 6633 0, 0, Opcode_retw_n_Slot_inst16b_encode 6634 }; 6635 6636 xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { 6637 Opcode_rfwo_Slot_inst_encode, 0, 0 6638 }; 6639 6640 xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { 6641 Opcode_rfwu_Slot_inst_encode, 0, 0 6642 }; 6643 6644 xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { 6645 Opcode_l32e_Slot_inst_encode, 0, 0 6646 }; 6647 6648 xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { 6649 Opcode_s32e_Slot_inst_encode, 0, 0 6650 }; 6651 6652 xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { 6653 Opcode_rsr_windowbase_Slot_inst_encode, 0, 0 6654 }; 6655 6656 xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { 6657 Opcode_wsr_windowbase_Slot_inst_encode, 0, 0 6658 }; 6659 6660 xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { 6661 Opcode_xsr_windowbase_Slot_inst_encode, 0, 0 6662 }; 6663 6664 xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { 6665 Opcode_rsr_windowstart_Slot_inst_encode, 0, 0 6666 }; 6667 6668 xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { 6669 Opcode_wsr_windowstart_Slot_inst_encode, 0, 0 6670 }; 6671 6672 xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { 6673 Opcode_xsr_windowstart_Slot_inst_encode, 0, 0 6674 }; 6675 6676 xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { 6677 0, Opcode_add_n_Slot_inst16a_encode, 0 6678 }; 6679 6680 xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { 6681 0, Opcode_addi_n_Slot_inst16a_encode, 0 6682 }; 6683 6684 xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { 6685 0, 0, Opcode_beqz_n_Slot_inst16b_encode 6686 }; 6687 6688 xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { 6689 0, 0, Opcode_bnez_n_Slot_inst16b_encode 6690 }; 6691 6692 xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { 6693 0, 0, Opcode_ill_n_Slot_inst16b_encode 6694 }; 6695 6696 xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { 6697 0, Opcode_l32i_n_Slot_inst16a_encode, 0 6698 }; 6699 6700 xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { 6701 0, 0, Opcode_mov_n_Slot_inst16b_encode 6702 }; 6703 6704 xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { 6705 0, 0, Opcode_movi_n_Slot_inst16b_encode 6706 }; 6707 6708 xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { 6709 0, 0, Opcode_nop_n_Slot_inst16b_encode 6710 }; 6711 6712 xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { 6713 0, 0, Opcode_ret_n_Slot_inst16b_encode 6714 }; 6715 6716 xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { 6717 0, Opcode_s32i_n_Slot_inst16a_encode, 0 6718 }; 6719 6720 xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { 6721 Opcode_addi_Slot_inst_encode, 0, 0 6722 }; 6723 6724 xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { 6725 Opcode_addmi_Slot_inst_encode, 0, 0 6726 }; 6727 6728 xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { 6729 Opcode_add_Slot_inst_encode, 0, 0 6730 }; 6731 6732 xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { 6733 Opcode_sub_Slot_inst_encode, 0, 0 6734 }; 6735 6736 xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { 6737 Opcode_addx2_Slot_inst_encode, 0, 0 6738 }; 6739 6740 xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { 6741 Opcode_addx4_Slot_inst_encode, 0, 0 6742 }; 6743 6744 xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { 6745 Opcode_addx8_Slot_inst_encode, 0, 0 6746 }; 6747 6748 xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { 6749 Opcode_subx2_Slot_inst_encode, 0, 0 6750 }; 6751 6752 xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { 6753 Opcode_subx4_Slot_inst_encode, 0, 0 6754 }; 6755 6756 xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { 6757 Opcode_subx8_Slot_inst_encode, 0, 0 6758 }; 6759 6760 xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { 6761 Opcode_and_Slot_inst_encode, 0, 0 6762 }; 6763 6764 xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { 6765 Opcode_or_Slot_inst_encode, 0, 0 6766 }; 6767 6768 xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { 6769 Opcode_xor_Slot_inst_encode, 0, 0 6770 }; 6771 6772 xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { 6773 Opcode_beqi_Slot_inst_encode, 0, 0 6774 }; 6775 6776 xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { 6777 Opcode_bnei_Slot_inst_encode, 0, 0 6778 }; 6779 6780 xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { 6781 Opcode_bgei_Slot_inst_encode, 0, 0 6782 }; 6783 6784 xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { 6785 Opcode_blti_Slot_inst_encode, 0, 0 6786 }; 6787 6788 xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { 6789 Opcode_bbci_Slot_inst_encode, 0, 0 6790 }; 6791 6792 xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { 6793 Opcode_bbsi_Slot_inst_encode, 0, 0 6794 }; 6795 6796 xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { 6797 Opcode_bgeui_Slot_inst_encode, 0, 0 6798 }; 6799 6800 xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { 6801 Opcode_bltui_Slot_inst_encode, 0, 0 6802 }; 6803 6804 xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { 6805 Opcode_beq_Slot_inst_encode, 0, 0 6806 }; 6807 6808 xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { 6809 Opcode_bne_Slot_inst_encode, 0, 0 6810 }; 6811 6812 xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { 6813 Opcode_bge_Slot_inst_encode, 0, 0 6814 }; 6815 6816 xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { 6817 Opcode_blt_Slot_inst_encode, 0, 0 6818 }; 6819 6820 xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { 6821 Opcode_bgeu_Slot_inst_encode, 0, 0 6822 }; 6823 6824 xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { 6825 Opcode_bltu_Slot_inst_encode, 0, 0 6826 }; 6827 6828 xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { 6829 Opcode_bany_Slot_inst_encode, 0, 0 6830 }; 6831 6832 xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { 6833 Opcode_bnone_Slot_inst_encode, 0, 0 6834 }; 6835 6836 xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { 6837 Opcode_ball_Slot_inst_encode, 0, 0 6838 }; 6839 6840 xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { 6841 Opcode_bnall_Slot_inst_encode, 0, 0 6842 }; 6843 6844 xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { 6845 Opcode_bbc_Slot_inst_encode, 0, 0 6846 }; 6847 6848 xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { 6849 Opcode_bbs_Slot_inst_encode, 0, 0 6850 }; 6851 6852 xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { 6853 Opcode_beqz_Slot_inst_encode, 0, 0 6854 }; 6855 6856 xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { 6857 Opcode_bnez_Slot_inst_encode, 0, 0 6858 }; 6859 6860 xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { 6861 Opcode_bgez_Slot_inst_encode, 0, 0 6862 }; 6863 6864 xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { 6865 Opcode_bltz_Slot_inst_encode, 0, 0 6866 }; 6867 6868 xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { 6869 Opcode_call0_Slot_inst_encode, 0, 0 6870 }; 6871 6872 xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { 6873 Opcode_callx0_Slot_inst_encode, 0, 0 6874 }; 6875 6876 xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { 6877 Opcode_extui_Slot_inst_encode, 0, 0 6878 }; 6879 6880 xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { 6881 Opcode_ill_Slot_inst_encode, 0, 0 6882 }; 6883 6884 xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { 6885 Opcode_j_Slot_inst_encode, 0, 0 6886 }; 6887 6888 xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { 6889 Opcode_jx_Slot_inst_encode, 0, 0 6890 }; 6891 6892 xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { 6893 Opcode_l16ui_Slot_inst_encode, 0, 0 6894 }; 6895 6896 xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { 6897 Opcode_l16si_Slot_inst_encode, 0, 0 6898 }; 6899 6900 xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { 6901 Opcode_l32i_Slot_inst_encode, 0, 0 6902 }; 6903 6904 xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { 6905 Opcode_l32r_Slot_inst_encode, 0, 0 6906 }; 6907 6908 xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { 6909 Opcode_l8ui_Slot_inst_encode, 0, 0 6910 }; 6911 6912 xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { 6913 Opcode_loop_Slot_inst_encode, 0, 0 6914 }; 6915 6916 xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { 6917 Opcode_loopnez_Slot_inst_encode, 0, 0 6918 }; 6919 6920 xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { 6921 Opcode_loopgtz_Slot_inst_encode, 0, 0 6922 }; 6923 6924 xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { 6925 Opcode_movi_Slot_inst_encode, 0, 0 6926 }; 6927 6928 xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { 6929 Opcode_moveqz_Slot_inst_encode, 0, 0 6930 }; 6931 6932 xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { 6933 Opcode_movnez_Slot_inst_encode, 0, 0 6934 }; 6935 6936 xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { 6937 Opcode_movltz_Slot_inst_encode, 0, 0 6938 }; 6939 6940 xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { 6941 Opcode_movgez_Slot_inst_encode, 0, 0 6942 }; 6943 6944 xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { 6945 Opcode_neg_Slot_inst_encode, 0, 0 6946 }; 6947 6948 xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { 6949 Opcode_abs_Slot_inst_encode, 0, 0 6950 }; 6951 6952 xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { 6953 Opcode_nop_Slot_inst_encode, 0, 0 6954 }; 6955 6956 xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { 6957 Opcode_ret_Slot_inst_encode, 0, 0 6958 }; 6959 6960 xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { 6961 Opcode_s16i_Slot_inst_encode, 0, 0 6962 }; 6963 6964 xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { 6965 Opcode_s32i_Slot_inst_encode, 0, 0 6966 }; 6967 6968 xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { 6969 Opcode_s8i_Slot_inst_encode, 0, 0 6970 }; 6971 6972 xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { 6973 Opcode_ssr_Slot_inst_encode, 0, 0 6974 }; 6975 6976 xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { 6977 Opcode_ssl_Slot_inst_encode, 0, 0 6978 }; 6979 6980 xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { 6981 Opcode_ssa8l_Slot_inst_encode, 0, 0 6982 }; 6983 6984 xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { 6985 Opcode_ssa8b_Slot_inst_encode, 0, 0 6986 }; 6987 6988 xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { 6989 Opcode_ssai_Slot_inst_encode, 0, 0 6990 }; 6991 6992 xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { 6993 Opcode_sll_Slot_inst_encode, 0, 0 6994 }; 6995 6996 xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { 6997 Opcode_src_Slot_inst_encode, 0, 0 6998 }; 6999 7000 xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { 7001 Opcode_srl_Slot_inst_encode, 0, 0 7002 }; 7003 7004 xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { 7005 Opcode_sra_Slot_inst_encode, 0, 0 7006 }; 7007 7008 xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { 7009 Opcode_slli_Slot_inst_encode, 0, 0 7010 }; 7011 7012 xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { 7013 Opcode_srai_Slot_inst_encode, 0, 0 7014 }; 7015 7016 xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { 7017 Opcode_srli_Slot_inst_encode, 0, 0 7018 }; 7019 7020 xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { 7021 Opcode_memw_Slot_inst_encode, 0, 0 7022 }; 7023 7024 xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { 7025 Opcode_extw_Slot_inst_encode, 0, 0 7026 }; 7027 7028 xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { 7029 Opcode_isync_Slot_inst_encode, 0, 0 7030 }; 7031 7032 xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { 7033 Opcode_rsync_Slot_inst_encode, 0, 0 7034 }; 7035 7036 xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { 7037 Opcode_esync_Slot_inst_encode, 0, 0 7038 }; 7039 7040 xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { 7041 Opcode_dsync_Slot_inst_encode, 0, 0 7042 }; 7043 7044 xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { 7045 Opcode_rsil_Slot_inst_encode, 0, 0 7046 }; 7047 7048 xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { 7049 Opcode_rsr_lend_Slot_inst_encode, 0, 0 7050 }; 7051 7052 xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { 7053 Opcode_wsr_lend_Slot_inst_encode, 0, 0 7054 }; 7055 7056 xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { 7057 Opcode_xsr_lend_Slot_inst_encode, 0, 0 7058 }; 7059 7060 xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { 7061 Opcode_rsr_lcount_Slot_inst_encode, 0, 0 7062 }; 7063 7064 xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { 7065 Opcode_wsr_lcount_Slot_inst_encode, 0, 0 7066 }; 7067 7068 xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { 7069 Opcode_xsr_lcount_Slot_inst_encode, 0, 0 7070 }; 7071 7072 xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { 7073 Opcode_rsr_lbeg_Slot_inst_encode, 0, 0 7074 }; 7075 7076 xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { 7077 Opcode_wsr_lbeg_Slot_inst_encode, 0, 0 7078 }; 7079 7080 xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { 7081 Opcode_xsr_lbeg_Slot_inst_encode, 0, 0 7082 }; 7083 7084 xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { 7085 Opcode_rsr_sar_Slot_inst_encode, 0, 0 7086 }; 7087 7088 xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { 7089 Opcode_wsr_sar_Slot_inst_encode, 0, 0 7090 }; 7091 7092 xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { 7093 Opcode_xsr_sar_Slot_inst_encode, 0, 0 7094 }; 7095 7096 xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { 7097 Opcode_rsr_litbase_Slot_inst_encode, 0, 0 7098 }; 7099 7100 xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { 7101 Opcode_wsr_litbase_Slot_inst_encode, 0, 0 7102 }; 7103 7104 xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { 7105 Opcode_xsr_litbase_Slot_inst_encode, 0, 0 7106 }; 7107 7108 xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = { 7109 Opcode_rsr_176_Slot_inst_encode, 0, 0 7110 }; 7111 7112 xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = { 7113 Opcode_rsr_208_Slot_inst_encode, 0, 0 7114 }; 7115 7116 xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { 7117 Opcode_rsr_ps_Slot_inst_encode, 0, 0 7118 }; 7119 7120 xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { 7121 Opcode_wsr_ps_Slot_inst_encode, 0, 0 7122 }; 7123 7124 xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { 7125 Opcode_xsr_ps_Slot_inst_encode, 0, 0 7126 }; 7127 7128 xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { 7129 Opcode_rsr_epc1_Slot_inst_encode, 0, 0 7130 }; 7131 7132 xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { 7133 Opcode_wsr_epc1_Slot_inst_encode, 0, 0 7134 }; 7135 7136 xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { 7137 Opcode_xsr_epc1_Slot_inst_encode, 0, 0 7138 }; 7139 7140 xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { 7141 Opcode_rsr_excsave1_Slot_inst_encode, 0, 0 7142 }; 7143 7144 xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { 7145 Opcode_wsr_excsave1_Slot_inst_encode, 0, 0 7146 }; 7147 7148 xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { 7149 Opcode_xsr_excsave1_Slot_inst_encode, 0, 0 7150 }; 7151 7152 xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { 7153 Opcode_rsr_epc2_Slot_inst_encode, 0, 0 7154 }; 7155 7156 xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { 7157 Opcode_wsr_epc2_Slot_inst_encode, 0, 0 7158 }; 7159 7160 xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { 7161 Opcode_xsr_epc2_Slot_inst_encode, 0, 0 7162 }; 7163 7164 xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { 7165 Opcode_rsr_excsave2_Slot_inst_encode, 0, 0 7166 }; 7167 7168 xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { 7169 Opcode_wsr_excsave2_Slot_inst_encode, 0, 0 7170 }; 7171 7172 xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { 7173 Opcode_xsr_excsave2_Slot_inst_encode, 0, 0 7174 }; 7175 7176 xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { 7177 Opcode_rsr_epc3_Slot_inst_encode, 0, 0 7178 }; 7179 7180 xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { 7181 Opcode_wsr_epc3_Slot_inst_encode, 0, 0 7182 }; 7183 7184 xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { 7185 Opcode_xsr_epc3_Slot_inst_encode, 0, 0 7186 }; 7187 7188 xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { 7189 Opcode_rsr_excsave3_Slot_inst_encode, 0, 0 7190 }; 7191 7192 xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { 7193 Opcode_wsr_excsave3_Slot_inst_encode, 0, 0 7194 }; 7195 7196 xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { 7197 Opcode_xsr_excsave3_Slot_inst_encode, 0, 0 7198 }; 7199 7200 xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { 7201 Opcode_rsr_epc4_Slot_inst_encode, 0, 0 7202 }; 7203 7204 xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { 7205 Opcode_wsr_epc4_Slot_inst_encode, 0, 0 7206 }; 7207 7208 xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { 7209 Opcode_xsr_epc4_Slot_inst_encode, 0, 0 7210 }; 7211 7212 xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { 7213 Opcode_rsr_excsave4_Slot_inst_encode, 0, 0 7214 }; 7215 7216 xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { 7217 Opcode_wsr_excsave4_Slot_inst_encode, 0, 0 7218 }; 7219 7220 xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { 7221 Opcode_xsr_excsave4_Slot_inst_encode, 0, 0 7222 }; 7223 7224 xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { 7225 Opcode_rsr_eps2_Slot_inst_encode, 0, 0 7226 }; 7227 7228 xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { 7229 Opcode_wsr_eps2_Slot_inst_encode, 0, 0 7230 }; 7231 7232 xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { 7233 Opcode_xsr_eps2_Slot_inst_encode, 0, 0 7234 }; 7235 7236 xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { 7237 Opcode_rsr_eps3_Slot_inst_encode, 0, 0 7238 }; 7239 7240 xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { 7241 Opcode_wsr_eps3_Slot_inst_encode, 0, 0 7242 }; 7243 7244 xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { 7245 Opcode_xsr_eps3_Slot_inst_encode, 0, 0 7246 }; 7247 7248 xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { 7249 Opcode_rsr_eps4_Slot_inst_encode, 0, 0 7250 }; 7251 7252 xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { 7253 Opcode_wsr_eps4_Slot_inst_encode, 0, 0 7254 }; 7255 7256 xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { 7257 Opcode_xsr_eps4_Slot_inst_encode, 0, 0 7258 }; 7259 7260 xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { 7261 Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0 7262 }; 7263 7264 xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { 7265 Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0 7266 }; 7267 7268 xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { 7269 Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0 7270 }; 7271 7272 xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { 7273 Opcode_rsr_depc_Slot_inst_encode, 0, 0 7274 }; 7275 7276 xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { 7277 Opcode_wsr_depc_Slot_inst_encode, 0, 0 7278 }; 7279 7280 xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { 7281 Opcode_xsr_depc_Slot_inst_encode, 0, 0 7282 }; 7283 7284 xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { 7285 Opcode_rsr_exccause_Slot_inst_encode, 0, 0 7286 }; 7287 7288 xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { 7289 Opcode_wsr_exccause_Slot_inst_encode, 0, 0 7290 }; 7291 7292 xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { 7293 Opcode_xsr_exccause_Slot_inst_encode, 0, 0 7294 }; 7295 7296 xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { 7297 Opcode_rsr_misc0_Slot_inst_encode, 0, 0 7298 }; 7299 7300 xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { 7301 Opcode_wsr_misc0_Slot_inst_encode, 0, 0 7302 }; 7303 7304 xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { 7305 Opcode_xsr_misc0_Slot_inst_encode, 0, 0 7306 }; 7307 7308 xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { 7309 Opcode_rsr_misc1_Slot_inst_encode, 0, 0 7310 }; 7311 7312 xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { 7313 Opcode_wsr_misc1_Slot_inst_encode, 0, 0 7314 }; 7315 7316 xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { 7317 Opcode_xsr_misc1_Slot_inst_encode, 0, 0 7318 }; 7319 7320 xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { 7321 Opcode_rsr_prid_Slot_inst_encode, 0, 0 7322 }; 7323 7324 xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { 7325 Opcode_rfi_Slot_inst_encode, 0, 0 7326 }; 7327 7328 xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { 7329 Opcode_waiti_Slot_inst_encode, 0, 0 7330 }; 7331 7332 xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { 7333 Opcode_rsr_interrupt_Slot_inst_encode, 0, 0 7334 }; 7335 7336 xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { 7337 Opcode_wsr_intset_Slot_inst_encode, 0, 0 7338 }; 7339 7340 xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { 7341 Opcode_wsr_intclear_Slot_inst_encode, 0, 0 7342 }; 7343 7344 xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { 7345 Opcode_rsr_intenable_Slot_inst_encode, 0, 0 7346 }; 7347 7348 xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { 7349 Opcode_wsr_intenable_Slot_inst_encode, 0, 0 7350 }; 7351 7352 xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { 7353 Opcode_xsr_intenable_Slot_inst_encode, 0, 0 7354 }; 7355 7356 xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { 7357 Opcode_break_Slot_inst_encode, 0, 0 7358 }; 7359 7360 xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { 7361 0, 0, Opcode_break_n_Slot_inst16b_encode 7362 }; 7363 7364 xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { 7365 Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0 7366 }; 7367 7368 xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { 7369 Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0 7370 }; 7371 7372 xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { 7373 Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0 7374 }; 7375 7376 xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { 7377 Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0 7378 }; 7379 7380 xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { 7381 Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0 7382 }; 7383 7384 xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { 7385 Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0 7386 }; 7387 7388 xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { 7389 Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0 7390 }; 7391 7392 xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { 7393 Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0 7394 }; 7395 7396 xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { 7397 Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0 7398 }; 7399 7400 xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { 7401 Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0 7402 }; 7403 7404 xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { 7405 Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0 7406 }; 7407 7408 xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { 7409 Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0 7410 }; 7411 7412 xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { 7413 Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0 7414 }; 7415 7416 xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { 7417 Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0 7418 }; 7419 7420 xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { 7421 Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0 7422 }; 7423 7424 xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { 7425 Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0 7426 }; 7427 7428 xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { 7429 Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0 7430 }; 7431 7432 xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { 7433 Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0 7434 }; 7435 7436 xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { 7437 Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0 7438 }; 7439 7440 xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { 7441 Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0 7442 }; 7443 7444 xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { 7445 Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0 7446 }; 7447 7448 xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { 7449 Opcode_rsr_debugcause_Slot_inst_encode, 0, 0 7450 }; 7451 7452 xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { 7453 Opcode_wsr_debugcause_Slot_inst_encode, 0, 0 7454 }; 7455 7456 xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { 7457 Opcode_xsr_debugcause_Slot_inst_encode, 0, 0 7458 }; 7459 7460 xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { 7461 Opcode_rsr_icount_Slot_inst_encode, 0, 0 7462 }; 7463 7464 xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { 7465 Opcode_wsr_icount_Slot_inst_encode, 0, 0 7466 }; 7467 7468 xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { 7469 Opcode_xsr_icount_Slot_inst_encode, 0, 0 7470 }; 7471 7472 xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { 7473 Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0 7474 }; 7475 7476 xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { 7477 Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0 7478 }; 7479 7480 xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { 7481 Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0 7482 }; 7483 7484 xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { 7485 Opcode_rsr_ddr_Slot_inst_encode, 0, 0 7486 }; 7487 7488 xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { 7489 Opcode_wsr_ddr_Slot_inst_encode, 0, 0 7490 }; 7491 7492 xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { 7493 Opcode_xsr_ddr_Slot_inst_encode, 0, 0 7494 }; 7495 7496 xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { 7497 Opcode_rfdo_Slot_inst_encode, 0, 0 7498 }; 7499 7500 xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { 7501 Opcode_rfdd_Slot_inst_encode, 0, 0 7502 }; 7503 7504 xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { 7505 Opcode_rsr_ccount_Slot_inst_encode, 0, 0 7506 }; 7507 7508 xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { 7509 Opcode_wsr_ccount_Slot_inst_encode, 0, 0 7510 }; 7511 7512 xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { 7513 Opcode_xsr_ccount_Slot_inst_encode, 0, 0 7514 }; 7515 7516 xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { 7517 Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0 7518 }; 7519 7520 xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { 7521 Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0 7522 }; 7523 7524 xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { 7525 Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0 7526 }; 7527 7528 xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { 7529 Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0 7530 }; 7531 7532 xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { 7533 Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0 7534 }; 7535 7536 xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { 7537 Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0 7538 }; 7539 7540 xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { 7541 Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0 7542 }; 7543 7544 xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { 7545 Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0 7546 }; 7547 7548 xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { 7549 Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0 7550 }; 7551 7552 xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { 7553 Opcode_ipf_Slot_inst_encode, 0, 0 7554 }; 7555 7556 xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { 7557 Opcode_ihi_Slot_inst_encode, 0, 0 7558 }; 7559 7560 xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { 7561 Opcode_iii_Slot_inst_encode, 0, 0 7562 }; 7563 7564 xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { 7565 Opcode_lict_Slot_inst_encode, 0, 0 7566 }; 7567 7568 xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { 7569 Opcode_licw_Slot_inst_encode, 0, 0 7570 }; 7571 7572 xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { 7573 Opcode_sict_Slot_inst_encode, 0, 0 7574 }; 7575 7576 xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { 7577 Opcode_sicw_Slot_inst_encode, 0, 0 7578 }; 7579 7580 xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { 7581 Opcode_dhwb_Slot_inst_encode, 0, 0 7582 }; 7583 7584 xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { 7585 Opcode_dhwbi_Slot_inst_encode, 0, 0 7586 }; 7587 7588 xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { 7589 Opcode_diwb_Slot_inst_encode, 0, 0 7590 }; 7591 7592 xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { 7593 Opcode_diwbi_Slot_inst_encode, 0, 0 7594 }; 7595 7596 xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { 7597 Opcode_dhi_Slot_inst_encode, 0, 0 7598 }; 7599 7600 xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { 7601 Opcode_dii_Slot_inst_encode, 0, 0 7602 }; 7603 7604 xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { 7605 Opcode_dpfr_Slot_inst_encode, 0, 0 7606 }; 7607 7608 xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { 7609 Opcode_dpfw_Slot_inst_encode, 0, 0 7610 }; 7611 7612 xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { 7613 Opcode_dpfro_Slot_inst_encode, 0, 0 7614 }; 7615 7616 xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { 7617 Opcode_dpfwo_Slot_inst_encode, 0, 0 7618 }; 7619 7620 xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { 7621 Opcode_sdct_Slot_inst_encode, 0, 0 7622 }; 7623 7624 xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { 7625 Opcode_ldct_Slot_inst_encode, 0, 0 7626 }; 7627 7628 xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = { 7629 Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0 7630 }; 7631 7632 xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = { 7633 Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0 7634 }; 7635 7636 xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = { 7637 Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0 7638 }; 7639 7640 xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = { 7641 Opcode_rsr_rasid_Slot_inst_encode, 0, 0 7642 }; 7643 7644 xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = { 7645 Opcode_wsr_rasid_Slot_inst_encode, 0, 0 7646 }; 7647 7648 xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = { 7649 Opcode_xsr_rasid_Slot_inst_encode, 0, 0 7650 }; 7651 7652 xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = { 7653 Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0 7654 }; 7655 7656 xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = { 7657 Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0 7658 }; 7659 7660 xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = { 7661 Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0 7662 }; 7663 7664 xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = { 7665 Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0 7666 }; 7667 7668 xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = { 7669 Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0 7670 }; 7671 7672 xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = { 7673 Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0 7674 }; 7675 7676 xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { 7677 Opcode_idtlb_Slot_inst_encode, 0, 0 7678 }; 7679 7680 xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { 7681 Opcode_pdtlb_Slot_inst_encode, 0, 0 7682 }; 7683 7684 xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { 7685 Opcode_rdtlb0_Slot_inst_encode, 0, 0 7686 }; 7687 7688 xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { 7689 Opcode_rdtlb1_Slot_inst_encode, 0, 0 7690 }; 7691 7692 xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { 7693 Opcode_wdtlb_Slot_inst_encode, 0, 0 7694 }; 7695 7696 xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { 7697 Opcode_iitlb_Slot_inst_encode, 0, 0 7698 }; 7699 7700 xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { 7701 Opcode_pitlb_Slot_inst_encode, 0, 0 7702 }; 7703 7704 xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { 7705 Opcode_ritlb0_Slot_inst_encode, 0, 0 7706 }; 7707 7708 xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { 7709 Opcode_ritlb1_Slot_inst_encode, 0, 0 7710 }; 7711 7712 xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { 7713 Opcode_witlb_Slot_inst_encode, 0, 0 7714 }; 7715 7716 xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = { 7717 Opcode_ldpte_Slot_inst_encode, 0, 0 7718 }; 7719 7720 xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = { 7721 Opcode_hwwitlba_Slot_inst_encode, 0, 0 7722 }; 7723 7724 xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = { 7725 Opcode_hwwdtlba_Slot_inst_encode, 0, 0 7726 }; 7727 7728 xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { 7729 Opcode_nsa_Slot_inst_encode, 0, 0 7730 }; 7731 7732 xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { 7733 Opcode_nsau_Slot_inst_encode, 0, 0 7734 }; 7735 7736 7737 /* Opcode table. */ 7739 7740 static xtensa_opcode_internal opcodes[] = { 7741 { "excw", 0 /* xt_iclass_excw */, 7742 0, 7743 Opcode_excw_encode_fns, 0, 0 }, 7744 { "rfe", 1 /* xt_iclass_rfe */, 7745 XTENSA_OPCODE_IS_JUMP, 7746 Opcode_rfe_encode_fns, 0, 0 }, 7747 { "rfde", 2 /* xt_iclass_rfde */, 7748 XTENSA_OPCODE_IS_JUMP, 7749 Opcode_rfde_encode_fns, 0, 0 }, 7750 { "syscall", 3 /* xt_iclass_syscall */, 7751 0, 7752 Opcode_syscall_encode_fns, 0, 0 }, 7753 { "simcall", 4 /* xt_iclass_simcall */, 7754 0, 7755 Opcode_simcall_encode_fns, 0, 0 }, 7756 { "call12", 5 /* xt_iclass_call12 */, 7757 XTENSA_OPCODE_IS_CALL, 7758 Opcode_call12_encode_fns, 0, 0 }, 7759 { "call8", 6 /* xt_iclass_call8 */, 7760 XTENSA_OPCODE_IS_CALL, 7761 Opcode_call8_encode_fns, 0, 0 }, 7762 { "call4", 7 /* xt_iclass_call4 */, 7763 XTENSA_OPCODE_IS_CALL, 7764 Opcode_call4_encode_fns, 0, 0 }, 7765 { "callx12", 8 /* xt_iclass_callx12 */, 7766 XTENSA_OPCODE_IS_CALL, 7767 Opcode_callx12_encode_fns, 0, 0 }, 7768 { "callx8", 9 /* xt_iclass_callx8 */, 7769 XTENSA_OPCODE_IS_CALL, 7770 Opcode_callx8_encode_fns, 0, 0 }, 7771 { "callx4", 10 /* xt_iclass_callx4 */, 7772 XTENSA_OPCODE_IS_CALL, 7773 Opcode_callx4_encode_fns, 0, 0 }, 7774 { "entry", 11 /* xt_iclass_entry */, 7775 0, 7776 Opcode_entry_encode_fns, 0, 0 }, 7777 { "movsp", 12 /* xt_iclass_movsp */, 7778 0, 7779 Opcode_movsp_encode_fns, 0, 0 }, 7780 { "rotw", 13 /* xt_iclass_rotw */, 7781 0, 7782 Opcode_rotw_encode_fns, 0, 0 }, 7783 { "retw", 14 /* xt_iclass_retw */, 7784 XTENSA_OPCODE_IS_JUMP, 7785 Opcode_retw_encode_fns, 0, 0 }, 7786 { "retw.n", 14 /* xt_iclass_retw */, 7787 XTENSA_OPCODE_IS_JUMP, 7788 Opcode_retw_n_encode_fns, 0, 0 }, 7789 { "rfwo", 15 /* xt_iclass_rfwou */, 7790 XTENSA_OPCODE_IS_JUMP, 7791 Opcode_rfwo_encode_fns, 0, 0 }, 7792 { "rfwu", 15 /* xt_iclass_rfwou */, 7793 XTENSA_OPCODE_IS_JUMP, 7794 Opcode_rfwu_encode_fns, 0, 0 }, 7795 { "l32e", 16 /* xt_iclass_l32e */, 7796 0, 7797 Opcode_l32e_encode_fns, 0, 0 }, 7798 { "s32e", 17 /* xt_iclass_s32e */, 7799 0, 7800 Opcode_s32e_encode_fns, 0, 0 }, 7801 { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */, 7802 0, 7803 Opcode_rsr_windowbase_encode_fns, 0, 0 }, 7804 { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */, 7805 0, 7806 Opcode_wsr_windowbase_encode_fns, 0, 0 }, 7807 { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */, 7808 0, 7809 Opcode_xsr_windowbase_encode_fns, 0, 0 }, 7810 { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */, 7811 0, 7812 Opcode_rsr_windowstart_encode_fns, 0, 0 }, 7813 { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */, 7814 0, 7815 Opcode_wsr_windowstart_encode_fns, 0, 0 }, 7816 { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */, 7817 0, 7818 Opcode_xsr_windowstart_encode_fns, 0, 0 }, 7819 { "add.n", 24 /* xt_iclass_add.n */, 7820 0, 7821 Opcode_add_n_encode_fns, 0, 0 }, 7822 { "addi.n", 25 /* xt_iclass_addi.n */, 7823 0, 7824 Opcode_addi_n_encode_fns, 0, 0 }, 7825 { "beqz.n", 26 /* xt_iclass_bz6 */, 7826 XTENSA_OPCODE_IS_BRANCH, 7827 Opcode_beqz_n_encode_fns, 0, 0 }, 7828 { "bnez.n", 26 /* xt_iclass_bz6 */, 7829 XTENSA_OPCODE_IS_BRANCH, 7830 Opcode_bnez_n_encode_fns, 0, 0 }, 7831 { "ill.n", 27 /* xt_iclass_ill.n */, 7832 0, 7833 Opcode_ill_n_encode_fns, 0, 0 }, 7834 { "l32i.n", 28 /* xt_iclass_loadi4 */, 7835 0, 7836 Opcode_l32i_n_encode_fns, 0, 0 }, 7837 { "mov.n", 29 /* xt_iclass_mov.n */, 7838 0, 7839 Opcode_mov_n_encode_fns, 0, 0 }, 7840 { "movi.n", 30 /* xt_iclass_movi.n */, 7841 0, 7842 Opcode_movi_n_encode_fns, 0, 0 }, 7843 { "nop.n", 31 /* xt_iclass_nopn */, 7844 0, 7845 Opcode_nop_n_encode_fns, 0, 0 }, 7846 { "ret.n", 32 /* xt_iclass_retn */, 7847 XTENSA_OPCODE_IS_JUMP, 7848 Opcode_ret_n_encode_fns, 0, 0 }, 7849 { "s32i.n", 33 /* xt_iclass_storei4 */, 7850 0, 7851 Opcode_s32i_n_encode_fns, 0, 0 }, 7852 { "addi", 34 /* xt_iclass_addi */, 7853 0, 7854 Opcode_addi_encode_fns, 0, 0 }, 7855 { "addmi", 35 /* xt_iclass_addmi */, 7856 0, 7857 Opcode_addmi_encode_fns, 0, 0 }, 7858 { "add", 36 /* xt_iclass_addsub */, 7859 0, 7860 Opcode_add_encode_fns, 0, 0 }, 7861 { "sub", 36 /* xt_iclass_addsub */, 7862 0, 7863 Opcode_sub_encode_fns, 0, 0 }, 7864 { "addx2", 36 /* xt_iclass_addsub */, 7865 0, 7866 Opcode_addx2_encode_fns, 0, 0 }, 7867 { "addx4", 36 /* xt_iclass_addsub */, 7868 0, 7869 Opcode_addx4_encode_fns, 0, 0 }, 7870 { "addx8", 36 /* xt_iclass_addsub */, 7871 0, 7872 Opcode_addx8_encode_fns, 0, 0 }, 7873 { "subx2", 36 /* xt_iclass_addsub */, 7874 0, 7875 Opcode_subx2_encode_fns, 0, 0 }, 7876 { "subx4", 36 /* xt_iclass_addsub */, 7877 0, 7878 Opcode_subx4_encode_fns, 0, 0 }, 7879 { "subx8", 36 /* xt_iclass_addsub */, 7880 0, 7881 Opcode_subx8_encode_fns, 0, 0 }, 7882 { "and", 37 /* xt_iclass_bit */, 7883 0, 7884 Opcode_and_encode_fns, 0, 0 }, 7885 { "or", 37 /* xt_iclass_bit */, 7886 0, 7887 Opcode_or_encode_fns, 0, 0 }, 7888 { "xor", 37 /* xt_iclass_bit */, 7889 0, 7890 Opcode_xor_encode_fns, 0, 0 }, 7891 { "beqi", 38 /* xt_iclass_bsi8 */, 7892 XTENSA_OPCODE_IS_BRANCH, 7893 Opcode_beqi_encode_fns, 0, 0 }, 7894 { "bnei", 38 /* xt_iclass_bsi8 */, 7895 XTENSA_OPCODE_IS_BRANCH, 7896 Opcode_bnei_encode_fns, 0, 0 }, 7897 { "bgei", 38 /* xt_iclass_bsi8 */, 7898 XTENSA_OPCODE_IS_BRANCH, 7899 Opcode_bgei_encode_fns, 0, 0 }, 7900 { "blti", 38 /* xt_iclass_bsi8 */, 7901 XTENSA_OPCODE_IS_BRANCH, 7902 Opcode_blti_encode_fns, 0, 0 }, 7903 { "bbci", 39 /* xt_iclass_bsi8b */, 7904 XTENSA_OPCODE_IS_BRANCH, 7905 Opcode_bbci_encode_fns, 0, 0 }, 7906 { "bbsi", 39 /* xt_iclass_bsi8b */, 7907 XTENSA_OPCODE_IS_BRANCH, 7908 Opcode_bbsi_encode_fns, 0, 0 }, 7909 { "bgeui", 40 /* xt_iclass_bsi8u */, 7910 XTENSA_OPCODE_IS_BRANCH, 7911 Opcode_bgeui_encode_fns, 0, 0 }, 7912 { "bltui", 40 /* xt_iclass_bsi8u */, 7913 XTENSA_OPCODE_IS_BRANCH, 7914 Opcode_bltui_encode_fns, 0, 0 }, 7915 { "beq", 41 /* xt_iclass_bst8 */, 7916 XTENSA_OPCODE_IS_BRANCH, 7917 Opcode_beq_encode_fns, 0, 0 }, 7918 { "bne", 41 /* xt_iclass_bst8 */, 7919 XTENSA_OPCODE_IS_BRANCH, 7920 Opcode_bne_encode_fns, 0, 0 }, 7921 { "bge", 41 /* xt_iclass_bst8 */, 7922 XTENSA_OPCODE_IS_BRANCH, 7923 Opcode_bge_encode_fns, 0, 0 }, 7924 { "blt", 41 /* xt_iclass_bst8 */, 7925 XTENSA_OPCODE_IS_BRANCH, 7926 Opcode_blt_encode_fns, 0, 0 }, 7927 { "bgeu", 41 /* xt_iclass_bst8 */, 7928 XTENSA_OPCODE_IS_BRANCH, 7929 Opcode_bgeu_encode_fns, 0, 0 }, 7930 { "bltu", 41 /* xt_iclass_bst8 */, 7931 XTENSA_OPCODE_IS_BRANCH, 7932 Opcode_bltu_encode_fns, 0, 0 }, 7933 { "bany", 41 /* xt_iclass_bst8 */, 7934 XTENSA_OPCODE_IS_BRANCH, 7935 Opcode_bany_encode_fns, 0, 0 }, 7936 { "bnone", 41 /* xt_iclass_bst8 */, 7937 XTENSA_OPCODE_IS_BRANCH, 7938 Opcode_bnone_encode_fns, 0, 0 }, 7939 { "ball", 41 /* xt_iclass_bst8 */, 7940 XTENSA_OPCODE_IS_BRANCH, 7941 Opcode_ball_encode_fns, 0, 0 }, 7942 { "bnall", 41 /* xt_iclass_bst8 */, 7943 XTENSA_OPCODE_IS_BRANCH, 7944 Opcode_bnall_encode_fns, 0, 0 }, 7945 { "bbc", 41 /* xt_iclass_bst8 */, 7946 XTENSA_OPCODE_IS_BRANCH, 7947 Opcode_bbc_encode_fns, 0, 0 }, 7948 { "bbs", 41 /* xt_iclass_bst8 */, 7949 XTENSA_OPCODE_IS_BRANCH, 7950 Opcode_bbs_encode_fns, 0, 0 }, 7951 { "beqz", 42 /* xt_iclass_bsz12 */, 7952 XTENSA_OPCODE_IS_BRANCH, 7953 Opcode_beqz_encode_fns, 0, 0 }, 7954 { "bnez", 42 /* xt_iclass_bsz12 */, 7955 XTENSA_OPCODE_IS_BRANCH, 7956 Opcode_bnez_encode_fns, 0, 0 }, 7957 { "bgez", 42 /* xt_iclass_bsz12 */, 7958 XTENSA_OPCODE_IS_BRANCH, 7959 Opcode_bgez_encode_fns, 0, 0 }, 7960 { "bltz", 42 /* xt_iclass_bsz12 */, 7961 XTENSA_OPCODE_IS_BRANCH, 7962 Opcode_bltz_encode_fns, 0, 0 }, 7963 { "call0", 43 /* xt_iclass_call0 */, 7964 XTENSA_OPCODE_IS_CALL, 7965 Opcode_call0_encode_fns, 0, 0 }, 7966 { "callx0", 44 /* xt_iclass_callx0 */, 7967 XTENSA_OPCODE_IS_CALL, 7968 Opcode_callx0_encode_fns, 0, 0 }, 7969 { "extui", 45 /* xt_iclass_exti */, 7970 0, 7971 Opcode_extui_encode_fns, 0, 0 }, 7972 { "ill", 46 /* xt_iclass_ill */, 7973 0, 7974 Opcode_ill_encode_fns, 0, 0 }, 7975 { "j", 47 /* xt_iclass_jump */, 7976 XTENSA_OPCODE_IS_JUMP, 7977 Opcode_j_encode_fns, 0, 0 }, 7978 { "jx", 48 /* xt_iclass_jumpx */, 7979 XTENSA_OPCODE_IS_JUMP, 7980 Opcode_jx_encode_fns, 0, 0 }, 7981 { "l16ui", 49 /* xt_iclass_l16ui */, 7982 0, 7983 Opcode_l16ui_encode_fns, 0, 0 }, 7984 { "l16si", 50 /* xt_iclass_l16si */, 7985 0, 7986 Opcode_l16si_encode_fns, 0, 0 }, 7987 { "l32i", 51 /* xt_iclass_l32i */, 7988 0, 7989 Opcode_l32i_encode_fns, 0, 0 }, 7990 { "l32r", 52 /* xt_iclass_l32r */, 7991 0, 7992 Opcode_l32r_encode_fns, 0, 0 }, 7993 { "l8ui", 53 /* xt_iclass_l8i */, 7994 0, 7995 Opcode_l8ui_encode_fns, 0, 0 }, 7996 { "loop", 54 /* xt_iclass_loop */, 7997 XTENSA_OPCODE_IS_LOOP, 7998 Opcode_loop_encode_fns, 0, 0 }, 7999 { "loopnez", 55 /* xt_iclass_loopz */, 8000 XTENSA_OPCODE_IS_LOOP, 8001 Opcode_loopnez_encode_fns, 0, 0 }, 8002 { "loopgtz", 55 /* xt_iclass_loopz */, 8003 XTENSA_OPCODE_IS_LOOP, 8004 Opcode_loopgtz_encode_fns, 0, 0 }, 8005 { "movi", 56 /* xt_iclass_movi */, 8006 0, 8007 Opcode_movi_encode_fns, 0, 0 }, 8008 { "moveqz", 57 /* xt_iclass_movz */, 8009 0, 8010 Opcode_moveqz_encode_fns, 0, 0 }, 8011 { "movnez", 57 /* xt_iclass_movz */, 8012 0, 8013 Opcode_movnez_encode_fns, 0, 0 }, 8014 { "movltz", 57 /* xt_iclass_movz */, 8015 0, 8016 Opcode_movltz_encode_fns, 0, 0 }, 8017 { "movgez", 57 /* xt_iclass_movz */, 8018 0, 8019 Opcode_movgez_encode_fns, 0, 0 }, 8020 { "neg", 58 /* xt_iclass_neg */, 8021 0, 8022 Opcode_neg_encode_fns, 0, 0 }, 8023 { "abs", 58 /* xt_iclass_neg */, 8024 0, 8025 Opcode_abs_encode_fns, 0, 0 }, 8026 { "nop", 59 /* xt_iclass_nop */, 8027 0, 8028 Opcode_nop_encode_fns, 0, 0 }, 8029 { "ret", 60 /* xt_iclass_return */, 8030 XTENSA_OPCODE_IS_JUMP, 8031 Opcode_ret_encode_fns, 0, 0 }, 8032 { "s16i", 61 /* xt_iclass_s16i */, 8033 0, 8034 Opcode_s16i_encode_fns, 0, 0 }, 8035 { "s32i", 62 /* xt_iclass_s32i */, 8036 0, 8037 Opcode_s32i_encode_fns, 0, 0 }, 8038 { "s8i", 63 /* xt_iclass_s8i */, 8039 0, 8040 Opcode_s8i_encode_fns, 0, 0 }, 8041 { "ssr", 64 /* xt_iclass_sar */, 8042 0, 8043 Opcode_ssr_encode_fns, 0, 0 }, 8044 { "ssl", 64 /* xt_iclass_sar */, 8045 0, 8046 Opcode_ssl_encode_fns, 0, 0 }, 8047 { "ssa8l", 64 /* xt_iclass_sar */, 8048 0, 8049 Opcode_ssa8l_encode_fns, 0, 0 }, 8050 { "ssa8b", 64 /* xt_iclass_sar */, 8051 0, 8052 Opcode_ssa8b_encode_fns, 0, 0 }, 8053 { "ssai", 65 /* xt_iclass_sari */, 8054 0, 8055 Opcode_ssai_encode_fns, 0, 0 }, 8056 { "sll", 66 /* xt_iclass_shifts */, 8057 0, 8058 Opcode_sll_encode_fns, 0, 0 }, 8059 { "src", 67 /* xt_iclass_shiftst */, 8060 0, 8061 Opcode_src_encode_fns, 0, 0 }, 8062 { "srl", 68 /* xt_iclass_shiftt */, 8063 0, 8064 Opcode_srl_encode_fns, 0, 0 }, 8065 { "sra", 68 /* xt_iclass_shiftt */, 8066 0, 8067 Opcode_sra_encode_fns, 0, 0 }, 8068 { "slli", 69 /* xt_iclass_slli */, 8069 0, 8070 Opcode_slli_encode_fns, 0, 0 }, 8071 { "srai", 70 /* xt_iclass_srai */, 8072 0, 8073 Opcode_srai_encode_fns, 0, 0 }, 8074 { "srli", 71 /* xt_iclass_srli */, 8075 0, 8076 Opcode_srli_encode_fns, 0, 0 }, 8077 { "memw", 72 /* xt_iclass_memw */, 8078 0, 8079 Opcode_memw_encode_fns, 0, 0 }, 8080 { "extw", 73 /* xt_iclass_extw */, 8081 0, 8082 Opcode_extw_encode_fns, 0, 0 }, 8083 { "isync", 74 /* xt_iclass_isync */, 8084 0, 8085 Opcode_isync_encode_fns, 0, 0 }, 8086 { "rsync", 75 /* xt_iclass_sync */, 8087 0, 8088 Opcode_rsync_encode_fns, 0, 0 }, 8089 { "esync", 75 /* xt_iclass_sync */, 8090 0, 8091 Opcode_esync_encode_fns, 0, 0 }, 8092 { "dsync", 75 /* xt_iclass_sync */, 8093 0, 8094 Opcode_dsync_encode_fns, 0, 0 }, 8095 { "rsil", 76 /* xt_iclass_rsil */, 8096 0, 8097 Opcode_rsil_encode_fns, 0, 0 }, 8098 { "rsr.lend", 77 /* xt_iclass_rsr.lend */, 8099 0, 8100 Opcode_rsr_lend_encode_fns, 0, 0 }, 8101 { "wsr.lend", 78 /* xt_iclass_wsr.lend */, 8102 0, 8103 Opcode_wsr_lend_encode_fns, 0, 0 }, 8104 { "xsr.lend", 79 /* xt_iclass_xsr.lend */, 8105 0, 8106 Opcode_xsr_lend_encode_fns, 0, 0 }, 8107 { "rsr.lcount", 80 /* xt_iclass_rsr.lcount */, 8108 0, 8109 Opcode_rsr_lcount_encode_fns, 0, 0 }, 8110 { "wsr.lcount", 81 /* xt_iclass_wsr.lcount */, 8111 0, 8112 Opcode_wsr_lcount_encode_fns, 0, 0 }, 8113 { "xsr.lcount", 82 /* xt_iclass_xsr.lcount */, 8114 0, 8115 Opcode_xsr_lcount_encode_fns, 0, 0 }, 8116 { "rsr.lbeg", 83 /* xt_iclass_rsr.lbeg */, 8117 0, 8118 Opcode_rsr_lbeg_encode_fns, 0, 0 }, 8119 { "wsr.lbeg", 84 /* xt_iclass_wsr.lbeg */, 8120 0, 8121 Opcode_wsr_lbeg_encode_fns, 0, 0 }, 8122 { "xsr.lbeg", 85 /* xt_iclass_xsr.lbeg */, 8123 0, 8124 Opcode_xsr_lbeg_encode_fns, 0, 0 }, 8125 { "rsr.sar", 86 /* xt_iclass_rsr.sar */, 8126 0, 8127 Opcode_rsr_sar_encode_fns, 0, 0 }, 8128 { "wsr.sar", 87 /* xt_iclass_wsr.sar */, 8129 0, 8130 Opcode_wsr_sar_encode_fns, 0, 0 }, 8131 { "xsr.sar", 88 /* xt_iclass_xsr.sar */, 8132 0, 8133 Opcode_xsr_sar_encode_fns, 0, 0 }, 8134 { "rsr.litbase", 89 /* xt_iclass_rsr.litbase */, 8135 0, 8136 Opcode_rsr_litbase_encode_fns, 0, 0 }, 8137 { "wsr.litbase", 90 /* xt_iclass_wsr.litbase */, 8138 0, 8139 Opcode_wsr_litbase_encode_fns, 0, 0 }, 8140 { "xsr.litbase", 91 /* xt_iclass_xsr.litbase */, 8141 0, 8142 Opcode_xsr_litbase_encode_fns, 0, 0 }, 8143 { "rsr.176", 92 /* xt_iclass_rsr.176 */, 8144 0, 8145 Opcode_rsr_176_encode_fns, 0, 0 }, 8146 { "rsr.208", 93 /* xt_iclass_rsr.208 */, 8147 0, 8148 Opcode_rsr_208_encode_fns, 0, 0 }, 8149 { "rsr.ps", 94 /* xt_iclass_rsr.ps */, 8150 0, 8151 Opcode_rsr_ps_encode_fns, 0, 0 }, 8152 { "wsr.ps", 95 /* xt_iclass_wsr.ps */, 8153 0, 8154 Opcode_wsr_ps_encode_fns, 0, 0 }, 8155 { "xsr.ps", 96 /* xt_iclass_xsr.ps */, 8156 0, 8157 Opcode_xsr_ps_encode_fns, 0, 0 }, 8158 { "rsr.epc1", 97 /* xt_iclass_rsr.epc1 */, 8159 0, 8160 Opcode_rsr_epc1_encode_fns, 0, 0 }, 8161 { "wsr.epc1", 98 /* xt_iclass_wsr.epc1 */, 8162 0, 8163 Opcode_wsr_epc1_encode_fns, 0, 0 }, 8164 { "xsr.epc1", 99 /* xt_iclass_xsr.epc1 */, 8165 0, 8166 Opcode_xsr_epc1_encode_fns, 0, 0 }, 8167 { "rsr.excsave1", 100 /* xt_iclass_rsr.excsave1 */, 8168 0, 8169 Opcode_rsr_excsave1_encode_fns, 0, 0 }, 8170 { "wsr.excsave1", 101 /* xt_iclass_wsr.excsave1 */, 8171 0, 8172 Opcode_wsr_excsave1_encode_fns, 0, 0 }, 8173 { "xsr.excsave1", 102 /* xt_iclass_xsr.excsave1 */, 8174 0, 8175 Opcode_xsr_excsave1_encode_fns, 0, 0 }, 8176 { "rsr.epc2", 103 /* xt_iclass_rsr.epc2 */, 8177 0, 8178 Opcode_rsr_epc2_encode_fns, 0, 0 }, 8179 { "wsr.epc2", 104 /* xt_iclass_wsr.epc2 */, 8180 0, 8181 Opcode_wsr_epc2_encode_fns, 0, 0 }, 8182 { "xsr.epc2", 105 /* xt_iclass_xsr.epc2 */, 8183 0, 8184 Opcode_xsr_epc2_encode_fns, 0, 0 }, 8185 { "rsr.excsave2", 106 /* xt_iclass_rsr.excsave2 */, 8186 0, 8187 Opcode_rsr_excsave2_encode_fns, 0, 0 }, 8188 { "wsr.excsave2", 107 /* xt_iclass_wsr.excsave2 */, 8189 0, 8190 Opcode_wsr_excsave2_encode_fns, 0, 0 }, 8191 { "xsr.excsave2", 108 /* xt_iclass_xsr.excsave2 */, 8192 0, 8193 Opcode_xsr_excsave2_encode_fns, 0, 0 }, 8194 { "rsr.epc3", 109 /* xt_iclass_rsr.epc3 */, 8195 0, 8196 Opcode_rsr_epc3_encode_fns, 0, 0 }, 8197 { "wsr.epc3", 110 /* xt_iclass_wsr.epc3 */, 8198 0, 8199 Opcode_wsr_epc3_encode_fns, 0, 0 }, 8200 { "xsr.epc3", 111 /* xt_iclass_xsr.epc3 */, 8201 0, 8202 Opcode_xsr_epc3_encode_fns, 0, 0 }, 8203 { "rsr.excsave3", 112 /* xt_iclass_rsr.excsave3 */, 8204 0, 8205 Opcode_rsr_excsave3_encode_fns, 0, 0 }, 8206 { "wsr.excsave3", 113 /* xt_iclass_wsr.excsave3 */, 8207 0, 8208 Opcode_wsr_excsave3_encode_fns, 0, 0 }, 8209 { "xsr.excsave3", 114 /* xt_iclass_xsr.excsave3 */, 8210 0, 8211 Opcode_xsr_excsave3_encode_fns, 0, 0 }, 8212 { "rsr.epc4", 115 /* xt_iclass_rsr.epc4 */, 8213 0, 8214 Opcode_rsr_epc4_encode_fns, 0, 0 }, 8215 { "wsr.epc4", 116 /* xt_iclass_wsr.epc4 */, 8216 0, 8217 Opcode_wsr_epc4_encode_fns, 0, 0 }, 8218 { "xsr.epc4", 117 /* xt_iclass_xsr.epc4 */, 8219 0, 8220 Opcode_xsr_epc4_encode_fns, 0, 0 }, 8221 { "rsr.excsave4", 118 /* xt_iclass_rsr.excsave4 */, 8222 0, 8223 Opcode_rsr_excsave4_encode_fns, 0, 0 }, 8224 { "wsr.excsave4", 119 /* xt_iclass_wsr.excsave4 */, 8225 0, 8226 Opcode_wsr_excsave4_encode_fns, 0, 0 }, 8227 { "xsr.excsave4", 120 /* xt_iclass_xsr.excsave4 */, 8228 0, 8229 Opcode_xsr_excsave4_encode_fns, 0, 0 }, 8230 { "rsr.eps2", 121 /* xt_iclass_rsr.eps2 */, 8231 0, 8232 Opcode_rsr_eps2_encode_fns, 0, 0 }, 8233 { "wsr.eps2", 122 /* xt_iclass_wsr.eps2 */, 8234 0, 8235 Opcode_wsr_eps2_encode_fns, 0, 0 }, 8236 { "xsr.eps2", 123 /* xt_iclass_xsr.eps2 */, 8237 0, 8238 Opcode_xsr_eps2_encode_fns, 0, 0 }, 8239 { "rsr.eps3", 124 /* xt_iclass_rsr.eps3 */, 8240 0, 8241 Opcode_rsr_eps3_encode_fns, 0, 0 }, 8242 { "wsr.eps3", 125 /* xt_iclass_wsr.eps3 */, 8243 0, 8244 Opcode_wsr_eps3_encode_fns, 0, 0 }, 8245 { "xsr.eps3", 126 /* xt_iclass_xsr.eps3 */, 8246 0, 8247 Opcode_xsr_eps3_encode_fns, 0, 0 }, 8248 { "rsr.eps4", 127 /* xt_iclass_rsr.eps4 */, 8249 0, 8250 Opcode_rsr_eps4_encode_fns, 0, 0 }, 8251 { "wsr.eps4", 128 /* xt_iclass_wsr.eps4 */, 8252 0, 8253 Opcode_wsr_eps4_encode_fns, 0, 0 }, 8254 { "xsr.eps4", 129 /* xt_iclass_xsr.eps4 */, 8255 0, 8256 Opcode_xsr_eps4_encode_fns, 0, 0 }, 8257 { "rsr.excvaddr", 130 /* xt_iclass_rsr.excvaddr */, 8258 0, 8259 Opcode_rsr_excvaddr_encode_fns, 0, 0 }, 8260 { "wsr.excvaddr", 131 /* xt_iclass_wsr.excvaddr */, 8261 0, 8262 Opcode_wsr_excvaddr_encode_fns, 0, 0 }, 8263 { "xsr.excvaddr", 132 /* xt_iclass_xsr.excvaddr */, 8264 0, 8265 Opcode_xsr_excvaddr_encode_fns, 0, 0 }, 8266 { "rsr.depc", 133 /* xt_iclass_rsr.depc */, 8267 0, 8268 Opcode_rsr_depc_encode_fns, 0, 0 }, 8269 { "wsr.depc", 134 /* xt_iclass_wsr.depc */, 8270 0, 8271 Opcode_wsr_depc_encode_fns, 0, 0 }, 8272 { "xsr.depc", 135 /* xt_iclass_xsr.depc */, 8273 0, 8274 Opcode_xsr_depc_encode_fns, 0, 0 }, 8275 { "rsr.exccause", 136 /* xt_iclass_rsr.exccause */, 8276 0, 8277 Opcode_rsr_exccause_encode_fns, 0, 0 }, 8278 { "wsr.exccause", 137 /* xt_iclass_wsr.exccause */, 8279 0, 8280 Opcode_wsr_exccause_encode_fns, 0, 0 }, 8281 { "xsr.exccause", 138 /* xt_iclass_xsr.exccause */, 8282 0, 8283 Opcode_xsr_exccause_encode_fns, 0, 0 }, 8284 { "rsr.misc0", 139 /* xt_iclass_rsr.misc0 */, 8285 0, 8286 Opcode_rsr_misc0_encode_fns, 0, 0 }, 8287 { "wsr.misc0", 140 /* xt_iclass_wsr.misc0 */, 8288 0, 8289 Opcode_wsr_misc0_encode_fns, 0, 0 }, 8290 { "xsr.misc0", 141 /* xt_iclass_xsr.misc0 */, 8291 0, 8292 Opcode_xsr_misc0_encode_fns, 0, 0 }, 8293 { "rsr.misc1", 142 /* xt_iclass_rsr.misc1 */, 8294 0, 8295 Opcode_rsr_misc1_encode_fns, 0, 0 }, 8296 { "wsr.misc1", 143 /* xt_iclass_wsr.misc1 */, 8297 0, 8298 Opcode_wsr_misc1_encode_fns, 0, 0 }, 8299 { "xsr.misc1", 144 /* xt_iclass_xsr.misc1 */, 8300 0, 8301 Opcode_xsr_misc1_encode_fns, 0, 0 }, 8302 { "rsr.prid", 145 /* xt_iclass_rsr.prid */, 8303 0, 8304 Opcode_rsr_prid_encode_fns, 0, 0 }, 8305 { "rfi", 146 /* xt_iclass_rfi */, 8306 XTENSA_OPCODE_IS_JUMP, 8307 Opcode_rfi_encode_fns, 0, 0 }, 8308 { "waiti", 147 /* xt_iclass_wait */, 8309 0, 8310 Opcode_waiti_encode_fns, 0, 0 }, 8311 { "rsr.interrupt", 148 /* xt_iclass_rsr.interrupt */, 8312 0, 8313 Opcode_rsr_interrupt_encode_fns, 0, 0 }, 8314 { "wsr.intset", 149 /* xt_iclass_wsr.intset */, 8315 0, 8316 Opcode_wsr_intset_encode_fns, 0, 0 }, 8317 { "wsr.intclear", 150 /* xt_iclass_wsr.intclear */, 8318 0, 8319 Opcode_wsr_intclear_encode_fns, 0, 0 }, 8320 { "rsr.intenable", 151 /* xt_iclass_rsr.intenable */, 8321 0, 8322 Opcode_rsr_intenable_encode_fns, 0, 0 }, 8323 { "wsr.intenable", 152 /* xt_iclass_wsr.intenable */, 8324 0, 8325 Opcode_wsr_intenable_encode_fns, 0, 0 }, 8326 { "xsr.intenable", 153 /* xt_iclass_xsr.intenable */, 8327 0, 8328 Opcode_xsr_intenable_encode_fns, 0, 0 }, 8329 { "break", 154 /* xt_iclass_break */, 8330 0, 8331 Opcode_break_encode_fns, 0, 0 }, 8332 { "break.n", 155 /* xt_iclass_break.n */, 8333 0, 8334 Opcode_break_n_encode_fns, 0, 0 }, 8335 { "rsr.dbreaka0", 156 /* xt_iclass_rsr.dbreaka0 */, 8336 0, 8337 Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, 8338 { "wsr.dbreaka0", 157 /* xt_iclass_wsr.dbreaka0 */, 8339 0, 8340 Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, 8341 { "xsr.dbreaka0", 158 /* xt_iclass_xsr.dbreaka0 */, 8342 0, 8343 Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, 8344 { "rsr.dbreakc0", 159 /* xt_iclass_rsr.dbreakc0 */, 8345 0, 8346 Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, 8347 { "wsr.dbreakc0", 160 /* xt_iclass_wsr.dbreakc0 */, 8348 0, 8349 Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, 8350 { "xsr.dbreakc0", 161 /* xt_iclass_xsr.dbreakc0 */, 8351 0, 8352 Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, 8353 { "rsr.dbreaka1", 162 /* xt_iclass_rsr.dbreaka1 */, 8354 0, 8355 Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, 8356 { "wsr.dbreaka1", 163 /* xt_iclass_wsr.dbreaka1 */, 8357 0, 8358 Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, 8359 { "xsr.dbreaka1", 164 /* xt_iclass_xsr.dbreaka1 */, 8360 0, 8361 Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, 8362 { "rsr.dbreakc1", 165 /* xt_iclass_rsr.dbreakc1 */, 8363 0, 8364 Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, 8365 { "wsr.dbreakc1", 166 /* xt_iclass_wsr.dbreakc1 */, 8366 0, 8367 Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, 8368 { "xsr.dbreakc1", 167 /* xt_iclass_xsr.dbreakc1 */, 8369 0, 8370 Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, 8371 { "rsr.ibreaka0", 168 /* xt_iclass_rsr.ibreaka0 */, 8372 0, 8373 Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, 8374 { "wsr.ibreaka0", 169 /* xt_iclass_wsr.ibreaka0 */, 8375 0, 8376 Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, 8377 { "xsr.ibreaka0", 170 /* xt_iclass_xsr.ibreaka0 */, 8378 0, 8379 Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, 8380 { "rsr.ibreaka1", 171 /* xt_iclass_rsr.ibreaka1 */, 8381 0, 8382 Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, 8383 { "wsr.ibreaka1", 172 /* xt_iclass_wsr.ibreaka1 */, 8384 0, 8385 Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, 8386 { "xsr.ibreaka1", 173 /* xt_iclass_xsr.ibreaka1 */, 8387 0, 8388 Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, 8389 { "rsr.ibreakenable", 174 /* xt_iclass_rsr.ibreakenable */, 8390 0, 8391 Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, 8392 { "wsr.ibreakenable", 175 /* xt_iclass_wsr.ibreakenable */, 8393 0, 8394 Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, 8395 { "xsr.ibreakenable", 176 /* xt_iclass_xsr.ibreakenable */, 8396 0, 8397 Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, 8398 { "rsr.debugcause", 177 /* xt_iclass_rsr.debugcause */, 8399 0, 8400 Opcode_rsr_debugcause_encode_fns, 0, 0 }, 8401 { "wsr.debugcause", 178 /* xt_iclass_wsr.debugcause */, 8402 0, 8403 Opcode_wsr_debugcause_encode_fns, 0, 0 }, 8404 { "xsr.debugcause", 179 /* xt_iclass_xsr.debugcause */, 8405 0, 8406 Opcode_xsr_debugcause_encode_fns, 0, 0 }, 8407 { "rsr.icount", 180 /* xt_iclass_rsr.icount */, 8408 0, 8409 Opcode_rsr_icount_encode_fns, 0, 0 }, 8410 { "wsr.icount", 181 /* xt_iclass_wsr.icount */, 8411 0, 8412 Opcode_wsr_icount_encode_fns, 0, 0 }, 8413 { "xsr.icount", 182 /* xt_iclass_xsr.icount */, 8414 0, 8415 Opcode_xsr_icount_encode_fns, 0, 0 }, 8416 { "rsr.icountlevel", 183 /* xt_iclass_rsr.icountlevel */, 8417 0, 8418 Opcode_rsr_icountlevel_encode_fns, 0, 0 }, 8419 { "wsr.icountlevel", 184 /* xt_iclass_wsr.icountlevel */, 8420 0, 8421 Opcode_wsr_icountlevel_encode_fns, 0, 0 }, 8422 { "xsr.icountlevel", 185 /* xt_iclass_xsr.icountlevel */, 8423 0, 8424 Opcode_xsr_icountlevel_encode_fns, 0, 0 }, 8425 { "rsr.ddr", 186 /* xt_iclass_rsr.ddr */, 8426 0, 8427 Opcode_rsr_ddr_encode_fns, 0, 0 }, 8428 { "wsr.ddr", 187 /* xt_iclass_wsr.ddr */, 8429 0, 8430 Opcode_wsr_ddr_encode_fns, 0, 0 }, 8431 { "xsr.ddr", 188 /* xt_iclass_xsr.ddr */, 8432 0, 8433 Opcode_xsr_ddr_encode_fns, 0, 0 }, 8434 { "rfdo", 189 /* xt_iclass_rfdo */, 8435 XTENSA_OPCODE_IS_JUMP, 8436 Opcode_rfdo_encode_fns, 0, 0 }, 8437 { "rfdd", 190 /* xt_iclass_rfdd */, 8438 XTENSA_OPCODE_IS_JUMP, 8439 Opcode_rfdd_encode_fns, 0, 0 }, 8440 { "rsr.ccount", 191 /* xt_iclass_rsr.ccount */, 8441 0, 8442 Opcode_rsr_ccount_encode_fns, 0, 0 }, 8443 { "wsr.ccount", 192 /* xt_iclass_wsr.ccount */, 8444 0, 8445 Opcode_wsr_ccount_encode_fns, 0, 0 }, 8446 { "xsr.ccount", 193 /* xt_iclass_xsr.ccount */, 8447 0, 8448 Opcode_xsr_ccount_encode_fns, 0, 0 }, 8449 { "rsr.ccompare0", 194 /* xt_iclass_rsr.ccompare0 */, 8450 0, 8451 Opcode_rsr_ccompare0_encode_fns, 0, 0 }, 8452 { "wsr.ccompare0", 195 /* xt_iclass_wsr.ccompare0 */, 8453 0, 8454 Opcode_wsr_ccompare0_encode_fns, 0, 0 }, 8455 { "xsr.ccompare0", 196 /* xt_iclass_xsr.ccompare0 */, 8456 0, 8457 Opcode_xsr_ccompare0_encode_fns, 0, 0 }, 8458 { "rsr.ccompare1", 197 /* xt_iclass_rsr.ccompare1 */, 8459 0, 8460 Opcode_rsr_ccompare1_encode_fns, 0, 0 }, 8461 { "wsr.ccompare1", 198 /* xt_iclass_wsr.ccompare1 */, 8462 0, 8463 Opcode_wsr_ccompare1_encode_fns, 0, 0 }, 8464 { "xsr.ccompare1", 199 /* xt_iclass_xsr.ccompare1 */, 8465 0, 8466 Opcode_xsr_ccompare1_encode_fns, 0, 0 }, 8467 { "rsr.ccompare2", 200 /* xt_iclass_rsr.ccompare2 */, 8468 0, 8469 Opcode_rsr_ccompare2_encode_fns, 0, 0 }, 8470 { "wsr.ccompare2", 201 /* xt_iclass_wsr.ccompare2 */, 8471 0, 8472 Opcode_wsr_ccompare2_encode_fns, 0, 0 }, 8473 { "xsr.ccompare2", 202 /* xt_iclass_xsr.ccompare2 */, 8474 0, 8475 Opcode_xsr_ccompare2_encode_fns, 0, 0 }, 8476 { "ipf", 203 /* xt_iclass_icache */, 8477 0, 8478 Opcode_ipf_encode_fns, 0, 0 }, 8479 { "ihi", 203 /* xt_iclass_icache */, 8480 0, 8481 Opcode_ihi_encode_fns, 0, 0 }, 8482 { "iii", 204 /* xt_iclass_icache_inv */, 8483 0, 8484 Opcode_iii_encode_fns, 0, 0 }, 8485 { "lict", 205 /* xt_iclass_licx */, 8486 0, 8487 Opcode_lict_encode_fns, 0, 0 }, 8488 { "licw", 205 /* xt_iclass_licx */, 8489 0, 8490 Opcode_licw_encode_fns, 0, 0 }, 8491 { "sict", 206 /* xt_iclass_sicx */, 8492 0, 8493 Opcode_sict_encode_fns, 0, 0 }, 8494 { "sicw", 206 /* xt_iclass_sicx */, 8495 0, 8496 Opcode_sicw_encode_fns, 0, 0 }, 8497 { "dhwb", 207 /* xt_iclass_dcache */, 8498 0, 8499 Opcode_dhwb_encode_fns, 0, 0 }, 8500 { "dhwbi", 207 /* xt_iclass_dcache */, 8501 0, 8502 Opcode_dhwbi_encode_fns, 0, 0 }, 8503 { "diwb", 208 /* xt_iclass_dcache_ind */, 8504 0, 8505 Opcode_diwb_encode_fns, 0, 0 }, 8506 { "diwbi", 208 /* xt_iclass_dcache_ind */, 8507 0, 8508 Opcode_diwbi_encode_fns, 0, 0 }, 8509 { "dhi", 209 /* xt_iclass_dcache_inv */, 8510 0, 8511 Opcode_dhi_encode_fns, 0, 0 }, 8512 { "dii", 209 /* xt_iclass_dcache_inv */, 8513 0, 8514 Opcode_dii_encode_fns, 0, 0 }, 8515 { "dpfr", 210 /* xt_iclass_dpf */, 8516 0, 8517 Opcode_dpfr_encode_fns, 0, 0 }, 8518 { "dpfw", 210 /* xt_iclass_dpf */, 8519 0, 8520 Opcode_dpfw_encode_fns, 0, 0 }, 8521 { "dpfro", 210 /* xt_iclass_dpf */, 8522 0, 8523 Opcode_dpfro_encode_fns, 0, 0 }, 8524 { "dpfwo", 210 /* xt_iclass_dpf */, 8525 0, 8526 Opcode_dpfwo_encode_fns, 0, 0 }, 8527 { "sdct", 211 /* xt_iclass_sdct */, 8528 0, 8529 Opcode_sdct_encode_fns, 0, 0 }, 8530 { "ldct", 212 /* xt_iclass_ldct */, 8531 0, 8532 Opcode_ldct_encode_fns, 0, 0 }, 8533 { "wsr.ptevaddr", 213 /* xt_iclass_wsr.ptevaddr */, 8534 0, 8535 Opcode_wsr_ptevaddr_encode_fns, 0, 0 }, 8536 { "rsr.ptevaddr", 214 /* xt_iclass_rsr.ptevaddr */, 8537 0, 8538 Opcode_rsr_ptevaddr_encode_fns, 0, 0 }, 8539 { "xsr.ptevaddr", 215 /* xt_iclass_xsr.ptevaddr */, 8540 0, 8541 Opcode_xsr_ptevaddr_encode_fns, 0, 0 }, 8542 { "rsr.rasid", 216 /* xt_iclass_rsr.rasid */, 8543 0, 8544 Opcode_rsr_rasid_encode_fns, 0, 0 }, 8545 { "wsr.rasid", 217 /* xt_iclass_wsr.rasid */, 8546 0, 8547 Opcode_wsr_rasid_encode_fns, 0, 0 }, 8548 { "xsr.rasid", 218 /* xt_iclass_xsr.rasid */, 8549 0, 8550 Opcode_xsr_rasid_encode_fns, 0, 0 }, 8551 { "rsr.itlbcfg", 219 /* xt_iclass_rsr.itlbcfg */, 8552 0, 8553 Opcode_rsr_itlbcfg_encode_fns, 0, 0 }, 8554 { "wsr.itlbcfg", 220 /* xt_iclass_wsr.itlbcfg */, 8555 0, 8556 Opcode_wsr_itlbcfg_encode_fns, 0, 0 }, 8557 { "xsr.itlbcfg", 221 /* xt_iclass_xsr.itlbcfg */, 8558 0, 8559 Opcode_xsr_itlbcfg_encode_fns, 0, 0 }, 8560 { "rsr.dtlbcfg", 222 /* xt_iclass_rsr.dtlbcfg */, 8561 0, 8562 Opcode_rsr_dtlbcfg_encode_fns, 0, 0 }, 8563 { "wsr.dtlbcfg", 223 /* xt_iclass_wsr.dtlbcfg */, 8564 0, 8565 Opcode_wsr_dtlbcfg_encode_fns, 0, 0 }, 8566 { "xsr.dtlbcfg", 224 /* xt_iclass_xsr.dtlbcfg */, 8567 0, 8568 Opcode_xsr_dtlbcfg_encode_fns, 0, 0 }, 8569 { "idtlb", 225 /* xt_iclass_idtlb */, 8570 0, 8571 Opcode_idtlb_encode_fns, 0, 0 }, 8572 { "pdtlb", 226 /* xt_iclass_rdtlb */, 8573 0, 8574 Opcode_pdtlb_encode_fns, 0, 0 }, 8575 { "rdtlb0", 226 /* xt_iclass_rdtlb */, 8576 0, 8577 Opcode_rdtlb0_encode_fns, 0, 0 }, 8578 { "rdtlb1", 226 /* xt_iclass_rdtlb */, 8579 0, 8580 Opcode_rdtlb1_encode_fns, 0, 0 }, 8581 { "wdtlb", 227 /* xt_iclass_wdtlb */, 8582 0, 8583 Opcode_wdtlb_encode_fns, 0, 0 }, 8584 { "iitlb", 228 /* xt_iclass_iitlb */, 8585 0, 8586 Opcode_iitlb_encode_fns, 0, 0 }, 8587 { "pitlb", 229 /* xt_iclass_ritlb */, 8588 0, 8589 Opcode_pitlb_encode_fns, 0, 0 }, 8590 { "ritlb0", 229 /* xt_iclass_ritlb */, 8591 0, 8592 Opcode_ritlb0_encode_fns, 0, 0 }, 8593 { "ritlb1", 229 /* xt_iclass_ritlb */, 8594 0, 8595 Opcode_ritlb1_encode_fns, 0, 0 }, 8596 { "witlb", 230 /* xt_iclass_witlb */, 8597 0, 8598 Opcode_witlb_encode_fns, 0, 0 }, 8599 { "ldpte", 231 /* xt_iclass_ldpte */, 8600 0, 8601 Opcode_ldpte_encode_fns, 0, 0 }, 8602 { "hwwitlba", 232 /* xt_iclass_hwwitlba */, 8603 XTENSA_OPCODE_IS_BRANCH, 8604 Opcode_hwwitlba_encode_fns, 0, 0 }, 8605 { "hwwdtlba", 233 /* xt_iclass_hwwdtlba */, 8606 0, 8607 Opcode_hwwdtlba_encode_fns, 0, 0 }, 8608 { "nsa", 234 /* xt_iclass_nsa */, 8609 0, 8610 Opcode_nsa_encode_fns, 0, 0 }, 8611 { "nsau", 234 /* xt_iclass_nsa */, 8612 0, 8613 Opcode_nsau_encode_fns, 0, 0 } 8614 }; 8615 8616 8617 /* Slot-specific opcode decode functions. */ 8619 8620 static int 8621 Slot_inst_decode (const xtensa_insnbuf insn) 8622 { 8623 switch (Field_op0_Slot_inst_get (insn)) 8624 { 8625 case 0: 8626 switch (Field_op1_Slot_inst_get (insn)) 8627 { 8628 case 0: 8629 switch (Field_op2_Slot_inst_get (insn)) 8630 { 8631 case 0: 8632 switch (Field_r_Slot_inst_get (insn)) 8633 { 8634 case 0: 8635 switch (Field_m_Slot_inst_get (insn)) 8636 { 8637 case 0: 8638 if (Field_s_Slot_inst_get (insn) == 0 && 8639 Field_n_Slot_inst_get (insn) == 0) 8640 return 77; /* ill */ 8641 break; 8642 case 2: 8643 switch (Field_n_Slot_inst_get (insn)) 8644 { 8645 case 0: 8646 return 96; /* ret */ 8647 case 1: 8648 return 14; /* retw */ 8649 case 2: 8650 return 79; /* jx */ 8651 } 8652 break; 8653 case 3: 8654 switch (Field_n_Slot_inst_get (insn)) 8655 { 8656 case 0: 8657 return 75; /* callx0 */ 8658 case 1: 8659 return 10; /* callx4 */ 8660 case 2: 8661 return 9; /* callx8 */ 8662 case 3: 8663 return 8; /* callx12 */ 8664 } 8665 break; 8666 } 8667 break; 8668 case 1: 8669 return 12; /* movsp */ 8670 case 2: 8671 if (Field_s_Slot_inst_get (insn) == 0) 8672 { 8673 switch (Field_t_Slot_inst_get (insn)) 8674 { 8675 case 0: 8676 return 114; /* isync */ 8677 case 1: 8678 return 115; /* rsync */ 8679 case 2: 8680 return 116; /* esync */ 8681 case 3: 8682 return 117; /* dsync */ 8683 case 8: 8684 return 0; /* excw */ 8685 case 12: 8686 return 112; /* memw */ 8687 case 13: 8688 return 113; /* extw */ 8689 case 15: 8690 return 95; /* nop */ 8691 } 8692 } 8693 break; 8694 case 3: 8695 switch (Field_t_Slot_inst_get (insn)) 8696 { 8697 case 0: 8698 switch (Field_s_Slot_inst_get (insn)) 8699 { 8700 case 0: 8701 return 1; /* rfe */ 8702 case 2: 8703 return 2; /* rfde */ 8704 case 4: 8705 return 16; /* rfwo */ 8706 case 5: 8707 return 17; /* rfwu */ 8708 } 8709 break; 8710 case 1: 8711 return 188; /* rfi */ 8712 } 8713 break; 8714 case 4: 8715 return 196; /* break */ 8716 case 5: 8717 switch (Field_s_Slot_inst_get (insn)) 8718 { 8719 case 0: 8720 if (Field_t_Slot_inst_get (insn) == 0) 8721 return 3; /* syscall */ 8722 break; 8723 case 1: 8724 if (Field_t_Slot_inst_get (insn) == 0) 8725 return 4; /* simcall */ 8726 break; 8727 } 8728 break; 8729 case 6: 8730 return 118; /* rsil */ 8731 case 7: 8732 if (Field_t_Slot_inst_get (insn) == 0) 8733 return 189; /* waiti */ 8734 break; 8735 } 8736 break; 8737 case 1: 8738 return 47; /* and */ 8739 case 2: 8740 return 48; /* or */ 8741 case 3: 8742 return 49; /* xor */ 8743 case 4: 8744 switch (Field_r_Slot_inst_get (insn)) 8745 { 8746 case 0: 8747 if (Field_t_Slot_inst_get (insn) == 0) 8748 return 100; /* ssr */ 8749 break; 8750 case 1: 8751 if (Field_t_Slot_inst_get (insn) == 0) 8752 return 101; /* ssl */ 8753 break; 8754 case 2: 8755 if (Field_t_Slot_inst_get (insn) == 0) 8756 return 102; /* ssa8l */ 8757 break; 8758 case 3: 8759 if (Field_t_Slot_inst_get (insn) == 0) 8760 return 103; /* ssa8b */ 8761 break; 8762 case 4: 8763 if (Field_thi3_Slot_inst_get (insn) == 0) 8764 return 104; /* ssai */ 8765 break; 8766 case 8: 8767 if (Field_s_Slot_inst_get (insn) == 0) 8768 return 13; /* rotw */ 8769 break; 8770 case 14: 8771 return 289; /* nsa */ 8772 case 15: 8773 return 290; /* nsau */ 8774 } 8775 break; 8776 case 5: 8777 switch (Field_r_Slot_inst_get (insn)) 8778 { 8779 case 1: 8780 return 287; /* hwwitlba */ 8781 case 3: 8782 return 283; /* ritlb0 */ 8783 case 4: 8784 if (Field_t_Slot_inst_get (insn) == 0) 8785 return 281; /* iitlb */ 8786 break; 8787 case 5: 8788 return 282; /* pitlb */ 8789 case 6: 8790 return 285; /* witlb */ 8791 case 7: 8792 return 284; /* ritlb1 */ 8793 case 9: 8794 return 288; /* hwwdtlba */ 8795 case 11: 8796 return 278; /* rdtlb0 */ 8797 case 12: 8798 if (Field_t_Slot_inst_get (insn) == 0) 8799 return 276; /* idtlb */ 8800 break; 8801 case 13: 8802 return 277; /* pdtlb */ 8803 case 14: 8804 return 280; /* wdtlb */ 8805 case 15: 8806 return 279; /* rdtlb1 */ 8807 } 8808 break; 8809 case 6: 8810 switch (Field_s_Slot_inst_get (insn)) 8811 { 8812 case 0: 8813 return 93; /* neg */ 8814 case 1: 8815 return 94; /* abs */ 8816 } 8817 break; 8818 case 8: 8819 return 39; /* add */ 8820 case 9: 8821 return 41; /* addx2 */ 8822 case 10: 8823 return 42; /* addx4 */ 8824 case 11: 8825 return 43; /* addx8 */ 8826 case 12: 8827 return 40; /* sub */ 8828 case 13: 8829 return 44; /* subx2 */ 8830 case 14: 8831 return 45; /* subx4 */ 8832 case 15: 8833 return 46; /* subx8 */ 8834 } 8835 break; 8836 case 1: 8837 switch (Field_op2_Slot_inst_get (insn)) 8838 { 8839 case 0: 8840 case 1: 8841 return 109; /* slli */ 8842 case 2: 8843 case 3: 8844 return 110; /* srai */ 8845 case 4: 8846 return 111; /* srli */ 8847 case 6: 8848 switch (Field_sr_Slot_inst_get (insn)) 8849 { 8850 case 0: 8851 return 127; /* xsr.lbeg */ 8852 case 1: 8853 return 121; /* xsr.lend */ 8854 case 2: 8855 return 124; /* xsr.lcount */ 8856 case 3: 8857 return 130; /* xsr.sar */ 8858 case 5: 8859 return 133; /* xsr.litbase */ 8860 case 72: 8861 return 22; /* xsr.windowbase */ 8862 case 73: 8863 return 25; /* xsr.windowstart */ 8864 case 83: 8865 return 266; /* xsr.ptevaddr */ 8866 case 90: 8867 return 269; /* xsr.rasid */ 8868 case 91: 8869 return 272; /* xsr.itlbcfg */ 8870 case 92: 8871 return 275; /* xsr.dtlbcfg */ 8872 case 96: 8873 return 218; /* xsr.ibreakenable */ 8874 case 104: 8875 return 230; /* xsr.ddr */ 8876 case 128: 8877 return 212; /* xsr.ibreaka0 */ 8878 case 129: 8879 return 215; /* xsr.ibreaka1 */ 8880 case 144: 8881 return 200; /* xsr.dbreaka0 */ 8882 case 145: 8883 return 206; /* xsr.dbreaka1 */ 8884 case 160: 8885 return 203; /* xsr.dbreakc0 */ 8886 case 161: 8887 return 209; /* xsr.dbreakc1 */ 8888 case 177: 8889 return 141; /* xsr.epc1 */ 8890 case 178: 8891 return 147; /* xsr.epc2 */ 8892 case 179: 8893 return 153; /* xsr.epc3 */ 8894 case 180: 8895 return 159; /* xsr.epc4 */ 8896 case 192: 8897 return 177; /* xsr.depc */ 8898 case 194: 8899 return 165; /* xsr.eps2 */ 8900 case 195: 8901 return 168; /* xsr.eps3 */ 8902 case 196: 8903 return 171; /* xsr.eps4 */ 8904 case 209: 8905 return 144; /* xsr.excsave1 */ 8906 case 210: 8907 return 150; /* xsr.excsave2 */ 8908 case 211: 8909 return 156; /* xsr.excsave3 */ 8910 case 212: 8911 return 162; /* xsr.excsave4 */ 8912 case 228: 8913 return 195; /* xsr.intenable */ 8914 case 230: 8915 return 138; /* xsr.ps */ 8916 case 232: 8917 return 180; /* xsr.exccause */ 8918 case 233: 8919 return 221; /* xsr.debugcause */ 8920 case 234: 8921 return 235; /* xsr.ccount */ 8922 case 236: 8923 return 224; /* xsr.icount */ 8924 case 237: 8925 return 227; /* xsr.icountlevel */ 8926 case 238: 8927 return 174; /* xsr.excvaddr */ 8928 case 240: 8929 return 238; /* xsr.ccompare0 */ 8930 case 241: 8931 return 241; /* xsr.ccompare1 */ 8932 case 242: 8933 return 244; /* xsr.ccompare2 */ 8934 case 244: 8935 return 183; /* xsr.misc0 */ 8936 case 245: 8937 return 186; /* xsr.misc1 */ 8938 } 8939 break; 8940 case 8: 8941 return 106; /* src */ 8942 case 9: 8943 if (Field_s_Slot_inst_get (insn) == 0) 8944 return 107; /* srl */ 8945 break; 8946 case 10: 8947 if (Field_t_Slot_inst_get (insn) == 0) 8948 return 105; /* sll */ 8949 break; 8950 case 11: 8951 if (Field_s_Slot_inst_get (insn) == 0) 8952 return 108; /* sra */ 8953 break; 8954 case 15: 8955 switch (Field_r_Slot_inst_get (insn)) 8956 { 8957 case 0: 8958 return 248; /* lict */ 8959 case 1: 8960 return 250; /* sict */ 8961 case 2: 8962 return 249; /* licw */ 8963 case 3: 8964 return 251; /* sicw */ 8965 case 8: 8966 return 263; /* ldct */ 8967 case 9: 8968 return 262; /* sdct */ 8969 case 14: 8970 if (Field_t_Slot_inst_get (insn) == 0 && 8971 Field_s_Slot_inst_get (insn) == 0) 8972 return 231; /* rfdo */ 8973 if (Field_t_Slot_inst_get (insn) == 1 && 8974 Field_s_Slot_inst_get (insn) == 0) 8975 return 232; /* rfdd */ 8976 break; 8977 case 15: 8978 return 286; /* ldpte */ 8979 } 8980 break; 8981 } 8982 break; 8983 case 3: 8984 switch (Field_op2_Slot_inst_get (insn)) 8985 { 8986 case 0: 8987 switch (Field_sr_Slot_inst_get (insn)) 8988 { 8989 case 0: 8990 return 125; /* rsr.lbeg */ 8991 case 1: 8992 return 119; /* rsr.lend */ 8993 case 2: 8994 return 122; /* rsr.lcount */ 8995 case 3: 8996 return 128; /* rsr.sar */ 8997 case 5: 8998 return 131; /* rsr.litbase */ 8999 case 72: 9000 return 20; /* rsr.windowbase */ 9001 case 73: 9002 return 23; /* rsr.windowstart */ 9003 case 83: 9004 return 265; /* rsr.ptevaddr */ 9005 case 90: 9006 return 267; /* rsr.rasid */ 9007 case 91: 9008 return 270; /* rsr.itlbcfg */ 9009 case 92: 9010 return 273; /* rsr.dtlbcfg */ 9011 case 96: 9012 return 216; /* rsr.ibreakenable */ 9013 case 104: 9014 return 228; /* rsr.ddr */ 9015 case 128: 9016 return 210; /* rsr.ibreaka0 */ 9017 case 129: 9018 return 213; /* rsr.ibreaka1 */ 9019 case 144: 9020 return 198; /* rsr.dbreaka0 */ 9021 case 145: 9022 return 204; /* rsr.dbreaka1 */ 9023 case 160: 9024 return 201; /* rsr.dbreakc0 */ 9025 case 161: 9026 return 207; /* rsr.dbreakc1 */ 9027 case 176: 9028 return 134; /* rsr.176 */ 9029 case 177: 9030 return 139; /* rsr.epc1 */ 9031 case 178: 9032 return 145; /* rsr.epc2 */ 9033 case 179: 9034 return 151; /* rsr.epc3 */ 9035 case 180: 9036 return 157; /* rsr.epc4 */ 9037 case 192: 9038 return 175; /* rsr.depc */ 9039 case 194: 9040 return 163; /* rsr.eps2 */ 9041 case 195: 9042 return 166; /* rsr.eps3 */ 9043 case 196: 9044 return 169; /* rsr.eps4 */ 9045 case 208: 9046 return 135; /* rsr.208 */ 9047 case 209: 9048 return 142; /* rsr.excsave1 */ 9049 case 210: 9050 return 148; /* rsr.excsave2 */ 9051 case 211: 9052 return 154; /* rsr.excsave3 */ 9053 case 212: 9054 return 160; /* rsr.excsave4 */ 9055 case 226: 9056 return 190; /* rsr.interrupt */ 9057 case 228: 9058 return 193; /* rsr.intenable */ 9059 case 230: 9060 return 136; /* rsr.ps */ 9061 case 232: 9062 return 178; /* rsr.exccause */ 9063 case 233: 9064 return 219; /* rsr.debugcause */ 9065 case 234: 9066 return 233; /* rsr.ccount */ 9067 case 235: 9068 return 187; /* rsr.prid */ 9069 case 236: 9070 return 222; /* rsr.icount */ 9071 case 237: 9072 return 225; /* rsr.icountlevel */ 9073 case 238: 9074 return 172; /* rsr.excvaddr */ 9075 case 240: 9076 return 236; /* rsr.ccompare0 */ 9077 case 241: 9078 return 239; /* rsr.ccompare1 */ 9079 case 242: 9080 return 242; /* rsr.ccompare2 */ 9081 case 244: 9082 return 181; /* rsr.misc0 */ 9083 case 245: 9084 return 184; /* rsr.misc1 */ 9085 } 9086 break; 9087 case 1: 9088 switch (Field_sr_Slot_inst_get (insn)) 9089 { 9090 case 0: 9091 return 126; /* wsr.lbeg */ 9092 case 1: 9093 return 120; /* wsr.lend */ 9094 case 2: 9095 return 123; /* wsr.lcount */ 9096 case 3: 9097 return 129; /* wsr.sar */ 9098 case 5: 9099 return 132; /* wsr.litbase */ 9100 case 72: 9101 return 21; /* wsr.windowbase */ 9102 case 73: 9103 return 24; /* wsr.windowstart */ 9104 case 83: 9105 return 264; /* wsr.ptevaddr */ 9106 case 90: 9107 return 268; /* wsr.rasid */ 9108 case 91: 9109 return 271; /* wsr.itlbcfg */ 9110 case 92: 9111 return 274; /* wsr.dtlbcfg */ 9112 case 96: 9113 return 217; /* wsr.ibreakenable */ 9114 case 104: 9115 return 229; /* wsr.ddr */ 9116 case 128: 9117 return 211; /* wsr.ibreaka0 */ 9118 case 129: 9119 return 214; /* wsr.ibreaka1 */ 9120 case 144: 9121 return 199; /* wsr.dbreaka0 */ 9122 case 145: 9123 return 205; /* wsr.dbreaka1 */ 9124 case 160: 9125 return 202; /* wsr.dbreakc0 */ 9126 case 161: 9127 return 208; /* wsr.dbreakc1 */ 9128 case 177: 9129 return 140; /* wsr.epc1 */ 9130 case 178: 9131 return 146; /* wsr.epc2 */ 9132 case 179: 9133 return 152; /* wsr.epc3 */ 9134 case 180: 9135 return 158; /* wsr.epc4 */ 9136 case 192: 9137 return 176; /* wsr.depc */ 9138 case 194: 9139 return 164; /* wsr.eps2 */ 9140 case 195: 9141 return 167; /* wsr.eps3 */ 9142 case 196: 9143 return 170; /* wsr.eps4 */ 9144 case 209: 9145 return 143; /* wsr.excsave1 */ 9146 case 210: 9147 return 149; /* wsr.excsave2 */ 9148 case 211: 9149 return 155; /* wsr.excsave3 */ 9150 case 212: 9151 return 161; /* wsr.excsave4 */ 9152 case 226: 9153 return 191; /* wsr.intset */ 9154 case 227: 9155 return 192; /* wsr.intclear */ 9156 case 228: 9157 return 194; /* wsr.intenable */ 9158 case 230: 9159 return 137; /* wsr.ps */ 9160 case 232: 9161 return 179; /* wsr.exccause */ 9162 case 233: 9163 return 220; /* wsr.debugcause */ 9164 case 234: 9165 return 234; /* wsr.ccount */ 9166 case 236: 9167 return 223; /* wsr.icount */ 9168 case 237: 9169 return 226; /* wsr.icountlevel */ 9170 case 238: 9171 return 173; /* wsr.excvaddr */ 9172 case 240: 9173 return 237; /* wsr.ccompare0 */ 9174 case 241: 9175 return 240; /* wsr.ccompare1 */ 9176 case 242: 9177 return 243; /* wsr.ccompare2 */ 9178 case 244: 9179 return 182; /* wsr.misc0 */ 9180 case 245: 9181 return 185; /* wsr.misc1 */ 9182 } 9183 break; 9184 case 8: 9185 return 89; /* moveqz */ 9186 case 9: 9187 return 90; /* movnez */ 9188 case 10: 9189 return 91; /* movltz */ 9190 case 11: 9191 return 92; /* movgez */ 9192 } 9193 break; 9194 case 4: 9195 case 5: 9196 return 76; /* extui */ 9197 case 9: 9198 switch (Field_op2_Slot_inst_get (insn)) 9199 { 9200 case 0: 9201 return 18; /* l32e */ 9202 case 4: 9203 return 19; /* s32e */ 9204 } 9205 break; 9206 } 9207 break; 9208 case 1: 9209 return 83; /* l32r */ 9210 case 2: 9211 switch (Field_r_Slot_inst_get (insn)) 9212 { 9213 case 0: 9214 return 84; /* l8ui */ 9215 case 1: 9216 return 80; /* l16ui */ 9217 case 2: 9218 return 82; /* l32i */ 9219 case 4: 9220 return 99; /* s8i */ 9221 case 5: 9222 return 97; /* s16i */ 9223 case 6: 9224 return 98; /* s32i */ 9225 case 7: 9226 switch (Field_t_Slot_inst_get (insn)) 9227 { 9228 case 0: 9229 return 258; /* dpfr */ 9230 case 1: 9231 return 259; /* dpfw */ 9232 case 2: 9233 return 260; /* dpfro */ 9234 case 3: 9235 return 261; /* dpfwo */ 9236 case 4: 9237 return 252; /* dhwb */ 9238 case 5: 9239 return 253; /* dhwbi */ 9240 case 6: 9241 return 256; /* dhi */ 9242 case 7: 9243 return 257; /* dii */ 9244 case 8: 9245 switch (Field_op1_Slot_inst_get (insn)) 9246 { 9247 case 4: 9248 return 254; /* diwb */ 9249 case 5: 9250 return 255; /* diwbi */ 9251 } 9252 break; 9253 case 12: 9254 return 245; /* ipf */ 9255 case 14: 9256 return 246; /* ihi */ 9257 case 15: 9258 return 247; /* iii */ 9259 } 9260 break; 9261 case 9: 9262 return 81; /* l16si */ 9263 case 10: 9264 return 88; /* movi */ 9265 case 12: 9266 return 37; /* addi */ 9267 case 13: 9268 return 38; /* addmi */ 9269 } 9270 break; 9271 case 5: 9272 switch (Field_n_Slot_inst_get (insn)) 9273 { 9274 case 0: 9275 return 74; /* call0 */ 9276 case 1: 9277 return 7; /* call4 */ 9278 case 2: 9279 return 6; /* call8 */ 9280 case 3: 9281 return 5; /* call12 */ 9282 } 9283 break; 9284 case 6: 9285 switch (Field_n_Slot_inst_get (insn)) 9286 { 9287 case 0: 9288 return 78; /* j */ 9289 case 1: 9290 switch (Field_m_Slot_inst_get (insn)) 9291 { 9292 case 0: 9293 return 70; /* beqz */ 9294 case 1: 9295 return 71; /* bnez */ 9296 case 2: 9297 return 73; /* bltz */ 9298 case 3: 9299 return 72; /* bgez */ 9300 } 9301 break; 9302 case 2: 9303 switch (Field_m_Slot_inst_get (insn)) 9304 { 9305 case 0: 9306 return 50; /* beqi */ 9307 case 1: 9308 return 51; /* bnei */ 9309 case 2: 9310 return 53; /* blti */ 9311 case 3: 9312 return 52; /* bgei */ 9313 } 9314 break; 9315 case 3: 9316 switch (Field_m_Slot_inst_get (insn)) 9317 { 9318 case 0: 9319 return 11; /* entry */ 9320 case 1: 9321 switch (Field_r_Slot_inst_get (insn)) 9322 { 9323 case 8: 9324 return 85; /* loop */ 9325 case 9: 9326 return 86; /* loopnez */ 9327 case 10: 9328 return 87; /* loopgtz */ 9329 } 9330 break; 9331 case 2: 9332 return 57; /* bltui */ 9333 case 3: 9334 return 56; /* bgeui */ 9335 } 9336 break; 9337 } 9338 break; 9339 case 7: 9340 switch (Field_r_Slot_inst_get (insn)) 9341 { 9342 case 0: 9343 return 65; /* bnone */ 9344 case 1: 9345 return 58; /* beq */ 9346 case 2: 9347 return 61; /* blt */ 9348 case 3: 9349 return 63; /* bltu */ 9350 case 4: 9351 return 66; /* ball */ 9352 case 5: 9353 return 68; /* bbc */ 9354 case 6: 9355 case 7: 9356 return 54; /* bbci */ 9357 case 8: 9358 return 64; /* bany */ 9359 case 9: 9360 return 59; /* bne */ 9361 case 10: 9362 return 60; /* bge */ 9363 case 11: 9364 return 62; /* bgeu */ 9365 case 12: 9366 return 67; /* bnall */ 9367 case 13: 9368 return 69; /* bbs */ 9369 case 14: 9370 case 15: 9371 return 55; /* bbsi */ 9372 } 9373 break; 9374 } 9375 return 0; 9376 } 9377 9378 static int 9379 Slot_inst16b_decode (const xtensa_insnbuf insn) 9380 { 9381 switch (Field_op0_Slot_inst16b_get (insn)) 9382 { 9383 case 12: 9384 switch (Field_i_Slot_inst16b_get (insn)) 9385 { 9386 case 0: 9387 return 33; /* movi.n */ 9388 case 1: 9389 switch (Field_z_Slot_inst16b_get (insn)) 9390 { 9391 case 0: 9392 return 28; /* beqz.n */ 9393 case 1: 9394 return 29; /* bnez.n */ 9395 } 9396 break; 9397 } 9398 break; 9399 case 13: 9400 switch (Field_r_Slot_inst16b_get (insn)) 9401 { 9402 case 0: 9403 return 32; /* mov.n */ 9404 case 15: 9405 switch (Field_t_Slot_inst16b_get (insn)) 9406 { 9407 case 0: 9408 return 35; /* ret.n */ 9409 case 1: 9410 return 15; /* retw.n */ 9411 case 2: 9412 return 197; /* break.n */ 9413 case 3: 9414 if (Field_s_Slot_inst16b_get (insn) == 0) 9415 return 34; /* nop.n */ 9416 break; 9417 case 6: 9418 if (Field_s_Slot_inst16b_get (insn) == 0) 9419 return 30; /* ill.n */ 9420 break; 9421 } 9422 break; 9423 } 9424 break; 9425 } 9426 return 0; 9427 } 9428 9429 static int 9430 Slot_inst16a_decode (const xtensa_insnbuf insn) 9431 { 9432 switch (Field_op0_Slot_inst16a_get (insn)) 9433 { 9434 case 8: 9435 return 31; /* l32i.n */ 9436 case 9: 9437 return 36; /* s32i.n */ 9438 case 10: 9439 return 26; /* add.n */ 9440 case 11: 9441 return 27; /* addi.n */ 9442 } 9443 return 0; 9444 } 9445 9446 9447 /* Instruction slots. */ 9449 9450 static void 9451 Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, 9452 xtensa_insnbuf slotbuf) 9453 { 9454 slotbuf[0] = (insn[0] & 0xffffff); 9455 } 9456 9457 static void 9458 Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, 9459 const xtensa_insnbuf slotbuf) 9460 { 9461 insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); 9462 } 9463 9464 static void 9465 Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, 9466 xtensa_insnbuf slotbuf) 9467 { 9468 slotbuf[0] = ((insn[0] & 0xffff00) >> 8); 9469 } 9470 9471 static void 9472 Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, 9473 const xtensa_insnbuf slotbuf) 9474 { 9475 insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8); 9476 } 9477 9478 static void 9479 Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, 9480 xtensa_insnbuf slotbuf) 9481 { 9482 slotbuf[0] = ((insn[0] & 0xffff00) >> 8); 9483 } 9484 9485 static void 9486 Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, 9487 const xtensa_insnbuf slotbuf) 9488 { 9489 insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8); 9490 } 9491 9492 static xtensa_get_field_fn 9493 Slot_inst_get_field_fns[] = { 9494 Field_t_Slot_inst_get, 9495 Field_bbi4_Slot_inst_get, 9496 Field_bbi_Slot_inst_get, 9497 Field_imm12_Slot_inst_get, 9498 Field_imm8_Slot_inst_get, 9499 Field_s_Slot_inst_get, 9500 Field_imm12b_Slot_inst_get, 9501 Field_imm16_Slot_inst_get, 9502 Field_m_Slot_inst_get, 9503 Field_n_Slot_inst_get, 9504 Field_offset_Slot_inst_get, 9505 Field_op0_Slot_inst_get, 9506 Field_op1_Slot_inst_get, 9507 Field_op2_Slot_inst_get, 9508 Field_r_Slot_inst_get, 9509 Field_sa4_Slot_inst_get, 9510 Field_sae4_Slot_inst_get, 9511 Field_sae_Slot_inst_get, 9512 Field_sal_Slot_inst_get, 9513 Field_sargt_Slot_inst_get, 9514 Field_sas4_Slot_inst_get, 9515 Field_sas_Slot_inst_get, 9516 Field_sr_Slot_inst_get, 9517 Field_st_Slot_inst_get, 9518 Field_thi3_Slot_inst_get, 9519 Field_imm4_Slot_inst_get, 9520 Field_mn_Slot_inst_get, 9521 0, 9522 0, 9523 0, 9524 0, 9525 0, 9526 0, 9527 0, 9528 0, 9529 Implicit_Field_ar0_get, 9530 Implicit_Field_ar4_get, 9531 Implicit_Field_ar8_get, 9532 Implicit_Field_ar12_get 9533 }; 9534 9535 static xtensa_set_field_fn 9536 Slot_inst_set_field_fns[] = { 9537 Field_t_Slot_inst_set, 9538 Field_bbi4_Slot_inst_set, 9539 Field_bbi_Slot_inst_set, 9540 Field_imm12_Slot_inst_set, 9541 Field_imm8_Slot_inst_set, 9542 Field_s_Slot_inst_set, 9543 Field_imm12b_Slot_inst_set, 9544 Field_imm16_Slot_inst_set, 9545 Field_m_Slot_inst_set, 9546 Field_n_Slot_inst_set, 9547 Field_offset_Slot_inst_set, 9548 Field_op0_Slot_inst_set, 9549 Field_op1_Slot_inst_set, 9550 Field_op2_Slot_inst_set, 9551 Field_r_Slot_inst_set, 9552 Field_sa4_Slot_inst_set, 9553 Field_sae4_Slot_inst_set, 9554 Field_sae_Slot_inst_set, 9555 Field_sal_Slot_inst_set, 9556 Field_sargt_Slot_inst_set, 9557 Field_sas4_Slot_inst_set, 9558 Field_sas_Slot_inst_set, 9559 Field_sr_Slot_inst_set, 9560 Field_st_Slot_inst_set, 9561 Field_thi3_Slot_inst_set, 9562 Field_imm4_Slot_inst_set, 9563 Field_mn_Slot_inst_set, 9564 0, 9565 0, 9566 0, 9567 0, 9568 0, 9569 0, 9570 0, 9571 0, 9572 Implicit_Field_set, 9573 Implicit_Field_set, 9574 Implicit_Field_set, 9575 Implicit_Field_set 9576 }; 9577 9578 static xtensa_get_field_fn 9579 Slot_inst16a_get_field_fns[] = { 9580 Field_t_Slot_inst16a_get, 9581 0, 9582 0, 9583 0, 9584 0, 9585 Field_s_Slot_inst16a_get, 9586 0, 9587 0, 9588 0, 9589 0, 9590 0, 9591 Field_op0_Slot_inst16a_get, 9592 0, 9593 0, 9594 Field_r_Slot_inst16a_get, 9595 0, 9596 0, 9597 0, 9598 0, 9599 0, 9600 0, 9601 0, 9602 Field_sr_Slot_inst16a_get, 9603 Field_st_Slot_inst16a_get, 9604 0, 9605 Field_imm4_Slot_inst16a_get, 9606 0, 9607 Field_i_Slot_inst16a_get, 9608 Field_imm6lo_Slot_inst16a_get, 9609 Field_imm6hi_Slot_inst16a_get, 9610 Field_imm7lo_Slot_inst16a_get, 9611 Field_imm7hi_Slot_inst16a_get, 9612 Field_z_Slot_inst16a_get, 9613 Field_imm6_Slot_inst16a_get, 9614 Field_imm7_Slot_inst16a_get, 9615 Implicit_Field_ar0_get, 9616 Implicit_Field_ar4_get, 9617 Implicit_Field_ar8_get, 9618 Implicit_Field_ar12_get 9619 }; 9620 9621 static xtensa_set_field_fn 9622 Slot_inst16a_set_field_fns[] = { 9623 Field_t_Slot_inst16a_set, 9624 0, 9625 0, 9626 0, 9627 0, 9628 Field_s_Slot_inst16a_set, 9629 0, 9630 0, 9631 0, 9632 0, 9633 0, 9634 Field_op0_Slot_inst16a_set, 9635 0, 9636 0, 9637 Field_r_Slot_inst16a_set, 9638 0, 9639 0, 9640 0, 9641 0, 9642 0, 9643 0, 9644 0, 9645 Field_sr_Slot_inst16a_set, 9646 Field_st_Slot_inst16a_set, 9647 0, 9648 Field_imm4_Slot_inst16a_set, 9649 0, 9650 Field_i_Slot_inst16a_set, 9651 Field_imm6lo_Slot_inst16a_set, 9652 Field_imm6hi_Slot_inst16a_set, 9653 Field_imm7lo_Slot_inst16a_set, 9654 Field_imm7hi_Slot_inst16a_set, 9655 Field_z_Slot_inst16a_set, 9656 Field_imm6_Slot_inst16a_set, 9657 Field_imm7_Slot_inst16a_set, 9658 Implicit_Field_set, 9659 Implicit_Field_set, 9660 Implicit_Field_set, 9661 Implicit_Field_set 9662 }; 9663 9664 static xtensa_get_field_fn 9665 Slot_inst16b_get_field_fns[] = { 9666 Field_t_Slot_inst16b_get, 9667 0, 9668 0, 9669 0, 9670 0, 9671 Field_s_Slot_inst16b_get, 9672 0, 9673 0, 9674 0, 9675 0, 9676 0, 9677 Field_op0_Slot_inst16b_get, 9678 0, 9679 0, 9680 Field_r_Slot_inst16b_get, 9681 0, 9682 0, 9683 0, 9684 0, 9685 0, 9686 0, 9687 0, 9688 Field_sr_Slot_inst16b_get, 9689 Field_st_Slot_inst16b_get, 9690 0, 9691 Field_imm4_Slot_inst16b_get, 9692 0, 9693 Field_i_Slot_inst16b_get, 9694 Field_imm6lo_Slot_inst16b_get, 9695 Field_imm6hi_Slot_inst16b_get, 9696 Field_imm7lo_Slot_inst16b_get, 9697 Field_imm7hi_Slot_inst16b_get, 9698 Field_z_Slot_inst16b_get, 9699 Field_imm6_Slot_inst16b_get, 9700 Field_imm7_Slot_inst16b_get, 9701 Implicit_Field_ar0_get, 9702 Implicit_Field_ar4_get, 9703 Implicit_Field_ar8_get, 9704 Implicit_Field_ar12_get 9705 }; 9706 9707 static xtensa_set_field_fn 9708 Slot_inst16b_set_field_fns[] = { 9709 Field_t_Slot_inst16b_set, 9710 0, 9711 0, 9712 0, 9713 0, 9714 Field_s_Slot_inst16b_set, 9715 0, 9716 0, 9717 0, 9718 0, 9719 0, 9720 Field_op0_Slot_inst16b_set, 9721 0, 9722 0, 9723 Field_r_Slot_inst16b_set, 9724 0, 9725 0, 9726 0, 9727 0, 9728 0, 9729 0, 9730 0, 9731 Field_sr_Slot_inst16b_set, 9732 Field_st_Slot_inst16b_set, 9733 0, 9734 Field_imm4_Slot_inst16b_set, 9735 0, 9736 Field_i_Slot_inst16b_set, 9737 Field_imm6lo_Slot_inst16b_set, 9738 Field_imm6hi_Slot_inst16b_set, 9739 Field_imm7lo_Slot_inst16b_set, 9740 Field_imm7hi_Slot_inst16b_set, 9741 Field_z_Slot_inst16b_set, 9742 Field_imm6_Slot_inst16b_set, 9743 Field_imm7_Slot_inst16b_set, 9744 Implicit_Field_set, 9745 Implicit_Field_set, 9746 Implicit_Field_set, 9747 Implicit_Field_set 9748 }; 9749 9750 static xtensa_slot_internal slots[] = { 9751 { "Inst", "x24", 0, 9752 Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, 9753 Slot_inst_get_field_fns, Slot_inst_set_field_fns, 9754 Slot_inst_decode, "nop" }, 9755 { "Inst16a", "x16a", 0, 9756 Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, 9757 Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, 9758 Slot_inst16a_decode, "" }, 9759 { "Inst16b", "x16b", 0, 9760 Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, 9761 Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, 9762 Slot_inst16b_decode, "nop.n" } 9763 }; 9764 9765 9766 /* Instruction formats. */ 9768 9769 static void 9770 Format_x24_encode (xtensa_insnbuf insn) 9771 { 9772 insn[0] = 0; 9773 } 9774 9775 static void 9776 Format_x16a_encode (xtensa_insnbuf insn) 9777 { 9778 insn[0] = 0x800000; 9779 } 9780 9781 static void 9782 Format_x16b_encode (xtensa_insnbuf insn) 9783 { 9784 insn[0] = 0xc00000; 9785 } 9786 9787 static int Format_x24_slots[] = { 0 }; 9788 9789 static int Format_x16a_slots[] = { 1 }; 9790 9791 static int Format_x16b_slots[] = { 2 }; 9792 9793 static xtensa_format_internal formats[] = { 9794 { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, 9795 { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, 9796 { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots } 9797 }; 9798 9799 9800 static int 9801 format_decoder (const xtensa_insnbuf insn) 9802 { 9803 if ((insn[0] & 0x800000) == 0) 9804 return 0; /* x24 */ 9805 if ((insn[0] & 0xc00000) == 0x800000) 9806 return 1; /* x16a */ 9807 if ((insn[0] & 0xe00000) == 0xc00000) 9808 return 2; /* x16b */ 9809 return -1; 9810 } 9811 9812 static int length_table[16] = { 9813 3, 9814 3, 9815 3, 9816 3, 9817 3, 9818 3, 9819 3, 9820 3, 9821 2, 9822 2, 9823 2, 9824 2, 9825 2, 9826 2, 9827 -1, 9828 -1 9829 }; 9830 9831 static int 9832 length_decoder (const unsigned char *insn) 9833 { 9834 int op0 = (insn[0] >> 4) & 0xf; 9835 return length_table[op0]; 9836 } 9837 9838 9839 /* Top-level ISA structure. */ 9841 9842 xtensa_isa_internal xtensa_modules = { 9843 1 /* big-endian */, 9844 3 /* insn_size */, 0, 9845 3, formats, format_decoder, length_decoder, 9846 3, slots, 9847 39 /* num_fields */, 9848 70, operands, 9849 235, iclasses, 9850 291, opcodes, 0, 9851 1, regfiles, 9852 NUM_STATES, states, 0, 9853 NUM_SYSREGS, sysregs, 0, 9854 { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, 9855 0, interfaces, 0, 9856 0, funcUnits, 0 9857 }; 9858
Indexes created Tue Oct 27 00:25:24 UTC 2026