tc-bpf.c revision 1.1.1.3
1 /* tc-bpf.c -- Assembler for the Linux eBPF. 2 Copyright (C) 2019-2024 Free Software Foundation, Inc. 3 Contributed by Oracle, Inc. 4 5 This file is part of GAS, the GNU Assembler. 6 7 GAS is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GAS is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GAS; see the file COPYING. If not, write to 19 the Free Software Foundation, 51 Franklin Street - Fifth Floor, 20 Boston, MA 02110-1301, USA. */ 21 22 #include "as.h" 23 #include "subsegs.h" 24 #include "symcat.h" 25 #include "opcode/bpf.h" 26 #include "elf/common.h" 27 #include "elf/bpf.h" 28 #include "dwarf2dbg.h" 29 #include "libiberty.h" 30 #include <ctype.h> 31 32 /* Data structure representing a parsed BPF instruction. */ 33 34 struct bpf_insn 35 { 36 enum bpf_insn_id id; 37 int size; /* Instruction size in bytes. */ 38 bpf_insn_word opcode; 39 uint8_t dst; 40 uint8_t src; 41 expressionS offset16; 42 expressionS imm32; 43 expressionS imm64; 44 expressionS disp16; 45 expressionS disp32; 46 47 unsigned int has_dst : 1; 48 unsigned int has_src : 1; 49 unsigned int has_offset16 : 1; 50 unsigned int has_disp16 : 1; 51 unsigned int has_disp32 : 1; 52 unsigned int has_imm32 : 1; 53 unsigned int has_imm64 : 1; 54 55 unsigned int is_relaxable : 1; 56 expressionS *relaxed_exp; 57 }; 58 59 const char comment_chars[] = "#"; 60 const char line_comment_chars[] = "#"; 61 const char line_separator_chars[] = ";`"; 62 const char EXP_CHARS[] = "eE"; 63 const char FLT_CHARS[] = "fFdD"; 64 65 /* Like s_lcomm_internal in gas/read.c but the alignment string 66 is allowed to be optional. */ 67 68 static symbolS * 69 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) 70 { 71 addressT align = 0; 72 73 SKIP_WHITESPACE (); 74 75 if (needs_align 76 && *input_line_pointer == ',') 77 { 78 align = parse_align (needs_align - 1); 79 80 if (align == (addressT) -1) 81 return NULL; 82 } 83 else 84 { 85 if (size >= 8) 86 align = 3; 87 else if (size >= 4) 88 align = 2; 89 else if (size >= 2) 90 align = 1; 91 else 92 align = 0; 93 } 94 95 bss_alloc (symbolP, size, align); 96 return symbolP; 97 } 98 99 static void 100 pe_lcomm (int needs_align) 101 { 102 s_comm_internal (needs_align * 2, pe_lcomm_internal); 103 } 104 105 /* The target specific pseudo-ops which we support. */ 106 const pseudo_typeS md_pseudo_table[] = 107 { 108 { "half", cons, 2 }, 109 { "word", cons, 4 }, 110 { "dword", cons, 8 }, 111 { "lcomm", pe_lcomm, 1 }, 112 { NULL, NULL, 0 } 113 }; 114 115 116 118 /* Command-line options processing. */ 119 120 enum options 121 { 122 OPTION_LITTLE_ENDIAN = OPTION_MD_BASE, 123 OPTION_BIG_ENDIAN, 124 OPTION_XBPF, 125 OPTION_DIALECT, 126 OPTION_ISA_SPEC, 127 OPTION_NO_RELAX, 128 }; 129 130 struct option md_longopts[] = 131 { 132 { "EL", no_argument, NULL, OPTION_LITTLE_ENDIAN }, 133 { "EB", no_argument, NULL, OPTION_BIG_ENDIAN }, 134 { "mxbpf", no_argument, NULL, OPTION_XBPF }, 135 { "mdialect", required_argument, NULL, OPTION_DIALECT}, 136 { "misa-spec", required_argument, NULL, OPTION_ISA_SPEC}, 137 { "mno-relax", no_argument, NULL, OPTION_NO_RELAX}, 138 { NULL, no_argument, NULL, 0 }, 139 }; 140 141 size_t md_longopts_size = sizeof (md_longopts); 142 143 const char * md_shortopts = ""; 144 145 /* BPF supports little-endian and big-endian variants. The following 146 global records what endianness to use. It can be configured using 147 command-line options. It defaults to the host endianness 148 initialized in md_begin. */ 149 150 static int set_target_endian = 0; 151 extern int target_big_endian; 152 153 /* Whether to relax branch instructions. Default is yes. Can be 154 changed using the -mno-relax command line option. */ 155 156 static int do_relax = 1; 157 158 /* The ISA specification can be one of BPF_V1, BPF_V2, BPF_V3, BPF_V4 159 or BPF_XPBF. The ISA spec to use can be configured using 160 command-line options. It defaults to the latest BPF spec. */ 161 162 static int isa_spec = BPF_V4; 163 164 /* The assembler supports two different dialects: "normal" syntax and 165 "pseudoc" syntax. The dialect to use can be configured using 166 command-line options. */ 167 168 enum target_asm_dialect 169 { 170 DIALECT_NORMAL, 171 DIALECT_PSEUDOC 172 }; 173 174 static int asm_dialect = DIALECT_NORMAL; 175 176 int 177 md_parse_option (int c, const char * arg) 178 { 179 switch (c) 180 { 181 case OPTION_BIG_ENDIAN: 182 set_target_endian = 1; 183 target_big_endian = 1; 184 break; 185 case OPTION_LITTLE_ENDIAN: 186 set_target_endian = 0; 187 target_big_endian = 0; 188 break; 189 case OPTION_DIALECT: 190 if (strcmp (arg, "normal") == 0) 191 asm_dialect = DIALECT_NORMAL; 192 else if (strcmp (arg, "pseudoc") == 0) 193 asm_dialect = DIALECT_PSEUDOC; 194 else 195 as_fatal (_("-mdialect=%s is not valid. Expected normal or pseudoc"), 196 arg); 197 break; 198 case OPTION_ISA_SPEC: 199 if (strcmp (arg, "v1") == 0) 200 isa_spec = BPF_V1; 201 else if (strcmp (arg, "v2") == 0) 202 isa_spec = BPF_V2; 203 else if (strcmp (arg, "v3") == 0) 204 isa_spec = BPF_V3; 205 else if (strcmp (arg, "v4") == 0) 206 isa_spec = BPF_V4; 207 else if (strcmp (arg, "xbpf") == 0) 208 isa_spec = BPF_XBPF; 209 else 210 as_fatal (_("-misa-spec=%s is not valid. Expected v1, v2, v3, v4 o xbpf"), 211 arg); 212 break; 213 case OPTION_XBPF: 214 /* This is an alias for -misa-spec=xbpf. */ 215 isa_spec = BPF_XBPF; 216 break; 217 case OPTION_NO_RELAX: 218 do_relax = 0; 219 break; 220 default: 221 return 0; 222 } 223 224 return 1; 225 } 226 227 void 228 md_show_usage (FILE * stream) 229 { 230 fprintf (stream, _("\nBPF options:\n")); 231 fprintf (stream, _("\ 232 BPF options:\n\ 233 -EL generate code for a little endian machine\n\ 234 -EB generate code for a big endian machine\n\ 235 -mdialect=DIALECT set the assembly dialect (normal, pseudoc)\n\ 236 -misa-spec set the BPF ISA spec (v1, v2, v3, v4, xbpf)\n\ 237 -mxbpf alias for -misa-spec=xbpf\n")); 238 } 239 240 241 /* This function is called once, at assembler startup time. This 243 should set up all the tables, etc that the MD part of the assembler 244 needs. */ 245 246 void 247 md_begin (void) 248 { 249 /* If not specified in the command line, use the host 250 endianness. */ 251 if (!set_target_endian) 252 { 253 #ifdef WORDS_BIGENDIAN 254 target_big_endian = 1; 255 #else 256 target_big_endian = 0; 257 #endif 258 } 259 260 /* Ensure that lines can begin with '*' in BPF store pseudoc instruction. */ 261 lex_type['*'] |= LEX_BEGIN_NAME; 262 263 /* Set the machine type. */ 264 bfd_default_set_arch_mach (stdoutput, bfd_arch_bpf, bfd_mach_bpf); 265 } 266 267 /* Round up a section size to the appropriate boundary. */ 268 269 valueT 270 md_section_align (segT segment, valueT size) 271 { 272 int align = bfd_section_alignment (segment); 273 274 return ((size + (1 << align) - 1) & -(1 << align)); 275 } 276 277 /* Return non-zero if the indicated VALUE has overflowed the maximum 278 range expressible by an signed number with the indicated number of 279 BITS. */ 280 281 static bool 282 signed_overflow (offsetT value, unsigned bits) 283 { 284 offsetT lim; 285 if (bits >= sizeof (offsetT) * 8) 286 return false; 287 lim = (offsetT) 1 << (bits - 1); 288 return (value < -lim || value >= lim); 289 } 290 291 /* Return non-zero if the two's complement encoding of VALUE would 292 overflow an immediate field of width BITS bits. */ 293 294 static bool 295 immediate_overflow (int64_t value, unsigned bits) 296 { 297 if (value < 0) 298 return signed_overflow (value, bits); 299 else 300 { 301 valueT lim; 302 303 if (bits >= sizeof (valueT) * 8) 304 return false; 305 306 lim = (valueT) 1 << bits; 307 return ((valueT) value >= lim); 308 } 309 } 310 311 312 /* Functions concerning relocs. */ 314 315 /* The location from which a PC relative jump should be calculated, 316 given a PC relative reloc. */ 317 318 long 319 md_pcrel_from_section (fixS *fixP, segT sec) 320 { 321 if (fixP->fx_addsy != (symbolS *) NULL 322 && (! S_IS_DEFINED (fixP->fx_addsy) 323 || (S_GET_SEGMENT (fixP->fx_addsy) != sec) 324 || S_IS_EXTERNAL (fixP->fx_addsy) 325 || S_IS_WEAK (fixP->fx_addsy))) 326 { 327 /* The symbol is undefined (or is defined but not in this section). 328 Let the linker figure it out. */ 329 return 0; 330 } 331 332 return fixP->fx_where + fixP->fx_frag->fr_address; 333 } 334 335 /* Write a value out to the object file, using the appropriate endianness. */ 336 337 void 338 md_number_to_chars (char * buf, valueT val, int n) 339 { 340 if (target_big_endian) 341 number_to_chars_bigendian (buf, val, n); 342 else 343 number_to_chars_littleendian (buf, val, n); 344 } 345 346 arelent * 347 tc_gen_reloc (asection *sec ATTRIBUTE_UNUSED, fixS *fixP) 348 { 349 bfd_reloc_code_real_type r_type = fixP->fx_r_type; 350 arelent *reloc; 351 352 reloc = XNEW (arelent); 353 354 if (fixP->fx_pcrel) 355 { 356 r_type = (r_type == BFD_RELOC_8 ? BFD_RELOC_8_PCREL 357 : r_type == BFD_RELOC_16 ? BFD_RELOC_16_PCREL 358 : r_type == BFD_RELOC_24 ? BFD_RELOC_24_PCREL 359 : r_type == BFD_RELOC_32 ? BFD_RELOC_32_PCREL 360 : r_type == BFD_RELOC_64 ? BFD_RELOC_64_PCREL 361 : r_type); 362 } 363 364 reloc->howto = bfd_reloc_type_lookup (stdoutput, r_type); 365 366 if (reloc->howto == (reloc_howto_type *) NULL) 367 { 368 as_bad_where (fixP->fx_file, fixP->fx_line, 369 _("relocation is not supported")); 370 return NULL; 371 } 372 373 //XXX gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative); 374 375 reloc->sym_ptr_ptr = XNEW (asymbol *); 376 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy); 377 378 /* Use fx_offset for these cases. */ 379 if (fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY 380 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT) 381 reloc->addend = fixP->fx_offset; 382 else 383 reloc->addend = fixP->fx_addnumber; 384 385 reloc->address = fixP->fx_frag->fr_address + fixP->fx_where; 386 return reloc; 387 } 388 389 390 /* Relaxations supported by this assembler. */ 392 393 #define RELAX_BRANCH_ENCODE(uncond, constant, length) \ 394 ((relax_substateT) \ 395 (0xc0000000 \ 396 | ((uncond) ? 1 : 0) \ 397 | ((constant) ? 2 : 0) \ 398 | ((length) << 2))) 399 400 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) 401 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xff) 402 #define RELAX_BRANCH_CONST(i) (((i) & 2) != 0) 403 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0) 404 405 406 /* Compute the length of a branch sequence, and adjust the stored 407 length accordingly. If FRAG is NULL, the worst-case length is 408 returned. */ 409 410 static unsigned 411 relaxed_branch_length (fragS *fragp, asection *sec, int update) 412 { 413 int length, uncond; 414 415 if (!fragp) 416 return 8 * 3; 417 418 uncond = RELAX_BRANCH_UNCOND (fragp->fr_subtype); 419 length = RELAX_BRANCH_LENGTH (fragp->fr_subtype); 420 421 if (uncond) 422 /* Length is the same for both JA and JAL. */ 423 length = 8; 424 else 425 { 426 if (RELAX_BRANCH_CONST (fragp->fr_subtype)) 427 { 428 int64_t val = fragp->fr_offset; 429 430 if (val < -32768 || val > 32767) 431 length = 8 * 3; 432 else 433 length = 8; 434 } 435 else if (fragp->fr_symbol != NULL 436 && S_IS_DEFINED (fragp->fr_symbol) 437 && !S_IS_WEAK (fragp->fr_symbol) 438 && sec == S_GET_SEGMENT (fragp->fr_symbol)) 439 { 440 offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; 441 442 /* Convert to 64-bit words, minus one. */ 443 val = (val - 8) / 8; 444 445 /* See if it fits in the signed 16-bits field. */ 446 if (val < -32768 || val > 32767) 447 length = 8 * 3; 448 else 449 length = 8; 450 } 451 else 452 /* Use short version, and let the linker relax instead, if 453 appropriate and if supported. */ 454 length = 8; 455 } 456 457 if (update) 458 fragp->fr_subtype = RELAX_BRANCH_ENCODE (uncond, 459 RELAX_BRANCH_CONST (fragp->fr_subtype), 460 length); 461 462 return length; 463 } 464 465 /* Estimate the size of a variant frag before relaxing. */ 466 467 int 468 md_estimate_size_before_relax (fragS *fragp, asection *sec) 469 { 470 return (fragp->fr_var = relaxed_branch_length (fragp, sec, true)); 471 } 472 473 /* Read a BPF instruction word from BUF. */ 474 475 static uint64_t 476 read_insn_word (bfd_byte *buf) 477 { 478 return bfd_getb64 (buf); 479 } 480 481 /* Write the given signed 16-bit value in the given BUFFER using the 482 target endianness. */ 483 484 static void 485 encode_int16 (int16_t value, char *buffer) 486 { 487 uint16_t val = value; 488 489 if (target_big_endian) 490 { 491 buffer[0] = (val >> 8) & 0xff; 492 buffer[1] = val & 0xff; 493 } 494 else 495 { 496 buffer[1] = (val >> 8) & 0xff; 497 buffer[0] = val & 0xff; 498 } 499 } 500 501 /* Write the given signed 32-bit value in the given BUFFER using the 502 target endianness. */ 503 504 static void 505 encode_int32 (int32_t value, char *buffer) 506 { 507 uint32_t val = value; 508 509 if (target_big_endian) 510 { 511 buffer[0] = (val >> 24) & 0xff; 512 buffer[1] = (val >> 16) & 0xff; 513 buffer[2] = (val >> 8) & 0xff; 514 buffer[3] = val & 0xff; 515 } 516 else 517 { 518 buffer[3] = (val >> 24) & 0xff; 519 buffer[2] = (val >> 16) & 0xff; 520 buffer[1] = (val >> 8) & 0xff; 521 buffer[0] = value & 0xff; 522 } 523 } 524 525 /* Write a BPF instruction to BUF. */ 526 527 static void 528 write_insn_bytes (bfd_byte *buf, char *bytes) 529 { 530 int i; 531 532 for (i = 0; i < 8; ++i) 533 md_number_to_chars ((char *) buf + i, (valueT) bytes[i], 1); 534 } 535 536 /* *FRAGP has been relaxed to its final size, and now needs to have 537 the bytes inside it modified to conform to the new size. 538 539 Called after relaxation is finished. 540 fragP->fr_type == rs_machine_dependent. 541 fragP->fr_subtype is the subtype of what the address relaxed to. */ 542 543 void 544 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, 545 segT sec ATTRIBUTE_UNUSED, 546 fragS *fragp ATTRIBUTE_UNUSED) 547 { 548 bfd_byte *buf = (bfd_byte *) fragp->fr_literal + fragp->fr_fix; 549 expressionS exp; 550 fixS *fixp; 551 bpf_insn_word word; 552 int disp_is_known = 0; 553 int64_t disp_to_target = 0; 554 555 uint64_t code; 556 557 gas_assert (RELAX_BRANCH_P (fragp->fr_subtype)); 558 559 /* Expression to be used in any resulting relocation in the relaxed 560 instructions. */ 561 exp.X_op = O_symbol; 562 exp.X_add_symbol = fragp->fr_symbol; 563 exp.X_add_number = fragp->fr_offset; 564 565 gas_assert (fragp->fr_var == RELAX_BRANCH_LENGTH (fragp->fr_subtype)); 566 567 /* Read an instruction word from the instruction to be relaxed, and 568 get the code. */ 569 word = read_insn_word (buf); 570 code = (word >> 60) & 0xf; 571 572 /* Determine whether the 16-bit displacement to the target is known 573 at this point. */ 574 if (RELAX_BRANCH_CONST (fragp->fr_subtype)) 575 { 576 disp_to_target = fragp->fr_offset; 577 disp_is_known = 1; 578 } 579 else if (fragp->fr_symbol != NULL 580 && S_IS_DEFINED (fragp->fr_symbol) 581 && !S_IS_WEAK (fragp->fr_symbol) 582 && sec == S_GET_SEGMENT (fragp->fr_symbol)) 583 { 584 offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; 585 /* Convert to 64-bit blocks minus one. */ 586 disp_to_target = (val - 8) / 8; 587 disp_is_known = 1; 588 } 589 590 /* The displacement should fit in a signed 32-bit number. */ 591 if (disp_is_known && signed_overflow (disp_to_target, 32)) 592 as_bad_where (fragp->fr_file, fragp->fr_line, 593 _("signed instruction operand out of range, shall fit in 32 bits")); 594 595 /* Now relax particular jump instructions. */ 596 if (code == BPF_CODE_JA) 597 { 598 /* Unconditional jump. 599 JA d16 -> JAL d32 */ 600 601 gas_assert (RELAX_BRANCH_UNCOND (fragp->fr_subtype)); 602 603 if (disp_is_known) 604 { 605 if (disp_to_target >= -32768 && disp_to_target <= 32767) 606 { 607 /* 16-bit disp is known and in range. Install a fixup 608 for the disp16 if the branch value is not constant. 609 This will be resolved by the assembler and units 610 converted. */ 611 612 if (!RELAX_BRANCH_CONST (fragp->fr_subtype)) 613 { 614 /* Install fixup for the JA. */ 615 reloc_howto_type *reloc_howto 616 = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_BPF_DISP16); 617 if (!reloc_howto) 618 abort(); 619 620 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal, 621 bfd_get_reloc_size (reloc_howto), 622 &exp, 623 reloc_howto->pc_relative, 624 BFD_RELOC_BPF_DISP16); 625 fixp->fx_file = fragp->fr_file; 626 fixp->fx_line = fragp->fr_line; 627 } 628 } 629 else 630 { 631 /* 16-bit disp is known and not in range. Turn the JA 632 into a JAL with a 32-bit displacement. */ 633 char bytes[8]; 634 635 bytes[0] = ((BPF_CLASS_JMP32|BPF_CODE_JA|BPF_SRC_K) >> 56) & 0xff; 636 bytes[1] = (word >> 48) & 0xff; 637 bytes[2] = 0; /* disp16 high */ 638 bytes[3] = 0; /* disp16 lo */ 639 encode_int32 ((int32_t) disp_to_target, bytes + 4); 640 641 write_insn_bytes (buf, bytes); 642 } 643 } 644 else 645 { 646 /* The displacement to the target is not known. Do not 647 relax. The linker will maybe do it if it chooses to. */ 648 649 reloc_howto_type *reloc_howto = NULL; 650 651 gas_assert (!RELAX_BRANCH_CONST (fragp->fr_subtype)); 652 653 /* Install fixup for the JA. */ 654 reloc_howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_BPF_DISP16); 655 if (!reloc_howto) 656 abort (); 657 658 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal, 659 bfd_get_reloc_size (reloc_howto), 660 &exp, 661 reloc_howto->pc_relative, 662 BFD_RELOC_BPF_DISP16); 663 fixp->fx_file = fragp->fr_file; 664 fixp->fx_line = fragp->fr_line; 665 } 666 667 buf += 8; 668 } 669 else 670 { 671 /* Conditional jump. 672 JXX d16 -> JXX +1; JA +1; JAL d32 */ 673 674 gas_assert (!RELAX_BRANCH_UNCOND (fragp->fr_subtype)); 675 676 if (disp_is_known) 677 { 678 if (disp_to_target >= -32768 && disp_to_target <= 32767) 679 { 680 /* 16-bit disp is known and in range. Install a fixup 681 for the disp16 if the branch value is not constant. 682 This will be resolved by the assembler and units 683 converted. */ 684 685 if (!RELAX_BRANCH_CONST (fragp->fr_subtype)) 686 { 687 /* Install fixup for the branch. */ 688 reloc_howto_type *reloc_howto 689 = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_BPF_DISP16); 690 if (!reloc_howto) 691 abort(); 692 693 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal, 694 bfd_get_reloc_size (reloc_howto), 695 &exp, 696 reloc_howto->pc_relative, 697 BFD_RELOC_BPF_DISP16); 698 fixp->fx_file = fragp->fr_file; 699 fixp->fx_line = fragp->fr_line; 700 } 701 702 buf += 8; 703 } 704 else 705 { 706 /* 16-bit disp is known and not in range. Turn the JXX 707 into a sequence JXX +1; JA +1; JAL d32. */ 708 709 char bytes[8]; 710 711 /* First, set the 16-bit offset in the current 712 instruction to 1. */ 713 714 if (target_big_endian) 715 bfd_putb16 (1, buf + 2); 716 else 717 bfd_putl16 (1, buf + 2); 718 buf += 8; 719 720 /* Then, write the JA + 1 */ 721 722 bytes[0] = 0x05; /* JA */ 723 bytes[1] = 0x0; 724 encode_int16 (1, bytes + 2); 725 bytes[4] = 0x0; 726 bytes[5] = 0x0; 727 bytes[6] = 0x0; 728 bytes[7] = 0x0; 729 write_insn_bytes (buf, bytes); 730 buf += 8; 731 732 /* Finally, write the JAL to the target. */ 733 734 bytes[0] = ((BPF_CLASS_JMP32|BPF_CODE_JA|BPF_SRC_K) >> 56) & 0xff; 735 bytes[1] = 0; 736 bytes[2] = 0; 737 bytes[3] = 0; 738 encode_int32 ((int32_t) disp_to_target, bytes + 4); 739 write_insn_bytes (buf, bytes); 740 buf += 8; 741 } 742 } 743 else 744 { 745 /* The displacement to the target is not known. Do not 746 relax. The linker will maybe do it if it chooses to. */ 747 748 reloc_howto_type *reloc_howto = NULL; 749 750 gas_assert (!RELAX_BRANCH_CONST (fragp->fr_subtype)); 751 752 /* Install fixup for the conditional jump. */ 753 reloc_howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_BPF_DISP16); 754 if (!reloc_howto) 755 abort (); 756 757 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal, 758 bfd_get_reloc_size (reloc_howto), 759 &exp, 760 reloc_howto->pc_relative, 761 BFD_RELOC_BPF_DISP16); 762 fixp->fx_file = fragp->fr_file; 763 fixp->fx_line = fragp->fr_line; 764 buf += 8; 765 } 766 } 767 768 gas_assert (buf == (bfd_byte *)fragp->fr_literal 769 + fragp->fr_fix + fragp->fr_var); 770 771 fragp->fr_fix += fragp->fr_var; 772 } 773 774 775 /* Apply a fixS (fixup of an instruction or data that we didn't have 777 enough info to complete immediately) to the data in a frag. */ 778 779 void 780 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) 781 { 782 char *where = fixP->fx_frag->fr_literal + fixP->fx_where; 783 784 switch (fixP->fx_r_type) 785 { 786 case BFD_RELOC_BPF_DISP16: 787 /* Convert from bytes to number of 64-bit words to the target, 788 minus one. */ 789 *valP = (((long) (*valP)) - 8) / 8; 790 break; 791 case BFD_RELOC_BPF_DISPCALL32: 792 case BFD_RELOC_BPF_DISP32: 793 /* Convert from bytes to number of 64-bit words to the target, 794 minus one. */ 795 *valP = (((long) (*valP)) - 8) / 8; 796 797 if (fixP->fx_r_type == BFD_RELOC_BPF_DISPCALL32) 798 { 799 /* eBPF supports two kind of CALL instructions: the so 800 called pseudo calls ("bpf to bpf") and external calls 801 ("bpf to kernel"). 802 803 Both kind of calls use the same instruction (CALL). 804 However, external calls are constructed by passing a 805 constant argument to the instruction, whereas pseudo 806 calls result from expressions involving symbols. In 807 practice, instructions requiring a fixup are interpreted 808 as pseudo-calls. If we are executing this code, this is 809 a pseudo call. 810 811 The kernel expects for pseudo-calls to be annotated by 812 having BPF_PSEUDO_CALL in the SRC field of the 813 instruction. But beware the infamous nibble-swapping of 814 eBPF and take endianness into account here. 815 816 Note that the CALL instruction has only one operand, so 817 this code is executed only once per instruction. */ 818 md_number_to_chars (where + 1, target_big_endian ? 0x01 : 0x10, 1); 819 } 820 break; 821 case BFD_RELOC_16_PCREL: 822 /* Convert from bytes to number of 64-bit words to the target, 823 minus one. */ 824 *valP = (((long) (*valP)) - 8) / 8; 825 break; 826 default: 827 break; 828 } 829 830 if (fixP->fx_addsy == (symbolS *) NULL) 831 fixP->fx_done = 1; 832 833 if (fixP->fx_done) 834 { 835 /* We're finished with this fixup. Install it because 836 bfd_install_relocation won't be called to do it. */ 837 switch (fixP->fx_r_type) 838 { 839 case BFD_RELOC_8: 840 md_number_to_chars (where, *valP, 1); 841 break; 842 case BFD_RELOC_16: 843 md_number_to_chars (where, *valP, 2); 844 break; 845 case BFD_RELOC_32: 846 md_number_to_chars (where, *valP, 4); 847 break; 848 case BFD_RELOC_64: 849 md_number_to_chars (where, *valP, 8); 850 break; 851 case BFD_RELOC_BPF_DISP16: 852 md_number_to_chars (where + 2, (uint16_t) *valP, 2); 853 break; 854 case BFD_RELOC_BPF_DISP32: 855 case BFD_RELOC_BPF_DISPCALL32: 856 md_number_to_chars (where + 4, (uint32_t) *valP, 4); 857 break; 858 case BFD_RELOC_16_PCREL: 859 md_number_to_chars (where + 2, (uint32_t) *valP, 2); 860 break; 861 default: 862 as_bad_where (fixP->fx_file, fixP->fx_line, 863 _("internal error: can't install fix for reloc type %d (`%s')"), 864 fixP->fx_r_type, bfd_get_reloc_code_name (fixP->fx_r_type)); 865 break; 866 } 867 } 868 869 /* Tuck `value' away for use by tc_gen_reloc. 870 See the comment describing fx_addnumber in write.h. 871 This field is misnamed (or misused :-). */ 872 fixP->fx_addnumber = *valP; 873 } 874 875 876 /* Instruction writing routines. */ 878 879 /* Encode a BPF instruction in the given buffer BYTES. Non-constant 880 immediates are encoded as zeroes. */ 881 882 static void 883 encode_insn (struct bpf_insn *insn, char *bytes, 884 int relaxed ATTRIBUTE_UNUSED) 885 { 886 uint8_t src, dst; 887 888 /* Zero all the bytes. */ 889 memset (bytes, 0, 16); 890 891 /* First encode the opcodes. Note that we have to handle the 892 endianness groups of the BPF instructions: 8 | 4 | 4 | 16 | 893 32. */ 894 if (target_big_endian) 895 { 896 /* code */ 897 bytes[0] = (insn->opcode >> 56) & 0xff; 898 /* regs */ 899 bytes[1] = (insn->opcode >> 48) & 0xff; 900 /* offset16 */ 901 bytes[2] = (insn->opcode >> 40) & 0xff; 902 bytes[3] = (insn->opcode >> 32) & 0xff; 903 /* imm32 */ 904 bytes[4] = (insn->opcode >> 24) & 0xff; 905 bytes[5] = (insn->opcode >> 16) & 0xff; 906 bytes[6] = (insn->opcode >> 8) & 0xff; 907 bytes[7] = insn->opcode & 0xff; 908 } 909 else 910 { 911 /* code */ 912 bytes[0] = (insn->opcode >> 56) & 0xff; 913 /* regs */ 914 bytes[1] = (((((insn->opcode >> 48) & 0xff) & 0xf) << 4) 915 | (((insn->opcode >> 48) & 0xff) & 0xf)); 916 /* offset16 */ 917 bytes[3] = (insn->opcode >> 40) & 0xff; 918 bytes[2] = (insn->opcode >> 32) & 0xff; 919 /* imm32 */ 920 bytes[7] = (insn->opcode >> 24) & 0xff; 921 bytes[6] = (insn->opcode >> 16) & 0xff; 922 bytes[5] = (insn->opcode >> 8) & 0xff; 923 bytes[4] = insn->opcode & 0xff; 924 } 925 926 /* Now the registers. */ 927 src = insn->has_src ? insn->src : 0; 928 dst = insn->has_dst ? insn->dst : 0; 929 930 if (target_big_endian) 931 bytes[1] = ((dst & 0xf) << 4) | (src & 0xf); 932 else 933 bytes[1] = ((src & 0xf) << 4) | (dst & 0xf); 934 935 /* Now the immediates that are known to be constant. */ 936 937 if (insn->has_imm32 && insn->imm32.X_op == O_constant) 938 { 939 int64_t imm = insn->imm32.X_add_number; 940 941 if (immediate_overflow (imm, 32)) 942 as_bad (_("immediate out of range, shall fit in 32 bits")); 943 else 944 encode_int32 (insn->imm32.X_add_number, bytes + 4); 945 } 946 947 if (insn->has_disp32 && insn->disp32.X_op == O_constant) 948 { 949 int64_t disp = insn->disp32.X_add_number; 950 951 if (immediate_overflow (disp, 32)) 952 as_bad (_("pc-relative offset out of range, shall fit in 32 bits")); 953 else 954 encode_int32 (insn->disp32.X_add_number, bytes + 4); 955 } 956 957 if (insn->has_offset16 && insn->offset16.X_op == O_constant) 958 { 959 int64_t offset = insn->offset16.X_add_number; 960 961 if (immediate_overflow (offset, 16)) 962 as_bad (_("pc-relative offset out of range, shall fit in 16 bits")); 963 else 964 encode_int16 (insn->offset16.X_add_number, bytes + 2); 965 } 966 967 if (insn->has_disp16 && insn->disp16.X_op == O_constant) 968 { 969 int64_t disp = insn->disp16.X_add_number; 970 971 if (immediate_overflow (disp, 16)) 972 as_bad (_("pc-relative offset out of range, shall fit in 16 bits")); 973 else 974 encode_int16 (insn->disp16.X_add_number, bytes + 2); 975 } 976 977 if (insn->has_imm64 && insn->imm64.X_op == O_constant) 978 { 979 uint64_t imm64 = insn->imm64.X_add_number; 980 981 if (target_big_endian) 982 { 983 bytes[12] = (imm64 >> 56) & 0xff; 984 bytes[13] = (imm64 >> 48) & 0xff; 985 bytes[14] = (imm64 >> 40) & 0xff; 986 bytes[15] = (imm64 >> 32) & 0xff; 987 bytes[4] = (imm64 >> 24) & 0xff; 988 bytes[5] = (imm64 >> 16) & 0xff; 989 bytes[6] = (imm64 >> 8) & 0xff; 990 bytes[7] = imm64 & 0xff; 991 } 992 else 993 { 994 bytes[15] = (imm64 >> 56) & 0xff; 995 bytes[14] = (imm64 >> 48) & 0xff; 996 bytes[13] = (imm64 >> 40) & 0xff; 997 bytes[12] = (imm64 >> 32) & 0xff; 998 bytes[7] = (imm64 >> 24) & 0xff; 999 bytes[6] = (imm64 >> 16) & 0xff; 1000 bytes[5] = (imm64 >> 8) & 0xff; 1001 bytes[4] = imm64 & 0xff; 1002 } 1003 } 1004 } 1005 1006 /* Install the fixups in INSN in their proper location in the 1007 specified FRAG at the location pointed by WHERE. */ 1008 1009 static void 1010 install_insn_fixups (struct bpf_insn *insn, fragS *frag, long where) 1011 { 1012 if (insn->has_imm64) 1013 { 1014 switch (insn->imm64.X_op) 1015 { 1016 case O_symbol: 1017 case O_subtract: 1018 case O_add: 1019 { 1020 reloc_howto_type *reloc_howto; 1021 int size; 1022 1023 reloc_howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_BPF_64); 1024 if (!reloc_howto) 1025 abort (); 1026 1027 size = bfd_get_reloc_size (reloc_howto); 1028 1029 fix_new_exp (frag, where, 1030 size, &insn->imm64, reloc_howto->pc_relative, 1031 BFD_RELOC_BPF_64); 1032 break; 1033 } 1034 case O_constant: 1035 /* Already handled in encode_insn. */ 1036 break; 1037 default: 1038 abort (); 1039 } 1040 } 1041 1042 if (insn->has_imm32) 1043 { 1044 switch (insn->imm32.X_op) 1045 { 1046 case O_symbol: 1047 case O_subtract: 1048 case O_add: 1049 case O_uminus: 1050 { 1051 reloc_howto_type *reloc_howto; 1052 int size; 1053 1054 reloc_howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); 1055 if (!reloc_howto) 1056 abort (); 1057 1058 size = bfd_get_reloc_size (reloc_howto); 1059 1060 fix_new_exp (frag, where + 4, 1061 size, &insn->imm32, reloc_howto->pc_relative, 1062 BFD_RELOC_32); 1063 break; 1064 } 1065 case O_constant: 1066 /* Already handled in encode_insn. */ 1067 break; 1068 default: 1069 abort (); 1070 } 1071 } 1072 1073 if (insn->has_disp32) 1074 { 1075 switch (insn->disp32.X_op) 1076 { 1077 case O_symbol: 1078 case O_subtract: 1079 case O_add: 1080 { 1081 reloc_howto_type *reloc_howto; 1082 int size; 1083 unsigned int bfd_reloc 1084 = (insn->id == BPF_INSN_CALL 1085 ? BFD_RELOC_BPF_DISPCALL32 1086 : BFD_RELOC_BPF_DISP32); 1087 1088 reloc_howto = bfd_reloc_type_lookup (stdoutput, bfd_reloc); 1089 if (!reloc_howto) 1090 abort (); 1091 1092 size = bfd_get_reloc_size (reloc_howto); 1093 1094 fix_new_exp (frag, where, 1095 size, &insn->disp32, reloc_howto->pc_relative, 1096 bfd_reloc); 1097 break; 1098 } 1099 case O_constant: 1100 /* Already handled in encode_insn. */ 1101 break; 1102 default: 1103 abort (); 1104 } 1105 } 1106 1107 if (insn->has_offset16) 1108 { 1109 switch (insn->offset16.X_op) 1110 { 1111 case O_symbol: 1112 case O_subtract: 1113 case O_add: 1114 { 1115 reloc_howto_type *reloc_howto; 1116 int size; 1117 1118 /* XXX we really need a new pc-rel offset in bytes 1119 relocation for this. */ 1120 reloc_howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_BPF_DISP16); 1121 if (!reloc_howto) 1122 abort (); 1123 1124 size = bfd_get_reloc_size (reloc_howto); 1125 1126 fix_new_exp (frag, where, 1127 size, &insn->offset16, reloc_howto->pc_relative, 1128 BFD_RELOC_BPF_DISP16); 1129 break; 1130 } 1131 case O_constant: 1132 /* Already handled in encode_insn. */ 1133 break; 1134 default: 1135 abort (); 1136 } 1137 } 1138 1139 if (insn->has_disp16) 1140 { 1141 switch (insn->disp16.X_op) 1142 { 1143 case O_symbol: 1144 case O_subtract: 1145 case O_add: 1146 { 1147 reloc_howto_type *reloc_howto; 1148 int size; 1149 1150 reloc_howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_BPF_DISP16); 1151 if (!reloc_howto) 1152 abort (); 1153 1154 size = bfd_get_reloc_size (reloc_howto); 1155 1156 fix_new_exp (frag, where, 1157 size, &insn->disp16, reloc_howto->pc_relative, 1158 BFD_RELOC_BPF_DISP16); 1159 break; 1160 } 1161 case O_constant: 1162 /* Already handled in encode_insn. */ 1163 break; 1164 default: 1165 abort (); 1166 } 1167 } 1168 1169 } 1170 1171 /* Add a new insn to the list of instructions. */ 1172 1173 static void 1174 add_fixed_insn (struct bpf_insn *insn) 1175 { 1176 char *this_frag = frag_more (insn->size); 1177 char bytes[16]; 1178 int i; 1179 1180 /* First encode the known parts of the instruction, including 1181 opcodes and constant immediates, and write them to the frag. */ 1182 encode_insn (insn, bytes, 0 /* relax */); 1183 for (i = 0; i < insn->size; ++i) 1184 md_number_to_chars (this_frag + i, (valueT) bytes[i], 1); 1185 1186 /* Now install the instruction fixups. */ 1187 install_insn_fixups (insn, frag_now, 1188 this_frag - frag_now->fr_literal); 1189 } 1190 1191 /* Add a new relaxable to the list of instructions. */ 1192 1193 static void 1194 add_relaxed_insn (struct bpf_insn *insn, expressionS *exp) 1195 { 1196 char bytes[16]; 1197 int i; 1198 char *this_frag; 1199 unsigned worst_case = relaxed_branch_length (NULL, NULL, 0); 1200 unsigned best_case = insn->size; 1201 1202 /* We only support relaxing branches, for the moment. */ 1203 relax_substateT subtype 1204 = RELAX_BRANCH_ENCODE (insn->id == BPF_INSN_JAR, 1205 exp->X_op == O_constant, 1206 worst_case); 1207 1208 frag_grow (worst_case); 1209 this_frag = frag_more (0); 1210 1211 /* First encode the known parts of the instruction, including 1212 opcodes and constant immediates, and write them to the frag. */ 1213 encode_insn (insn, bytes, 1 /* relax */); 1214 for (i = 0; i < insn->size; ++i) 1215 md_number_to_chars (this_frag + i, (valueT) bytes[i], 1); 1216 1217 /* Note that instruction fixups will be applied once the frag is 1218 relaxed, in md_convert_frag. */ 1219 frag_var (rs_machine_dependent, 1220 worst_case, best_case, 1221 subtype, exp->X_add_symbol, exp->X_add_number /* offset */, 1222 NULL); 1223 } 1224 1225 1226 /* Parse an operand expression. Returns the first character that is 1228 not part of the expression, or NULL in case of parse error. 1229 1230 See md_operand below to see how exp_parse_failed is used. */ 1231 1232 static int exp_parse_failed = 0; 1233 static bool parsing_insn_operands = false; 1234 1235 static char * 1236 parse_expression (char *s, expressionS *exp) 1237 { 1238 char *saved_input_line_pointer = input_line_pointer; 1239 char *saved_s = s; 1240 1241 /* Wake up bpf_parse_name before the call to expression (). */ 1242 parsing_insn_operands = true; 1243 1244 exp_parse_failed = 0; 1245 input_line_pointer = s; 1246 expression (exp); 1247 s = input_line_pointer; 1248 input_line_pointer = saved_input_line_pointer; 1249 1250 switch (exp->X_op == O_absent || exp_parse_failed) 1251 return NULL; 1252 1253 /* The expression parser may consume trailing whitespaces. We have 1254 to undo that since the instruction templates may be expecting 1255 these whitespaces. */ 1256 { 1257 char *p; 1258 for (p = s - 1; p >= saved_s && *p == ' '; --p) 1259 --s; 1260 } 1261 1262 return s; 1263 } 1264 1265 /* Parse a BPF register name and return the corresponding register 1266 number. Return NULL in case of parse error, or a pointer to the 1267 first character in S that is not part of the register name. */ 1268 1269 static char * 1270 parse_bpf_register (char *s, char rw, uint8_t *regno) 1271 { 1272 if (asm_dialect == DIALECT_NORMAL) 1273 { 1274 rw = 'r'; 1275 if (*s != '%') 1276 return NULL; 1277 s += 1; 1278 1279 if (*s == 'f' && *(s + 1) == 'p') 1280 { 1281 *regno = 10; 1282 s += 2; 1283 return s; 1284 } 1285 } 1286 1287 if (*s != rw) 1288 return NULL; 1289 s += 1; 1290 1291 if (*s == '1') 1292 { 1293 if (*(s + 1) == '0') 1294 { 1295 *regno = 10; 1296 s += 2; 1297 } 1298 else 1299 { 1300 *regno = 1; 1301 s += 1; 1302 } 1303 } 1304 else if (*s >= '0' && *s <= '9') 1305 { 1306 *regno = *s - '0'; 1307 s += 1; 1308 } 1309 1310 /* If we are still parsing a name, it is not a register. */ 1311 if (is_part_of_name (*s)) 1312 return NULL; 1313 1314 return s; 1315 } 1316 1317 /* Symbols created by this parse, but not yet committed to the real 1318 symbol table. */ 1319 static symbolS *deferred_sym_rootP; 1320 static symbolS *deferred_sym_lastP; 1321 1322 /* Symbols discarded by a previous parse. Symbols cannot easily be freed 1323 after creation, so try to recycle. */ 1324 static symbolS *orphan_sym_rootP; 1325 static symbolS *orphan_sym_lastP; 1326 1327 /* Implement md_parse_name hook. Handles any symbol found in an expression. 1328 This allows us to tentatively create symbols, before we know for sure 1329 whether the parser is using the correct template for an instruction. 1330 If we end up keeping the instruction, the deferred symbols are committed 1331 to the real symbol table. This approach is modeled after the riscv port. */ 1332 1333 bool 1334 bpf_parse_name (const char *name, expressionS *exp, enum expr_mode mode) 1335 { 1336 symbolS *sym; 1337 1338 /* If we aren't currently parsing an instruction, don't do anything. 1339 This prevents tampering with operands to directives. */ 1340 if (!parsing_insn_operands) 1341 return false; 1342 1343 gas_assert (mode == expr_normal); 1344 1345 /* Pseudo-C syntax uses unprefixed register names like r2 or w3. 1346 Since many instructions take either a register or an 1347 immediate/expression, we should not allow references to symbols 1348 with these names in operands. */ 1349 if (asm_dialect == DIALECT_PSEUDOC) 1350 { 1351 uint8_t regno; 1352 1353 if (parse_bpf_register ((char *) name, 'r', ®no) 1354 || parse_bpf_register ((char *) name, 'w', ®no)) 1355 { 1356 as_bad (_("unexpected register name `%s' in expression"), 1357 name); 1358 return false; 1359 } 1360 } 1361 1362 if (symbol_find (name) != NULL) 1363 return false; 1364 1365 for (sym = deferred_sym_rootP; sym; sym = symbol_next (sym)) 1366 if (strcmp (name, S_GET_NAME (sym)) == 0) 1367 break; 1368 1369 /* Tentatively create a symbol. */ 1370 if (!sym) 1371 { 1372 /* See if we can reuse a symbol discarded by a previous parse. 1373 This may be quite common, for example when trying multiple templates 1374 for an instruction with the first reference to a valid symbol. */ 1375 for (sym = orphan_sym_rootP; sym; sym = symbol_next (sym)) 1376 if (strcmp (name, S_GET_NAME (sym)) == 0) 1377 { 1378 symbol_remove (sym, &orphan_sym_rootP, &orphan_sym_lastP); 1379 break; 1380 } 1381 1382 if (!sym) 1383 sym = symbol_create (name, undefined_section, &zero_address_frag, 0); 1384 1385 /* Add symbol to the deferred list. If we commit to the isntruction, 1386 then the symbol will be inserted into to the real symbol table at 1387 that point (in md_assemble). */ 1388 symbol_append (sym, deferred_sym_lastP, &deferred_sym_rootP, 1389 &deferred_sym_lastP); 1390 } 1391 1392 exp->X_op = O_symbol; 1393 exp->X_add_symbol = sym; 1394 exp->X_add_number = 0; 1395 1396 return true; 1397 } 1398 1399 /* Collect a parse error message. */ 1400 1401 static int partial_match_length = 0; 1402 static char *errmsg = NULL; 1403 1404 static void 1405 parse_error (int length, const char *fmt, ...) 1406 { 1407 if (length > partial_match_length) 1408 { 1409 va_list args; 1410 1411 free (errmsg); 1412 va_start (args, fmt); 1413 errmsg = xvasprintf (fmt, args); 1414 va_end (args); 1415 partial_match_length = length; 1416 } 1417 1418 /* Discard deferred symbols from the failed parse. They may potentially 1419 be reused in the future from the orphan list. */ 1420 while (deferred_sym_rootP) 1421 { 1422 symbolS *sym = deferred_sym_rootP; 1423 symbol_remove (sym, &deferred_sym_rootP, &deferred_sym_lastP); 1424 symbol_append (sym, orphan_sym_lastP, &orphan_sym_rootP, 1425 &orphan_sym_lastP); 1426 } 1427 } 1428 1429 /* Assemble a machine instruction in STR and emit the frags/bytes it 1430 assembles to. */ 1431 1432 void 1433 md_assemble (char *str ATTRIBUTE_UNUSED) 1434 { 1435 /* There are two different syntaxes that can be used to write BPF 1436 instructions. One is very conventional and like any other 1437 assembly language where each instruction is conformed by an 1438 instruction mnemonic followed by its operands. This is what we 1439 call the "normal" syntax. The other syntax tries to look like C 1440 statements. We have to support both syntaxes in this assembler. 1441 1442 One of the many nuisances introduced by this eccentricity is that 1443 in the pseudo-c syntax it is not possible to hash the opcodes 1444 table by instruction mnemonic, because there is none. So we have 1445 no other choice than to try to parse all instruction opcodes 1446 until one matches. This is slow. 1447 1448 Another problem is that emitting detailed diagnostics becomes 1449 tricky, since the lack of mnemonic means it is not clear what 1450 instruction was intended by the user, and we cannot emit 1451 diagnostics for every attempted template. So if an instruction 1452 is not parsed, we report the diagnostic corresponding to the 1453 partially parsed instruction that was matched further. */ 1454 1455 unsigned int idx = 0; 1456 struct bpf_insn insn; 1457 const struct bpf_opcode *opcode; 1458 1459 /* Initialize the global diagnostic variables. See the parse_error 1460 function above. */ 1461 partial_match_length = 0; 1462 errmsg = NULL; 1463 1464 #define PARSE_ERROR(...) parse_error (s - str, __VA_ARGS__) 1465 1466 while ((opcode = bpf_get_opcode (idx++)) != NULL) 1467 { 1468 const char *p; 1469 char *s; 1470 const char *template 1471 = (asm_dialect == DIALECT_PSEUDOC ? opcode->pseudoc : opcode->normal); 1472 1473 /* Do not try to match opcodes with a higher version than the 1474 selected ISA spec. */ 1475 if (opcode->version > isa_spec) 1476 continue; 1477 1478 memset (&insn, 0, sizeof (struct bpf_insn)); 1479 insn.size = 8; 1480 for (s = str, p = template; *p != '\0';) 1481 { 1482 if (*p == ' ') 1483 { 1484 /* Expect zero or more spaces. */ 1485 while (*s != '\0' && (*s == ' ' || *s == '\t')) 1486 s += 1; 1487 p += 1; 1488 } 1489 else if (*p == '%') 1490 { 1491 if (*(p + 1) == '%') 1492 { 1493 if (*s != '%') 1494 { 1495 PARSE_ERROR ("expected '%%'"); 1496 break; 1497 } 1498 p += 2; 1499 s += 1; 1500 } 1501 else if (*(p + 1) == 'w') 1502 { 1503 /* Expect zero or more spaces. */ 1504 while (*s != '\0' && (*s == ' ' || *s == '\t')) 1505 s += 1; 1506 p += 2; 1507 } 1508 else if (*(p + 1) == 'W') 1509 { 1510 /* Expect one or more spaces. */ 1511 if (*s != ' ' && *s != '\t') 1512 { 1513 PARSE_ERROR ("expected white space, got '%s'", 1514 s); 1515 break; 1516 } 1517 while (*s != '\0' && (*s == ' ' || *s == '\t')) 1518 s += 1; 1519 p += 2; 1520 } 1521 else if (strncmp (p, "%dr", 3) == 0) 1522 { 1523 uint8_t regno; 1524 char *news = parse_bpf_register (s, 'r', ®no); 1525 1526 if (news == NULL || (insn.has_dst && regno != insn.dst)) 1527 { 1528 if (news != NULL) 1529 PARSE_ERROR ("expected register r%d, got r%d", 1530 insn.dst, regno); 1531 else 1532 PARSE_ERROR ("expected register name, got '%s'", s); 1533 break; 1534 } 1535 s = news; 1536 insn.dst = regno; 1537 insn.has_dst = 1; 1538 p += 3; 1539 } 1540 else if (strncmp (p, "%sr", 3) == 0) 1541 { 1542 uint8_t regno; 1543 char *news = parse_bpf_register (s, 'r', ®no); 1544 1545 if (news == NULL || (insn.has_src && regno != insn.src)) 1546 { 1547 if (news != NULL) 1548 PARSE_ERROR ("expected register r%d, got r%d", 1549 insn.dst, regno); 1550 else 1551 PARSE_ERROR ("expected register name, got '%s'", s); 1552 break; 1553 } 1554 s = news; 1555 insn.src = regno; 1556 insn.has_src = 1; 1557 p += 3; 1558 } 1559 else if (strncmp (p, "%dw", 3) == 0) 1560 { 1561 uint8_t regno; 1562 char *news = parse_bpf_register (s, 'w', ®no); 1563 1564 if (news == NULL || (insn.has_dst && regno != insn.dst)) 1565 { 1566 if (news != NULL) 1567 PARSE_ERROR ("expected register r%d, got r%d", 1568 insn.dst, regno); 1569 else 1570 PARSE_ERROR ("expected register name, got '%s'", s); 1571 break; 1572 } 1573 s = news; 1574 insn.dst = regno; 1575 insn.has_dst = 1; 1576 p += 3; 1577 } 1578 else if (strncmp (p, "%sw", 3) == 0) 1579 { 1580 uint8_t regno; 1581 char *news = parse_bpf_register (s, 'w', ®no); 1582 1583 if (news == NULL || (insn.has_src && regno != insn.src)) 1584 { 1585 if (news != NULL) 1586 PARSE_ERROR ("expected register r%d, got r%d", 1587 insn.dst, regno); 1588 else 1589 PARSE_ERROR ("expected register name, got '%s'", s); 1590 break; 1591 } 1592 s = news; 1593 insn.src = regno; 1594 insn.has_src = 1; 1595 p += 3; 1596 } 1597 else if (strncmp (p, "%i32", 4) == 0 1598 || strncmp (p, "%I32", 4) == 0) 1599 { 1600 if (p[1] == 'I') 1601 { 1602 while (*s == ' ' || *s == '\t') 1603 s += 1; 1604 if (*s != '+' && *s != '-') 1605 { 1606 PARSE_ERROR ("expected `+' or `-', got `%c'", *s); 1607 break; 1608 } 1609 } 1610 1611 s = parse_expression (s, &insn.imm32); 1612 if (s == NULL) 1613 { 1614 PARSE_ERROR ("expected signed 32-bit immediate"); 1615 break; 1616 } 1617 insn.has_imm32 = 1; 1618 p += 4; 1619 } 1620 else if (strncmp (p, "%o16", 4) == 0) 1621 { 1622 while (*s == ' ' || *s == '\t') 1623 s += 1; 1624 if (*s != '+' && *s != '-') 1625 { 1626 PARSE_ERROR ("expected `+' or `-', got `%c'", *s); 1627 break; 1628 } 1629 1630 s = parse_expression (s, &insn.offset16); 1631 if (s == NULL) 1632 { 1633 PARSE_ERROR ("expected signed 16-bit offset"); 1634 break; 1635 } 1636 insn.has_offset16 = 1; 1637 p += 4; 1638 } 1639 else if (strncmp (p, "%d16", 4) == 0) 1640 { 1641 s = parse_expression (s, &insn.disp16); 1642 if (s == NULL) 1643 { 1644 PARSE_ERROR ("expected signed 16-bit displacement"); 1645 break; 1646 } 1647 insn.has_disp16 = 1; 1648 insn.is_relaxable = (insn.disp16.X_op != O_constant); 1649 p += 4; 1650 } 1651 else if (strncmp (p, "%d32", 4) == 0) 1652 { 1653 s = parse_expression (s, &insn.disp32); 1654 if (s == NULL) 1655 { 1656 PARSE_ERROR ("expected signed 32-bit displacement"); 1657 break; 1658 } 1659 insn.has_disp32 = 1; 1660 p += 4; 1661 } 1662 else if (strncmp (p, "%i64", 4) == 0) 1663 { 1664 s = parse_expression (s, &insn.imm64); 1665 if (s == NULL) 1666 { 1667 PARSE_ERROR ("expected signed 64-bit immediate"); 1668 break; 1669 } 1670 insn.has_imm64 = 1; 1671 insn.size = 16; 1672 p += 4; 1673 } 1674 else 1675 as_fatal (_("invalid %%-tag in BPF opcode '%s'\n"), template); 1676 } 1677 else 1678 { 1679 /* Match a literal character. */ 1680 if (*s != *p) 1681 { 1682 if (*s == '\0') 1683 PARSE_ERROR ("expected '%c'", *p); 1684 else if (*s == '%') 1685 { 1686 /* This is to workaround a bug in as_bad. */ 1687 char tmp[3]; 1688 1689 tmp[0] = '%'; 1690 tmp[1] = '%'; 1691 tmp[2] = '\0'; 1692 1693 PARSE_ERROR ("expected '%c', got '%s'", *p, tmp); 1694 } 1695 else 1696 PARSE_ERROR ("expected '%c', got '%c'", *p, *s); 1697 break; 1698 } 1699 p += 1; 1700 s += 1; 1701 } 1702 } 1703 1704 if (*p == '\0') 1705 { 1706 /* Allow white spaces at the end of the line. */ 1707 while (*s != '\0' && (*s == ' ' || *s == '\t')) 1708 s += 1; 1709 if (*s == '\0') 1710 /* We parsed an instruction successfully. */ 1711 break; 1712 PARSE_ERROR ("extra junk at end of line"); 1713 } 1714 } 1715 1716 /* Mark that we are no longer parsing an instruction, bpf_parse_name does 1717 not interfere with symbols in e.g. assembler directives. */ 1718 parsing_insn_operands = false; 1719 1720 if (opcode == NULL) 1721 { 1722 as_bad (_("unrecognized instruction `%s'"), str); 1723 if (errmsg != NULL) 1724 { 1725 as_bad ("%s", errmsg); 1726 free (errmsg); 1727 } 1728 1729 return; 1730 } 1731 insn.id = opcode->id; 1732 insn.opcode = opcode->opcode; 1733 1734 #undef PARSE_ERROR 1735 1736 /* Commit any symbols created while parsing the instruction. */ 1737 while (deferred_sym_rootP) 1738 { 1739 symbolS *sym = deferred_sym_rootP; 1740 symbol_remove (sym, &deferred_sym_rootP, &deferred_sym_lastP); 1741 symbol_append (sym, symbol_lastP, &symbol_rootP, &symbol_lastP); 1742 symbol_table_insert (sym); 1743 } 1744 1745 /* Generate the frags and fixups for the parsed instruction. */ 1746 if (do_relax && isa_spec >= BPF_V4 && insn.is_relaxable) 1747 { 1748 expressionS *relaxable_exp = NULL; 1749 1750 if (insn.has_disp16) 1751 relaxable_exp = &insn.disp16; 1752 else 1753 abort (); 1754 1755 add_relaxed_insn (&insn, relaxable_exp); 1756 } 1757 else 1758 add_fixed_insn (&insn); 1759 1760 /* Emit DWARF2 debugging information. */ 1761 dwarf2_emit_insn (insn.size); 1762 } 1763 1764 /* Parse an operand that is machine-specific. */ 1765 1766 void 1767 md_operand (expressionS *expressionP) 1768 { 1769 /* If this hook is invoked it means GAS failed to parse a generic 1770 expression. We should inhibit the as_bad in expr.c, so we can 1771 fail while parsing instruction alternatives. To do that, we 1772 change the expression to not have an O_absent. But then we also 1773 need to set exp_parse_failed to parse_expression above does the 1774 right thing. */ 1775 ++input_line_pointer; 1776 expressionP->X_op = O_constant; 1777 expressionP->X_add_number = 0; 1778 exp_parse_failed = 1; 1779 } 1780 1781 symbolS * 1782 md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 1783 { 1784 return NULL; 1785 } 1786 1787 1788 /* Turn a string in input_line_pointer into a floating point constant 1790 of type TYPE, and store the appropriate bytes in *LITP. The number 1791 of LITTLENUMS emitted is stored in *SIZEP. An error message is 1792 returned, or NULL on OK. */ 1793 1794 const char * 1795 md_atof (int type, char *litP, int *sizeP) 1796 { 1797 return ieee_md_atof (type, litP, sizeP, false); 1798 } 1799 1800 1801 /* Determine whether the equal sign in the given string corresponds to 1803 a BPF instruction, i.e. when it is not to be considered a symbol 1804 assignment. */ 1805 1806 bool 1807 bpf_tc_equal_in_insn (int c ATTRIBUTE_UNUSED, char *str ATTRIBUTE_UNUSED) 1808 { 1809 uint8_t regno; 1810 1811 /* Only pseudo-c instructions can have equal signs, and of these, 1812 all that could be confused with a symbol assignment all start 1813 with a register name. */ 1814 if (asm_dialect == DIALECT_PSEUDOC) 1815 { 1816 char *w = parse_bpf_register (str, 'w', ®no); 1817 char *r = parse_bpf_register (str, 'r', ®no); 1818 1819 if ((w != NULL && *w == '\0') 1820 || (r != NULL && *r == '\0')) 1821 return 1; 1822 } 1823 1824 return 0; 1825 } 1826 1827 /* Some special processing for a BPF ELF file. */ 1828 1829 void 1830 bpf_elf_final_processing (void) 1831 { 1832 /* Annotate the BPF ISA version in the ELF flag bits. */ 1833 elf_elfheader (stdoutput)->e_flags |= (isa_spec & EF_BPF_CPUVER); 1834 } 1835
Indexes created Sat Apr 11 00:22:22 UTC 2026