tc-h8300.c revision 1.1.1.1
1 /* tc-h8300.c -- Assemble code for the Renesas H8/300 2 Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000, 3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc. 4 5 This file is part of GAS, the GNU Assembler. 6 7 GAS is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GAS is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GAS; see the file COPYING. If not, write to the Free 19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 20 02110-1301, USA. */ 21 22 /* Written By Steve Chamberlain <sac (at) cygnus.com>. */ 23 24 #include "as.h" 25 #include "subsegs.h" 26 #include "dwarf2dbg.h" 27 28 #define DEFINE_TABLE 29 #define h8_opcodes ops 30 #include "opcode/h8300.h" 31 #include "safe-ctype.h" 32 33 #ifdef OBJ_ELF 34 #include "elf/h8.h" 35 #endif 36 37 const char comment_chars[] = ";"; 38 const char line_comment_chars[] = "#"; 39 const char line_separator_chars[] = ""; 40 41 static void sbranch (int); 42 static void h8300hmode (int); 43 static void h8300smode (int); 44 static void h8300hnmode (int); 45 static void h8300snmode (int); 46 static void h8300sxmode (int); 47 static void h8300sxnmode (int); 48 static void pint (int); 49 50 int Hmode; 51 int Smode; 52 int Nmode; 53 int SXmode; 54 55 #define PSIZE (Hmode && !Nmode ? L_32 : L_16) 56 57 static int bsize = L_8; /* Default branch displacement. */ 58 59 struct h8_instruction 60 { 61 int length; 62 int noperands; 63 int idx; 64 int size; 65 const struct h8_opcode *opcode; 66 }; 67 68 static struct h8_instruction *h8_instructions; 69 70 static void 71 h8300hmode (int arg ATTRIBUTE_UNUSED) 72 { 73 Hmode = 1; 74 Smode = 0; 75 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300h)) 76 as_warn (_("could not set architecture and machine")); 77 } 78 79 static void 80 h8300smode (int arg ATTRIBUTE_UNUSED) 81 { 82 Smode = 1; 83 Hmode = 1; 84 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300s)) 85 as_warn (_("could not set architecture and machine")); 86 } 87 88 static void 89 h8300hnmode (int arg ATTRIBUTE_UNUSED) 90 { 91 Hmode = 1; 92 Smode = 0; 93 Nmode = 1; 94 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300hn)) 95 as_warn (_("could not set architecture and machine")); 96 } 97 98 static void 99 h8300snmode (int arg ATTRIBUTE_UNUSED) 100 { 101 Smode = 1; 102 Hmode = 1; 103 Nmode = 1; 104 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sn)) 105 as_warn (_("could not set architecture and machine")); 106 } 107 108 static void 109 h8300sxmode (int arg ATTRIBUTE_UNUSED) 110 { 111 Smode = 1; 112 Hmode = 1; 113 SXmode = 1; 114 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sx)) 115 as_warn (_("could not set architecture and machine")); 116 } 117 118 static void 119 h8300sxnmode (int arg ATTRIBUTE_UNUSED) 120 { 121 Smode = 1; 122 Hmode = 1; 123 SXmode = 1; 124 Nmode = 1; 125 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sxn)) 126 as_warn (_("could not set architecture and machine")); 127 } 128 129 static void 130 sbranch (int size) 131 { 132 bsize = size; 133 } 134 135 static void 136 pint (int arg ATTRIBUTE_UNUSED) 137 { 138 cons (Hmode ? 4 : 2); 139 } 140 141 /* This table describes all the machine specific pseudo-ops the assembler 142 has to support. The fields are: 143 pseudo-op name without dot 144 function to call to execute this pseudo-op 145 Integer arg to pass to the function. */ 146 147 const pseudo_typeS md_pseudo_table[] = 148 { 149 {"h8300h", h8300hmode, 0}, 150 {"h8300hn", h8300hnmode, 0}, 151 {"h8300s", h8300smode, 0}, 152 {"h8300sn", h8300snmode, 0}, 153 {"h8300sx", h8300sxmode, 0}, 154 {"h8300sxn", h8300sxnmode, 0}, 155 {"sbranch", sbranch, L_8}, 156 {"lbranch", sbranch, L_16}, 157 158 {"int", pint, 0}, 159 {"data.b", cons, 1}, 160 {"data.w", cons, 2}, 161 {"data.l", cons, 4}, 162 {"form", listing_psize, 0}, 163 {"heading", listing_title, 0}, 164 {"import", s_ignore, 0}, 165 {"page", listing_eject, 0}, 166 {"program", s_ignore, 0}, 167 {0, 0, 0} 168 }; 169 170 const char EXP_CHARS[] = "eE"; 171 172 /* Chars that mean this number is a floating point constant 173 As in 0f12.456 174 or 0d1.2345e12. */ 175 const char FLT_CHARS[] = "rRsSfFdDxXpP"; 176 177 static struct hash_control *opcode_hash_control; /* Opcode mnemonics. */ 178 179 /* This function is called once, at assembler startup time. This 180 should set up all the tables, etc. that the MD part of the assembler 181 needs. */ 182 183 void 184 md_begin (void) 185 { 186 unsigned int nopcodes; 187 struct h8_opcode *p, *p1; 188 struct h8_instruction *pi; 189 char prev_buffer[100]; 190 int idx = 0; 191 192 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300)) 193 as_warn (_("could not set architecture and machine")); 194 195 opcode_hash_control = hash_new (); 196 prev_buffer[0] = 0; 197 198 nopcodes = sizeof (h8_opcodes) / sizeof (struct h8_opcode); 199 200 h8_instructions = (struct h8_instruction *) 201 xmalloc (nopcodes * sizeof (struct h8_instruction)); 202 203 pi = h8_instructions; 204 p1 = h8_opcodes; 205 /* We do a minimum amount of sorting on the opcode table; this is to 206 make it easy to describe the mova instructions without unnecessary 207 code duplication. 208 Sorting only takes place inside blocks of instructions of the form 209 X/Y, so for example mova/b, mova/w and mova/l can be intermixed. */ 210 while (p1) 211 { 212 struct h8_opcode *first_skipped = 0; 213 int len, cmplen = 0; 214 char *src = p1->name; 215 char *dst, *buffer; 216 217 if (p1->name == 0) 218 break; 219 /* Strip off any . part when inserting the opcode and only enter 220 unique codes into the hash table. */ 221 dst = buffer = malloc (strlen (src) + 1); 222 while (*src) 223 { 224 if (*src == '.') 225 { 226 src++; 227 break; 228 } 229 if (*src == '/') 230 cmplen = src - p1->name + 1; 231 *dst++ = *src++; 232 } 233 *dst = 0; 234 len = dst - buffer; 235 if (cmplen == 0) 236 cmplen = len; 237 hash_insert (opcode_hash_control, buffer, (char *) pi); 238 strcpy (prev_buffer, buffer); 239 idx++; 240 241 for (p = p1; p->name; p++) 242 { 243 /* A negative TIME is used to indicate that we've added this opcode 244 already. */ 245 if (p->time == -1) 246 continue; 247 if (strncmp (p->name, buffer, cmplen) != 0 248 || (p->name[cmplen] != '\0' && p->name[cmplen] != '.' 249 && p->name[cmplen - 1] != '/')) 250 { 251 if (first_skipped == 0) 252 first_skipped = p; 253 break; 254 } 255 if (strncmp (p->name, buffer, len) != 0) 256 { 257 if (first_skipped == 0) 258 first_skipped = p; 259 continue; 260 } 261 262 p->time = -1; 263 pi->size = p->name[len] == '.' ? p->name[len + 1] : 0; 264 pi->idx = idx; 265 266 /* Find the number of operands. */ 267 pi->noperands = 0; 268 while (pi->noperands < 3 && p->args.nib[pi->noperands] != (op_type) E) 269 pi->noperands++; 270 271 /* Find the length of the opcode in bytes. */ 272 pi->length = 0; 273 while (p->data.nib[pi->length * 2] != (op_type) E) 274 pi->length++; 275 276 pi->opcode = p; 277 pi++; 278 } 279 p1 = first_skipped; 280 } 281 282 /* Add entry for the NULL vector terminator. */ 283 pi->length = 0; 284 pi->noperands = 0; 285 pi->idx = 0; 286 pi->size = 0; 287 pi->opcode = 0; 288 289 linkrelax = 1; 290 } 291 292 struct h8_op 293 { 294 op_type mode; 295 unsigned reg; 296 expressionS exp; 297 }; 298 299 static void clever_message (const struct h8_instruction *, struct h8_op *); 300 static void fix_operand_size (struct h8_op *, int); 301 static void build_bytes (const struct h8_instruction *, struct h8_op *); 302 static void do_a_fix_imm (int, int, struct h8_op *, int); 303 static void check_operand (struct h8_op *, unsigned int, char *); 304 static const struct h8_instruction * get_specific (const struct h8_instruction *, struct h8_op *, int) ; 305 static char *get_operands (unsigned, char *, struct h8_op *); 306 static void get_operand (char **, struct h8_op *, int); 307 static int parse_reg (char *, op_type *, unsigned *, int); 308 static char *skip_colonthing (char *, int *); 309 static char *parse_exp (char *, struct h8_op *); 310 311 static int constant_fits_width_p (struct h8_op *, unsigned int); 312 static int constant_fits_size_p (struct h8_op *, int, int); 313 314 /* 315 parse operands 316 WREG r0,r1,r2,r3,r4,r5,r6,r7,fp,sp 317 r0l,r0h,..r7l,r7h 318 @WREG 319 @WREG+ 320 @-WREG 321 #const 322 ccr 323 */ 324 325 /* Try to parse a reg name. Return the number of chars consumed. */ 326 327 static int 328 parse_reg (char *src, op_type *mode, unsigned int *reg, int direction) 329 { 330 char *end; 331 int len; 332 333 /* Cribbed from get_symbol_end. */ 334 if (!is_name_beginner (*src) || *src == '\001') 335 return 0; 336 end = src + 1; 337 while ((is_part_of_name (*end) && *end != '.') || *end == '\001') 338 end++; 339 len = end - src; 340 341 if (len == 2 && TOLOWER (src[0]) == 's' && TOLOWER (src[1]) == 'p') 342 { 343 *mode = PSIZE | REG | direction; 344 *reg = 7; 345 return len; 346 } 347 if (len == 3 && 348 TOLOWER (src[0]) == 'c' && 349 TOLOWER (src[1]) == 'c' && 350 TOLOWER (src[2]) == 'r') 351 { 352 *mode = CCR; 353 *reg = 0; 354 return len; 355 } 356 if (len == 3 && 357 TOLOWER (src[0]) == 'e' && 358 TOLOWER (src[1]) == 'x' && 359 TOLOWER (src[2]) == 'r') 360 { 361 *mode = EXR; 362 *reg = 1; 363 return len; 364 } 365 if (len == 3 && 366 TOLOWER (src[0]) == 'v' && 367 TOLOWER (src[1]) == 'b' && 368 TOLOWER (src[2]) == 'r') 369 { 370 *mode = VBR; 371 *reg = 6; 372 return len; 373 } 374 if (len == 3 && 375 TOLOWER (src[0]) == 's' && 376 TOLOWER (src[1]) == 'b' && 377 TOLOWER (src[2]) == 'r') 378 { 379 *mode = SBR; 380 *reg = 7; 381 return len; 382 } 383 if (len == 2 && TOLOWER (src[0]) == 'f' && TOLOWER (src[1]) == 'p') 384 { 385 *mode = PSIZE | REG | direction; 386 *reg = 6; 387 return len; 388 } 389 if (len == 3 && TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' && 390 src[2] >= '0' && src[2] <= '7') 391 { 392 *mode = L_32 | REG | direction; 393 *reg = src[2] - '0'; 394 if (!Hmode) 395 as_warn (_("Reg not valid for H8/300")); 396 return len; 397 } 398 if (len == 2 && TOLOWER (src[0]) == 'e' && src[1] >= '0' && src[1] <= '7') 399 { 400 *mode = L_16 | REG | direction; 401 *reg = src[1] - '0' + 8; 402 if (!Hmode) 403 as_warn (_("Reg not valid for H8/300")); 404 return len; 405 } 406 407 if (TOLOWER (src[0]) == 'r') 408 { 409 if (src[1] >= '0' && src[1] <= '7') 410 { 411 if (len == 3 && TOLOWER (src[2]) == 'l') 412 { 413 *mode = L_8 | REG | direction; 414 *reg = (src[1] - '0') + 8; 415 return len; 416 } 417 if (len == 3 && TOLOWER (src[2]) == 'h') 418 { 419 *mode = L_8 | REG | direction; 420 *reg = (src[1] - '0'); 421 return len; 422 } 423 if (len == 2) 424 { 425 *mode = L_16 | REG | direction; 426 *reg = (src[1] - '0'); 427 return len; 428 } 429 } 430 } 431 432 return 0; 433 } 434 435 436 /* Parse an immediate or address-related constant and store it in OP. 437 If the user also specifies the operand's size, store that size 438 in OP->MODE, otherwise leave it for later code to decide. */ 439 440 static char * 441 parse_exp (char *src, struct h8_op *op) 442 { 443 char *save; 444 445 save = input_line_pointer; 446 input_line_pointer = src; 447 expression (&op->exp); 448 if (op->exp.X_op == O_absent) 449 as_bad (_("missing operand")); 450 src = input_line_pointer; 451 input_line_pointer = save; 452 453 return skip_colonthing (src, &op->mode); 454 } 455 456 457 /* If SRC starts with an explicit operand size, skip it and store the size 458 in *MODE. Leave *MODE unchanged otherwise. */ 459 460 static char * 461 skip_colonthing (char *src, int *mode) 462 { 463 if (*src == ':') 464 { 465 src++; 466 *mode &= ~SIZE; 467 if (src[0] == '8' && !ISDIGIT (src[1])) 468 *mode |= L_8; 469 else if (src[0] == '2' && !ISDIGIT (src[1])) 470 *mode |= L_2; 471 else if (src[0] == '3' && !ISDIGIT (src[1])) 472 *mode |= L_3; 473 else if (src[0] == '4' && !ISDIGIT (src[1])) 474 *mode |= L_4; 475 else if (src[0] == '5' && !ISDIGIT (src[1])) 476 *mode |= L_5; 477 else if (src[0] == '2' && src[1] == '4' && !ISDIGIT (src[2])) 478 *mode |= L_24; 479 else if (src[0] == '3' && src[1] == '2' && !ISDIGIT (src[2])) 480 *mode |= L_32; 481 else if (src[0] == '1' && src[1] == '6' && !ISDIGIT (src[2])) 482 *mode |= L_16; 483 else 484 as_bad (_("invalid operand size requested")); 485 486 while (ISDIGIT (*src)) 487 src++; 488 } 489 return src; 490 } 491 492 /* The many forms of operand: 493 494 Rn Register direct 495 @Rn Register indirect 496 @(exp[:16], Rn) Register indirect with displacement 497 @Rn+ 498 @-Rn 499 @aa:8 absolute 8 bit 500 @aa:16 absolute 16 bit 501 @aa absolute 16 bit 502 503 #xx[:size] immediate data 504 @(exp:[8], pc) pc rel 505 @@aa[:8] memory indirect. */ 506 507 static int 508 constant_fits_width_p (struct h8_op *operand, unsigned int width) 509 { 510 return ((operand->exp.X_add_number & ~width) == 0 511 || (operand->exp.X_add_number | width) == (unsigned)(~0)); 512 } 513 514 static int 515 constant_fits_size_p (struct h8_op *operand, int size, int no_symbols) 516 { 517 offsetT num = operand->exp.X_add_number; 518 if (no_symbols 519 && (operand->exp.X_add_symbol != 0 || operand->exp.X_op_symbol != 0)) 520 return 0; 521 switch (size) 522 { 523 case L_2: 524 return (num & ~3) == 0; 525 case L_3: 526 return (num & ~7) == 0; 527 case L_3NZ: 528 return num >= 1 && num < 8; 529 case L_4: 530 return (num & ~15) == 0; 531 case L_5: 532 return num >= 1 && num < 32; 533 case L_8: 534 return (num & ~0xFF) == 0 || ((unsigned)num | 0x7F) == ~0u; 535 case L_8U: 536 return (num & ~0xFF) == 0; 537 case L_16: 538 return (num & ~0xFFFF) == 0 || ((unsigned)num | 0x7FFF) == ~0u; 539 case L_16U: 540 return (num & ~0xFFFF) == 0; 541 case L_32: 542 return 1; 543 default: 544 abort (); 545 } 546 } 547 548 static void 549 get_operand (char **ptr, struct h8_op *op, int direction) 550 { 551 char *src = *ptr; 552 op_type mode; 553 unsigned int num; 554 unsigned int len; 555 556 op->mode = 0; 557 558 /* Check for '(' and ')' for instructions ldm and stm. */ 559 if (src[0] == '(' && src[8] == ')') 560 ++ src; 561 562 /* Gross. Gross. ldm and stm have a format not easily handled 563 by get_operand. We deal with it explicitly here. */ 564 if (TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' && 565 ISDIGIT (src[2]) && src[3] == '-' && 566 TOLOWER (src[4]) == 'e' && TOLOWER (src[5]) == 'r' && ISDIGIT (src[6])) 567 { 568 int low, high; 569 570 low = src[2] - '0'; 571 high = src[6] - '0'; 572 573 /* Check register pair's validity as per tech note TN-H8*-193A/E 574 from Renesas for H8S and H8SX hardware manual. */ 575 if ( !(low == 0 && (high == 1 || high == 2 || high == 3)) 576 && !(low == 1 && (high == 2 || high == 3 || high == 4) && SXmode) 577 && !(low == 2 && (high == 3 || ((high == 4 || high == 5) && SXmode))) 578 && !(low == 3 && (high == 4 || high == 5 || high == 6) && SXmode) 579 && !(low == 4 && (high == 5 || high == 6)) 580 && !(low == 4 && high == 7 && SXmode) 581 && !(low == 5 && (high == 6 || high == 7) && SXmode) 582 && !(low == 6 && high == 7 && SXmode)) 583 as_bad (_("Invalid register list for ldm/stm\n")); 584 585 /* Even sicker. We encode two registers into op->reg. One 586 for the low register to save, the other for the high 587 register to save; we also set the high bit in op->reg 588 so we know this is "very special". */ 589 op->reg = 0x80000000 | (high << 8) | low; 590 op->mode = REG; 591 if (src[7] == ')') 592 *ptr = src + 8; 593 else 594 *ptr = src + 7; 595 return; 596 } 597 598 len = parse_reg (src, &op->mode, &op->reg, direction); 599 if (len) 600 { 601 src += len; 602 if (*src == '.') 603 { 604 int size = op->mode & SIZE; 605 switch (src[1]) 606 { 607 case 'l': case 'L': 608 if (size != L_32) 609 as_warn (_("mismatch between register and suffix")); 610 op->mode = (op->mode & ~MODE) | LOWREG; 611 break; 612 case 'w': case 'W': 613 if (size != L_32 && size != L_16) 614 as_warn (_("mismatch between register and suffix")); 615 op->mode = (op->mode & ~MODE) | LOWREG; 616 op->mode = (op->mode & ~SIZE) | L_16; 617 break; 618 case 'b': case 'B': 619 op->mode = (op->mode & ~MODE) | LOWREG; 620 if (size != L_32 && size != L_8) 621 as_warn (_("mismatch between register and suffix")); 622 op->mode = (op->mode & ~MODE) | LOWREG; 623 op->mode = (op->mode & ~SIZE) | L_8; 624 break; 625 default: 626 as_warn ("invalid suffix after register."); 627 break; 628 } 629 src += 2; 630 } 631 *ptr = src; 632 return; 633 } 634 635 if (*src == '@') 636 { 637 src++; 638 if (*src == '@') 639 { 640 *ptr = parse_exp (src + 1, op); 641 if (op->exp.X_add_number >= 0x100) 642 { 643 int divisor = 1; 644 645 op->mode = VECIND; 646 /* FIXME : 2? or 4? */ 647 if (op->exp.X_add_number >= 0x400) 648 as_bad (_("address too high for vector table jmp/jsr")); 649 else if (op->exp.X_add_number >= 0x200) 650 divisor = 4; 651 else 652 divisor = 2; 653 654 op->exp.X_add_number = op->exp.X_add_number / divisor - 0x80; 655 } 656 else 657 op->mode = MEMIND; 658 return; 659 } 660 661 if (*src == '-' || *src == '+') 662 { 663 len = parse_reg (src + 1, &mode, &num, direction); 664 if (len == 0) 665 { 666 /* Oops, not a reg after all, must be ordinary exp. */ 667 op->mode = ABS | direction; 668 *ptr = parse_exp (src, op); 669 return; 670 } 671 672 if (((mode & SIZE) != PSIZE) 673 /* For Normal mode accept 16 bit and 32 bit pointer registers. */ 674 && (!Nmode || ((mode & SIZE) != L_32))) 675 as_bad (_("Wrong size pointer register for architecture.")); 676 677 op->mode = src[0] == '-' ? RDPREDEC : RDPREINC; 678 op->reg = num; 679 *ptr = src + 1 + len; 680 return; 681 } 682 if (*src == '(') 683 { 684 src++; 685 686 /* See if this is @(ERn.x, PC). */ 687 len = parse_reg (src, &mode, &op->reg, direction); 688 if (len != 0 && (mode & MODE) == REG && src[len] == '.') 689 { 690 switch (TOLOWER (src[len + 1])) 691 { 692 case 'b': 693 mode = PCIDXB | direction; 694 break; 695 case 'w': 696 mode = PCIDXW | direction; 697 break; 698 case 'l': 699 mode = PCIDXL | direction; 700 break; 701 default: 702 mode = 0; 703 break; 704 } 705 if (mode 706 && src[len + 2] == ',' 707 && TOLOWER (src[len + 3]) != 'p' 708 && TOLOWER (src[len + 4]) != 'c' 709 && src[len + 5] != ')') 710 { 711 *ptr = src + len + 6; 712 op->mode |= mode; 713 return; 714 } 715 /* Fall through into disp case - the grammar is somewhat 716 ambiguous, so we should try whether it's a DISP operand 717 after all ("ER3.L" might be a poorly named label...). */ 718 } 719 720 /* Disp. */ 721 722 /* Start off assuming a 16 bit offset. */ 723 724 src = parse_exp (src, op); 725 if (*src == ')') 726 { 727 op->mode |= ABS | direction; 728 *ptr = src + 1; 729 return; 730 } 731 732 if (*src != ',') 733 { 734 as_bad (_("expected @(exp, reg16)")); 735 return; 736 } 737 src++; 738 739 len = parse_reg (src, &mode, &op->reg, direction); 740 if (len == 0 || (mode & MODE) != REG) 741 { 742 as_bad (_("expected @(exp, reg16)")); 743 return; 744 } 745 src += len; 746 if (src[0] == '.') 747 { 748 switch (TOLOWER (src[1])) 749 { 750 case 'b': 751 op->mode |= INDEXB | direction; 752 break; 753 case 'w': 754 op->mode |= INDEXW | direction; 755 break; 756 case 'l': 757 op->mode |= INDEXL | direction; 758 break; 759 default: 760 as_bad (_("expected .L, .W or .B for register in indexed addressing mode")); 761 } 762 src += 2; 763 op->reg &= 7; 764 } 765 else 766 op->mode |= DISP | direction; 767 src = skip_colonthing (src, &op->mode); 768 769 if (*src != ')' && '(') 770 { 771 as_bad (_("expected @(exp, reg16)")); 772 return; 773 } 774 *ptr = src + 1; 775 return; 776 } 777 len = parse_reg (src, &mode, &num, direction); 778 779 if (len) 780 { 781 src += len; 782 if (*src == '+' || *src == '-') 783 { 784 if (((mode & SIZE) != PSIZE) 785 /* For Normal mode accept 16 bit and 32 bit pointer registers. */ 786 && (!Nmode || ((mode & SIZE) != L_32))) 787 as_bad (_("Wrong size pointer register for architecture.")); 788 op->mode = *src == '+' ? RSPOSTINC : RSPOSTDEC; 789 op->reg = num; 790 src++; 791 *ptr = src; 792 return; 793 } 794 if (((mode & SIZE) != PSIZE) 795 /* For Normal mode accept 16 bit and 32 bit pointer registers. */ 796 && (!Nmode || ((mode & SIZE) != L_32))) 797 as_bad (_("Wrong size pointer register for architecture.")); 798 799 op->mode = direction | IND | PSIZE; 800 op->reg = num; 801 *ptr = src; 802 803 return; 804 } 805 else 806 { 807 /* must be a symbol */ 808 809 op->mode = ABS | direction; 810 *ptr = parse_exp (src, op); 811 return; 812 } 813 } 814 815 if (*src == '#') 816 { 817 op->mode = IMM; 818 *ptr = parse_exp (src + 1, op); 819 return; 820 } 821 else if (strncmp (src, "mach", 4) == 0 || 822 strncmp (src, "macl", 4) == 0 || 823 strncmp (src, "MACH", 4) == 0 || 824 strncmp (src, "MACL", 4) == 0) 825 { 826 op->reg = TOLOWER (src[3]) == 'l'; 827 op->mode = MACREG; 828 *ptr = src + 4; 829 return; 830 } 831 else 832 { 833 op->mode = PCREL; 834 *ptr = parse_exp (src, op); 835 } 836 } 837 838 static char * 839 get_operands (unsigned int noperands, char *op_end, struct h8_op *operand) 840 { 841 char *ptr = op_end; 842 843 switch (noperands) 844 { 845 case 0: 846 break; 847 848 case 1: 849 ptr++; 850 get_operand (&ptr, operand + 0, SRC); 851 if (*ptr == ',') 852 { 853 ptr++; 854 get_operand (&ptr, operand + 1, DST); 855 } 856 break; 857 858 case 2: 859 ptr++; 860 get_operand (&ptr, operand + 0, SRC); 861 if (*ptr == ',') 862 ptr++; 863 get_operand (&ptr, operand + 1, DST); 864 break; 865 866 case 3: 867 ptr++; 868 get_operand (&ptr, operand + 0, SRC); 869 if (*ptr == ',') 870 ptr++; 871 get_operand (&ptr, operand + 1, DST); 872 if (*ptr == ',') 873 ptr++; 874 get_operand (&ptr, operand + 2, OP3); 875 break; 876 877 default: 878 abort (); 879 } 880 881 return ptr; 882 } 883 884 /* MOVA has special requirements. Rather than adding twice the amount of 885 addressing modes, we simply special case it a bit. */ 886 static void 887 get_mova_operands (char *op_end, struct h8_op *operand) 888 { 889 char *ptr = op_end; 890 891 if (ptr[1] != '@' || ptr[2] != '(') 892 goto error; 893 ptr += 3; 894 operand[0].mode = 0; 895 ptr = parse_exp (ptr, &operand[0]); 896 897 if (*ptr !=',') 898 goto error; 899 ptr++; 900 get_operand (&ptr, operand + 1, DST); 901 902 if (*ptr =='.') 903 { 904 ptr++; 905 switch (*ptr++) 906 { 907 case 'b': case 'B': 908 operand[0].mode = (operand[0].mode & ~MODE) | INDEXB; 909 break; 910 case 'w': case 'W': 911 operand[0].mode = (operand[0].mode & ~MODE) | INDEXW; 912 break; 913 case 'l': case 'L': 914 operand[0].mode = (operand[0].mode & ~MODE) | INDEXL; 915 break; 916 default: 917 goto error; 918 } 919 } 920 else if ((operand[1].mode & MODE) == LOWREG) 921 { 922 switch (operand[1].mode & SIZE) 923 { 924 case L_8: 925 operand[0].mode = (operand[0].mode & ~MODE) | INDEXB; 926 break; 927 case L_16: 928 operand[0].mode = (operand[0].mode & ~MODE) | INDEXW; 929 break; 930 case L_32: 931 operand[0].mode = (operand[0].mode & ~MODE) | INDEXL; 932 break; 933 default: 934 goto error; 935 } 936 } 937 else 938 goto error; 939 940 if (*ptr++ != ')' || *ptr++ != ',') 941 goto error; 942 get_operand (&ptr, operand + 2, OP3); 943 /* See if we can use the short form of MOVA. */ 944 if (((operand[1].mode & MODE) == REG || (operand[1].mode & MODE) == LOWREG) 945 && (operand[2].mode & MODE) == REG 946 && (operand[1].reg & 7) == (operand[2].reg & 7)) 947 { 948 operand[1].mode = operand[2].mode = 0; 949 operand[0].reg = operand[2].reg & 7; 950 } 951 return; 952 953 error: 954 as_bad (_("expected valid addressing mode for mova: \"@(disp, ea.sz),ERn\"")); 955 } 956 957 static void 958 get_rtsl_operands (char *ptr, struct h8_op *operand) 959 { 960 int mode, len, type = 0; 961 unsigned int num, num2; 962 963 ptr++; 964 if (*ptr == '(') 965 { 966 ptr++; 967 type = 1; 968 } 969 len = parse_reg (ptr, &mode, &num, SRC); 970 if (len == 0 || (mode & MODE) != REG) 971 { 972 as_bad (_("expected register")); 973 return; 974 } 975 ptr += len; 976 if (*ptr == '-') 977 { 978 len = parse_reg (++ptr, &mode, &num2, SRC); 979 if (len == 0 || (mode & MODE) != REG) 980 { 981 as_bad (_("expected register")); 982 return; 983 } 984 ptr += len; 985 /* CONST_xxx are used as placeholders in the opcode table. */ 986 num = num2 - num; 987 if (num > 3) 988 { 989 as_bad (_("invalid register list")); 990 return; 991 } 992 } 993 else 994 num2 = num, num = 0; 995 if (type == 1 && *ptr++ != ')') 996 { 997 as_bad (_("expected closing paren")); 998 return; 999 } 1000 operand[0].mode = RS32; 1001 operand[1].mode = RD32; 1002 operand[0].reg = num; 1003 operand[1].reg = num2; 1004 } 1005 1006 /* Passed a pointer to a list of opcodes which use different 1007 addressing modes, return the opcode which matches the opcodes 1008 provided. */ 1009 1010 static const struct h8_instruction * 1011 get_specific (const struct h8_instruction *instruction, 1012 struct h8_op *operands, int size) 1013 { 1014 const struct h8_instruction *this_try = instruction; 1015 const struct h8_instruction *found_other = 0, *found_mismatched = 0; 1016 int found = 0; 1017 int this_index = instruction->idx; 1018 int noperands = 0; 1019 1020 /* There's only one ldm/stm and it's easier to just 1021 get out quick for them. */ 1022 if (OP_KIND (instruction->opcode->how) == O_LDM 1023 || OP_KIND (instruction->opcode->how) == O_STM) 1024 return this_try; 1025 1026 while (noperands < 3 && operands[noperands].mode != 0) 1027 noperands++; 1028 1029 while (this_index == instruction->idx && !found) 1030 { 1031 int this_size; 1032 1033 found = 1; 1034 this_try = instruction++; 1035 this_size = this_try->opcode->how & SN; 1036 1037 if (this_try->noperands != noperands) 1038 found = 0; 1039 else if (this_try->noperands > 0) 1040 { 1041 int i; 1042 1043 for (i = 0; i < this_try->noperands && found; i++) 1044 { 1045 op_type op = this_try->opcode->args.nib[i]; 1046 int op_mode = op & MODE; 1047 int op_size = op & SIZE; 1048 int x = operands[i].mode; 1049 int x_mode = x & MODE; 1050 int x_size = x & SIZE; 1051 1052 if (op_mode == LOWREG && (x_mode == REG || x_mode == LOWREG)) 1053 { 1054 if ((x_size == L_8 && (operands[i].reg & 8) == 0) 1055 || (x_size == L_16 && (operands[i].reg & 8) == 8)) 1056 as_warn (_("can't use high part of register in operand %d"), i); 1057 1058 if (x_size != op_size) 1059 found = 0; 1060 } 1061 else if (op_mode == REG) 1062 { 1063 if (x_mode == LOWREG) 1064 x_mode = REG; 1065 if (x_mode != REG) 1066 found = 0; 1067 1068 if (x_size == L_P) 1069 x_size = (Hmode ? L_32 : L_16); 1070 if (op_size == L_P) 1071 op_size = (Hmode ? L_32 : L_16); 1072 1073 /* The size of the reg is v important. */ 1074 if (op_size != x_size) 1075 found = 0; 1076 } 1077 else if (op_mode & CTRL) /* control register */ 1078 { 1079 if (!(x_mode & CTRL)) 1080 found = 0; 1081 1082 switch (x_mode) 1083 { 1084 case CCR: 1085 if (op_mode != CCR && 1086 op_mode != CCR_EXR && 1087 op_mode != CC_EX_VB_SB) 1088 found = 0; 1089 break; 1090 case EXR: 1091 if (op_mode != EXR && 1092 op_mode != CCR_EXR && 1093 op_mode != CC_EX_VB_SB) 1094 found = 0; 1095 break; 1096 case MACH: 1097 if (op_mode != MACH && 1098 op_mode != MACREG) 1099 found = 0; 1100 break; 1101 case MACL: 1102 if (op_mode != MACL && 1103 op_mode != MACREG) 1104 found = 0; 1105 break; 1106 case VBR: 1107 if (op_mode != VBR && 1108 op_mode != VBR_SBR && 1109 op_mode != CC_EX_VB_SB) 1110 found = 0; 1111 break; 1112 case SBR: 1113 if (op_mode != SBR && 1114 op_mode != VBR_SBR && 1115 op_mode != CC_EX_VB_SB) 1116 found = 0; 1117 break; 1118 } 1119 } 1120 else if ((op & ABSJMP) && (x_mode == ABS || x_mode == PCREL)) 1121 { 1122 operands[i].mode &= ~MODE; 1123 operands[i].mode |= ABSJMP; 1124 /* But it may not be 24 bits long. */ 1125 if (x_mode == ABS && !Hmode) 1126 { 1127 operands[i].mode &= ~SIZE; 1128 operands[i].mode |= L_16; 1129 } 1130 if ((operands[i].mode & SIZE) == L_32 1131 && (op_mode & SIZE) != L_32) 1132 found = 0; 1133 } 1134 else if (x_mode == IMM && op_mode != IMM) 1135 { 1136 offsetT num = operands[i].exp.X_add_number; 1137 if (op_mode == KBIT || op_mode == DBIT) 1138 /* This is ok if the immediate value is sensible. */; 1139 else if (op_mode == CONST_2) 1140 found = num == 2; 1141 else if (op_mode == CONST_4) 1142 found = num == 4; 1143 else if (op_mode == CONST_8) 1144 found = num == 8; 1145 else if (op_mode == CONST_16) 1146 found = num == 16; 1147 else 1148 found = 0; 1149 } 1150 else if (op_mode == PCREL && op_mode == x_mode) 1151 { 1152 /* movsd, bsr/bc and bsr/bs only come in PCREL16 flavour: 1153 If x_size is L_8, promote it. */ 1154 if (OP_KIND (this_try->opcode->how) == O_MOVSD 1155 || OP_KIND (this_try->opcode->how) == O_BSRBC 1156 || OP_KIND (this_try->opcode->how) == O_BSRBS) 1157 if (x_size == L_8) 1158 x_size = L_16; 1159 1160 /* The size of the displacement is important. */ 1161 if (op_size != x_size) 1162 found = 0; 1163 } 1164 else if ((op_mode == DISP || op_mode == IMM || op_mode == ABS 1165 || op_mode == INDEXB || op_mode == INDEXW 1166 || op_mode == INDEXL) 1167 && op_mode == x_mode) 1168 { 1169 /* Promote a L_24 to L_32 if it makes us match. */ 1170 if (x_size == L_24 && op_size == L_32) 1171 { 1172 x &= ~SIZE; 1173 x |= x_size = L_32; 1174 } 1175 1176 if (((x_size == L_16 && op_size == L_16U) 1177 || (x_size == L_8 && op_size == L_8U) 1178 || (x_size == L_3 && op_size == L_3NZ)) 1179 /* We're deliberately more permissive for ABS modes. */ 1180 && (op_mode == ABS 1181 || constant_fits_size_p (operands + i, op_size, 1182 op & NO_SYMBOLS))) 1183 x_size = op_size; 1184 1185 if (x_size != 0 && op_size != x_size) 1186 found = 0; 1187 else if (x_size == 0 1188 && ! constant_fits_size_p (operands + i, op_size, 1189 op & NO_SYMBOLS)) 1190 found = 0; 1191 } 1192 else if (op_mode != x_mode) 1193 { 1194 found = 0; 1195 } 1196 } 1197 } 1198 if (found) 1199 { 1200 if ((this_try->opcode->available == AV_H8SX && ! SXmode) 1201 || (this_try->opcode->available == AV_H8S && ! Smode) 1202 || (this_try->opcode->available == AV_H8H && ! Hmode)) 1203 found = 0, found_other = this_try; 1204 else if (this_size != size && (this_size != SN && size != SN)) 1205 found_mismatched = this_try, found = 0; 1206 1207 } 1208 } 1209 if (found) 1210 return this_try; 1211 if (found_other) 1212 { 1213 as_warn (_("Opcode `%s' with these operand types not available in %s mode"), 1214 found_other->opcode->name, 1215 (! Hmode && ! Smode ? "H8/300" 1216 : SXmode ? "H8sx" 1217 : Smode ? "H8/300S" 1218 : "H8/300H")); 1219 } 1220 else if (found_mismatched) 1221 { 1222 as_warn (_("mismatch between opcode size and operand size")); 1223 return found_mismatched; 1224 } 1225 return 0; 1226 } 1227 1228 static void 1229 check_operand (struct h8_op *operand, unsigned int width, char *string) 1230 { 1231 if (operand->exp.X_add_symbol == 0 1232 && operand->exp.X_op_symbol == 0) 1233 { 1234 /* No symbol involved, let's look at offset, it's dangerous if 1235 any of the high bits are not 0 or ff's, find out by oring or 1236 anding with the width and seeing if the answer is 0 or all 1237 fs. */ 1238 1239 if (! constant_fits_width_p (operand, width)) 1240 { 1241 if (width == 255 1242 && (operand->exp.X_add_number & 0xff00) == 0xff00) 1243 { 1244 /* Just ignore this one - which happens when trying to 1245 fit a 16 bit address truncated into an 8 bit address 1246 of something like bset. */ 1247 } 1248 else if (strcmp (string, "@") == 0 1249 && width == 0xffff 1250 && (operand->exp.X_add_number & 0xff8000) == 0xff8000) 1251 { 1252 /* Just ignore this one - which happens when trying to 1253 fit a 24 bit address truncated into a 16 bit address 1254 of something like mov.w. */ 1255 } 1256 else 1257 { 1258 as_warn (_("operand %s0x%lx out of range."), string, 1259 (unsigned long) operand->exp.X_add_number); 1260 } 1261 } 1262 } 1263 } 1264 1265 /* RELAXMODE has one of 3 values: 1266 1267 0 Output a "normal" reloc, no relaxing possible for this insn/reloc 1268 1269 1 Output a relaxable 24bit absolute mov.w address relocation 1270 (may relax into a 16bit absolute address). 1271 1272 2 Output a relaxable 16/24 absolute mov.b address relocation 1273 (may relax into an 8bit absolute address). */ 1274 1275 static void 1276 do_a_fix_imm (int offset, int nibble, struct h8_op *operand, int relaxmode) 1277 { 1278 int idx; 1279 int size; 1280 int where; 1281 char *bytes = frag_now->fr_literal + offset; 1282 1283 char *t = ((operand->mode & MODE) == IMM) ? "#" : "@"; 1284 1285 if (operand->exp.X_add_symbol == 0) 1286 { 1287 switch (operand->mode & SIZE) 1288 { 1289 case L_2: 1290 check_operand (operand, 0x3, t); 1291 bytes[0] |= (operand->exp.X_add_number & 3) << (nibble ? 0 : 4); 1292 break; 1293 case L_3: 1294 case L_3NZ: 1295 check_operand (operand, 0x7, t); 1296 bytes[0] |= (operand->exp.X_add_number & 7) << (nibble ? 0 : 4); 1297 break; 1298 case L_4: 1299 check_operand (operand, 0xF, t); 1300 bytes[0] |= (operand->exp.X_add_number & 15) << (nibble ? 0 : 4); 1301 break; 1302 case L_5: 1303 check_operand (operand, 0x1F, t); 1304 bytes[0] |= operand->exp.X_add_number & 31; 1305 break; 1306 case L_8: 1307 case L_8U: 1308 check_operand (operand, 0xff, t); 1309 bytes[0] |= operand->exp.X_add_number; 1310 break; 1311 case L_16: 1312 case L_16U: 1313 check_operand (operand, 0xffff, t); 1314 bytes[0] |= operand->exp.X_add_number >> 8; 1315 bytes[1] |= operand->exp.X_add_number >> 0; 1316 break; 1317 case L_24: 1318 check_operand (operand, 0xffffff, t); 1319 bytes[0] |= operand->exp.X_add_number >> 16; 1320 bytes[1] |= operand->exp.X_add_number >> 8; 1321 bytes[2] |= operand->exp.X_add_number >> 0; 1322 break; 1323 1324 case L_32: 1325 /* This should be done with bfd. */ 1326 bytes[0] |= operand->exp.X_add_number >> 24; 1327 bytes[1] |= operand->exp.X_add_number >> 16; 1328 bytes[2] |= operand->exp.X_add_number >> 8; 1329 bytes[3] |= operand->exp.X_add_number >> 0; 1330 if (relaxmode != 0) 1331 { 1332 idx = (relaxmode == 2) ? R_MOV24B1 : R_MOVL1; 1333 fix_new_exp (frag_now, offset, 4, &operand->exp, 0, idx); 1334 } 1335 break; 1336 } 1337 } 1338 else 1339 { 1340 switch (operand->mode & SIZE) 1341 { 1342 case L_24: 1343 case L_32: 1344 size = 4; 1345 where = (operand->mode & SIZE) == L_24 ? -1 : 0; 1346 if (relaxmode == 2) 1347 idx = R_MOV24B1; 1348 else if (relaxmode == 1) 1349 idx = R_MOVL1; 1350 else 1351 idx = R_RELLONG; 1352 break; 1353 default: 1354 as_bad (_("Can't work out size of operand.\n")); 1355 case L_16: 1356 case L_16U: 1357 size = 2; 1358 where = 0; 1359 if (relaxmode == 2) 1360 idx = R_MOV16B1; 1361 else 1362 idx = R_RELWORD; 1363 operand->exp.X_add_number = 1364 ((operand->exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; 1365 operand->exp.X_add_number |= (bytes[0] << 8) | bytes[1]; 1366 break; 1367 case L_8: 1368 size = 1; 1369 where = 0; 1370 idx = R_RELBYTE; 1371 operand->exp.X_add_number = 1372 ((operand->exp.X_add_number & 0xff) ^ 0x80) - 0x80; 1373 operand->exp.X_add_number |= bytes[0]; 1374 } 1375 1376 fix_new_exp (frag_now, 1377 offset + where, 1378 size, 1379 &operand->exp, 1380 0, 1381 idx); 1382 } 1383 } 1384 1385 /* Now we know what sort of opcodes it is, let's build the bytes. */ 1386 1387 static void 1388 build_bytes (const struct h8_instruction *this_try, struct h8_op *operand) 1389 { 1390 int i; 1391 char *output = frag_more (this_try->length); 1392 const op_type *nibble_ptr = this_try->opcode->data.nib; 1393 op_type c; 1394 unsigned int nibble_count = 0; 1395 int op_at[3]; 1396 int nib = 0; 1397 int movb = 0; 1398 char asnibbles[100]; 1399 char *p = asnibbles; 1400 int high, low; 1401 1402 if (!Hmode && this_try->opcode->available != AV_H8) 1403 as_warn (_("Opcode `%s' with these operand types not available in H8/300 mode"), 1404 this_try->opcode->name); 1405 else if (!Smode 1406 && this_try->opcode->available != AV_H8 1407 && this_try->opcode->available != AV_H8H) 1408 as_warn (_("Opcode `%s' with these operand types not available in H8/300H mode"), 1409 this_try->opcode->name); 1410 else if (!SXmode 1411 && this_try->opcode->available != AV_H8 1412 && this_try->opcode->available != AV_H8H 1413 && this_try->opcode->available != AV_H8S) 1414 as_warn (_("Opcode `%s' with these operand types not available in H8/300S mode"), 1415 this_try->opcode->name); 1416 1417 while (*nibble_ptr != (op_type) E) 1418 { 1419 int d; 1420 1421 nib = 0; 1422 c = *nibble_ptr++; 1423 1424 d = (c & OP3) == OP3 ? 2 : (c & DST) == DST ? 1 : 0; 1425 1426 if (c < 16) 1427 nib = c; 1428 else 1429 { 1430 int c2 = c & MODE; 1431 1432 if (c2 == REG || c2 == LOWREG 1433 || c2 == IND || c2 == PREINC || c2 == PREDEC 1434 || c2 == POSTINC || c2 == POSTDEC) 1435 { 1436 nib = operand[d].reg; 1437 if (c2 == LOWREG) 1438 nib &= 7; 1439 } 1440 1441 else if (c & CTRL) /* Control reg operand. */ 1442 nib = operand[d].reg; 1443 1444 else if ((c & DISPREG) == (DISPREG)) 1445 { 1446 nib = operand[d].reg; 1447 } 1448 else if (c2 == ABS) 1449 { 1450 operand[d].mode = c; 1451 op_at[d] = nibble_count; 1452 nib = 0; 1453 } 1454 else if (c2 == IMM || c2 == PCREL || c2 == ABS 1455 || (c & ABSJMP) || c2 == DISP) 1456 { 1457 operand[d].mode = c; 1458 op_at[d] = nibble_count; 1459 nib = 0; 1460 } 1461 else if ((c & IGNORE) || (c & DATA)) 1462 nib = 0; 1463 1464 else if (c2 == DBIT) 1465 { 1466 switch (operand[0].exp.X_add_number) 1467 { 1468 case 1: 1469 nib = c; 1470 break; 1471 case 2: 1472 nib = 0x8 | c; 1473 break; 1474 default: 1475 as_bad (_("Need #1 or #2 here")); 1476 } 1477 } 1478 else if (c2 == KBIT) 1479 { 1480 switch (operand[0].exp.X_add_number) 1481 { 1482 case 1: 1483 nib = 0; 1484 break; 1485 case 2: 1486 nib = 8; 1487 break; 1488 case 4: 1489 if (!Hmode) 1490 as_warn (_("#4 not valid on H8/300.")); 1491 nib = 9; 1492 break; 1493 1494 default: 1495 as_bad (_("Need #1 or #2 here")); 1496 break; 1497 } 1498 /* Stop it making a fix. */ 1499 operand[0].mode = 0; 1500 } 1501 1502 if (c & MEMRELAX) 1503 operand[d].mode |= MEMRELAX; 1504 1505 if (c & B31) 1506 nib |= 0x8; 1507 1508 if (c & B21) 1509 nib |= 0x4; 1510 1511 if (c & B11) 1512 nib |= 0x2; 1513 1514 if (c & B01) 1515 nib |= 0x1; 1516 1517 if (c2 == MACREG) 1518 { 1519 if (operand[0].mode == MACREG) 1520 /* stmac has mac[hl] as the first operand. */ 1521 nib = 2 + operand[0].reg; 1522 else 1523 /* ldmac has mac[hl] as the second operand. */ 1524 nib = 2 + operand[1].reg; 1525 } 1526 } 1527 nibble_count++; 1528 1529 *p++ = nib; 1530 } 1531 1532 /* Disgusting. Why, oh why didn't someone ask us for advice 1533 on the assembler format. */ 1534 if (OP_KIND (this_try->opcode->how) == O_LDM) 1535 { 1536 high = (operand[1].reg >> 8) & 0xf; 1537 low = (operand[1].reg) & 0xf; 1538 asnibbles[2] = high - low; 1539 asnibbles[7] = high; 1540 } 1541 else if (OP_KIND (this_try->opcode->how) == O_STM) 1542 { 1543 high = (operand[0].reg >> 8) & 0xf; 1544 low = (operand[0].reg) & 0xf; 1545 asnibbles[2] = high - low; 1546 asnibbles[7] = low; 1547 } 1548 1549 for (i = 0; i < this_try->length; i++) 1550 output[i] = (asnibbles[i * 2] << 4) | asnibbles[i * 2 + 1]; 1551 1552 /* Note if this is a movb or a bit manipulation instruction 1553 there is a special relaxation which only applies. */ 1554 if ( this_try->opcode->how == O (O_MOV, SB) 1555 || this_try->opcode->how == O (O_BCLR, SB) 1556 || this_try->opcode->how == O (O_BAND, SB) 1557 || this_try->opcode->how == O (O_BIAND, SB) 1558 || this_try->opcode->how == O (O_BILD, SB) 1559 || this_try->opcode->how == O (O_BIOR, SB) 1560 || this_try->opcode->how == O (O_BIST, SB) 1561 || this_try->opcode->how == O (O_BIXOR, SB) 1562 || this_try->opcode->how == O (O_BLD, SB) 1563 || this_try->opcode->how == O (O_BNOT, SB) 1564 || this_try->opcode->how == O (O_BOR, SB) 1565 || this_try->opcode->how == O (O_BSET, SB) 1566 || this_try->opcode->how == O (O_BST, SB) 1567 || this_try->opcode->how == O (O_BTST, SB) 1568 || this_try->opcode->how == O (O_BXOR, SB)) 1569 movb = 1; 1570 1571 /* Output any fixes. */ 1572 for (i = 0; i < this_try->noperands; i++) 1573 { 1574 int x = operand[i].mode; 1575 int x_mode = x & MODE; 1576 1577 if (x_mode == IMM || x_mode == DISP) 1578 do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2, 1579 op_at[i] & 1, operand + i, (x & MEMRELAX) != 0); 1580 1581 else if (x_mode == ABS) 1582 do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2, 1583 op_at[i] & 1, operand + i, 1584 (x & MEMRELAX) ? movb + 1 : 0); 1585 1586 else if (x_mode == PCREL) 1587 { 1588 int size16 = (x & SIZE) == L_16; 1589 int size = size16 ? 2 : 1; 1590 int type = size16 ? R_PCRWORD : R_PCRBYTE; 1591 fixS *fixP; 1592 1593 check_operand (operand + i, size16 ? 0x7fff : 0x7f, "@"); 1594 1595 if (operand[i].exp.X_add_number & 1) 1596 as_warn (_("branch operand has odd offset (%lx)\n"), 1597 (unsigned long) operand->exp.X_add_number); 1598 #ifndef OBJ_ELF 1599 /* The COFF port has always been off by one, changing it 1600 now would be an incompatible change, so we leave it as-is. 1601 1602 We don't want to do this for ELF as we want to be 1603 compatible with the proposed ELF format from Hitachi. */ 1604 operand[i].exp.X_add_number -= 1; 1605 #endif 1606 if (size16) 1607 { 1608 operand[i].exp.X_add_number = 1609 ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; 1610 } 1611 else 1612 { 1613 operand[i].exp.X_add_number = 1614 ((operand[i].exp.X_add_number & 0xff) ^ 0x80) - 0x80; 1615 } 1616 1617 /* For BRA/S. */ 1618 if (! size16) 1619 operand[i].exp.X_add_number |= output[op_at[i] / 2]; 1620 1621 fixP = fix_new_exp (frag_now, 1622 output - frag_now->fr_literal + op_at[i] / 2, 1623 size, 1624 &operand[i].exp, 1625 1, 1626 type); 1627 fixP->fx_signed = 1; 1628 } 1629 else if (x_mode == MEMIND) 1630 { 1631 check_operand (operand + i, 0xff, "@@"); 1632 fix_new_exp (frag_now, 1633 output - frag_now->fr_literal + 1, 1634 1, 1635 &operand[i].exp, 1636 0, 1637 R_MEM_INDIRECT); 1638 } 1639 else if (x_mode == VECIND) 1640 { 1641 check_operand (operand + i, 0x7f, "@@"); 1642 /* FIXME: approximating the effect of "B31" here... 1643 This is very hackish, and ought to be done a better way. */ 1644 operand[i].exp.X_add_number |= 0x80; 1645 fix_new_exp (frag_now, 1646 output - frag_now->fr_literal + 1, 1647 1, 1648 &operand[i].exp, 1649 0, 1650 R_MEM_INDIRECT); 1651 } 1652 else if (x & ABSJMP) 1653 { 1654 int where = 0; 1655 bfd_reloc_code_real_type reloc_type = R_JMPL1; 1656 1657 #ifdef OBJ_ELF 1658 /* To be compatible with the proposed H8 ELF format, we 1659 want the relocation's offset to point to the first byte 1660 that will be modified, not to the start of the instruction. */ 1661 1662 if ((operand->mode & SIZE) == L_32) 1663 { 1664 where = 2; 1665 reloc_type = R_RELLONG; 1666 } 1667 else 1668 where = 1; 1669 #endif 1670 1671 /* This jmp may be a jump or a branch. */ 1672 1673 check_operand (operand + i, 1674 SXmode ? 0xffffffff : Hmode ? 0xffffff : 0xffff, 1675 "@"); 1676 1677 if (operand[i].exp.X_add_number & 1) 1678 as_warn (_("branch operand has odd offset (%lx)\n"), 1679 (unsigned long) operand->exp.X_add_number); 1680 1681 if (!Hmode) 1682 operand[i].exp.X_add_number = 1683 ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; 1684 fix_new_exp (frag_now, 1685 output - frag_now->fr_literal + where, 1686 4, 1687 &operand[i].exp, 1688 0, 1689 reloc_type); 1690 } 1691 } 1692 } 1693 1694 /* Try to give an intelligent error message for common and simple to 1695 detect errors. */ 1696 1697 static void 1698 clever_message (const struct h8_instruction *instruction, 1699 struct h8_op *operand) 1700 { 1701 /* Find out if there was more than one possible opcode. */ 1702 1703 if ((instruction + 1)->idx != instruction->idx) 1704 { 1705 int argn; 1706 1707 /* Only one opcode of this flavour, try to guess which operand 1708 didn't match. */ 1709 for (argn = 0; argn < instruction->noperands; argn++) 1710 { 1711 switch (instruction->opcode->args.nib[argn]) 1712 { 1713 case RD16: 1714 if (operand[argn].mode != RD16) 1715 { 1716 as_bad (_("destination operand must be 16 bit register")); 1717 return; 1718 1719 } 1720 break; 1721 1722 case RS8: 1723 if (operand[argn].mode != RS8) 1724 { 1725 as_bad (_("source operand must be 8 bit register")); 1726 return; 1727 } 1728 break; 1729 1730 case ABS16DST: 1731 if (operand[argn].mode != ABS16DST) 1732 { 1733 as_bad (_("destination operand must be 16bit absolute address")); 1734 return; 1735 } 1736 break; 1737 case RD8: 1738 if (operand[argn].mode != RD8) 1739 { 1740 as_bad (_("destination operand must be 8 bit register")); 1741 return; 1742 } 1743 break; 1744 1745 case ABS16SRC: 1746 if (operand[argn].mode != ABS16SRC) 1747 { 1748 as_bad (_("source operand must be 16bit absolute address")); 1749 return; 1750 } 1751 break; 1752 1753 } 1754 } 1755 } 1756 as_bad (_("invalid operands")); 1757 } 1758 1759 1760 /* If OPERAND is part of an address, adjust its size and value given 1761 that it addresses SIZE bytes. 1762 1763 This function decides how big non-immediate constants are when no 1764 size was explicitly given. It also scales down the assembly-level 1765 displacement in an @(d:2,ERn) operand. */ 1766 1767 static void 1768 fix_operand_size (struct h8_op *operand, int size) 1769 { 1770 if (SXmode && (operand->mode & MODE) == DISP) 1771 { 1772 /* If the user didn't specify an operand width, see if we 1773 can use @(d:2,ERn). */ 1774 if ((operand->mode & SIZE) == 0 1775 && operand->exp.X_add_symbol == 0 1776 && operand->exp.X_op_symbol == 0 1777 && (operand->exp.X_add_number == size 1778 || operand->exp.X_add_number == size * 2 1779 || operand->exp.X_add_number == size * 3)) 1780 operand->mode |= L_2; 1781 1782 /* Scale down the displacement in an @(d:2,ERn) operand. 1783 X_add_number then contains the desired field value. */ 1784 if ((operand->mode & SIZE) == L_2) 1785 { 1786 if (operand->exp.X_add_number % size != 0) 1787 as_warn (_("operand/size mis-match")); 1788 operand->exp.X_add_number /= size; 1789 } 1790 } 1791 1792 if ((operand->mode & SIZE) == 0) 1793 switch (operand->mode & MODE) 1794 { 1795 case DISP: 1796 case INDEXB: 1797 case INDEXW: 1798 case INDEXL: 1799 case ABS: 1800 /* Pick a 24-bit address unless we know that a 16-bit address 1801 is safe. get_specific() will relax L_24 into L_32 where 1802 necessary. */ 1803 if (Hmode 1804 && !Nmode 1805 && (operand->exp.X_add_number < -32768 1806 || operand->exp.X_add_number > 32767 1807 || operand->exp.X_add_symbol != 0 1808 || operand->exp.X_op_symbol != 0)) 1809 operand->mode |= L_24; 1810 else 1811 operand->mode |= L_16; 1812 break; 1813 1814 case PCREL: 1815 /* This condition is long standing, though somewhat suspect. */ 1816 if (operand->exp.X_add_number > -128 1817 && operand->exp.X_add_number < 127) 1818 { 1819 if (operand->exp.X_add_symbol != NULL) 1820 operand->mode |= bsize; 1821 else 1822 operand->mode |= L_8; 1823 } 1824 else 1825 operand->mode |= L_16; 1826 break; 1827 } 1828 } 1829 1830 1831 /* This is the guts of the machine-dependent assembler. STR points to 1832 a machine dependent instruction. This function is supposed to emit 1833 the frags/bytes it assembles. */ 1834 1835 void 1836 md_assemble (char *str) 1837 { 1838 char *op_start; 1839 char *op_end; 1840 struct h8_op operand[3]; 1841 const struct h8_instruction *instruction; 1842 const struct h8_instruction *prev_instruction; 1843 1844 char *dot = 0; 1845 char *slash = 0; 1846 char c; 1847 int size, i; 1848 1849 /* Drop leading whitespace. */ 1850 while (*str == ' ') 1851 str++; 1852 1853 /* Find the op code end. */ 1854 for (op_start = op_end = str; 1855 *op_end != 0 && *op_end != ' '; 1856 op_end++) 1857 { 1858 if (*op_end == '.') 1859 { 1860 dot = op_end + 1; 1861 *op_end = 0; 1862 op_end += 2; 1863 break; 1864 } 1865 else if (*op_end == '/' && ! slash) 1866 slash = op_end; 1867 } 1868 1869 if (op_end == op_start) 1870 { 1871 as_bad (_("can't find opcode ")); 1872 } 1873 c = *op_end; 1874 1875 *op_end = 0; 1876 1877 /* The assembler stops scanning the opcode at slashes, so it fails 1878 to make characters following them lower case. Fix them. */ 1879 if (slash) 1880 while (*++slash) 1881 *slash = TOLOWER (*slash); 1882 1883 instruction = (const struct h8_instruction *) 1884 hash_find (opcode_hash_control, op_start); 1885 1886 if (instruction == NULL) 1887 { 1888 as_bad (_("unknown opcode")); 1889 return; 1890 } 1891 1892 /* We used to set input_line_pointer to the result of get_operands, 1893 but that is wrong. Our caller assumes we don't change it. */ 1894 1895 operand[0].mode = 0; 1896 operand[1].mode = 0; 1897 operand[2].mode = 0; 1898 1899 if (OP_KIND (instruction->opcode->how) == O_MOVAB 1900 || OP_KIND (instruction->opcode->how) == O_MOVAW 1901 || OP_KIND (instruction->opcode->how) == O_MOVAL) 1902 get_mova_operands (op_end, operand); 1903 else if (OP_KIND (instruction->opcode->how) == O_RTEL 1904 || OP_KIND (instruction->opcode->how) == O_RTSL) 1905 get_rtsl_operands (op_end, operand); 1906 else 1907 get_operands (instruction->noperands, op_end, operand); 1908 1909 *op_end = c; 1910 prev_instruction = instruction; 1911 1912 /* Now we have operands from instruction. 1913 Let's check them out for ldm and stm. */ 1914 if (OP_KIND (instruction->opcode->how) == O_LDM) 1915 { 1916 /* The first operand must be @er7+, and the 1917 second operand must be a register pair. */ 1918 if ((operand[0].mode != RSINC) 1919 || (operand[0].reg != 7) 1920 || ((operand[1].reg & 0x80000000) == 0)) 1921 as_bad (_("invalid operand in ldm")); 1922 } 1923 else if (OP_KIND (instruction->opcode->how) == O_STM) 1924 { 1925 /* The first operand must be a register pair, 1926 and the second operand must be @-er7. */ 1927 if (((operand[0].reg & 0x80000000) == 0) 1928 || (operand[1].mode != RDDEC) 1929 || (operand[1].reg != 7)) 1930 as_bad (_("invalid operand in stm")); 1931 } 1932 1933 size = SN; 1934 if (dot) 1935 { 1936 switch (TOLOWER (*dot)) 1937 { 1938 case 'b': 1939 size = SB; 1940 break; 1941 1942 case 'w': 1943 size = SW; 1944 break; 1945 1946 case 'l': 1947 size = SL; 1948 break; 1949 } 1950 } 1951 if (OP_KIND (instruction->opcode->how) == O_MOVAB || 1952 OP_KIND (instruction->opcode->how) == O_MOVAW || 1953 OP_KIND (instruction->opcode->how) == O_MOVAL) 1954 { 1955 switch (operand[0].mode & MODE) 1956 { 1957 case INDEXB: 1958 default: 1959 fix_operand_size (&operand[1], 1); 1960 break; 1961 case INDEXW: 1962 fix_operand_size (&operand[1], 2); 1963 break; 1964 case INDEXL: 1965 fix_operand_size (&operand[1], 4); 1966 break; 1967 } 1968 } 1969 else 1970 { 1971 for (i = 0; i < 3 && operand[i].mode != 0; i++) 1972 switch (size) 1973 { 1974 case SN: 1975 case SB: 1976 default: 1977 fix_operand_size (&operand[i], 1); 1978 break; 1979 case SW: 1980 fix_operand_size (&operand[i], 2); 1981 break; 1982 case SL: 1983 fix_operand_size (&operand[i], 4); 1984 break; 1985 } 1986 } 1987 1988 instruction = get_specific (instruction, operand, size); 1989 1990 if (instruction == 0) 1991 { 1992 /* Couldn't find an opcode which matched the operands. */ 1993 char *where = frag_more (2); 1994 1995 where[0] = 0x0; 1996 where[1] = 0x0; 1997 clever_message (prev_instruction, operand); 1998 1999 return; 2000 } 2001 2002 build_bytes (instruction, operand); 2003 2004 dwarf2_emit_insn (instruction->length); 2005 } 2006 2007 symbolS * 2008 md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 2009 { 2010 return 0; 2011 } 2012 2013 /* Various routines to kill one day. */ 2014 2015 char * 2016 md_atof (int type, char *litP, int *sizeP) 2017 { 2018 return ieee_md_atof (type, litP, sizeP, TRUE); 2019 } 2020 2021 #define OPTION_H_TICK_HEX (OPTION_MD_BASE) 2023 2024 const char *md_shortopts = ""; 2025 struct option md_longopts[] = { 2026 { "h-tick-hex", no_argument, NULL, OPTION_H_TICK_HEX }, 2027 {NULL, no_argument, NULL, 0} 2028 }; 2029 2030 size_t md_longopts_size = sizeof (md_longopts); 2031 2032 int 2033 md_parse_option (int c ATTRIBUTE_UNUSED, char *arg ATTRIBUTE_UNUSED) 2034 { 2035 switch (c) 2036 { 2037 case OPTION_H_TICK_HEX: 2038 enable_h_tick_hex = 1; 2039 break; 2040 2041 default: 2042 return 0; 2043 } 2044 return 1; 2045 } 2046 2047 void 2048 md_show_usage (FILE *stream ATTRIBUTE_UNUSED) 2049 { 2050 } 2051 2052 void tc_aout_fix_to_chars (void); 2054 2055 void 2056 tc_aout_fix_to_chars (void) 2057 { 2058 printf (_("call to tc_aout_fix_to_chars \n")); 2059 abort (); 2060 } 2061 2062 void 2063 md_convert_frag (bfd *headers ATTRIBUTE_UNUSED, 2064 segT seg ATTRIBUTE_UNUSED, 2065 fragS *fragP ATTRIBUTE_UNUSED) 2066 { 2067 printf (_("call to md_convert_frag \n")); 2068 abort (); 2069 } 2070 2071 valueT 2072 md_section_align (segT segment, valueT size) 2073 { 2074 int align = bfd_get_section_alignment (stdoutput, segment); 2075 return ((size + (1 << align) - 1) & (-1 << align)); 2076 } 2077 2078 void 2079 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) 2080 { 2081 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; 2082 long val = *valP; 2083 2084 switch (fixP->fx_size) 2085 { 2086 case 1: 2087 *buf++ = val; 2088 break; 2089 case 2: 2090 *buf++ = (val >> 8); 2091 *buf++ = val; 2092 break; 2093 case 4: 2094 *buf++ = (val >> 24); 2095 *buf++ = (val >> 16); 2096 *buf++ = (val >> 8); 2097 *buf++ = val; 2098 break; 2099 case 8: 2100 /* This can arise when the .quad or .8byte pseudo-ops are used. 2101 Returning here (without setting fx_done) will cause the code 2102 to attempt to generate a reloc which will then fail with the 2103 slightly more helpful error message: "Cannot represent 2104 relocation type BFD_RELOC_64". */ 2105 return; 2106 default: 2107 abort (); 2108 } 2109 2110 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0) 2111 fixP->fx_done = 1; 2112 } 2113 2114 int 2115 md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED, 2116 segT segment_type ATTRIBUTE_UNUSED) 2117 { 2118 printf (_("call to md_estimate_size_before_relax \n")); 2119 abort (); 2120 } 2121 2122 /* Put number into target byte order. */ 2123 void 2124 md_number_to_chars (char *ptr, valueT use, int nbytes) 2125 { 2126 number_to_chars_bigendian (ptr, use, nbytes); 2127 } 2128 2129 long 2130 md_pcrel_from (fixS *fixP ATTRIBUTE_UNUSED) 2131 { 2132 abort (); 2133 } 2134 2135 arelent * 2136 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) 2137 { 2138 arelent *rel; 2139 bfd_reloc_code_real_type r_type; 2140 2141 if (fixp->fx_addsy && fixp->fx_subsy) 2142 { 2143 if ((S_GET_SEGMENT (fixp->fx_addsy) != S_GET_SEGMENT (fixp->fx_subsy)) 2144 || S_GET_SEGMENT (fixp->fx_addsy) == undefined_section) 2145 { 2146 as_bad_where (fixp->fx_file, fixp->fx_line, 2147 _("Difference of symbols in different sections is not supported")); 2148 return NULL; 2149 } 2150 } 2151 2152 rel = xmalloc (sizeof (arelent)); 2153 rel->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); 2154 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 2155 rel->address = fixp->fx_frag->fr_address + fixp->fx_where; 2156 rel->addend = fixp->fx_offset; 2157 2158 r_type = fixp->fx_r_type; 2159 2160 #define DEBUG 0 2161 #if DEBUG 2162 fprintf (stderr, "%s\n", bfd_get_reloc_code_name (r_type)); 2163 fflush (stderr); 2164 #endif 2165 rel->howto = bfd_reloc_type_lookup (stdoutput, r_type); 2166 if (rel->howto == NULL) 2167 { 2168 as_bad_where (fixp->fx_file, fixp->fx_line, 2169 _("Cannot represent relocation type %s"), 2170 bfd_get_reloc_code_name (r_type)); 2171 return NULL; 2172 } 2173 2174 return rel; 2175 } 2176
Indexes created Fri Mar 20 00:23:26 UTC 2026