tc-h8300.c revision 1.1.1.12
1 /* tc-h8300.c -- Assemble code for the Renesas H8/300 2 Copyright (C) 1991-2026 Free Software Foundation, Inc. 3 4 This file is part of GAS, the GNU Assembler. 5 6 GAS is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GAS is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GAS; see the file COPYING. If not, write to the Free 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 19 02110-1301, USA. */ 20 21 /* Written By Steve Chamberlain <sac (at) cygnus.com>. */ 22 23 #include "as.h" 24 #include "subsegs.h" 25 #include "dwarf2dbg.h" 26 27 #define DEFINE_TABLE 28 #define h8_opcodes ops 29 #include "opcode/h8300.h" 30 #include "safe-ctype.h" 31 #include "elf/h8.h" 32 33 const char comment_chars[] = ";"; 34 const char line_comment_chars[] = "#"; 35 #ifdef TE_LINUX 36 const char line_separator_chars[] = "!"; 37 #else 38 const char line_separator_chars[] = ""; 39 #endif 40 41 static void sbranch (int); 42 static void h8300hmode (int); 43 static void h8300smode (int); 44 static void h8300hnmode (int); 45 static void h8300snmode (int); 46 static void h8300sxmode (int); 47 static void h8300sxnmode (int); 48 static void pint (int); 49 50 int Hmode; 51 int Smode; 52 int Nmode; 53 int SXmode; 54 55 static int default_mach = bfd_mach_h8300; 56 57 #define PSIZE (Hmode && !Nmode ? L_32 : L_16) 58 59 static int bsize = L_8; /* Default branch displacement. */ 60 61 struct h8_instruction 62 { 63 int length; 64 int noperands; 65 int idx; 66 int size; 67 const struct h8_opcode *opcode; 68 }; 69 70 static struct h8_instruction *h8_instructions; 71 72 static void 73 h8300hmode (int arg ATTRIBUTE_UNUSED) 74 { 75 Hmode = 1; 76 Smode = 0; 77 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300h)) 78 as_warn (_("could not set architecture and machine")); 79 } 80 81 static void 82 h8300smode (int arg ATTRIBUTE_UNUSED) 83 { 84 Smode = 1; 85 Hmode = 1; 86 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300s)) 87 as_warn (_("could not set architecture and machine")); 88 } 89 90 static void 91 h8300hnmode (int arg ATTRIBUTE_UNUSED) 92 { 93 Hmode = 1; 94 Smode = 0; 95 Nmode = 1; 96 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300hn)) 97 as_warn (_("could not set architecture and machine")); 98 } 99 100 static void 101 h8300snmode (int arg ATTRIBUTE_UNUSED) 102 { 103 Smode = 1; 104 Hmode = 1; 105 Nmode = 1; 106 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sn)) 107 as_warn (_("could not set architecture and machine")); 108 } 109 110 static void 111 h8300sxmode (int arg ATTRIBUTE_UNUSED) 112 { 113 Smode = 1; 114 Hmode = 1; 115 SXmode = 1; 116 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sx)) 117 as_warn (_("could not set architecture and machine")); 118 } 119 120 static void 121 h8300sxnmode (int arg ATTRIBUTE_UNUSED) 122 { 123 Smode = 1; 124 Hmode = 1; 125 SXmode = 1; 126 Nmode = 1; 127 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sxn)) 128 as_warn (_("could not set architecture and machine")); 129 } 130 131 static void 132 sbranch (int size) 133 { 134 bsize = size; 135 } 136 137 static void 138 pint (int arg ATTRIBUTE_UNUSED) 139 { 140 cons (Hmode ? 4 : 2); 141 } 142 143 /* Like obj_elf_section, but issues a warning for new 144 sections which do not have an attribute specification. */ 145 146 static void 147 h8300_elf_section (int push) 148 { 149 static const char * known_data_sections [] 150 = { ".rodata", ".tdata", ".tbss", ".gnu_object_only" }; 151 static const char * known_data_prefixes [] 152 = { ".debug", ".zdebug", ".gnu.warning" }; 153 char * saved_ilp = input_line_pointer; 154 const char * name; 155 156 name = obj_elf_section_name (); 157 if (name == NULL) 158 return; 159 160 if (* input_line_pointer != ',' 161 && bfd_get_section_by_name (stdoutput, name) == NULL) 162 { 163 signed int i; 164 165 /* Ignore this warning for well known data sections. */ 166 for (i = ARRAY_SIZE (known_data_sections); i--;) 167 if (strcmp (name, known_data_sections[i]) == 0) 168 break; 169 170 if (i < 0) 171 for (i = ARRAY_SIZE (known_data_prefixes); i--;) 172 if (startswith (name, known_data_prefixes[i])) 173 break; 174 175 if (i < 0) 176 as_warn (_("new section '%s' defined without attributes - this might cause problems"), name); 177 } 178 179 /* FIXME: We ought to free the memory allocated by obj_elf_section_name() 180 for 'name', but we do not know if it was taken from the obstack, via 181 demand_copy_C_string(), or xmalloc()ed. */ 182 input_line_pointer = saved_ilp; 183 obj_elf_section (push); 184 } 185 186 /* This table describes all the machine specific pseudo-ops the assembler 187 has to support. The fields are: 188 pseudo-op name without dot 189 function to call to execute this pseudo-op 190 Integer arg to pass to the function. */ 191 192 const pseudo_typeS md_pseudo_table[] = 193 { 194 {"h8300h", h8300hmode, 0}, 195 {"h8300hn", h8300hnmode, 0}, 196 {"h8300s", h8300smode, 0}, 197 {"h8300sn", h8300snmode, 0}, 198 {"h8300sx", h8300sxmode, 0}, 199 {"h8300sxn", h8300sxnmode, 0}, 200 {"sbranch", sbranch, L_8}, 201 {"lbranch", sbranch, L_16}, 202 203 {"int", pint, 0}, 204 {"data.b", cons, 1}, 205 {"data.w", cons, 2}, 206 {"data.l", cons, 4}, 207 {"form", listing_psize, 0}, 208 {"heading", listing_title, 0}, 209 {"import", s_ignore, 0}, 210 {"page", listing_eject, 0}, 211 {"program", s_ignore, 0}, 212 213 {"section", h8300_elf_section, 0}, 214 {"section.s", h8300_elf_section, 0}, 215 {"sect", h8300_elf_section, 0}, 216 {"sect.s", h8300_elf_section, 0}, 217 218 {0, 0, 0} 219 }; 220 221 const char EXP_CHARS[] = "eE"; 222 223 /* Chars that mean this number is a floating point constant 224 As in 0f12.456 225 or 0d1.2345e12. */ 226 const char FLT_CHARS[] = "rRsSfFdDxXpP"; 227 228 static htab_t opcode_hash_control; /* Opcode mnemonics. */ 229 230 /* This function is called once, at assembler startup time. This 231 should set up all the tables, etc. that the MD part of the assembler 232 needs. */ 233 234 void 235 md_begin (void) 236 { 237 unsigned int nopcodes; 238 struct h8_opcode *p, *p1; 239 struct h8_instruction *pi; 240 int idx = 0; 241 242 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, default_mach)) 243 as_warn (_("could not set architecture and machine")); 244 245 opcode_hash_control = str_htab_create (); 246 247 nopcodes = sizeof (h8_opcodes) / sizeof (struct h8_opcode); 248 249 h8_instructions = XNEWVEC (struct h8_instruction, nopcodes); 250 251 pi = h8_instructions; 252 p1 = h8_opcodes; 253 /* We do a minimum amount of sorting on the opcode table; this is to 254 make it easy to describe the mova instructions without unnecessary 255 code duplication. 256 Sorting only takes place inside blocks of instructions of the form 257 X/Y, so for example mova/b, mova/w and mova/l can be intermixed. */ 258 while (p1) 259 { 260 struct h8_opcode *first_skipped = 0; 261 int len, cmplen = 0; 262 const char *src = p1->name; 263 char *dst, *buffer; 264 265 if (p1->name == 0) 266 break; 267 /* Strip off any . part when inserting the opcode and only enter 268 unique codes into the hash table. */ 269 dst = buffer = notes_alloc (strlen (src) + 1); 270 while (*src) 271 { 272 if (*src == '.') 273 { 274 src++; 275 break; 276 } 277 if (*src == '/') 278 cmplen = src - p1->name + 1; 279 *dst++ = *src++; 280 } 281 *dst = 0; 282 len = dst - buffer; 283 if (cmplen == 0) 284 cmplen = len; 285 str_hash_insert (opcode_hash_control, buffer, pi, 0); 286 idx++; 287 288 for (p = p1; p->name; p++) 289 { 290 /* A negative TIME is used to indicate that we've added this opcode 291 already. */ 292 if (p->time == -1) 293 continue; 294 if (strncmp (p->name, buffer, cmplen) != 0 295 || (p->name[cmplen] != '\0' && p->name[cmplen] != '.' 296 && p->name[cmplen - 1] != '/')) 297 { 298 if (first_skipped == 0) 299 first_skipped = p; 300 break; 301 } 302 if (strncmp (p->name, buffer, len) != 0) 303 { 304 if (first_skipped == 0) 305 first_skipped = p; 306 continue; 307 } 308 309 p->time = -1; 310 pi->size = p->name[len] == '.' ? p->name[len + 1] : 0; 311 pi->idx = idx; 312 313 /* Find the number of operands. */ 314 pi->noperands = 0; 315 while (pi->noperands < 3 && p->args.nib[pi->noperands] != (op_type) E) 316 pi->noperands++; 317 318 /* Find the length of the opcode in bytes. */ 319 pi->length = 0; 320 while (p->data.nib[pi->length * 2] != (op_type) E) 321 pi->length++; 322 323 pi->opcode = p; 324 pi++; 325 } 326 p1 = first_skipped; 327 } 328 329 /* Add entry for the NULL vector terminator. */ 330 pi->length = 0; 331 pi->noperands = 0; 332 pi->idx = 0; 333 pi->size = 0; 334 pi->opcode = 0; 335 336 linkrelax = 1; 337 } 338 339 struct h8_op 340 { 341 op_type mode; 342 unsigned reg; 343 expressionS exp; 344 }; 345 346 static void clever_message (const struct h8_instruction *, struct h8_op *); 347 static void fix_operand_size (struct h8_op *, int); 348 static void build_bytes (const struct h8_instruction *, struct h8_op *); 349 static void do_a_fix_imm (int, int, struct h8_op *, int, const struct h8_instruction *); 350 static void check_operand (struct h8_op *, unsigned int, const char *); 351 static const struct h8_instruction * get_specific (const struct h8_instruction *, struct h8_op *, int) ; 352 static char *get_operands (unsigned, char *, struct h8_op *); 353 static void get_operand (char **, struct h8_op *, int); 354 static int parse_reg (char *, op_type *, unsigned *, int); 355 static char *skip_colonthing (char *, int *); 356 static char *parse_exp (char *, struct h8_op *); 357 358 static int constant_fits_size_p (struct h8_op *, int, int); 359 360 /* 361 parse operands 362 WREG r0,r1,r2,r3,r4,r5,r6,r7,fp,sp 363 r0l,r0h,..r7l,r7h 364 @WREG 365 @WREG+ 366 @-WREG 367 #const 368 ccr 369 */ 370 371 /* Try to parse a reg name. Return the number of chars consumed. */ 372 373 static int 374 parse_reg (char *src, op_type *mode, unsigned int *reg, int direction) 375 { 376 char *end; 377 int len; 378 379 /* Cribbed from get_symbol_name. */ 380 if (!is_name_beginner (*src) || *src == '\001') 381 return 0; 382 end = src + 1; 383 while ((is_part_of_name (*end) && *end != '.') || *end == '\001') 384 end++; 385 len = end - src; 386 387 if (len == 2 && TOLOWER (src[0]) == 's' && TOLOWER (src[1]) == 'p') 388 { 389 *mode = PSIZE | REG | direction; 390 *reg = 7; 391 return len; 392 } 393 if (len == 3 && 394 TOLOWER (src[0]) == 'c' && 395 TOLOWER (src[1]) == 'c' && 396 TOLOWER (src[2]) == 'r') 397 { 398 *mode = CCR; 399 *reg = 0; 400 return len; 401 } 402 if (len == 3 && 403 TOLOWER (src[0]) == 'e' && 404 TOLOWER (src[1]) == 'x' && 405 TOLOWER (src[2]) == 'r') 406 { 407 *mode = EXR; 408 *reg = 1; 409 return len; 410 } 411 if (len == 3 && 412 TOLOWER (src[0]) == 'v' && 413 TOLOWER (src[1]) == 'b' && 414 TOLOWER (src[2]) == 'r') 415 { 416 *mode = VBR; 417 *reg = 6; 418 return len; 419 } 420 if (len == 3 && 421 TOLOWER (src[0]) == 's' && 422 TOLOWER (src[1]) == 'b' && 423 TOLOWER (src[2]) == 'r') 424 { 425 *mode = SBR; 426 *reg = 7; 427 return len; 428 } 429 if (len == 2 && TOLOWER (src[0]) == 'f' && TOLOWER (src[1]) == 'p') 430 { 431 *mode = PSIZE | REG | direction; 432 *reg = 6; 433 return len; 434 } 435 if (len == 3 && TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' && 436 src[2] >= '0' && src[2] <= '7') 437 { 438 *mode = L_32 | REG | direction; 439 *reg = src[2] - '0'; 440 if (!Hmode) 441 as_warn (_("Reg not valid for H8/300")); 442 return len; 443 } 444 if (len == 2 && TOLOWER (src[0]) == 'e' && src[1] >= '0' && src[1] <= '7') 445 { 446 *mode = L_16 | REG | direction; 447 *reg = src[1] - '0' + 8; 448 if (!Hmode) 449 as_warn (_("Reg not valid for H8/300")); 450 return len; 451 } 452 453 if (TOLOWER (src[0]) == 'r') 454 { 455 if (src[1] >= '0' && src[1] <= '7') 456 { 457 if (len == 3 && TOLOWER (src[2]) == 'l') 458 { 459 *mode = L_8 | REG | direction; 460 *reg = (src[1] - '0') + 8; 461 return len; 462 } 463 if (len == 3 && TOLOWER (src[2]) == 'h') 464 { 465 *mode = L_8 | REG | direction; 466 *reg = (src[1] - '0'); 467 return len; 468 } 469 if (len == 2) 470 { 471 *mode = L_16 | REG | direction; 472 *reg = (src[1] - '0'); 473 return len; 474 } 475 } 476 } 477 478 return 0; 479 } 480 481 482 /* Parse an immediate or address-related constant and store it in OP. 483 If the user also specifies the operand's size, store that size 484 in OP->MODE, otherwise leave it for later code to decide. */ 485 486 static char * 487 parse_exp (char *src, struct h8_op *op) 488 { 489 char *save; 490 491 save = input_line_pointer; 492 input_line_pointer = src; 493 expression (&op->exp); 494 if (op->exp.X_op == O_absent) 495 as_bad (_("missing operand")); 496 src = input_line_pointer; 497 input_line_pointer = save; 498 499 return skip_colonthing (src, &op->mode); 500 } 501 502 503 /* If SRC starts with an explicit operand size, skip it and store the size 504 in *MODE. Leave *MODE unchanged otherwise. */ 505 506 static char * 507 skip_colonthing (char *src, int *mode) 508 { 509 if (*src == ':') 510 { 511 src++; 512 *mode &= ~SIZE; 513 if (src[0] == '8' && !ISDIGIT (src[1])) 514 *mode |= L_8; 515 else if (src[0] == '2' && !ISDIGIT (src[1])) 516 *mode |= L_2; 517 else if (src[0] == '3' && !ISDIGIT (src[1])) 518 *mode |= L_3; 519 else if (src[0] == '4' && !ISDIGIT (src[1])) 520 *mode |= L_4; 521 else if (src[0] == '5' && !ISDIGIT (src[1])) 522 *mode |= L_5; 523 else if (src[0] == '2' && src[1] == '4' && !ISDIGIT (src[2])) 524 *mode |= L_24; 525 else if (src[0] == '3' && src[1] == '2' && !ISDIGIT (src[2])) 526 *mode |= L_32; 527 else if (src[0] == '1' && src[1] == '6' && !ISDIGIT (src[2])) 528 *mode |= L_16; 529 else 530 as_bad (_("invalid operand size requested")); 531 532 while (ISDIGIT (*src)) 533 src++; 534 } 535 return src; 536 } 537 538 /* The many forms of operand: 539 540 Rn Register direct 541 @Rn Register indirect 542 @(exp[:16], Rn) Register indirect with displacement 543 @Rn+ 544 @-Rn 545 @aa:8 absolute 8 bit 546 @aa:16 absolute 16 bit 547 @aa absolute 16 bit 548 549 #xx[:size] immediate data 550 @(exp:[8], pc) pc rel 551 @@aa[:8] memory indirect. */ 552 553 static int 554 constant_fits_width_p (struct h8_op *operand, offsetT width) 555 { 556 offsetT num; 557 558 num = ((operand->exp.X_add_number & 0xffffffff) ^ 0x80000000) - 0x80000000; 559 return (num & ~width) == 0 || (num | width) == ~0; 560 } 561 562 static int 563 constant_fits_size_p (struct h8_op *operand, int size, int no_symbols) 564 { 565 offsetT num; 566 567 if (no_symbols 568 && (operand->exp.X_add_symbol != 0 || operand->exp.X_op_symbol != 0)) 569 return 0; 570 num = operand->exp.X_add_number & 0xffffffff; 571 switch (size) 572 { 573 case L_2: 574 return (num & ~3) == 0; 575 case L_3: 576 return (num & ~7) == 0; 577 case L_3NZ: 578 return num >= 1 && num < 8; 579 case L_4: 580 return (num & ~15) == 0; 581 case L_5: 582 return num >= 1 && num < 32; 583 case L_8: 584 num = (num ^ 0x80000000) - 0x80000000; 585 return (num & ~0xFF) == 0 || (num | 0x7F) == ~0; 586 case L_8U: 587 return (num & ~0xFF) == 0; 588 case L_16: 589 num = (num ^ 0x80000000) - 0x80000000; 590 return (num & ~0xFFFF) == 0 || (num | 0x7FFF) == ~0; 591 case L_16U: 592 return (num & ~0xFFFF) == 0; 593 case L_32: 594 return 1; 595 default: 596 abort (); 597 } 598 } 599 600 static void 601 get_operand (char **ptr, struct h8_op *op, int direction) 602 { 603 char *src = *ptr; 604 op_type mode; 605 unsigned int num; 606 unsigned int len; 607 608 op->mode = 0; 609 610 /* Check for '(' and ')' for instructions ldm and stm. */ 611 if (src[0] == '(' && src[8] == ')') 612 ++ src; 613 614 /* Gross. Gross. ldm and stm have a format not easily handled 615 by get_operand. We deal with it explicitly here. */ 616 if (TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' && 617 ISDIGIT (src[2]) && src[3] == '-' && 618 TOLOWER (src[4]) == 'e' && TOLOWER (src[5]) == 'r' && ISDIGIT (src[6])) 619 { 620 int low, high; 621 622 low = src[2] - '0'; 623 high = src[6] - '0'; 624 625 /* Check register pair's validity as per tech note TN-H8*-193A/E 626 from Renesas for H8S and H8SX hardware manual. */ 627 if ( !(low == 0 && (high == 1 || high == 2 || high == 3)) 628 && !(low == 1 && (high == 2 || high == 3 || high == 4) && SXmode) 629 && !(low == 2 && (high == 3 || ((high == 4 || high == 5) && SXmode))) 630 && !(low == 3 && (high == 4 || high == 5 || high == 6) && SXmode) 631 && !(low == 4 && (high == 5 || high == 6)) 632 && !(low == 4 && high == 7 && SXmode) 633 && !(low == 5 && (high == 6 || high == 7) && SXmode) 634 && !(low == 6 && high == 7 && SXmode)) 635 as_bad (_("Invalid register list for ldm/stm\n")); 636 637 /* Even sicker. We encode two registers into op->reg. One 638 for the low register to save, the other for the high 639 register to save; we also set the high bit in op->reg 640 so we know this is "very special". */ 641 op->reg = 0x80000000 | (high << 8) | low; 642 op->mode = REG; 643 if (src[7] == ')') 644 *ptr = src + 8; 645 else 646 *ptr = src + 7; 647 return; 648 } 649 650 len = parse_reg (src, &op->mode, &op->reg, direction); 651 if (len) 652 { 653 src += len; 654 if (*src == '.') 655 { 656 int size = op->mode & SIZE; 657 switch (src[1]) 658 { 659 case 'l': case 'L': 660 if (size != L_32) 661 as_warn (_("mismatch between register and suffix")); 662 op->mode = (op->mode & ~MODE) | LOWREG; 663 break; 664 case 'w': case 'W': 665 if (size != L_32 && size != L_16) 666 as_warn (_("mismatch between register and suffix")); 667 op->mode = (op->mode & ~MODE) | LOWREG; 668 op->mode = (op->mode & ~SIZE) | L_16; 669 break; 670 case 'b': case 'B': 671 op->mode = (op->mode & ~MODE) | LOWREG; 672 if (size != L_32 && size != L_8) 673 as_warn (_("mismatch between register and suffix")); 674 op->mode = (op->mode & ~MODE) | LOWREG; 675 op->mode = (op->mode & ~SIZE) | L_8; 676 break; 677 default: 678 as_warn (_("invalid suffix after register.")); 679 break; 680 } 681 src += 2; 682 } 683 *ptr = src; 684 return; 685 } 686 687 if (*src == '@') 688 { 689 src++; 690 if (*src == '@') 691 { 692 *ptr = parse_exp (src + 1, op); 693 if (op->exp.X_add_number >= 0x100) 694 { 695 int divisor = 1; 696 697 op->mode = VECIND; 698 /* FIXME : 2? or 4? */ 699 if (op->exp.X_add_number >= 0x400) 700 as_bad (_("address too high for vector table jmp/jsr")); 701 else if (op->exp.X_add_number >= 0x200) 702 divisor = 4; 703 else 704 divisor = 2; 705 706 op->exp.X_add_number = op->exp.X_add_number / divisor - 0x80; 707 } 708 else 709 op->mode = MEMIND; 710 return; 711 } 712 713 if (*src == '-' || *src == '+') 714 { 715 len = parse_reg (src + 1, &mode, &num, direction); 716 if (len == 0) 717 { 718 /* Oops, not a reg after all, must be ordinary exp. */ 719 op->mode = ABS | direction; 720 *ptr = parse_exp (src, op); 721 return; 722 } 723 724 if (((mode & SIZE) != PSIZE) 725 /* For Normal mode accept 16 bit and 32 bit pointer registers. */ 726 && (!Nmode || ((mode & SIZE) != L_32))) 727 as_bad (_("Wrong size pointer register for architecture.")); 728 729 op->mode = src[0] == '-' ? RDPREDEC : RDPREINC; 730 op->reg = num; 731 *ptr = src + 1 + len; 732 return; 733 } 734 if (*src == '(') 735 { 736 src++; 737 738 /* See if this is @(ERn.x, PC). */ 739 len = parse_reg (src, &mode, &op->reg, direction); 740 if (len != 0 && (mode & MODE) == REG && src[len] == '.') 741 { 742 switch (TOLOWER (src[len + 1])) 743 { 744 case 'b': 745 mode = PCIDXB | direction; 746 break; 747 case 'w': 748 mode = PCIDXW | direction; 749 break; 750 case 'l': 751 mode = PCIDXL | direction; 752 break; 753 default: 754 mode = 0; 755 break; 756 } 757 if (mode 758 && src[len + 2] == ',' 759 && TOLOWER (src[len + 3]) != 'p' 760 && TOLOWER (src[len + 4]) != 'c' 761 && src[len + 5] != ')') 762 { 763 *ptr = src + len + 6; 764 op->mode |= mode; 765 return; 766 } 767 /* Fall through into disp case - the grammar is somewhat 768 ambiguous, so we should try whether it's a DISP operand 769 after all ("ER3.L" might be a poorly named label...). */ 770 } 771 772 /* Disp. */ 773 774 /* Start off assuming a 16 bit offset. */ 775 776 src = parse_exp (src, op); 777 if (*src == ')') 778 { 779 op->mode |= ABS | direction; 780 *ptr = src + 1; 781 return; 782 } 783 784 if (*src != ',') 785 { 786 as_bad (_("expected @(exp, reg16)")); 787 return; 788 } 789 src++; 790 791 len = parse_reg (src, &mode, &op->reg, direction); 792 if (len == 0 || (mode & MODE) != REG) 793 { 794 as_bad (_("expected @(exp, reg16)")); 795 return; 796 } 797 src += len; 798 if (src[0] == '.') 799 { 800 switch (TOLOWER (src[1])) 801 { 802 case 'b': 803 op->mode |= INDEXB | direction; 804 break; 805 case 'w': 806 op->mode |= INDEXW | direction; 807 break; 808 case 'l': 809 op->mode |= INDEXL | direction; 810 break; 811 default: 812 as_bad (_("expected .L, .W or .B for register in indexed addressing mode")); 813 } 814 src += 2; 815 op->reg &= 7; 816 } 817 else 818 op->mode |= DISP | direction; 819 src = skip_colonthing (src, &op->mode); 820 821 if (*src != ')') 822 { 823 as_bad (_("expected @(exp, reg16)")); 824 return; 825 } 826 *ptr = src + 1; 827 return; 828 } 829 len = parse_reg (src, &mode, &num, direction); 830 831 if (len) 832 { 833 src += len; 834 if (*src == '+' || *src == '-') 835 { 836 if (((mode & SIZE) != PSIZE) 837 /* For Normal mode accept 16 bit and 32 bit pointer registers. */ 838 && (!Nmode || ((mode & SIZE) != L_32))) 839 as_bad (_("Wrong size pointer register for architecture.")); 840 op->mode = *src == '+' ? RSPOSTINC : RSPOSTDEC; 841 op->reg = num; 842 src++; 843 *ptr = src; 844 return; 845 } 846 if (((mode & SIZE) != PSIZE) 847 /* For Normal mode accept 16 bit and 32 bit pointer registers. */ 848 && (!Nmode || ((mode & SIZE) != L_32))) 849 as_bad (_("Wrong size pointer register for architecture.")); 850 851 op->mode = direction | IND | PSIZE; 852 op->reg = num; 853 *ptr = src; 854 855 return; 856 } 857 else 858 { 859 /* must be a symbol */ 860 861 op->mode = ABS | direction; 862 *ptr = parse_exp (src, op); 863 return; 864 } 865 } 866 867 if (*src == '#') 868 { 869 op->mode = IMM; 870 *ptr = parse_exp (src + 1, op); 871 return; 872 } 873 else if (startswith (src, "mach") || 874 startswith (src, "macl") || 875 startswith (src, "MACH") || 876 startswith (src, "MACL")) 877 { 878 op->reg = TOLOWER (src[3]) == 'l'; 879 op->mode = MACREG; 880 *ptr = src + 4; 881 return; 882 } 883 else 884 { 885 op->mode = PCREL; 886 *ptr = parse_exp (src, op); 887 } 888 } 889 890 static char * 891 get_operands (unsigned int noperands, char *op_end, struct h8_op *operand) 892 { 893 char *ptr = op_end; 894 895 switch (noperands) 896 { 897 case 0: 898 break; 899 900 case 1: 901 ptr++; 902 get_operand (&ptr, operand + 0, SRC); 903 if (*ptr == ',') 904 { 905 ptr++; 906 get_operand (&ptr, operand + 1, DST); 907 } 908 break; 909 910 case 2: 911 ptr++; 912 get_operand (&ptr, operand + 0, SRC); 913 if (*ptr == ',') 914 ptr++; 915 get_operand (&ptr, operand + 1, DST); 916 break; 917 918 case 3: 919 ptr++; 920 get_operand (&ptr, operand + 0, SRC); 921 if (*ptr == ',') 922 ptr++; 923 get_operand (&ptr, operand + 1, DST); 924 if (*ptr == ',') 925 ptr++; 926 get_operand (&ptr, operand + 2, OP3); 927 break; 928 929 default: 930 abort (); 931 } 932 933 return ptr; 934 } 935 936 /* MOVA has special requirements. Rather than adding twice the amount of 937 addressing modes, we simply special case it a bit. */ 938 static void 939 get_mova_operands (char *op_end, struct h8_op *operand) 940 { 941 char *ptr = op_end; 942 943 if (ptr[1] != '@' || ptr[2] != '(') 944 goto error; 945 ptr += 3; 946 operand[0].mode = 0; 947 ptr = parse_exp (ptr, &operand[0]); 948 949 if (*ptr !=',') 950 goto error; 951 ptr++; 952 get_operand (&ptr, operand + 1, DST); 953 954 if (*ptr =='.') 955 { 956 ptr++; 957 switch (*ptr++) 958 { 959 case 'b': case 'B': 960 operand[0].mode = (operand[0].mode & ~MODE) | INDEXB; 961 break; 962 case 'w': case 'W': 963 operand[0].mode = (operand[0].mode & ~MODE) | INDEXW; 964 break; 965 case 'l': case 'L': 966 operand[0].mode = (operand[0].mode & ~MODE) | INDEXL; 967 break; 968 default: 969 goto error; 970 } 971 } 972 else if ((operand[1].mode & MODE) == LOWREG) 973 { 974 switch (operand[1].mode & SIZE) 975 { 976 case L_8: 977 operand[0].mode = (operand[0].mode & ~MODE) | INDEXB; 978 break; 979 case L_16: 980 operand[0].mode = (operand[0].mode & ~MODE) | INDEXW; 981 break; 982 case L_32: 983 operand[0].mode = (operand[0].mode & ~MODE) | INDEXL; 984 break; 985 default: 986 goto error; 987 } 988 } 989 else 990 goto error; 991 992 if (*ptr++ != ')' || *ptr++ != ',') 993 goto error; 994 get_operand (&ptr, operand + 2, OP3); 995 /* See if we can use the short form of MOVA. */ 996 if (((operand[1].mode & MODE) == REG || (operand[1].mode & MODE) == LOWREG) 997 && (operand[2].mode & MODE) == REG 998 && (operand[1].reg & 7) == (operand[2].reg & 7)) 999 { 1000 operand[1].mode = operand[2].mode = 0; 1001 operand[0].reg = operand[2].reg & 7; 1002 } 1003 return; 1004 1005 error: 1006 as_bad (_("expected valid addressing mode for mova: \"@(disp, ea.sz),ERn\"")); 1007 } 1008 1009 static void 1010 get_rtsl_operands (char *ptr, struct h8_op *operand) 1011 { 1012 int mode, len, type = 0; 1013 unsigned int num, num2; 1014 1015 ptr++; 1016 if (*ptr == '(') 1017 { 1018 ptr++; 1019 type = 1; 1020 } 1021 len = parse_reg (ptr, &mode, &num, SRC); 1022 if (len == 0 || (mode & MODE) != REG) 1023 { 1024 as_bad (_("expected register")); 1025 return; 1026 } 1027 ptr += len; 1028 if (*ptr == '-') 1029 { 1030 len = parse_reg (++ptr, &mode, &num2, SRC); 1031 if (len == 0 || (mode & MODE) != REG) 1032 { 1033 as_bad (_("expected register")); 1034 return; 1035 } 1036 ptr += len; 1037 /* CONST_xxx are used as placeholders in the opcode table. */ 1038 num = num2 - num; 1039 if (num > 3) 1040 { 1041 as_bad (_("invalid register list")); 1042 return; 1043 } 1044 } 1045 else 1046 num2 = num, num = 0; 1047 if (type == 1 && *ptr++ != ')') 1048 { 1049 as_bad (_("expected closing paren")); 1050 return; 1051 } 1052 operand[0].mode = RS32; 1053 operand[1].mode = RD32; 1054 operand[0].reg = num; 1055 operand[1].reg = num2; 1056 } 1057 1058 /* Passed a pointer to a list of opcodes which use different 1059 addressing modes, return the opcode which matches the opcodes 1060 provided. */ 1061 1062 static const struct h8_instruction * 1063 get_specific (const struct h8_instruction *instruction, 1064 struct h8_op *operands, int size) 1065 { 1066 const struct h8_instruction *this_try = instruction; 1067 const struct h8_instruction *found_other = 0, *found_mismatched = 0; 1068 int found = 0; 1069 int this_index = instruction->idx; 1070 int noperands = 0; 1071 1072 /* There's only one ldm/stm and it's easier to just 1073 get out quick for them. */ 1074 if (OP_KIND (instruction->opcode->how) == O_LDM 1075 || OP_KIND (instruction->opcode->how) == O_STM) 1076 return this_try; 1077 1078 while (noperands < 3 && operands[noperands].mode != 0) 1079 noperands++; 1080 1081 while (this_index == instruction->idx && !found) 1082 { 1083 int this_size; 1084 1085 found = 1; 1086 this_try = instruction++; 1087 this_size = this_try->opcode->how & SN; 1088 1089 if (this_try->noperands != noperands) 1090 found = 0; 1091 else if (this_try->noperands > 0) 1092 { 1093 int i; 1094 1095 for (i = 0; i < this_try->noperands && found; i++) 1096 { 1097 op_type op = this_try->opcode->args.nib[i]; 1098 int op_mode = op & MODE; 1099 int op_size = op & SIZE; 1100 int x = operands[i].mode; 1101 int x_mode = x & MODE; 1102 int x_size = x & SIZE; 1103 1104 if (op_mode == LOWREG && (x_mode == REG || x_mode == LOWREG)) 1105 { 1106 if ((x_size == L_8 && (operands[i].reg & 8) == 0) 1107 || (x_size == L_16 && (operands[i].reg & 8) == 8)) 1108 as_warn (_("can't use high part of register in operand %d"), i); 1109 1110 if (x_size != op_size) 1111 found = 0; 1112 } 1113 else if (op_mode == REG) 1114 { 1115 if (x_mode == LOWREG) 1116 x_mode = REG; 1117 if (x_mode != REG) 1118 found = 0; 1119 1120 if (x_size == L_P) 1121 x_size = (Hmode ? L_32 : L_16); 1122 if (op_size == L_P) 1123 op_size = (Hmode ? L_32 : L_16); 1124 1125 /* The size of the reg is v important. */ 1126 if (op_size != x_size) 1127 found = 0; 1128 } 1129 else if (op_mode & CTRL) /* control register */ 1130 { 1131 if (!(x_mode & CTRL)) 1132 found = 0; 1133 1134 switch (x_mode) 1135 { 1136 case CCR: 1137 if (op_mode != CCR && 1138 op_mode != CCR_EXR && 1139 op_mode != CC_EX_VB_SB) 1140 found = 0; 1141 break; 1142 case EXR: 1143 if (op_mode != EXR && 1144 op_mode != CCR_EXR && 1145 op_mode != CC_EX_VB_SB) 1146 found = 0; 1147 break; 1148 case MACH: 1149 if (op_mode != MACH && 1150 op_mode != MACREG) 1151 found = 0; 1152 break; 1153 case MACL: 1154 if (op_mode != MACL && 1155 op_mode != MACREG) 1156 found = 0; 1157 break; 1158 case VBR: 1159 if (op_mode != VBR && 1160 op_mode != VBR_SBR && 1161 op_mode != CC_EX_VB_SB) 1162 found = 0; 1163 break; 1164 case SBR: 1165 if (op_mode != SBR && 1166 op_mode != VBR_SBR && 1167 op_mode != CC_EX_VB_SB) 1168 found = 0; 1169 break; 1170 } 1171 } 1172 else if ((op & ABSJMP) && (x_mode == ABS || x_mode == PCREL)) 1173 { 1174 operands[i].mode &= ~MODE; 1175 operands[i].mode |= ABSJMP; 1176 /* But it may not be 24 bits long. */ 1177 if (x_mode == ABS && !Hmode) 1178 { 1179 operands[i].mode &= ~SIZE; 1180 operands[i].mode |= L_16; 1181 } 1182 if ((operands[i].mode & SIZE) == L_32 1183 && (op_mode & SIZE) != L_32) 1184 found = 0; 1185 } 1186 else if (x_mode == IMM && op_mode != IMM) 1187 { 1188 offsetT num = operands[i].exp.X_add_number & 0xffffffff; 1189 if (op_mode == KBIT || op_mode == DBIT) 1190 /* This is ok if the immediate value is sensible. */; 1191 else if (op_mode == CONST_2) 1192 found = num == 2; 1193 else if (op_mode == CONST_4) 1194 found = num == 4; 1195 else if (op_mode == CONST_8) 1196 found = num == 8; 1197 else if (op_mode == CONST_16) 1198 found = num == 16; 1199 else 1200 found = 0; 1201 } 1202 else if (op_mode == PCREL && op_mode == x_mode) 1203 { 1204 /* movsd, bsr/bc and bsr/bs only come in PCREL16 flavour: 1205 If x_size is L_8, promote it. */ 1206 if (OP_KIND (this_try->opcode->how) == O_MOVSD 1207 || OP_KIND (this_try->opcode->how) == O_BSRBC 1208 || OP_KIND (this_try->opcode->how) == O_BSRBS) 1209 if (x_size == L_8) 1210 x_size = L_16; 1211 1212 /* The size of the displacement is important. */ 1213 if (op_size != x_size) 1214 found = 0; 1215 } 1216 else if ((op_mode == DISP || op_mode == IMM || op_mode == ABS 1217 || op_mode == INDEXB || op_mode == INDEXW 1218 || op_mode == INDEXL) 1219 && op_mode == x_mode) 1220 { 1221 /* Promote a L_24 to L_32 if it makes us match. */ 1222 if (x_size == L_24 && op_size == L_32) 1223 { 1224 x &= ~SIZE; 1225 x |= x_size = L_32; 1226 } 1227 1228 if (((x_size == L_16 && op_size == L_16U) 1229 || (x_size == L_8 && op_size == L_8U) 1230 || (x_size == L_3 && op_size == L_3NZ)) 1231 /* We're deliberately more permissive for ABS modes. */ 1232 && (op_mode == ABS 1233 || constant_fits_size_p (operands + i, op_size, 1234 op & NO_SYMBOLS))) 1235 x_size = op_size; 1236 1237 if (x_size != 0 && op_size != x_size) 1238 found = 0; 1239 else if (x_size == 0 1240 && ! constant_fits_size_p (operands + i, op_size, 1241 op & NO_SYMBOLS)) 1242 found = 0; 1243 } 1244 else if (op_mode != x_mode) 1245 { 1246 found = 0; 1247 } 1248 } 1249 } 1250 if (found) 1251 { 1252 if ((this_try->opcode->available == AV_H8SX && ! SXmode) 1253 || (this_try->opcode->available == AV_H8S && ! Smode) 1254 || (this_try->opcode->available == AV_H8H && ! Hmode)) 1255 found = 0, found_other = this_try; 1256 else if (this_size != size && (this_size != SN && size != SN)) 1257 found_mismatched = this_try, found = 0; 1258 1259 } 1260 } 1261 if (found) 1262 return this_try; 1263 if (found_other) 1264 { 1265 as_warn (_("Opcode `%s' with these operand types not available in %s mode"), 1266 found_other->opcode->name, 1267 (! Hmode && ! Smode ? "H8/300" 1268 : SXmode ? "H8sx" 1269 : Smode ? "H8/300S" 1270 : "H8/300H")); 1271 } 1272 else if (found_mismatched) 1273 { 1274 as_warn (_("mismatch between opcode size and operand size")); 1275 return found_mismatched; 1276 } 1277 return 0; 1278 } 1279 1280 static void 1281 check_operand (struct h8_op *operand, unsigned int width, const char *string) 1282 { 1283 if (operand->exp.X_add_symbol == 0 1284 && operand->exp.X_op_symbol == 0) 1285 { 1286 /* No symbol involved, let's look at offset, it's dangerous if 1287 any of the high bits are not 0 or ff's, find out by oring or 1288 anding with the width and seeing if the answer is 0 or all 1289 fs. */ 1290 1291 if (! constant_fits_width_p (operand, width)) 1292 { 1293 if (width == 255 1294 && (operand->exp.X_add_number & 0xff00) == 0xff00) 1295 { 1296 /* Just ignore this one - which happens when trying to 1297 fit a 16 bit address truncated into an 8 bit address 1298 of something like bset. */ 1299 } 1300 else if (strcmp (string, "@") == 0 1301 && width == 0xffff 1302 && (operand->exp.X_add_number & 0xff8000) == 0xff8000) 1303 { 1304 /* Just ignore this one - which happens when trying to 1305 fit a 24 bit address truncated into a 16 bit address 1306 of something like mov.w. */ 1307 } 1308 else 1309 { 1310 as_warn (_("operand %s0x%lx out of range."), string, 1311 (unsigned long) operand->exp.X_add_number); 1312 } 1313 } 1314 } 1315 } 1316 1317 /* RELAXMODE has one of 3 values: 1318 1319 0 Output a "normal" reloc, no relaxing possible for this insn/reloc 1320 1321 1 Output a relaxable 24bit absolute mov.w address relocation 1322 (may relax into a 16bit absolute address). 1323 1324 2 Output a relaxable 16/24 absolute mov.b address relocation 1325 (may relax into an 8bit absolute address). */ 1326 1327 static void 1328 do_a_fix_imm (int offset, int nibble, struct h8_op *operand, int relaxmode, const struct h8_instruction *this_try) 1329 { 1330 int idx; 1331 int size; 1332 int where; 1333 char *bytes = frag_now->fr_literal + offset; 1334 1335 const char *t = ((operand->mode & MODE) == IMM) ? "#" : "@"; 1336 1337 if (operand->exp.X_add_symbol == 0) 1338 { 1339 switch (operand->mode & SIZE) 1340 { 1341 case L_2: 1342 check_operand (operand, 0x3, t); 1343 bytes[0] |= (operand->exp.X_add_number & 3) << (nibble ? 0 : 4); 1344 break; 1345 case L_3: 1346 case L_3NZ: 1347 check_operand (operand, 0x7, t); 1348 bytes[0] |= (operand->exp.X_add_number & 7) << (nibble ? 0 : 4); 1349 break; 1350 case L_4: 1351 check_operand (operand, 0xF, t); 1352 bytes[0] |= (operand->exp.X_add_number & 15) << (nibble ? 0 : 4); 1353 break; 1354 case L_5: 1355 check_operand (operand, 0x1F, t); 1356 bytes[0] |= operand->exp.X_add_number & 31; 1357 break; 1358 case L_8: 1359 case L_8U: 1360 check_operand (operand, 0xff, t); 1361 bytes[0] |= operand->exp.X_add_number; 1362 break; 1363 case L_16: 1364 case L_16U: 1365 check_operand (operand, 0xffff, t); 1366 bytes[0] |= operand->exp.X_add_number >> 8; 1367 bytes[1] |= operand->exp.X_add_number >> 0; 1368 /* MOVA needs both relocs to relax the second operand properly. */ 1369 if (relaxmode != 0 1370 && (OP_KIND(this_try->opcode->how) == O_MOVAB 1371 || OP_KIND(this_try->opcode->how) == O_MOVAW 1372 || OP_KIND(this_try->opcode->how) == O_MOVAL)) 1373 { 1374 idx = BFD_RELOC_16; 1375 fix_new_exp (frag_now, offset, 2, &operand->exp, 0, idx); 1376 } 1377 break; 1378 case L_24: 1379 check_operand (operand, 0xffffff, t); 1380 bytes[0] |= operand->exp.X_add_number >> 16; 1381 bytes[1] |= operand->exp.X_add_number >> 8; 1382 bytes[2] |= operand->exp.X_add_number >> 0; 1383 break; 1384 1385 case L_32: 1386 /* This should be done with bfd. */ 1387 bytes[0] |= operand->exp.X_add_number >> 24; 1388 bytes[1] |= operand->exp.X_add_number >> 16; 1389 bytes[2] |= operand->exp.X_add_number >> 8; 1390 bytes[3] |= operand->exp.X_add_number >> 0; 1391 if (relaxmode != 0) 1392 { 1393 if ((operand->mode & MODE) == DISP && relaxmode == 1) 1394 idx = BFD_RELOC_H8_DISP32A16; 1395 else 1396 idx = (relaxmode == 2) ? R_MOV24B1 : R_MOVL1; 1397 fix_new_exp (frag_now, offset, 4, &operand->exp, 0, idx); 1398 } 1399 break; 1400 } 1401 } 1402 else 1403 { 1404 switch (operand->mode & SIZE) 1405 { 1406 case L_24: 1407 case L_32: 1408 size = 4; 1409 where = (operand->mode & SIZE) == L_24 ? -1 : 0; 1410 if ((operand->mode & MODE) == DISP && relaxmode == 1) 1411 idx = BFD_RELOC_H8_DISP32A16; 1412 else if (relaxmode == 2) 1413 idx = R_MOV24B1; 1414 else if (relaxmode == 1) 1415 idx = R_MOVL1; 1416 else 1417 idx = R_RELLONG; 1418 break; 1419 default: 1420 as_bad (_("Can't work out size of operand.\n")); 1421 /* Fall through. */ 1422 case L_16: 1423 case L_16U: 1424 size = 2; 1425 where = 0; 1426 if (relaxmode == 2) 1427 idx = R_MOV16B1; 1428 else 1429 idx = R_RELWORD; 1430 operand->exp.X_add_number = 1431 ((operand->exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; 1432 operand->exp.X_add_number |= (bytes[0] << 8) | bytes[1]; 1433 break; 1434 case L_8: 1435 size = 1; 1436 where = 0; 1437 idx = R_RELBYTE; 1438 operand->exp.X_add_number = 1439 ((operand->exp.X_add_number & 0xff) ^ 0x80) - 0x80; 1440 operand->exp.X_add_number |= bytes[0]; 1441 } 1442 1443 fix_new_exp (frag_now, 1444 offset + where, 1445 size, 1446 &operand->exp, 1447 0, 1448 idx); 1449 } 1450 } 1451 1452 /* Now we know what sort of opcodes it is, let's build the bytes. */ 1453 1454 static void 1455 build_bytes (const struct h8_instruction *this_try, struct h8_op *operand) 1456 { 1457 int i; 1458 char *output = frag_more (this_try->length); 1459 const op_type *nibble_ptr = this_try->opcode->data.nib; 1460 op_type c; 1461 unsigned int nibble_count = 0; 1462 int op_at[3]; 1463 int nib = 0; 1464 int movb = 0; 1465 char asnibbles[100]; 1466 char *p = asnibbles; 1467 int high, low; 1468 1469 if (!Hmode && this_try->opcode->available != AV_H8) 1470 as_warn (_("Opcode `%s' with these operand types not available in H8/300 mode"), 1471 this_try->opcode->name); 1472 else if (!Smode 1473 && this_try->opcode->available != AV_H8 1474 && this_try->opcode->available != AV_H8H) 1475 as_warn (_("Opcode `%s' with these operand types not available in H8/300H mode"), 1476 this_try->opcode->name); 1477 else if (!SXmode 1478 && this_try->opcode->available != AV_H8 1479 && this_try->opcode->available != AV_H8H 1480 && this_try->opcode->available != AV_H8S) 1481 as_warn (_("Opcode `%s' with these operand types not available in H8/300S mode"), 1482 this_try->opcode->name); 1483 1484 while (*nibble_ptr != (op_type) E) 1485 { 1486 int d; 1487 1488 nib = 0; 1489 c = *nibble_ptr++; 1490 1491 d = (c & OP3) == OP3 ? 2 : (c & DST) == DST ? 1 : 0; 1492 1493 if (c < 16) 1494 nib = c; 1495 else 1496 { 1497 int c2 = c & MODE; 1498 1499 if (c2 == REG || c2 == LOWREG 1500 || c2 == IND || c2 == PREINC || c2 == PREDEC 1501 || c2 == POSTINC || c2 == POSTDEC) 1502 { 1503 nib = operand[d].reg; 1504 if (c2 == LOWREG) 1505 nib &= 7; 1506 } 1507 1508 else if (c & CTRL) /* Control reg operand. */ 1509 nib = operand[d].reg; 1510 1511 else if ((c & DISPREG) == (DISPREG)) 1512 { 1513 nib = operand[d].reg; 1514 } 1515 else if (c2 == ABS) 1516 { 1517 operand[d].mode = c; 1518 op_at[d] = nibble_count; 1519 nib = 0; 1520 } 1521 else if (c2 == IMM || c2 == PCREL || c2 == ABS 1522 || (c & ABSJMP) || c2 == DISP) 1523 { 1524 operand[d].mode = c; 1525 op_at[d] = nibble_count; 1526 nib = 0; 1527 } 1528 else if ((c & IGNORE) || (c & DATA)) 1529 nib = 0; 1530 1531 else if (c2 == DBIT) 1532 { 1533 switch (operand[0].exp.X_add_number) 1534 { 1535 case 1: 1536 nib = c; 1537 break; 1538 case 2: 1539 nib = 0x8 | c; 1540 break; 1541 default: 1542 as_bad (_("Need #1 or #2 here")); 1543 } 1544 } 1545 else if (c2 == KBIT) 1546 { 1547 switch (operand[0].exp.X_add_number) 1548 { 1549 case 1: 1550 nib = 0; 1551 break; 1552 case 2: 1553 nib = 8; 1554 break; 1555 case 4: 1556 if (!Hmode) 1557 as_warn (_("#4 not valid on H8/300.")); 1558 nib = 9; 1559 break; 1560 1561 default: 1562 as_bad (_("Need #1 or #2 here")); 1563 break; 1564 } 1565 /* Stop it making a fix. */ 1566 operand[0].mode = 0; 1567 } 1568 1569 if (c & MEMRELAX) 1570 operand[d].mode |= MEMRELAX; 1571 1572 if (c & B31) 1573 nib |= 0x8; 1574 1575 if (c & B21) 1576 nib |= 0x4; 1577 1578 if (c & B11) 1579 nib |= 0x2; 1580 1581 if (c & B01) 1582 nib |= 0x1; 1583 1584 if (c2 == MACREG) 1585 { 1586 if (operand[0].mode == MACREG) 1587 /* stmac has mac[hl] as the first operand. */ 1588 nib = 2 + operand[0].reg; 1589 else 1590 /* ldmac has mac[hl] as the second operand. */ 1591 nib = 2 + operand[1].reg; 1592 } 1593 } 1594 nibble_count++; 1595 1596 *p++ = nib; 1597 } 1598 1599 /* Disgusting. Why, oh why didn't someone ask us for advice 1600 on the assembler format. */ 1601 if (OP_KIND (this_try->opcode->how) == O_LDM) 1602 { 1603 high = (operand[1].reg >> 8) & 0xf; 1604 low = (operand[1].reg) & 0xf; 1605 asnibbles[2] = high - low; 1606 asnibbles[7] = high; 1607 } 1608 else if (OP_KIND (this_try->opcode->how) == O_STM) 1609 { 1610 high = (operand[0].reg >> 8) & 0xf; 1611 low = (operand[0].reg) & 0xf; 1612 asnibbles[2] = high - low; 1613 asnibbles[7] = low; 1614 } 1615 1616 for (i = 0; i < this_try->length; i++) 1617 output[i] = (asnibbles[i * 2] << 4) | asnibbles[i * 2 + 1]; 1618 1619 /* Note if this is a mov.b or a bit manipulation instruction 1620 there is a special relaxation which only applies. */ 1621 if ( this_try->opcode->how == O (O_MOV, SB) 1622 || this_try->opcode->how == O (O_BCLR, SB) 1623 || this_try->opcode->how == O (O_BAND, SB) 1624 || this_try->opcode->how == O (O_BIAND, SB) 1625 || this_try->opcode->how == O (O_BILD, SB) 1626 || this_try->opcode->how == O (O_BIOR, SB) 1627 || this_try->opcode->how == O (O_BIST, SB) 1628 || this_try->opcode->how == O (O_BIXOR, SB) 1629 || this_try->opcode->how == O (O_BLD, SB) 1630 || this_try->opcode->how == O (O_BNOT, SB) 1631 || this_try->opcode->how == O (O_BOR, SB) 1632 || this_try->opcode->how == O (O_BSET, SB) 1633 || this_try->opcode->how == O (O_BST, SB) 1634 || this_try->opcode->how == O (O_BTST, SB) 1635 || this_try->opcode->how == O (O_BXOR, SB)) 1636 movb = 1; 1637 1638 /* Output any fixes. */ 1639 for (i = 0; i < this_try->noperands; i++) 1640 { 1641 int x = operand[i].mode; 1642 int x_mode = x & MODE; 1643 1644 if (x_mode == IMM || x_mode == DISP) 1645 do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2, 1646 op_at[i] & 1, operand + i, (x & MEMRELAX) != 0, 1647 this_try); 1648 else if (x_mode == ABS) 1649 do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2, 1650 op_at[i] & 1, operand + i, 1651 (x & MEMRELAX) ? movb + 1 : 0, 1652 this_try); 1653 1654 else if (x_mode == PCREL) 1655 { 1656 int size16 = (x & SIZE) == L_16; 1657 int size = size16 ? 2 : 1; 1658 int type = size16 ? R_PCRWORD : R_PCRBYTE; 1659 fixS *fixP; 1660 1661 check_operand (operand + i, size16 ? 0x7fff : 0x7f, "@"); 1662 1663 if (operand[i].exp.X_add_number & 1) 1664 as_warn (_("branch operand has odd offset (%lx)\n"), 1665 (unsigned long) operand->exp.X_add_number); 1666 if (size16) 1667 { 1668 operand[i].exp.X_add_number = 1669 ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; 1670 } 1671 else 1672 { 1673 operand[i].exp.X_add_number = 1674 ((operand[i].exp.X_add_number & 0xff) ^ 0x80) - 0x80; 1675 } 1676 1677 /* For BRA/S. */ 1678 if (! size16) 1679 operand[i].exp.X_add_number |= output[op_at[i] / 2]; 1680 1681 fixP = fix_new_exp (frag_now, 1682 output - frag_now->fr_literal + op_at[i] / 2, 1683 size, 1684 &operand[i].exp, 1685 1, 1686 type); 1687 fixP->fx_signed = 1; 1688 } 1689 else if (x_mode == MEMIND) 1690 { 1691 check_operand (operand + i, 0xff, "@@"); 1692 fix_new_exp (frag_now, 1693 output - frag_now->fr_literal + 1, 1694 1, 1695 &operand[i].exp, 1696 0, 1697 R_MEM_INDIRECT); 1698 } 1699 else if (x_mode == VECIND) 1700 { 1701 check_operand (operand + i, 0x7f, "@@"); 1702 /* FIXME: approximating the effect of "B31" here... 1703 This is very hackish, and ought to be done a better way. */ 1704 operand[i].exp.X_add_number |= 0x80; 1705 fix_new_exp (frag_now, 1706 output - frag_now->fr_literal + 1, 1707 1, 1708 &operand[i].exp, 1709 0, 1710 R_MEM_INDIRECT); 1711 } 1712 else if (x & ABSJMP) 1713 { 1714 int where = 0; 1715 bfd_reloc_code_real_type reloc_type = R_JMPL1; 1716 1717 /* To be compatible with the proposed H8 ELF format, we 1718 want the relocation's offset to point to the first byte 1719 that will be modified, not to the start of the instruction. */ 1720 1721 if ((operand->mode & SIZE) == L_32) 1722 { 1723 where = 2; 1724 reloc_type = R_RELLONG; 1725 } 1726 else 1727 where = 1; 1728 1729 /* This jmp may be a jump or a branch. */ 1730 1731 check_operand (operand + i, 1732 SXmode ? 0xffffffff : Hmode ? 0xffffff : 0xffff, 1733 "@"); 1734 1735 if (operand[i].exp.X_add_number & 1) 1736 as_warn (_("branch operand has odd offset (%lx)\n"), 1737 (unsigned long) operand->exp.X_add_number); 1738 1739 if (!Hmode) 1740 operand[i].exp.X_add_number = 1741 ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; 1742 fix_new_exp (frag_now, 1743 output - frag_now->fr_literal + where, 1744 4, 1745 &operand[i].exp, 1746 0, 1747 reloc_type); 1748 } 1749 } 1750 } 1751 1752 /* Try to give an intelligent error message for common and simple to 1753 detect errors. */ 1754 1755 static void 1756 clever_message (const struct h8_instruction *instruction, 1757 struct h8_op *operand) 1758 { 1759 /* Find out if there was more than one possible opcode. */ 1760 1761 if ((instruction + 1)->idx != instruction->idx) 1762 { 1763 int argn; 1764 1765 /* Only one opcode of this flavour, try to guess which operand 1766 didn't match. */ 1767 for (argn = 0; argn < instruction->noperands; argn++) 1768 { 1769 switch (instruction->opcode->args.nib[argn]) 1770 { 1771 case RD16: 1772 if (operand[argn].mode != RD16) 1773 { 1774 as_bad (_("destination operand must be 16 bit register")); 1775 return; 1776 1777 } 1778 break; 1779 1780 case RS8: 1781 if (operand[argn].mode != RS8) 1782 { 1783 as_bad (_("source operand must be 8 bit register")); 1784 return; 1785 } 1786 break; 1787 1788 case ABS16DST: 1789 if (operand[argn].mode != ABS16DST) 1790 { 1791 as_bad (_("destination operand must be 16bit absolute address")); 1792 return; 1793 } 1794 break; 1795 case RD8: 1796 if (operand[argn].mode != RD8) 1797 { 1798 as_bad (_("destination operand must be 8 bit register")); 1799 return; 1800 } 1801 break; 1802 1803 case ABS16SRC: 1804 if (operand[argn].mode != ABS16SRC) 1805 { 1806 as_bad (_("source operand must be 16bit absolute address")); 1807 return; 1808 } 1809 break; 1810 1811 } 1812 } 1813 } 1814 as_bad (_("invalid operands")); 1815 } 1816 1817 1818 /* If OPERAND is part of an address, adjust its size and value given 1819 that it addresses SIZE bytes. 1820 1821 This function decides how big non-immediate constants are when no 1822 size was explicitly given. It also scales down the assembly-level 1823 displacement in an @(d:2,ERn) operand. */ 1824 1825 static void 1826 fix_operand_size (struct h8_op *operand, int size) 1827 { 1828 if (SXmode && (operand->mode & MODE) == DISP) 1829 { 1830 /* If the user didn't specify an operand width, see if we 1831 can use @(d:2,ERn). */ 1832 if ((operand->mode & SIZE) == 0 1833 && operand->exp.X_add_symbol == 0 1834 && operand->exp.X_op_symbol == 0 1835 && (operand->exp.X_add_number == size 1836 || operand->exp.X_add_number == size * 2 1837 || operand->exp.X_add_number == size * 3)) 1838 operand->mode |= L_2; 1839 1840 /* Scale down the displacement in an @(d:2,ERn) operand. 1841 X_add_number then contains the desired field value. */ 1842 if ((operand->mode & SIZE) == L_2) 1843 { 1844 if (operand->exp.X_add_number % size != 0) 1845 as_warn (_("operand/size mis-match")); 1846 operand->exp.X_add_number /= size; 1847 } 1848 } 1849 1850 if ((operand->mode & SIZE) == 0) 1851 switch (operand->mode & MODE) 1852 { 1853 case DISP: 1854 case INDEXB: 1855 case INDEXW: 1856 case INDEXL: 1857 case ABS: 1858 /* Pick a 24-bit address unless we know that a 16-bit address 1859 is safe. get_specific() will relax L_24 into L_32 where 1860 necessary. */ 1861 if (Hmode 1862 && !Nmode 1863 && ((((addressT) operand->exp.X_add_number + 0x8000) 1864 & 0xffffffff) > 0xffff 1865 || operand->exp.X_add_symbol != 0 1866 || operand->exp.X_op_symbol != 0)) 1867 operand->mode |= L_24; 1868 else 1869 operand->mode |= L_16; 1870 break; 1871 1872 case PCREL: 1873 if ((((addressT) operand->exp.X_add_number + 0x80) 1874 & 0xffffffff) <= 0xff) 1875 { 1876 if (operand->exp.X_add_symbol != NULL) 1877 operand->mode |= bsize; 1878 else 1879 operand->mode |= L_8; 1880 } 1881 else 1882 operand->mode |= L_16; 1883 break; 1884 } 1885 } 1886 1887 1888 /* This is the guts of the machine-dependent assembler. STR points to 1889 a machine dependent instruction. This function is supposed to emit 1890 the frags/bytes it assembles. */ 1891 1892 void 1893 md_assemble (char *str) 1894 { 1895 char *op_start; 1896 char *op_end; 1897 struct h8_op operand[3]; 1898 const struct h8_instruction *instruction; 1899 const struct h8_instruction *prev_instruction; 1900 1901 char *dot = 0; 1902 char *slash = 0; 1903 char c; 1904 int size, i; 1905 1906 /* Drop leading whitespace. */ 1907 while (is_whitespace (*str)) 1908 str++; 1909 1910 /* Find the op code end. */ 1911 for (op_start = op_end = str; 1912 !is_end_of_stmt (*op_end) && !is_whitespace (*op_end); 1913 op_end++) 1914 { 1915 if (*op_end == '.') 1916 { 1917 dot = op_end + 1; 1918 *op_end = 0; 1919 op_end += 2; 1920 break; 1921 } 1922 else if (*op_end == '/' && ! slash) 1923 slash = op_end; 1924 } 1925 1926 if (op_end == op_start) 1927 { 1928 as_bad (_("can't find opcode ")); 1929 } 1930 c = *op_end; 1931 1932 *op_end = 0; 1933 1934 /* The assembler stops scanning the opcode at slashes, so it fails 1935 to make characters following them lower case. Fix them. */ 1936 if (slash) 1937 while (*++slash) 1938 *slash = TOLOWER (*slash); 1939 1940 instruction = str_hash_find (opcode_hash_control, op_start); 1941 1942 if (instruction == NULL) 1943 { 1944 as_bad (_("unknown opcode")); 1945 return; 1946 } 1947 1948 /* We used to set input_line_pointer to the result of get_operands, 1949 but that is wrong. Our caller assumes we don't change it. */ 1950 1951 operand[0].mode = 0; 1952 operand[1].mode = 0; 1953 operand[2].mode = 0; 1954 1955 if (OP_KIND (instruction->opcode->how) == O_MOVAB 1956 || OP_KIND (instruction->opcode->how) == O_MOVAW 1957 || OP_KIND (instruction->opcode->how) == O_MOVAL) 1958 get_mova_operands (op_end, operand); 1959 else if (OP_KIND (instruction->opcode->how) == O_RTEL 1960 || OP_KIND (instruction->opcode->how) == O_RTSL) 1961 get_rtsl_operands (op_end, operand); 1962 else 1963 get_operands (instruction->noperands, op_end, operand); 1964 1965 *op_end = c; 1966 prev_instruction = instruction; 1967 1968 /* Now we have operands from instruction. 1969 Let's check them out for ldm and stm. */ 1970 if (OP_KIND (instruction->opcode->how) == O_LDM) 1971 { 1972 /* The first operand must be @er7+, and the 1973 second operand must be a register pair. */ 1974 if ((operand[0].mode != RSINC) 1975 || (operand[0].reg != 7) 1976 || ((operand[1].reg & 0x80000000) == 0)) 1977 as_bad (_("invalid operand in ldm")); 1978 } 1979 else if (OP_KIND (instruction->opcode->how) == O_STM) 1980 { 1981 /* The first operand must be a register pair, 1982 and the second operand must be @-er7. */ 1983 if (((operand[0].reg & 0x80000000) == 0) 1984 || (operand[1].mode != RDDEC) 1985 || (operand[1].reg != 7)) 1986 as_bad (_("invalid operand in stm")); 1987 } 1988 1989 size = SN; 1990 if (dot) 1991 { 1992 switch (TOLOWER (*dot)) 1993 { 1994 case 'b': 1995 size = SB; 1996 break; 1997 1998 case 'w': 1999 size = SW; 2000 break; 2001 2002 case 'l': 2003 size = SL; 2004 break; 2005 } 2006 } 2007 if (OP_KIND (instruction->opcode->how) == O_MOVAB || 2008 OP_KIND (instruction->opcode->how) == O_MOVAW || 2009 OP_KIND (instruction->opcode->how) == O_MOVAL) 2010 { 2011 switch (operand[0].mode & MODE) 2012 { 2013 case INDEXB: 2014 default: 2015 fix_operand_size (&operand[1], 1); 2016 break; 2017 case INDEXW: 2018 fix_operand_size (&operand[1], 2); 2019 break; 2020 case INDEXL: 2021 fix_operand_size (&operand[1], 4); 2022 break; 2023 } 2024 } 2025 else 2026 { 2027 for (i = 0; i < 3 && operand[i].mode != 0; i++) 2028 switch (size) 2029 { 2030 case SN: 2031 case SB: 2032 default: 2033 fix_operand_size (&operand[i], 1); 2034 break; 2035 case SW: 2036 fix_operand_size (&operand[i], 2); 2037 break; 2038 case SL: 2039 fix_operand_size (&operand[i], 4); 2040 break; 2041 } 2042 } 2043 2044 instruction = get_specific (instruction, operand, size); 2045 2046 if (instruction == 0) 2047 { 2048 /* Couldn't find an opcode which matched the operands. */ 2049 char *where = frag_more (2); 2050 2051 where[0] = 0x0; 2052 where[1] = 0x0; 2053 clever_message (prev_instruction, operand); 2054 2055 return; 2056 } 2057 2058 build_bytes (instruction, operand); 2059 2060 dwarf2_emit_insn (instruction->length); 2061 } 2062 2063 symbolS * 2064 md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 2065 { 2066 return 0; 2067 } 2068 2069 /* Various routines to kill one day. */ 2070 2071 const char * 2072 md_atof (int type, char *litP, int *sizeP) 2073 { 2074 return ieee_md_atof (type, litP, sizeP, true); 2075 } 2076 2077 #define OPTION_H_TICK_HEX (OPTION_MD_BASE) 2079 #define OPTION_MACH (OPTION_MD_BASE+1) 2080 2081 const char md_shortopts[] = ""; 2082 const struct option md_longopts[] = 2083 { 2084 { "h-tick-hex", no_argument, NULL, OPTION_H_TICK_HEX }, 2085 { "mach", required_argument, NULL, OPTION_MACH }, 2086 {NULL, no_argument, NULL, 0} 2087 }; 2088 2089 const size_t md_longopts_size = sizeof (md_longopts); 2090 2091 struct mach_func 2092 { 2093 const char *name; 2094 void (*func) (void); 2095 }; 2096 2097 static void 2098 mach_h8300h (void) 2099 { 2100 Hmode = 1; 2101 Smode = 0; 2102 Nmode = 0; 2103 SXmode = 0; 2104 default_mach = bfd_mach_h8300h; 2105 } 2106 2107 static void 2108 mach_h8300hn (void) 2109 { 2110 Hmode = 1; 2111 Smode = 0; 2112 Nmode = 1; 2113 SXmode = 0; 2114 default_mach = bfd_mach_h8300hn; 2115 } 2116 2117 static void 2118 mach_h8300s (void) 2119 { 2120 Hmode = 1; 2121 Smode = 1; 2122 Nmode = 0; 2123 SXmode = 0; 2124 default_mach = bfd_mach_h8300s; 2125 } 2126 2127 static void 2128 mach_h8300sn (void) 2129 { 2130 Hmode = 1; 2131 Smode = 1; 2132 Nmode = 1; 2133 SXmode = 0; 2134 default_mach = bfd_mach_h8300sn; 2135 } 2136 2137 static void 2138 mach_h8300sx (void) 2139 { 2140 Hmode = 1; 2141 Smode = 1; 2142 Nmode = 0; 2143 SXmode = 1; 2144 default_mach = bfd_mach_h8300sx; 2145 } 2146 2147 static void 2148 mach_h8300sxn (void) 2149 { 2150 Hmode = 1; 2151 Smode = 1; 2152 Nmode = 1; 2153 SXmode = 1; 2154 default_mach = bfd_mach_h8300sxn; 2155 } 2156 2157 const struct mach_func mach_table[] = 2158 { 2159 {"h8300h", mach_h8300h}, 2160 {"h8300hn", mach_h8300hn}, 2161 {"h8300s", mach_h8300s}, 2162 {"h8300sn", mach_h8300sn}, 2163 {"h8300sx", mach_h8300sx}, 2164 {"h8300sxn", mach_h8300sxn} 2165 }; 2166 2167 int 2168 md_parse_option (int c ATTRIBUTE_UNUSED, const char *arg ATTRIBUTE_UNUSED) 2169 { 2170 unsigned int i; 2171 switch (c) 2172 { 2173 case OPTION_H_TICK_HEX: 2174 enable_h_tick_hex = 1; 2175 break; 2176 case OPTION_MACH: 2177 for (i = 0; i < sizeof(mach_table) / sizeof(struct mach_func); i++) 2178 { 2179 if (strcasecmp (arg, mach_table[i].name) == 0) 2180 { 2181 mach_table[i].func(); 2182 break; 2183 } 2184 } 2185 if (i >= sizeof(mach_table) / sizeof(struct mach_func)) 2186 as_bad (_("Invalid argument to --mach option: %s"), arg); 2187 break; 2188 default: 2189 return 0; 2190 } 2191 return 1; 2192 } 2193 2194 void 2195 md_show_usage (FILE *stream) 2196 { 2197 fprintf (stream, _(" H8300-specific assembler options:\n")); 2198 fprintf (stream, _("\ 2199 -mach=<name> Set the H8300 machine type to one of:\n\ 2200 h8300h, h8300hn, h8300s, h8300sn, h8300sx, h8300sxn\n")); 2201 fprintf (stream, _("\ 2202 -h-tick-hex Support H'00 style hex constants\n")); 2203 } 2204 2205 void tc_aout_fix_to_chars (void); 2207 2208 void 2209 tc_aout_fix_to_chars (void) 2210 { 2211 printf (_("call to tc_aout_fix_to_chars \n")); 2212 abort (); 2213 } 2214 2215 void 2216 md_convert_frag (bfd *headers ATTRIBUTE_UNUSED, 2217 segT seg ATTRIBUTE_UNUSED, 2218 fragS *fragP ATTRIBUTE_UNUSED) 2219 { 2220 printf (_("call to md_convert_frag \n")); 2221 abort (); 2222 } 2223 2224 valueT 2225 md_section_align (segT segment, valueT size) 2226 { 2227 int align = bfd_section_alignment (segment); 2228 return (size + ((valueT) 1 << align) - 1) & -((valueT) 1 << align); 2229 } 2230 2231 void 2232 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) 2233 { 2234 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; 2235 long val = *valP; 2236 2237 switch (fixP->fx_size) 2238 { 2239 case 1: 2240 *buf++ = val; 2241 break; 2242 case 2: 2243 *buf++ = (val >> 8); 2244 *buf++ = val; 2245 break; 2246 case 4: 2247 *buf++ = (val >> 24); 2248 *buf++ = (val >> 16); 2249 *buf++ = (val >> 8); 2250 *buf++ = val; 2251 break; 2252 case 8: 2253 /* This can arise when the .quad or .8byte pseudo-ops are used. 2254 Returning here (without setting fx_done) will cause the code 2255 to attempt to generate a reloc which will then fail with the 2256 slightly more helpful error message: "Cannot represent 2257 relocation type BFD_RELOC_64". */ 2258 return; 2259 default: 2260 abort (); 2261 } 2262 2263 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0) 2264 fixP->fx_done = 1; 2265 } 2266 2267 int 2268 md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED, 2269 segT segment_type ATTRIBUTE_UNUSED) 2270 { 2271 printf (_("call to md_estimate_size_before_relax \n")); 2272 abort (); 2273 } 2274 2275 /* Put number into target byte order. */ 2276 void 2277 md_number_to_chars (char *ptr, valueT use, int nbytes) 2278 { 2279 number_to_chars_bigendian (ptr, use, nbytes); 2280 } 2281 2282 long 2283 md_pcrel_from (fixS *fixp) 2284 { 2285 as_bad_where (fixp->fx_file, fixp->fx_line, 2286 _("Unexpected reference to a symbol in a non-code section")); 2287 return 0; 2288 } 2289 2290 arelent * 2291 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) 2292 { 2293 arelent *rel; 2294 bfd_reloc_code_real_type r_type; 2295 2296 if (fixp->fx_addsy && fixp->fx_subsy) 2297 { 2298 if ((S_GET_SEGMENT (fixp->fx_addsy) != S_GET_SEGMENT (fixp->fx_subsy)) 2299 || S_GET_SEGMENT (fixp->fx_addsy) == undefined_section) 2300 { 2301 as_bad_subtract (fixp); 2302 return NULL; 2303 } 2304 } 2305 2306 rel = notes_alloc (sizeof (arelent)); 2307 rel->sym_ptr_ptr = notes_alloc (sizeof (asymbol *)); 2308 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 2309 rel->address = fixp->fx_frag->fr_address + fixp->fx_where; 2310 rel->addend = fixp->fx_offset; 2311 2312 r_type = fixp->fx_r_type; 2313 2314 #define DEBUG 0 2315 #if DEBUG 2316 fprintf (stderr, "%s\n", bfd_get_reloc_code_name (r_type)); 2317 fflush (stderr); 2318 #endif 2319 rel->howto = bfd_reloc_type_lookup (stdoutput, r_type); 2320 if (rel->howto == NULL) 2321 { 2322 as_bad_where (fixp->fx_file, fixp->fx_line, 2323 _("Cannot represent relocation type %s"), 2324 bfd_get_reloc_code_name (r_type)); 2325 return NULL; 2326 } 2327 2328 return rel; 2329 } 2330
Indexes created Fri Mar 20 00:23:26 UTC 2026