tc-msp430.c revision 1.1.1.2.8.1
1 /* tc-msp430.c -- Assembler code for the Texas Instruments MSP430 2 3 Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2009, 2010, 2012 4 Free Software Foundation, Inc. 5 Contributed by Dmitry Diky <diwil (at) mail.ru> 6 7 This file is part of GAS, the GNU Assembler. 8 9 GAS is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 GAS is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with GAS; see the file COPYING. If not, write to 21 the Free Software Foundation, 51 Franklin Street - Fifth Floor, 22 Boston, MA 02110-1301, USA. */ 23 24 #include "as.h" 25 #include <limits.h> 26 #define PUSH_1X_WORKAROUND 27 #include "subsegs.h" 28 #include "opcode/msp430.h" 29 #include "safe-ctype.h" 30 #include "dwarf2dbg.h" 31 32 /* We will disable polymorphs by default because it is dangerous. 33 The potential problem here is the following: assume we got the 34 following code: 35 36 jump .l1 37 nop 38 jump subroutine ; external symbol 39 .l1: 40 nop 41 ret 42 43 In case of assembly time relaxation we'll get: 44 0: jmp .l1 <.text +0x08> (reloc deleted) 45 2: nop 46 4: br subroutine 47 .l1: 48 8: nop 49 10: ret 50 51 If the 'subroutine' is within +-1024 bytes range then linker 52 will produce: 53 0: jmp .text +0x08 54 2: nop 55 4: jmp subroutine 56 .l1: 57 6: nop 58 8: ret ; 'jmp .text +0x08' will land here. WRONG!!! 59 60 The workaround is the following: 61 1. Declare global var enable_polymorphs which set to 1 via option -mp. 62 2. Declare global var enable_relax which set to 1 via option -mQ. 63 64 If polymorphs are enabled, and relax isn't, treat all jumps as long jumps, 65 do not delete any relocs and leave them for linker. 66 67 If relax is enabled, relax at assembly time and kill relocs as necessary. */ 68 69 int msp430_enable_relax; 70 int msp430_enable_polys; 71 72 /* GCC uses the some condition codes which we'll 73 implement as new polymorph instructions. 74 75 COND EXPL SHORT JUMP LONG JUMP 76 =============================================== 77 eq == jeq jne +4; br lab 78 ne != jne jeq +4; br lab 79 80 ltn honours no-overflow flag 81 ltn < jn jn +2; jmp +4; br lab 82 83 lt < jl jge +4; br lab 84 ltu < jlo lhs +4; br lab 85 le <= see below 86 leu <= see below 87 88 gt > see below 89 gtu > see below 90 ge >= jge jl +4; br lab 91 geu >= jhs jlo +4; br lab 92 =============================================== 93 94 Therefore, new opcodes are (BranchEQ -> beq; and so on...) 95 beq,bne,blt,bltn,bltu,bge,bgeu 96 'u' means unsigned compares 97 98 Also, we add 'jump' instruction: 99 jump UNCOND -> jmp br lab 100 101 They will have fmt == 4, and insn_opnumb == number of instruction. */ 102 103 struct rcodes_s 104 { 105 char * name; 106 int index; /* Corresponding insn_opnumb. */ 107 int sop; /* Opcode if jump length is short. */ 108 long lpos; /* Label position. */ 109 long lop0; /* Opcode 1 _word_ (16 bits). */ 110 long lop1; /* Opcode second word. */ 111 long lop2; /* Opcode third word. */ 112 }; 113 114 #define MSP430_RLC(n,i,sop,o1) \ 115 {#n, i, sop, 2, (o1 + 2), 0x4010, 0} 116 117 static struct rcodes_s msp430_rcodes[] = 118 { 119 MSP430_RLC (beq, 0, 0x2400, 0x2000), 120 MSP430_RLC (bne, 1, 0x2000, 0x2400), 121 MSP430_RLC (blt, 2, 0x3800, 0x3400), 122 MSP430_RLC (bltu, 3, 0x2800, 0x2c00), 123 MSP430_RLC (bge, 4, 0x3400, 0x3800), 124 MSP430_RLC (bgeu, 5, 0x2c00, 0x2800), 125 {"bltn", 6, 0x3000, 3, 0x3000 + 1, 0x3c00 + 2,0x4010}, 126 {"jump", 7, 0x3c00, 1, 0x4010, 0, 0}, 127 {0,0,0,0,0,0,0} 128 }; 129 #undef MSP430_RLC 130 131 132 /* More difficult than above and they have format 5. 133 134 COND EXPL SHORT LONG 135 ================================================================= 136 gt > jeq +2; jge label jeq +6; jl +4; br label 137 gtu > jeq +2; jhs label jeq +6; jlo +4; br label 138 leu <= jeq label; jlo label jeq +2; jhs +4; br label 139 le <= jeq label; jl label jeq +2; jge +4; br label 140 ================================================================= */ 141 142 struct hcodes_s 143 { 144 char * name; 145 int index; /* Corresponding insn_opnumb. */ 146 int tlab; /* Number of labels in short mode. */ 147 int op0; /* Opcode for first word of short jump. */ 148 int op1; /* Opcode for second word of short jump. */ 149 int lop0; /* Opcodes for long jump mode. */ 150 int lop1; 151 int lop2; 152 }; 153 154 static struct hcodes_s msp430_hcodes[] = 155 { 156 {"bgt", 0, 1, 0x2401, 0x3400, 0x2403, 0x3802, 0x4010 }, 157 {"bgtu", 1, 1, 0x2401, 0x2c00, 0x2403, 0x2802, 0x4010 }, 158 {"bleu", 2, 2, 0x2400, 0x2800, 0x2401, 0x2c02, 0x4010 }, 159 {"ble", 3, 2, 0x2400, 0x3800, 0x2401, 0x3402, 0x4010 }, 160 {0,0,0,0,0,0,0,0} 161 }; 162 163 const char comment_chars[] = ";"; 164 const char line_comment_chars[] = "#"; 165 const char line_separator_chars[] = "{"; 166 const char EXP_CHARS[] = "eE"; 167 const char FLT_CHARS[] = "dD"; 168 169 /* Handle long expressions. */ 170 extern LITTLENUM_TYPE generic_bignum[]; 171 172 static struct hash_control *msp430_hash; 173 174 /* Relaxations. */ 175 #define STATE_UNCOND_BRANCH 1 /* jump */ 176 #define STATE_NOOV_BRANCH 3 /* bltn */ 177 #define STATE_SIMPLE_BRANCH 2 /* bne, beq, etc... */ 178 #define STATE_EMUL_BRANCH 4 179 180 #define CNRL 2 181 #define CUBL 4 182 #define CNOL 8 183 #define CSBL 6 184 #define CEBL 4 185 186 /* Length. */ 187 #define STATE_BITS10 1 /* wild guess. short jump */ 188 #define STATE_WORD 2 /* 2 bytes pc rel. addr. more */ 189 #define STATE_UNDEF 3 /* cannot handle this yet. convert to word mode */ 190 191 #define ENCODE_RELAX(what,length) (((what) << 2) + (length)) 192 #define RELAX_STATE(s) ((s) & 3) 193 #define RELAX_LEN(s) ((s) >> 2) 194 #define RELAX_NEXT(a,b) ENCODE_RELAX (a, b + 1) 195 196 relax_typeS md_relax_table[] = 197 { 198 /* Unused. */ 199 {1, 1, 0, 0}, 200 {1, 1, 0, 0}, 201 {1, 1, 0, 0}, 202 {1, 1, 0, 0}, 203 204 /* Unconditional jump. */ 205 {1, 1, 8, 5}, 206 {1024, -1024, CNRL, RELAX_NEXT (STATE_UNCOND_BRANCH, STATE_BITS10)}, /* state 10 bits displ */ 207 {0, 0, CUBL, RELAX_NEXT (STATE_UNCOND_BRANCH, STATE_WORD)}, /* state word */ 208 {1, 1, CUBL, 0}, /* state undef */ 209 210 /* Simple branches. */ 211 {0, 0, 8, 9}, 212 {1024, -1024, CNRL, RELAX_NEXT (STATE_SIMPLE_BRANCH, STATE_BITS10)}, /* state 10 bits displ */ 213 {0, 0, CSBL, RELAX_NEXT (STATE_SIMPLE_BRANCH, STATE_WORD)}, /* state word */ 214 {1, 1, CSBL, 0}, 215 216 /* blt no overflow branch. */ 217 {1, 1, 8, 13}, 218 {1024, -1024, CNRL, RELAX_NEXT (STATE_NOOV_BRANCH, STATE_BITS10)}, /* state 10 bits displ */ 219 {0, 0, CNOL, RELAX_NEXT (STATE_NOOV_BRANCH, STATE_WORD)}, /* state word */ 220 {1, 1, CNOL, 0}, 221 222 /* Emulated branches. */ 223 {1, 1, 8, 17}, 224 {1020, -1020, CEBL, RELAX_NEXT (STATE_EMUL_BRANCH, STATE_BITS10)}, /* state 10 bits displ */ 225 {0, 0, CNOL, RELAX_NEXT (STATE_EMUL_BRANCH, STATE_WORD)}, /* state word */ 226 {1, 1, CNOL, 0} 227 }; 228 229 230 #define MAX_OP_LEN 256 231 232 struct mcu_type_s 233 { 234 char * name; 235 int isa; 236 int mach; 237 }; 238 239 #define MSP430_ISA_11 11 240 #define MSP430_ISA_110 110 241 #define MSP430_ISA_12 12 242 #define MSP430_ISA_13 13 243 #define MSP430_ISA_14 14 244 #define MSP430_ISA_15 15 245 #define MSP430_ISA_16 16 246 #define MSP430_ISA_21 21 247 #define MSP430_ISA_31 31 248 #define MSP430_ISA_32 32 249 #define MSP430_ISA_33 33 250 #define MSP430_ISA_41 41 251 #define MSP430_ISA_42 42 252 #define MSP430_ISA_43 43 253 #define MSP430_ISA_44 44 254 255 #define CHECK_RELOC_MSP430 ((imm_op || byte_op)?BFD_RELOC_MSP430_16_BYTE:BFD_RELOC_MSP430_16) 256 #define CHECK_RELOC_MSP430_PCREL ((imm_op || byte_op)?BFD_RELOC_MSP430_16_PCREL_BYTE:BFD_RELOC_MSP430_16_PCREL) 257 258 static struct mcu_type_s mcu_types[] = 259 { 260 {"msp1", MSP430_ISA_11, bfd_mach_msp11}, 261 {"msp2", MSP430_ISA_14, bfd_mach_msp14}, 262 {"msp430x110", MSP430_ISA_11, bfd_mach_msp11}, 263 {"msp430x112", MSP430_ISA_11, bfd_mach_msp11}, 264 {"msp430x1101", MSP430_ISA_110, bfd_mach_msp110}, 265 {"msp430x1111", MSP430_ISA_110, bfd_mach_msp110}, 266 {"msp430x1121", MSP430_ISA_110, bfd_mach_msp110}, 267 {"msp430x1122", MSP430_ISA_11, bfd_mach_msp110}, 268 {"msp430x1132", MSP430_ISA_11, bfd_mach_msp110}, 269 270 {"msp430x122", MSP430_ISA_12, bfd_mach_msp12}, 271 {"msp430x123", MSP430_ISA_12, bfd_mach_msp12}, 272 {"msp430x1222", MSP430_ISA_12, bfd_mach_msp12}, 273 {"msp430x1232", MSP430_ISA_12, bfd_mach_msp12}, 274 275 {"msp430x133", MSP430_ISA_13, bfd_mach_msp13}, 276 {"msp430x135", MSP430_ISA_13, bfd_mach_msp13}, 277 {"msp430x1331", MSP430_ISA_13, bfd_mach_msp13}, 278 {"msp430x1351", MSP430_ISA_13, bfd_mach_msp13}, 279 {"msp430x147", MSP430_ISA_14, bfd_mach_msp14}, 280 {"msp430x148", MSP430_ISA_14, bfd_mach_msp14}, 281 {"msp430x149", MSP430_ISA_14, bfd_mach_msp14}, 282 283 {"msp430x155", MSP430_ISA_15, bfd_mach_msp15}, 284 {"msp430x156", MSP430_ISA_15, bfd_mach_msp15}, 285 {"msp430x157", MSP430_ISA_15, bfd_mach_msp15}, 286 {"msp430x167", MSP430_ISA_16, bfd_mach_msp16}, 287 {"msp430x168", MSP430_ISA_16, bfd_mach_msp16}, 288 {"msp430x169", MSP430_ISA_16, bfd_mach_msp16}, 289 {"msp430x1610", MSP430_ISA_16, bfd_mach_msp16}, 290 {"msp430x1611", MSP430_ISA_16, bfd_mach_msp16}, 291 {"msp430x1612", MSP430_ISA_16, bfd_mach_msp16}, 292 293 {"msp430x2101", MSP430_ISA_21, bfd_mach_msp21}, 294 {"msp430x2111", MSP430_ISA_21, bfd_mach_msp21}, 295 {"msp430x2121", MSP430_ISA_21, bfd_mach_msp21}, 296 {"msp430x2131", MSP430_ISA_21, bfd_mach_msp21}, 297 298 {"msp430x311", MSP430_ISA_31, bfd_mach_msp31}, 299 {"msp430x312", MSP430_ISA_31, bfd_mach_msp31}, 300 {"msp430x313", MSP430_ISA_31, bfd_mach_msp31}, 301 {"msp430x314", MSP430_ISA_31, bfd_mach_msp31}, 302 {"msp430x315", MSP430_ISA_31, bfd_mach_msp31}, 303 {"msp430x323", MSP430_ISA_32, bfd_mach_msp32}, 304 {"msp430x325", MSP430_ISA_32, bfd_mach_msp32}, 305 {"msp430x336", MSP430_ISA_33, bfd_mach_msp33}, 306 {"msp430x337", MSP430_ISA_33, bfd_mach_msp33}, 307 308 {"msp430x412", MSP430_ISA_41, bfd_mach_msp41}, 309 {"msp430x413", MSP430_ISA_41, bfd_mach_msp41}, 310 {"msp430x415", MSP430_ISA_41, bfd_mach_msp41}, 311 {"msp430x417", MSP430_ISA_41, bfd_mach_msp41}, 312 313 {"msp430xE423", MSP430_ISA_42, bfd_mach_msp42}, 314 {"msp430xE425", MSP430_ISA_42, bfd_mach_msp42}, 315 {"msp430xE427", MSP430_ISA_42, bfd_mach_msp42}, 316 317 {"msp430xW423", MSP430_ISA_42, bfd_mach_msp42}, 318 {"msp430xW425", MSP430_ISA_42, bfd_mach_msp42}, 319 {"msp430xW427", MSP430_ISA_42, bfd_mach_msp42}, 320 321 {"msp430xG437", MSP430_ISA_43, bfd_mach_msp43}, 322 {"msp430xG438", MSP430_ISA_43, bfd_mach_msp43}, 323 {"msp430xG439", MSP430_ISA_43, bfd_mach_msp43}, 324 325 {"msp430x435", MSP430_ISA_43, bfd_mach_msp43}, 326 {"msp430x436", MSP430_ISA_43, bfd_mach_msp43}, 327 {"msp430x437", MSP430_ISA_43, bfd_mach_msp43}, 328 {"msp430x447", MSP430_ISA_44, bfd_mach_msp44}, 329 {"msp430x448", MSP430_ISA_44, bfd_mach_msp44}, 330 {"msp430x449", MSP430_ISA_44, bfd_mach_msp44}, 331 332 {NULL, 0, 0} 333 }; 334 335 336 static struct mcu_type_s default_mcu = 337 { "msp430x11", MSP430_ISA_11, bfd_mach_msp11 }; 338 339 static struct mcu_type_s * msp430_mcu = & default_mcu; 340 341 /* Profiling capability: 342 It is a performance hit to use gcc's profiling approach for this tiny target. 343 Even more -- jtag hardware facility does not perform any profiling functions. 344 However we've got gdb's built-in simulator where we can do anything. 345 Therefore my suggestion is: 346 347 We define new section ".profiler" which holds all profiling information. 348 We define new pseudo operation .profiler which will instruct assembler to 349 add new profile entry to the object file. Profile should take place at the 350 present address. 351 352 Pseudo-op format: 353 354 .profiler flags,function_to_profile [, cycle_corrector, extra] 355 356 where 'flags' is a combination of the following chars: 357 s - function Start 358 x - function eXit 359 i - function is in Init section 360 f - function is in Fini section 361 l - Library call 362 c - libC standard call 363 d - stack value Demand (saved at run-time in simulator) 364 I - Interrupt service routine 365 P - Prologue start 366 p - Prologue end 367 E - Epilogue start 368 e - Epilogue end 369 j - long Jump/ sjlj unwind 370 a - an Arbitrary code fragment 371 t - exTra parameter saved (constant value like frame size) 372 '""' optional: "sil" == sil 373 374 function_to_profile - function's address 375 cycle_corrector - a value which should be added to the cycle 376 counter, zero if omitted 377 extra - some extra parameter, zero if omitted. 378 379 For example: 380 ------------------------------ 381 .global fxx 382 .type fxx,@function 383 fxx: 384 .LFrameOffset_fxx=0x08 385 .profiler "scdP", fxx ; function entry. 386 ; we also demand stack value to be displayed 387 push r11 388 push r10 389 push r9 390 push r8 391 .profiler "cdp",fxx,0, .LFrameOffset_fxx ; check stack value at this point 392 ; (this is a prologue end) 393 ; note, that spare var filled with the frame size 394 mov r15,r8 395 .... 396 .profiler cdE,fxx ; check stack 397 pop r8 398 pop r9 399 pop r10 400 pop r11 401 .profiler xcde,fxx,3 ; exit adds 3 to the cycle counter 402 ret ; cause 'ret' insn takes 3 cycles 403 ------------------------------- 404 405 This profiling approach does not produce any overhead and 406 absolutely harmless. 407 So, even profiled code can be uploaded to the MCU. */ 408 #define MSP430_PROFILER_FLAG_ENTRY 1 /* s */ 409 #define MSP430_PROFILER_FLAG_EXIT 2 /* x */ 410 #define MSP430_PROFILER_FLAG_INITSECT 4 /* i */ 411 #define MSP430_PROFILER_FLAG_FINISECT 8 /* f */ 412 #define MSP430_PROFILER_FLAG_LIBCALL 0x10 /* l */ 413 #define MSP430_PROFILER_FLAG_STDCALL 0x20 /* c */ 414 #define MSP430_PROFILER_FLAG_STACKDMD 0x40 /* d */ 415 #define MSP430_PROFILER_FLAG_ISR 0x80 /* I */ 416 #define MSP430_PROFILER_FLAG_PROLSTART 0x100 /* P */ 417 #define MSP430_PROFILER_FLAG_PROLEND 0x200 /* p */ 418 #define MSP430_PROFILER_FLAG_EPISTART 0x400 /* E */ 419 #define MSP430_PROFILER_FLAG_EPIEND 0x800 /* e */ 420 #define MSP430_PROFILER_FLAG_JUMP 0x1000 /* j */ 421 #define MSP430_PROFILER_FLAG_FRAGMENT 0x2000 /* a */ 422 #define MSP430_PROFILER_FLAG_EXTRA 0x4000 /* t */ 423 #define MSP430_PROFILER_FLAG_notyet 0x8000 /* ? */ 424 425 static int 426 pow2value (int y) 427 { 428 int n = 0; 429 unsigned int x; 430 431 x = y; 432 433 if (!x) 434 return 1; 435 436 for (; x; x = x >> 1) 437 if (x & 1) 438 n++; 439 440 return n == 1; 441 } 442 443 /* Parse ordinary expression. */ 444 445 static char * 446 parse_exp (char * s, expressionS * op) 447 { 448 input_line_pointer = s; 449 expression (op); 450 if (op->X_op == O_absent) 451 as_bad (_("missing operand")); 452 return input_line_pointer; 453 } 454 455 456 /* Delete spaces from s: X ( r 1 2) => X(r12). */ 457 458 static void 459 del_spaces (char * s) 460 { 461 while (*s) 462 { 463 if (ISSPACE (*s)) 464 { 465 char *m = s + 1; 466 467 while (ISSPACE (*m) && *m) 468 m++; 469 memmove (s, m, strlen (m) + 1); 470 } 471 else 472 s++; 473 } 474 } 475 476 static inline char * 477 skip_space (char * s) 478 { 479 while (ISSPACE (*s)) 480 ++s; 481 return s; 482 } 483 484 /* Extract one word from FROM and copy it to TO. Delimiters are ",;\n" */ 485 486 static char * 487 extract_operand (char * from, char * to, int limit) 488 { 489 int size = 0; 490 491 /* Drop leading whitespace. */ 492 from = skip_space (from); 493 494 while (size < limit && *from) 495 { 496 *(to + size) = *from; 497 if (*from == ',' || *from == ';' || *from == '\n') 498 break; 499 from++; 500 size++; 501 } 502 503 *(to + size) = 0; 504 del_spaces (to); 505 506 from++; 507 508 return from; 509 } 510 511 static void 512 msp430_profiler (int dummy ATTRIBUTE_UNUSED) 513 { 514 char buffer[1024]; 515 char f[32]; 516 char * str = buffer; 517 char * flags = f; 518 int p_flags = 0; 519 char * halt; 520 int ops = 0; 521 int left; 522 char * s; 523 segT seg; 524 int subseg; 525 char * end = 0; 526 expressionS exp; 527 expressionS exp1; 528 529 s = input_line_pointer; 530 end = input_line_pointer; 531 532 while (*end && *end != '\n') 533 end++; 534 535 while (*s && *s != '\n') 536 { 537 if (*s == ',') 538 ops++; 539 s++; 540 } 541 542 left = 3 - ops; 543 544 if (ops < 1) 545 { 546 as_bad (_(".profiler pseudo requires at least two operands.")); 547 input_line_pointer = end; 548 return; 549 } 550 551 input_line_pointer = extract_operand (input_line_pointer, flags, 32); 552 553 while (*flags) 554 { 555 switch (*flags) 556 { 557 case '"': 558 break; 559 case 'a': 560 p_flags |= MSP430_PROFILER_FLAG_FRAGMENT; 561 break; 562 case 'j': 563 p_flags |= MSP430_PROFILER_FLAG_JUMP; 564 break; 565 case 'P': 566 p_flags |= MSP430_PROFILER_FLAG_PROLSTART; 567 break; 568 case 'p': 569 p_flags |= MSP430_PROFILER_FLAG_PROLEND; 570 break; 571 case 'E': 572 p_flags |= MSP430_PROFILER_FLAG_EPISTART; 573 break; 574 case 'e': 575 p_flags |= MSP430_PROFILER_FLAG_EPIEND; 576 break; 577 case 's': 578 p_flags |= MSP430_PROFILER_FLAG_ENTRY; 579 break; 580 case 'x': 581 p_flags |= MSP430_PROFILER_FLAG_EXIT; 582 break; 583 case 'i': 584 p_flags |= MSP430_PROFILER_FLAG_INITSECT; 585 break; 586 case 'f': 587 p_flags |= MSP430_PROFILER_FLAG_FINISECT; 588 break; 589 case 'l': 590 p_flags |= MSP430_PROFILER_FLAG_LIBCALL; 591 break; 592 case 'c': 593 p_flags |= MSP430_PROFILER_FLAG_STDCALL; 594 break; 595 case 'd': 596 p_flags |= MSP430_PROFILER_FLAG_STACKDMD; 597 break; 598 case 'I': 599 p_flags |= MSP430_PROFILER_FLAG_ISR; 600 break; 601 case 't': 602 p_flags |= MSP430_PROFILER_FLAG_EXTRA; 603 break; 604 default: 605 as_warn (_("unknown profiling flag - ignored.")); 606 break; 607 } 608 flags++; 609 } 610 611 if (p_flags 612 && ( ! pow2value (p_flags & ( MSP430_PROFILER_FLAG_ENTRY 613 | MSP430_PROFILER_FLAG_EXIT)) 614 || ! pow2value (p_flags & ( MSP430_PROFILER_FLAG_PROLSTART 615 | MSP430_PROFILER_FLAG_PROLEND 616 | MSP430_PROFILER_FLAG_EPISTART 617 | MSP430_PROFILER_FLAG_EPIEND)) 618 || ! pow2value (p_flags & ( MSP430_PROFILER_FLAG_INITSECT 619 | MSP430_PROFILER_FLAG_FINISECT)))) 620 { 621 as_bad (_("ambiguous flags combination - '.profiler' directive ignored.")); 622 input_line_pointer = end; 623 return; 624 } 625 626 /* Generate temp symbol which denotes current location. */ 627 if (now_seg == absolute_section) /* Paranoia ? */ 628 { 629 exp1.X_op = O_constant; 630 exp1.X_add_number = abs_section_offset; 631 as_warn (_("profiling in absolute section?")); 632 } 633 else 634 { 635 exp1.X_op = O_symbol; 636 exp1.X_add_symbol = symbol_temp_new_now (); 637 exp1.X_add_number = 0; 638 } 639 640 /* Generate a symbol which holds flags value. */ 641 exp.X_op = O_constant; 642 exp.X_add_number = p_flags; 643 644 /* Save current section. */ 645 seg = now_seg; 646 subseg = now_subseg; 647 648 /* Now go to .profiler section. */ 649 obj_elf_change_section (".profiler", SHT_PROGBITS, 0, 0, 0, 0, 0); 650 651 /* Save flags. */ 652 emit_expr (& exp, 2); 653 654 /* Save label value. */ 655 emit_expr (& exp1, 2); 656 657 while (ops--) 658 { 659 /* Now get profiling info. */ 660 halt = extract_operand (input_line_pointer, str, 1024); 661 /* Process like ".word xxx" directive. */ 662 parse_exp (str, & exp); 663 emit_expr (& exp, 2); 664 input_line_pointer = halt; 665 } 666 667 /* Fill the rest with zeros. */ 668 exp.X_op = O_constant; 669 exp.X_add_number = 0; 670 while (left--) 671 emit_expr (& exp, 2); 672 673 /* Return to current section. */ 674 subseg_set (seg, subseg); 675 } 676 677 static char * 678 extract_word (char * from, char * to, int limit) 679 { 680 char *op_end; 681 int size = 0; 682 683 /* Drop leading whitespace. */ 684 from = skip_space (from); 685 *to = 0; 686 687 /* Find the op code end. */ 688 for (op_end = from; *op_end != 0 && is_part_of_name (*op_end);) 689 { 690 to[size++] = *op_end++; 691 if (size + 1 >= limit) 692 break; 693 } 694 695 to[size] = 0; 696 return op_end; 697 } 698 699 #define OPTION_MMCU 'm' 700 #define OPTION_RELAX 'Q' 701 #define OPTION_POLYMORPHS 'P' 702 703 static void 704 msp430_set_arch (int dummy ATTRIBUTE_UNUSED) 705 { 706 char *str = (char *) alloca (32); /* 32 for good measure. */ 707 708 input_line_pointer = extract_word (input_line_pointer, str, 32); 709 710 md_parse_option (OPTION_MMCU, str); 711 bfd_set_arch_mach (stdoutput, TARGET_ARCH, msp430_mcu->mach); 712 } 713 714 static void 715 show_mcu_list (FILE * stream) 716 { 717 int i; 718 719 fprintf (stream, _("Known MCU names:\n")); 720 721 for (i = 0; mcu_types[i].name; i++) 722 fprintf (stream, _("\t %s\n"), mcu_types[i].name); 723 724 fprintf (stream, "\n"); 725 } 726 727 int 728 md_parse_option (int c, char * arg) 729 { 730 int i; 731 732 switch (c) 733 { 734 case OPTION_MMCU: 735 for (i = 0; mcu_types[i].name; ++i) 736 if (strcmp (mcu_types[i].name, arg) == 0) 737 break; 738 739 if (!mcu_types[i].name) 740 { 741 show_mcu_list (stderr); 742 as_fatal (_("unknown MCU: %s\n"), arg); 743 } 744 745 if (msp430_mcu == &default_mcu || msp430_mcu->mach == mcu_types[i].mach) 746 msp430_mcu = &mcu_types[i]; 747 else 748 as_fatal (_("redefinition of mcu type %s' to %s'"), 749 msp430_mcu->name, mcu_types[i].name); 750 return 1; 751 break; 752 753 case OPTION_RELAX: 754 msp430_enable_relax = 1; 755 return 1; 756 break; 757 758 case OPTION_POLYMORPHS: 759 msp430_enable_polys = 1; 760 return 1; 761 break; 762 } 763 764 return 0; 765 } 766 767 768 const pseudo_typeS md_pseudo_table[] = 769 { 770 {"arch", msp430_set_arch, 0}, 771 {"profiler", msp430_profiler, 0}, 772 {NULL, NULL, 0} 773 }; 774 775 const char *md_shortopts = "m:"; 776 777 struct option md_longopts[] = 778 { 779 {"mmcu", required_argument, NULL, OPTION_MMCU}, 780 {"mP", no_argument, NULL, OPTION_POLYMORPHS}, 781 {"mQ", no_argument, NULL, OPTION_RELAX}, 782 {NULL, no_argument, NULL, 0} 783 }; 784 785 size_t md_longopts_size = sizeof (md_longopts); 786 787 void 788 md_show_usage (FILE * stream) 789 { 790 fprintf (stream, 791 _("MSP430 options:\n" 792 " -mmcu=[msp430-name] select microcontroller type\n" 793 " msp430x110 msp430x112\n" 794 " msp430x1101 msp430x1111\n" 795 " msp430x1121 msp430x1122 msp430x1132\n" 796 " msp430x122 msp430x123\n" 797 " msp430x1222 msp430x1232\n" 798 " msp430x133 msp430x135\n" 799 " msp430x1331 msp430x1351\n" 800 " msp430x147 msp430x148 msp430x149\n" 801 " msp430x155 msp430x156 msp430x157\n" 802 " msp430x167 msp430x168 msp430x169\n" 803 " msp430x1610 msp430x1611 msp430x1612\n" 804 " msp430x311 msp430x312 msp430x313 msp430x314 msp430x315\n" 805 " msp430x323 msp430x325\n" 806 " msp430x336 msp430x337\n" 807 " msp430x412 msp430x413 msp430x415 msp430x417\n" 808 " msp430xE423 msp430xE425 msp430E427\n" 809 " msp430xW423 msp430xW425 msp430W427\n" 810 " msp430xG437 msp430xG438 msp430G439\n" 811 " msp430x435 msp430x436 msp430x437\n" 812 " msp430x447 msp430x448 msp430x449\n")); 813 fprintf (stream, 814 _(" -mQ - enable relaxation at assembly time. DANGEROUS!\n" 815 " -mP - enable polymorph instructions\n")); 816 817 show_mcu_list (stream); 818 } 819 820 symbolS * 821 md_undefined_symbol (char * name ATTRIBUTE_UNUSED) 822 { 823 return 0; 824 } 825 826 static char * 827 extract_cmd (char * from, char * to, int limit) 828 { 829 int size = 0; 830 831 while (*from && ! ISSPACE (*from) && *from != '.' && limit > size) 832 { 833 *(to + size) = *from; 834 from++; 835 size++; 836 } 837 838 *(to + size) = 0; 839 840 return from; 841 } 842 843 char * 844 md_atof (int type, char * litP, int * sizeP) 845 { 846 return ieee_md_atof (type, litP, sizeP, FALSE); 847 } 848 849 void 850 md_begin (void) 851 { 852 struct msp430_opcode_s * opcode; 853 msp430_hash = hash_new (); 854 855 for (opcode = msp430_opcodes; opcode->name; opcode++) 856 hash_insert (msp430_hash, opcode->name, (char *) opcode); 857 858 bfd_set_arch_mach (stdoutput, TARGET_ARCH, msp430_mcu->mach); 859 } 860 861 static int 862 check_reg (char * t) 863 { 864 /* If this is a reg numb, str 't' must be a number from 0 - 15. */ 865 866 if (strlen (t) > 2 && *(t + 2) != '+') 867 return 1; 868 869 while (*t) 870 { 871 if ((*t < '0' || *t > '9') && *t != '+') 872 break; 873 t++; 874 } 875 876 if (*t) 877 return 1; 878 879 return 0; 880 } 881 882 883 static int 884 msp430_srcoperand (struct msp430_operand_s * op, 885 char * l, int bin, int * imm_op) 886 { 887 char *__tl = l; 888 889 /* Check if an immediate #VALUE. The hash sign should be only at the beginning! */ 890 if (*l == '#') 891 { 892 char *h = l; 893 int vshift = -1; 894 int rval = 0; 895 896 /* Check if there is: 897 llo(x) - least significant 16 bits, x &= 0xffff 898 lhi(x) - x = (x >> 16) & 0xffff, 899 hlo(x) - x = (x >> 32) & 0xffff, 900 hhi(x) - x = (x >> 48) & 0xffff 901 The value _MUST_ be constant expression: #hlo(1231231231). */ 902 903 *imm_op = 1; 904 905 if (strncasecmp (h, "#llo(", 5) == 0) 906 { 907 vshift = 0; 908 rval = 3; 909 } 910 else if (strncasecmp (h, "#lhi(", 5) == 0) 911 { 912 vshift = 1; 913 rval = 3; 914 } 915 else if (strncasecmp (h, "#hlo(", 5) == 0) 916 { 917 vshift = 2; 918 rval = 3; 919 } 920 else if (strncasecmp (h, "#hhi(", 5) == 0) 921 { 922 vshift = 3; 923 rval = 3; 924 } 925 else if (strncasecmp (h, "#lo(", 4) == 0) 926 { 927 vshift = 0; 928 rval = 2; 929 } 930 else if (strncasecmp (h, "#hi(", 4) == 0) 931 { 932 vshift = 1; 933 rval = 2; 934 } 935 936 op->reg = 0; /* Reg PC. */ 937 op->am = 3; 938 op->ol = 1; /* Immediate will follow an instruction. */ 939 __tl = h + 1 + rval; 940 op->mode = OP_EXP; 941 942 parse_exp (__tl, &(op->exp)); 943 if (op->exp.X_op == O_constant) 944 { 945 int x = op->exp.X_add_number; 946 947 if (vshift == 0) 948 { 949 x = x & 0xffff; 950 op->exp.X_add_number = x; 951 } 952 else if (vshift == 1) 953 { 954 x = (x >> 16) & 0xffff; 955 op->exp.X_add_number = x; 956 } 957 else if (vshift > 1) 958 { 959 if (x < 0) 960 op->exp.X_add_number = -1; 961 else 962 op->exp.X_add_number = 0; /* Nothing left. */ 963 x = op->exp.X_add_number; 964 } 965 966 if (op->exp.X_add_number > 65535 || op->exp.X_add_number < -32768) 967 { 968 as_bad (_("value %d out of range. Use #lo() or #hi()"), x); 969 return 1; 970 } 971 972 /* Now check constants. */ 973 /* Substitute register mode with a constant generator if applicable. */ 974 975 x = (short) x; /* Extend sign. */ 976 977 if (x == 0) 978 { 979 op->reg = 3; 980 op->am = 0; 981 op->ol = 0; 982 op->mode = OP_REG; 983 } 984 else if (x == 1) 985 { 986 op->reg = 3; 987 op->am = 1; 988 op->ol = 0; 989 op->mode = OP_REG; 990 } 991 else if (x == 2) 992 { 993 op->reg = 3; 994 op->am = 2; 995 op->ol = 0; 996 op->mode = OP_REG; 997 } 998 else if (x == -1) 999 { 1000 op->reg = 3; 1001 op->am = 3; 1002 op->ol = 0; 1003 op->mode = OP_REG; 1004 } 1005 else if (x == 4) 1006 { 1007 #ifdef PUSH_1X_WORKAROUND 1008 if (bin == 0x1200) 1009 { 1010 /* Remove warning as confusing. 1011 as_warn (_("Hardware push bug workaround")); */ 1012 } 1013 else 1014 #endif 1015 { 1016 op->reg = 2; 1017 op->am = 2; 1018 op->ol = 0; 1019 op->mode = OP_REG; 1020 } 1021 } 1022 else if (x == 8) 1023 { 1024 #ifdef PUSH_1X_WORKAROUND 1025 if (bin == 0x1200) 1026 { 1027 /* Remove warning as confusing. 1028 as_warn (_("Hardware push bug workaround")); */ 1029 } 1030 else 1031 #endif 1032 { 1033 op->reg = 2; 1034 op->am = 3; 1035 op->ol = 0; 1036 op->mode = OP_REG; 1037 } 1038 } 1039 } 1040 else if (op->exp.X_op == O_symbol) 1041 { 1042 op->mode = OP_EXP; 1043 } 1044 else if (op->exp.X_op == O_big) 1045 { 1046 short x; 1047 if (vshift != -1) 1048 { 1049 op->exp.X_op = O_constant; 1050 op->exp.X_add_number = 0xffff & generic_bignum[vshift]; 1051 x = op->exp.X_add_number; 1052 } 1053 else 1054 { 1055 as_bad (_ 1056 ("unknown expression in operand %s. use #llo() #lhi() #hlo() #hhi() "), 1057 l); 1058 return 1; 1059 } 1060 1061 if (x == 0) 1062 { 1063 op->reg = 3; 1064 op->am = 0; 1065 op->ol = 0; 1066 op->mode = OP_REG; 1067 } 1068 else if (x == 1) 1069 { 1070 op->reg = 3; 1071 op->am = 1; 1072 op->ol = 0; 1073 op->mode = OP_REG; 1074 } 1075 else if (x == 2) 1076 { 1077 op->reg = 3; 1078 op->am = 2; 1079 op->ol = 0; 1080 op->mode = OP_REG; 1081 } 1082 else if (x == -1) 1083 { 1084 op->reg = 3; 1085 op->am = 3; 1086 op->ol = 0; 1087 op->mode = OP_REG; 1088 } 1089 else if (x == 4) 1090 { 1091 op->reg = 2; 1092 op->am = 2; 1093 op->ol = 0; 1094 op->mode = OP_REG; 1095 } 1096 else if (x == 8) 1097 { 1098 op->reg = 2; 1099 op->am = 3; 1100 op->ol = 0; 1101 op->mode = OP_REG; 1102 } 1103 } 1104 /* Redundant (yet) check. */ 1105 else if (op->exp.X_op == O_register) 1106 as_bad 1107 (_("Registers cannot be used within immediate expression [%s]"), l); 1108 else 1109 as_bad (_("unknown operand %s"), l); 1110 1111 return 0; 1112 } 1113 1114 /* Check if absolute &VALUE (assume that we can construct something like ((a&b)<<7 + 25). */ 1115 if (*l == '&') 1116 { 1117 char *h = l; 1118 1119 op->reg = 2; /* reg 2 in absolute addr mode. */ 1120 op->am = 1; /* mode As == 01 bin. */ 1121 op->ol = 1; /* Immediate value followed by instruction. */ 1122 __tl = h + 1; 1123 parse_exp (__tl, &(op->exp)); 1124 op->mode = OP_EXP; 1125 if (op->exp.X_op == O_constant) 1126 { 1127 int x = op->exp.X_add_number; 1128 1129 if (x > 65535 || x < -32768) 1130 { 1131 as_bad (_("value out of range: %d"), x); 1132 return 1; 1133 } 1134 } 1135 else if (op->exp.X_op == O_symbol) 1136 ; 1137 else 1138 { 1139 /* Redundant (yet) check. */ 1140 if (op->exp.X_op == O_register) 1141 as_bad 1142 (_("Registers cannot be used within absolute expression [%s]"), l); 1143 else 1144 as_bad (_("unknown expression in operand %s"), l); 1145 return 1; 1146 } 1147 return 0; 1148 } 1149 1150 /* Check if indirect register mode @Rn / postincrement @Rn+. */ 1151 if (*l == '@') 1152 { 1153 char *t = l; 1154 char *m = strchr (l, '+'); 1155 1156 if (t != l) 1157 { 1158 as_bad (_("unknown addressing mode %s"), l); 1159 return 1; 1160 } 1161 1162 t++; 1163 if (*t != 'r' && *t != 'R') 1164 { 1165 as_bad (_("unknown addressing mode %s"), l); 1166 return 1; 1167 } 1168 1169 t++; /* Points to the reg value. */ 1170 1171 if (check_reg (t)) 1172 { 1173 as_bad (_("Bad register name r%s"), t); 1174 return 1; 1175 } 1176 1177 op->mode = OP_REG; 1178 op->am = m ? 3 : 2; 1179 op->ol = 0; 1180 if (m) 1181 *m = 0; /* strip '+' */ 1182 op->reg = atoi (t); 1183 if (op->reg < 0 || op->reg > 15) 1184 { 1185 as_bad (_("MSP430 does not have %d registers"), op->reg); 1186 return 1; 1187 } 1188 1189 return 0; 1190 } 1191 1192 /* Check if register indexed X(Rn). */ 1193 do 1194 { 1195 char *h = strrchr (l, '('); 1196 char *m = strrchr (l, ')'); 1197 char *t; 1198 1199 *imm_op = 1; 1200 1201 if (!h) 1202 break; 1203 if (!m) 1204 { 1205 as_bad (_("')' required")); 1206 return 1; 1207 } 1208 1209 t = h; 1210 op->am = 1; 1211 op->ol = 1; 1212 /* Extract a register. */ 1213 t++; /* Advance pointer. */ 1214 1215 if (*t != 'r' && *t != 'R') 1216 { 1217 as_bad (_ 1218 ("unknown operator %s. Did you mean X(Rn) or #[hl][hl][oi](CONST) ?"), 1219 l); 1220 return 1; 1221 } 1222 t++; 1223 1224 op->reg = *t - '0'; 1225 if (op->reg > 9 || op->reg < 0) 1226 { 1227 as_bad (_("unknown operator (r%s substituted as a register name"), 1228 t); 1229 return 1; 1230 } 1231 t++; 1232 if (*t != ')') 1233 { 1234 op->reg = op->reg * 10; 1235 op->reg += *t - '0'; 1236 1237 if (op->reg > 15) 1238 { 1239 as_bad (_("unknown operator %s"), l); 1240 return 1; 1241 } 1242 if (op->reg == 2) 1243 { 1244 as_bad (_("r2 should not be used in indexed addressing mode")); 1245 return 1; 1246 } 1247 1248 if (*(t + 1) != ')') 1249 { 1250 as_bad (_("unknown operator %s"), l); 1251 return 1; 1252 } 1253 } 1254 1255 /* Extract constant. */ 1256 __tl = l; 1257 *h = 0; 1258 op->mode = OP_EXP; 1259 parse_exp (__tl, &(op->exp)); 1260 if (op->exp.X_op == O_constant) 1261 { 1262 int x = op->exp.X_add_number; 1263 1264 if (x > 65535 || x < -32768) 1265 { 1266 as_bad (_("value out of range: %d"), x); 1267 return 1; 1268 } 1269 1270 if (x == 0) 1271 { 1272 op->mode = OP_REG; 1273 op->am = 2; 1274 op->ol = 0; 1275 return 0; 1276 } 1277 } 1278 else if (op->exp.X_op == O_symbol) 1279 ; 1280 else 1281 { 1282 /* Redundant (yet) check. */ 1283 if (op->exp.X_op == O_register) 1284 as_bad 1285 (_("Registers cannot be used as a prefix of indexed expression [%s]"), l); 1286 else 1287 as_bad (_("unknown expression in operand %s"), l); 1288 return 1; 1289 } 1290 1291 return 0; 1292 } 1293 while (0); 1294 1295 /* Register mode 'mov r1,r2'. */ 1296 do 1297 { 1298 char *t = l; 1299 1300 /* Operand should be a register. */ 1301 if (*t == 'r' || *t == 'R') 1302 { 1303 int x = atoi (t + 1); 1304 1305 if (check_reg (t + 1)) 1306 break; 1307 1308 if (x < 0 || x > 15) 1309 break; /* Symbolic mode. */ 1310 1311 op->mode = OP_REG; 1312 op->am = 0; 1313 op->ol = 0; 1314 op->reg = x; 1315 return 0; 1316 } 1317 } 1318 while (0); 1319 1320 /* Symbolic mode 'mov a, b' == 'mov x(pc), y(pc)'. */ 1321 do 1322 { 1323 op->mode = OP_EXP; 1324 op->reg = 0; /* PC relative... be careful. */ 1325 op->am = 1; 1326 op->ol = 1; 1327 __tl = l; 1328 parse_exp (__tl, &(op->exp)); 1329 return 0; 1330 } 1331 while (0); 1332 1333 /* Unreachable. */ 1334 as_bad (_("unknown addressing mode for operand %s"), l); 1335 return 1; 1336 } 1337 1338 1339 static int 1340 msp430_dstoperand (struct msp430_operand_s * op, char * l, int bin) 1341 { 1342 int dummy; 1343 int ret = msp430_srcoperand (op, l, bin, & dummy); 1344 1345 if (ret) 1346 return ret; 1347 1348 if (op->am == 2) 1349 { 1350 char *__tl = "0"; 1351 1352 op->mode = OP_EXP; 1353 op->am = 1; 1354 op->ol = 1; 1355 parse_exp (__tl, &(op->exp)); 1356 1357 if (op->exp.X_op != O_constant || op->exp.X_add_number != 0) 1358 { 1359 as_bad (_("Internal bug. Try to use 0(r%d) instead of @r%d"), 1360 op->reg, op->reg); 1361 return 1; 1362 } 1363 return 0; 1364 } 1365 1366 if (op->am > 1) 1367 { 1368 as_bad (_ 1369 ("this addressing mode is not applicable for destination operand")); 1370 return 1; 1371 } 1372 return 0; 1373 } 1374 1375 1376 /* Parse instruction operands. 1377 Return binary opcode. */ 1378 1379 static unsigned int 1380 msp430_operands (struct msp430_opcode_s * opcode, char * line) 1381 { 1382 int bin = opcode->bin_opcode; /* Opcode mask. */ 1383 int __is = 0; 1384 char l1[MAX_OP_LEN], l2[MAX_OP_LEN]; 1385 char *frag; 1386 int where; 1387 struct msp430_operand_s op1, op2; 1388 int res = 0; 1389 static short ZEROS = 0; 1390 int byte_op, imm_op; 1391 1392 /* Opcode is the one from opcodes table 1393 line contains something like 1394 [.w] @r2+, 5(R1) 1395 or 1396 .b @r2+, 5(R1). */ 1397 1398 /* Check if byte or word operation. */ 1399 if (*line == '.' && TOLOWER (*(line + 1)) == 'b') 1400 { 1401 bin |= BYTE_OPERATION; 1402 byte_op = 1; 1403 } 1404 else 1405 byte_op = 0; 1406 1407 /* skip .[bwBW]. */ 1408 while (! ISSPACE (*line) && *line) 1409 line++; 1410 1411 if (opcode->insn_opnumb && (!*line || *line == '\n')) 1412 { 1413 as_bad (_("instruction %s requires %d operand(s)"), 1414 opcode->name, opcode->insn_opnumb); 1415 return 0; 1416 } 1417 1418 memset (l1, 0, sizeof (l1)); 1419 memset (l2, 0, sizeof (l2)); 1420 memset (&op1, 0, sizeof (op1)); 1421 memset (&op2, 0, sizeof (op2)); 1422 1423 imm_op = 0; 1424 1425 switch (opcode->fmt) 1426 { 1427 case 0: /* Emulated. */ 1428 switch (opcode->insn_opnumb) 1429 { 1430 case 0: 1431 /* Set/clear bits instructions. */ 1432 __is = 2; 1433 frag = frag_more (__is); 1434 bfd_putl16 ((bfd_vma) bin, frag); 1435 dwarf2_emit_insn (__is); 1436 break; 1437 case 1: 1438 /* Something which works with destination operand. */ 1439 line = extract_operand (line, l1, sizeof (l1)); 1440 res = msp430_dstoperand (&op1, l1, opcode->bin_opcode); 1441 if (res) 1442 break; 1443 1444 bin |= (op1.reg | (op1.am << 7)); 1445 __is = 1 + op1.ol; 1446 frag = frag_more (2 * __is); 1447 where = frag - frag_now->fr_literal; 1448 bfd_putl16 ((bfd_vma) bin, frag); 1449 dwarf2_emit_insn (2 * __is); 1450 1451 if (op1.mode == OP_EXP) 1452 { 1453 where += 2; 1454 bfd_putl16 ((bfd_vma) ZEROS, frag + 2); 1455 1456 if (op1.reg) 1457 fix_new_exp (frag_now, where, 2, 1458 &(op1.exp), FALSE, CHECK_RELOC_MSP430); 1459 else 1460 fix_new_exp (frag_now, where, 2, 1461 &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL); 1462 } 1463 break; 1464 1465 case 2: 1466 { 1467 /* Shift instruction. */ 1468 line = extract_operand (line, l1, sizeof (l1)); 1469 strncpy (l2, l1, sizeof (l2)); 1470 l2[sizeof (l2) - 1] = '\0'; 1471 res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op); 1472 res += msp430_dstoperand (&op2, l2, opcode->bin_opcode); 1473 1474 if (res) 1475 break; /* An error occurred. All warnings were done before. */ 1476 1477 bin |= (op2.reg | (op1.reg << 8) | (op1.am << 4) | (op2.am << 7)); 1478 1479 __is = 1 + op1.ol + op2.ol; /* insn size in words. */ 1480 frag = frag_more (2 * __is); 1481 where = frag - frag_now->fr_literal; 1482 bfd_putl16 ((bfd_vma) bin, frag); 1483 dwarf2_emit_insn (2 * __is); 1484 1485 if (op1.mode == OP_EXP) 1486 { 1487 where += 2; /* Advance 'where' as we do not know _where_. */ 1488 bfd_putl16 ((bfd_vma) ZEROS, frag + 2); 1489 1490 if (op1.reg || (op1.reg == 0 && op1.am == 3)) /* Not PC relative. */ 1491 fix_new_exp (frag_now, where, 2, 1492 &(op1.exp), FALSE, CHECK_RELOC_MSP430); 1493 else 1494 fix_new_exp (frag_now, where, 2, 1495 &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL); 1496 } 1497 1498 if (op2.mode == OP_EXP) 1499 { 1500 imm_op = 0; 1501 bfd_putl16 ((bfd_vma) ZEROS, frag + 2 + ((__is == 3) ? 2 : 0)); 1502 1503 if (op2.reg) /* Not PC relative. */ 1504 fix_new_exp (frag_now, where + 2, 2, 1505 &(op2.exp), FALSE, CHECK_RELOC_MSP430); 1506 else 1507 fix_new_exp (frag_now, where + 2, 2, 1508 &(op2.exp), TRUE, CHECK_RELOC_MSP430_PCREL); 1509 } 1510 break; 1511 } 1512 case 3: 1513 /* Branch instruction => mov dst, r0. */ 1514 line = extract_operand (line, l1, sizeof (l1)); 1515 1516 res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op); 1517 if (res) 1518 break; 1519 1520 byte_op = 0; 1521 imm_op = 0; 1522 1523 bin |= ((op1.reg << 8) | (op1.am << 4)); 1524 __is = 1 + op1.ol; 1525 frag = frag_more (2 * __is); 1526 where = frag - frag_now->fr_literal; 1527 bfd_putl16 ((bfd_vma) bin, frag); 1528 dwarf2_emit_insn (2 * __is); 1529 1530 if (op1.mode == OP_EXP) 1531 { 1532 where += 2; 1533 bfd_putl16 ((bfd_vma) ZEROS, frag + 2); 1534 1535 if (op1.reg || (op1.reg == 0 && op1.am == 3)) 1536 fix_new_exp (frag_now, where, 2, 1537 &(op1.exp), FALSE, CHECK_RELOC_MSP430); 1538 else 1539 fix_new_exp (frag_now, where, 2, 1540 &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL); 1541 } 1542 break; 1543 } 1544 break; 1545 1546 case 1: /* Format 1, double operand. */ 1547 line = extract_operand (line, l1, sizeof (l1)); 1548 line = extract_operand (line, l2, sizeof (l2)); 1549 res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op); 1550 res += msp430_dstoperand (&op2, l2, opcode->bin_opcode); 1551 1552 if (res) 1553 break; /* Error occurred. All warnings were done before. */ 1554 1555 bin |= (op2.reg | (op1.reg << 8) | (op1.am << 4) | (op2.am << 7)); 1556 1557 __is = 1 + op1.ol + op2.ol; /* insn size in words. */ 1558 frag = frag_more (2 * __is); 1559 where = frag - frag_now->fr_literal; 1560 bfd_putl16 ((bfd_vma) bin, frag); 1561 dwarf2_emit_insn (2 * __is); 1562 1563 if (op1.mode == OP_EXP) 1564 { 1565 where += 2; /* Advance where as we do not know _where_. */ 1566 bfd_putl16 ((bfd_vma) ZEROS, frag + 2); 1567 1568 if (op1.reg || (op1.reg == 0 && op1.am == 3)) /* Not PC relative. */ 1569 fix_new_exp (frag_now, where, 2, 1570 &(op1.exp), FALSE, CHECK_RELOC_MSP430); 1571 else 1572 fix_new_exp (frag_now, where, 2, 1573 &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL); 1574 } 1575 1576 if (op2.mode == OP_EXP) 1577 { 1578 imm_op = 0; 1579 bfd_putl16 ((bfd_vma) ZEROS, frag + 2 + ((__is == 3) ? 2 : 0)); 1580 1581 if (op2.reg) /* Not PC relative. */ 1582 fix_new_exp (frag_now, where + 2, 2, 1583 &(op2.exp), FALSE, CHECK_RELOC_MSP430); 1584 else 1585 fix_new_exp (frag_now, where + 2, 2, 1586 &(op2.exp), TRUE, CHECK_RELOC_MSP430_PCREL); 1587 } 1588 break; 1589 1590 case 2: /* Single-operand mostly instr. */ 1591 if (opcode->insn_opnumb == 0) 1592 { 1593 /* reti instruction. */ 1594 frag = frag_more (2); 1595 bfd_putl16 ((bfd_vma) bin, frag); 1596 dwarf2_emit_insn (2); 1597 break; 1598 } 1599 1600 line = extract_operand (line, l1, sizeof (l1)); 1601 res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op); 1602 if (res) 1603 break; /* Error in operand. */ 1604 1605 bin |= op1.reg | (op1.am << 4); 1606 __is = 1 + op1.ol; 1607 frag = frag_more (2 * __is); 1608 where = frag - frag_now->fr_literal; 1609 bfd_putl16 ((bfd_vma) bin, frag); 1610 dwarf2_emit_insn (2 * __is); 1611 1612 if (op1.mode == OP_EXP) 1613 { 1614 bfd_putl16 ((bfd_vma) ZEROS, frag + 2); 1615 1616 if (op1.reg || (op1.reg == 0 && op1.am == 3)) /* Not PC relative. */ 1617 fix_new_exp (frag_now, where + 2, 2, 1618 &(op1.exp), FALSE, CHECK_RELOC_MSP430); 1619 else 1620 fix_new_exp (frag_now, where + 2, 2, 1621 &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL); 1622 } 1623 break; 1624 1625 case 3: /* Conditional jumps instructions. */ 1626 line = extract_operand (line, l1, sizeof (l1)); 1627 /* l1 is a label. */ 1628 if (l1[0]) 1629 { 1630 char *m = l1; 1631 expressionS exp; 1632 1633 if (*m == '$') 1634 m++; 1635 1636 parse_exp (m, &exp); 1637 frag = frag_more (2); /* Instr size is 1 word. */ 1638 1639 /* In order to handle something like: 1640 1641 and #0x8000, r5 1642 tst r5 1643 jz 4 ; skip next 4 bytes 1644 inv r5 1645 inc r5 1646 nop ; will jump here if r5 positive or zero 1647 1648 jCOND -n ;assumes jump n bytes backward: 1649 1650 mov r5,r6 1651 jmp -2 1652 1653 is equal to: 1654 lab: 1655 mov r5,r6 1656 jmp lab 1657 1658 jCOND $n ; jump from PC in either direction. */ 1659 1660 if (exp.X_op == O_constant) 1661 { 1662 int x = exp.X_add_number; 1663 1664 if (x & 1) 1665 { 1666 as_warn (_("Even number required. Rounded to %d"), x + 1); 1667 x++; 1668 } 1669 1670 if ((*l1 == '$' && x > 0) || x < 0) 1671 x -= 2; 1672 1673 x >>= 1; 1674 1675 if (x > 512 || x < -511) 1676 { 1677 as_bad (_("Wrong displacement %d"), x << 1); 1678 break; 1679 } 1680 1681 bin |= x & 0x3ff; 1682 bfd_putl16 ((bfd_vma) bin, frag); 1683 } 1684 else if (exp.X_op == O_symbol && *l1 != '$') 1685 { 1686 where = frag - frag_now->fr_literal; 1687 fix_new_exp (frag_now, where, 2, 1688 &exp, TRUE, BFD_RELOC_MSP430_10_PCREL); 1689 1690 bfd_putl16 ((bfd_vma) bin, frag); 1691 } 1692 else if (*l1 == '$') 1693 { 1694 as_bad (_("instruction requires label sans '$'")); 1695 } 1696 else 1697 { 1698 as_bad (_ 1699 ("instruction requires label or value in range -511:512")); 1700 } 1701 dwarf2_emit_insn (2 * __is); 1702 break; 1703 } 1704 else 1705 { 1706 as_bad (_("instruction requires label")); 1707 break; 1708 } 1709 break; 1710 1711 case 4: /* Extended jumps. */ 1712 if (!msp430_enable_polys) 1713 { 1714 as_bad (_("polymorphs are not enabled. Use -mP option to enable.")); 1715 break; 1716 } 1717 1718 line = extract_operand (line, l1, sizeof (l1)); 1719 if (l1[0]) 1720 { 1721 char *m = l1; 1722 expressionS exp; 1723 1724 /* Ignore absolute addressing. make it PC relative anyway. */ 1725 if (*m == '#' || *m == '$') 1726 m++; 1727 1728 parse_exp (m, & exp); 1729 if (exp.X_op == O_symbol) 1730 { 1731 /* Relaxation required. */ 1732 struct rcodes_s rc = msp430_rcodes[opcode->insn_opnumb]; 1733 1734 /* The parameter to dwarf2_emit_insn is actually the offset to the start 1735 of the insn from the fix piece of instruction that was emitted. 1736 Since next fragments may have variable size we tie debug info 1737 to the beginning of the instruction. */ 1738 frag = frag_more (8); 1739 dwarf2_emit_insn (0); 1740 bfd_putl16 ((bfd_vma) rc.sop, frag); 1741 frag = frag_variant (rs_machine_dependent, 8, 2, 1742 ENCODE_RELAX (rc.lpos, STATE_BITS10), /* Wild guess. */ 1743 exp.X_add_symbol, 1744 0, /* Offset is zero if jump dist less than 1K. */ 1745 (char *) frag); 1746 break; 1747 } 1748 } 1749 1750 as_bad (_("instruction requires label")); 1751 break; 1752 1753 case 5: /* Emulated extended branches. */ 1754 if (!msp430_enable_polys) 1755 { 1756 as_bad (_("polymorphs are not enabled. Use -mP option to enable.")); 1757 break; 1758 } 1759 line = extract_operand (line, l1, sizeof (l1)); 1760 if (l1[0]) 1761 { 1762 char * m = l1; 1763 expressionS exp; 1764 1765 /* Ignore absolute addressing. make it PC relative anyway. */ 1766 if (*m == '#' || *m == '$') 1767 m++; 1768 1769 parse_exp (m, & exp); 1770 if (exp.X_op == O_symbol) 1771 { 1772 /* Relaxation required. */ 1773 struct hcodes_s hc = msp430_hcodes[opcode->insn_opnumb]; 1774 1775 frag = frag_more (8); 1776 dwarf2_emit_insn (0); 1777 bfd_putl16 ((bfd_vma) hc.op0, frag); 1778 bfd_putl16 ((bfd_vma) hc.op1, frag+2); 1779 1780 frag = frag_variant (rs_machine_dependent, 8, 2, 1781 ENCODE_RELAX (STATE_EMUL_BRANCH, STATE_BITS10), /* Wild guess. */ 1782 exp.X_add_symbol, 1783 0, /* Offset is zero if jump dist less than 1K. */ 1784 (char *) frag); 1785 break; 1786 } 1787 } 1788 1789 as_bad (_("instruction requires label")); 1790 break; 1791 1792 default: 1793 as_bad (_("Illegal instruction or not implemented opcode.")); 1794 } 1795 1796 input_line_pointer = line; 1797 return 0; 1798 } 1799 1800 void 1801 md_assemble (char * str) 1802 { 1803 struct msp430_opcode_s * opcode; 1804 char cmd[32]; 1805 unsigned int i = 0; 1806 1807 str = skip_space (str); /* Skip leading spaces. */ 1808 str = extract_cmd (str, cmd, sizeof (cmd)); 1809 1810 while (cmd[i] && i < sizeof (cmd)) 1811 { 1812 char a = TOLOWER (cmd[i]); 1813 cmd[i] = a; 1814 i++; 1815 } 1816 1817 if (!cmd[0]) 1818 { 1819 as_bad (_("can't find opcode ")); 1820 return; 1821 } 1822 1823 opcode = (struct msp430_opcode_s *) hash_find (msp430_hash, cmd); 1824 1825 if (opcode == NULL) 1826 { 1827 as_bad (_("unknown opcode `%s'"), cmd); 1828 return; 1829 } 1830 1831 { 1832 char *__t = input_line_pointer; 1833 1834 msp430_operands (opcode, str); 1835 input_line_pointer = __t; 1836 } 1837 } 1838 1839 /* GAS will call this function for each section at the end of the assembly, 1840 to permit the CPU backend to adjust the alignment of a section. */ 1841 1842 valueT 1843 md_section_align (asection * seg, valueT addr) 1844 { 1845 int align = bfd_get_section_alignment (stdoutput, seg); 1846 1847 return ((addr + (1 << align) - 1) & (-1 << align)); 1848 } 1849 1850 /* If you define this macro, it should return the offset between the 1851 address of a PC relative fixup and the position from which the PC 1852 relative adjustment should be made. On many processors, the base 1853 of a PC relative instruction is the next instruction, so this 1854 macro would return the length of an instruction. */ 1855 1856 long 1857 md_pcrel_from_section (fixS * fixp, segT sec) 1858 { 1859 if (fixp->fx_addsy != (symbolS *) NULL 1860 && (!S_IS_DEFINED (fixp->fx_addsy) 1861 || (S_GET_SEGMENT (fixp->fx_addsy) != sec))) 1862 return 0; 1863 1864 return fixp->fx_frag->fr_address + fixp->fx_where; 1865 } 1866 1867 /* Replaces standard TC_FORCE_RELOCATION_LOCAL. 1868 Now it handles the situation when relocations 1869 have to be passed to linker. */ 1870 int 1871 msp430_force_relocation_local(fixS *fixp) 1872 { 1873 if (msp430_enable_polys 1874 && !msp430_enable_relax) 1875 return 1; 1876 else 1877 return (!fixp->fx_pcrel 1878 || generic_force_reloc(fixp)); 1879 } 1880 1881 1882 /* GAS will call this for each fixup. It should store the correct 1883 value in the object file. */ 1884 void 1885 md_apply_fix (fixS * fixp, valueT * valuep, segT seg) 1886 { 1887 unsigned char * where; 1888 unsigned long insn; 1889 long value; 1890 1891 if (fixp->fx_addsy == (symbolS *) NULL) 1892 { 1893 value = *valuep; 1894 fixp->fx_done = 1; 1895 } 1896 else if (fixp->fx_pcrel) 1897 { 1898 segT s = S_GET_SEGMENT (fixp->fx_addsy); 1899 1900 if (fixp->fx_addsy && (s == seg || s == absolute_section)) 1901 { 1902 /* FIXME: We can appear here only in case if we perform a pc 1903 relative jump to the label which is i) global, ii) locally 1904 defined or this is a jump to an absolute symbol. 1905 If this is an absolute symbol -- everything is OK. 1906 If this is a global label, we've got a symbol value defined 1907 twice: 1908 1. S_GET_VALUE (fixp->fx_addsy) will contain a symbol offset 1909 from this section start 1910 2. *valuep will contain the real offset from jump insn to the 1911 label 1912 So, the result of S_GET_VALUE (fixp->fx_addsy) + (* valuep); 1913 will be incorrect. Therefore remove s_get_value. */ 1914 value = /* S_GET_VALUE (fixp->fx_addsy) + */ * valuep; 1915 fixp->fx_done = 1; 1916 } 1917 else 1918 value = *valuep; 1919 } 1920 else 1921 { 1922 value = fixp->fx_offset; 1923 1924 if (fixp->fx_subsy != (symbolS *) NULL) 1925 { 1926 if (S_GET_SEGMENT (fixp->fx_subsy) == absolute_section) 1927 { 1928 value -= S_GET_VALUE (fixp->fx_subsy); 1929 fixp->fx_done = 1; 1930 } 1931 else 1932 { 1933 /* We don't actually support subtracting a symbol. */ 1934 as_bad_where (fixp->fx_file, fixp->fx_line, 1935 _("expression too complex")); 1936 } 1937 } 1938 } 1939 1940 fixp->fx_no_overflow = 1; 1941 1942 /* if polymorphs are enabled and relax disabled. 1943 do not kill any relocs and pass them to linker. */ 1944 if (msp430_enable_polys 1945 && !msp430_enable_relax) 1946 { 1947 if (!fixp->fx_addsy || (fixp->fx_addsy 1948 && S_GET_SEGMENT (fixp->fx_addsy) == absolute_section)) 1949 fixp->fx_done = 1; /* It is ok to kill 'abs' reloc. */ 1950 else 1951 fixp->fx_done = 0; 1952 } 1953 1954 if (fixp->fx_done) 1955 { 1956 /* Fetch the instruction, insert the fully resolved operand 1957 value, and stuff the instruction back again. */ 1958 1959 where = (unsigned char *) fixp->fx_frag->fr_literal + fixp->fx_where; 1960 1961 insn = bfd_getl16 (where); 1962 1963 switch (fixp->fx_r_type) 1964 { 1965 case BFD_RELOC_MSP430_10_PCREL: 1966 if (value & 1) 1967 as_bad_where (fixp->fx_file, fixp->fx_line, 1968 _("odd address operand: %ld"), value); 1969 1970 /* Jumps are in words. */ 1971 value >>= 1; 1972 --value; /* Correct PC. */ 1973 1974 if (value < -512 || value > 511) 1975 as_bad_where (fixp->fx_file, fixp->fx_line, 1976 _("operand out of range: %ld"), value); 1977 1978 value &= 0x3ff; /* get rid of extended sign */ 1979 bfd_putl16 ((bfd_vma) (value | insn), where); 1980 break; 1981 1982 case BFD_RELOC_MSP430_RL_PCREL: 1983 case BFD_RELOC_MSP430_16_PCREL: 1984 if (value & 1) 1985 as_bad_where (fixp->fx_file, fixp->fx_line, 1986 _("odd address operand: %ld"), value); 1987 1988 /* Nothing to be corrected here. */ 1989 if (value < -32768 || value > 65536) 1990 as_bad_where (fixp->fx_file, fixp->fx_line, 1991 _("operand out of range: %ld"), value); 1992 1993 value &= 0xffff; /* Get rid of extended sign. */ 1994 bfd_putl16 ((bfd_vma) value, where); 1995 break; 1996 1997 case BFD_RELOC_MSP430_16_PCREL_BYTE: 1998 /* Nothing to be corrected here. */ 1999 if (value < -32768 || value > 65536) 2000 as_bad_where (fixp->fx_file, fixp->fx_line, 2001 _("operand out of range: %ld"), value); 2002 2003 value &= 0xffff; /* Get rid of extended sign. */ 2004 bfd_putl16 ((bfd_vma) value, where); 2005 break; 2006 2007 case BFD_RELOC_32: 2008 bfd_putl16 ((bfd_vma) value, where); 2009 break; 2010 2011 case BFD_RELOC_MSP430_16: 2012 case BFD_RELOC_16: 2013 case BFD_RELOC_MSP430_16_BYTE: 2014 value &= 0xffff; 2015 bfd_putl16 ((bfd_vma) value, where); 2016 break; 2017 2018 default: 2019 as_fatal (_("line %d: unknown relocation type: 0x%x"), 2020 fixp->fx_line, fixp->fx_r_type); 2021 break; 2022 } 2023 } 2024 else 2025 { 2026 fixp->fx_addnumber = value; 2027 } 2028 } 2029 2030 /* GAS will call this to generate a reloc, passing the resulting reloc 2031 to `bfd_install_relocation'. This currently works poorly, as 2032 `bfd_install_relocation' often does the wrong thing, and instances of 2033 `tc_gen_reloc' have been written to work around the problems, which 2034 in turns makes it difficult to fix `bfd_install_relocation'. */ 2035 2036 /* If while processing a fixup, a reloc really needs to be created 2037 then it is done here. */ 2038 2039 arelent * 2040 tc_gen_reloc (asection * seg ATTRIBUTE_UNUSED, fixS * fixp) 2041 { 2042 arelent * reloc; 2043 2044 reloc = xmalloc (sizeof (arelent)); 2045 2046 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); 2047 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 2048 2049 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 2050 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); 2051 if (reloc->howto == (reloc_howto_type *) NULL) 2052 { 2053 as_bad_where (fixp->fx_file, fixp->fx_line, 2054 _("reloc %d not supported by object file format"), 2055 (int) fixp->fx_r_type); 2056 return NULL; 2057 } 2058 2059 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT 2060 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 2061 reloc->address = fixp->fx_offset; 2062 2063 reloc->addend = fixp->fx_offset; 2064 2065 return reloc; 2066 } 2067 2068 int 2069 md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED, 2070 asection * segment_type ATTRIBUTE_UNUSED) 2071 { 2072 if (fragP->fr_symbol && S_GET_SEGMENT (fragP->fr_symbol) == segment_type) 2073 { 2074 /* This is a jump -> pcrel mode. Nothing to do much here. 2075 Return value == 2. */ 2076 fragP->fr_subtype = 2077 ENCODE_RELAX (RELAX_LEN (fragP->fr_subtype), STATE_BITS10); 2078 } 2079 else if (fragP->fr_symbol) 2080 { 2081 /* Its got a segment, but its not ours. Even if fr_symbol is in 2082 an absolute segment, we don't know a displacement until we link 2083 object files. So it will always be long. This also applies to 2084 labels in a subsegment of current. Liker may relax it to short 2085 jump later. Return value == 8. */ 2086 fragP->fr_subtype = 2087 ENCODE_RELAX (RELAX_LEN (fragP->fr_subtype), STATE_WORD); 2088 } 2089 else 2090 { 2091 /* We know the abs value. may be it is a jump to fixed address. 2092 Impossible in our case, cause all constants already handled. */ 2093 fragP->fr_subtype = 2094 ENCODE_RELAX (RELAX_LEN (fragP->fr_subtype), STATE_UNDEF); 2095 } 2096 2097 return md_relax_table[fragP->fr_subtype].rlx_length; 2098 } 2099 2100 void 2101 md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED, 2102 asection * sec ATTRIBUTE_UNUSED, 2103 fragS * fragP) 2104 { 2105 char * where = 0; 2106 int rela = -1; 2107 int i; 2108 struct rcodes_s * cc = NULL; 2109 struct hcodes_s * hc = NULL; 2110 2111 switch (fragP->fr_subtype) 2112 { 2113 case ENCODE_RELAX (STATE_UNCOND_BRANCH, STATE_BITS10): 2114 case ENCODE_RELAX (STATE_SIMPLE_BRANCH, STATE_BITS10): 2115 case ENCODE_RELAX (STATE_NOOV_BRANCH, STATE_BITS10): 2116 /* We do not have to convert anything here. 2117 Just apply a fix. */ 2118 rela = BFD_RELOC_MSP430_10_PCREL; 2119 break; 2120 2121 case ENCODE_RELAX (STATE_UNCOND_BRANCH, STATE_WORD): 2122 case ENCODE_RELAX (STATE_UNCOND_BRANCH, STATE_UNDEF): 2123 /* Convert uncond branch jmp lab -> br lab. */ 2124 cc = & msp430_rcodes[7]; 2125 where = fragP->fr_literal + fragP->fr_fix; 2126 bfd_putl16 (cc->lop0, where); 2127 rela = BFD_RELOC_MSP430_RL_PCREL; 2128 fragP->fr_fix += 2; 2129 break; 2130 2131 case ENCODE_RELAX (STATE_SIMPLE_BRANCH, STATE_WORD): 2132 case ENCODE_RELAX (STATE_SIMPLE_BRANCH, STATE_UNDEF): 2133 { 2134 /* Other simple branches. */ 2135 int insn = bfd_getl16 (fragP->fr_opcode); 2136 2137 insn &= 0xffff; 2138 /* Find actual instruction. */ 2139 for (i = 0; i < 7 && !cc; i++) 2140 if (msp430_rcodes[i].sop == insn) 2141 cc = & msp430_rcodes[i]; 2142 if (!cc || !cc->name) 2143 as_fatal (_("internal inconsistency problem in %s: insn %04lx"), 2144 __FUNCTION__, (long) insn); 2145 where = fragP->fr_literal + fragP->fr_fix; 2146 bfd_putl16 (cc->lop0, where); 2147 bfd_putl16 (cc->lop1, where + 2); 2148 rela = BFD_RELOC_MSP430_RL_PCREL; 2149 fragP->fr_fix += 4; 2150 } 2151 break; 2152 2153 case ENCODE_RELAX (STATE_NOOV_BRANCH, STATE_WORD): 2154 case ENCODE_RELAX (STATE_NOOV_BRANCH, STATE_UNDEF): 2155 cc = & msp430_rcodes[6]; 2156 where = fragP->fr_literal + fragP->fr_fix; 2157 bfd_putl16 (cc->lop0, where); 2158 bfd_putl16 (cc->lop1, where + 2); 2159 bfd_putl16 (cc->lop2, where + 4); 2160 rela = BFD_RELOC_MSP430_RL_PCREL; 2161 fragP->fr_fix += 6; 2162 break; 2163 2164 case ENCODE_RELAX (STATE_EMUL_BRANCH, STATE_BITS10): 2165 { 2166 int insn = bfd_getl16 (fragP->fr_opcode + 2); 2167 2168 insn &= 0xffff; 2169 for (i = 0; i < 4 && !hc; i++) 2170 if (msp430_hcodes[i].op1 == insn) 2171 hc = &msp430_hcodes[i]; 2172 if (!hc || !hc->name) 2173 as_fatal (_("internal inconsistency problem in %s: ext. insn %04lx"), 2174 __FUNCTION__, (long) insn); 2175 rela = BFD_RELOC_MSP430_10_PCREL; 2176 /* Apply a fix for a first label if necessary. 2177 another fix will be applied to the next word of insn anyway. */ 2178 if (hc->tlab == 2) 2179 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 2180 fragP->fr_offset, TRUE, rela); 2181 fragP->fr_fix += 2; 2182 } 2183 2184 break; 2185 2186 case ENCODE_RELAX (STATE_EMUL_BRANCH, STATE_WORD): 2187 case ENCODE_RELAX (STATE_EMUL_BRANCH, STATE_UNDEF): 2188 { 2189 int insn = bfd_getl16 (fragP->fr_opcode + 2); 2190 2191 insn &= 0xffff; 2192 for (i = 0; i < 4 && !hc; i++) 2193 if (msp430_hcodes[i].op1 == insn) 2194 hc = & msp430_hcodes[i]; 2195 if (!hc || !hc->name) 2196 as_fatal (_("internal inconsistency problem in %s: ext. insn %04lx"), 2197 __FUNCTION__, (long) insn); 2198 rela = BFD_RELOC_MSP430_RL_PCREL; 2199 where = fragP->fr_literal + fragP->fr_fix; 2200 bfd_putl16 (hc->lop0, where); 2201 bfd_putl16 (hc->lop1, where + 2); 2202 bfd_putl16 (hc->lop2, where + 4); 2203 fragP->fr_fix += 6; 2204 } 2205 break; 2206 2207 default: 2208 as_fatal (_("internal inconsistency problem in %s: %lx"), 2209 __FUNCTION__, (long) fragP->fr_subtype); 2210 break; 2211 } 2212 2213 /* Now apply fix. */ 2214 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 2215 fragP->fr_offset, TRUE, rela); 2216 /* Just fixed 2 bytes. */ 2217 fragP->fr_fix += 2; 2218 } 2219 2220 /* Relax fragment. Mostly stolen from hc11 and mcore 2221 which arches I think I know. */ 2222 2223 long 2224 msp430_relax_frag (segT seg ATTRIBUTE_UNUSED, fragS * fragP, 2225 long stretch ATTRIBUTE_UNUSED) 2226 { 2227 long growth; 2228 offsetT aim = 0; 2229 symbolS *symbolP; 2230 const relax_typeS *this_type; 2231 const relax_typeS *start_type; 2232 relax_substateT next_state; 2233 relax_substateT this_state; 2234 const relax_typeS *table = md_relax_table; 2235 2236 /* Nothing to be done if the frag has already max size. */ 2237 if (RELAX_STATE (fragP->fr_subtype) == STATE_UNDEF 2238 || RELAX_STATE (fragP->fr_subtype) == STATE_WORD) 2239 return 0; 2240 2241 if (RELAX_STATE (fragP->fr_subtype) == STATE_BITS10) 2242 { 2243 symbolP = fragP->fr_symbol; 2244 if (symbol_resolved_p (symbolP)) 2245 as_fatal (_("internal inconsistency problem in %s: resolved symbol"), 2246 __FUNCTION__); 2247 /* We know the offset. calculate a distance. */ 2248 aim = S_GET_VALUE (symbolP) - fragP->fr_address - fragP->fr_fix; 2249 } 2250 2251 if (!msp430_enable_relax) 2252 { 2253 /* Relaxation is not enabled. So, make all jump as long ones 2254 by setting 'aim' to quite high value. */ 2255 aim = 0x7fff; 2256 } 2257 2258 this_state = fragP->fr_subtype; 2259 start_type = this_type = table + this_state; 2260 2261 if (aim < 0) 2262 { 2263 /* Look backwards. */ 2264 for (next_state = this_type->rlx_more; next_state;) 2265 if (aim >= this_type->rlx_backward || !this_type->rlx_backward) 2266 next_state = 0; 2267 else 2268 { 2269 /* Grow to next state. */ 2270 this_state = next_state; 2271 this_type = table + this_state; 2272 next_state = this_type->rlx_more; 2273 } 2274 } 2275 else 2276 { 2277 /* Look forwards. */ 2278 for (next_state = this_type->rlx_more; next_state;) 2279 if (aim <= this_type->rlx_forward || !this_type->rlx_forward) 2280 next_state = 0; 2281 else 2282 { 2283 /* Grow to next state. */ 2284 this_state = next_state; 2285 this_type = table + this_state; 2286 next_state = this_type->rlx_more; 2287 } 2288 } 2289 2290 growth = this_type->rlx_length - start_type->rlx_length; 2291 if (growth != 0) 2292 fragP->fr_subtype = this_state; 2293 return growth; 2294 } 2295
Indexes created Mon Mar 30 00:23:01 UTC 2026