tc-sparc.c revision 1.1.1.2.8.1
1 /* tc-sparc.c -- Assemble for the SPARC 2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 4 2011 5 Free Software Foundation, Inc. 6 This file is part of GAS, the GNU Assembler. 7 8 GAS is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 GAS is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public 19 License along with GAS; see the file COPYING. If not, write 20 to the Free Software Foundation, 51 Franklin Street - Fifth Floor, 21 Boston, MA 02110-1301, USA. */ 22 23 #include "as.h" 24 #include "safe-ctype.h" 25 #include "subsegs.h" 26 27 #include "opcode/sparc.h" 28 #include "dw2gencfi.h" 29 30 #ifdef OBJ_ELF 31 #include "elf/sparc.h" 32 #include "dwarf2dbg.h" 33 #endif 34 35 /* Some ancient Sun C compilers would not take such hex constants as 36 unsigned, and would end up sign-extending them to form an offsetT, 37 so use these constants instead. */ 38 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1) 39 #define U0x80000000 ((((unsigned long) 1 << 16) << 15)) 40 41 static int sparc_ip (char *, const struct sparc_opcode **); 42 static int parse_keyword_arg (int (*) (const char *), char **, int *); 43 static int parse_const_expr_arg (char **, int *); 44 static int get_expression (char *); 45 46 /* Default architecture. */ 47 /* ??? The default value should be V8, but sparclite support was added 48 by making it the default. GCC now passes -Asparclite, so maybe sometime in 49 the future we can set this to V8. */ 50 #ifndef DEFAULT_ARCH 51 #define DEFAULT_ARCH "sparclite" 52 #endif 53 static char *default_arch = DEFAULT_ARCH; 54 55 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size' 56 have been set. */ 57 static int default_init_p; 58 59 /* Current architecture. We don't bump up unless necessary. */ 60 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6; 61 62 /* The maximum architecture level we can bump up to. 63 In a 32 bit environment, don't allow bumping up to v9 by default. 64 The native assembler works this way. The user is required to pass 65 an explicit argument before we'll create v9 object files. However, if 66 we don't see any v9 insns, a v8plus object file is not created. */ 67 static enum sparc_opcode_arch_val max_architecture; 68 69 /* Either 32 or 64, selects file format. */ 70 static int sparc_arch_size; 71 /* Initial (default) value, recorded separately in case a user option 72 changes the value before md_show_usage is called. */ 73 static int default_arch_size; 74 75 #ifdef OBJ_ELF 76 /* The currently selected v9 memory model. Currently only used for 77 ELF. */ 78 static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO; 79 80 #ifndef TE_SOLARIS 81 /* Bitmask of instruction types seen so far, used to populate the 82 GNU attributes section with hwcap information. */ 83 static int hwcap_seen; 84 #endif 85 #endif 86 87 static int hwcap_allowed; 88 89 static int architecture_requested; 90 static int warn_on_bump; 91 92 /* If warn_on_bump and the needed architecture is higher than this 93 architecture, issue a warning. */ 94 static enum sparc_opcode_arch_val warn_after_architecture; 95 96 /* Non-zero if as should generate error if an undeclared g[23] register 97 has been used in -64. */ 98 static int no_undeclared_regs; 99 100 /* Non-zero if we should try to relax jumps and calls. */ 101 static int sparc_relax; 102 103 /* Non-zero if we are generating PIC code. */ 104 int sparc_pic_code; 105 106 /* Non-zero if we should give an error when misaligned data is seen. */ 107 static int enforce_aligned_data; 108 109 extern int target_big_endian; 110 111 static int target_little_endian_data; 112 113 /* Symbols for global registers on v9. */ 114 static symbolS *globals[8]; 115 116 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ 117 int sparc_cie_data_alignment; 118 119 /* V9 and 86x have big and little endian data, but instructions are always big 120 endian. The sparclet has bi-endian support but both data and insns have 121 the same endianness. Global `target_big_endian' is used for data. 122 The following macro is used for instructions. */ 123 #ifndef INSN_BIG_ENDIAN 124 #define INSN_BIG_ENDIAN (target_big_endian \ 125 || default_arch_type == sparc86x \ 126 || SPARC_OPCODE_ARCH_V9_P (max_architecture)) 127 #endif 128 129 /* Handle of the OPCODE hash table. */ 130 static struct hash_control *op_hash; 131 132 static void s_data1 (void); 133 static void s_seg (int); 134 static void s_proc (int); 135 static void s_reserve (int); 136 static void s_common (int); 137 static void s_empty (int); 138 static void s_uacons (int); 139 static void s_ncons (int); 140 #ifdef OBJ_ELF 141 static void s_register (int); 142 #endif 143 144 const pseudo_typeS md_pseudo_table[] = 145 { 146 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */ 147 {"common", s_common, 0}, 148 {"empty", s_empty, 0}, 149 {"global", s_globl, 0}, 150 {"half", cons, 2}, 151 {"nword", s_ncons, 0}, 152 {"optim", s_ignore, 0}, 153 {"proc", s_proc, 0}, 154 {"reserve", s_reserve, 0}, 155 {"seg", s_seg, 0}, 156 {"skip", s_space, 0}, 157 {"word", cons, 4}, 158 {"xword", cons, 8}, 159 {"uahalf", s_uacons, 2}, 160 {"uaword", s_uacons, 4}, 161 {"uaxword", s_uacons, 8}, 162 #ifdef OBJ_ELF 163 /* These are specific to sparc/svr4. */ 164 {"2byte", s_uacons, 2}, 165 {"4byte", s_uacons, 4}, 166 {"8byte", s_uacons, 8}, 167 {"register", s_register, 0}, 168 #endif 169 {NULL, 0, 0}, 170 }; 171 172 /* This array holds the chars that always start a comment. If the 173 pre-processor is disabled, these aren't very useful. */ 174 const char comment_chars[] = "!"; /* JF removed '|' from 175 comment_chars. */ 176 177 /* This array holds the chars that only start a comment at the beginning of 178 a line. If the line seems to have the form '# 123 filename' 179 .line and .file directives will appear in the pre-processed output. */ 180 /* Note that input_file.c hand checks for '#' at the beginning of the 181 first line of the input file. This is because the compiler outputs 182 #NO_APP at the beginning of its output. */ 183 /* Also note that comments started like this one will always 184 work if '/' isn't otherwise defined. */ 185 const char line_comment_chars[] = "#"; 186 187 const char line_separator_chars[] = ";"; 188 189 /* Chars that can be used to separate mant from exp in floating point 190 nums. */ 191 const char EXP_CHARS[] = "eE"; 192 193 /* Chars that mean this number is a floating point constant. 194 As in 0f12.456 195 or 0d1.2345e12 */ 196 const char FLT_CHARS[] = "rRsSfFdDxXpP"; 197 198 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be 199 changed in read.c. Ideally it shouldn't have to know about it at all, 200 but nothing is ideal around here. */ 201 202 #define isoctal(c) ((unsigned) ((c) - '0') < 8) 203 204 struct sparc_it 205 { 206 char *error; 207 unsigned long opcode; 208 struct nlist *nlistp; 209 expressionS exp; 210 expressionS exp2; 211 int pcrel; 212 bfd_reloc_code_real_type reloc; 213 }; 214 215 struct sparc_it the_insn, set_insn; 216 217 static void output_insn (const struct sparc_opcode *, struct sparc_it *); 218 219 /* Table of arguments to -A. 221 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect 222 for this use. That table is for opcodes only. This table is for opcodes 223 and file formats. */ 224 225 enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus, 226 v8plusa, v9, v9a, v9b, v9_64}; 227 228 static struct sparc_arch { 229 char *name; 230 char *opcode_arch; 231 enum sparc_arch_types arch_type; 232 /* Default word size, as specified during configuration. 233 A value of zero means can't be used to specify default architecture. */ 234 int default_arch_size; 235 /* Allowable arg to -A? */ 236 int user_option_p; 237 int hwcap_allowed; 238 } sparc_arch_table[] = { 239 { "v6", "v6", v6, 0, 1, 0 }, 240 { "v7", "v7", v7, 0, 1, 0 }, 241 { "v8", "v8", v8, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD }, 242 { "v8a", "v8", v8, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD }, 243 { "sparc", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS }, 244 { "sparcvis", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS }, 245 { "sparcvis2", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2 }, 246 { "sparcfmaf", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF }, 247 { "sparcima", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_IMA }, 248 { "sparcvis3", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC }, 249 { "sparc4", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE }, 250 { "sparcvis3r", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU }, 251 { "sparclet", "sparclet", sparclet, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD }, 252 { "sparclite", "sparclite", sparclite, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD }, 253 { "sparc86x", "sparclite", sparc86x, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD }, 254 { "v8plus", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS }, 255 { "v8plusa", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS }, 256 { "v8plusb", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2 }, 257 { "v8plusc", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT }, 258 { "v8plusd", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC }, 259 { "v8pluse", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE }, 260 { "v8plusv", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_ASI_CACHE_SPARING|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE }, 261 { "v9", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC }, 262 { "v9a", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS }, 263 { "v9b", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2 }, 264 { "v9c", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT }, 265 { "v9d", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC }, 266 { "v9e", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE }, 267 { "v9v", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_ASI_CACHE_SPARING|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE }, 268 /* This exists to allow configure.in/Makefile.in to pass one 269 value to specify both the default machine and default word size. */ 270 { "v9-64", "v9", v9, 64, 0, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC }, 271 { NULL, NULL, v8, 0, 0, 0 } 272 }; 273 274 /* Variant of default_arch */ 275 static enum sparc_arch_types default_arch_type; 276 277 static struct sparc_arch * 278 lookup_arch (char *name) 279 { 280 struct sparc_arch *sa; 281 282 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++) 283 if (strcmp (sa->name, name) == 0) 284 break; 285 if (sa->name == NULL) 286 return NULL; 287 return sa; 288 } 289 290 /* Initialize the default opcode arch and word size from the default 291 architecture name. */ 292 293 static void 294 init_default_arch (void) 295 { 296 struct sparc_arch *sa = lookup_arch (default_arch); 297 298 if (sa == NULL 299 || sa->default_arch_size == 0) 300 as_fatal (_("Invalid default architecture, broken assembler.")); 301 302 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch); 303 if (max_architecture == SPARC_OPCODE_ARCH_BAD) 304 as_fatal (_("Bad opcode table, broken assembler.")); 305 default_arch_size = sparc_arch_size = sa->default_arch_size; 306 default_init_p = 1; 307 default_arch_type = sa->arch_type; 308 } 309 310 /* Called by TARGET_FORMAT. */ 311 312 const char * 313 sparc_target_format (void) 314 { 315 /* We don't get a chance to initialize anything before we're called, 316 so handle that now. */ 317 if (! default_init_p) 318 init_default_arch (); 319 320 #ifdef OBJ_AOUT 321 #ifdef TE_NetBSD 322 return "a.out-sparc-netbsd"; 323 #else 324 #ifdef TE_SPARCAOUT 325 if (target_big_endian) 326 return "a.out-sunos-big"; 327 else if (default_arch_type == sparc86x && target_little_endian_data) 328 return "a.out-sunos-big"; 329 else 330 return "a.out-sparc-little"; 331 #else 332 return "a.out-sunos-big"; 333 #endif 334 #endif 335 #endif 336 337 #ifdef OBJ_BOUT 338 return "b.out.big"; 339 #endif 340 341 #ifdef OBJ_COFF 342 #ifdef TE_LYNX 343 return "coff-sparc-lynx"; 344 #else 345 return "coff-sparc"; 346 #endif 347 #endif 348 349 #ifdef TE_VXWORKS 350 return "elf32-sparc-vxworks"; 351 #endif 352 353 #ifdef OBJ_ELF 354 return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT; 355 #endif 356 357 abort (); 358 } 359 360 /* md_parse_option 362 * Invocation line includes a switch not recognized by the base assembler. 363 * See if it's a processor-specific option. These are: 364 * 365 * -bump 366 * Warn on architecture bumps. See also -A. 367 * 368 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet 369 * Standard 32 bit architectures. 370 * -Av9, -Av9a, -Av9b 371 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which). 372 * This used to only mean 64 bits, but properly specifying it 373 * complicated gcc's ASM_SPECs, so now opcode selection is 374 * specified orthogonally to word size (except when specifying 375 * the default, but that is an internal implementation detail). 376 * -Av8plus, -Av8plusa, -Av8plusb 377 * Same as -Av9{,a,b}. 378 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb 379 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's 380 * assembler. 381 * -xarch=v9, -xarch=v9a, -xarch=v9b 382 * Same as -Av9{,a,b} -64, for compatibility with Sun's 383 * assembler. 384 * 385 * Select the architecture and possibly the file format. 386 * Instructions or features not supported by the selected 387 * architecture cause fatal errors. 388 * 389 * The default is to start at v6, and bump the architecture up 390 * whenever an instruction is seen at a higher level. In 32 bit 391 * environments, v9 is not bumped up to, the user must pass 392 * -Av8plus{,a,b}. 393 * 394 * If -bump is specified, a warning is printing when bumping to 395 * higher levels. 396 * 397 * If an architecture is specified, all instructions must match 398 * that architecture. Any higher level instructions are flagged 399 * as errors. Note that in the 32 bit environment specifying 400 * -Av8plus does not automatically create a v8plus object file, a 401 * v9 insn must be seen. 402 * 403 * If both an architecture and -bump are specified, the 404 * architecture starts at the specified level, but bumps are 405 * warnings. Note that we can't set `current_architecture' to 406 * the requested level in this case: in the 32 bit environment, 407 * we still must avoid creating v8plus object files unless v9 408 * insns are seen. 409 * 410 * Note: 411 * Bumping between incompatible architectures is always an 412 * error. For example, from sparclite to v9. 413 */ 414 415 #ifdef OBJ_ELF 416 const char *md_shortopts = "A:K:VQ:sq"; 417 #else 418 #ifdef OBJ_AOUT 419 const char *md_shortopts = "A:k"; 420 #else 421 const char *md_shortopts = "A:"; 422 #endif 423 #endif 424 struct option md_longopts[] = { 425 #define OPTION_BUMP (OPTION_MD_BASE) 426 {"bump", no_argument, NULL, OPTION_BUMP}, 427 #define OPTION_SPARC (OPTION_MD_BASE + 1) 428 {"sparc", no_argument, NULL, OPTION_SPARC}, 429 #define OPTION_XARCH (OPTION_MD_BASE + 2) 430 {"xarch", required_argument, NULL, OPTION_XARCH}, 431 #ifdef OBJ_ELF 432 #define OPTION_32 (OPTION_MD_BASE + 3) 433 {"32", no_argument, NULL, OPTION_32}, 434 #define OPTION_64 (OPTION_MD_BASE + 4) 435 {"64", no_argument, NULL, OPTION_64}, 436 #define OPTION_TSO (OPTION_MD_BASE + 5) 437 {"TSO", no_argument, NULL, OPTION_TSO}, 438 #define OPTION_PSO (OPTION_MD_BASE + 6) 439 {"PSO", no_argument, NULL, OPTION_PSO}, 440 #define OPTION_RMO (OPTION_MD_BASE + 7) 441 {"RMO", no_argument, NULL, OPTION_RMO}, 442 #endif 443 #ifdef SPARC_BIENDIAN 444 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8) 445 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN}, 446 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9) 447 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN}, 448 #endif 449 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10) 450 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA}, 451 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11) 452 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA}, 453 #ifdef OBJ_ELF 454 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12) 455 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS}, 456 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13) 457 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS}, 458 #endif 459 #define OPTION_RELAX (OPTION_MD_BASE + 14) 460 {"relax", no_argument, NULL, OPTION_RELAX}, 461 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15) 462 {"no-relax", no_argument, NULL, OPTION_NO_RELAX}, 463 {NULL, no_argument, NULL, 0} 464 }; 465 466 size_t md_longopts_size = sizeof (md_longopts); 467 468 int 469 md_parse_option (int c, char *arg) 470 { 471 /* We don't get a chance to initialize anything before we're called, 472 so handle that now. */ 473 if (! default_init_p) 474 init_default_arch (); 475 476 switch (c) 477 { 478 case OPTION_BUMP: 479 warn_on_bump = 1; 480 warn_after_architecture = SPARC_OPCODE_ARCH_V6; 481 break; 482 483 case OPTION_XARCH: 484 #ifdef OBJ_ELF 485 if (strncmp (arg, "v9", 2) != 0) 486 md_parse_option (OPTION_32, NULL); 487 else 488 md_parse_option (OPTION_64, NULL); 489 #endif 490 /* Fall through. */ 491 492 case 'A': 493 { 494 struct sparc_arch *sa; 495 enum sparc_opcode_arch_val opcode_arch; 496 497 sa = lookup_arch (arg); 498 if (sa == NULL 499 || ! sa->user_option_p) 500 { 501 if (c == OPTION_XARCH) 502 as_bad (_("invalid architecture -xarch=%s"), arg); 503 else 504 as_bad (_("invalid architecture -A%s"), arg); 505 return 0; 506 } 507 508 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch); 509 if (opcode_arch == SPARC_OPCODE_ARCH_BAD) 510 as_fatal (_("Bad opcode table, broken assembler.")); 511 512 if (!architecture_requested 513 || opcode_arch > max_architecture) 514 max_architecture = opcode_arch; 515 hwcap_allowed |= sa->hwcap_allowed; 516 architecture_requested = 1; 517 } 518 break; 519 520 case OPTION_SPARC: 521 /* Ignore -sparc, used by SunOS make default .s.o rule. */ 522 break; 523 524 case OPTION_ENFORCE_ALIGNED_DATA: 525 enforce_aligned_data = 1; 526 break; 527 528 #ifdef SPARC_BIENDIAN 529 case OPTION_LITTLE_ENDIAN: 530 target_big_endian = 0; 531 if (default_arch_type != sparclet) 532 as_fatal ("This target does not support -EL"); 533 break; 534 case OPTION_LITTLE_ENDIAN_DATA: 535 target_little_endian_data = 1; 536 target_big_endian = 0; 537 if (default_arch_type != sparc86x 538 && default_arch_type != v9) 539 as_fatal ("This target does not support --little-endian-data"); 540 break; 541 case OPTION_BIG_ENDIAN: 542 target_big_endian = 1; 543 break; 544 #endif 545 546 #ifdef OBJ_AOUT 547 case 'k': 548 sparc_pic_code = 1; 549 break; 550 #endif 551 552 #ifdef OBJ_ELF 553 case OPTION_32: 554 case OPTION_64: 555 { 556 const char **list, **l; 557 558 sparc_arch_size = c == OPTION_32 ? 32 : 64; 559 list = bfd_target_list (); 560 for (l = list; *l != NULL; l++) 561 { 562 if (sparc_arch_size == 32) 563 { 564 if (CONST_STRNEQ (*l, "elf32-sparc")) 565 break; 566 } 567 else 568 { 569 if (CONST_STRNEQ (*l, "elf64-sparc")) 570 break; 571 } 572 } 573 if (*l == NULL) 574 as_fatal (_("No compiled in support for %d bit object file format"), 575 sparc_arch_size); 576 free (list); 577 578 if (sparc_arch_size == 64 579 && max_architecture < SPARC_OPCODE_ARCH_V9) 580 max_architecture = SPARC_OPCODE_ARCH_V9; 581 } 582 break; 583 584 case OPTION_TSO: 585 sparc_memory_model = MM_TSO; 586 break; 587 588 case OPTION_PSO: 589 sparc_memory_model = MM_PSO; 590 break; 591 592 case OPTION_RMO: 593 sparc_memory_model = MM_RMO; 594 break; 595 596 case 'V': 597 print_version_id (); 598 break; 599 600 case 'Q': 601 /* Qy - do emit .comment 602 Qn - do not emit .comment. */ 603 break; 604 605 case 's': 606 /* Use .stab instead of .stab.excl. */ 607 break; 608 609 case 'q': 610 /* quick -- Native assembler does fewer checks. */ 611 break; 612 613 case 'K': 614 if (strcmp (arg, "PIC") != 0) 615 as_warn (_("Unrecognized option following -K")); 616 else 617 sparc_pic_code = 1; 618 break; 619 620 case OPTION_NO_UNDECLARED_REGS: 621 no_undeclared_regs = 1; 622 break; 623 624 case OPTION_UNDECLARED_REGS: 625 no_undeclared_regs = 0; 626 break; 627 #endif 628 629 case OPTION_RELAX: 630 sparc_relax = 1; 631 break; 632 633 case OPTION_NO_RELAX: 634 sparc_relax = 0; 635 break; 636 637 default: 638 return 0; 639 } 640 641 return 1; 642 } 643 644 void 645 md_show_usage (FILE *stream) 646 { 647 const struct sparc_arch *arch; 648 int column; 649 650 /* We don't get a chance to initialize anything before we're called, 651 so handle that now. */ 652 if (! default_init_p) 653 init_default_arch (); 654 655 fprintf (stream, _("SPARC options:\n")); 656 column = 0; 657 for (arch = &sparc_arch_table[0]; arch->name; arch++) 658 { 659 if (!arch->user_option_p) 660 continue; 661 if (arch != &sparc_arch_table[0]) 662 fprintf (stream, " | "); 663 if (column + strlen (arch->name) > 70) 664 { 665 column = 0; 666 fputc ('\n', stream); 667 } 668 column += 5 + 2 + strlen (arch->name); 669 fprintf (stream, "-A%s", arch->name); 670 } 671 for (arch = &sparc_arch_table[0]; arch->name; arch++) 672 { 673 if (!arch->user_option_p) 674 continue; 675 fprintf (stream, " | "); 676 if (column + strlen (arch->name) > 65) 677 { 678 column = 0; 679 fputc ('\n', stream); 680 } 681 column += 5 + 7 + strlen (arch->name); 682 fprintf (stream, "-xarch=%s", arch->name); 683 } 684 fprintf (stream, _("\n\ 685 specify variant of SPARC architecture\n\ 686 -bump warn when assembler switches architectures\n\ 687 -sparc ignored\n\ 688 --enforce-aligned-data force .long, etc., to be aligned correctly\n\ 689 -relax relax jumps and branches (default)\n\ 690 -no-relax avoid changing any jumps and branches\n")); 691 #ifdef OBJ_AOUT 692 fprintf (stream, _("\ 693 -k generate PIC\n")); 694 #endif 695 #ifdef OBJ_ELF 696 fprintf (stream, _("\ 697 -32 create 32 bit object file\n\ 698 -64 create 64 bit object file\n")); 699 fprintf (stream, _("\ 700 [default is %d]\n"), default_arch_size); 701 fprintf (stream, _("\ 702 -TSO use Total Store Ordering\n\ 703 -PSO use Partial Store Ordering\n\ 704 -RMO use Relaxed Memory Ordering\n")); 705 fprintf (stream, _("\ 706 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO"); 707 fprintf (stream, _("\ 708 -KPIC generate PIC\n\ 709 -V print assembler version number\n\ 710 -undeclared-regs ignore application global register usage without\n\ 711 appropriate .register directive (default)\n\ 712 -no-undeclared-regs force error on application global register usage\n\ 713 without appropriate .register directive\n\ 714 -q ignored\n\ 715 -Qy, -Qn ignored\n\ 716 -s ignored\n")); 717 #endif 718 #ifdef SPARC_BIENDIAN 719 fprintf (stream, _("\ 720 -EL generate code for a little endian machine\n\ 721 -EB generate code for a big endian machine\n\ 722 --little-endian-data generate code for a machine having big endian\n\ 723 instructions and little endian data.\n")); 724 #endif 725 } 726 727 /* Native operand size opcode translation. */ 729 struct 730 { 731 char *name; 732 char *name32; 733 char *name64; 734 } native_op_table[] = 735 { 736 {"ldn", "ld", "ldx"}, 737 {"ldna", "lda", "ldxa"}, 738 {"stn", "st", "stx"}, 739 {"stna", "sta", "stxa"}, 740 {"slln", "sll", "sllx"}, 741 {"srln", "srl", "srlx"}, 742 {"sran", "sra", "srax"}, 743 {"casn", "cas", "casx"}, 744 {"casna", "casa", "casxa"}, 745 {"clrn", "clr", "clrx"}, 746 {NULL, NULL, NULL}, 747 }; 748 749 /* sparc64 privileged and hyperprivileged registers. */ 751 752 struct priv_reg_entry 753 { 754 char *name; 755 int regnum; 756 }; 757 758 struct priv_reg_entry priv_reg_table[] = 759 { 760 {"tpc", 0}, 761 {"tnpc", 1}, 762 {"tstate", 2}, 763 {"tt", 3}, 764 {"tick", 4}, 765 {"tba", 5}, 766 {"pstate", 6}, 767 {"tl", 7}, 768 {"pil", 8}, 769 {"cwp", 9}, 770 {"cansave", 10}, 771 {"canrestore", 11}, 772 {"cleanwin", 12}, 773 {"otherwin", 13}, 774 {"wstate", 14}, 775 {"fq", 15}, 776 {"gl", 16}, 777 {"ver", 31}, 778 {"", -1}, /* End marker. */ 779 }; 780 781 struct priv_reg_entry hpriv_reg_table[] = 782 { 783 {"hpstate", 0}, 784 {"htstate", 1}, 785 {"hintp", 3}, 786 {"htba", 5}, 787 {"hver", 6}, 788 {"hstick_cmpr", 31}, 789 {"", -1}, /* End marker. */ 790 }; 791 792 /* v9a specific asrs. This table is ordered by initial 793 letter, in reverse. */ 794 795 struct priv_reg_entry v9a_asr_table[] = 796 { 797 {"tick_cmpr", 23}, 798 {"sys_tick_cmpr", 25}, 799 {"sys_tick", 24}, 800 {"stick_cmpr", 25}, 801 {"stick", 24}, 802 {"softint_clear", 21}, 803 {"softint_set", 20}, 804 {"softint", 22}, 805 {"set_softint", 20}, 806 {"pause", 27}, 807 {"pic", 17}, 808 {"pcr", 16}, 809 {"gsr", 19}, 810 {"dcr", 18}, 811 {"cps", 28}, 812 {"cfr", 26}, 813 {"clear_softint", 21}, 814 {"", -1}, /* End marker. */ 815 }; 816 817 static int 818 cmp_reg_entry (const void *parg, const void *qarg) 819 { 820 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg; 821 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg; 822 823 return strcmp (q->name, p->name); 824 } 825 826 /* This function is called once, at assembler startup time. It should 828 set up all the tables, etc. that the MD part of the assembler will 829 need. */ 830 831 void 832 md_begin (void) 833 { 834 register const char *retval = NULL; 835 int lose = 0; 836 register unsigned int i = 0; 837 838 /* We don't get a chance to initialize anything before md_parse_option 839 is called, and it may not be called, so handle default initialization 840 now if not already done. */ 841 if (! default_init_p) 842 init_default_arch (); 843 844 sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4; 845 op_hash = hash_new (); 846 847 while (i < (unsigned int) sparc_num_opcodes) 848 { 849 const char *name = sparc_opcodes[i].name; 850 retval = hash_insert (op_hash, name, (void *) &sparc_opcodes[i]); 851 if (retval != NULL) 852 { 853 as_bad (_("Internal error: can't hash `%s': %s\n"), 854 sparc_opcodes[i].name, retval); 855 lose = 1; 856 } 857 do 858 { 859 if (sparc_opcodes[i].match & sparc_opcodes[i].lose) 860 { 861 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"), 862 sparc_opcodes[i].name, sparc_opcodes[i].args); 863 lose = 1; 864 } 865 ++i; 866 } 867 while (i < (unsigned int) sparc_num_opcodes 868 && !strcmp (sparc_opcodes[i].name, name)); 869 } 870 871 for (i = 0; native_op_table[i].name; i++) 872 { 873 const struct sparc_opcode *insn; 874 char *name = ((sparc_arch_size == 32) 875 ? native_op_table[i].name32 876 : native_op_table[i].name64); 877 insn = (struct sparc_opcode *) hash_find (op_hash, name); 878 if (insn == NULL) 879 { 880 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"), 881 name, native_op_table[i].name); 882 lose = 1; 883 } 884 else 885 { 886 retval = hash_insert (op_hash, native_op_table[i].name, 887 (void *) insn); 888 if (retval != NULL) 889 { 890 as_bad (_("Internal error: can't hash `%s': %s\n"), 891 sparc_opcodes[i].name, retval); 892 lose = 1; 893 } 894 } 895 } 896 897 if (lose) 898 as_fatal (_("Broken assembler. No assembly attempted.")); 899 900 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]), 901 sizeof (priv_reg_table[0]), cmp_reg_entry); 902 903 /* If -bump, record the architecture level at which we start issuing 904 warnings. The behaviour is different depending upon whether an 905 architecture was explicitly specified. If it wasn't, we issue warnings 906 for all upwards bumps. If it was, we don't start issuing warnings until 907 we need to bump beyond the requested architecture or when we bump between 908 conflicting architectures. */ 909 910 if (warn_on_bump 911 && architecture_requested) 912 { 913 /* `max_architecture' records the requested architecture. 914 Issue warnings if we go above it. */ 915 warn_after_architecture = max_architecture; 916 917 /* Find the highest architecture level that doesn't conflict with 918 the requested one. */ 919 for (max_architecture = SPARC_OPCODE_ARCH_MAX; 920 max_architecture > warn_after_architecture; 921 --max_architecture) 922 if (! SPARC_OPCODE_CONFLICT_P (max_architecture, 923 warn_after_architecture)) 924 break; 925 } 926 } 927 928 /* Called after all assembly has been done. */ 929 930 void 931 sparc_md_end (void) 932 { 933 unsigned long mach = bfd_mach_sparc; 934 935 if (sparc_arch_size == 64) 936 switch (current_architecture) 937 { 938 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break; 939 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break; 940 default: mach = bfd_mach_sparc_v9; break; 941 } 942 else 943 switch (current_architecture) 944 { 945 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break; 946 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break; 947 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break; 948 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break; 949 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't 950 be but for now it is (since that's the way it's always been 951 treated). */ 952 default: break; 953 } 954 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach); 955 956 #if defined(OBJ_ELF) && !defined(TE_SOLARIS) 957 if (hwcap_seen) 958 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS, hwcap_seen); 959 #endif 960 } 961 962 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */ 964 965 static inline int 966 in_signed_range (bfd_signed_vma val, bfd_signed_vma max) 967 { 968 if (max <= 0) 969 abort (); 970 /* Sign-extend the value from the architecture word size, so that 971 0xffffffff is always considered -1 on sparc32. */ 972 if (sparc_arch_size == 32) 973 { 974 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31; 975 val = ((val & U0xffffffff) ^ sign) - sign; 976 } 977 if (val > max) 978 return 0; 979 if (val < ~max) 980 return 0; 981 return 1; 982 } 983 984 /* Return non-zero if VAL is in the range 0 to MAX. */ 985 986 static inline int 987 in_unsigned_range (bfd_vma val, bfd_vma max) 988 { 989 if (val > max) 990 return 0; 991 return 1; 992 } 993 994 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX. 995 (e.g. -15 to +31). */ 996 997 static inline int 998 in_bitfield_range (bfd_signed_vma val, bfd_signed_vma max) 999 { 1000 if (max <= 0) 1001 abort (); 1002 if (val > max) 1003 return 0; 1004 if (val < ~(max >> 1)) 1005 return 0; 1006 return 1; 1007 } 1008 1009 static int 1010 sparc_ffs (unsigned int mask) 1011 { 1012 int i; 1013 1014 if (mask == 0) 1015 return -1; 1016 1017 for (i = 0; (mask & 1) == 0; ++i) 1018 mask >>= 1; 1019 return i; 1020 } 1021 1022 /* Implement big shift right. */ 1023 static bfd_vma 1024 BSR (bfd_vma val, int amount) 1025 { 1026 if (sizeof (bfd_vma) <= 4 && amount >= 32) 1027 as_fatal (_("Support for 64-bit arithmetic not compiled in.")); 1028 return val >> amount; 1029 } 1030 1031 /* For communication between sparc_ip and get_expression. */ 1033 static char *expr_end; 1034 1035 /* Values for `special_case'. 1036 Instructions that require wierd handling because they're longer than 1037 4 bytes. */ 1038 #define SPECIAL_CASE_NONE 0 1039 #define SPECIAL_CASE_SET 1 1040 #define SPECIAL_CASE_SETSW 2 1041 #define SPECIAL_CASE_SETX 3 1042 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */ 1043 #define SPECIAL_CASE_FDIV 4 1044 1045 /* Bit masks of various insns. */ 1046 #define NOP_INSN 0x01000000 1047 #define OR_INSN 0x80100000 1048 #define XOR_INSN 0x80180000 1049 #define FMOVS_INSN 0x81A00020 1050 #define SETHI_INSN 0x01000000 1051 #define SLLX_INSN 0x81281000 1052 #define SRA_INSN 0x81380000 1053 1054 /* The last instruction to be assembled. */ 1055 static const struct sparc_opcode *last_insn; 1056 /* The assembled opcode of `last_insn'. */ 1057 static unsigned long last_opcode; 1058 1059 /* Handle the set and setuw synthetic instructions. */ 1061 1062 static void 1063 synthetize_setuw (const struct sparc_opcode *insn) 1064 { 1065 int need_hi22_p = 0; 1066 int rd = (the_insn.opcode & RD (~0)) >> 25; 1067 1068 if (the_insn.exp.X_op == O_constant) 1069 { 1070 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 1071 { 1072 if (sizeof (offsetT) > 4 1073 && (the_insn.exp.X_add_number < 0 1074 || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) 1075 as_warn (_("set: number not in 0..4294967295 range")); 1076 } 1077 else 1078 { 1079 if (sizeof (offsetT) > 4 1080 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 1081 || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) 1082 as_warn (_("set: number not in -2147483648..4294967295 range")); 1083 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number; 1084 } 1085 } 1086 1087 /* See if operand is absolute and small; skip sethi if so. */ 1088 if (the_insn.exp.X_op != O_constant 1089 || the_insn.exp.X_add_number >= (1 << 12) 1090 || the_insn.exp.X_add_number < -(1 << 12)) 1091 { 1092 the_insn.opcode = (SETHI_INSN | RD (rd) 1093 | ((the_insn.exp.X_add_number >> 10) 1094 & (the_insn.exp.X_op == O_constant 1095 ? 0x3fffff : 0))); 1096 the_insn.reloc = (the_insn.exp.X_op != O_constant 1097 ? BFD_RELOC_HI22 : BFD_RELOC_NONE); 1098 output_insn (insn, &the_insn); 1099 need_hi22_p = 1; 1100 } 1101 1102 /* See if operand has no low-order bits; skip OR if so. */ 1103 if (the_insn.exp.X_op != O_constant 1104 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0) 1105 || ! need_hi22_p) 1106 { 1107 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0) 1108 | RD (rd) | IMMED 1109 | (the_insn.exp.X_add_number 1110 & (the_insn.exp.X_op != O_constant 1111 ? 0 : need_hi22_p ? 0x3ff : 0x1fff))); 1112 the_insn.reloc = (the_insn.exp.X_op != O_constant 1113 ? BFD_RELOC_LO10 : BFD_RELOC_NONE); 1114 output_insn (insn, &the_insn); 1115 } 1116 } 1117 1118 /* Handle the setsw synthetic instruction. */ 1119 1120 static void 1121 synthetize_setsw (const struct sparc_opcode *insn) 1122 { 1123 int low32, rd, opc; 1124 1125 rd = (the_insn.opcode & RD (~0)) >> 25; 1126 1127 if (the_insn.exp.X_op != O_constant) 1128 { 1129 synthetize_setuw (insn); 1130 1131 /* Need to sign extend it. */ 1132 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd)); 1133 the_insn.reloc = BFD_RELOC_NONE; 1134 output_insn (insn, &the_insn); 1135 return; 1136 } 1137 1138 if (sizeof (offsetT) > 4 1139 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 1140 || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) 1141 as_warn (_("setsw: number not in -2147483648..4294967295 range")); 1142 1143 low32 = the_insn.exp.X_add_number; 1144 1145 if (low32 >= 0) 1146 { 1147 synthetize_setuw (insn); 1148 return; 1149 } 1150 1151 opc = OR_INSN; 1152 1153 the_insn.reloc = BFD_RELOC_NONE; 1154 /* See if operand is absolute and small; skip sethi if so. */ 1155 if (low32 < -(1 << 12)) 1156 { 1157 the_insn.opcode = (SETHI_INSN | RD (rd) 1158 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff)); 1159 output_insn (insn, &the_insn); 1160 low32 = 0x1c00 | (low32 & 0x3ff); 1161 opc = RS1 (rd) | XOR_INSN; 1162 } 1163 1164 the_insn.opcode = (opc | RD (rd) | IMMED 1165 | (low32 & 0x1fff)); 1166 output_insn (insn, &the_insn); 1167 } 1168 1169 /* Handle the setsw synthetic instruction. */ 1170 1171 static void 1172 synthetize_setx (const struct sparc_opcode *insn) 1173 { 1174 int upper32, lower32; 1175 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14; 1176 int dstreg = (the_insn.opcode & RD (~0)) >> 25; 1177 int upper_dstreg; 1178 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0; 1179 int need_xor10_p = 0; 1180 1181 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000) 1182 lower32 = SIGNEXT32 (the_insn.exp.X_add_number); 1183 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32)); 1184 #undef SIGNEXT32 1185 1186 upper_dstreg = tmpreg; 1187 /* The tmp reg should not be the dst reg. */ 1188 if (tmpreg == dstreg) 1189 as_warn (_("setx: temporary register same as destination register")); 1190 1191 /* ??? Obviously there are other optimizations we can do 1192 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be 1193 doing some of these. Later. If you do change things, try to 1194 change all of this to be table driven as well. */ 1195 /* What to output depends on the number if it's constant. 1196 Compute that first, then output what we've decided upon. */ 1197 if (the_insn.exp.X_op != O_constant) 1198 { 1199 if (sparc_arch_size == 32) 1200 { 1201 /* When arch size is 32, we want setx to be equivalent 1202 to setuw for anything but constants. */ 1203 the_insn.exp.X_add_number &= 0xffffffff; 1204 synthetize_setuw (insn); 1205 return; 1206 } 1207 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1; 1208 lower32 = 0; 1209 upper32 = 0; 1210 } 1211 else 1212 { 1213 /* Reset X_add_number, we've extracted it as upper32/lower32. 1214 Otherwise fixup_segment will complain about not being able to 1215 write an 8 byte number in a 4 byte field. */ 1216 the_insn.exp.X_add_number = 0; 1217 1218 /* Only need hh22 if `or' insn can't handle constant. */ 1219 if (upper32 < -(1 << 12) || upper32 >= (1 << 12)) 1220 need_hh22_p = 1; 1221 1222 /* Does bottom part (after sethi) have bits? */ 1223 if ((need_hh22_p && (upper32 & 0x3ff) != 0) 1224 /* No hh22, but does upper32 still have bits we can't set 1225 from lower32? */ 1226 || (! need_hh22_p && upper32 != 0 && upper32 != -1)) 1227 need_hm10_p = 1; 1228 1229 /* If the lower half is all zero, we build the upper half directly 1230 into the dst reg. */ 1231 if (lower32 != 0 1232 /* Need lower half if number is zero or 0xffffffff00000000. */ 1233 || (! need_hh22_p && ! need_hm10_p)) 1234 { 1235 /* No need for sethi if `or' insn can handle constant. */ 1236 if (lower32 < -(1 << 12) || lower32 >= (1 << 12) 1237 /* Note that we can't use a negative constant in the `or' 1238 insn unless the upper 32 bits are all ones. */ 1239 || (lower32 < 0 && upper32 != -1) 1240 || (lower32 >= 0 && upper32 == -1)) 1241 need_hi22_p = 1; 1242 1243 if (need_hi22_p && upper32 == -1) 1244 need_xor10_p = 1; 1245 1246 /* Does bottom part (after sethi) have bits? */ 1247 else if ((need_hi22_p && (lower32 & 0x3ff) != 0) 1248 /* No sethi. */ 1249 || (! need_hi22_p && (lower32 & 0x1fff) != 0) 1250 /* Need `or' if we didn't set anything else. */ 1251 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p)) 1252 need_lo10_p = 1; 1253 } 1254 else 1255 /* Output directly to dst reg if lower 32 bits are all zero. */ 1256 upper_dstreg = dstreg; 1257 } 1258 1259 if (!upper_dstreg && dstreg) 1260 as_warn (_("setx: illegal temporary register g0")); 1261 1262 if (need_hh22_p) 1263 { 1264 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg) 1265 | ((upper32 >> 10) & 0x3fffff)); 1266 the_insn.reloc = (the_insn.exp.X_op != O_constant 1267 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE); 1268 output_insn (insn, &the_insn); 1269 } 1270 1271 if (need_hi22_p) 1272 { 1273 the_insn.opcode = (SETHI_INSN | RD (dstreg) 1274 | (((need_xor10_p ? ~lower32 : lower32) 1275 >> 10) & 0x3fffff)); 1276 the_insn.reloc = (the_insn.exp.X_op != O_constant 1277 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE); 1278 output_insn (insn, &the_insn); 1279 } 1280 1281 if (need_hm10_p) 1282 { 1283 the_insn.opcode = (OR_INSN 1284 | (need_hh22_p ? RS1 (upper_dstreg) : 0) 1285 | RD (upper_dstreg) 1286 | IMMED 1287 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff))); 1288 the_insn.reloc = (the_insn.exp.X_op != O_constant 1289 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE); 1290 output_insn (insn, &the_insn); 1291 } 1292 1293 if (need_lo10_p) 1294 { 1295 /* FIXME: One nice optimization to do here is to OR the low part 1296 with the highpart if hi22 isn't needed and the low part is 1297 positive. */ 1298 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0) 1299 | RD (dstreg) 1300 | IMMED 1301 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff))); 1302 the_insn.reloc = (the_insn.exp.X_op != O_constant 1303 ? BFD_RELOC_LO10 : BFD_RELOC_NONE); 1304 output_insn (insn, &the_insn); 1305 } 1306 1307 /* If we needed to build the upper part, shift it into place. */ 1308 if (need_hh22_p || need_hm10_p) 1309 { 1310 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg) 1311 | IMMED | 32); 1312 the_insn.reloc = BFD_RELOC_NONE; 1313 output_insn (insn, &the_insn); 1314 } 1315 1316 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */ 1317 if (need_xor10_p) 1318 { 1319 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED 1320 | 0x1c00 | (lower32 & 0x3ff)); 1321 the_insn.reloc = BFD_RELOC_NONE; 1322 output_insn (insn, &the_insn); 1323 } 1324 1325 /* If we needed to build both upper and lower parts, OR them together. */ 1326 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p)) 1327 { 1328 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg) 1329 | RD (dstreg)); 1330 the_insn.reloc = BFD_RELOC_NONE; 1331 output_insn (insn, &the_insn); 1332 } 1333 } 1334 1335 /* Main entry point to assemble one instruction. */ 1337 1338 void 1339 md_assemble (char *str) 1340 { 1341 const struct sparc_opcode *insn; 1342 int special_case; 1343 1344 know (str); 1345 special_case = sparc_ip (str, &insn); 1346 if (insn == NULL) 1347 return; 1348 1349 /* We warn about attempts to put a floating point branch in a delay slot, 1350 unless the delay slot has been annulled. */ 1351 if (last_insn != NULL 1352 && (insn->flags & F_FBR) != 0 1353 && (last_insn->flags & F_DELAYED) != 0 1354 /* ??? This test isn't completely accurate. We assume anything with 1355 F_{UNBR,CONDBR,FBR} set is annullable. */ 1356 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0 1357 || (last_opcode & ANNUL) == 0)) 1358 as_warn (_("FP branch in delay slot")); 1359 1360 /* SPARC before v9 requires a nop instruction between a floating 1361 point instruction and a floating point branch. We insert one 1362 automatically, with a warning. */ 1363 if (max_architecture < SPARC_OPCODE_ARCH_V9 1364 && last_insn != NULL 1365 && (insn->flags & F_FBR) != 0 1366 && (last_insn->flags & F_FLOAT) != 0) 1367 { 1368 struct sparc_it nop_insn; 1369 1370 nop_insn.opcode = NOP_INSN; 1371 nop_insn.reloc = BFD_RELOC_NONE; 1372 output_insn (insn, &nop_insn); 1373 as_warn (_("FP branch preceded by FP instruction; NOP inserted")); 1374 } 1375 1376 switch (special_case) 1377 { 1378 case SPECIAL_CASE_NONE: 1379 /* Normal insn. */ 1380 output_insn (insn, &the_insn); 1381 break; 1382 1383 case SPECIAL_CASE_SETSW: 1384 synthetize_setsw (insn); 1385 break; 1386 1387 case SPECIAL_CASE_SET: 1388 synthetize_setuw (insn); 1389 break; 1390 1391 case SPECIAL_CASE_SETX: 1392 synthetize_setx (insn); 1393 break; 1394 1395 case SPECIAL_CASE_FDIV: 1396 { 1397 int rd = (the_insn.opcode >> 25) & 0x1f; 1398 1399 output_insn (insn, &the_insn); 1400 1401 /* According to information leaked from Sun, the "fdiv" instructions 1402 on early SPARC machines would produce incorrect results sometimes. 1403 The workaround is to add an fmovs of the destination register to 1404 itself just after the instruction. This was true on machines 1405 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */ 1406 gas_assert (the_insn.reloc == BFD_RELOC_NONE); 1407 the_insn.opcode = FMOVS_INSN | rd | RD (rd); 1408 output_insn (insn, &the_insn); 1409 return; 1410 } 1411 1412 default: 1413 as_fatal (_("failed special case insn sanity check")); 1414 } 1415 } 1416 1417 static const char * 1418 get_hwcap_name (int mask) 1419 { 1420 if (mask & HWCAP_MUL32) 1421 return "mul32"; 1422 if (mask & HWCAP_DIV32) 1423 return "div32"; 1424 if (mask & HWCAP_FSMULD) 1425 return "fsmuld"; 1426 if (mask & HWCAP_V8PLUS) 1427 return "v8plus"; 1428 if (mask & HWCAP_POPC) 1429 return "popc"; 1430 if (mask & HWCAP_VIS) 1431 return "vis"; 1432 if (mask & HWCAP_VIS2) 1433 return "vis2"; 1434 if (mask & HWCAP_ASI_BLK_INIT) 1435 return "ASIBlkInit"; 1436 if (mask & HWCAP_FMAF) 1437 return "fmaf"; 1438 if (mask & HWCAP_VIS3) 1439 return "vis3"; 1440 if (mask & HWCAP_HPC) 1441 return "hpc"; 1442 if (mask & HWCAP_RANDOM) 1443 return "random"; 1444 if (mask & HWCAP_TRANS) 1445 return "trans"; 1446 if (mask & HWCAP_FJFMAU) 1447 return "fjfmau"; 1448 if (mask & HWCAP_IMA) 1449 return "ima"; 1450 if (mask & HWCAP_ASI_CACHE_SPARING) 1451 return "cspare"; 1452 if (mask & HWCAP_AES) 1453 return "aes"; 1454 if (mask & HWCAP_DES) 1455 return "des"; 1456 if (mask & HWCAP_KASUMI) 1457 return "kasumi"; 1458 if (mask & HWCAP_CAMELLIA) 1459 return "camellia"; 1460 if (mask & HWCAP_MD5) 1461 return "md5"; 1462 if (mask & HWCAP_SHA1) 1463 return "sha1"; 1464 if (mask & HWCAP_SHA256) 1465 return "sha256"; 1466 if (mask & HWCAP_SHA512) 1467 return "sha512"; 1468 if (mask & HWCAP_MPMUL) 1469 return "mpmul"; 1470 if (mask & HWCAP_MONT) 1471 return "mont"; 1472 if (mask & HWCAP_PAUSE) 1473 return "pause"; 1474 if (mask & HWCAP_CBCOND) 1475 return "cbcond"; 1476 if (mask & HWCAP_CRC32C) 1477 return "crc32c"; 1478 return "UNKNOWN"; 1479 } 1480 1481 /* Subroutine of md_assemble to do the actual parsing. */ 1482 1483 static int 1484 sparc_ip (char *str, const struct sparc_opcode **pinsn) 1485 { 1486 char *error_message = ""; 1487 char *s; 1488 const char *args; 1489 char c; 1490 const struct sparc_opcode *insn; 1491 char *argsStart; 1492 unsigned long opcode; 1493 unsigned int mask = 0; 1494 int match = 0; 1495 int comma = 0; 1496 int v9_arg_p; 1497 int special_case = SPECIAL_CASE_NONE; 1498 1499 s = str; 1500 if (ISLOWER (*s)) 1501 { 1502 do 1503 ++s; 1504 while (ISLOWER (*s) || ISDIGIT (*s) || *s == '_'); 1505 } 1506 1507 switch (*s) 1508 { 1509 case '\0': 1510 break; 1511 1512 case ',': 1513 comma = 1; 1514 /* Fall through. */ 1515 1516 case ' ': 1517 *s++ = '\0'; 1518 break; 1519 1520 default: 1521 as_bad (_("Unknown opcode: `%s'"), str); 1522 *pinsn = NULL; 1523 return special_case; 1524 } 1525 insn = (struct sparc_opcode *) hash_find (op_hash, str); 1526 *pinsn = insn; 1527 if (insn == NULL) 1528 { 1529 as_bad (_("Unknown opcode: `%s'"), str); 1530 return special_case; 1531 } 1532 if (comma) 1533 { 1534 *--s = ','; 1535 } 1536 1537 argsStart = s; 1538 for (;;) 1539 { 1540 opcode = insn->match; 1541 memset (&the_insn, '\0', sizeof (the_insn)); 1542 the_insn.reloc = BFD_RELOC_NONE; 1543 v9_arg_p = 0; 1544 1545 /* Build the opcode, checking as we go to make sure that the 1546 operands match. */ 1547 for (args = insn->args;; ++args) 1548 { 1549 switch (*args) 1550 { 1551 case 'K': 1552 { 1553 int kmask = 0; 1554 1555 /* Parse a series of masks. */ 1556 if (*s == '#') 1557 { 1558 while (*s == '#') 1559 { 1560 int jmask; 1561 1562 if (! parse_keyword_arg (sparc_encode_membar, &s, 1563 &jmask)) 1564 { 1565 error_message = _(": invalid membar mask name"); 1566 goto error; 1567 } 1568 kmask |= jmask; 1569 while (*s == ' ') 1570 ++s; 1571 if (*s == '|' || *s == '+') 1572 ++s; 1573 while (*s == ' ') 1574 ++s; 1575 } 1576 } 1577 else 1578 { 1579 if (! parse_const_expr_arg (&s, &kmask)) 1580 { 1581 error_message = _(": invalid membar mask expression"); 1582 goto error; 1583 } 1584 if (kmask < 0 || kmask > 127) 1585 { 1586 error_message = _(": invalid membar mask number"); 1587 goto error; 1588 } 1589 } 1590 1591 opcode |= MEMBAR (kmask); 1592 continue; 1593 } 1594 1595 case '3': 1596 { 1597 int smask = 0; 1598 1599 if (! parse_const_expr_arg (&s, &smask)) 1600 { 1601 error_message = _(": invalid siam mode expression"); 1602 goto error; 1603 } 1604 if (smask < 0 || smask > 7) 1605 { 1606 error_message = _(": invalid siam mode number"); 1607 goto error; 1608 } 1609 opcode |= smask; 1610 continue; 1611 } 1612 1613 case '*': 1614 { 1615 int fcn = 0; 1616 1617 /* Parse a prefetch function. */ 1618 if (*s == '#') 1619 { 1620 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn)) 1621 { 1622 error_message = _(": invalid prefetch function name"); 1623 goto error; 1624 } 1625 } 1626 else 1627 { 1628 if (! parse_const_expr_arg (&s, &fcn)) 1629 { 1630 error_message = _(": invalid prefetch function expression"); 1631 goto error; 1632 } 1633 if (fcn < 0 || fcn > 31) 1634 { 1635 error_message = _(": invalid prefetch function number"); 1636 goto error; 1637 } 1638 } 1639 opcode |= RD (fcn); 1640 continue; 1641 } 1642 1643 case '!': 1644 case '?': 1645 /* Parse a sparc64 privileged register. */ 1646 if (*s == '%') 1647 { 1648 struct priv_reg_entry *p = priv_reg_table; 1649 unsigned int len = 9999999; /* Init to make gcc happy. */ 1650 1651 s += 1; 1652 while (p->name[0] > s[0]) 1653 p++; 1654 while (p->name[0] == s[0]) 1655 { 1656 len = strlen (p->name); 1657 if (strncmp (p->name, s, len) == 0) 1658 break; 1659 p++; 1660 } 1661 if (p->name[0] != s[0]) 1662 { 1663 error_message = _(": unrecognizable privileged register"); 1664 goto error; 1665 } 1666 if (*args == '?') 1667 opcode |= (p->regnum << 14); 1668 else 1669 opcode |= (p->regnum << 25); 1670 s += len; 1671 continue; 1672 } 1673 else 1674 { 1675 error_message = _(": unrecognizable privileged register"); 1676 goto error; 1677 } 1678 1679 case '$': 1680 case '%': 1681 /* Parse a sparc64 hyperprivileged register. */ 1682 if (*s == '%') 1683 { 1684 struct priv_reg_entry *p = hpriv_reg_table; 1685 unsigned int len = 9999999; /* Init to make gcc happy. */ 1686 1687 s += 1; 1688 while (p->name[0] > s[0]) 1689 p++; 1690 while (p->name[0] == s[0]) 1691 { 1692 len = strlen (p->name); 1693 if (strncmp (p->name, s, len) == 0) 1694 break; 1695 p++; 1696 } 1697 if (p->name[0] != s[0]) 1698 { 1699 error_message = _(": unrecognizable hyperprivileged register"); 1700 goto error; 1701 } 1702 if (*args == '$') 1703 opcode |= (p->regnum << 14); 1704 else 1705 opcode |= (p->regnum << 25); 1706 s += len; 1707 continue; 1708 } 1709 else 1710 { 1711 error_message = _(": unrecognizable hyperprivileged register"); 1712 goto error; 1713 } 1714 1715 case '_': 1716 case '/': 1717 /* Parse a v9a/v9b ancillary state register. */ 1718 if (*s == '%') 1719 { 1720 struct priv_reg_entry *p = v9a_asr_table; 1721 unsigned int len = 9999999; /* Init to make gcc happy. */ 1722 1723 s += 1; 1724 while (p->name[0] > s[0]) 1725 p++; 1726 while (p->name[0] == s[0]) 1727 { 1728 len = strlen (p->name); 1729 if (strncmp (p->name, s, len) == 0) 1730 break; 1731 p++; 1732 } 1733 if (p->name[0] != s[0]) 1734 { 1735 error_message = _(": unrecognizable v9a or v9b ancillary state register"); 1736 goto error; 1737 } 1738 if (*args == '/' && (p->regnum == 20 || p->regnum == 21)) 1739 { 1740 error_message = _(": rd on write only ancillary state register"); 1741 goto error; 1742 } 1743 if (p->regnum >= 24 1744 && (insn->architecture 1745 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A))) 1746 { 1747 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */ 1748 error_message = _(": unrecognizable v9a ancillary state register"); 1749 goto error; 1750 } 1751 if (*args == '/') 1752 opcode |= (p->regnum << 14); 1753 else 1754 opcode |= (p->regnum << 25); 1755 s += len; 1756 continue; 1757 } 1758 else 1759 { 1760 error_message = _(": unrecognizable v9a or v9b ancillary state register"); 1761 goto error; 1762 } 1763 1764 case 'M': 1765 case 'm': 1766 if (strncmp (s, "%asr", 4) == 0) 1767 { 1768 s += 4; 1769 1770 if (ISDIGIT (*s)) 1771 { 1772 long num = 0; 1773 1774 while (ISDIGIT (*s)) 1775 { 1776 num = num * 10 + *s - '0'; 1777 ++s; 1778 } 1779 1780 if (current_architecture >= SPARC_OPCODE_ARCH_V9) 1781 { 1782 if (num < 16 || 31 < num) 1783 { 1784 error_message = _(": asr number must be between 16 and 31"); 1785 goto error; 1786 } 1787 } 1788 else 1789 { 1790 if (num < 0 || 31 < num) 1791 { 1792 error_message = _(": asr number must be between 0 and 31"); 1793 goto error; 1794 } 1795 } 1796 1797 opcode |= (*args == 'M' ? RS1 (num) : RD (num)); 1798 continue; 1799 } 1800 else 1801 { 1802 error_message = _(": expecting %asrN"); 1803 goto error; 1804 } 1805 } /* if %asr */ 1806 break; 1807 1808 case 'I': 1809 the_insn.reloc = BFD_RELOC_SPARC_11; 1810 goto immediate; 1811 1812 case 'j': 1813 the_insn.reloc = BFD_RELOC_SPARC_10; 1814 goto immediate; 1815 1816 case ')': 1817 if (*s == ' ') 1818 s++; 1819 if ((s[0] == '0' && s[1] == 'x' && ISXDIGIT (s[2])) 1820 || ISDIGIT (*s)) 1821 { 1822 long num = 0; 1823 1824 if (s[0] == '0' && s[1] == 'x') 1825 { 1826 s += 2; 1827 while (ISXDIGIT (*s)) 1828 { 1829 num <<= 4; 1830 num |= hex_value (*s); 1831 ++s; 1832 } 1833 } 1834 else 1835 { 1836 while (ISDIGIT (*s)) 1837 { 1838 num = num * 10 + *s - '0'; 1839 ++s; 1840 } 1841 } 1842 if (num < 0 || num > 31) 1843 { 1844 error_message = _(": crypto immediate must be between 0 and 31"); 1845 goto error; 1846 } 1847 1848 opcode |= RS3 (num); 1849 continue; 1850 } 1851 else 1852 { 1853 error_message = _(": expecting crypto immediate"); 1854 goto error; 1855 } 1856 1857 case 'X': 1858 /* V8 systems don't understand BFD_RELOC_SPARC_5. */ 1859 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 1860 the_insn.reloc = BFD_RELOC_SPARC_5; 1861 else 1862 the_insn.reloc = BFD_RELOC_SPARC13; 1863 /* These fields are unsigned, but for upward compatibility, 1864 allow negative values as well. */ 1865 goto immediate; 1866 1867 case 'Y': 1868 /* V8 systems don't understand BFD_RELOC_SPARC_6. */ 1869 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 1870 the_insn.reloc = BFD_RELOC_SPARC_6; 1871 else 1872 the_insn.reloc = BFD_RELOC_SPARC13; 1873 /* These fields are unsigned, but for upward compatibility, 1874 allow negative values as well. */ 1875 goto immediate; 1876 1877 case 'k': 1878 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16; 1879 the_insn.pcrel = 1; 1880 goto immediate; 1881 1882 case '=': 1883 the_insn.reloc = /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10; 1884 the_insn.pcrel = 1; 1885 goto immediate; 1886 1887 case 'G': 1888 the_insn.reloc = BFD_RELOC_SPARC_WDISP19; 1889 the_insn.pcrel = 1; 1890 goto immediate; 1891 1892 case 'N': 1893 if (*s == 'p' && s[1] == 'n') 1894 { 1895 s += 2; 1896 continue; 1897 } 1898 break; 1899 1900 case 'T': 1901 if (*s == 'p' && s[1] == 't') 1902 { 1903 s += 2; 1904 continue; 1905 } 1906 break; 1907 1908 case 'z': 1909 if (*s == ' ') 1910 { 1911 ++s; 1912 } 1913 if (strncmp (s, "%icc", 4) == 0) 1914 { 1915 s += 4; 1916 continue; 1917 } 1918 break; 1919 1920 case 'Z': 1921 if (*s == ' ') 1922 { 1923 ++s; 1924 } 1925 if (strncmp (s, "%xcc", 4) == 0) 1926 { 1927 s += 4; 1928 continue; 1929 } 1930 break; 1931 1932 case '6': 1933 if (*s == ' ') 1934 { 1935 ++s; 1936 } 1937 if (strncmp (s, "%fcc0", 5) == 0) 1938 { 1939 s += 5; 1940 continue; 1941 } 1942 break; 1943 1944 case '7': 1945 if (*s == ' ') 1946 { 1947 ++s; 1948 } 1949 if (strncmp (s, "%fcc1", 5) == 0) 1950 { 1951 s += 5; 1952 continue; 1953 } 1954 break; 1955 1956 case '8': 1957 if (*s == ' ') 1958 { 1959 ++s; 1960 } 1961 if (strncmp (s, "%fcc2", 5) == 0) 1962 { 1963 s += 5; 1964 continue; 1965 } 1966 break; 1967 1968 case '9': 1969 if (*s == ' ') 1970 { 1971 ++s; 1972 } 1973 if (strncmp (s, "%fcc3", 5) == 0) 1974 { 1975 s += 5; 1976 continue; 1977 } 1978 break; 1979 1980 case 'P': 1981 if (strncmp (s, "%pc", 3) == 0) 1982 { 1983 s += 3; 1984 continue; 1985 } 1986 break; 1987 1988 case 'W': 1989 if (strncmp (s, "%tick", 5) == 0) 1990 { 1991 s += 5; 1992 continue; 1993 } 1994 break; 1995 1996 case '\0': /* End of args. */ 1997 if (s[0] == ',' && s[1] == '%') 1998 { 1999 static const struct ops 2000 { 2001 /* The name as it appears in assembler. */ 2002 char *name; 2003 /* strlen (name), precomputed for speed */ 2004 int len; 2005 /* The reloc this pseudo-op translates to. */ 2006 int reloc; 2007 /* 1 if tls call. */ 2008 int tls_call; 2009 } 2010 ops[] = 2011 { 2012 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD, 0 }, 2013 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL, 1 }, 2014 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD, 0 }, 2015 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL, 1 }, 2016 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD, 0 }, 2017 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX, 0 }, 2018 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD, 0 }, 2019 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 }, 2020 { "gdop", 4, BFD_RELOC_SPARC_GOTDATA_OP, 0 }, 2021 { NULL, 0, 0, 0 } 2022 }; 2023 const struct ops *o; 2024 char *s1; 2025 int npar = 0; 2026 2027 for (o = ops; o->name; o++) 2028 if (strncmp (s + 2, o->name, o->len) == 0) 2029 break; 2030 if (o->name == NULL) 2031 break; 2032 2033 if (s[o->len + 2] != '(') 2034 { 2035 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); 2036 return special_case; 2037 } 2038 2039 if (! o->tls_call && the_insn.reloc != BFD_RELOC_NONE) 2040 { 2041 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"), 2042 o->name); 2043 return special_case; 2044 } 2045 2046 if (o->tls_call 2047 && (the_insn.reloc != BFD_RELOC_32_PCREL_S2 2048 || the_insn.exp.X_add_number != 0 2049 || the_insn.exp.X_add_symbol 2050 != symbol_find_or_make ("__tls_get_addr"))) 2051 { 2052 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"), 2053 o->name); 2054 return special_case; 2055 } 2056 2057 the_insn.reloc = o->reloc; 2058 memset (&the_insn.exp, 0, sizeof (the_insn.exp)); 2059 s += o->len + 3; 2060 2061 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) 2062 if (*s1 == '(') 2063 npar++; 2064 else if (*s1 == ')') 2065 { 2066 if (!npar) 2067 break; 2068 npar--; 2069 } 2070 2071 if (*s1 != ')') 2072 { 2073 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); 2074 return special_case; 2075 } 2076 2077 *s1 = '\0'; 2078 (void) get_expression (s); 2079 *s1 = ')'; 2080 s = s1 + 1; 2081 } 2082 if (*s == '\0') 2083 match = 1; 2084 break; 2085 2086 case '+': 2087 if (*s == '+') 2088 { 2089 ++s; 2090 continue; 2091 } 2092 if (*s == '-') 2093 { 2094 continue; 2095 } 2096 break; 2097 2098 case '[': /* These must match exactly. */ 2099 case ']': 2100 case ',': 2101 case ' ': 2102 if (*s++ == *args) 2103 continue; 2104 break; 2105 2106 case '#': /* Must be at least one digit. */ 2107 if (ISDIGIT (*s++)) 2108 { 2109 while (ISDIGIT (*s)) 2110 { 2111 ++s; 2112 } 2113 continue; 2114 } 2115 break; 2116 2117 case 'C': /* Coprocessor state register. */ 2118 if (strncmp (s, "%csr", 4) == 0) 2119 { 2120 s += 4; 2121 continue; 2122 } 2123 break; 2124 2125 case 'b': /* Next operand is a coprocessor register. */ 2126 case 'c': 2127 case 'D': 2128 if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s)) 2129 { 2130 mask = *s++; 2131 if (ISDIGIT (*s)) 2132 { 2133 mask = 10 * (mask - '0') + (*s++ - '0'); 2134 if (mask >= 32) 2135 { 2136 break; 2137 } 2138 } 2139 else 2140 { 2141 mask -= '0'; 2142 } 2143 switch (*args) 2144 { 2145 2146 case 'b': 2147 opcode |= mask << 14; 2148 continue; 2149 2150 case 'c': 2151 opcode |= mask; 2152 continue; 2153 2154 case 'D': 2155 opcode |= mask << 25; 2156 continue; 2157 } 2158 } 2159 break; 2160 2161 case 'r': /* next operand must be a register */ 2162 case 'O': 2163 case '1': 2164 case '2': 2165 case 'd': 2166 if (*s++ == '%') 2167 { 2168 switch (c = *s++) 2169 { 2170 2171 case 'f': /* frame pointer */ 2172 if (*s++ == 'p') 2173 { 2174 mask = 0x1e; 2175 break; 2176 } 2177 goto error; 2178 2179 case 'g': /* global register */ 2180 c = *s++; 2181 if (isoctal (c)) 2182 { 2183 mask = c - '0'; 2184 break; 2185 } 2186 goto error; 2187 2188 case 'i': /* in register */ 2189 c = *s++; 2190 if (isoctal (c)) 2191 { 2192 mask = c - '0' + 24; 2193 break; 2194 } 2195 goto error; 2196 2197 case 'l': /* local register */ 2198 c = *s++; 2199 if (isoctal (c)) 2200 { 2201 mask = (c - '0' + 16); 2202 break; 2203 } 2204 goto error; 2205 2206 case 'o': /* out register */ 2207 c = *s++; 2208 if (isoctal (c)) 2209 { 2210 mask = (c - '0' + 8); 2211 break; 2212 } 2213 goto error; 2214 2215 case 's': /* stack pointer */ 2216 if (*s++ == 'p') 2217 { 2218 mask = 0xe; 2219 break; 2220 } 2221 goto error; 2222 2223 case 'r': /* any register */ 2224 if (!ISDIGIT ((c = *s++))) 2225 { 2226 goto error; 2227 } 2228 /* FALLTHROUGH */ 2229 case '0': 2230 case '1': 2231 case '2': 2232 case '3': 2233 case '4': 2234 case '5': 2235 case '6': 2236 case '7': 2237 case '8': 2238 case '9': 2239 if (ISDIGIT (*s)) 2240 { 2241 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32) 2242 { 2243 goto error; 2244 } 2245 } 2246 else 2247 { 2248 c -= '0'; 2249 } 2250 mask = c; 2251 break; 2252 2253 default: 2254 goto error; 2255 } 2256 2257 if ((mask & ~1) == 2 && sparc_arch_size == 64 2258 && no_undeclared_regs && ! globals[mask]) 2259 as_bad (_("detected global register use not covered by .register pseudo-op")); 2260 2261 /* Got the register, now figure out where 2262 it goes in the opcode. */ 2263 switch (*args) 2264 { 2265 case '1': 2266 opcode |= mask << 14; 2267 continue; 2268 2269 case '2': 2270 opcode |= mask; 2271 continue; 2272 2273 case 'd': 2274 opcode |= mask << 25; 2275 continue; 2276 2277 case 'r': 2278 opcode |= (mask << 25) | (mask << 14); 2279 continue; 2280 2281 case 'O': 2282 opcode |= (mask << 25) | (mask << 0); 2283 continue; 2284 } 2285 } 2286 break; 2287 2288 case 'e': /* next operand is a floating point register */ 2289 case 'v': 2290 case 'V': 2291 2292 case 'f': 2293 case 'B': 2294 case 'R': 2295 2296 case '4': 2297 case '5': 2298 2299 case 'g': 2300 case 'H': 2301 case 'J': 2302 { 2303 char format; 2304 2305 if (*s++ == '%' 2306 && ((format = *s) == 'f') 2307 && ISDIGIT (*++s)) 2308 { 2309 for (mask = 0; ISDIGIT (*s); ++s) 2310 { 2311 mask = 10 * mask + (*s - '0'); 2312 } /* read the number */ 2313 2314 if ((*args == 'v' 2315 || *args == 'B' 2316 || *args == '5' 2317 || *args == 'H') 2318 && (mask & 1)) 2319 { 2320 break; 2321 } /* register must be even numbered */ 2322 2323 if ((*args == 'V' 2324 || *args == 'R' 2325 || *args == 'J') 2326 && (mask & 3)) 2327 { 2328 break; 2329 } /* register must be multiple of 4 */ 2330 2331 if (mask >= 64) 2332 { 2333 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 2334 error_message = _(": There are only 64 f registers; [0-63]"); 2335 else 2336 error_message = _(": There are only 32 f registers; [0-31]"); 2337 goto error; 2338 } /* on error */ 2339 else if (mask >= 32) 2340 { 2341 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 2342 { 2343 if (*args == 'e' || *args == 'f' || *args == 'g') 2344 { 2345 error_message 2346 = _(": There are only 32 single precision f registers; [0-31]"); 2347 goto error; 2348 } 2349 v9_arg_p = 1; 2350 mask -= 31; /* wrap high bit */ 2351 } 2352 else 2353 { 2354 error_message = _(": There are only 32 f registers; [0-31]"); 2355 goto error; 2356 } 2357 } 2358 } 2359 else 2360 { 2361 break; 2362 } /* if not an 'f' register. */ 2363 2364 switch (*args) 2365 { 2366 case 'v': 2367 case 'V': 2368 case 'e': 2369 opcode |= RS1 (mask); 2370 continue; 2371 2372 case 'f': 2373 case 'B': 2374 case 'R': 2375 opcode |= RS2 (mask); 2376 continue; 2377 2378 case '4': 2379 case '5': 2380 opcode |= RS3 (mask); 2381 continue; 2382 2383 case 'g': 2384 case 'H': 2385 case 'J': 2386 opcode |= RD (mask); 2387 continue; 2388 } /* Pack it in. */ 2389 2390 know (0); 2391 break; 2392 } /* float arg */ 2393 2394 case 'F': 2395 if (strncmp (s, "%fsr", 4) == 0) 2396 { 2397 s += 4; 2398 continue; 2399 } 2400 break; 2401 2402 case '(': 2403 if (strncmp (s, "%efsr", 5) == 0) 2404 { 2405 s += 5; 2406 continue; 2407 } 2408 break; 2409 2410 case '0': /* 64 bit immediate (set, setsw, setx insn) */ 2411 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */ 2412 goto immediate; 2413 2414 case 'l': /* 22 bit PC relative immediate */ 2415 the_insn.reloc = BFD_RELOC_SPARC_WDISP22; 2416 the_insn.pcrel = 1; 2417 goto immediate; 2418 2419 case 'L': /* 30 bit immediate */ 2420 the_insn.reloc = BFD_RELOC_32_PCREL_S2; 2421 the_insn.pcrel = 1; 2422 goto immediate; 2423 2424 case 'h': 2425 case 'n': /* 22 bit immediate */ 2426 the_insn.reloc = BFD_RELOC_SPARC22; 2427 goto immediate; 2428 2429 case 'i': /* 13 bit immediate */ 2430 the_insn.reloc = BFD_RELOC_SPARC13; 2431 2432 /* fallthrough */ 2433 2434 immediate: 2435 if (*s == ' ') 2436 s++; 2437 2438 { 2439 char *s1; 2440 char *op_arg = NULL; 2441 static expressionS op_exp; 2442 bfd_reloc_code_real_type old_reloc = the_insn.reloc; 2443 2444 /* Check for %hi, etc. */ 2445 if (*s == '%') 2446 { 2447 static const struct ops { 2448 /* The name as it appears in assembler. */ 2449 char *name; 2450 /* strlen (name), precomputed for speed */ 2451 int len; 2452 /* The reloc this pseudo-op translates to. */ 2453 int reloc; 2454 /* Non-zero if for v9 only. */ 2455 int v9_p; 2456 /* Non-zero if can be used in pc-relative contexts. */ 2457 int pcrel_p;/*FIXME:wip*/ 2458 } ops[] = { 2459 /* hix/lox must appear before hi/lo so %hix won't be 2460 mistaken for %hi. */ 2461 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 }, 2462 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 }, 2463 { "hi", 2, BFD_RELOC_HI22, 0, 1 }, 2464 { "lo", 2, BFD_RELOC_LO10, 0, 1 }, 2465 { "pc22", 4, BFD_RELOC_SPARC_PC22, 0, 1 }, 2466 { "pc10", 4, BFD_RELOC_SPARC_PC10, 0, 1 }, 2467 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 }, 2468 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 }, 2469 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 }, 2470 { "h34", 3, BFD_RELOC_SPARC_H34, 1, 0 }, 2471 { "l34", 3, BFD_RELOC_SPARC_L44, 1, 0 }, 2472 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 }, 2473 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 }, 2474 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 }, 2475 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 }, 2476 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 }, 2477 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22, 0, 0 }, 2478 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10, 0, 0 }, 2479 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22, 0, 0 }, 2480 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10, 0, 0 }, 2481 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22, 0, 2482 0 }, 2483 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10, 0, 2484 0 }, 2485 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22, 0, 0 }, 2486 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10, 0, 0 }, 2487 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22, 0, 0 }, 2488 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10, 0, 0 }, 2489 { "gdop_hix22", 10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22, 2490 0, 0 }, 2491 { "gdop_lox10", 10, BFD_RELOC_SPARC_GOTDATA_OP_LOX10, 2492 0, 0 }, 2493 { NULL, 0, 0, 0, 0 } 2494 }; 2495 const struct ops *o; 2496 2497 for (o = ops; o->name; o++) 2498 if (strncmp (s + 1, o->name, o->len) == 0) 2499 break; 2500 if (o->name == NULL) 2501 break; 2502 2503 if (s[o->len + 1] != '(') 2504 { 2505 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); 2506 return special_case; 2507 } 2508 2509 op_arg = o->name; 2510 the_insn.reloc = o->reloc; 2511 s += o->len + 2; 2512 v9_arg_p = o->v9_p; 2513 } 2514 2515 /* Note that if the get_expression() fails, we will still 2516 have created U entries in the symbol table for the 2517 'symbols' in the input string. Try not to create U 2518 symbols for registers, etc. */ 2519 2520 /* This stuff checks to see if the expression ends in 2521 +%reg. If it does, it removes the register from 2522 the expression, and re-sets 's' to point to the 2523 right place. */ 2524 2525 if (op_arg) 2526 { 2527 int npar = 0; 2528 2529 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) 2530 if (*s1 == '(') 2531 npar++; 2532 else if (*s1 == ')') 2533 { 2534 if (!npar) 2535 break; 2536 npar--; 2537 } 2538 2539 if (*s1 != ')') 2540 { 2541 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg); 2542 return special_case; 2543 } 2544 2545 *s1 = '\0'; 2546 (void) get_expression (s); 2547 *s1 = ')'; 2548 s = s1 + 1; 2549 if (*s == ',' || *s == ']' || !*s) 2550 continue; 2551 if (*s != '+' && *s != '-') 2552 { 2553 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg); 2554 return special_case; 2555 } 2556 *s1 = '0'; 2557 s = s1; 2558 op_exp = the_insn.exp; 2559 memset (&the_insn.exp, 0, sizeof (the_insn.exp)); 2560 } 2561 2562 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) 2563 ; 2564 2565 if (s1 != s && ISDIGIT (s1[-1])) 2566 { 2567 if (s1[-2] == '%' && s1[-3] == '+') 2568 s1 -= 3; 2569 else if (strchr ("golir0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+') 2570 s1 -= 4; 2571 else if (s1[-3] == 'r' && s1[-4] == '%' && s1[-5] == '+') 2572 s1 -= 5; 2573 else 2574 s1 = NULL; 2575 if (s1) 2576 { 2577 *s1 = '\0'; 2578 if (op_arg && s1 == s + 1) 2579 the_insn.exp.X_op = O_absent; 2580 else 2581 (void) get_expression (s); 2582 *s1 = '+'; 2583 if (op_arg) 2584 *s = ')'; 2585 s = s1; 2586 } 2587 } 2588 else 2589 s1 = NULL; 2590 2591 if (!s1) 2592 { 2593 (void) get_expression (s); 2594 if (op_arg) 2595 *s = ')'; 2596 s = expr_end; 2597 } 2598 2599 if (op_arg) 2600 { 2601 the_insn.exp2 = the_insn.exp; 2602 the_insn.exp = op_exp; 2603 if (the_insn.exp2.X_op == O_absent) 2604 the_insn.exp2.X_op = O_illegal; 2605 else if (the_insn.exp.X_op == O_absent) 2606 { 2607 the_insn.exp = the_insn.exp2; 2608 the_insn.exp2.X_op = O_illegal; 2609 } 2610 else if (the_insn.exp.X_op == O_constant) 2611 { 2612 valueT val = the_insn.exp.X_add_number; 2613 switch (the_insn.reloc) 2614 { 2615 default: 2616 break; 2617 2618 case BFD_RELOC_SPARC_HH22: 2619 val = BSR (val, 32); 2620 /* Fall through. */ 2621 2622 case BFD_RELOC_SPARC_LM22: 2623 case BFD_RELOC_HI22: 2624 val = (val >> 10) & 0x3fffff; 2625 break; 2626 2627 case BFD_RELOC_SPARC_HM10: 2628 val = BSR (val, 32); 2629 /* Fall through. */ 2630 2631 case BFD_RELOC_LO10: 2632 val &= 0x3ff; 2633 break; 2634 2635 case BFD_RELOC_SPARC_H34: 2636 val >>= 12; 2637 val &= 0x3fffff; 2638 break; 2639 2640 case BFD_RELOC_SPARC_H44: 2641 val >>= 22; 2642 val &= 0x3fffff; 2643 break; 2644 2645 case BFD_RELOC_SPARC_M44: 2646 val >>= 12; 2647 val &= 0x3ff; 2648 break; 2649 2650 case BFD_RELOC_SPARC_L44: 2651 val &= 0xfff; 2652 break; 2653 2654 case BFD_RELOC_SPARC_HIX22: 2655 val = ~val; 2656 val = (val >> 10) & 0x3fffff; 2657 break; 2658 2659 case BFD_RELOC_SPARC_LOX10: 2660 val = (val & 0x3ff) | 0x1c00; 2661 break; 2662 } 2663 the_insn.exp = the_insn.exp2; 2664 the_insn.exp.X_add_number += val; 2665 the_insn.exp2.X_op = O_illegal; 2666 the_insn.reloc = old_reloc; 2667 } 2668 else if (the_insn.exp2.X_op != O_constant) 2669 { 2670 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg); 2671 return special_case; 2672 } 2673 else 2674 { 2675 if (old_reloc != BFD_RELOC_SPARC13 2676 || the_insn.reloc != BFD_RELOC_LO10 2677 || sparc_arch_size != 64 2678 || sparc_pic_code) 2679 { 2680 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg); 2681 return special_case; 2682 } 2683 the_insn.reloc = BFD_RELOC_SPARC_OLO10; 2684 } 2685 } 2686 } 2687 /* Check for constants that don't require emitting a reloc. */ 2688 if (the_insn.exp.X_op == O_constant 2689 && the_insn.exp.X_add_symbol == 0 2690 && the_insn.exp.X_op_symbol == 0) 2691 { 2692 /* For pc-relative call instructions, we reject 2693 constants to get better code. */ 2694 if (the_insn.pcrel 2695 && the_insn.reloc == BFD_RELOC_32_PCREL_S2 2696 && in_signed_range (the_insn.exp.X_add_number, 0x3fff)) 2697 { 2698 error_message = _(": PC-relative operand can't be a constant"); 2699 goto error; 2700 } 2701 2702 if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22 2703 && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64) 2704 { 2705 error_message = _(": TLS operand can't be a constant"); 2706 goto error; 2707 } 2708 2709 /* Constants that won't fit are checked in md_apply_fix 2710 and bfd_install_relocation. 2711 ??? It would be preferable to install the constants 2712 into the insn here and save having to create a fixS 2713 for each one. There already exists code to handle 2714 all the various cases (e.g. in md_apply_fix and 2715 bfd_install_relocation) so duplicating all that code 2716 here isn't right. */ 2717 2718 /* This is a special case to handle cbcond instructions 2719 properly, which can need two relocations. The first 2720 one is for the 5-bit immediate field and the latter 2721 is going to be for the WDISP10 branch part. We 2722 handle the R_SPARC_5 immediate directly here so that 2723 we don't need to add support for multiple relocations 2724 in one instruction just yet. */ 2725 if (the_insn.reloc == BFD_RELOC_SPARC_5) 2726 { 2727 valueT val = the_insn.exp.X_add_number; 2728 2729 if (! in_bitfield_range (val, 0x1f)) 2730 { 2731 error_message = _(": Immediate value in cbcond is out of range."); 2732 goto error; 2733 } 2734 opcode |= val & 0x1f; 2735 the_insn.reloc = BFD_RELOC_NONE; 2736 } 2737 } 2738 2739 continue; 2740 2741 case 'a': 2742 if (*s++ == 'a') 2743 { 2744 opcode |= ANNUL; 2745 continue; 2746 } 2747 break; 2748 2749 case 'A': 2750 { 2751 int asi = 0; 2752 2753 /* Parse an asi. */ 2754 if (*s == '#') 2755 { 2756 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi)) 2757 { 2758 error_message = _(": invalid ASI name"); 2759 goto error; 2760 } 2761 } 2762 else 2763 { 2764 if (! parse_const_expr_arg (&s, &asi)) 2765 { 2766 error_message = _(": invalid ASI expression"); 2767 goto error; 2768 } 2769 if (asi < 0 || asi > 255) 2770 { 2771 error_message = _(": invalid ASI number"); 2772 goto error; 2773 } 2774 } 2775 opcode |= ASI (asi); 2776 continue; 2777 } /* Alternate space. */ 2778 2779 case 'p': 2780 if (strncmp (s, "%psr", 4) == 0) 2781 { 2782 s += 4; 2783 continue; 2784 } 2785 break; 2786 2787 case 'q': /* Floating point queue. */ 2788 if (strncmp (s, "%fq", 3) == 0) 2789 { 2790 s += 3; 2791 continue; 2792 } 2793 break; 2794 2795 case 'Q': /* Coprocessor queue. */ 2796 if (strncmp (s, "%cq", 3) == 0) 2797 { 2798 s += 3; 2799 continue; 2800 } 2801 break; 2802 2803 case 'S': 2804 if (strcmp (str, "set") == 0 2805 || strcmp (str, "setuw") == 0) 2806 { 2807 special_case = SPECIAL_CASE_SET; 2808 continue; 2809 } 2810 else if (strcmp (str, "setsw") == 0) 2811 { 2812 special_case = SPECIAL_CASE_SETSW; 2813 continue; 2814 } 2815 else if (strcmp (str, "setx") == 0) 2816 { 2817 special_case = SPECIAL_CASE_SETX; 2818 continue; 2819 } 2820 else if (strncmp (str, "fdiv", 4) == 0) 2821 { 2822 special_case = SPECIAL_CASE_FDIV; 2823 continue; 2824 } 2825 break; 2826 2827 case 'o': 2828 if (strncmp (s, "%asi", 4) != 0) 2829 break; 2830 s += 4; 2831 continue; 2832 2833 case 's': 2834 if (strncmp (s, "%fprs", 5) != 0) 2835 break; 2836 s += 5; 2837 continue; 2838 2839 case 'E': 2840 if (strncmp (s, "%ccr", 4) != 0) 2841 break; 2842 s += 4; 2843 continue; 2844 2845 case 't': 2846 if (strncmp (s, "%tbr", 4) != 0) 2847 break; 2848 s += 4; 2849 continue; 2850 2851 case 'w': 2852 if (strncmp (s, "%wim", 4) != 0) 2853 break; 2854 s += 4; 2855 continue; 2856 2857 case 'x': 2858 { 2859 char *push = input_line_pointer; 2860 expressionS e; 2861 2862 input_line_pointer = s; 2863 expression (&e); 2864 if (e.X_op == O_constant) 2865 { 2866 int n = e.X_add_number; 2867 if (n != e.X_add_number || (n & ~0x1ff) != 0) 2868 as_bad (_("OPF immediate operand out of range (0-0x1ff)")); 2869 else 2870 opcode |= e.X_add_number << 5; 2871 } 2872 else 2873 as_bad (_("non-immediate OPF operand, ignored")); 2874 s = input_line_pointer; 2875 input_line_pointer = push; 2876 continue; 2877 } 2878 2879 case 'y': 2880 if (strncmp (s, "%y", 2) != 0) 2881 break; 2882 s += 2; 2883 continue; 2884 2885 case 'u': 2886 case 'U': 2887 { 2888 /* Parse a sparclet cpreg. */ 2889 int cpreg; 2890 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg)) 2891 { 2892 error_message = _(": invalid cpreg name"); 2893 goto error; 2894 } 2895 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg)); 2896 continue; 2897 } 2898 2899 default: 2900 as_fatal (_("failed sanity check.")); 2901 } /* switch on arg code. */ 2902 2903 /* Break out of for() loop. */ 2904 break; 2905 } /* For each arg that we expect. */ 2906 2907 error: 2908 if (match == 0) 2909 { 2910 /* Args don't match. */ 2911 if (&insn[1] - sparc_opcodes < sparc_num_opcodes 2912 && (insn->name == insn[1].name 2913 || !strcmp (insn->name, insn[1].name))) 2914 { 2915 ++insn; 2916 s = argsStart; 2917 continue; 2918 } 2919 else 2920 { 2921 as_bad (_("Illegal operands%s"), error_message); 2922 return special_case; 2923 } 2924 } 2925 else 2926 { 2927 /* We have a match. Now see if the architecture is OK. */ 2928 int needed_arch_mask = insn->architecture; 2929 int hwcaps = insn->hwcaps; 2930 2931 #if defined(OBJ_ELF) && !defined(TE_SOLARIS) 2932 if (hwcaps) 2933 hwcap_seen |= hwcaps; 2934 #endif 2935 if (v9_arg_p) 2936 { 2937 needed_arch_mask &= 2938 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1); 2939 if (! needed_arch_mask) 2940 needed_arch_mask = 2941 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); 2942 } 2943 2944 if (needed_arch_mask 2945 & SPARC_OPCODE_SUPPORTED (current_architecture)) 2946 /* OK. */ 2947 ; 2948 /* Can we bump up the architecture? */ 2949 else if (needed_arch_mask 2950 & SPARC_OPCODE_SUPPORTED (max_architecture)) 2951 { 2952 enum sparc_opcode_arch_val needed_architecture = 2953 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture) 2954 & needed_arch_mask); 2955 2956 gas_assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX); 2957 if (warn_on_bump 2958 && needed_architecture > warn_after_architecture) 2959 { 2960 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""), 2961 sparc_opcode_archs[current_architecture].name, 2962 sparc_opcode_archs[needed_architecture].name, 2963 str); 2964 warn_after_architecture = needed_architecture; 2965 } 2966 current_architecture = needed_architecture; 2967 } 2968 /* Conflict. */ 2969 /* ??? This seems to be a bit fragile. What if the next entry in 2970 the opcode table is the one we want and it is supported? 2971 It is possible to arrange the table today so that this can't 2972 happen but what about tomorrow? */ 2973 else 2974 { 2975 int arch, printed_one_p = 0; 2976 char *p; 2977 char required_archs[SPARC_OPCODE_ARCH_MAX * 16]; 2978 2979 /* Create a list of the architectures that support the insn. */ 2980 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture); 2981 p = required_archs; 2982 arch = sparc_ffs (needed_arch_mask); 2983 while ((1 << arch) <= needed_arch_mask) 2984 { 2985 if ((1 << arch) & needed_arch_mask) 2986 { 2987 if (printed_one_p) 2988 *p++ = '|'; 2989 strcpy (p, sparc_opcode_archs[arch].name); 2990 p += strlen (p); 2991 printed_one_p = 1; 2992 } 2993 ++arch; 2994 } 2995 2996 as_bad (_("Architecture mismatch on \"%s\"."), str); 2997 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"), 2998 required_archs, 2999 sparc_opcode_archs[max_architecture].name); 3000 return special_case; 3001 } 3002 3003 /* Make sure the the hwcaps used by the instruction are 3004 currently enabled. */ 3005 if (hwcaps & ~hwcap_allowed) 3006 { 3007 const char *hwcap_name = get_hwcap_name(hwcaps & ~hwcap_allowed); 3008 3009 as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."), 3010 hwcap_name, str); 3011 return special_case; 3012 } 3013 } /* If no match. */ 3014 3015 break; 3016 } /* Forever looking for a match. */ 3017 3018 the_insn.opcode = opcode; 3019 return special_case; 3020 } 3021 3022 /* Parse an argument that can be expressed as a keyword. 3023 (eg: #StoreStore or %ccfr). 3024 The result is a boolean indicating success. 3025 If successful, INPUT_POINTER is updated. */ 3026 3027 static int 3028 parse_keyword_arg (int (*lookup_fn) (const char *), 3029 char **input_pointerP, 3030 int *valueP) 3031 { 3032 int value; 3033 char c, *p, *q; 3034 3035 p = *input_pointerP; 3036 for (q = p + (*p == '#' || *p == '%'); 3037 ISALNUM (*q) || *q == '_'; 3038 ++q) 3039 continue; 3040 c = *q; 3041 *q = 0; 3042 value = (*lookup_fn) (p); 3043 *q = c; 3044 if (value == -1) 3045 return 0; 3046 *valueP = value; 3047 *input_pointerP = q; 3048 return 1; 3049 } 3050 3051 /* Parse an argument that is a constant expression. 3052 The result is a boolean indicating success. */ 3053 3054 static int 3055 parse_const_expr_arg (char **input_pointerP, int *valueP) 3056 { 3057 char *save = input_line_pointer; 3058 expressionS exp; 3059 3060 input_line_pointer = *input_pointerP; 3061 /* The next expression may be something other than a constant 3062 (say if we're not processing the right variant of the insn). 3063 Don't call expression unless we're sure it will succeed as it will 3064 signal an error (which we want to defer until later). */ 3065 /* FIXME: It might be better to define md_operand and have it recognize 3066 things like %asi, etc. but continuing that route through to the end 3067 is a lot of work. */ 3068 if (*input_line_pointer == '%') 3069 { 3070 input_line_pointer = save; 3071 return 0; 3072 } 3073 expression (&exp); 3074 *input_pointerP = input_line_pointer; 3075 input_line_pointer = save; 3076 if (exp.X_op != O_constant) 3077 return 0; 3078 *valueP = exp.X_add_number; 3079 return 1; 3080 } 3081 3082 /* Subroutine of sparc_ip to parse an expression. */ 3083 3084 static int 3085 get_expression (char *str) 3086 { 3087 char *save_in; 3088 segT seg; 3089 3090 save_in = input_line_pointer; 3091 input_line_pointer = str; 3092 seg = expression (&the_insn.exp); 3093 if (seg != absolute_section 3094 && seg != text_section 3095 && seg != data_section 3096 && seg != bss_section 3097 && seg != undefined_section) 3098 { 3099 the_insn.error = _("bad segment"); 3100 expr_end = input_line_pointer; 3101 input_line_pointer = save_in; 3102 return 1; 3103 } 3104 expr_end = input_line_pointer; 3105 input_line_pointer = save_in; 3106 return 0; 3107 } 3108 3109 /* Subroutine of md_assemble to output one insn. */ 3110 3111 static void 3112 output_insn (const struct sparc_opcode *insn, struct sparc_it *theinsn) 3113 { 3114 char *toP = frag_more (4); 3115 3116 /* Put out the opcode. */ 3117 if (INSN_BIG_ENDIAN) 3118 number_to_chars_bigendian (toP, (valueT) theinsn->opcode, 4); 3119 else 3120 number_to_chars_littleendian (toP, (valueT) theinsn->opcode, 4); 3121 3122 /* Put out the symbol-dependent stuff. */ 3123 if (theinsn->reloc != BFD_RELOC_NONE) 3124 { 3125 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */ 3126 (toP - frag_now->fr_literal), /* Where. */ 3127 4, /* Size. */ 3128 &theinsn->exp, 3129 theinsn->pcrel, 3130 theinsn->reloc); 3131 /* Turn off overflow checking in fixup_segment. We'll do our 3132 own overflow checking in md_apply_fix. This is necessary because 3133 the insn size is 4 and fixup_segment will signal an overflow for 3134 large 8 byte quantities. */ 3135 fixP->fx_no_overflow = 1; 3136 if (theinsn->reloc == BFD_RELOC_SPARC_OLO10) 3137 fixP->tc_fix_data = theinsn->exp2.X_add_number; 3138 } 3139 3140 last_insn = insn; 3141 last_opcode = theinsn->opcode; 3142 3143 #ifdef OBJ_ELF 3144 dwarf2_emit_insn (4); 3145 #endif 3146 } 3147 3148 char * 3150 md_atof (int type, char *litP, int *sizeP) 3151 { 3152 return ieee_md_atof (type, litP, sizeP, target_big_endian); 3153 } 3154 3155 /* Write a value out to the object file, using the appropriate 3156 endianness. */ 3157 3158 void 3159 md_number_to_chars (char *buf, valueT val, int n) 3160 { 3161 if (target_big_endian) 3162 number_to_chars_bigendian (buf, val, n); 3163 else if (target_little_endian_data 3164 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC)) 3165 /* Output debug words, which are not in allocated sections, as big 3166 endian. */ 3167 number_to_chars_bigendian (buf, val, n); 3168 else if (target_little_endian_data || ! target_big_endian) 3169 number_to_chars_littleendian (buf, val, n); 3170 } 3171 3172 /* Apply a fixS to the frags, now that we know the value it ought to 3174 hold. */ 3175 3176 void 3177 md_apply_fix (fixS *fixP, valueT *valP, segT segment ATTRIBUTE_UNUSED) 3178 { 3179 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; 3180 offsetT val = * (offsetT *) valP; 3181 long insn; 3182 3183 gas_assert (fixP->fx_r_type < BFD_RELOC_UNUSED); 3184 3185 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ 3186 3187 #ifdef OBJ_ELF 3188 /* SPARC ELF relocations don't use an addend in the data field. */ 3189 if (fixP->fx_addsy != NULL) 3190 { 3191 switch (fixP->fx_r_type) 3192 { 3193 case BFD_RELOC_SPARC_TLS_GD_HI22: 3194 case BFD_RELOC_SPARC_TLS_GD_LO10: 3195 case BFD_RELOC_SPARC_TLS_GD_ADD: 3196 case BFD_RELOC_SPARC_TLS_GD_CALL: 3197 case BFD_RELOC_SPARC_TLS_LDM_HI22: 3198 case BFD_RELOC_SPARC_TLS_LDM_LO10: 3199 case BFD_RELOC_SPARC_TLS_LDM_ADD: 3200 case BFD_RELOC_SPARC_TLS_LDM_CALL: 3201 case BFD_RELOC_SPARC_TLS_LDO_HIX22: 3202 case BFD_RELOC_SPARC_TLS_LDO_LOX10: 3203 case BFD_RELOC_SPARC_TLS_LDO_ADD: 3204 case BFD_RELOC_SPARC_TLS_IE_HI22: 3205 case BFD_RELOC_SPARC_TLS_IE_LO10: 3206 case BFD_RELOC_SPARC_TLS_IE_LD: 3207 case BFD_RELOC_SPARC_TLS_IE_LDX: 3208 case BFD_RELOC_SPARC_TLS_IE_ADD: 3209 case BFD_RELOC_SPARC_TLS_LE_HIX22: 3210 case BFD_RELOC_SPARC_TLS_LE_LOX10: 3211 case BFD_RELOC_SPARC_TLS_DTPMOD32: 3212 case BFD_RELOC_SPARC_TLS_DTPMOD64: 3213 case BFD_RELOC_SPARC_TLS_DTPOFF32: 3214 case BFD_RELOC_SPARC_TLS_DTPOFF64: 3215 case BFD_RELOC_SPARC_TLS_TPOFF32: 3216 case BFD_RELOC_SPARC_TLS_TPOFF64: 3217 S_SET_THREAD_LOCAL (fixP->fx_addsy); 3218 3219 default: 3220 break; 3221 } 3222 3223 return; 3224 } 3225 #endif 3226 3227 /* This is a hack. There should be a better way to 3228 handle this. Probably in terms of howto fields, once 3229 we can look at these fixups in terms of howtos. */ 3230 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy) 3231 val += fixP->fx_where + fixP->fx_frag->fr_address; 3232 3233 #ifdef OBJ_AOUT 3234 /* FIXME: More ridiculous gas reloc hacking. If we are going to 3235 generate a reloc, then we just want to let the reloc addend set 3236 the value. We do not want to also stuff the addend into the 3237 object file. Including the addend in the object file works when 3238 doing a static link, because the linker will ignore the object 3239 file contents. However, the dynamic linker does not ignore the 3240 object file contents. */ 3241 if (fixP->fx_addsy != NULL 3242 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2) 3243 val = 0; 3244 3245 /* When generating PIC code, we do not want an addend for a reloc 3246 against a local symbol. We adjust fx_addnumber to cancel out the 3247 value already included in val, and to also cancel out the 3248 adjustment which bfd_install_relocation will create. */ 3249 if (sparc_pic_code 3250 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2 3251 && fixP->fx_addsy != NULL 3252 && ! S_IS_COMMON (fixP->fx_addsy) 3253 && symbol_section_p (fixP->fx_addsy)) 3254 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); 3255 3256 /* When generating PIC code, we need to fiddle to get 3257 bfd_install_relocation to do the right thing for a PC relative 3258 reloc against a local symbol which we are going to keep. */ 3259 if (sparc_pic_code 3260 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 3261 && fixP->fx_addsy != NULL 3262 && (S_IS_EXTERNAL (fixP->fx_addsy) 3263 || S_IS_WEAK (fixP->fx_addsy)) 3264 && S_IS_DEFINED (fixP->fx_addsy) 3265 && ! S_IS_COMMON (fixP->fx_addsy)) 3266 { 3267 val = 0; 3268 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); 3269 } 3270 #endif 3271 3272 /* If this is a data relocation, just output VAL. */ 3273 3274 if (fixP->fx_r_type == BFD_RELOC_8) 3275 { 3276 md_number_to_chars (buf, val, 1); 3277 } 3278 else if (fixP->fx_r_type == BFD_RELOC_16 3279 || fixP->fx_r_type == BFD_RELOC_SPARC_UA16) 3280 { 3281 md_number_to_chars (buf, val, 2); 3282 } 3283 else if (fixP->fx_r_type == BFD_RELOC_32 3284 || fixP->fx_r_type == BFD_RELOC_SPARC_UA32 3285 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32) 3286 { 3287 md_number_to_chars (buf, val, 4); 3288 } 3289 else if (fixP->fx_r_type == BFD_RELOC_64 3290 || fixP->fx_r_type == BFD_RELOC_SPARC_UA64) 3291 { 3292 md_number_to_chars (buf, val, 8); 3293 } 3294 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 3295 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 3296 { 3297 fixP->fx_done = 0; 3298 return; 3299 } 3300 else 3301 { 3302 /* It's a relocation against an instruction. */ 3303 3304 if (INSN_BIG_ENDIAN) 3305 insn = bfd_getb32 ((unsigned char *) buf); 3306 else 3307 insn = bfd_getl32 ((unsigned char *) buf); 3308 3309 switch (fixP->fx_r_type) 3310 { 3311 case BFD_RELOC_32_PCREL_S2: 3312 val = val >> 2; 3313 /* FIXME: This increment-by-one deserves a comment of why it's 3314 being done! */ 3315 if (! sparc_pic_code 3316 || fixP->fx_addsy == NULL 3317 || symbol_section_p (fixP->fx_addsy)) 3318 ++val; 3319 3320 insn |= val & 0x3fffffff; 3321 3322 /* See if we have a delay slot. */ 3323 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix) 3324 { 3325 #define G0 0 3326 #define O7 15 3327 #define XCC (2 << 20) 3328 #define COND(x) (((x)&0xf)<<25) 3329 #define CONDA COND(0x8) 3330 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC) 3331 #define INSN_BA (F2(0,2) | CONDA) 3332 #define INSN_OR F3(2, 0x2, 0) 3333 #define INSN_NOP F2(0,4) 3334 3335 long delay; 3336 3337 /* If the instruction is a call with either: 3338 restore 3339 arithmetic instruction with rd == %o7 3340 where rs1 != %o7 and rs2 if it is register != %o7 3341 then we can optimize if the call destination is near 3342 by changing the call into a branch always. */ 3343 if (INSN_BIG_ENDIAN) 3344 delay = bfd_getb32 ((unsigned char *) buf + 4); 3345 else 3346 delay = bfd_getl32 ((unsigned char *) buf + 4); 3347 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2)) 3348 break; 3349 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */ 3350 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */ 3351 || ((delay & RD (~0)) != RD (O7)))) 3352 break; 3353 if ((delay & RS1 (~0)) == RS1 (O7) 3354 || ((delay & F3I (~0)) == 0 3355 && (delay & RS2 (~0)) == RS2 (O7))) 3356 break; 3357 /* Ensure the branch will fit into simm22. */ 3358 if ((val & 0x3fe00000) 3359 && (val & 0x3fe00000) != 0x3fe00000) 3360 break; 3361 /* Check if the arch is v9 and branch will fit 3362 into simm19. */ 3363 if (((val & 0x3c0000) == 0 3364 || (val & 0x3c0000) == 0x3c0000) 3365 && (sparc_arch_size == 64 3366 || current_architecture >= SPARC_OPCODE_ARCH_V9)) 3367 /* ba,pt %xcc */ 3368 insn = INSN_BPA | (val & 0x7ffff); 3369 else 3370 /* ba */ 3371 insn = INSN_BA | (val & 0x3fffff); 3372 if (fixP->fx_where >= 4 3373 && ((delay & (0xffffffff ^ RS1 (~0))) 3374 == (INSN_OR | RD (O7) | RS2 (G0)))) 3375 { 3376 long setter; 3377 int reg; 3378 3379 if (INSN_BIG_ENDIAN) 3380 setter = bfd_getb32 ((unsigned char *) buf - 4); 3381 else 3382 setter = bfd_getl32 ((unsigned char *) buf - 4); 3383 if ((setter & (0xffffffff ^ RD (~0))) 3384 != (INSN_OR | RS1 (O7) | RS2 (G0))) 3385 break; 3386 /* The sequence was 3387 or %o7, %g0, %rN 3388 call foo 3389 or %rN, %g0, %o7 3390 3391 If call foo was replaced with ba, replace 3392 or %rN, %g0, %o7 with nop. */ 3393 reg = (delay & RS1 (~0)) >> 14; 3394 if (reg != ((setter & RD (~0)) >> 25) 3395 || reg == G0 || reg == O7) 3396 break; 3397 3398 if (INSN_BIG_ENDIAN) 3399 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4); 3400 else 3401 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4); 3402 } 3403 } 3404 break; 3405 3406 case BFD_RELOC_SPARC_11: 3407 if (! in_signed_range (val, 0x7ff)) 3408 as_bad_where (fixP->fx_file, fixP->fx_line, 3409 _("relocation overflow")); 3410 insn |= val & 0x7ff; 3411 break; 3412 3413 case BFD_RELOC_SPARC_10: 3414 if (! in_signed_range (val, 0x3ff)) 3415 as_bad_where (fixP->fx_file, fixP->fx_line, 3416 _("relocation overflow")); 3417 insn |= val & 0x3ff; 3418 break; 3419 3420 case BFD_RELOC_SPARC_7: 3421 if (! in_bitfield_range (val, 0x7f)) 3422 as_bad_where (fixP->fx_file, fixP->fx_line, 3423 _("relocation overflow")); 3424 insn |= val & 0x7f; 3425 break; 3426 3427 case BFD_RELOC_SPARC_6: 3428 if (! in_bitfield_range (val, 0x3f)) 3429 as_bad_where (fixP->fx_file, fixP->fx_line, 3430 _("relocation overflow")); 3431 insn |= val & 0x3f; 3432 break; 3433 3434 case BFD_RELOC_SPARC_5: 3435 if (! in_bitfield_range (val, 0x1f)) 3436 as_bad_where (fixP->fx_file, fixP->fx_line, 3437 _("relocation overflow")); 3438 insn |= val & 0x1f; 3439 break; 3440 3441 case BFD_RELOC_SPARC_WDISP10: 3442 if ((val & 3) 3443 || val >= 0x007fc 3444 || val <= -(offsetT) 0x808) 3445 as_bad_where (fixP->fx_file, fixP->fx_line, 3446 _("relocation overflow")); 3447 /* FIXME: The +1 deserves a comment. */ 3448 val = (val >> 2) + 1; 3449 insn |= ((val & 0x300) << 11) 3450 | ((val & 0xff) << 5); 3451 break; 3452 3453 case BFD_RELOC_SPARC_WDISP16: 3454 if ((val & 3) 3455 || val >= 0x1fffc 3456 || val <= -(offsetT) 0x20008) 3457 as_bad_where (fixP->fx_file, fixP->fx_line, 3458 _("relocation overflow")); 3459 /* FIXME: The +1 deserves a comment. */ 3460 val = (val >> 2) + 1; 3461 insn |= ((val & 0xc000) << 6) | (val & 0x3fff); 3462 break; 3463 3464 case BFD_RELOC_SPARC_WDISP19: 3465 if ((val & 3) 3466 || val >= 0xffffc 3467 || val <= -(offsetT) 0x100008) 3468 as_bad_where (fixP->fx_file, fixP->fx_line, 3469 _("relocation overflow")); 3470 /* FIXME: The +1 deserves a comment. */ 3471 val = (val >> 2) + 1; 3472 insn |= val & 0x7ffff; 3473 break; 3474 3475 case BFD_RELOC_SPARC_HH22: 3476 val = BSR (val, 32); 3477 /* Fall through. */ 3478 3479 case BFD_RELOC_SPARC_LM22: 3480 case BFD_RELOC_HI22: 3481 if (!fixP->fx_addsy) 3482 insn |= (val >> 10) & 0x3fffff; 3483 else 3484 /* FIXME: Need comment explaining why we do this. */ 3485 insn &= ~0xffff; 3486 break; 3487 3488 case BFD_RELOC_SPARC22: 3489 if (val & ~0x003fffff) 3490 as_bad_where (fixP->fx_file, fixP->fx_line, 3491 _("relocation overflow")); 3492 insn |= (val & 0x3fffff); 3493 break; 3494 3495 case BFD_RELOC_SPARC_HM10: 3496 val = BSR (val, 32); 3497 /* Fall through. */ 3498 3499 case BFD_RELOC_LO10: 3500 if (!fixP->fx_addsy) 3501 insn |= val & 0x3ff; 3502 else 3503 /* FIXME: Need comment explaining why we do this. */ 3504 insn &= ~0xff; 3505 break; 3506 3507 case BFD_RELOC_SPARC_OLO10: 3508 val &= 0x3ff; 3509 val += fixP->tc_fix_data; 3510 /* Fall through. */ 3511 3512 case BFD_RELOC_SPARC13: 3513 if (! in_signed_range (val, 0x1fff)) 3514 as_bad_where (fixP->fx_file, fixP->fx_line, 3515 _("relocation overflow")); 3516 insn |= val & 0x1fff; 3517 break; 3518 3519 case BFD_RELOC_SPARC_WDISP22: 3520 val = (val >> 2) + 1; 3521 /* Fall through. */ 3522 case BFD_RELOC_SPARC_BASE22: 3523 insn |= val & 0x3fffff; 3524 break; 3525 3526 case BFD_RELOC_SPARC_H34: 3527 if (!fixP->fx_addsy) 3528 { 3529 bfd_vma tval = val; 3530 tval >>= 12; 3531 insn |= tval & 0x3fffff; 3532 } 3533 break; 3534 3535 case BFD_RELOC_SPARC_H44: 3536 if (!fixP->fx_addsy) 3537 { 3538 bfd_vma tval = val; 3539 tval >>= 22; 3540 insn |= tval & 0x3fffff; 3541 } 3542 break; 3543 3544 case BFD_RELOC_SPARC_M44: 3545 if (!fixP->fx_addsy) 3546 insn |= (val >> 12) & 0x3ff; 3547 break; 3548 3549 case BFD_RELOC_SPARC_L44: 3550 if (!fixP->fx_addsy) 3551 insn |= val & 0xfff; 3552 break; 3553 3554 case BFD_RELOC_SPARC_HIX22: 3555 if (!fixP->fx_addsy) 3556 { 3557 val ^= ~(offsetT) 0; 3558 insn |= (val >> 10) & 0x3fffff; 3559 } 3560 break; 3561 3562 case BFD_RELOC_SPARC_LOX10: 3563 if (!fixP->fx_addsy) 3564 insn |= 0x1c00 | (val & 0x3ff); 3565 break; 3566 3567 case BFD_RELOC_NONE: 3568 default: 3569 as_bad_where (fixP->fx_file, fixP->fx_line, 3570 _("bad or unhandled relocation type: 0x%02x"), 3571 fixP->fx_r_type); 3572 break; 3573 } 3574 3575 if (INSN_BIG_ENDIAN) 3576 bfd_putb32 (insn, (unsigned char *) buf); 3577 else 3578 bfd_putl32 (insn, (unsigned char *) buf); 3579 } 3580 3581 /* Are we finished with this relocation now? */ 3582 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) 3583 fixP->fx_done = 1; 3584 } 3585 3586 /* Translate internal representation of relocation info to BFD target 3587 format. */ 3588 3589 arelent ** 3590 tc_gen_reloc (asection *section, fixS *fixp) 3591 { 3592 static arelent *relocs[3]; 3593 arelent *reloc; 3594 bfd_reloc_code_real_type code; 3595 3596 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent)); 3597 relocs[1] = NULL; 3598 3599 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 3600 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 3601 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 3602 3603 switch (fixp->fx_r_type) 3604 { 3605 case BFD_RELOC_16: 3606 case BFD_RELOC_32: 3607 case BFD_RELOC_HI22: 3608 case BFD_RELOC_LO10: 3609 case BFD_RELOC_32_PCREL_S2: 3610 case BFD_RELOC_SPARC13: 3611 case BFD_RELOC_SPARC22: 3612 case BFD_RELOC_SPARC_PC22: 3613 case BFD_RELOC_SPARC_PC10: 3614 case BFD_RELOC_SPARC_BASE13: 3615 case BFD_RELOC_SPARC_WDISP10: 3616 case BFD_RELOC_SPARC_WDISP16: 3617 case BFD_RELOC_SPARC_WDISP19: 3618 case BFD_RELOC_SPARC_WDISP22: 3619 case BFD_RELOC_64: 3620 case BFD_RELOC_SPARC_5: 3621 case BFD_RELOC_SPARC_6: 3622 case BFD_RELOC_SPARC_7: 3623 case BFD_RELOC_SPARC_10: 3624 case BFD_RELOC_SPARC_11: 3625 case BFD_RELOC_SPARC_HH22: 3626 case BFD_RELOC_SPARC_HM10: 3627 case BFD_RELOC_SPARC_LM22: 3628 case BFD_RELOC_SPARC_PC_HH22: 3629 case BFD_RELOC_SPARC_PC_HM10: 3630 case BFD_RELOC_SPARC_PC_LM22: 3631 case BFD_RELOC_SPARC_H34: 3632 case BFD_RELOC_SPARC_H44: 3633 case BFD_RELOC_SPARC_M44: 3634 case BFD_RELOC_SPARC_L44: 3635 case BFD_RELOC_SPARC_HIX22: 3636 case BFD_RELOC_SPARC_LOX10: 3637 case BFD_RELOC_SPARC_REV32: 3638 case BFD_RELOC_SPARC_OLO10: 3639 case BFD_RELOC_SPARC_UA16: 3640 case BFD_RELOC_SPARC_UA32: 3641 case BFD_RELOC_SPARC_UA64: 3642 case BFD_RELOC_8_PCREL: 3643 case BFD_RELOC_16_PCREL: 3644 case BFD_RELOC_32_PCREL: 3645 case BFD_RELOC_64_PCREL: 3646 case BFD_RELOC_SPARC_PLT32: 3647 case BFD_RELOC_SPARC_PLT64: 3648 case BFD_RELOC_VTABLE_ENTRY: 3649 case BFD_RELOC_VTABLE_INHERIT: 3650 case BFD_RELOC_SPARC_TLS_GD_HI22: 3651 case BFD_RELOC_SPARC_TLS_GD_LO10: 3652 case BFD_RELOC_SPARC_TLS_GD_ADD: 3653 case BFD_RELOC_SPARC_TLS_GD_CALL: 3654 case BFD_RELOC_SPARC_TLS_LDM_HI22: 3655 case BFD_RELOC_SPARC_TLS_LDM_LO10: 3656 case BFD_RELOC_SPARC_TLS_LDM_ADD: 3657 case BFD_RELOC_SPARC_TLS_LDM_CALL: 3658 case BFD_RELOC_SPARC_TLS_LDO_HIX22: 3659 case BFD_RELOC_SPARC_TLS_LDO_LOX10: 3660 case BFD_RELOC_SPARC_TLS_LDO_ADD: 3661 case BFD_RELOC_SPARC_TLS_IE_HI22: 3662 case BFD_RELOC_SPARC_TLS_IE_LO10: 3663 case BFD_RELOC_SPARC_TLS_IE_LD: 3664 case BFD_RELOC_SPARC_TLS_IE_LDX: 3665 case BFD_RELOC_SPARC_TLS_IE_ADD: 3666 case BFD_RELOC_SPARC_TLS_LE_HIX22: 3667 case BFD_RELOC_SPARC_TLS_LE_LOX10: 3668 case BFD_RELOC_SPARC_TLS_DTPOFF32: 3669 case BFD_RELOC_SPARC_TLS_DTPOFF64: 3670 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22: 3671 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10: 3672 case BFD_RELOC_SPARC_GOTDATA_OP: 3673 code = fixp->fx_r_type; 3674 break; 3675 default: 3676 abort (); 3677 return NULL; 3678 } 3679 3680 #if defined (OBJ_ELF) || defined (OBJ_AOUT) 3681 /* If we are generating PIC code, we need to generate a different 3682 set of relocs. */ 3683 3684 #ifdef OBJ_ELF 3685 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_" 3686 #else 3687 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_" 3688 #endif 3689 #ifdef TE_VXWORKS 3690 #define GOTT_BASE "__GOTT_BASE__" 3691 #define GOTT_INDEX "__GOTT_INDEX__" 3692 #endif 3693 3694 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */ 3695 3696 if (sparc_pic_code) 3697 { 3698 switch (code) 3699 { 3700 case BFD_RELOC_32_PCREL_S2: 3701 if (generic_force_reloc (fixp)) 3702 code = BFD_RELOC_SPARC_WPLT30; 3703 break; 3704 case BFD_RELOC_HI22: 3705 code = BFD_RELOC_SPARC_GOT22; 3706 if (fixp->fx_addsy != NULL) 3707 { 3708 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) 3709 code = BFD_RELOC_SPARC_PC22; 3710 #ifdef TE_VXWORKS 3711 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 3712 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) 3713 code = BFD_RELOC_HI22; /* Unchanged. */ 3714 #endif 3715 } 3716 break; 3717 case BFD_RELOC_LO10: 3718 code = BFD_RELOC_SPARC_GOT10; 3719 if (fixp->fx_addsy != NULL) 3720 { 3721 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) 3722 code = BFD_RELOC_SPARC_PC10; 3723 #ifdef TE_VXWORKS 3724 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 3725 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) 3726 code = BFD_RELOC_LO10; /* Unchanged. */ 3727 #endif 3728 } 3729 break; 3730 case BFD_RELOC_SPARC13: 3731 code = BFD_RELOC_SPARC_GOT13; 3732 break; 3733 default: 3734 break; 3735 } 3736 } 3737 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */ 3738 3739 /* Nothing is aligned in DWARF debugging sections. */ 3740 if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING) 3741 switch (code) 3742 { 3743 case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break; 3744 case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break; 3745 case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break; 3746 default: break; 3747 } 3748 3749 if (code == BFD_RELOC_SPARC_OLO10) 3750 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10); 3751 else 3752 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 3753 if (reloc->howto == 0) 3754 { 3755 as_bad_where (fixp->fx_file, fixp->fx_line, 3756 _("internal error: can't export reloc type %d (`%s')"), 3757 fixp->fx_r_type, bfd_get_reloc_code_name (code)); 3758 xfree (reloc); 3759 relocs[0] = NULL; 3760 return relocs; 3761 } 3762 3763 /* @@ Why fx_addnumber sometimes and fx_offset other times? */ 3764 #ifdef OBJ_AOUT 3765 3766 if (reloc->howto->pc_relative == 0 3767 || code == BFD_RELOC_SPARC_PC10 3768 || code == BFD_RELOC_SPARC_PC22) 3769 reloc->addend = fixp->fx_addnumber; 3770 else if (sparc_pic_code 3771 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2 3772 && fixp->fx_addsy != NULL 3773 && (S_IS_EXTERNAL (fixp->fx_addsy) 3774 || S_IS_WEAK (fixp->fx_addsy)) 3775 && S_IS_DEFINED (fixp->fx_addsy) 3776 && ! S_IS_COMMON (fixp->fx_addsy)) 3777 reloc->addend = fixp->fx_addnumber; 3778 else 3779 reloc->addend = fixp->fx_offset - reloc->address; 3780 3781 #else /* elf or coff */ 3782 3783 if (code != BFD_RELOC_32_PCREL_S2 3784 && code != BFD_RELOC_SPARC_WDISP22 3785 && code != BFD_RELOC_SPARC_WDISP16 3786 && code != BFD_RELOC_SPARC_WDISP19 3787 && code != BFD_RELOC_SPARC_WDISP10 3788 && code != BFD_RELOC_SPARC_WPLT30 3789 && code != BFD_RELOC_SPARC_TLS_GD_CALL 3790 && code != BFD_RELOC_SPARC_TLS_LDM_CALL) 3791 reloc->addend = fixp->fx_addnumber; 3792 else if (symbol_section_p (fixp->fx_addsy)) 3793 reloc->addend = (section->vma 3794 + fixp->fx_addnumber 3795 + md_pcrel_from (fixp)); 3796 else 3797 reloc->addend = fixp->fx_offset; 3798 #endif 3799 3800 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13 3801 on the same location. */ 3802 if (code == BFD_RELOC_SPARC_OLO10) 3803 { 3804 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent)); 3805 relocs[2] = NULL; 3806 3807 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 3808 *reloc->sym_ptr_ptr 3809 = symbol_get_bfdsym (section_symbol (absolute_section)); 3810 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 3811 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13); 3812 reloc->addend = fixp->tc_fix_data; 3813 } 3814 3815 return relocs; 3816 } 3817 3818 /* We have no need to default values of symbols. */ 3820 3821 symbolS * 3822 md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 3823 { 3824 return 0; 3825 } 3826 3827 /* Round up a section size to the appropriate boundary. */ 3828 3829 valueT 3830 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) 3831 { 3832 #ifndef OBJ_ELF 3833 /* This is not right for ELF; a.out wants it, and COFF will force 3834 the alignment anyways. */ 3835 valueT align = ((valueT) 1 3836 << (valueT) bfd_get_section_alignment (stdoutput, segment)); 3837 valueT newsize; 3838 3839 /* Turn alignment value into a mask. */ 3840 align--; 3841 newsize = (size + align) & ~align; 3842 return newsize; 3843 #else 3844 return size; 3845 #endif 3846 } 3847 3848 /* Exactly what point is a PC-relative offset relative TO? 3849 On the sparc, they're relative to the address of the offset, plus 3850 its size. This gets us to the following instruction. 3851 (??? Is this right? FIXME-SOON) */ 3852 long 3853 md_pcrel_from (fixS *fixP) 3854 { 3855 long ret; 3856 3857 ret = fixP->fx_where + fixP->fx_frag->fr_address; 3858 if (! sparc_pic_code 3859 || fixP->fx_addsy == NULL 3860 || symbol_section_p (fixP->fx_addsy)) 3861 ret += fixP->fx_size; 3862 return ret; 3863 } 3864 3865 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power 3867 of two. */ 3868 3869 static int 3870 mylog2 (int value) 3871 { 3872 int shift; 3873 3874 if (value <= 0) 3875 return -1; 3876 3877 for (shift = 0; (value & 1) == 0; value >>= 1) 3878 ++shift; 3879 3880 return (value == 1) ? shift : -1; 3881 } 3882 3883 /* Sort of like s_lcomm. */ 3884 3885 #ifndef OBJ_ELF 3886 static int max_alignment = 15; 3887 #endif 3888 3889 static void 3890 s_reserve (int ignore ATTRIBUTE_UNUSED) 3891 { 3892 char *name; 3893 char *p; 3894 char c; 3895 int align; 3896 int size; 3897 int temp; 3898 symbolS *symbolP; 3899 3900 name = input_line_pointer; 3901 c = get_symbol_end (); 3902 p = input_line_pointer; 3903 *p = c; 3904 SKIP_WHITESPACE (); 3905 3906 if (*input_line_pointer != ',') 3907 { 3908 as_bad (_("Expected comma after name")); 3909 ignore_rest_of_line (); 3910 return; 3911 } 3912 3913 ++input_line_pointer; 3914 3915 if ((size = get_absolute_expression ()) < 0) 3916 { 3917 as_bad (_("BSS length (%d.) <0! Ignored."), size); 3918 ignore_rest_of_line (); 3919 return; 3920 } /* Bad length. */ 3921 3922 *p = 0; 3923 symbolP = symbol_find_or_make (name); 3924 *p = c; 3925 3926 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0 3927 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0) 3928 { 3929 as_bad (_("bad .reserve segment -- expected BSS segment")); 3930 return; 3931 } 3932 3933 if (input_line_pointer[2] == '.') 3934 input_line_pointer += 7; 3935 else 3936 input_line_pointer += 6; 3937 SKIP_WHITESPACE (); 3938 3939 if (*input_line_pointer == ',') 3940 { 3941 ++input_line_pointer; 3942 3943 SKIP_WHITESPACE (); 3944 if (*input_line_pointer == '\n') 3945 { 3946 as_bad (_("missing alignment")); 3947 ignore_rest_of_line (); 3948 return; 3949 } 3950 3951 align = (int) get_absolute_expression (); 3952 3953 #ifndef OBJ_ELF 3954 if (align > max_alignment) 3955 { 3956 align = max_alignment; 3957 as_warn (_("alignment too large; assuming %d"), align); 3958 } 3959 #endif 3960 3961 if (align < 0) 3962 { 3963 as_bad (_("negative alignment")); 3964 ignore_rest_of_line (); 3965 return; 3966 } 3967 3968 if (align != 0) 3969 { 3970 temp = mylog2 (align); 3971 if (temp < 0) 3972 { 3973 as_bad (_("alignment not a power of 2")); 3974 ignore_rest_of_line (); 3975 return; 3976 } 3977 3978 align = temp; 3979 } 3980 3981 record_alignment (bss_section, align); 3982 } 3983 else 3984 align = 0; 3985 3986 if (!S_IS_DEFINED (symbolP) 3987 #ifdef OBJ_AOUT 3988 && S_GET_OTHER (symbolP) == 0 3989 && S_GET_DESC (symbolP) == 0 3990 #endif 3991 ) 3992 { 3993 if (! need_pass_2) 3994 { 3995 char *pfrag; 3996 segT current_seg = now_seg; 3997 subsegT current_subseg = now_subseg; 3998 3999 /* Switch to bss. */ 4000 subseg_set (bss_section, 1); 4001 4002 if (align) 4003 /* Do alignment. */ 4004 frag_align (align, 0, 0); 4005 4006 /* Detach from old frag. */ 4007 if (S_GET_SEGMENT (symbolP) == bss_section) 4008 symbol_get_frag (symbolP)->fr_symbol = NULL; 4009 4010 symbol_set_frag (symbolP, frag_now); 4011 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, 4012 (offsetT) size, (char *) 0); 4013 *pfrag = 0; 4014 4015 S_SET_SEGMENT (symbolP, bss_section); 4016 4017 subseg_set (current_seg, current_subseg); 4018 4019 #ifdef OBJ_ELF 4020 S_SET_SIZE (symbolP, size); 4021 #endif 4022 } 4023 } 4024 else 4025 { 4026 as_warn (_("Ignoring attempt to re-define symbol %s"), 4027 S_GET_NAME (symbolP)); 4028 } 4029 4030 demand_empty_rest_of_line (); 4031 } 4032 4033 static void 4034 s_common (int ignore ATTRIBUTE_UNUSED) 4035 { 4036 char *name; 4037 char c; 4038 char *p; 4039 offsetT temp, size; 4040 symbolS *symbolP; 4041 4042 name = input_line_pointer; 4043 c = get_symbol_end (); 4044 /* Just after name is now '\0'. */ 4045 p = input_line_pointer; 4046 *p = c; 4047 SKIP_WHITESPACE (); 4048 if (*input_line_pointer != ',') 4049 { 4050 as_bad (_("Expected comma after symbol-name")); 4051 ignore_rest_of_line (); 4052 return; 4053 } 4054 4055 /* Skip ','. */ 4056 input_line_pointer++; 4057 4058 if ((temp = get_absolute_expression ()) < 0) 4059 { 4060 as_bad (_(".COMMon length (%lu) out of range ignored"), 4061 (unsigned long) temp); 4062 ignore_rest_of_line (); 4063 return; 4064 } 4065 size = temp; 4066 *p = 0; 4067 symbolP = symbol_find_or_make (name); 4068 *p = c; 4069 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) 4070 { 4071 as_bad (_("Ignoring attempt to re-define symbol")); 4072 ignore_rest_of_line (); 4073 return; 4074 } 4075 if (S_GET_VALUE (symbolP) != 0) 4076 { 4077 if (S_GET_VALUE (symbolP) != (valueT) size) 4078 { 4079 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."), 4080 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size); 4081 } 4082 } 4083 else 4084 { 4085 #ifndef OBJ_ELF 4086 S_SET_VALUE (symbolP, (valueT) size); 4087 S_SET_EXTERNAL (symbolP); 4088 #endif 4089 } 4090 know (symbol_get_frag (symbolP) == &zero_address_frag); 4091 if (*input_line_pointer != ',') 4092 { 4093 as_bad (_("Expected comma after common length")); 4094 ignore_rest_of_line (); 4095 return; 4096 } 4097 input_line_pointer++; 4098 SKIP_WHITESPACE (); 4099 if (*input_line_pointer != '"') 4100 { 4101 temp = get_absolute_expression (); 4102 4103 #ifndef OBJ_ELF 4104 if (temp > max_alignment) 4105 { 4106 temp = max_alignment; 4107 as_warn (_("alignment too large; assuming %ld"), (long) temp); 4108 } 4109 #endif 4110 4111 if (temp < 0) 4112 { 4113 as_bad (_("negative alignment")); 4114 ignore_rest_of_line (); 4115 return; 4116 } 4117 4118 #ifdef OBJ_ELF 4119 if (symbol_get_obj (symbolP)->local) 4120 { 4121 segT old_sec; 4122 int old_subsec; 4123 int align; 4124 4125 old_sec = now_seg; 4126 old_subsec = now_subseg; 4127 4128 if (temp == 0) 4129 align = 0; 4130 else 4131 align = mylog2 (temp); 4132 4133 if (align < 0) 4134 { 4135 as_bad (_("alignment not a power of 2")); 4136 ignore_rest_of_line (); 4137 return; 4138 } 4139 4140 record_alignment (bss_section, align); 4141 subseg_set (bss_section, 0); 4142 if (align) 4143 frag_align (align, 0, 0); 4144 if (S_GET_SEGMENT (symbolP) == bss_section) 4145 symbol_get_frag (symbolP)->fr_symbol = 0; 4146 symbol_set_frag (symbolP, frag_now); 4147 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, 4148 (offsetT) size, (char *) 0); 4149 *p = 0; 4150 S_SET_SEGMENT (symbolP, bss_section); 4151 S_CLEAR_EXTERNAL (symbolP); 4152 S_SET_SIZE (symbolP, size); 4153 subseg_set (old_sec, old_subsec); 4154 } 4155 else 4156 #endif /* OBJ_ELF */ 4157 { 4158 allocate_common: 4159 S_SET_VALUE (symbolP, (valueT) size); 4160 #ifdef OBJ_ELF 4161 S_SET_ALIGN (symbolP, temp); 4162 S_SET_SIZE (symbolP, size); 4163 #endif 4164 S_SET_EXTERNAL (symbolP); 4165 S_SET_SEGMENT (symbolP, bfd_com_section_ptr); 4166 } 4167 } 4168 else 4169 { 4170 input_line_pointer++; 4171 /* @@ Some use the dot, some don't. Can we get some consistency?? */ 4172 if (*input_line_pointer == '.') 4173 input_line_pointer++; 4174 /* @@ Some say data, some say bss. */ 4175 if (strncmp (input_line_pointer, "bss\"", 4) 4176 && strncmp (input_line_pointer, "data\"", 5)) 4177 { 4178 while (*--input_line_pointer != '"') 4179 ; 4180 input_line_pointer--; 4181 goto bad_common_segment; 4182 } 4183 while (*input_line_pointer++ != '"') 4184 ; 4185 goto allocate_common; 4186 } 4187 4188 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; 4189 4190 demand_empty_rest_of_line (); 4191 return; 4192 4193 { 4194 bad_common_segment: 4195 p = input_line_pointer; 4196 while (*p && *p != '\n') 4197 p++; 4198 c = *p; 4199 *p = '\0'; 4200 as_bad (_("bad .common segment %s"), input_line_pointer + 1); 4201 *p = c; 4202 input_line_pointer = p; 4203 ignore_rest_of_line (); 4204 return; 4205 } 4206 } 4207 4208 /* Handle the .empty pseudo-op. This suppresses the warnings about 4209 invalid delay slot usage. */ 4210 4211 static void 4212 s_empty (int ignore ATTRIBUTE_UNUSED) 4213 { 4214 /* The easy way to implement is to just forget about the last 4215 instruction. */ 4216 last_insn = NULL; 4217 } 4218 4219 static void 4220 s_seg (int ignore ATTRIBUTE_UNUSED) 4221 { 4222 4223 if (strncmp (input_line_pointer, "\"text\"", 6) == 0) 4224 { 4225 input_line_pointer += 6; 4226 s_text (0); 4227 return; 4228 } 4229 if (strncmp (input_line_pointer, "\"data\"", 6) == 0) 4230 { 4231 input_line_pointer += 6; 4232 s_data (0); 4233 return; 4234 } 4235 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0) 4236 { 4237 input_line_pointer += 7; 4238 s_data1 (); 4239 return; 4240 } 4241 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0) 4242 { 4243 input_line_pointer += 5; 4244 /* We only support 2 segments -- text and data -- for now, so 4245 things in the "bss segment" will have to go into data for now. 4246 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */ 4247 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */ 4248 return; 4249 } 4250 as_bad (_("Unknown segment type")); 4251 demand_empty_rest_of_line (); 4252 } 4253 4254 static void 4255 s_data1 (void) 4256 { 4257 subseg_set (data_section, 1); 4258 demand_empty_rest_of_line (); 4259 } 4260 4261 static void 4262 s_proc (int ignore ATTRIBUTE_UNUSED) 4263 { 4264 while (!is_end_of_line[(unsigned char) *input_line_pointer]) 4265 { 4266 ++input_line_pointer; 4267 } 4268 ++input_line_pointer; 4269 } 4270 4271 /* This static variable is set by s_uacons to tell sparc_cons_align 4272 that the expression does not need to be aligned. */ 4273 4274 static int sparc_no_align_cons = 0; 4275 4276 /* This static variable is set by sparc_cons to emit requested types 4277 of relocations in cons_fix_new_sparc. */ 4278 4279 static const char *sparc_cons_special_reloc; 4280 4281 /* This handles the unaligned space allocation pseudo-ops, such as 4282 .uaword. .uaword is just like .word, but the value does not need 4283 to be aligned. */ 4284 4285 static void 4286 s_uacons (int bytes) 4287 { 4288 /* Tell sparc_cons_align not to align this value. */ 4289 sparc_no_align_cons = 1; 4290 cons (bytes); 4291 sparc_no_align_cons = 0; 4292 } 4293 4294 /* This handles the native word allocation pseudo-op .nword. 4295 For sparc_arch_size 32 it is equivalent to .word, for 4296 sparc_arch_size 64 it is equivalent to .xword. */ 4297 4298 static void 4299 s_ncons (int bytes ATTRIBUTE_UNUSED) 4300 { 4301 cons (sparc_arch_size == 32 ? 4 : 8); 4302 } 4303 4304 #ifdef OBJ_ELF 4305 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a 4306 global register. 4307 The syntax is: 4308 4309 .register %g[2367],{#scratch|symbolname|#ignore} 4310 */ 4311 4312 static void 4313 s_register (int ignore ATTRIBUTE_UNUSED) 4314 { 4315 char c; 4316 int reg; 4317 int flags; 4318 const char *regname; 4319 4320 if (input_line_pointer[0] != '%' 4321 || input_line_pointer[1] != 'g' 4322 || ((input_line_pointer[2] & ~1) != '2' 4323 && (input_line_pointer[2] & ~1) != '6') 4324 || input_line_pointer[3] != ',') 4325 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); 4326 reg = input_line_pointer[2] - '0'; 4327 input_line_pointer += 4; 4328 4329 if (*input_line_pointer == '#') 4330 { 4331 ++input_line_pointer; 4332 regname = input_line_pointer; 4333 c = get_symbol_end (); 4334 if (strcmp (regname, "scratch") && strcmp (regname, "ignore")) 4335 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); 4336 if (regname[0] == 'i') 4337 regname = NULL; 4338 else 4339 regname = ""; 4340 } 4341 else 4342 { 4343 regname = input_line_pointer; 4344 c = get_symbol_end (); 4345 } 4346 if (sparc_arch_size == 64) 4347 { 4348 if (globals[reg]) 4349 { 4350 if ((regname && globals[reg] != (symbolS *) 1 4351 && strcmp (S_GET_NAME (globals[reg]), regname)) 4352 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1))) 4353 as_bad (_("redefinition of global register")); 4354 } 4355 else 4356 { 4357 if (regname == NULL) 4358 globals[reg] = (symbolS *) 1; 4359 else 4360 { 4361 if (*regname) 4362 { 4363 if (symbol_find (regname)) 4364 as_bad (_("Register symbol %s already defined."), 4365 regname); 4366 } 4367 globals[reg] = symbol_make (regname); 4368 flags = symbol_get_bfdsym (globals[reg])->flags; 4369 if (! *regname) 4370 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK); 4371 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK))) 4372 flags |= BSF_GLOBAL; 4373 symbol_get_bfdsym (globals[reg])->flags = flags; 4374 S_SET_VALUE (globals[reg], (valueT) reg); 4375 S_SET_ALIGN (globals[reg], reg); 4376 S_SET_SIZE (globals[reg], 0); 4377 /* Although we actually want undefined_section here, 4378 we have to use absolute_section, because otherwise 4379 generic as code will make it a COM section. 4380 We fix this up in sparc_adjust_symtab. */ 4381 S_SET_SEGMENT (globals[reg], absolute_section); 4382 S_SET_OTHER (globals[reg], 0); 4383 elf_symbol (symbol_get_bfdsym (globals[reg])) 4384 ->internal_elf_sym.st_info = 4385 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER); 4386 elf_symbol (symbol_get_bfdsym (globals[reg])) 4387 ->internal_elf_sym.st_shndx = SHN_UNDEF; 4388 } 4389 } 4390 } 4391 4392 *input_line_pointer = c; 4393 4394 demand_empty_rest_of_line (); 4395 } 4396 4397 /* Adjust the symbol table. We set undefined sections for STT_REGISTER 4398 symbols which need it. */ 4399 4400 void 4401 sparc_adjust_symtab (void) 4402 { 4403 symbolS *sym; 4404 4405 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) 4406 { 4407 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) 4408 ->internal_elf_sym.st_info) != STT_REGISTER) 4409 continue; 4410 4411 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) 4412 ->internal_elf_sym.st_shndx != SHN_UNDEF)) 4413 continue; 4414 4415 S_SET_SEGMENT (sym, undefined_section); 4416 } 4417 } 4418 #endif 4419 4420 /* If the --enforce-aligned-data option is used, we require .word, 4421 et. al., to be aligned correctly. We do it by setting up an 4422 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that 4423 no unexpected alignment was introduced. 4424 4425 The SunOS and Solaris native assemblers enforce aligned data by 4426 default. We don't want to do that, because gcc can deliberately 4427 generate misaligned data if the packed attribute is used. Instead, 4428 we permit misaligned data by default, and permit the user to set an 4429 option to check for it. */ 4430 4431 void 4432 sparc_cons_align (int nbytes) 4433 { 4434 int nalign; 4435 4436 /* Only do this if we are enforcing aligned data. */ 4437 if (! enforce_aligned_data) 4438 return; 4439 4440 /* Don't align if this is an unaligned pseudo-op. */ 4441 if (sparc_no_align_cons) 4442 return; 4443 4444 nalign = mylog2 (nbytes); 4445 if (nalign == 0) 4446 return; 4447 4448 gas_assert (nalign > 0); 4449 4450 if (now_seg == absolute_section) 4451 { 4452 if ((abs_section_offset & ((1 << nalign) - 1)) != 0) 4453 as_bad (_("misaligned data")); 4454 return; 4455 } 4456 4457 frag_var (rs_align_test, 1, 1, (relax_substateT) 0, 4458 (symbolS *) NULL, (offsetT) nalign, (char *) NULL); 4459 4460 record_alignment (now_seg, nalign); 4461 } 4462 4463 /* This is called from HANDLE_ALIGN in tc-sparc.h. */ 4464 4465 void 4466 sparc_handle_align (fragS *fragp) 4467 { 4468 int count, fix; 4469 char *p; 4470 4471 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; 4472 4473 switch (fragp->fr_type) 4474 { 4475 case rs_align_test: 4476 if (count != 0) 4477 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data")); 4478 break; 4479 4480 case rs_align_code: 4481 p = fragp->fr_literal + fragp->fr_fix; 4482 fix = 0; 4483 4484 if (count & 3) 4485 { 4486 fix = count & 3; 4487 memset (p, 0, fix); 4488 p += fix; 4489 count -= fix; 4490 } 4491 4492 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8) 4493 { 4494 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */ 4495 if (INSN_BIG_ENDIAN) 4496 number_to_chars_bigendian (p, wval, 4); 4497 else 4498 number_to_chars_littleendian (p, wval, 4); 4499 p += 4; 4500 count -= 4; 4501 fix += 4; 4502 } 4503 4504 if (INSN_BIG_ENDIAN) 4505 number_to_chars_bigendian (p, 0x01000000, 4); 4506 else 4507 number_to_chars_littleendian (p, 0x01000000, 4); 4508 4509 fragp->fr_fix += fix; 4510 fragp->fr_var = 4; 4511 break; 4512 4513 default: 4514 break; 4515 } 4516 } 4517 4518 #ifdef OBJ_ELF 4519 /* Some special processing for a Sparc ELF file. */ 4520 4521 void 4522 sparc_elf_final_processing (void) 4523 { 4524 /* Set the Sparc ELF flag bits. FIXME: There should probably be some 4525 sort of BFD interface for this. */ 4526 if (sparc_arch_size == 64) 4527 { 4528 switch (sparc_memory_model) 4529 { 4530 case MM_RMO: 4531 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO; 4532 break; 4533 case MM_PSO: 4534 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO; 4535 break; 4536 default: 4537 break; 4538 } 4539 } 4540 else if (current_architecture >= SPARC_OPCODE_ARCH_V9) 4541 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS; 4542 if (current_architecture == SPARC_OPCODE_ARCH_V9A) 4543 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1; 4544 else if (current_architecture == SPARC_OPCODE_ARCH_V9B) 4545 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3; 4546 } 4547 4548 void 4549 sparc_cons (expressionS *exp, int size) 4550 { 4551 char *save; 4552 4553 SKIP_WHITESPACE (); 4554 sparc_cons_special_reloc = NULL; 4555 save = input_line_pointer; 4556 if (input_line_pointer[0] == '%' 4557 && input_line_pointer[1] == 'r' 4558 && input_line_pointer[2] == '_') 4559 { 4560 if (strncmp (input_line_pointer + 3, "disp", 4) == 0) 4561 { 4562 input_line_pointer += 7; 4563 sparc_cons_special_reloc = "disp"; 4564 } 4565 else if (strncmp (input_line_pointer + 3, "plt", 3) == 0) 4566 { 4567 if (size != 4 && size != 8) 4568 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size); 4569 else 4570 { 4571 input_line_pointer += 6; 4572 sparc_cons_special_reloc = "plt"; 4573 } 4574 } 4575 else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0) 4576 { 4577 if (size != 4 && size != 8) 4578 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size); 4579 else 4580 { 4581 input_line_pointer += 13; 4582 sparc_cons_special_reloc = "tls_dtpoff"; 4583 } 4584 } 4585 if (sparc_cons_special_reloc) 4586 { 4587 int bad = 0; 4588 4589 switch (size) 4590 { 4591 case 1: 4592 if (*input_line_pointer != '8') 4593 bad = 1; 4594 input_line_pointer--; 4595 break; 4596 case 2: 4597 if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6') 4598 bad = 1; 4599 break; 4600 case 4: 4601 if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2') 4602 bad = 1; 4603 break; 4604 case 8: 4605 if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4') 4606 bad = 1; 4607 break; 4608 default: 4609 bad = 1; 4610 break; 4611 } 4612 4613 if (bad) 4614 { 4615 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"), 4616 sparc_cons_special_reloc, size * 8, size); 4617 } 4618 else 4619 { 4620 input_line_pointer += 2; 4621 if (*input_line_pointer != '(') 4622 { 4623 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), 4624 sparc_cons_special_reloc, size * 8); 4625 bad = 1; 4626 } 4627 } 4628 4629 if (bad) 4630 { 4631 input_line_pointer = save; 4632 sparc_cons_special_reloc = NULL; 4633 } 4634 else 4635 { 4636 int c; 4637 char *end = ++input_line_pointer; 4638 int npar = 0; 4639 4640 while (! is_end_of_line[(c = *end)]) 4641 { 4642 if (c == '(') 4643 npar++; 4644 else if (c == ')') 4645 { 4646 if (!npar) 4647 break; 4648 npar--; 4649 } 4650 end++; 4651 } 4652 4653 if (c != ')') 4654 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), 4655 sparc_cons_special_reloc, size * 8); 4656 else 4657 { 4658 *end = '\0'; 4659 expression (exp); 4660 *end = c; 4661 if (input_line_pointer != end) 4662 { 4663 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), 4664 sparc_cons_special_reloc, size * 8); 4665 } 4666 else 4667 { 4668 input_line_pointer++; 4669 SKIP_WHITESPACE (); 4670 c = *input_line_pointer; 4671 if (! is_end_of_line[c] && c != ',') 4672 as_bad (_("Illegal operands: garbage after %%r_%s%d()"), 4673 sparc_cons_special_reloc, size * 8); 4674 } 4675 } 4676 } 4677 } 4678 } 4679 if (sparc_cons_special_reloc == NULL) 4680 expression (exp); 4681 } 4682 4683 #endif 4684 4685 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a 4686 reloc for a cons. We could use the definition there, except that 4687 we want to handle little endian relocs specially. */ 4688 4689 void 4690 cons_fix_new_sparc (fragS *frag, 4691 int where, 4692 unsigned int nbytes, 4693 expressionS *exp) 4694 { 4695 bfd_reloc_code_real_type r; 4696 4697 r = (nbytes == 1 ? BFD_RELOC_8 : 4698 (nbytes == 2 ? BFD_RELOC_16 : 4699 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); 4700 4701 if (target_little_endian_data 4702 && nbytes == 4 4703 && now_seg->flags & SEC_ALLOC) 4704 r = BFD_RELOC_SPARC_REV32; 4705 4706 if (sparc_cons_special_reloc) 4707 { 4708 if (*sparc_cons_special_reloc == 'd') 4709 switch (nbytes) 4710 { 4711 case 1: r = BFD_RELOC_8_PCREL; break; 4712 case 2: r = BFD_RELOC_16_PCREL; break; 4713 case 4: r = BFD_RELOC_32_PCREL; break; 4714 case 8: r = BFD_RELOC_64_PCREL; break; 4715 default: abort (); 4716 } 4717 else if (*sparc_cons_special_reloc == 'p') 4718 switch (nbytes) 4719 { 4720 case 4: r = BFD_RELOC_SPARC_PLT32; break; 4721 case 8: r = BFD_RELOC_SPARC_PLT64; break; 4722 } 4723 else 4724 switch (nbytes) 4725 { 4726 case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break; 4727 case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break; 4728 } 4729 } 4730 else if (sparc_no_align_cons) 4731 { 4732 switch (nbytes) 4733 { 4734 case 2: r = BFD_RELOC_SPARC_UA16; break; 4735 case 4: r = BFD_RELOC_SPARC_UA32; break; 4736 case 8: r = BFD_RELOC_SPARC_UA64; break; 4737 default: abort (); 4738 } 4739 } 4740 4741 fix_new_exp (frag, where, (int) nbytes, exp, 0, r); 4742 sparc_cons_special_reloc = NULL; 4743 } 4744 4745 void 4746 sparc_cfi_frame_initial_instructions (void) 4747 { 4748 cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0); 4749 } 4750 4751 int 4752 sparc_regname_to_dw2regnum (char *regname) 4753 { 4754 char *p, *q; 4755 4756 if (!regname[0]) 4757 return -1; 4758 4759 q = "goli"; 4760 p = strchr (q, regname[0]); 4761 if (p) 4762 { 4763 if (regname[1] < '0' || regname[1] > '8' || regname[2]) 4764 return -1; 4765 return (p - q) * 8 + regname[1] - '0'; 4766 } 4767 if (regname[0] == 's' && regname[1] == 'p' && !regname[2]) 4768 return 14; 4769 if (regname[0] == 'f' && regname[1] == 'p' && !regname[2]) 4770 return 30; 4771 if (regname[0] == 'f' || regname[0] == 'r') 4772 { 4773 unsigned int regnum; 4774 4775 regnum = strtoul (regname + 1, &q, 10); 4776 if (p == q || *q) 4777 return -1; 4778 if (regnum >= ((regname[0] == 'f' 4779 && SPARC_OPCODE_ARCH_V9_P (max_architecture)) 4780 ? 64 : 32)) 4781 return -1; 4782 if (regname[0] == 'f') 4783 { 4784 regnum += 32; 4785 if (regnum >= 64 && (regnum & 1)) 4786 return -1; 4787 } 4788 return regnum; 4789 } 4790 return -1; 4791 } 4792 4793 void 4794 sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes) 4795 { 4796 sparc_cons_special_reloc = "disp"; 4797 sparc_no_align_cons = 1; 4798 emit_expr (exp, nbytes); 4799 sparc_no_align_cons = 0; 4800 sparc_cons_special_reloc = NULL; 4801 } 4802
Indexes created Sun Mar 01 05:31:48 UTC 2026