tc-v850.c revision 1.1.1.10
1 /* tc-v850.c -- Assembler code for the NEC V850 2 Copyright (C) 1996-2026 Free Software Foundation, Inc. 3 4 This file is part of GAS, the GNU Assembler. 5 6 GAS is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GAS is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GAS; see the file COPYING. If not, write to 18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, 19 Boston, MA 02110-1301, USA. */ 20 21 #include "as.h" 22 #include "safe-ctype.h" 23 #include "subsegs.h" 24 #include "opcode/v850.h" 25 #include "dwarf2dbg.h" 26 27 /* Sign-extend a 16-bit number. */ 28 #define SEXT16(x) ((((x) & 0xffff) ^ (~0x7fff)) + 0x8000) 29 30 /* Set to TRUE if we want to be pedantic about signed overflows. */ 31 static bool warn_signed_overflows = false; 32 static bool warn_unsigned_overflows = false; 33 34 /* Non-zero if floating point insns are not being used. */ 35 static signed int soft_float = -1; 36 37 /* Indicates the target BFD machine number. */ 38 static int machine = -1; 39 40 41 /* Indicates the target BFD architecture. */ 42 enum bfd_architecture v850_target_arch = bfd_arch_v850_rh850; 43 const char * v850_target_format = "elf32-v850-rh850"; 44 static flagword v850_e_flags = 0; 45 46 /* Indicates the target processor(s) for the assemble. */ 47 static int processor_mask = 0; 48 49 /* Structure to hold information about predefined registers. */ 51 struct reg_name 52 { 53 const char *name; 54 int value; 55 unsigned int processors; 56 }; 57 58 /* Generic assembler global variables which must be defined by all 59 targets. */ 60 61 /* Characters which always start a comment. */ 62 const char comment_chars[] = "#"; 63 64 /* Characters which start a comment at the beginning of a line. */ 65 const char line_comment_chars[] = ";#"; 66 67 /* Characters which may be used to separate multiple commands on a 68 single line. */ 69 const char line_separator_chars[] = ";"; 70 71 /* Characters which are used to indicate an exponent in a floating 72 point number. */ 73 const char EXP_CHARS[] = "eE"; 74 75 /* Characters which mean that a number is a floating point constant, 76 as in 0d1.0. */ 77 const char FLT_CHARS[] = "dD"; 78 79 const relax_typeS md_relax_table[] = 81 { 82 /* Conditional branches.(V850/V850E, max 22bit) */ 83 #define SUBYPTE_COND_9_22 0 84 {0xfe, -0x100, 2, SUBYPTE_COND_9_22 + 1}, 85 {0x1ffffe + 2, -0x200000 + 2, 6, 0}, 86 /* Conditional branches.(V850/V850E, max 22bit) */ 87 #define SUBYPTE_SA_9_22 2 88 {0xfe, -0x100, 2, SUBYPTE_SA_9_22 + 1}, 89 {0x1ffffe + 4, -0x200000 + 4, 8, 0}, 90 /* Unconditional branches.(V850/V850E, max 22bit) */ 91 #define SUBYPTE_UNCOND_9_22 4 92 {0xfe, -0x100, 2, SUBYPTE_UNCOND_9_22 + 1}, 93 {0x1ffffe, -0x200000, 4, 0}, 94 /* Conditional branches.(V850E2, max 32bit) */ 95 #define SUBYPTE_COND_9_22_32 6 96 {0xfe, -0x100, 2, SUBYPTE_COND_9_22_32 + 1}, 97 {0x1fffff + 2, -0x200000 + 2, 6, SUBYPTE_COND_9_22_32 + 2}, 98 {0x7ffffffe, -0x80000000, 8, 0}, 99 /* Conditional branches.(V850E2, max 32bit) */ 100 #define SUBYPTE_SA_9_22_32 9 101 {0xfe, -0x100, 2, SUBYPTE_SA_9_22_32 + 1}, 102 {0x1ffffe + 4, -0x200000 + 4, 8, SUBYPTE_SA_9_22_32 + 2}, 103 {0x7ffffffe, -0x80000000, 10, 0}, 104 /* Unconditional branches.(V850E2, max 32bit) */ 105 #define SUBYPTE_UNCOND_9_22_32 12 106 {0xfe, -0x100, 2, SUBYPTE_UNCOND_9_22_32 + 1}, 107 {0x1ffffe, -0x200000, 4, SUBYPTE_UNCOND_9_22_32 + 2}, 108 {0x7ffffffe, -0x80000000, 6, 0}, 109 /* Conditional branches.(V850E2R max 22bit) */ 110 #define SUBYPTE_COND_9_17_22 15 111 {0xfe, -0x100, 2, SUBYPTE_COND_9_17_22 + 1}, 112 {0xfffe, -0x10000, 4, SUBYPTE_COND_9_17_22 + 2}, 113 {0x1ffffe + 2, -0x200000 + 2, 6, 0}, 114 /* Conditional branches.(V850E2R max 22bit) */ 115 #define SUBYPTE_SA_9_17_22 18 116 {0xfe, -0x100, 2, SUBYPTE_SA_9_17_22 + 1}, 117 {0xfffe, -0x10000, 4, SUBYPTE_SA_9_17_22 + 2}, 118 {0x1ffffe + 4, -0x200000 + 4, 8, 0}, 119 /* Conditional branches.(V850E2R max 32bit) */ 120 #define SUBYPTE_COND_9_17_22_32 21 121 {0xfe, -0x100, 2, SUBYPTE_COND_9_17_22_32 + 1}, 122 {0xfffe, -0x10000, 4, SUBYPTE_COND_9_17_22_32 + 2}, 123 {0x1ffffe + 2, -0x200000 + 2, 6, SUBYPTE_COND_9_17_22_32 + 3}, 124 {0x7ffffffe, -0x80000000, 8, 0}, 125 /* Conditional branches.(V850E2R max 32bit) */ 126 #define SUBYPTE_SA_9_17_22_32 25 127 {0xfe, -0x100, 2, SUBYPTE_SA_9_17_22_32 + 1}, 128 {0xfffe, -0x10000, 4, SUBYPTE_SA_9_17_22_32 + 2}, 129 {0x1ffffe + 4, -0x200000 + 4, 8, SUBYPTE_SA_9_17_22_32 + 3}, 130 {0x7ffffffe, -0x80000000, 10, 0}, 131 /* Loop. (V850E2V4_UP, max 22-bit). */ 132 #define SUBYPTE_LOOP_16_22 29 133 {0x0, -0x0fffe, 4, SUBYPTE_LOOP_16_22 + 1}, 134 {0x1ffffe + 2, -0x200000 + 2, 6, 0}, 135 }; 136 137 static int v850_relax = 0; 138 139 /* Default branch disp size 22 or 32. */ 140 static int default_disp_size = 22; 141 142 /* Default no using bcond17. */ 143 static int no_bcond17 = 0; 144 145 /* Default no using ld/st 23bit offset. */ 146 static int no_stld23 = 0; 147 148 /* Fixups. */ 149 #define MAX_INSN_FIXUPS 5 150 151 struct v850_fixup 152 { 153 expressionS exp; 154 int opindex; 155 bfd_reloc_code_real_type reloc; 156 }; 157 158 struct v850_fixup fixups[MAX_INSN_FIXUPS]; 159 static int fc; 160 161 struct v850_seg_entry 162 { 163 segT s; 164 const char *name; 165 flagword flags; 166 }; 167 168 struct v850_seg_entry v850_seg_table[] = 169 { 170 { NULL, ".sdata", 171 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS 172 | SEC_SMALL_DATA }, 173 { NULL, ".tdata", 174 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS }, 175 { NULL, ".zdata", 176 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS }, 177 { NULL, ".sbss", 178 SEC_ALLOC | SEC_SMALL_DATA }, 179 { NULL, ".tbss", 180 SEC_ALLOC }, 181 { NULL, ".zbss", 182 SEC_ALLOC}, 183 { NULL, ".rosdata", 184 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_DATA 185 | SEC_HAS_CONTENTS | SEC_SMALL_DATA }, 186 { NULL, ".rozdata", 187 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_DATA 188 | SEC_HAS_CONTENTS }, 189 { NULL, ".scommon", 190 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS 191 | SEC_SMALL_DATA | SEC_IS_COMMON }, 192 { NULL, ".tcommon", 193 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS 194 | SEC_IS_COMMON }, 195 { NULL, ".zcommon", 196 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS 197 | SEC_IS_COMMON }, 198 { NULL, ".call_table_data", 199 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS }, 200 { NULL, ".call_table_text", 201 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_CODE 202 | SEC_HAS_CONTENTS}, 203 }; 204 205 #define SDATA_SECTION 0 206 #define TDATA_SECTION 1 207 #define ZDATA_SECTION 2 208 #define SBSS_SECTION 3 209 #define TBSS_SECTION 4 210 #define ZBSS_SECTION 5 211 #define ROSDATA_SECTION 6 212 #define ROZDATA_SECTION 7 213 #define SCOMMON_SECTION 8 214 #define TCOMMON_SECTION 9 215 #define ZCOMMON_SECTION 10 216 #define CALL_TABLE_DATA_SECTION 11 217 #define CALL_TABLE_TEXT_SECTION 12 218 219 static void 220 do_v850_seg (int i, subsegT sub) 221 { 222 struct v850_seg_entry *seg = v850_seg_table + i; 223 224 obj_elf_section_change_hook (); 225 226 if (seg->s != NULL) 227 subseg_set (seg->s, sub); 228 else 229 { 230 seg->s = subseg_new (seg->name, sub); 231 bfd_set_section_flags (seg->s, seg->flags); 232 if ((seg->flags & SEC_LOAD) == 0) 233 seg_info (seg->s)->bss = 1; 234 } 235 } 236 237 static void 238 v850_seg (int i) 239 { 240 subsegT sub = get_absolute_expression (); 241 242 do_v850_seg (i, sub); 243 demand_empty_rest_of_line (); 244 } 245 246 static void 247 v850_offset (int ignore ATTRIBUTE_UNUSED) 248 { 249 char *pfrag; 250 int temp = get_absolute_expression (); 251 252 pfrag = frag_var (rs_org, 1, 1, 0, NULL, temp, NULL); 253 *pfrag = 0; 254 255 demand_empty_rest_of_line (); 256 } 257 258 /* Copied from obj_elf_common() in gas/config/obj-elf.c. */ 259 260 static void 261 v850_comm (int area) 262 { 263 char *name; 264 char c; 265 char *p; 266 int temp; 267 unsigned int size; 268 symbolS *symbolP; 269 int have_align; 270 271 c = get_symbol_name (&name); 272 273 /* Just after name is now '\0'. */ 274 p = input_line_pointer; 275 *p = c; 276 277 SKIP_WHITESPACE (); 278 279 if (*input_line_pointer != ',') 280 { 281 as_bad (_("Expected comma after symbol-name")); 282 ignore_rest_of_line (); 283 return; 284 } 285 286 /* Skip ','. */ 287 input_line_pointer++; 288 289 if ((temp = get_absolute_expression ()) < 0) 290 { 291 /* xgettext:c-format */ 292 as_bad (_(".COMMon length (%d.) < 0! Ignored."), temp); 293 ignore_rest_of_line (); 294 return; 295 } 296 297 size = temp; 298 *p = 0; 299 symbolP = symbol_find_or_make (name); 300 *p = c; 301 302 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) 303 { 304 as_bad (_("Ignoring attempt to re-define symbol")); 305 ignore_rest_of_line (); 306 return; 307 } 308 309 if (S_GET_VALUE (symbolP) != 0) 310 { 311 if (S_GET_VALUE (symbolP) != size) 312 /* xgettext:c-format */ 313 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."), 314 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size); 315 } 316 317 know (symbol_get_frag (symbolP) == &zero_address_frag); 318 319 if (*input_line_pointer != ',') 320 have_align = 0; 321 else 322 { 323 have_align = 1; 324 input_line_pointer++; 325 SKIP_WHITESPACE (); 326 } 327 328 if (! have_align || *input_line_pointer != '"') 329 { 330 if (! have_align) 331 temp = 0; 332 else 333 { 334 temp = get_absolute_expression (); 335 336 if (temp < 0) 337 { 338 temp = 0; 339 as_warn (_("Common alignment negative; 0 assumed")); 340 } 341 } 342 343 if (symbol_get_obj (symbolP)->local) 344 { 345 segT old_sec; 346 int old_subsec; 347 char *pfrag; 348 int align; 349 350 old_sec = now_seg; 351 old_subsec = now_subseg; 352 353 switch (area) 354 { 355 case SCOMMON_SECTION: 356 do_v850_seg (SBSS_SECTION, 0); 357 break; 358 359 case ZCOMMON_SECTION: 360 do_v850_seg (ZBSS_SECTION, 0); 361 break; 362 363 case TCOMMON_SECTION: 364 do_v850_seg (TBSS_SECTION, 0); 365 break; 366 } 367 368 if (temp) 369 { 370 /* Convert to a power of 2 alignment. */ 371 for (align = 0; (temp & 1) == 0; temp >>= 1, ++align) 372 ; 373 374 if (temp != 1) 375 { 376 as_bad (_("Common alignment not a power of 2")); 377 ignore_rest_of_line (); 378 return; 379 } 380 } 381 else 382 align = 0; 383 384 record_alignment (now_seg, align); 385 386 if (align) 387 frag_align (align, 0, 0); 388 389 switch (area) 390 { 391 case SCOMMON_SECTION: 392 if (S_GET_SEGMENT (symbolP) == v850_seg_table[SBSS_SECTION].s) 393 symbol_get_frag (symbolP)->fr_symbol = 0; 394 break; 395 396 case ZCOMMON_SECTION: 397 if (S_GET_SEGMENT (symbolP) == v850_seg_table[ZBSS_SECTION].s) 398 symbol_get_frag (symbolP)->fr_symbol = 0; 399 break; 400 401 case TCOMMON_SECTION: 402 if (S_GET_SEGMENT (symbolP) == v850_seg_table[TBSS_SECTION].s) 403 symbol_get_frag (symbolP)->fr_symbol = 0; 404 break; 405 406 default: 407 abort (); 408 } 409 410 symbol_set_frag (symbolP, frag_now); 411 pfrag = frag_var (rs_org, 1, 1, 0, symbolP, size, NULL); 412 *pfrag = 0; 413 S_SET_SIZE (symbolP, size); 414 415 switch (area) 416 { 417 case SCOMMON_SECTION: 418 S_SET_SEGMENT (symbolP, v850_seg_table[SBSS_SECTION].s); 419 break; 420 421 case ZCOMMON_SECTION: 422 S_SET_SEGMENT (symbolP, v850_seg_table[ZBSS_SECTION].s); 423 break; 424 425 case TCOMMON_SECTION: 426 S_SET_SEGMENT (symbolP, v850_seg_table[TBSS_SECTION].s); 427 break; 428 429 default: 430 abort (); 431 } 432 433 S_CLEAR_EXTERNAL (symbolP); 434 obj_elf_section_change_hook (); 435 subseg_set (old_sec, old_subsec); 436 } 437 else 438 { 439 segT old_sec; 440 int old_subsec; 441 442 allocate_common: 443 old_sec = now_seg; 444 old_subsec = now_subseg; 445 446 S_SET_VALUE (symbolP, (valueT) size); 447 S_SET_ALIGN (symbolP, temp); 448 S_SET_EXTERNAL (symbolP); 449 450 switch (area) 451 { 452 case SCOMMON_SECTION: 453 case ZCOMMON_SECTION: 454 case TCOMMON_SECTION: 455 do_v850_seg (area, 0); 456 S_SET_SEGMENT (symbolP, v850_seg_table[area].s); 457 break; 458 459 default: 460 abort (); 461 } 462 463 obj_elf_section_change_hook (); 464 subseg_set (old_sec, old_subsec); 465 } 466 } 467 else 468 { 469 input_line_pointer++; 470 471 /* @@ Some use the dot, some don't. Can we get some consistency?? */ 472 if (*input_line_pointer == '.') 473 input_line_pointer++; 474 475 /* @@ Some say data, some say bss. */ 476 if (!startswith (input_line_pointer, "bss\"") 477 && !startswith (input_line_pointer, "data\"")) 478 { 479 while (*--input_line_pointer != '"') 480 ; 481 input_line_pointer--; 482 goto bad_common_segment; 483 } 484 485 while (*input_line_pointer++ != '"') 486 ; 487 488 goto allocate_common; 489 } 490 491 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; 492 493 demand_empty_rest_of_line (); 494 return; 495 496 { 497 bad_common_segment: 498 p = input_line_pointer; 499 while (*p && *p != '\n') 500 p++; 501 c = *p; 502 *p = '\0'; 503 as_bad (_("bad .common segment %s"), input_line_pointer + 1); 504 *p = c; 505 input_line_pointer = p; 506 ignore_rest_of_line (); 507 return; 508 } 509 } 510 511 static void 512 set_machine (int number) 513 { 514 machine = number; 515 bfd_set_arch_mach (stdoutput, v850_target_arch, machine); 516 517 switch (machine) 518 { 519 case 0: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); break; 520 case bfd_mach_v850: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); break; 521 case bfd_mach_v850e: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); break; 522 case bfd_mach_v850e1: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); break; 523 case bfd_mach_v850e2: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2); break; 524 case bfd_mach_v850e2v3:SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3); break; 525 case bfd_mach_v850e3v5: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5); break; 526 } 527 } 528 529 static void 530 v850_longcode (int type) 531 { 532 expressionS ex; 533 534 if (! v850_relax) 535 { 536 if (type == 1) 537 as_warn (_(".longcall pseudo-op seen when not relaxing")); 538 else 539 as_warn (_(".longjump pseudo-op seen when not relaxing")); 540 } 541 542 expression (&ex); 543 544 if (ex.X_op != O_symbol || ex.X_add_number != 0) 545 { 546 as_bad (_("bad .longcall format")); 547 ignore_rest_of_line (); 548 549 return; 550 } 551 552 if (type == 1) 553 fix_new_exp (frag_now, frag_now_fix (), 4, & ex, 1, 554 BFD_RELOC_V850_LONGCALL); 555 else 556 fix_new_exp (frag_now, frag_now_fix (), 4, & ex, 1, 557 BFD_RELOC_V850_LONGJUMP); 558 559 demand_empty_rest_of_line (); 560 } 561 562 /* The target specific pseudo-ops which we support. */ 563 const pseudo_typeS md_pseudo_table[] = 564 { 565 { "sdata", v850_seg, SDATA_SECTION }, 566 { "tdata", v850_seg, TDATA_SECTION }, 567 { "zdata", v850_seg, ZDATA_SECTION }, 568 { "sbss", v850_seg, SBSS_SECTION }, 569 { "tbss", v850_seg, TBSS_SECTION }, 570 { "zbss", v850_seg, ZBSS_SECTION }, 571 { "rosdata", v850_seg, ROSDATA_SECTION }, 572 { "rozdata", v850_seg, ROZDATA_SECTION }, 573 { "offset", v850_offset, 0 }, 574 { "word", cons, 4 }, 575 { "zcomm", v850_comm, ZCOMMON_SECTION }, 576 { "scomm", v850_comm, SCOMMON_SECTION }, 577 { "tcomm", v850_comm, TCOMMON_SECTION }, 578 { "v850", set_machine, 0 }, 579 { "call_table_data", v850_seg, CALL_TABLE_DATA_SECTION }, 580 { "call_table_text", v850_seg, CALL_TABLE_TEXT_SECTION }, 581 { "v850e", set_machine, bfd_mach_v850e }, 582 { "v850e1", set_machine, bfd_mach_v850e1 }, 583 { "v850e2", set_machine, bfd_mach_v850e2 }, 584 { "v850e2v3", set_machine, bfd_mach_v850e2v3 }, 585 { "v850e2v4", set_machine, bfd_mach_v850e3v5 }, 586 { "v850e3v5", set_machine, bfd_mach_v850e3v5 }, 587 { "longcall", v850_longcode, 1 }, 588 { "longjump", v850_longcode, 2 }, 589 { NULL, NULL, 0 } 590 }; 591 592 /* Opcode hash table. */ 593 static htab_t v850_hash; 594 595 /* This table is sorted. Suitable for searching by a binary search. */ 596 static const struct reg_name pre_defined_registers[] = 597 { 598 { "ep", 30, PROCESSOR_ALL }, /* ep - element ptr. */ 599 { "gp", 4, PROCESSOR_ALL }, /* gp - global ptr. */ 600 { "hp", 2, PROCESSOR_ALL }, /* hp - handler stack ptr. */ 601 { "lp", 31, PROCESSOR_ALL }, /* lp - link ptr. */ 602 { "r0", 0, PROCESSOR_ALL }, 603 { "r1", 1, PROCESSOR_ALL }, 604 { "r10", 10, PROCESSOR_ALL }, 605 { "r11", 11, PROCESSOR_ALL }, 606 { "r12", 12, PROCESSOR_ALL }, 607 { "r13", 13, PROCESSOR_ALL }, 608 { "r14", 14, PROCESSOR_ALL }, 609 { "r15", 15, PROCESSOR_ALL }, 610 { "r16", 16, PROCESSOR_ALL }, 611 { "r17", 17, PROCESSOR_ALL }, 612 { "r18", 18, PROCESSOR_ALL }, 613 { "r19", 19, PROCESSOR_ALL }, 614 { "r2", 2, PROCESSOR_ALL }, 615 { "r20", 20, PROCESSOR_ALL }, 616 { "r21", 21, PROCESSOR_ALL }, 617 { "r22", 22, PROCESSOR_ALL }, 618 { "r23", 23, PROCESSOR_ALL }, 619 { "r24", 24, PROCESSOR_ALL }, 620 { "r25", 25, PROCESSOR_ALL }, 621 { "r26", 26, PROCESSOR_ALL }, 622 { "r27", 27, PROCESSOR_ALL }, 623 { "r28", 28, PROCESSOR_ALL }, 624 { "r29", 29, PROCESSOR_ALL }, 625 { "r3", 3, PROCESSOR_ALL }, 626 { "r30", 30, PROCESSOR_ALL }, 627 { "r31", 31, PROCESSOR_ALL }, 628 { "r4", 4, PROCESSOR_ALL }, 629 { "r5", 5, PROCESSOR_ALL }, 630 { "r6", 6, PROCESSOR_ALL }, 631 { "r7", 7, PROCESSOR_ALL }, 632 { "r8", 8, PROCESSOR_ALL }, 633 { "r9", 9, PROCESSOR_ALL }, 634 { "sp", 3, PROCESSOR_ALL }, /* sp - stack ptr. */ 635 { "tp", 5, PROCESSOR_ALL }, /* tp - text ptr. */ 636 { "zero", 0, PROCESSOR_ALL }, 637 }; 638 639 #define REG_NAME_CNT \ 640 (sizeof (pre_defined_registers) / sizeof (struct reg_name)) 641 642 static const struct reg_name system_registers[] = 643 { 644 { "asid", 23, PROCESSOR_NOT_V850 }, 645 { "bpam", 25, PROCESSOR_NOT_V850 }, 646 { "bpav", 24, PROCESSOR_NOT_V850 }, 647 { "bpc", 22, PROCESSOR_NOT_V850 }, 648 { "bpdm", 27, PROCESSOR_NOT_V850 }, 649 { "bpdv", 26, PROCESSOR_NOT_V850 }, 650 { "bsel", 31, PROCESSOR_V850E2_UP }, 651 { "cfg", 7, PROCESSOR_V850E2V3_UP }, 652 { "ctbp", 20, PROCESSOR_NOT_V850 }, 653 { "ctpc", 16, PROCESSOR_NOT_V850 }, 654 { "ctpsw", 17, PROCESSOR_NOT_V850 }, 655 { "dbic", 15, PROCESSOR_V850E2_UP }, 656 { "dbpc", 18, PROCESSOR_NOT_V850 }, 657 { "dbpsw", 19, PROCESSOR_NOT_V850 }, 658 { "dbwr", 30, PROCESSOR_V850E2_UP }, 659 { "dir", 21, PROCESSOR_NOT_V850 }, 660 { "dpa0l", 16, PROCESSOR_V850E2V3_UP }, 661 { "dpa0u", 17, PROCESSOR_V850E2V3_UP }, 662 { "dpa1l", 18, PROCESSOR_V850E2V3_UP }, 663 { "dpa1u", 19, PROCESSOR_V850E2V3_UP }, 664 { "dpa2l", 20, PROCESSOR_V850E2V3_UP }, 665 { "dpa2u", 21, PROCESSOR_V850E2V3_UP }, 666 { "dpa3l", 22, PROCESSOR_V850E2V3_UP }, 667 { "dpa3u", 23, PROCESSOR_V850E2V3_UP }, 668 { "dpa4l", 24, PROCESSOR_V850E2V3_UP }, 669 { "dpa4u", 25, PROCESSOR_V850E2V3_UP }, 670 { "dpa5l", 26, PROCESSOR_V850E2V3_UP }, 671 { "dpa5u", 27, PROCESSOR_V850E2V3_UP }, 672 { "ecr", 4, PROCESSOR_ALL }, 673 { "eh_base", 3, PROCESSOR_V850E2V3_UP }, 674 { "eh_cfg", 1, PROCESSOR_V850E2V3_UP }, 675 { "eh_reset", 2, PROCESSOR_V850E2V3_UP }, 676 { "eiic", 13, PROCESSOR_V850E2_UP }, 677 { "eipc", 0, PROCESSOR_ALL }, 678 { "eipsw", 1, PROCESSOR_ALL }, 679 { "eiwr", 28, PROCESSOR_V850E2_UP }, 680 { "feic", 14, PROCESSOR_V850E2_UP }, 681 { "fepc", 2, PROCESSOR_ALL }, 682 { "fepsw", 3, PROCESSOR_ALL }, 683 { "fewr", 29, PROCESSOR_V850E2_UP }, 684 { "fpcc", 9, PROCESSOR_V850E2V3_UP }, 685 { "fpcfg", 10, PROCESSOR_V850E2V3_UP }, 686 { "fpec", 11, PROCESSOR_V850E2V3_UP }, 687 { "fpepc", 7, PROCESSOR_V850E2V3_UP }, 688 { "fpspc", 27, PROCESSOR_V850E2V3_UP }, 689 { "fpsr", 6, PROCESSOR_V850E2V3_UP }, 690 { "fpst", 8, PROCESSOR_V850E2V3_UP }, 691 { "ipa0l", 6, PROCESSOR_V850E2V3_UP }, 692 { "ipa0u", 7, PROCESSOR_V850E2V3_UP }, 693 { "ipa1l", 8, PROCESSOR_V850E2V3_UP }, 694 { "ipa1u", 9, PROCESSOR_V850E2V3_UP }, 695 { "ipa2l", 10, PROCESSOR_V850E2V3_UP }, 696 { "ipa2u", 11, PROCESSOR_V850E2V3_UP }, 697 { "ipa3l", 12, PROCESSOR_V850E2V3_UP }, 698 { "ipa3u", 13, PROCESSOR_V850E2V3_UP }, 699 { "ipa4l", 14, PROCESSOR_V850E2V3_UP }, 700 { "ipa4u", 15, PROCESSOR_V850E2V3_UP }, 701 { "mca", 24, PROCESSOR_V850E2V3_UP }, 702 { "mcc", 26, PROCESSOR_V850E2V3_UP }, 703 { "mcr", 27, PROCESSOR_V850E2V3_UP }, 704 { "mcs", 25, PROCESSOR_V850E2V3_UP }, 705 { "mpc", 1, PROCESSOR_V850E2V3_UP }, 706 { "mpm", 0, PROCESSOR_V850E2V3_UP }, 707 { "mpu10_dpa0l", 16, PROCESSOR_V850E2V3_UP }, 708 { "mpu10_dpa0u", 17, PROCESSOR_V850E2V3_UP }, 709 { "mpu10_dpa1l", 18, PROCESSOR_V850E2V3_UP }, 710 { "mpu10_dpa1u", 19, PROCESSOR_V850E2V3_UP }, 711 { "mpu10_dpa2l", 20, PROCESSOR_V850E2V3_UP }, 712 { "mpu10_dpa2u", 21, PROCESSOR_V850E2V3_UP }, 713 { "mpu10_dpa3l", 22, PROCESSOR_V850E2V3_UP }, 714 { "mpu10_dpa3u", 23, PROCESSOR_V850E2V3_UP }, 715 { "mpu10_dpa4l", 24, PROCESSOR_V850E2V3_UP }, 716 { "mpu10_dpa4u", 25, PROCESSOR_V850E2V3_UP }, 717 { "mpu10_dpa5l", 26, PROCESSOR_V850E2V3_UP }, 718 { "mpu10_dpa5u", 27, PROCESSOR_V850E2V3_UP }, 719 { "mpu10_ipa0l", 6, PROCESSOR_V850E2V3_UP }, 720 { "mpu10_ipa0u", 7, PROCESSOR_V850E2V3_UP }, 721 { "mpu10_ipa1l", 8, PROCESSOR_V850E2V3_UP }, 722 { "mpu10_ipa1u", 9, PROCESSOR_V850E2V3_UP }, 723 { "mpu10_ipa2l", 10, PROCESSOR_V850E2V3_UP }, 724 { "mpu10_ipa2u", 11, PROCESSOR_V850E2V3_UP }, 725 { "mpu10_ipa3l", 12, PROCESSOR_V850E2V3_UP }, 726 { "mpu10_ipa3u", 13, PROCESSOR_V850E2V3_UP }, 727 { "mpu10_ipa4l", 14, PROCESSOR_V850E2V3_UP }, 728 { "mpu10_ipa4u", 15, PROCESSOR_V850E2V3_UP }, 729 { "mpu10_mpc", 1, PROCESSOR_V850E2V3_UP }, 730 { "mpu10_mpm", 0, PROCESSOR_V850E2V3_UP }, 731 { "mpu10_tid", 2, PROCESSOR_V850E2V3_UP }, 732 { "mpu10_vmadr", 5, PROCESSOR_V850E2V3_UP }, 733 { "mpu10_vmecr", 3, PROCESSOR_V850E2V3_UP }, 734 { "mpu10_vmtid", 4, PROCESSOR_V850E2V3_UP }, 735 { "pid", 6, PROCESSOR_V850E2V3_UP }, 736 { "pmcr0", 4, PROCESSOR_V850E2V3_UP }, 737 { "pmis2", 14, PROCESSOR_V850E2V3_UP }, 738 { "psw", 5, PROCESSOR_ALL }, 739 { "scbp", 12, PROCESSOR_V850E2V3_UP }, 740 { "sccfg", 11, PROCESSOR_V850E2V3_UP }, 741 { "sr0", 0, PROCESSOR_ALL }, 742 { "sr1", 1, PROCESSOR_ALL }, 743 { "sr10", 10, PROCESSOR_ALL }, 744 { "sr11", 11, PROCESSOR_ALL }, 745 { "sr12", 12, PROCESSOR_ALL }, 746 { "sr13", 13, PROCESSOR_ALL }, 747 { "sr14", 14, PROCESSOR_ALL }, 748 { "sr15", 15, PROCESSOR_ALL }, 749 { "sr16", 16, PROCESSOR_ALL }, 750 { "sr17", 17, PROCESSOR_ALL }, 751 { "sr18", 18, PROCESSOR_ALL }, 752 { "sr19", 19, PROCESSOR_ALL }, 753 { "sr2", 2, PROCESSOR_ALL }, 754 { "sr20", 20, PROCESSOR_ALL }, 755 { "sr21", 21, PROCESSOR_ALL }, 756 { "sr22", 22, PROCESSOR_ALL }, 757 { "sr23", 23, PROCESSOR_ALL }, 758 { "sr24", 24, PROCESSOR_ALL }, 759 { "sr25", 25, PROCESSOR_ALL }, 760 { "sr26", 26, PROCESSOR_ALL }, 761 { "sr27", 27, PROCESSOR_ALL }, 762 { "sr28", 28, PROCESSOR_ALL }, 763 { "sr29", 29, PROCESSOR_ALL }, 764 { "sr3", 3, PROCESSOR_ALL }, 765 { "sr30", 30, PROCESSOR_ALL }, 766 { "sr31", 31, PROCESSOR_ALL }, 767 { "sr4", 4, PROCESSOR_ALL }, 768 { "sr5", 5, PROCESSOR_ALL }, 769 { "sr6", 6, PROCESSOR_ALL }, 770 { "sr7", 7, PROCESSOR_ALL }, 771 { "sr8", 8, PROCESSOR_ALL }, 772 { "sr9", 9, PROCESSOR_ALL }, 773 { "sw_base", 3, PROCESSOR_V850E2V3_UP }, 774 { "sw_cfg", 1, PROCESSOR_V850E2V3_UP }, 775 { "sw_ctl", 0, PROCESSOR_V850E2V3_UP }, 776 { "tid", 2, PROCESSOR_V850E2V3_UP }, 777 { "vmadr", 6, PROCESSOR_V850E2V3_UP }, 778 { "vmecr", 4, PROCESSOR_V850E2V3_UP }, 779 { "vmtid", 5, PROCESSOR_V850E2V3_UP }, 780 { "vsadr", 2, PROCESSOR_V850E2V3_UP }, 781 { "vsecr", 0, PROCESSOR_V850E2V3_UP }, 782 { "vstid", 1, PROCESSOR_V850E2V3_UP }, 783 }; 784 785 #define SYSREG_NAME_CNT \ 786 (sizeof (system_registers) / sizeof (struct reg_name)) 787 788 789 static const struct reg_name cc_names[] = 790 { 791 { "c", 0x1, PROCESSOR_ALL }, 792 { "e", 0x2, PROCESSOR_ALL }, 793 { "ge", 0xe, PROCESSOR_ALL }, 794 { "gt", 0xf, PROCESSOR_ALL }, 795 { "h", 0xb, PROCESSOR_ALL }, 796 { "l", 0x1, PROCESSOR_ALL }, 797 { "le", 0x7, PROCESSOR_ALL }, 798 { "lt", 0x6, PROCESSOR_ALL }, 799 { "n", 0x4, PROCESSOR_ALL }, 800 { "nc", 0x9, PROCESSOR_ALL }, 801 { "ne", 0xa, PROCESSOR_ALL }, 802 { "nh", 0x3, PROCESSOR_ALL }, 803 { "nl", 0x9, PROCESSOR_ALL }, 804 { "ns", 0xc, PROCESSOR_ALL }, 805 { "nv", 0x8, PROCESSOR_ALL }, 806 { "nz", 0xa, PROCESSOR_ALL }, 807 { "p", 0xc, PROCESSOR_ALL }, 808 { "s", 0x4, PROCESSOR_ALL }, 809 #define COND_SA_NUM 0xd 810 { "sa", COND_SA_NUM, PROCESSOR_ALL }, 811 { "t", 0x5, PROCESSOR_ALL }, 812 { "v", 0x0, PROCESSOR_ALL }, 813 { "z", 0x2, PROCESSOR_ALL }, 814 }; 815 816 #define CC_NAME_CNT \ 817 (sizeof (cc_names) / sizeof (struct reg_name)) 818 819 static const struct reg_name float_cc_names[] = 820 { 821 { "eq", 0x2, PROCESSOR_V850E2V3_UP }, /* true. */ 822 { "f", 0x0, PROCESSOR_V850E2V3_UP }, /* true. */ 823 { "ge", 0xd, PROCESSOR_V850E2V3_UP }, /* false. */ 824 { "gl", 0xb, PROCESSOR_V850E2V3_UP }, /* false. */ 825 { "gle", 0x9, PROCESSOR_V850E2V3_UP }, /* false. */ 826 { "gt", 0xf, PROCESSOR_V850E2V3_UP }, /* false. */ 827 { "le", 0xe, PROCESSOR_V850E2V3_UP }, /* true. */ 828 { "lt", 0xc, PROCESSOR_V850E2V3_UP }, /* true. */ 829 { "neq", 0x2, PROCESSOR_V850E2V3_UP }, /* false. */ 830 { "nge", 0xd, PROCESSOR_V850E2V3_UP }, /* true. */ 831 { "ngl", 0xb, PROCESSOR_V850E2V3_UP }, /* true. */ 832 { "ngle",0x9, PROCESSOR_V850E2V3_UP }, /* true. */ 833 { "ngt", 0xf, PROCESSOR_V850E2V3_UP }, /* true. */ 834 { "nle", 0xe, PROCESSOR_V850E2V3_UP }, /* false. */ 835 { "nlt", 0xc, PROCESSOR_V850E2V3_UP }, /* false. */ 836 { "oge", 0x5, PROCESSOR_V850E2V3_UP }, /* false. */ 837 { "ogl", 0x3, PROCESSOR_V850E2V3_UP }, /* false. */ 838 { "ogt", 0x7, PROCESSOR_V850E2V3_UP }, /* false. */ 839 { "ole", 0x6, PROCESSOR_V850E2V3_UP }, /* true. */ 840 { "olt", 0x4, PROCESSOR_V850E2V3_UP }, /* true. */ 841 { "or", 0x1, PROCESSOR_V850E2V3_UP }, /* false. */ 842 { "seq", 0xa, PROCESSOR_V850E2V3_UP }, /* true. */ 843 { "sf", 0x8, PROCESSOR_V850E2V3_UP }, /* true. */ 844 { "sne", 0xa, PROCESSOR_V850E2V3_UP }, /* false. */ 845 { "st", 0x8, PROCESSOR_V850E2V3_UP }, /* false. */ 846 { "t", 0x0, PROCESSOR_V850E2V3_UP }, /* false. */ 847 { "ueq", 0x3, PROCESSOR_V850E2V3_UP }, /* true. */ 848 { "uge", 0x4, PROCESSOR_V850E2V3_UP }, /* false. */ 849 { "ugt", 0x6, PROCESSOR_V850E2V3_UP }, /* false. */ 850 { "ule", 0x7, PROCESSOR_V850E2V3_UP }, /* true. */ 851 { "ult", 0x5, PROCESSOR_V850E2V3_UP }, /* true. */ 852 { "un", 0x1, PROCESSOR_V850E2V3_UP }, /* true. */ 853 }; 854 855 #define FLOAT_CC_NAME_CNT \ 856 (sizeof (float_cc_names) / sizeof (struct reg_name)) 857 858 859 static const struct reg_name cacheop_names[] = 860 { 861 { "cfald", 0x44, PROCESSOR_V850E3V5_UP }, 862 { "cfali", 0x40, PROCESSOR_V850E3V5_UP }, 863 { "chbid", 0x04, PROCESSOR_V850E3V5_UP }, 864 { "chbii", 0x00, PROCESSOR_V850E3V5_UP }, 865 { "chbiwbd", 0x06, PROCESSOR_V850E3V5_UP }, 866 { "chbwbd", 0x07, PROCESSOR_V850E3V5_UP }, 867 { "cibid", 0x24, PROCESSOR_V850E3V5_UP }, 868 { "cibii", 0x20, PROCESSOR_V850E3V5_UP }, 869 { "cibiwbd", 0x26, PROCESSOR_V850E3V5_UP }, 870 { "cibwbd", 0x27, PROCESSOR_V850E3V5_UP }, 871 { "cildd", 0x65, PROCESSOR_V850E3V5_UP }, 872 { "cildi", 0x61, PROCESSOR_V850E3V5_UP }, 873 { "cistd", 0x64, PROCESSOR_V850E3V5_UP }, 874 { "cisti", 0x60, PROCESSOR_V850E3V5_UP }, 875 }; 876 877 #define CACHEOP_NAME_CNT \ 878 (sizeof (cacheop_names) / sizeof (struct reg_name)) 879 880 static const struct reg_name prefop_names[] = 881 { 882 { "prefd", 0x04, PROCESSOR_V850E3V5_UP }, 883 { "prefi", 0x00, PROCESSOR_V850E3V5_UP }, 884 }; 885 886 #define PREFOP_NAME_CNT \ 887 (sizeof (prefop_names) / sizeof (struct reg_name)) 888 889 static const struct reg_name vector_registers[] = 890 { 891 { "vr0", 0, PROCESSOR_V850E3V5_UP }, 892 { "vr1", 1, PROCESSOR_V850E3V5_UP }, 893 { "vr10", 10, PROCESSOR_V850E3V5_UP }, 894 { "vr11", 11, PROCESSOR_V850E3V5_UP }, 895 { "vr12", 12, PROCESSOR_V850E3V5_UP }, 896 { "vr13", 13, PROCESSOR_V850E3V5_UP }, 897 { "vr14", 14, PROCESSOR_V850E3V5_UP }, 898 { "vr15", 15, PROCESSOR_V850E3V5_UP }, 899 { "vr16", 16, PROCESSOR_V850E3V5_UP }, 900 { "vr17", 17, PROCESSOR_V850E3V5_UP }, 901 { "vr18", 18, PROCESSOR_V850E3V5_UP }, 902 { "vr19", 19, PROCESSOR_V850E3V5_UP }, 903 { "vr2", 2, PROCESSOR_V850E3V5_UP }, 904 { "vr20", 20, PROCESSOR_V850E3V5_UP }, 905 { "vr21", 21, PROCESSOR_V850E3V5_UP }, 906 { "vr22", 22, PROCESSOR_V850E3V5_UP }, 907 { "vr23", 23, PROCESSOR_V850E3V5_UP }, 908 { "vr24", 24, PROCESSOR_V850E3V5_UP }, 909 { "vr25", 25, PROCESSOR_V850E3V5_UP }, 910 { "vr26", 26, PROCESSOR_V850E3V5_UP }, 911 { "vr27", 27, PROCESSOR_V850E3V5_UP }, 912 { "vr28", 28, PROCESSOR_V850E3V5_UP }, 913 { "vr29", 29, PROCESSOR_V850E3V5_UP }, 914 { "vr3", 3, PROCESSOR_V850E3V5_UP }, 915 { "vr30", 30, PROCESSOR_V850E3V5_UP }, 916 { "vr31", 31, PROCESSOR_V850E3V5_UP }, 917 { "vr4", 4, PROCESSOR_V850E3V5_UP }, 918 { "vr5", 5, PROCESSOR_V850E3V5_UP }, 919 { "vr6", 6, PROCESSOR_V850E3V5_UP }, 920 { "vr7", 7, PROCESSOR_V850E3V5_UP }, 921 { "vr8", 8, PROCESSOR_V850E3V5_UP }, 922 { "vr9", 9, PROCESSOR_V850E3V5_UP }, 923 }; 924 925 #define VREG_NAME_CNT \ 926 (sizeof (vector_registers) / sizeof (struct reg_name)) 927 928 /* Do a binary search of the given register table to see if NAME is a 929 valid register name. Return the register number from the array on 930 success, or -1 on failure. */ 931 932 static int 933 reg_name_search (const struct reg_name *regs, 934 int regcount, 935 const char *name, 936 bool accept_numbers) 937 { 938 int middle, low, high; 939 int cmp; 940 symbolS *symbolP; 941 942 /* If the register name is a symbol, then evaluate it. */ 943 if ((symbolP = symbol_find (name)) != NULL) 944 { 945 /* If the symbol is an alias for another name then use that. 946 If the symbol is an alias for a number, then return the number. */ 947 if (symbol_equated_p (symbolP)) 948 name 949 = S_GET_NAME (symbol_get_value_expression (symbolP)->X_add_symbol); 950 else if (accept_numbers) 951 { 952 int reg = S_GET_VALUE (symbolP); 953 return reg; 954 } 955 956 /* Otherwise drop through and try parsing name normally. */ 957 } 958 959 low = 0; 960 high = regcount - 1; 961 962 do 963 { 964 middle = (low + high) / 2; 965 cmp = strcasecmp (name, regs[middle].name); 966 if (cmp < 0) 967 high = middle - 1; 968 else if (cmp > 0) 969 low = middle + 1; 970 else 971 return ((regs[middle].processors & processor_mask) 972 ? regs[middle].value 973 : -1); 974 } 975 while (low <= high); 976 return -1; 977 } 978 979 /* Summary of register_name(). 980 981 in: Input_line_pointer points to 1st char of operand. 982 983 out: An expressionS. 984 The operand may have been a register: in this case, X_op == O_register, 985 X_add_number is set to the register number, and truth is returned. 986 Input_line_pointer->(next non-blank) char after operand, or is in 987 its original state. */ 988 989 static bool 990 register_name (expressionS *expressionP) 991 { 992 int reg_number; 993 char *name; 994 char *start; 995 char c; 996 997 /* Find the spelling of the operand. */ 998 start = input_line_pointer; 999 c = get_symbol_name (&name); 1000 1001 reg_number = reg_name_search (pre_defined_registers, REG_NAME_CNT, 1002 name, false); 1003 1004 /* Put back the delimiting char. */ 1005 (void) restore_line_pointer (c); 1006 1007 expressionP->X_add_symbol = NULL; 1008 expressionP->X_op_symbol = NULL; 1009 1010 /* Look to see if it's in the register table. */ 1011 if (reg_number >= 0) 1012 { 1013 expressionP->X_op = O_register; 1014 expressionP->X_add_number = reg_number; 1015 1016 return true; 1017 } 1018 1019 /* Reset the line as if we had not done anything. */ 1020 input_line_pointer = start; 1021 1022 expressionP->X_op = O_illegal; 1023 1024 return false; 1025 } 1026 1027 /* Summary of system_register_name(). 1028 1029 in: INPUT_LINE_POINTER points to 1st char of operand. 1030 EXPRESSIONP points to an expression structure to be filled in. 1031 ACCEPT_NUMBERS is true iff numerical register names may be used. 1032 1033 out: An expressionS structure in expressionP. 1034 The operand may have been a register: in this case, X_op == O_register, 1035 X_add_number is set to the register number, and truth is returned. 1036 Input_line_pointer->(next non-blank) char after operand, or is in 1037 its original state. */ 1038 1039 static bool 1040 system_register_name (expressionS *expressionP, 1041 bool accept_numbers) 1042 { 1043 int reg_number; 1044 char *name; 1045 char *start; 1046 char c; 1047 1048 /* Find the spelling of the operand. */ 1049 start = input_line_pointer; 1050 c = get_symbol_name (&name); 1051 reg_number = reg_name_search (system_registers, SYSREG_NAME_CNT, name, 1052 accept_numbers); 1053 1054 /* Put back the delimiting char. */ 1055 (void) restore_line_pointer (c); 1056 1057 if (reg_number < 0 1058 && accept_numbers) 1059 { 1060 /* Reset input_line pointer. */ 1061 input_line_pointer = start; 1062 1063 if (ISDIGIT (*input_line_pointer)) 1064 { 1065 reg_number = strtol (input_line_pointer, &input_line_pointer, 0); 1066 } 1067 } 1068 1069 expressionP->X_add_symbol = NULL; 1070 expressionP->X_op_symbol = NULL; 1071 1072 /* Look to see if it's in the register table. */ 1073 if (reg_number >= 0) 1074 { 1075 expressionP->X_op = O_register; 1076 expressionP->X_add_number = reg_number; 1077 1078 return true; 1079 } 1080 1081 /* Reset the line as if we had not done anything. */ 1082 input_line_pointer = start; 1083 1084 expressionP->X_op = O_illegal; 1085 1086 return false; 1087 } 1088 1089 /* Summary of cc_name(). 1090 1091 in: INPUT_LINE_POINTER points to 1st char of operand. 1092 1093 out: An expressionS. 1094 The operand may have been a register: in this case, X_op == O_register, 1095 X_add_number is set to the register number, and truth is returned. 1096 Input_line_pointer->(next non-blank) char after operand, or is in 1097 its original state. */ 1098 1099 static bool 1100 cc_name (expressionS *expressionP, 1101 bool accept_numbers) 1102 { 1103 int reg_number; 1104 char *name; 1105 char *start; 1106 char c; 1107 1108 /* Find the spelling of the operand. */ 1109 start = input_line_pointer; 1110 c = get_symbol_name (&name); 1111 reg_number = reg_name_search (cc_names, CC_NAME_CNT, name, accept_numbers); 1112 1113 /* Put back the delimiting char. */ 1114 (void) restore_line_pointer (c); 1115 1116 if (reg_number < 0 1117 && accept_numbers) 1118 { 1119 /* Reset input_line pointer. */ 1120 input_line_pointer = start; 1121 1122 if (ISDIGIT (*input_line_pointer)) 1123 { 1124 reg_number = strtol (input_line_pointer, &input_line_pointer, 0); 1125 } 1126 } 1127 1128 expressionP->X_add_symbol = NULL; 1129 expressionP->X_op_symbol = NULL; 1130 1131 /* Look to see if it's in the register table. */ 1132 if (reg_number >= 0) 1133 { 1134 expressionP->X_op = O_constant; 1135 expressionP->X_add_number = reg_number; 1136 1137 return true; 1138 } 1139 1140 /* Reset the line as if we had not done anything. */ 1141 input_line_pointer = start; 1142 1143 expressionP->X_op = O_illegal; 1144 expressionP->X_add_number = 0; 1145 1146 return false; 1147 } 1148 1149 static bool 1150 float_cc_name (expressionS *expressionP, 1151 bool accept_numbers) 1152 { 1153 int reg_number; 1154 char *name; 1155 char *start; 1156 char c; 1157 1158 /* Find the spelling of the operand. */ 1159 start = input_line_pointer; 1160 c = get_symbol_name (&name); 1161 reg_number = reg_name_search (float_cc_names, FLOAT_CC_NAME_CNT, name, accept_numbers); 1162 1163 /* Put back the delimiting char. */ 1164 (void) restore_line_pointer (c); 1165 1166 if (reg_number < 0 1167 && accept_numbers) 1168 { 1169 /* Reset input_line pointer. */ 1170 input_line_pointer = start; 1171 1172 if (ISDIGIT (*input_line_pointer)) 1173 { 1174 reg_number = strtol (input_line_pointer, &input_line_pointer, 0); 1175 } 1176 } 1177 1178 expressionP->X_add_symbol = NULL; 1179 expressionP->X_op_symbol = NULL; 1180 1181 /* Look to see if it's in the register table. */ 1182 if (reg_number >= 0) 1183 { 1184 expressionP->X_op = O_constant; 1185 expressionP->X_add_number = reg_number; 1186 1187 return true; 1188 } 1189 1190 /* Reset the line as if we had not done anything. */ 1191 input_line_pointer = start; 1192 1193 expressionP->X_op = O_illegal; 1194 expressionP->X_add_number = 0; 1195 1196 return false; 1197 } 1198 1199 static bool 1200 cacheop_name (expressionS * expressionP, 1201 bool accept_numbers) 1202 { 1203 int reg_number; 1204 char *name; 1205 char *start; 1206 char c; 1207 1208 /* Find the spelling of the operand. */ 1209 start = input_line_pointer; 1210 c = get_symbol_name (&name); 1211 reg_number = reg_name_search (cacheop_names, CACHEOP_NAME_CNT, name, accept_numbers); 1212 1213 /* Put back the delimiting char. */ 1214 (void) restore_line_pointer (c); 1215 1216 if (reg_number < 0 1217 && accept_numbers) 1218 { 1219 /* Reset input_line pointer. */ 1220 input_line_pointer = start; 1221 1222 if (ISDIGIT (*input_line_pointer)) 1223 reg_number = strtol (input_line_pointer, &input_line_pointer, 0); 1224 } 1225 1226 expressionP->X_add_symbol = NULL; 1227 expressionP->X_op_symbol = NULL; 1228 1229 /* Look to see if it's in the register table. */ 1230 if (reg_number >= 0) 1231 { 1232 expressionP->X_op = O_constant; 1233 expressionP->X_add_number = reg_number; 1234 1235 return true; 1236 } 1237 1238 /* Reset the line as if we had not done anything. */ 1239 input_line_pointer = start; 1240 1241 expressionP->X_op = O_illegal; 1242 expressionP->X_add_number = 0; 1243 1244 return false; 1245 } 1246 1247 static bool 1248 prefop_name (expressionS * expressionP, 1249 bool accept_numbers) 1250 { 1251 int reg_number; 1252 char *name; 1253 char *start; 1254 char c; 1255 1256 /* Find the spelling of the operand. */ 1257 start = input_line_pointer; 1258 c = get_symbol_name (&name); 1259 reg_number = reg_name_search (prefop_names, PREFOP_NAME_CNT, name, accept_numbers); 1260 1261 /* Put back the delimiting char. */ 1262 (void) restore_line_pointer (c); 1263 1264 if (reg_number < 0 1265 && accept_numbers) 1266 { 1267 /* Reset input_line pointer. */ 1268 input_line_pointer = start; 1269 1270 if (ISDIGIT (*input_line_pointer)) 1271 reg_number = strtol (input_line_pointer, &input_line_pointer, 0); 1272 } 1273 1274 expressionP->X_add_symbol = NULL; 1275 expressionP->X_op_symbol = NULL; 1276 1277 /* Look to see if it's in the register table. */ 1278 if (reg_number >= 0) 1279 { 1280 expressionP->X_op = O_constant; 1281 expressionP->X_add_number = reg_number; 1282 1283 return true; 1284 } 1285 1286 /* Reset the line as if we had not done anything. */ 1287 input_line_pointer = start; 1288 1289 expressionP->X_op = O_illegal; 1290 expressionP->X_add_number = 0; 1291 1292 return false; 1293 } 1294 1295 static bool 1296 vector_register_name (expressionS *expressionP) 1297 { 1298 int reg_number; 1299 char *name; 1300 char *start; 1301 char c; 1302 1303 /* Find the spelling of the operand. */ 1304 start = input_line_pointer; 1305 c = get_symbol_name (&name); 1306 1307 reg_number = reg_name_search (vector_registers, VREG_NAME_CNT, 1308 name, false); 1309 1310 /* Put back the delimiting char. */ 1311 (void) restore_line_pointer (c); 1312 1313 expressionP->X_add_symbol = NULL; 1314 expressionP->X_op_symbol = NULL; 1315 1316 /* Look to see if it's in the register table. */ 1317 if (reg_number >= 0) 1318 { 1319 expressionP->X_op = O_register; 1320 expressionP->X_add_number = reg_number; 1321 1322 return true; 1323 } 1324 1325 /* Reset the line as if we had not done anything. */ 1326 input_line_pointer = start; 1327 1328 expressionP->X_op = O_illegal; 1329 1330 return false; 1331 } 1332 1333 static void 1334 skip_white_space (void) 1335 { 1336 while (is_whitespace (*input_line_pointer)) 1337 ++input_line_pointer; 1338 } 1339 1340 /* Summary of parse_register_list (). 1341 1342 in: INPUT_LINE_POINTER points to 1st char of a list of registers. 1343 INSN is the partially constructed instruction. 1344 OPERAND is the operand being inserted. 1345 1346 out: NULL if the parse completed successfully, otherwise a 1347 pointer to an error message is returned. If the parse 1348 completes the correct bit fields in the instruction 1349 will be filled in. 1350 1351 Parses register lists with the syntax: 1352 1353 { rX } 1354 { rX, rY } 1355 { rX - rY } 1356 { rX - rY, rZ } 1357 etc 1358 1359 and also parses constant expressions whose bits indicate the 1360 registers in the lists. The LSB in the expression refers to 1361 the lowest numbered permissible register in the register list, 1362 and so on upwards. System registers are considered to be very 1363 high numbers. */ 1364 1365 static const char * 1366 parse_register_list (unsigned long *insn, 1367 const struct v850_operand *operand) 1368 { 1369 static int type1_regs[32] = 1370 { 1371 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1372 0, 0, 0, 0, 0, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 1373 }; 1374 1375 int *regs; 1376 expressionS exp; 1377 1378 /* Select a register array to parse. */ 1379 switch (operand->shift) 1380 { 1381 case 0xffe00001: regs = type1_regs; break; 1382 default: 1383 as_bad (_("unknown operand shift: %x\n"), operand->shift); 1384 return _("internal failure in parse_register_list"); 1385 } 1386 1387 skip_white_space (); 1388 1389 /* If the expression starts with a curly brace it is a register list. 1390 Otherwise it is a constant expression, whose bits indicate which 1391 registers are to be included in the list. */ 1392 if (*input_line_pointer != '{') 1393 { 1394 int reg; 1395 int i; 1396 1397 expression (&exp); 1398 1399 if (exp.X_op != O_constant) 1400 return _("constant expression or register list expected"); 1401 1402 if (regs == type1_regs) 1403 { 1404 if (exp.X_add_number & 0xFFFFF000) 1405 return _("high bits set in register list expression"); 1406 1407 for (reg = 20; reg < 32; reg++) 1408 if (exp.X_add_number & (1 << (reg - 20))) 1409 { 1410 for (i = 0; i < 32; i++) 1411 if (regs[i] == reg) 1412 *insn |= (1 << i); 1413 } 1414 } 1415 1416 return NULL; 1417 } 1418 1419 input_line_pointer++; 1420 1421 /* Parse the register list until a terminator (closing curly brace or 1422 new-line) is found. */ 1423 for (;;) 1424 { 1425 skip_white_space (); 1426 1427 if (register_name (&exp)) 1428 { 1429 int i; 1430 1431 /* Locate the given register in the list, and if it is there, 1432 insert the corresponding bit into the instruction. */ 1433 for (i = 0; i < 32; i++) 1434 { 1435 if (regs[i] == exp.X_add_number) 1436 { 1437 *insn |= 1u << i; 1438 break; 1439 } 1440 } 1441 1442 if (i == 32) 1443 return _("illegal register included in list"); 1444 } 1445 else if (system_register_name (&exp, true)) 1446 { 1447 if (regs == type1_regs) 1448 { 1449 return _("system registers cannot be included in list"); 1450 } 1451 } 1452 1453 if (*input_line_pointer == '}') 1454 { 1455 input_line_pointer++; 1456 break; 1457 } 1458 else if (*input_line_pointer == ',') 1459 { 1460 input_line_pointer++; 1461 continue; 1462 } 1463 else if (*input_line_pointer == '-') 1464 { 1465 /* We have encountered a range of registers: rX - rY. */ 1466 int j; 1467 expressionS exp2; 1468 1469 /* Skip the dash. */ 1470 ++input_line_pointer; 1471 1472 /* Get the second register in the range. */ 1473 if (! register_name (&exp2)) 1474 { 1475 return _("second register should follow dash in register list"); 1476 } 1477 1478 if (exp.X_add_number > exp2.X_add_number) 1479 { 1480 return _("second register should be greater than first register"); 1481 } 1482 1483 /* Add the rest of the registers in the range. */ 1484 for (j = exp.X_add_number + 1; j <= exp2.X_add_number; j++) 1485 { 1486 int i; 1487 1488 /* Locate the given register in the list, and if it is there, 1489 insert the corresponding bit into the instruction. */ 1490 for (i = 0; i < 32; i++) 1491 { 1492 if (regs[i] == j) 1493 { 1494 *insn |= (1 << i); 1495 break; 1496 } 1497 } 1498 1499 if (i == 32) 1500 return _("illegal register included in list"); 1501 } 1502 1503 exp = exp2; 1504 } 1505 else 1506 break; 1507 } 1508 1509 return NULL; 1510 } 1511 1512 const char md_shortopts[] = "m:"; 1513 1514 const struct option md_longopts[] = 1515 { 1516 #define OPTION_DISP_SIZE_DEFAULT_22 (OPTION_MD_BASE) 1517 {"disp-size-default-22", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_22}, 1518 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 1) 1519 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32}, 1520 {NULL, no_argument, NULL, 0} 1521 }; 1522 1523 const size_t md_longopts_size = sizeof (md_longopts); 1524 1525 static bool v850_data_8 = false; 1526 1527 void 1528 md_show_usage (FILE *stream) 1529 { 1530 fprintf (stream, _(" V850 options:\n")); 1531 fprintf (stream, _(" -mwarn-signed-overflow Warn if signed immediate values overflow\n")); 1532 fprintf (stream, _(" -mwarn-unsigned-overflow Warn if unsigned immediate values overflow\n")); 1533 fprintf (stream, _(" -mv850 The code is targeted at the v850\n")); 1534 fprintf (stream, _(" -mv850e The code is targeted at the v850e\n")); 1535 fprintf (stream, _(" -mv850e1 The code is targeted at the v850e1\n")); 1536 fprintf (stream, _(" -mv850e2 The code is targeted at the v850e2\n")); 1537 fprintf (stream, _(" -mv850e2v3 The code is targeted at the v850e2v3\n")); 1538 fprintf (stream, _(" -mv850e2v4 Alias for -mv850e3v5\n")); 1539 fprintf (stream, _(" -mv850e3v5 The code is targeted at the v850e3v5\n")); 1540 fprintf (stream, _(" -mrelax Enable relaxation\n")); 1541 fprintf (stream, _(" --disp-size-default-22 branch displacement with unknown size is 22 bits (default)\n")); 1542 fprintf (stream, _(" --disp-size-default-32 branch displacement with unknown size is 32 bits\n")); 1543 fprintf (stream, _(" -mextension enable extension opcode support\n")); 1544 fprintf (stream, _(" -mno-bcond17 disable b<cond> disp17 instruction\n")); 1545 fprintf (stream, _(" -mno-stld23 disable st/ld offset23 instruction\n")); 1546 fprintf (stream, _(" -mgcc-abi Mark the binary as using the old GCC ABI\n")); 1547 fprintf (stream, _(" -mrh850-abi Mark the binary as using the RH850 ABI (default)\n")); 1548 fprintf (stream, _(" -m8byte-align Mark the binary as using 64-bit alignment\n")); 1549 fprintf (stream, _(" -m4byte-align Mark the binary as using 32-bit alignment (default)\n")); 1550 fprintf (stream, _(" -msoft-float Mark the binary as not using FP insns (default for pre e2v3)\n")); 1551 fprintf (stream, _(" -mhard-float Mark the binary as using FP insns (default for e2v3 and up)\n")); 1552 } 1553 1554 int 1555 md_parse_option (int c, const char *arg) 1556 { 1557 if (c != 'm') 1558 { 1559 switch (c) 1560 { 1561 case OPTION_DISP_SIZE_DEFAULT_22: 1562 default_disp_size = 22; 1563 return 1; 1564 1565 case OPTION_DISP_SIZE_DEFAULT_32: 1566 default_disp_size = 32; 1567 return 1; 1568 } 1569 return 0; 1570 } 1571 1572 if (strcmp (arg, "warn-signed-overflow") == 0) 1573 warn_signed_overflows = true; 1574 1575 else if (strcmp (arg, "warn-unsigned-overflow") == 0) 1576 warn_unsigned_overflows = true; 1577 1578 else if (strcmp (arg, "v850") == 0) 1579 { 1580 machine = 0; 1581 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); 1582 } 1583 else if (strcmp (arg, "v850e") == 0) 1584 { 1585 machine = bfd_mach_v850e; 1586 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); 1587 } 1588 else if (strcmp (arg, "v850e1") == 0) 1589 { 1590 machine = bfd_mach_v850e1; 1591 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E1); 1592 } 1593 else if (strcmp (arg, "v850e2") == 0) 1594 { 1595 machine = bfd_mach_v850e2; 1596 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2); 1597 } 1598 else if (strcmp (arg, "v850e2v3") == 0) 1599 { 1600 machine = bfd_mach_v850e2v3; 1601 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3); 1602 } 1603 else if (strcmp (arg, "v850e2v4") == 0) 1604 { 1605 machine = bfd_mach_v850e3v5; 1606 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5); 1607 } 1608 else if (strcmp (arg, "v850e3v5") == 0) 1609 { 1610 machine = bfd_mach_v850e3v5; 1611 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5); 1612 } 1613 else if (strcmp (arg, "extension") == 0) 1614 { 1615 processor_mask |= PROCESSOR_OPTION_EXTENSION | PROCESSOR_OPTION_ALIAS; 1616 } 1617 else if (strcmp (arg, "no-bcond17") == 0) 1618 { 1619 no_bcond17 = 1; 1620 } 1621 else if (strcmp (arg, "no-stld23") == 0) 1622 { 1623 no_stld23 = 1; 1624 } 1625 else if (strcmp (arg, "relax") == 0) 1626 v850_relax = 1; 1627 else if (strcmp (arg, "gcc-abi") == 0) 1628 { 1629 v850_target_arch = bfd_arch_v850; 1630 v850_target_format = "elf32-v850"; 1631 } 1632 else if (strcmp (arg, "rh850-abi") == 0) 1633 { 1634 v850_target_arch = bfd_arch_v850_rh850; 1635 v850_target_format = "elf32-v850-rh850"; 1636 } 1637 else if (strcmp (arg, "8byte-align") == 0) 1638 { 1639 v850_data_8 = true; 1640 v850_e_flags |= EF_RH850_DATA_ALIGN8; 1641 } 1642 else if (strcmp (arg, "4byte-align") == 0) 1643 { 1644 v850_data_8 = false; 1645 v850_e_flags &= ~ EF_RH850_DATA_ALIGN8; 1646 } 1647 else if (strcmp (arg, "soft-float") == 0) 1648 soft_float = 1; 1649 else if (strcmp (arg, "hard-float") == 0) 1650 soft_float = 0; 1651 else 1652 return 0; 1653 1654 return 1; 1655 } 1656 1657 symbolS * 1658 md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 1659 { 1660 return 0; 1661 } 1662 1663 const char * 1664 md_atof (int type, char *litp, int *sizep) 1665 { 1666 return ieee_md_atof (type, litp, sizep, false); 1667 } 1668 1669 /* Very gross. */ 1670 1671 void 1672 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, 1673 asection *sec ATTRIBUTE_UNUSED, 1674 fragS *fragP) 1675 { 1676 unsigned int opindex = (uintptr_t) fragP->fr_opcode; 1677 1678 if (fragP->fr_subtype == SUBYPTE_LOOP_16_22) 1679 { 1680 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 1681 fragP->fr_offset, 1, BFD_RELOC_UNUSED + opindex); 1682 fragP->fr_fix += 4; 1683 } 1684 else if (fragP->fr_subtype == SUBYPTE_LOOP_16_22 + 1) 1685 { 1686 char *buffer = fragP->fr_literal + fragP->fr_fix; 1687 int loop_reg = buffer[0] & 0x1f; 1688 1689 /* Add -1.reg. */ 1690 md_number_to_chars (buffer, 0x025f | (loop_reg << 11), 2); 1691 /* Now create the conditional branch + fixup to the final target. */ 1692 /* 0x000107ea = bne LBL(disp17). */ 1693 md_number_to_chars (buffer + 2, 0x000107ea, 4); 1694 fix_new (fragP, fragP->fr_fix + 2, 4, fragP->fr_symbol, 1695 fragP->fr_offset, 1, BFD_RELOC_V850_17_PCREL); 1696 fragP->fr_fix += 6; 1697 } 1698 /* In range conditional or unconditional branch. */ 1699 else if (fragP->fr_subtype == SUBYPTE_COND_9_22 1700 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22 1701 || fragP->fr_subtype == SUBYPTE_COND_9_22_32 1702 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 1703 || fragP->fr_subtype == SUBYPTE_COND_9_17_22 1704 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 1705 || fragP->fr_subtype == SUBYPTE_SA_9_22 1706 || fragP->fr_subtype == SUBYPTE_SA_9_22_32 1707 || fragP->fr_subtype == SUBYPTE_SA_9_17_22 1708 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32) 1709 1710 { 1711 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 1712 fragP->fr_offset, 1, BFD_RELOC_UNUSED + opindex); 1713 fragP->fr_fix += 2; 1714 } 1715 /* V850e2r-v3 17bit conditional branch. */ 1716 else if (fragP->fr_subtype == SUBYPTE_COND_9_17_22 + 1 1717 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 1 1718 || fragP->fr_subtype == SUBYPTE_SA_9_17_22 + 1 1719 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 1) 1720 { 1721 char *buffer = fragP->fr_literal + fragP->fr_fix; 1722 1723 buffer[0] &= 0x0f; /* Use condition. */ 1724 buffer[0] |= 0xe0; 1725 buffer[1] = 0x07; 1726 1727 /* Now create the unconditional branch + fixup to the final 1728 target. */ 1729 md_number_to_chars (buffer + 2, 0x0001, 2); 1730 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 1731 fragP->fr_offset, 1, BFD_RELOC_V850_17_PCREL); 1732 fragP->fr_fix += 4; 1733 } 1734 /* Out of range conditional branch. Emit a branch around a 22bit jump. */ 1735 else if (fragP->fr_subtype == SUBYPTE_COND_9_22 + 1 1736 || fragP->fr_subtype == SUBYPTE_COND_9_22_32 + 1 1737 || fragP->fr_subtype == SUBYPTE_COND_9_17_22 + 2 1738 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 2) 1739 { 1740 char *buffer = fragP->fr_literal + fragP->fr_fix; 1741 1742 /* Reverse the condition of the first branch. */ 1743 buffer[0] ^= 0x08; 1744 /* Mask off all the displacement bits. */ 1745 buffer[0] &= 0x8f; 1746 buffer[1] &= 0x07; 1747 /* Now set the displacement bits so that we branch 1748 around the unconditional branch. */ 1749 buffer[0] |= 0x30; 1750 1751 /* Now create the unconditional branch + fixup to the final 1752 target. */ 1753 md_number_to_chars (buffer + 2, 0x00000780, 4); 1754 fix_new (fragP, fragP->fr_fix + 2, 4, fragP->fr_symbol, 1755 fragP->fr_offset, 1, BFD_RELOC_V850_22_PCREL); 1756 fragP->fr_fix += 6; 1757 } 1758 /* Out of range conditional branch. Emit a branch around a 32bit jump. */ 1759 else if (fragP->fr_subtype == SUBYPTE_COND_9_22_32 + 2 1760 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 3) 1761 { 1762 char *buffer = fragP->fr_literal + fragP->fr_fix; 1763 1764 /* Reverse the condition of the first branch. */ 1765 buffer[0] ^= 0x08; 1766 /* Mask off all the displacement bits. */ 1767 buffer[0] &= 0x8f; 1768 buffer[1] &= 0x07; 1769 /* Now set the displacement bits so that we branch 1770 around the unconditional branch. */ 1771 buffer[0] |= 0x40; 1772 1773 /* Now create the unconditional branch + fixup to the final 1774 target. */ 1775 md_number_to_chars (buffer + 2, 0x02e0, 2); 1776 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol, 1777 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL); 1778 fragP->fr_fix += 8; 1779 } 1780 /* Out of range unconditional branch. Emit a 22bit jump. */ 1781 else if (fragP->fr_subtype == SUBYPTE_UNCOND_9_22 + 1 1782 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 + 1) 1783 { 1784 md_number_to_chars (fragP->fr_fix + fragP->fr_literal, 0x00000780, 4); 1785 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 1786 fragP->fr_offset, 1, BFD_RELOC_V850_22_PCREL); 1787 fragP->fr_fix += 4; 1788 } 1789 /* Out of range unconditional branch. Emit a 32bit jump. */ 1790 else if (fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 + 2) 1791 { 1792 md_number_to_chars (fragP->fr_fix + fragP->fr_literal, 0x02e0, 2); 1793 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol, 1794 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL); 1795 fragP->fr_fix += 6; 1796 } 1797 /* Out of range SA conditional branch. Emit a branch to a 22bit jump. */ 1798 else if (fragP->fr_subtype == SUBYPTE_SA_9_22 + 1 1799 || fragP->fr_subtype == SUBYPTE_SA_9_22_32 + 1 1800 || fragP->fr_subtype == SUBYPTE_SA_9_17_22 + 2 1801 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 2) 1802 { 1803 char *buffer = fragP->fr_literal + fragP->fr_fix; 1804 1805 /* bsa .+4 */ 1806 buffer[0] &= 0x8f; 1807 buffer[0] |= 0x20; 1808 buffer[1] &= 0x07; 1809 1810 /* br .+6 */ 1811 md_number_to_chars (buffer + 2, 0x05b5, 2); 1812 1813 /* Now create the unconditional branch + fixup to the final 1814 target. */ 1815 /* jr SYM */ 1816 md_number_to_chars (buffer + 4, 0x00000780, 4); 1817 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol, 1818 fragP->fr_offset, 1, BFD_RELOC_V850_22_PCREL); 1819 fragP->fr_fix += 8; 1820 } 1821 /* Out of range SA conditional branch. Emit a branch around a 32bit jump. */ 1822 else if (fragP->fr_subtype == SUBYPTE_SA_9_22_32 + 2 1823 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 3) 1824 { 1825 char *buffer = fragP->fr_literal + fragP->fr_fix; 1826 1827 /* bsa .+2 */ 1828 buffer[0] &= 0x8f; 1829 buffer[0] |= 0x20; 1830 buffer[1] &= 0x07; 1831 1832 /* br .+8 */ 1833 md_number_to_chars (buffer + 2, 0x05c5, 2); 1834 1835 /* Now create the unconditional branch + fixup to the final 1836 target. */ 1837 /* jr SYM */ 1838 md_number_to_chars (buffer + 4, 0x02e0, 2); 1839 fix_new (fragP, fragP->fr_fix + 6, 4, fragP->fr_symbol, 1840 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL); 1841 1842 fragP->fr_fix += 10; 1843 } 1844 else 1845 abort (); 1846 } 1847 1848 valueT 1849 md_section_align (asection *seg, valueT addr) 1850 { 1851 int align = bfd_section_alignment (seg); 1852 return ((addr + (1 << align) - 1) & -(1 << align)); 1853 } 1854 1855 void 1856 md_begin (void) 1857 { 1858 const char *prev_name = ""; 1859 const struct v850_opcode *op; 1860 1861 if (startswith (TARGET_CPU, "v850e3v5")) 1862 { 1863 if (machine == -1) 1864 machine = bfd_mach_v850e3v5; 1865 1866 if (!processor_mask) 1867 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5); 1868 } 1869 else if (startswith (TARGET_CPU, "v850e2v4")) 1870 { 1871 if (machine == -1) 1872 machine = bfd_mach_v850e3v5; 1873 1874 if (!processor_mask) 1875 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5); 1876 } 1877 else if (startswith (TARGET_CPU, "v850e2v3")) 1878 { 1879 if (machine == -1) 1880 machine = bfd_mach_v850e2v3; 1881 1882 if (!processor_mask) 1883 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3); 1884 } 1885 else if (startswith (TARGET_CPU, "v850e2")) 1886 { 1887 if (machine == -1) 1888 machine = bfd_mach_v850e2; 1889 1890 if (!processor_mask) 1891 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2); 1892 } 1893 else if (startswith (TARGET_CPU, "v850e1")) 1894 { 1895 if (machine == -1) 1896 machine = bfd_mach_v850e1; 1897 1898 if (!processor_mask) 1899 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E1); 1900 } 1901 else if (startswith (TARGET_CPU, "v850e")) 1902 { 1903 if (machine == -1) 1904 machine = bfd_mach_v850e; 1905 1906 if (!processor_mask) 1907 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); 1908 } 1909 else if (startswith (TARGET_CPU, "v850")) 1910 { 1911 if (machine == -1) 1912 machine = 0; 1913 1914 if (!processor_mask) 1915 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); 1916 } 1917 else 1918 /* xgettext:c-format */ 1919 as_bad (_("Unable to determine default target processor from string: %s"), 1920 TARGET_CPU); 1921 1922 if (soft_float == -1) 1923 soft_float = machine < bfd_mach_v850e2v3; 1924 1925 v850_hash = str_htab_create (); 1926 1927 /* Insert unique names into hash table. The V850 instruction set 1928 has many identical opcode names that have different opcodes based 1929 on the operands. This hash table then provides a quick index to 1930 the first opcode with a particular name in the opcode table. */ 1931 op = v850_opcodes; 1932 while (op->name) 1933 { 1934 if (strcmp (prev_name, op->name)) 1935 { 1936 prev_name = op->name; 1937 str_hash_insert (v850_hash, op->name, op, 0); 1938 } 1939 op++; 1940 } 1941 1942 bfd_set_arch_mach (stdoutput, v850_target_arch, machine); 1943 bfd_set_private_flags (stdoutput, v850_e_flags); 1944 } 1945 1946 1947 static bfd_reloc_code_real_type 1948 handle_hi016 (const struct v850_operand *operand, const char **errmsg) 1949 { 1950 if (operand == NULL) 1951 return BFD_RELOC_HI16; 1952 1953 if (operand->default_reloc == BFD_RELOC_HI16) 1954 return BFD_RELOC_HI16; 1955 1956 if (operand->default_reloc == BFD_RELOC_HI16_S) 1957 return BFD_RELOC_HI16; 1958 1959 if (operand->default_reloc == BFD_RELOC_16) 1960 return BFD_RELOC_HI16; 1961 1962 *errmsg = _("hi0() relocation used on an instruction which does " 1963 "not support it"); 1964 return BFD_RELOC_64; /* Used to indicate an error condition. */ 1965 } 1966 1967 static bfd_reloc_code_real_type 1968 handle_hi16 (const struct v850_operand *operand, const char **errmsg) 1969 { 1970 if (operand == NULL) 1971 return BFD_RELOC_HI16_S; 1972 1973 if (operand->default_reloc == BFD_RELOC_HI16_S) 1974 return BFD_RELOC_HI16_S; 1975 1976 if (operand->default_reloc == BFD_RELOC_HI16) 1977 return BFD_RELOC_HI16_S; 1978 1979 if (operand->default_reloc == BFD_RELOC_16) 1980 return BFD_RELOC_HI16_S; 1981 1982 *errmsg = _("hi() relocation used on an instruction which does " 1983 "not support it"); 1984 return BFD_RELOC_64; /* Used to indicate an error condition. */ 1985 } 1986 1987 static bfd_reloc_code_real_type 1988 handle_lo16 (const struct v850_operand *operand, const char **errmsg) 1989 { 1990 if (operand == NULL) 1991 return BFD_RELOC_LO16; 1992 1993 switch (operand->default_reloc) 1994 { 1995 case BFD_RELOC_LO16: return BFD_RELOC_LO16; 1996 case BFD_RELOC_V850_LO16_SPLIT_OFFSET: return BFD_RELOC_V850_LO16_SPLIT_OFFSET; 1997 case BFD_RELOC_V850_16_SPLIT_OFFSET: return BFD_RELOC_V850_LO16_SPLIT_OFFSET; 1998 case BFD_RELOC_V850_16_S1: return BFD_RELOC_V850_LO16_S1; 1999 case BFD_RELOC_16: return BFD_RELOC_LO16; 2000 default: 2001 *errmsg = _("lo() relocation used on an instruction which does " 2002 "not support it"); 2003 return BFD_RELOC_64; /* Used to indicate an error condition. */ 2004 } 2005 } 2006 2007 static bfd_reloc_code_real_type 2008 handle_ctoff (const struct v850_operand *operand, const char **errmsg) 2009 { 2010 if (v850_target_arch == bfd_arch_v850_rh850) 2011 { 2012 *errmsg = _("ctoff() is not supported by the rh850 ABI. Use -mgcc-abi instead"); 2013 return BFD_RELOC_64; /* Used to indicate an error condition. */ 2014 } 2015 2016 if (operand == NULL) 2017 return BFD_RELOC_V850_CALLT_16_16_OFFSET; 2018 2019 if (operand->default_reloc == BFD_RELOC_V850_CALLT_6_7_OFFSET) 2020 return operand->default_reloc; 2021 2022 if (operand->default_reloc == BFD_RELOC_V850_16_S1) 2023 return BFD_RELOC_V850_CALLT_15_16_OFFSET; 2024 2025 if (operand->default_reloc == BFD_RELOC_16) 2026 return BFD_RELOC_V850_CALLT_16_16_OFFSET; 2027 2028 *errmsg = _("ctoff() relocation used on an instruction which does not support it"); 2029 return BFD_RELOC_64; /* Used to indicate an error condition. */ 2030 } 2031 2032 static bfd_reloc_code_real_type 2033 handle_sdaoff (const struct v850_operand *operand, const char **errmsg) 2034 { 2035 if (operand == NULL) 2036 return BFD_RELOC_V850_SDA_16_16_OFFSET; 2037 2038 if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET) 2039 return BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET; 2040 2041 if (operand->default_reloc == BFD_RELOC_16) 2042 return BFD_RELOC_V850_SDA_16_16_OFFSET; 2043 2044 if (operand->default_reloc == BFD_RELOC_V850_16_S1) 2045 return BFD_RELOC_V850_SDA_15_16_OFFSET; 2046 2047 *errmsg = _("sdaoff() relocation used on an instruction which does not support it"); 2048 return BFD_RELOC_64; /* Used to indicate an error condition. */ 2049 } 2050 2051 static bfd_reloc_code_real_type 2052 handle_zdaoff (const struct v850_operand *operand, const char **errmsg) 2053 { 2054 if (operand == NULL) 2055 return BFD_RELOC_V850_ZDA_16_16_OFFSET; 2056 2057 if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET) 2058 return BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET; 2059 2060 if (operand->default_reloc == BFD_RELOC_16) 2061 return BFD_RELOC_V850_ZDA_16_16_OFFSET; 2062 2063 if (operand->default_reloc == BFD_RELOC_V850_16_S1) 2064 return BFD_RELOC_V850_ZDA_15_16_OFFSET; 2065 2066 *errmsg = _("zdaoff() relocation used on an instruction which does not support it"); 2067 return BFD_RELOC_64; /* Used to indicate an error condition. */ 2068 } 2069 2070 static bfd_reloc_code_real_type 2071 handle_tdaoff (const struct v850_operand *operand, const char **errmsg) 2072 { 2073 if (operand == NULL) 2074 /* Data item, not an instruction. */ 2075 return BFD_RELOC_V850_TDA_16_16_OFFSET; 2076 2077 switch (operand->default_reloc) 2078 { 2079 /* sld.hu, operand: D5-4. */ 2080 case BFD_RELOC_V850_TDA_4_5_OFFSET: 2081 /* sld.bu, operand: D4. */ 2082 case BFD_RELOC_V850_TDA_4_4_OFFSET: 2083 /* sld.w/sst.w, operand: D8_6. */ 2084 case BFD_RELOC_V850_TDA_6_8_OFFSET: 2085 /* sld.h/sst.h, operand: D8_7. */ 2086 case BFD_RELOC_V850_TDA_7_8_OFFSET: 2087 /* sld.b/sst.b, operand: D7. */ 2088 case BFD_RELOC_V850_TDA_7_7_OFFSET: 2089 return operand->default_reloc; 2090 default: 2091 break; 2092 } 2093 2094 if (operand->default_reloc == BFD_RELOC_16 && operand->shift == 16) 2095 /* set1 & chums, operands: D16. */ 2096 return BFD_RELOC_V850_TDA_16_16_OFFSET; 2097 2098 *errmsg = _("tdaoff() relocation used on an instruction which does not support it"); 2099 /* Used to indicate an error condition. */ 2100 return BFD_RELOC_64; 2101 } 2102 2103 /* Warning: The code in this function relies upon the definitions 2104 in the v850_operands[] array (defined in opcodes/v850-opc.c) 2105 matching the hard coded values contained herein. */ 2106 2107 static bfd_reloc_code_real_type 2108 v850_reloc_prefix (const struct v850_operand *operand, const char **errmsg) 2109 { 2110 bool paren_skipped = false; 2111 2112 /* Skip leading opening parenthesis. */ 2113 if (*input_line_pointer == '(') 2114 { 2115 ++input_line_pointer; 2116 paren_skipped = true; 2117 } 2118 2119 #define CHECK_(name, reloc) \ 2120 if (strncmp (input_line_pointer, name "(", strlen (name) + 1) == 0) \ 2121 { \ 2122 input_line_pointer += strlen (name); \ 2123 return reloc; \ 2124 } 2125 2126 CHECK_ ("hi0", handle_hi016 (operand, errmsg)); 2127 CHECK_ ("hi", handle_hi16 (operand, errmsg)); 2128 CHECK_ ("lo", handle_lo16 (operand, errmsg)); 2129 CHECK_ ("sdaoff", handle_sdaoff (operand, errmsg)); 2130 CHECK_ ("zdaoff", handle_zdaoff (operand, errmsg)); 2131 CHECK_ ("tdaoff", handle_tdaoff (operand, errmsg)); 2132 CHECK_ ("hilo", BFD_RELOC_32); 2133 CHECK_ ("lo23", BFD_RELOC_V850_23); 2134 CHECK_ ("ctoff", handle_ctoff (operand, errmsg)); 2135 2136 /* Restore skipped parenthesis. */ 2137 if (paren_skipped) 2138 --input_line_pointer; 2139 2140 return BFD_RELOC_NONE; 2141 } 2142 2143 /* Insert an operand value into an instruction. */ 2144 2145 static unsigned long 2146 v850_insert_operand (unsigned long insn, 2147 const struct v850_operand *operand, 2148 offsetT val, 2149 const char **errmsg) 2150 { 2151 if (operand->insert) 2152 { 2153 const char *message = NULL; 2154 2155 insn = operand->insert (insn, val, &message); 2156 if (message != NULL) 2157 { 2158 if ((operand->flags & V850_OPERAND_SIGNED) 2159 && ! warn_signed_overflows 2160 && v850_msg_is_out_of_range (message)) 2161 { 2162 /* Skip warning... */ 2163 } 2164 else if ((operand->flags & V850_OPERAND_SIGNED) == 0 2165 && ! warn_unsigned_overflows 2166 && v850_msg_is_out_of_range (message)) 2167 { 2168 /* Skip warning... */ 2169 } 2170 else 2171 { 2172 if (errmsg != NULL) 2173 *errmsg = message; 2174 } 2175 } 2176 } 2177 else if (operand->bits == -1 2178 || operand->flags & V850E_IMMEDIATE16 2179 || operand->flags & V850E_IMMEDIATE23 2180 || operand->flags & V850E_IMMEDIATE32) 2181 { 2182 abort (); 2183 } 2184 else 2185 { 2186 if (operand->bits < 32) 2187 { 2188 long min, max; 2189 2190 if ((operand->flags & V850_OPERAND_SIGNED) != 0) 2191 { 2192 if (! warn_signed_overflows) 2193 max = (1 << operand->bits) - 1; 2194 else 2195 max = (1 << (operand->bits - 1)) - 1; 2196 2197 min = -(1 << (operand->bits - 1)); 2198 } 2199 else 2200 { 2201 max = (1 << operand->bits) - 1; 2202 2203 if (! warn_unsigned_overflows) 2204 min = -(1 << (operand->bits - 1)); 2205 else 2206 min = 0; 2207 } 2208 2209 /* Some people write constants with the sign extension done by 2210 hand but only up to 32 bits. This shouldn't really be valid, 2211 but, to permit this code to assemble on a 64-bit host, we 2212 sign extend the 32-bit value to 64 bits if so doing makes the 2213 value valid. */ 2214 if (val > max 2215 && (offsetT) (val - 0x80000000 - 0x80000000) >= min 2216 && (offsetT) (val - 0x80000000 - 0x80000000) <= max) 2217 val = val - 0x80000000 - 0x80000000; 2218 2219 /* Similarly, people write expressions like ~(1<<15), and expect 2220 this to be OK for a 32-bit unsigned value. */ 2221 else if (val < min 2222 && (offsetT) (val + 0x80000000 + 0x80000000) >= min 2223 && (offsetT) (val + 0x80000000 + 0x80000000) <= max) 2224 val = val + 0x80000000 + 0x80000000; 2225 2226 else if (val < (offsetT) min || val > (offsetT) max) 2227 { 2228 static char buf [128]; 2229 2230 /* Restore min and mix to expected values for decimal ranges. */ 2231 if ((operand->flags & V850_OPERAND_SIGNED) 2232 && ! warn_signed_overflows) 2233 max = (1 << (operand->bits - 1)) - 1; 2234 2235 if (! (operand->flags & V850_OPERAND_SIGNED) 2236 && ! warn_unsigned_overflows) 2237 min = 0; 2238 2239 sprintf (buf, _("operand out of range (%d is not between %d and %d)"), 2240 (int) val, (int) min, (int) max); 2241 *errmsg = buf; 2242 } 2243 2244 insn |= (((long) val & ((1 << operand->bits) - 1)) << operand->shift); 2245 } 2246 else 2247 { 2248 insn |= (((long) val) << operand->shift); 2249 } 2250 } 2251 2252 return insn; 2253 } 2254 2255 static char copy_of_instruction[128]; 2257 2258 void 2259 md_assemble (char *str) 2260 { 2261 char *s; 2262 char *start_of_operands; 2263 struct v850_opcode *opcode; 2264 struct v850_opcode *next_opcode; 2265 const unsigned char *opindex_ptr; 2266 int next_opindex; 2267 int relaxable = 0; 2268 unsigned long insn = 0; 2269 unsigned long insn_size; 2270 char *f = NULL; 2271 int i; 2272 int match; 2273 bool extra_data_after_insn = false; 2274 unsigned extra_data_len = 0; 2275 unsigned long extra_data = 0; 2276 char *saved_input_line_pointer; 2277 char most_match_errmsg[1024]; 2278 int most_match_count = -1; 2279 2280 strncpy (copy_of_instruction, str, sizeof (copy_of_instruction) - 1); 2281 most_match_errmsg[0] = 0; 2282 2283 /* Get the opcode. */ 2284 for (s = str; ! is_end_of_stmt (*s) && ! is_whitespace (*s); s++) 2285 continue; 2286 2287 if (*s != '\0') 2288 *s++ = '\0'; 2289 2290 /* Find the first opcode with the proper name. */ 2291 opcode = str_hash_find (v850_hash, str); 2292 if (opcode == NULL) 2293 { 2294 /* xgettext:c-format */ 2295 as_bad (_("Unrecognized opcode: `%s'"), str); 2296 ignore_rest_of_line (); 2297 return; 2298 } 2299 2300 str = s; 2301 while (is_whitespace (*str)) 2302 ++str; 2303 2304 start_of_operands = str; 2305 2306 saved_input_line_pointer = input_line_pointer; 2307 2308 for (;;) 2309 { 2310 const char *errmsg = NULL; 2311 const char *warningmsg = NULL; 2312 2313 match = 0; 2314 opindex_ptr = opcode->operands; 2315 2316 if (no_stld23) 2317 { 2318 if ((startswith (opcode->name, "st.") 2319 && v850_operands[opcode->operands[1]].bits == 23) 2320 || (startswith (opcode->name, "ld.") 2321 && v850_operands[opcode->operands[0]].bits == 23)) 2322 { 2323 errmsg = _("st/ld offset 23 instruction was disabled ."); 2324 goto error; 2325 } 2326 } 2327 2328 if ((opcode->processors & processor_mask & PROCESSOR_MASK) == 0 2329 || (((opcode->processors & ~PROCESSOR_MASK) != 0) 2330 && ((opcode->processors & processor_mask & ~PROCESSOR_MASK) == 0))) 2331 { 2332 errmsg = _("Target processor does not support this instruction."); 2333 goto error; 2334 } 2335 2336 relaxable = 0; 2337 fc = 0; 2338 next_opindex = 0; 2339 insn = opcode->opcode; 2340 extra_data_len = 0; 2341 extra_data_after_insn = false; 2342 2343 input_line_pointer = str = start_of_operands; 2344 2345 for (opindex_ptr = opcode->operands; *opindex_ptr != 0; opindex_ptr++) 2346 { 2347 const struct v850_operand *operand; 2348 char *hold; 2349 expressionS ex; 2350 bfd_reloc_code_real_type reloc; 2351 2352 if (next_opindex == 0) 2353 operand = &v850_operands[*opindex_ptr]; 2354 else 2355 { 2356 operand = &v850_operands[next_opindex]; 2357 next_opindex = 0; 2358 } 2359 2360 errmsg = NULL; 2361 2362 while (is_whitespace (*str)) 2363 ++str; 2364 2365 if (operand->flags & V850_OPERAND_BANG 2366 && *str == '!') 2367 ++str; 2368 else if (operand->flags & V850_OPERAND_PERCENT 2369 && *str == '%') 2370 ++str; 2371 2372 if (*str == ',' || *str == '[' || *str == ']') 2373 ++str; 2374 2375 while (is_whitespace (*str)) 2376 ++str; 2377 2378 if ( (strcmp (opcode->name, "pushsp") == 0 2379 || strcmp (opcode->name, "popsp") == 0 2380 || strcmp (opcode->name, "dbpush") == 0) 2381 && (*str == '-')) 2382 ++str; 2383 2384 if (operand->flags & V850_OPERAND_RELAX) 2385 relaxable = 1; 2386 2387 /* Gather the operand. */ 2388 hold = input_line_pointer; 2389 input_line_pointer = str; 2390 2391 /* lo(), hi(), hi0(), etc... */ 2392 if ((reloc = v850_reloc_prefix (operand, &errmsg)) != BFD_RELOC_NONE) 2393 { 2394 /* This is a fake reloc, used to indicate an error condition. */ 2395 if (reloc == BFD_RELOC_64) 2396 { 2397 /* match = 1; */ 2398 goto error; 2399 } 2400 2401 expression (&ex); 2402 2403 if (ex.X_op == O_constant) 2404 { 2405 switch (reloc) 2406 { 2407 case BFD_RELOC_V850_ZDA_16_16_OFFSET: 2408 case BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET: 2409 case BFD_RELOC_V850_ZDA_15_16_OFFSET: 2410 /* To cope with "not1 7, zdaoff(0xfffff006)[r0]" 2411 and the like. */ 2412 /* Fall through. */ 2413 2414 case BFD_RELOC_LO16: 2415 case BFD_RELOC_V850_LO16_S1: 2416 case BFD_RELOC_V850_LO16_SPLIT_OFFSET: 2417 { 2418 /* Truncate, then sign extend the value. */ 2419 ex.X_add_number = SEXT16 (ex.X_add_number); 2420 break; 2421 } 2422 2423 case BFD_RELOC_HI16: 2424 { 2425 /* Truncate, then sign extend the value. */ 2426 ex.X_add_number = SEXT16 (ex.X_add_number >> 16); 2427 break; 2428 } 2429 2430 case BFD_RELOC_HI16_S: 2431 { 2432 /* Truncate, then sign extend the value. */ 2433 int temp = (ex.X_add_number >> 16) & 0xffff; 2434 2435 temp += (ex.X_add_number >> 15) & 1; 2436 2437 ex.X_add_number = SEXT16 (temp); 2438 break; 2439 } 2440 2441 case BFD_RELOC_V850_23: 2442 if ((operand->flags & V850E_IMMEDIATE23) == 0) 2443 { 2444 errmsg = _("immediate operand is too large"); 2445 goto error; 2446 } 2447 break; 2448 2449 case BFD_RELOC_32: 2450 case BFD_RELOC_V850_32_ABS: 2451 case BFD_RELOC_V850_32_PCREL: 2452 if ((operand->flags & V850E_IMMEDIATE32) == 0) 2453 { 2454 errmsg = _("immediate operand is too large"); 2455 goto error; 2456 } 2457 2458 break; 2459 2460 default: 2461 as_bad (_("AAARG -> unhandled constant reloc: %d"), reloc); 2462 break; 2463 } 2464 2465 if (operand->flags & V850E_IMMEDIATE32) 2466 { 2467 extra_data_after_insn = true; 2468 extra_data_len = 4; 2469 extra_data = 0; 2470 } 2471 else if (operand->flags & V850E_IMMEDIATE23) 2472 { 2473 if (reloc != BFD_RELOC_V850_23) 2474 { 2475 errmsg = _("immediate operand is too large"); 2476 goto error; 2477 } 2478 extra_data_after_insn = true; 2479 extra_data_len = 2; 2480 extra_data = 0; 2481 } 2482 else if ((operand->flags & V850E_IMMEDIATE16) 2483 || (operand->flags & V850E_IMMEDIATE16HI)) 2484 { 2485 if (operand->flags & V850E_IMMEDIATE16HI 2486 && reloc != BFD_RELOC_HI16 2487 && reloc != BFD_RELOC_HI16_S) 2488 { 2489 errmsg = _("immediate operand is too large"); 2490 goto error; 2491 } 2492 else if (operand->flags & V850E_IMMEDIATE16 2493 && reloc != BFD_RELOC_LO16) 2494 { 2495 errmsg = _("immediate operand is too large"); 2496 goto error; 2497 } 2498 2499 extra_data_after_insn = true; 2500 extra_data_len = 2; 2501 extra_data = 0; 2502 } 2503 2504 if (fc > MAX_INSN_FIXUPS) 2505 as_fatal (_("too many fixups")); 2506 2507 fixups[fc].exp = ex; 2508 fixups[fc].opindex = *opindex_ptr; 2509 fixups[fc].reloc = reloc; 2510 fc++; 2511 } 2512 else /* ex.X_op != O_constant. */ 2513 { 2514 if ((reloc == BFD_RELOC_32 2515 || reloc == BFD_RELOC_V850_32_ABS 2516 || reloc == BFD_RELOC_V850_32_PCREL) 2517 && operand->bits < 32) 2518 { 2519 errmsg = _("immediate operand is too large"); 2520 goto error; 2521 } 2522 else if (reloc == BFD_RELOC_V850_23 2523 && (operand->flags & V850E_IMMEDIATE23) == 0) 2524 { 2525 errmsg = _("immediate operand is too large"); 2526 goto error; 2527 } 2528 else if ((reloc == BFD_RELOC_HI16 2529 || reloc == BFD_RELOC_HI16_S) 2530 && operand->bits < 16) 2531 { 2532 errmsg = _("immediate operand is too large"); 2533 goto error; 2534 } 2535 2536 if (operand->flags & V850E_IMMEDIATE32) 2537 { 2538 extra_data_after_insn = true; 2539 extra_data_len = 4; 2540 extra_data = 0; 2541 } 2542 else if (operand->flags & V850E_IMMEDIATE23) 2543 { 2544 if (reloc != BFD_RELOC_V850_23) 2545 { 2546 errmsg = _("immediate operand is too large"); 2547 goto error; 2548 } 2549 extra_data_after_insn = true; 2550 extra_data_len = 2; 2551 extra_data = 0; 2552 } 2553 else if ((operand->flags & V850E_IMMEDIATE16) 2554 || (operand->flags & V850E_IMMEDIATE16HI)) 2555 { 2556 if (operand->flags & V850E_IMMEDIATE16HI 2557 && reloc != BFD_RELOC_HI16 2558 && reloc != BFD_RELOC_HI16_S) 2559 { 2560 errmsg = _("immediate operand is too large"); 2561 goto error; 2562 } 2563 else if (operand->flags & V850E_IMMEDIATE16 2564 && reloc != BFD_RELOC_LO16) 2565 { 2566 errmsg = _("immediate operand is too large"); 2567 goto error; 2568 } 2569 2570 extra_data_after_insn = true; 2571 extra_data_len = 2; 2572 extra_data = 0; 2573 } 2574 2575 if (fc > MAX_INSN_FIXUPS) 2576 as_fatal (_("too many fixups")); 2577 2578 fixups[fc].exp = ex; 2579 fixups[fc].opindex = *opindex_ptr; 2580 fixups[fc].reloc = reloc; 2581 fc++; 2582 } 2583 } 2584 else if (operand->flags & V850E_IMMEDIATE16 2585 || operand->flags & V850E_IMMEDIATE16HI) 2586 { 2587 expression (&ex); 2588 2589 switch (ex.X_op) 2590 { 2591 case O_constant: 2592 if (operand->flags & V850E_IMMEDIATE16HI) 2593 { 2594 if (ex.X_add_number & 0xffff) 2595 { 2596 errmsg = _("constant too big to fit into instruction"); 2597 goto error; 2598 } 2599 2600 ex.X_add_number >>= 16; 2601 } 2602 if (operand->flags & V850E_IMMEDIATE16) 2603 { 2604 if ((ex.X_add_number & 0xffff8000) 2605 && ((ex.X_add_number & 0xffff8000) != 0xffff8000)) 2606 { 2607 errmsg = _("constant too big to fit into instruction"); 2608 goto error; 2609 } 2610 } 2611 break; 2612 2613 case O_illegal: 2614 errmsg = _("illegal operand"); 2615 goto error; 2616 2617 case O_absent: 2618 errmsg = _("missing operand"); 2619 goto error; 2620 2621 default: 2622 if (fc >= MAX_INSN_FIXUPS) 2623 as_fatal (_("too many fixups")); 2624 2625 fixups[fc].exp = ex; 2626 fixups[fc].opindex = *opindex_ptr; 2627 fixups[fc].reloc = operand->default_reloc; 2628 ++fc; 2629 2630 ex.X_add_number = 0; 2631 break; 2632 } 2633 2634 extra_data_after_insn = true; 2635 extra_data_len = 2; 2636 extra_data = ex.X_add_number; 2637 } 2638 else if (operand->flags & V850E_IMMEDIATE23) 2639 { 2640 expression (&ex); 2641 2642 switch (ex.X_op) 2643 { 2644 case O_constant: 2645 break; 2646 2647 case O_illegal: 2648 errmsg = _("illegal operand"); 2649 goto error; 2650 2651 case O_absent: 2652 errmsg = _("missing operand"); 2653 goto error; 2654 2655 default: 2656 break; 2657 } 2658 2659 if (fc >= MAX_INSN_FIXUPS) 2660 as_fatal (_("too many fixups")); 2661 2662 fixups[fc].exp = ex; 2663 fixups[fc].opindex = *opindex_ptr; 2664 fixups[fc].reloc = operand->default_reloc; 2665 ++fc; 2666 2667 extra_data_after_insn = true; 2668 extra_data_len = 2; 2669 extra_data = 0; 2670 } 2671 else if (operand->flags & V850E_IMMEDIATE32) 2672 { 2673 expression (&ex); 2674 2675 switch (ex.X_op) 2676 { 2677 case O_constant: 2678 if ((operand->default_reloc == BFD_RELOC_V850_32_ABS 2679 || operand->default_reloc == BFD_RELOC_V850_32_PCREL) 2680 && (ex.X_add_number & 1)) 2681 { 2682 errmsg = _("odd number cannot be used here"); 2683 goto error; 2684 } 2685 break; 2686 2687 case O_illegal: 2688 errmsg = _("illegal operand"); 2689 goto error; 2690 2691 case O_absent: 2692 errmsg = _("missing operand"); 2693 goto error; 2694 2695 default: 2696 if (fc >= MAX_INSN_FIXUPS) 2697 as_fatal (_("too many fixups")); 2698 2699 fixups[fc].exp = ex; 2700 fixups[fc].opindex = *opindex_ptr; 2701 fixups[fc].reloc = operand->default_reloc; 2702 ++fc; 2703 2704 ex.X_add_number = 0; 2705 break; 2706 } 2707 2708 extra_data_after_insn = true; 2709 extra_data_len = 4; 2710 extra_data = ex.X_add_number; 2711 } 2712 else if (operand->flags & V850E_OPERAND_REG_LIST) 2713 { 2714 errmsg = parse_register_list (&insn, operand); 2715 2716 if (errmsg) 2717 goto error; 2718 } 2719 else 2720 { 2721 errmsg = NULL; 2722 2723 if ((operand->flags & V850_OPERAND_REG) != 0) 2724 { 2725 if (!register_name (&ex)) 2726 { 2727 errmsg = _("invalid register name"); 2728 } 2729 2730 if ((operand->flags & V850_NOT_R0) 2731 && ex.X_add_number == 0) 2732 { 2733 errmsg = _("register r0 cannot be used here"); 2734 } 2735 2736 if (operand->flags & V850_REG_EVEN) 2737 { 2738 if (ex.X_add_number % 2) 2739 errmsg = _("odd register cannot be used here"); 2740 ex.X_add_number = ex.X_add_number / 2; 2741 } 2742 2743 } 2744 else if ((operand->flags & V850_OPERAND_SRG) != 0) 2745 { 2746 if (!system_register_name (&ex, true)) 2747 { 2748 errmsg = _("invalid system register name"); 2749 } 2750 } 2751 else if ((operand->flags & V850_OPERAND_EP) != 0) 2752 { 2753 char *start = input_line_pointer; 2754 char *name; 2755 char c = get_symbol_name (&name); 2756 2757 if (strcmp (name, "ep") != 0 && strcmp (name, "r30") != 0) 2758 { 2759 /* Put things back the way we found them. */ 2760 (void) restore_line_pointer (c); 2761 input_line_pointer = start; 2762 errmsg = _("expected EP register"); 2763 goto error; 2764 } 2765 2766 (void) restore_line_pointer (c); 2767 str = input_line_pointer; 2768 input_line_pointer = hold; 2769 2770 while (is_whitespace (*str) || *str == ',' 2771 || *str == '[' || *str == ']') 2772 ++str; 2773 continue; 2774 } 2775 else if ((operand->flags & V850_OPERAND_CC) != 0) 2776 { 2777 if (!cc_name (&ex, true)) 2778 { 2779 errmsg = _("invalid condition code name"); 2780 } 2781 2782 if ((operand->flags & V850_NOT_SA) 2783 && ex.X_add_number == COND_SA_NUM) 2784 { 2785 errmsg = _("condition sa cannot be used here"); 2786 } 2787 } 2788 else if ((operand->flags & V850_OPERAND_FLOAT_CC) != 0) 2789 { 2790 if (!float_cc_name (&ex, true)) 2791 { 2792 errmsg = _("invalid condition code name"); 2793 } 2794 } 2795 else if ((operand->flags & V850_OPERAND_CACHEOP) != 0) 2796 { 2797 if (!cacheop_name (&ex, true)) 2798 errmsg = _("invalid cache operation name"); 2799 } 2800 else if ((operand->flags & V850_OPERAND_PREFOP) != 0) 2801 { 2802 if (!prefop_name (&ex, true)) 2803 errmsg = _("invalid pref operation name"); 2804 } 2805 else if ((operand->flags & V850_OPERAND_VREG) != 0) 2806 { 2807 if (!vector_register_name (&ex)) 2808 errmsg = _("invalid vector register name"); 2809 } 2810 else if ((register_name (&ex) 2811 && (operand->flags & V850_OPERAND_REG) == 0)) 2812 { 2813 char *name; 2814 char c; 2815 int exists = 0; 2816 2817 /* It is possible that an alias has been defined that 2818 matches a register name. For example the code may 2819 include a ".set ZERO, 0" directive, which matches 2820 the register name "zero". Attempt to reparse the 2821 field as an expression, and only complain if we 2822 cannot generate a constant. */ 2823 2824 input_line_pointer = str; 2825 2826 c = get_symbol_name (&name); 2827 2828 if (symbol_find (name) != NULL) 2829 exists = 1; 2830 2831 (void) restore_line_pointer (c); 2832 input_line_pointer = str; 2833 2834 expression (&ex); 2835 2836 if (ex.X_op != O_constant) 2837 { 2838 /* If this register is actually occurring too early on 2839 the parsing of the instruction, (because another 2840 field is missing) then report this. */ 2841 if (opindex_ptr[1] != 0 2842 && ((v850_operands[opindex_ptr[1]].flags 2843 & V850_OPERAND_REG) 2844 ||(v850_operands[opindex_ptr[1]].flags 2845 & V850_OPERAND_VREG))) 2846 errmsg = _("syntax error: value is missing before the register name"); 2847 else 2848 errmsg = _("syntax error: register not expected"); 2849 2850 /* If we created a symbol in the process of this 2851 test then delete it now, so that it will not 2852 be output with the real symbols... */ 2853 if (exists == 0 2854 && ex.X_op == O_symbol) 2855 symbol_remove (ex.X_add_symbol, 2856 &symbol_rootP, &symbol_lastP); 2857 } 2858 } 2859 else if (system_register_name (&ex, false) 2860 && (operand->flags & V850_OPERAND_SRG) == 0) 2861 { 2862 errmsg = _("syntax error: system register not expected"); 2863 } 2864 else if (cc_name (&ex, false) 2865 && (operand->flags & V850_OPERAND_CC) == 0) 2866 { 2867 errmsg = _("syntax error: condition code not expected"); 2868 } 2869 else if (float_cc_name (&ex, false) 2870 && (operand->flags & V850_OPERAND_FLOAT_CC) == 0) 2871 { 2872 errmsg = _("syntax error: condition code not expected"); 2873 } 2874 else if (vector_register_name (&ex) 2875 && (operand->flags & V850_OPERAND_VREG) == 0) 2876 { 2877 errmsg = _("syntax error: vector register not expected"); 2878 } 2879 else 2880 { 2881 expression (&ex); 2882 resolve_register (&ex); 2883 2884 if ((operand->flags & V850_NOT_IMM0) 2885 && ex.X_op == O_constant 2886 && ex.X_add_number == 0) 2887 { 2888 errmsg = _("immediate 0 cannot be used here"); 2889 } 2890 2891 /* Special case: 2892 If we are assembling a MOV/JARL/JR instruction and the immediate 2893 value does not fit into the bits available then create a 2894 fake error so that the next MOV/JARL/JR instruction will be 2895 selected. This one has a 32 bit immediate field. */ 2896 2897 if ((strcmp (opcode->name, "mov") == 0 2898 || strcmp (opcode->name, "jarl") == 0 2899 || strcmp (opcode->name, "jr") == 0) 2900 && ex.X_op == O_constant 2901 && (ex.X_add_number < (-(1 << (operand->bits - 1))) 2902 || ex.X_add_number > ((1 << (operand->bits - 1)) - 1))) 2903 { 2904 errmsg = _("immediate operand is too large"); 2905 } 2906 2907 if ((strcmp (opcode->name, "jarl") == 0 2908 || strcmp (opcode->name, "jr") == 0) 2909 && ex.X_op != O_constant 2910 && operand->bits != default_disp_size) 2911 { 2912 errmsg = _("immediate operand is not match"); 2913 } 2914 2915 /* Special case2 : 2916 If we are assembling a ld/st instruction and the immediate 2917 value does not fit into the bits available then create a 2918 fake error so that the next ld/st instruction will be 2919 selected. */ 2920 if ( ( (startswith (opcode->name, "st.")) 2921 || (startswith (opcode->name, "ld."))) 2922 && ex.X_op == O_constant 2923 && (ex.X_add_number < (-(1 << (operand->bits - 1))) 2924 || ex.X_add_number > ((1 << (operand->bits - 1)) - 1))) 2925 errmsg = _("displacement is too large"); 2926 } 2927 2928 if (errmsg) 2929 goto error; 2930 2931 switch (ex.X_op) 2932 { 2933 case O_illegal: 2934 errmsg = _("illegal operand"); 2935 goto error; 2936 case O_absent: 2937 errmsg = _("missing operand"); 2938 goto error; 2939 case O_register: 2940 if ((operand->flags 2941 & (V850_OPERAND_REG | V850_OPERAND_SRG | V850_OPERAND_VREG)) == 0) 2942 { 2943 errmsg = _("invalid operand"); 2944 goto error; 2945 } 2946 2947 insn = v850_insert_operand (insn, operand, 2948 ex.X_add_number, 2949 &warningmsg); 2950 2951 break; 2952 2953 case O_constant: 2954 insn = v850_insert_operand (insn, operand, ex.X_add_number, 2955 &warningmsg); 2956 break; 2957 2958 default: 2959 /* We need to generate a fixup for this expression. */ 2960 if (fc >= MAX_INSN_FIXUPS) 2961 as_fatal (_("too many fixups")); 2962 2963 fixups[fc].exp = ex; 2964 fixups[fc].opindex = *opindex_ptr; 2965 fixups[fc].reloc = BFD_RELOC_NONE; 2966 ++fc; 2967 break; 2968 } 2969 } 2970 2971 str = input_line_pointer; 2972 input_line_pointer = hold; 2973 2974 while (is_whitespace (*str) || *str == ',' || *str == '[' || *str == ']' 2975 || *str == ')') 2976 ++str; 2977 } 2978 2979 while (is_whitespace (*str)) 2980 ++str; 2981 2982 if (*str == '\0') 2983 match = 1; 2984 2985 error: 2986 if (match == 0) 2987 { 2988 if ((opindex_ptr - opcode->operands) >= most_match_count) 2989 { 2990 most_match_count = opindex_ptr - opcode->operands; 2991 if (errmsg != NULL) 2992 strncpy (most_match_errmsg, errmsg, sizeof (most_match_errmsg)-1); 2993 } 2994 2995 next_opcode = opcode + 1; 2996 if (next_opcode->name != NULL 2997 && strcmp (next_opcode->name, opcode->name) == 0) 2998 { 2999 opcode = next_opcode; 3000 3001 /* Skip versions that are not supported by the target 3002 processor. */ 3003 if ((opcode->processors & processor_mask) == 0) 3004 goto error; 3005 3006 continue; 3007 } 3008 3009 if (most_match_errmsg[0] == 0) 3010 /* xgettext:c-format. */ 3011 as_bad (_("junk at end of line: `%s'"), str); 3012 else 3013 as_bad ("%s: %s", copy_of_instruction, most_match_errmsg); 3014 3015 if (*input_line_pointer == ']') 3016 ++input_line_pointer; 3017 3018 ignore_rest_of_line (); 3019 input_line_pointer = saved_input_line_pointer; 3020 return; 3021 } 3022 3023 if (warningmsg != NULL) 3024 as_warn ("%s", warningmsg); 3025 break; 3026 } 3027 3028 input_line_pointer = str; 3029 3030 /* Tie dwarf2 debug info to the address at the start of the insn. 3031 We can't do this after the insn has been output as the current 3032 frag may have been closed off. eg. by frag_var. */ 3033 dwarf2_emit_insn (0); 3034 3035 /* Write out the instruction. */ 3036 if (relaxable && fc > 0) 3037 { 3038 insn_size = 2; 3039 fc = 0; 3040 3041 if (strcmp (opcode->name, "loop") == 0) 3042 { 3043 if (((processor_mask & PROCESSOR_V850E3V5_UP) == 0) || default_disp_size == 22) 3044 { 3045 insn_size = 4; 3046 f = frag_var (rs_machine_dependent, 6, 2, SUBYPTE_LOOP_16_22, 3047 fixups[0].exp.X_add_symbol, 3048 fixups[0].exp.X_add_number, 3049 (char *) (uintptr_t) fixups[0].opindex); 3050 md_number_to_chars (f, insn, insn_size); 3051 md_number_to_chars (f+4, 0, 4); 3052 } 3053 else 3054 { 3055 as_bad (_("loop: 32-bit displacement not supported")); 3056 } 3057 } 3058 else if (strcmp (opcode->name, "br") == 0 3059 || strcmp (opcode->name, "jbr") == 0) 3060 { 3061 if ((processor_mask & PROCESSOR_V850E2_UP) == 0 || default_disp_size == 22) 3062 { 3063 f = frag_var (rs_machine_dependent, 4, 2, SUBYPTE_UNCOND_9_22, 3064 fixups[0].exp.X_add_symbol, 3065 fixups[0].exp.X_add_number, 3066 (char *) (uintptr_t) fixups[0].opindex); 3067 md_number_to_chars (f, insn, insn_size); 3068 md_number_to_chars (f + 2, 0, 2); 3069 } 3070 else 3071 { 3072 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_UNCOND_9_22_32, 3073 fixups[0].exp.X_add_symbol, 3074 fixups[0].exp.X_add_number, 3075 (char *) (uintptr_t) fixups[0].opindex); 3076 md_number_to_chars (f, insn, insn_size); 3077 md_number_to_chars (f + 2, 0, 4); 3078 } 3079 } 3080 else /* b<cond>, j<cond>. */ 3081 { 3082 if (default_disp_size == 22 3083 || (processor_mask & PROCESSOR_V850E2_UP) == 0) 3084 { 3085 if (processor_mask & PROCESSOR_V850E2V3_UP && !no_bcond17) 3086 { 3087 if (strcmp (opcode->name, "bsa") == 0) 3088 { 3089 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_SA_9_17_22, 3090 fixups[0].exp.X_add_symbol, 3091 fixups[0].exp.X_add_number, 3092 (char *) (uintptr_t) fixups[0].opindex); 3093 md_number_to_chars (f, insn, insn_size); 3094 md_number_to_chars (f + 2, 0, 6); 3095 } 3096 else 3097 { 3098 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_COND_9_17_22, 3099 fixups[0].exp.X_add_symbol, 3100 fixups[0].exp.X_add_number, 3101 (char *) (uintptr_t) fixups[0].opindex); 3102 md_number_to_chars (f, insn, insn_size); 3103 md_number_to_chars (f + 2, 0, 4); 3104 } 3105 } 3106 else 3107 { 3108 if (strcmp (opcode->name, "bsa") == 0) 3109 { 3110 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_SA_9_22, 3111 fixups[0].exp.X_add_symbol, 3112 fixups[0].exp.X_add_number, 3113 (char *) (uintptr_t) fixups[0].opindex); 3114 md_number_to_chars (f, insn, insn_size); 3115 md_number_to_chars (f + 2, 0, 6); 3116 } 3117 else 3118 { 3119 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_COND_9_22, 3120 fixups[0].exp.X_add_symbol, 3121 fixups[0].exp.X_add_number, 3122 (char *) (uintptr_t) fixups[0].opindex); 3123 md_number_to_chars (f, insn, insn_size); 3124 md_number_to_chars (f + 2, 0, 4); 3125 } 3126 } 3127 } 3128 else 3129 { 3130 if (processor_mask & PROCESSOR_V850E2V3_UP && !no_bcond17) 3131 { 3132 if (strcmp (opcode->name, "bsa") == 0) 3133 { 3134 f = frag_var (rs_machine_dependent, 10, 8, SUBYPTE_SA_9_17_22_32, 3135 fixups[0].exp.X_add_symbol, 3136 fixups[0].exp.X_add_number, 3137 (char *) (uintptr_t) fixups[0].opindex); 3138 md_number_to_chars (f, insn, insn_size); 3139 md_number_to_chars (f + 2, 0, 8); 3140 } 3141 else 3142 { 3143 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_COND_9_17_22_32, 3144 fixups[0].exp.X_add_symbol, 3145 fixups[0].exp.X_add_number, 3146 (char *) (uintptr_t) fixups[0].opindex); 3147 md_number_to_chars (f, insn, insn_size); 3148 md_number_to_chars (f + 2, 0, 6); 3149 } 3150 } 3151 else 3152 { 3153 if (strcmp (opcode->name, "bsa") == 0) 3154 { 3155 f = frag_var (rs_machine_dependent, 10, 8, SUBYPTE_SA_9_22_32, 3156 fixups[0].exp.X_add_symbol, 3157 fixups[0].exp.X_add_number, 3158 (char *) (uintptr_t) fixups[0].opindex); 3159 md_number_to_chars (f, insn, insn_size); 3160 md_number_to_chars (f + 2, 0, 8); 3161 } 3162 else 3163 { 3164 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_COND_9_22_32, 3165 fixups[0].exp.X_add_symbol, 3166 fixups[0].exp.X_add_number, 3167 (char *) (uintptr_t) fixups[0].opindex); 3168 md_number_to_chars (f, insn, insn_size); 3169 md_number_to_chars (f + 2, 0, 6); 3170 } 3171 } 3172 } 3173 } 3174 } 3175 else 3176 { 3177 /* Four byte insns have an opcode with the two high bits on. */ 3178 if ((insn & 0x0600) == 0x0600) 3179 insn_size = 4; 3180 else 3181 insn_size = 2; 3182 3183 /* Special case: 32 bit MOV. */ 3184 if ((insn & 0xffe0) == 0x0620) 3185 insn_size = 2; 3186 3187 /* Special case: 32 bit JARL,JMP,JR. */ 3188 if ((insn & 0x1ffe0) == 0x2e0 /* JARL. */ 3189 || (insn & 0x1ffe0) == 0x6e0 /* JMP. */ 3190 || (insn & 0x1ffff) == 0x2e0) /* JR. */ 3191 insn_size = 2; 3192 3193 if (obstack_room (& frchain_now->frch_obstack) < (insn_size + extra_data_len)) 3194 { 3195 frag_wane (frag_now); 3196 frag_new (0); 3197 } 3198 3199 f = frag_more (insn_size); 3200 md_number_to_chars (f, insn, insn_size); 3201 3202 if (extra_data_after_insn) 3203 { 3204 f = frag_more (extra_data_len); 3205 md_number_to_chars (f, extra_data, extra_data_len); 3206 3207 extra_data_after_insn = false; 3208 } 3209 } 3210 3211 /* Create any fixups. At this point we do not use a 3212 bfd_reloc_code_real_type, but instead just use the 3213 BFD_RELOC_UNUSED plus the operand index. This lets us easily 3214 handle fixups for any operand type, although that is admittedly 3215 not a very exciting feature. We pick a BFD reloc type in 3216 md_apply_fix. */ 3217 for (i = 0; i < fc; i++) 3218 { 3219 const struct v850_operand *operand; 3220 bfd_reloc_code_real_type reloc; 3221 3222 operand = &v850_operands[fixups[i].opindex]; 3223 3224 reloc = fixups[i].reloc; 3225 3226 if (reloc != BFD_RELOC_NONE) 3227 { 3228 reloc_howto_type *reloc_howto = 3229 bfd_reloc_type_lookup (stdoutput, reloc); 3230 int size; 3231 int address; 3232 fixS *fixP; 3233 3234 if (!reloc_howto) 3235 abort (); 3236 3237 size = bfd_get_reloc_size (reloc_howto); 3238 3239 /* XXX This will abort on an R_V850_8 reloc - 3240 is this reloc actually used? */ 3241 if (size != 2 && size != 4) 3242 abort (); 3243 3244 if (extra_data_len == 0) 3245 { 3246 address = (f - frag_now->fr_literal) + insn_size - size; 3247 } 3248 else 3249 { 3250 address = (f - frag_now->fr_literal) + extra_data_len - size; 3251 } 3252 3253 if ((operand->flags & V850E_IMMEDIATE32) && (operand->flags & V850_PCREL)) 3254 { 3255 fixups[i].exp.X_add_number += 2; 3256 } 3257 else if (operand->default_reloc == BFD_RELOC_V850_16_PCREL) 3258 { 3259 fixups[i].exp.X_add_number += 2; 3260 address += 2; 3261 } 3262 3263 /* fprintf (stderr, "0x%x %d %ld\n", address, size, fixups[i].exp.X_add_number); */ 3264 fixP = fix_new_exp (frag_now, address, size, 3265 &fixups[i].exp, 3266 reloc_howto->pc_relative, 3267 reloc); 3268 3269 fixP->tc_fix_data = (void *) operand; 3270 3271 switch (reloc) 3272 { 3273 case BFD_RELOC_LO16: 3274 case BFD_RELOC_V850_LO16_S1: 3275 case BFD_RELOC_V850_LO16_SPLIT_OFFSET: 3276 case BFD_RELOC_HI16: 3277 case BFD_RELOC_HI16_S: 3278 fixP->fx_no_overflow = 1; 3279 break; 3280 default: 3281 break; 3282 } 3283 } 3284 else 3285 { 3286 gas_assert (f != NULL); 3287 fix_new_exp (frag_now, 3288 f - frag_now->fr_literal, 4, 3289 & fixups[i].exp, 3290 (operand->flags & V850_PCREL) != 0, 3291 fixups[i].opindex + BFD_RELOC_UNUSED); 3292 } 3293 } 3294 3295 input_line_pointer = saved_input_line_pointer; 3296 } 3297 3298 /* If while processing a fixup, a reloc really needs to be created 3299 then it is done here. */ 3300 3301 arelent * 3302 tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp) 3303 { 3304 arelent *reloc; 3305 3306 reloc = notes_alloc (sizeof (arelent)); 3307 reloc->sym_ptr_ptr = notes_alloc (sizeof (asymbol *)); 3308 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 3309 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 3310 3311 if ( fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY 3312 || fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT 3313 || fixp->fx_r_type == BFD_RELOC_V850_LONGCALL 3314 || fixp->fx_r_type == BFD_RELOC_V850_LONGJUMP 3315 || fixp->fx_r_type == BFD_RELOC_V850_ALIGN) 3316 reloc->addend = fixp->fx_offset; 3317 else 3318 { 3319 #if 0 3320 if (fixp->fx_r_type == BFD_RELOC_32 3321 && fixp->fx_pcrel) 3322 fixp->fx_r_type = BFD_RELOC_32_PCREL; 3323 #endif 3324 3325 reloc->addend = fixp->fx_addnumber; 3326 } 3327 3328 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); 3329 3330 if (reloc->howto == NULL) 3331 { 3332 as_bad_where (fixp->fx_file, fixp->fx_line, 3333 /* xgettext:c-format */ 3334 _("reloc %d not supported by object file format"), 3335 (int) fixp->fx_r_type); 3336 return NULL; 3337 } 3338 3339 return reloc; 3340 } 3341 3342 void 3343 v850_handle_align (fragS * frag) 3344 { 3345 if (v850_relax 3346 && frag->fr_type == rs_align 3347 && frag->fr_address + frag->fr_fix > 0 3348 && frag->fr_offset > 1 3349 && now_seg != bss_section 3350 && now_seg != v850_seg_table[SBSS_SECTION].s 3351 && now_seg != v850_seg_table[TBSS_SECTION].s 3352 && now_seg != v850_seg_table[ZBSS_SECTION].s) 3353 fix_new (frag, frag->fr_fix, 2, & abs_symbol, frag->fr_offset, 0, 3354 BFD_RELOC_V850_ALIGN); 3355 } 3356 3357 /* Return current size of variable part of frag. */ 3358 3359 int 3360 md_estimate_size_before_relax (fragS *fragp, asection *seg ATTRIBUTE_UNUSED) 3361 { 3362 if (fragp->fr_subtype >= sizeof (md_relax_table) / sizeof (md_relax_table[0])) 3363 abort (); 3364 3365 return md_relax_table[fragp->fr_subtype].rlx_length; 3366 } 3367 3368 long 3369 v850_pcrel_from_section (fixS *fixp, segT section) 3370 { 3371 /* If the symbol is undefined, or in a section other than our own, 3372 or it is weak (in which case it may well be in another section, 3373 then let the linker figure it out. */ 3374 if (fixp->fx_addsy != NULL 3375 && (! S_IS_DEFINED (fixp->fx_addsy) 3376 || S_IS_WEAK (fixp->fx_addsy) 3377 || (S_GET_SEGMENT (fixp->fx_addsy) != section))) 3378 return 0; 3379 3380 return fixp->fx_frag->fr_address + fixp->fx_where; 3381 } 3382 3383 void 3384 md_apply_fix (fixS *fixP, valueT *valueP, segT seg ATTRIBUTE_UNUSED) 3385 { 3386 valueT value = * valueP; 3387 char *where; 3388 3389 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 3390 || fixP->fx_r_type == BFD_RELOC_V850_LONGCALL 3391 || fixP->fx_r_type == BFD_RELOC_V850_LONGJUMP 3392 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 3393 { 3394 fixP->fx_done = 0; 3395 return; 3396 } 3397 3398 if (fixP->fx_addsy == NULL) 3399 fixP->fx_addnumber = value, 3400 fixP->fx_done = 1; 3401 3402 else if (fixP->fx_pcrel) 3403 fixP->fx_addnumber = fixP->fx_offset; 3404 3405 else 3406 { 3407 value = fixP->fx_offset; 3408 if (fixP->fx_subsy != NULL) 3409 { 3410 if (S_GET_SEGMENT (fixP->fx_subsy) == absolute_section) 3411 value -= S_GET_VALUE (fixP->fx_subsy); 3412 else 3413 /* We don't actually support subtracting a symbol. */ 3414 as_bad_subtract (fixP); 3415 } 3416 fixP->fx_addnumber = value; 3417 } 3418 3419 if (fixP->fx_r_type >= BFD_RELOC_UNUSED) 3420 { 3421 int opindex; 3422 const struct v850_operand *operand; 3423 unsigned long insn; 3424 const char *errmsg = NULL; 3425 3426 opindex = fixP->fx_r_type - BFD_RELOC_UNUSED; 3427 operand = &v850_operands[opindex]; 3428 3429 /* Fetch the instruction, insert the fully resolved operand 3430 value, and stuff the instruction back again. 3431 3432 Note the instruction has been stored in little endian 3433 format! */ 3434 where = fixP->fx_frag->fr_literal + fixP->fx_where; 3435 3436 if (fixP->fx_size > 2) 3437 insn = bfd_getl32 (where); 3438 else 3439 insn = bfd_getl16 (where); 3440 3441 /* When inserting loop offsets a backwards displacement 3442 is encoded as a positive value. */ 3443 if (operand->flags & V850_INVERSE_PCREL) 3444 value = - value; 3445 3446 insn = v850_insert_operand (insn, operand, (offsetT) value, 3447 &errmsg); 3448 if (errmsg) 3449 as_warn_where (fixP->fx_file, fixP->fx_line, "%s", errmsg); 3450 3451 if (fixP->fx_size > 2) 3452 bfd_putl32 (insn, where); 3453 else 3454 bfd_putl16 (insn, where); 3455 3456 if (fixP->fx_done) 3457 /* Nothing else to do here. */ 3458 return; 3459 3460 /* Determine a BFD reloc value based on the operand information. 3461 We are only prepared to turn a few of the operands into relocs. */ 3462 3463 if (operand->default_reloc == BFD_RELOC_NONE) 3464 { 3465 as_bad_where (fixP->fx_file, fixP->fx_line, 3466 _("unresolved expression that must be resolved")); 3467 fixP->fx_done = 1; 3468 return; 3469 } 3470 3471 { 3472 fixP->fx_r_type = operand->default_reloc; 3473 if (operand->default_reloc == BFD_RELOC_V850_16_PCREL) 3474 { 3475 fixP->fx_where += 2; 3476 fixP->fx_size = 2; 3477 fixP->fx_addnumber += 2; 3478 } 3479 } 3480 } 3481 else if (fixP->fx_done) 3482 { 3483 /* We still have to insert the value into memory! */ 3484 where = fixP->fx_frag->fr_literal + fixP->fx_where; 3485 3486 if (fixP->tc_fix_data != NULL 3487 && ((struct v850_operand *) fixP->tc_fix_data)->insert != NULL) 3488 { 3489 const char * message = NULL; 3490 struct v850_operand * operand = fixP->tc_fix_data; 3491 unsigned long insn; 3492 3493 /* The variable "where" currently points at the exact point inside 3494 the insn where we need to insert the value. But we need to 3495 extract the entire insn so we probably need to move "where" 3496 back a few bytes. */ 3497 3498 if (fixP->fx_size == 2) 3499 where -= 2; 3500 else if (fixP->fx_size == 1) 3501 where -= 3; 3502 3503 insn = bfd_getl32 (where); 3504 3505 /* Use the operand's insertion procedure, if present, in order to 3506 make sure that the value is correctly stored in the insn. */ 3507 insn = operand->insert (insn, (offsetT) value, & message); 3508 /* Ignore message even if it is set. */ 3509 3510 bfd_putl32 (insn, where); 3511 } 3512 else 3513 { 3514 switch (fixP->fx_r_type) 3515 { 3516 case BFD_RELOC_V850_32_ABS: 3517 case BFD_RELOC_V850_32_PCREL: 3518 bfd_putl32 (value & 0xfffffffe, where); 3519 break; 3520 3521 case BFD_RELOC_32: 3522 bfd_putl32 (value, where); 3523 break; 3524 3525 case BFD_RELOC_V850_23: 3526 bfd_putl32 (((value & 0x7f) << 4) | ((value & 0x7fff80) << (16-7)) 3527 | (bfd_getl32 (where) & ~((0x7f << 4) | (0xffff << 16))), 3528 where); 3529 break; 3530 3531 case BFD_RELOC_16: 3532 case BFD_RELOC_HI16: 3533 case BFD_RELOC_HI16_S: 3534 case BFD_RELOC_LO16: 3535 case BFD_RELOC_V850_ZDA_16_16_OFFSET: 3536 case BFD_RELOC_V850_SDA_16_16_OFFSET: 3537 case BFD_RELOC_V850_TDA_16_16_OFFSET: 3538 case BFD_RELOC_V850_CALLT_16_16_OFFSET: 3539 bfd_putl16 (value & 0xffff, where); 3540 break; 3541 3542 case BFD_RELOC_8: 3543 *where = value & 0xff; 3544 break; 3545 3546 case BFD_RELOC_V850_9_PCREL: 3547 bfd_putl16 (((value & 0x1f0) << 7) | ((value & 0x0e) << 3) 3548 | (bfd_getl16 (where) & ~((0x1f0 << 7) | (0x0e << 3))), where); 3549 break; 3550 3551 case BFD_RELOC_V850_17_PCREL: 3552 bfd_putl32 (((value & 0x10000) >> (16 - 4)) | ((value & 0xfffe) << 16) 3553 | (bfd_getl32 (where) & ~((0x10000 >> (16 - 4)) | (0xfffe << 16))), where); 3554 break; 3555 3556 case BFD_RELOC_V850_16_PCREL: 3557 bfd_putl16 ((-value & 0xfffe) | (bfd_getl16 (where + 2) & 0x0001), 3558 where + 2); 3559 break; 3560 3561 case BFD_RELOC_V850_22_PCREL: 3562 bfd_putl32 (((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16) 3563 | (bfd_getl32 (where) & ~((0xfffe << 16) | (0x3f0000 >> 16))), where); 3564 break; 3565 3566 case BFD_RELOC_V850_16_S1: 3567 case BFD_RELOC_V850_LO16_S1: 3568 case BFD_RELOC_V850_ZDA_15_16_OFFSET: 3569 case BFD_RELOC_V850_SDA_15_16_OFFSET: 3570 bfd_putl16 (value & 0xfffe, where); 3571 break; 3572 3573 case BFD_RELOC_V850_16_SPLIT_OFFSET: 3574 case BFD_RELOC_V850_LO16_SPLIT_OFFSET: 3575 case BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET: 3576 case BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET: 3577 bfd_putl32 (((value << 16) & 0xfffe0000) 3578 | ((value << 5) & 0x20) 3579 | (bfd_getl32 (where) & ~0xfffe0020), where); 3580 break; 3581 3582 case BFD_RELOC_V850_TDA_6_8_OFFSET: 3583 *where = (*where & ~0x7e) | ((value >> 1) & 0x7e); 3584 break; 3585 3586 case BFD_RELOC_V850_TDA_7_8_OFFSET: 3587 *where = (*where & ~0x7f) | ((value >> 1) & 0x7f); 3588 break; 3589 3590 case BFD_RELOC_V850_TDA_7_7_OFFSET: 3591 *where = (*where & ~0x7f) | (value & 0x7f); 3592 break; 3593 3594 case BFD_RELOC_V850_TDA_4_5_OFFSET: 3595 *where = (*where & ~0xf) | ((value >> 1) & 0xf); 3596 break; 3597 3598 case BFD_RELOC_V850_TDA_4_4_OFFSET: 3599 *where = (*where & ~0xf) | (value & 0xf); 3600 break; 3601 3602 case BFD_RELOC_V850_CALLT_6_7_OFFSET: 3603 *where = (*where & ~0x3f) | (value & 0x3f); 3604 break; 3605 3606 default: 3607 abort (); 3608 } 3609 } 3610 } 3611 } 3612 3613 /* Parse a cons expression. We have to handle hi(), lo(), etc 3614 on the v850. */ 3615 3616 bfd_reloc_code_real_type 3617 parse_cons_expression_v850 (expressionS *exp) 3618 { 3619 const char *errmsg; 3620 bfd_reloc_code_real_type r; 3621 3622 /* See if there's a reloc prefix like hi() we have to handle. */ 3623 r = v850_reloc_prefix (NULL, &errmsg); 3624 3625 /* Do normal expression parsing. */ 3626 expression (exp); 3627 return r; 3628 } 3629 3630 /* Create a fixup for a cons expression. If parse_cons_expression_v850 3631 found a reloc prefix, then we use that reloc, else we choose an 3632 appropriate one based on the size of the expression. */ 3633 3634 void 3635 cons_fix_new_v850 (fragS *frag, 3636 int where, 3637 int size, 3638 expressionS *exp, 3639 bfd_reloc_code_real_type r) 3640 { 3641 if (r == BFD_RELOC_NONE) 3642 { 3643 if (size == 4) 3644 r = BFD_RELOC_32; 3645 if (size == 2) 3646 r = BFD_RELOC_16; 3647 if (size == 1) 3648 r = BFD_RELOC_8; 3649 } 3650 3651 if (exp != NULL) 3652 fix_new_exp (frag, where, size, exp, 0, r); 3653 else 3654 fix_new (frag, where, size, NULL, 0, 0, r); 3655 } 3656 3657 bool 3658 v850_fix_adjustable (fixS *fixP) 3659 { 3660 if (fixP->fx_addsy == NULL) 3661 return 1; 3662 3663 /* Don't adjust function names. */ 3664 if (S_IS_FUNCTION (fixP->fx_addsy)) 3665 return 0; 3666 3667 /* We need the symbol name for the VTABLE entries. */ 3668 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 3669 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 3670 return 0; 3671 3672 return 1; 3673 } 3674 3675 int 3676 v850_force_relocation (struct fix *fixP) 3677 { 3678 if (fixP->fx_r_type == BFD_RELOC_V850_LONGCALL 3679 || fixP->fx_r_type == BFD_RELOC_V850_LONGJUMP) 3680 return 1; 3681 3682 if (v850_relax 3683 && (fixP->fx_pcrel 3684 || fixP->fx_r_type == BFD_RELOC_V850_ALIGN 3685 || fixP->fx_r_type == BFD_RELOC_V850_9_PCREL 3686 || fixP->fx_r_type == BFD_RELOC_V850_16_PCREL 3687 || fixP->fx_r_type == BFD_RELOC_V850_17_PCREL 3688 || fixP->fx_r_type == BFD_RELOC_V850_22_PCREL 3689 || fixP->fx_r_type == BFD_RELOC_V850_32_PCREL 3690 || fixP->fx_r_type >= BFD_RELOC_UNUSED)) 3691 return 1; 3692 3693 return generic_force_reloc (fixP); 3694 } 3695 3696 /* Create a v850 note section. */ 3697 void 3698 v850_md_finish (void) 3699 { 3700 segT note_sec; 3701 segT orig_seg = now_seg; 3702 subsegT orig_subseg = now_subseg; 3703 enum v850_notes id; 3704 3705 note_sec = subseg_new (V850_NOTE_SECNAME, 0); 3706 bfd_set_section_flags (note_sec, SEC_HAS_CONTENTS | SEC_READONLY | SEC_MERGE); 3707 bfd_set_section_alignment (note_sec, 2); 3708 3709 /* Provide default values for all of the notes. */ 3710 for (id = V850_NOTE_ALIGNMENT; id <= NUM_V850_NOTES; id++) 3711 { 3712 int val = 0; 3713 char * p; 3714 3715 /* Follow the standard note section layout: 3716 First write the length of the name string. */ 3717 p = frag_more (4); 3718 md_number_to_chars (p, 4, 4); 3719 3720 /* Next comes the length of the "descriptor", i.e., the actual data. */ 3721 p = frag_more (4); 3722 md_number_to_chars (p, 4, 4); 3723 3724 /* Write the note type. */ 3725 p = frag_more (4); 3726 md_number_to_chars (p, id, 4); 3727 3728 /* Write the name field. */ 3729 p = frag_more (4); 3730 memcpy (p, V850_NOTE_NAME, 4); 3731 3732 /* Finally, write the descriptor. */ 3733 p = frag_more (4); 3734 switch (id) 3735 { 3736 case V850_NOTE_ALIGNMENT: 3737 val = v850_data_8 ? EF_RH850_DATA_ALIGN8 : EF_RH850_DATA_ALIGN4; 3738 break; 3739 3740 case V850_NOTE_DATA_SIZE: 3741 /* GCC does not currently support an option 3742 for 32-bit doubles with the V850 backend. */ 3743 val = EF_RH850_DOUBLE64; 3744 break; 3745 3746 case V850_NOTE_FPU_INFO: 3747 if (! soft_float) 3748 switch (machine) 3749 { 3750 case bfd_mach_v850e3v5: val = EF_RH850_FPU30; break; 3751 case bfd_mach_v850e2v3: val = EF_RH850_FPU20; break; 3752 default: break; 3753 } 3754 break; 3755 3756 default: 3757 break; 3758 } 3759 md_number_to_chars (p, val, 4); 3760 } 3761 3762 /* Paranoia - we probably do not need this. */ 3763 subseg_set (orig_seg, orig_subseg); 3764 } 3765
Indexes created Thu May 07 00:24:58 UTC 2026