tc-v850.c revision 1.1.1.2
1 /* tc-v850.c -- Assembler code for the NEC V850 2 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 3 2006, 2007, 2009, 2010, 2011 Free Software Foundation, Inc. 4 5 This file is part of GAS, the GNU Assembler. 6 7 GAS is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GAS is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GAS; see the file COPYING. If not, write to 19 the Free Software Foundation, 51 Franklin Street - Fifth Floor, 20 Boston, MA 02110-1301, USA. */ 21 22 #include "as.h" 23 #include "safe-ctype.h" 24 #include "subsegs.h" 25 #include "opcode/v850.h" 26 #include "dwarf2dbg.h" 27 28 /* Sign-extend a 16-bit number. */ 29 #define SEXT16(x) ((((x) & 0xffff) ^ (~0x7fff)) + 0x8000) 30 31 /* Temporarily holds the reloc in a cons expression. */ 32 static bfd_reloc_code_real_type hold_cons_reloc = BFD_RELOC_UNUSED; 33 34 /* Set to TRUE if we want to be pedantic about signed overflows. */ 35 static bfd_boolean warn_signed_overflows = FALSE; 36 static bfd_boolean warn_unsigned_overflows = FALSE; 37 38 /* Indicates the target BFD machine number. */ 39 static int machine = -1; 40 41 /* Indicates the target processor(s) for the assemble. */ 42 static int processor_mask = 0; 43 44 /* Structure to hold information about predefined registers. */ 46 struct reg_name 47 { 48 const char *name; 49 int value; 50 unsigned int processors; 51 }; 52 53 /* Generic assembler global variables which must be defined by all 54 targets. */ 55 56 /* Characters which always start a comment. */ 57 const char comment_chars[] = "#"; 58 59 /* Characters which start a comment at the beginning of a line. */ 60 const char line_comment_chars[] = ";#"; 61 62 /* Characters which may be used to separate multiple commands on a 63 single line. */ 64 const char line_separator_chars[] = ";"; 65 66 /* Characters which are used to indicate an exponent in a floating 67 point number. */ 68 const char EXP_CHARS[] = "eE"; 69 70 /* Characters which mean that a number is a floating point constant, 71 as in 0d1.0. */ 72 const char FLT_CHARS[] = "dD"; 73 74 const relax_typeS md_relax_table[] = 76 { 77 /* Conditional branches.(V850/V850E, max 22bit) */ 78 #define SUBYPTE_COND_9_22 0 79 {0xfe, -0x100, 2, SUBYPTE_COND_9_22 + 1}, 80 {0x1ffffe + 2, -0x200000 + 2, 6, 0}, 81 /* Conditional branches.(V850/V850E, max 22bit) */ 82 #define SUBYPTE_SA_9_22 2 83 {0xfe, -0x100, 2, SUBYPTE_SA_9_22 + 1}, 84 {0x1ffffe + 4, -0x200000 + 4, 8, 0}, 85 /* Unconditional branches.(V850/V850E, max 22bit) */ 86 #define SUBYPTE_UNCOND_9_22 4 87 {0xfe, -0x100, 2, SUBYPTE_UNCOND_9_22 + 1}, 88 {0x1ffffe, -0x200000, 4, 0}, 89 /* Conditional branches.(V850E2, max 32bit) */ 90 #define SUBYPTE_COND_9_22_32 6 91 {0xfe, -0x100, 2, SUBYPTE_COND_9_22_32 + 1}, 92 {0x1fffff + 2, -0x200000 + 2, 6, SUBYPTE_COND_9_22_32 + 2}, 93 {0x7ffffffe, -0x80000000, 8, 0}, 94 /* Conditional branches.(V850E2, max 32bit) */ 95 #define SUBYPTE_SA_9_22_32 9 96 {0xfe, -0x100, 2, SUBYPTE_SA_9_22_32 + 1}, 97 {0x1ffffe + 4, -0x200000 + 4, 8, SUBYPTE_SA_9_22_32 + 2}, 98 {0x7ffffffe, -0x80000000, 10, 0}, 99 /* Unconditional branches.(V850E2, max 32bit) */ 100 #define SUBYPTE_UNCOND_9_22_32 12 101 {0xfe, -0x100, 2, SUBYPTE_UNCOND_9_22_32 + 1}, 102 {0x1ffffe, -0x200000, 4, SUBYPTE_UNCOND_9_22_32 + 2}, 103 {0x7ffffffe, -0x80000000, 6, 0}, 104 /* Conditional branches.(V850E2R max 22bit) */ 105 #define SUBYPTE_COND_9_17_22 15 106 {0xfe, -0x100, 2, SUBYPTE_COND_9_17_22 + 1}, 107 {0xfffe, -0x10000, 4, SUBYPTE_COND_9_17_22 + 2}, 108 {0x1ffffe + 2, -0x200000 + 2, 6, 0}, 109 /* Conditional branches.(V850E2R max 22bit) */ 110 #define SUBYPTE_SA_9_17_22 18 111 {0xfe, -0x100, 2, SUBYPTE_SA_9_17_22 + 1}, 112 {0xfffe, -0x10000, 4, SUBYPTE_SA_9_17_22 + 2}, 113 {0x1ffffe + 4, -0x200000 + 4, 8, 0}, 114 /* Conditional branches.(V850E2R max 32bit) */ 115 #define SUBYPTE_COND_9_17_22_32 21 116 {0xfe, -0x100, 2, SUBYPTE_COND_9_17_22_32 + 1}, 117 {0xfffe, -0x10000, 4, SUBYPTE_COND_9_17_22_32 + 2}, 118 {0x1ffffe + 2, -0x200000 + 2, 6, SUBYPTE_COND_9_17_22_32 + 3}, 119 {0x7ffffffe, -0x80000000, 8, 0}, 120 /* Conditional branches.(V850E2R max 32bit) */ 121 #define SUBYPTE_SA_9_17_22_32 25 122 {0xfe, -0x100, 2, SUBYPTE_SA_9_17_22_32 + 1}, 123 {0xfffe, -0x10000, 4, SUBYPTE_SA_9_17_22_32 + 2}, 124 {0x1ffffe + 4, -0x200000 + 4, 8, SUBYPTE_SA_9_17_22_32 + 3}, 125 {0x7ffffffe, -0x80000000, 10, 0}, 126 }; 127 128 static int v850_relax = 0; 129 130 /* Default branch disp size 22 or 32. */ 131 static int default_disp_size = 22; 132 133 /* Default no using bcond17. */ 134 static int no_bcond17 = 0; 135 136 /* Default no using ld/st 23bit offset. */ 137 static int no_stld23 = 0; 138 139 /* Fixups. */ 140 #define MAX_INSN_FIXUPS 5 141 142 struct v850_fixup 143 { 144 expressionS exp; 145 int opindex; 146 bfd_reloc_code_real_type reloc; 147 }; 148 149 struct v850_fixup fixups[MAX_INSN_FIXUPS]; 150 static int fc; 151 152 struct v850_seg_entry 153 { 154 segT s; 155 const char *name; 156 flagword flags; 157 }; 158 159 struct v850_seg_entry v850_seg_table[] = 160 { 161 { NULL, ".sdata", 162 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS 163 | SEC_SMALL_DATA }, 164 { NULL, ".tdata", 165 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS }, 166 { NULL, ".zdata", 167 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS }, 168 { NULL, ".sbss", 169 SEC_ALLOC | SEC_SMALL_DATA }, 170 { NULL, ".tbss", 171 SEC_ALLOC }, 172 { NULL, ".zbss", 173 SEC_ALLOC}, 174 { NULL, ".rosdata", 175 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_DATA 176 | SEC_HAS_CONTENTS | SEC_SMALL_DATA }, 177 { NULL, ".rozdata", 178 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_DATA 179 | SEC_HAS_CONTENTS }, 180 { NULL, ".scommon", 181 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS 182 | SEC_SMALL_DATA | SEC_IS_COMMON }, 183 { NULL, ".tcommon", 184 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS 185 | SEC_IS_COMMON }, 186 { NULL, ".zcommon", 187 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS 188 | SEC_IS_COMMON }, 189 { NULL, ".call_table_data", 190 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS }, 191 { NULL, ".call_table_text", 192 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_CODE 193 | SEC_HAS_CONTENTS}, 194 { NULL, ".bss", 195 SEC_ALLOC } 196 }; 197 198 #define SDATA_SECTION 0 199 #define TDATA_SECTION 1 200 #define ZDATA_SECTION 2 201 #define SBSS_SECTION 3 202 #define TBSS_SECTION 4 203 #define ZBSS_SECTION 5 204 #define ROSDATA_SECTION 6 205 #define ROZDATA_SECTION 7 206 #define SCOMMON_SECTION 8 207 #define TCOMMON_SECTION 9 208 #define ZCOMMON_SECTION 10 209 #define CALL_TABLE_DATA_SECTION 11 210 #define CALL_TABLE_TEXT_SECTION 12 211 #define BSS_SECTION 13 212 213 static void 214 do_v850_seg (int i, subsegT sub) 215 { 216 struct v850_seg_entry *seg = v850_seg_table + i; 217 218 obj_elf_section_change_hook (); 219 220 if (seg->s != NULL) 221 subseg_set (seg->s, sub); 222 else 223 { 224 seg->s = subseg_new (seg->name, sub); 225 bfd_set_section_flags (stdoutput, seg->s, seg->flags); 226 if ((seg->flags & SEC_LOAD) == 0) 227 seg_info (seg->s)->bss = 1; 228 } 229 } 230 231 static void 232 v850_seg (int i) 233 { 234 subsegT sub = get_absolute_expression (); 235 236 do_v850_seg (i, sub); 237 demand_empty_rest_of_line (); 238 } 239 240 static void 241 v850_offset (int ignore ATTRIBUTE_UNUSED) 242 { 243 char *pfrag; 244 int temp = get_absolute_expression (); 245 246 pfrag = frag_var (rs_org, 1, 1, (relax_substateT)0, (symbolS *)0, 247 (offsetT) temp, (char *) 0); 248 *pfrag = 0; 249 250 demand_empty_rest_of_line (); 251 } 252 253 /* Copied from obj_elf_common() in gas/config/obj-elf.c. */ 254 255 static void 256 v850_comm (int area) 257 { 258 char *name; 259 char c; 260 char *p; 261 int temp; 262 unsigned int size; 263 symbolS *symbolP; 264 int have_align; 265 266 name = input_line_pointer; 267 c = get_symbol_end (); 268 269 /* Just after name is now '\0'. */ 270 p = input_line_pointer; 271 *p = c; 272 273 SKIP_WHITESPACE (); 274 275 if (*input_line_pointer != ',') 276 { 277 as_bad (_("Expected comma after symbol-name")); 278 ignore_rest_of_line (); 279 return; 280 } 281 282 /* Skip ','. */ 283 input_line_pointer++; 284 285 if ((temp = get_absolute_expression ()) < 0) 286 { 287 /* xgettext:c-format */ 288 as_bad (_(".COMMon length (%d.) < 0! Ignored."), temp); 289 ignore_rest_of_line (); 290 return; 291 } 292 293 size = temp; 294 *p = 0; 295 symbolP = symbol_find_or_make (name); 296 *p = c; 297 298 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) 299 { 300 as_bad (_("Ignoring attempt to re-define symbol")); 301 ignore_rest_of_line (); 302 return; 303 } 304 305 if (S_GET_VALUE (symbolP) != 0) 306 { 307 if (S_GET_VALUE (symbolP) != size) 308 /* xgettext:c-format */ 309 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."), 310 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size); 311 } 312 313 know (symbol_get_frag (symbolP) == &zero_address_frag); 314 315 if (*input_line_pointer != ',') 316 have_align = 0; 317 else 318 { 319 have_align = 1; 320 input_line_pointer++; 321 SKIP_WHITESPACE (); 322 } 323 324 if (! have_align || *input_line_pointer != '"') 325 { 326 if (! have_align) 327 temp = 0; 328 else 329 { 330 temp = get_absolute_expression (); 331 332 if (temp < 0) 333 { 334 temp = 0; 335 as_warn (_("Common alignment negative; 0 assumed")); 336 } 337 } 338 339 if (symbol_get_obj (symbolP)->local) 340 { 341 segT old_sec; 342 int old_subsec; 343 char *pfrag; 344 int align; 345 flagword applicable; 346 347 old_sec = now_seg; 348 old_subsec = now_subseg; 349 350 applicable = bfd_applicable_section_flags (stdoutput); 351 352 applicable &= SEC_ALLOC; 353 354 switch (area) 355 { 356 case SCOMMON_SECTION: 357 do_v850_seg (SBSS_SECTION, 0); 358 break; 359 360 case ZCOMMON_SECTION: 361 do_v850_seg (ZBSS_SECTION, 0); 362 break; 363 364 case TCOMMON_SECTION: 365 do_v850_seg (TBSS_SECTION, 0); 366 break; 367 } 368 369 if (temp) 370 { 371 /* Convert to a power of 2 alignment. */ 372 for (align = 0; (temp & 1) == 0; temp >>= 1, ++align) 373 ; 374 375 if (temp != 1) 376 { 377 as_bad (_("Common alignment not a power of 2")); 378 ignore_rest_of_line (); 379 return; 380 } 381 } 382 else 383 align = 0; 384 385 record_alignment (now_seg, align); 386 387 if (align) 388 frag_align (align, 0, 0); 389 390 switch (area) 391 { 392 case SCOMMON_SECTION: 393 if (S_GET_SEGMENT (symbolP) == v850_seg_table[SBSS_SECTION].s) 394 symbol_get_frag (symbolP)->fr_symbol = 0; 395 break; 396 397 case ZCOMMON_SECTION: 398 if (S_GET_SEGMENT (symbolP) == v850_seg_table[ZBSS_SECTION].s) 399 symbol_get_frag (symbolP)->fr_symbol = 0; 400 break; 401 402 case TCOMMON_SECTION: 403 if (S_GET_SEGMENT (symbolP) == v850_seg_table[TBSS_SECTION].s) 404 symbol_get_frag (symbolP)->fr_symbol = 0; 405 break; 406 407 default: 408 abort (); 409 } 410 411 symbol_set_frag (symbolP, frag_now); 412 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, 413 (offsetT) size, (char *) 0); 414 *pfrag = 0; 415 S_SET_SIZE (symbolP, size); 416 417 switch (area) 418 { 419 case SCOMMON_SECTION: 420 S_SET_SEGMENT (symbolP, v850_seg_table[SBSS_SECTION].s); 421 break; 422 423 case ZCOMMON_SECTION: 424 S_SET_SEGMENT (symbolP, v850_seg_table[ZBSS_SECTION].s); 425 break; 426 427 case TCOMMON_SECTION: 428 S_SET_SEGMENT (symbolP, v850_seg_table[TBSS_SECTION].s); 429 break; 430 431 default: 432 abort (); 433 } 434 435 S_CLEAR_EXTERNAL (symbolP); 436 obj_elf_section_change_hook (); 437 subseg_set (old_sec, old_subsec); 438 } 439 else 440 { 441 segT old_sec; 442 int old_subsec; 443 444 allocate_common: 445 old_sec = now_seg; 446 old_subsec = now_subseg; 447 448 S_SET_VALUE (symbolP, (valueT) size); 449 S_SET_ALIGN (symbolP, temp); 450 S_SET_EXTERNAL (symbolP); 451 452 switch (area) 453 { 454 case SCOMMON_SECTION: 455 case ZCOMMON_SECTION: 456 case TCOMMON_SECTION: 457 do_v850_seg (area, 0); 458 S_SET_SEGMENT (symbolP, v850_seg_table[area].s); 459 break; 460 461 default: 462 abort (); 463 } 464 465 obj_elf_section_change_hook (); 466 subseg_set (old_sec, old_subsec); 467 } 468 } 469 else 470 { 471 input_line_pointer++; 472 473 /* @@ Some use the dot, some don't. Can we get some consistency?? */ 474 if (*input_line_pointer == '.') 475 input_line_pointer++; 476 477 /* @@ Some say data, some say bss. */ 478 if (strncmp (input_line_pointer, "bss\"", 4) 479 && strncmp (input_line_pointer, "data\"", 5)) 480 { 481 while (*--input_line_pointer != '"') 482 ; 483 input_line_pointer--; 484 goto bad_common_segment; 485 } 486 487 while (*input_line_pointer++ != '"') 488 ; 489 490 goto allocate_common; 491 } 492 493 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; 494 495 demand_empty_rest_of_line (); 496 return; 497 498 { 499 bad_common_segment: 500 p = input_line_pointer; 501 while (*p && *p != '\n') 502 p++; 503 c = *p; 504 *p = '\0'; 505 as_bad (_("bad .common segment %s"), input_line_pointer + 1); 506 *p = c; 507 input_line_pointer = p; 508 ignore_rest_of_line (); 509 return; 510 } 511 } 512 513 static void 514 set_machine (int number) 515 { 516 machine = number; 517 bfd_set_arch_mach (stdoutput, TARGET_ARCH, machine); 518 519 switch (machine) 520 { 521 case 0: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); break; 522 case bfd_mach_v850: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); break; 523 case bfd_mach_v850e: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); break; 524 case bfd_mach_v850e1: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); break; 525 case bfd_mach_v850e2: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2); break; 526 case bfd_mach_v850e2v3:SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3); break; 527 } 528 } 529 530 static void 531 v850_longcode (int type) 532 { 533 expressionS ex; 534 535 if (! v850_relax) 536 { 537 if (type == 1) 538 as_warn (_(".longcall pseudo-op seen when not relaxing")); 539 else 540 as_warn (_(".longjump pseudo-op seen when not relaxing")); 541 } 542 543 expression (&ex); 544 545 if (ex.X_op != O_symbol || ex.X_add_number != 0) 546 { 547 as_bad (_("bad .longcall format")); 548 ignore_rest_of_line (); 549 550 return; 551 } 552 553 if (type == 1) 554 fix_new_exp (frag_now, frag_now_fix (), 4, & ex, 1, 555 BFD_RELOC_V850_LONGCALL); 556 else 557 fix_new_exp (frag_now, frag_now_fix (), 4, & ex, 1, 558 BFD_RELOC_V850_LONGJUMP); 559 560 demand_empty_rest_of_line (); 561 } 562 563 /* The target specific pseudo-ops which we support. */ 564 const pseudo_typeS md_pseudo_table[] = 565 { 566 { "sdata", v850_seg, SDATA_SECTION }, 567 { "tdata", v850_seg, TDATA_SECTION }, 568 { "zdata", v850_seg, ZDATA_SECTION }, 569 { "sbss", v850_seg, SBSS_SECTION }, 570 { "tbss", v850_seg, TBSS_SECTION }, 571 { "zbss", v850_seg, ZBSS_SECTION }, 572 { "rosdata", v850_seg, ROSDATA_SECTION }, 573 { "rozdata", v850_seg, ROZDATA_SECTION }, 574 { "bss", v850_seg, BSS_SECTION }, 575 { "offset", v850_offset, 0 }, 576 { "word", cons, 4 }, 577 { "zcomm", v850_comm, ZCOMMON_SECTION }, 578 { "scomm", v850_comm, SCOMMON_SECTION }, 579 { "tcomm", v850_comm, TCOMMON_SECTION }, 580 { "v850", set_machine, 0 }, 581 { "call_table_data", v850_seg, CALL_TABLE_DATA_SECTION }, 582 { "call_table_text", v850_seg, CALL_TABLE_TEXT_SECTION }, 583 { "v850e", set_machine, bfd_mach_v850e }, 584 { "v850e1", set_machine, bfd_mach_v850e1 }, 585 { "v850e2", set_machine, bfd_mach_v850e2 }, 586 { "v850e2v3", set_machine, bfd_mach_v850e2v3 }, 587 { "longcall", v850_longcode, 1 }, 588 { "longjump", v850_longcode, 2 }, 589 { NULL, NULL, 0 } 590 }; 591 592 /* Opcode hash table. */ 593 static struct hash_control *v850_hash; 594 595 /* This table is sorted. Suitable for searching by a binary search. */ 596 static const struct reg_name pre_defined_registers[] = 597 { 598 { "ep", 30, PROCESSOR_ALL }, /* ep - element ptr. */ 599 { "gp", 4, PROCESSOR_ALL }, /* gp - global ptr. */ 600 { "hp", 2, PROCESSOR_ALL }, /* hp - handler stack ptr. */ 601 { "lp", 31, PROCESSOR_ALL }, /* lp - link ptr. */ 602 { "r0", 0, PROCESSOR_ALL }, 603 { "r1", 1, PROCESSOR_ALL }, 604 { "r10", 10, PROCESSOR_ALL }, 605 { "r11", 11, PROCESSOR_ALL }, 606 { "r12", 12, PROCESSOR_ALL }, 607 { "r13", 13, PROCESSOR_ALL }, 608 { "r14", 14, PROCESSOR_ALL }, 609 { "r15", 15, PROCESSOR_ALL }, 610 { "r16", 16, PROCESSOR_ALL }, 611 { "r17", 17, PROCESSOR_ALL }, 612 { "r18", 18, PROCESSOR_ALL }, 613 { "r19", 19, PROCESSOR_ALL }, 614 { "r2", 2, PROCESSOR_ALL }, 615 { "r20", 20, PROCESSOR_ALL }, 616 { "r21", 21, PROCESSOR_ALL }, 617 { "r22", 22, PROCESSOR_ALL }, 618 { "r23", 23, PROCESSOR_ALL }, 619 { "r24", 24, PROCESSOR_ALL }, 620 { "r25", 25, PROCESSOR_ALL }, 621 { "r26", 26, PROCESSOR_ALL }, 622 { "r27", 27, PROCESSOR_ALL }, 623 { "r28", 28, PROCESSOR_ALL }, 624 { "r29", 29, PROCESSOR_ALL }, 625 { "r3", 3, PROCESSOR_ALL }, 626 { "r30", 30, PROCESSOR_ALL }, 627 { "r31", 31, PROCESSOR_ALL }, 628 { "r4", 4, PROCESSOR_ALL }, 629 { "r5", 5, PROCESSOR_ALL }, 630 { "r6", 6, PROCESSOR_ALL }, 631 { "r7", 7, PROCESSOR_ALL }, 632 { "r8", 8, PROCESSOR_ALL }, 633 { "r9", 9, PROCESSOR_ALL }, 634 { "sp", 3, PROCESSOR_ALL }, /* sp - stack ptr. */ 635 { "tp", 5, PROCESSOR_ALL }, /* tp - text ptr. */ 636 { "zero", 0, PROCESSOR_ALL }, 637 }; 638 639 #define REG_NAME_CNT \ 640 (sizeof (pre_defined_registers) / sizeof (struct reg_name)) 641 642 static const struct reg_name system_registers[] = 643 { 644 { "asid", 23, PROCESSOR_NOT_V850 }, 645 { "bpam", 25, PROCESSOR_NOT_V850 }, 646 { "bpav", 24, PROCESSOR_NOT_V850 }, 647 { "bpc", 22, PROCESSOR_NOT_V850 }, 648 { "bpdm", 27, PROCESSOR_NOT_V850 }, 649 { "bpdv", 26, PROCESSOR_NOT_V850 }, 650 { "bsel", 31, PROCESSOR_V850E2_ALL }, 651 { "cfg", 7, PROCESSOR_V850E2V3 }, 652 { "ctbp", 20, PROCESSOR_NOT_V850 }, 653 { "ctpc", 16, PROCESSOR_NOT_V850 }, 654 { "ctpsw", 17, PROCESSOR_NOT_V850 }, 655 { "dbic", 15, PROCESSOR_V850E2_ALL }, 656 { "dbpc", 18, PROCESSOR_NOT_V850 }, 657 { "dbpsw", 19, PROCESSOR_NOT_V850 }, 658 { "dbwr", 30, PROCESSOR_V850E2_ALL }, 659 { "dir", 21, PROCESSOR_NOT_V850 }, 660 { "dpa0l", 16, PROCESSOR_V850E2V3 }, 661 { "dpa0u", 17, PROCESSOR_V850E2V3 }, 662 { "dpa1l", 18, PROCESSOR_V850E2V3 }, 663 { "dpa1u", 19, PROCESSOR_V850E2V3 }, 664 { "dpa2l", 20, PROCESSOR_V850E2V3 }, 665 { "dpa2u", 21, PROCESSOR_V850E2V3 }, 666 { "dpa3l", 22, PROCESSOR_V850E2V3 }, 667 { "dpa3u", 23, PROCESSOR_V850E2V3 }, 668 { "dpa4l", 24, PROCESSOR_V850E2V3 }, 669 { "dpa4u", 25, PROCESSOR_V850E2V3 }, 670 { "dpa5l", 26, PROCESSOR_V850E2V3 }, 671 { "dpa5u", 27, PROCESSOR_V850E2V3 }, 672 { "ecr", 4, PROCESSOR_ALL }, 673 { "eh_base", 3, PROCESSOR_V850E2V3 }, 674 { "eh_cfg", 1, PROCESSOR_V850E2V3 }, 675 { "eh_reset", 2, PROCESSOR_V850E2V3 }, 676 { "eiic", 13, PROCESSOR_V850E2_ALL }, 677 { "eipc", 0, PROCESSOR_ALL }, 678 { "eipsw", 1, PROCESSOR_ALL }, 679 { "eiwr", 28, PROCESSOR_V850E2_ALL }, 680 { "feic", 14, PROCESSOR_V850E2_ALL }, 681 { "fepc", 2, PROCESSOR_ALL }, 682 { "fepsw", 3, PROCESSOR_ALL }, 683 { "fewr", 29, PROCESSOR_V850E2_ALL }, 684 { "fpcc", 9, PROCESSOR_V850E2V3 }, 685 { "fpcfg", 10, PROCESSOR_V850E2V3 }, 686 { "fpec", 11, PROCESSOR_V850E2V3 }, 687 { "fpepc", 7, PROCESSOR_V850E2V3 }, 688 { "fpspc", 27, PROCESSOR_V850E2V3 }, 689 { "fpsr", 6, PROCESSOR_V850E2V3 }, 690 { "fpst", 8, PROCESSOR_V850E2V3 }, 691 { "ipa0l", 6, PROCESSOR_V850E2V3 }, 692 { "ipa0u", 7, PROCESSOR_V850E2V3 }, 693 { "ipa1l", 8, PROCESSOR_V850E2V3 }, 694 { "ipa1u", 9, PROCESSOR_V850E2V3 }, 695 { "ipa2l", 10, PROCESSOR_V850E2V3 }, 696 { "ipa2u", 11, PROCESSOR_V850E2V3 }, 697 { "ipa3l", 12, PROCESSOR_V850E2V3 }, 698 { "ipa3u", 13, PROCESSOR_V850E2V3 }, 699 { "ipa4l", 14, PROCESSOR_V850E2V3 }, 700 { "ipa4u", 15, PROCESSOR_V850E2V3 }, 701 { "mca", 24, PROCESSOR_V850E2V3 }, 702 { "mcc", 26, PROCESSOR_V850E2V3 }, 703 { "mcr", 27, PROCESSOR_V850E2V3 }, 704 { "mcs", 25, PROCESSOR_V850E2V3 }, 705 { "mpc", 1, PROCESSOR_V850E2V3 }, 706 { "mpm", 0, PROCESSOR_V850E2V3 }, 707 { "mpu10_dpa0l", 16, PROCESSOR_V850E2V3 }, 708 { "mpu10_dpa0u", 17, PROCESSOR_V850E2V3 }, 709 { "mpu10_dpa1l", 18, PROCESSOR_V850E2V3 }, 710 { "mpu10_dpa1u", 19, PROCESSOR_V850E2V3 }, 711 { "mpu10_dpa2l", 20, PROCESSOR_V850E2V3 }, 712 { "mpu10_dpa2u", 21, PROCESSOR_V850E2V3 }, 713 { "mpu10_dpa3l", 22, PROCESSOR_V850E2V3 }, 714 { "mpu10_dpa3u", 23, PROCESSOR_V850E2V3 }, 715 { "mpu10_dpa4l", 24, PROCESSOR_V850E2V3 }, 716 { "mpu10_dpa4u", 25, PROCESSOR_V850E2V3 }, 717 { "mpu10_dpa5l", 26, PROCESSOR_V850E2V3 }, 718 { "mpu10_dpa5u", 27, PROCESSOR_V850E2V3 }, 719 { "mpu10_ipa0l", 6, PROCESSOR_V850E2V3 }, 720 { "mpu10_ipa0u", 7, PROCESSOR_V850E2V3 }, 721 { "mpu10_ipa1l", 8, PROCESSOR_V850E2V3 }, 722 { "mpu10_ipa1u", 9, PROCESSOR_V850E2V3 }, 723 { "mpu10_ipa2l", 10, PROCESSOR_V850E2V3 }, 724 { "mpu10_ipa2u", 11, PROCESSOR_V850E2V3 }, 725 { "mpu10_ipa3l", 12, PROCESSOR_V850E2V3 }, 726 { "mpu10_ipa3u", 13, PROCESSOR_V850E2V3 }, 727 { "mpu10_ipa4l", 14, PROCESSOR_V850E2V3 }, 728 { "mpu10_ipa4u", 15, PROCESSOR_V850E2V3 }, 729 { "mpu10_mpc", 1, PROCESSOR_V850E2V3 }, 730 { "mpu10_mpm", 0, PROCESSOR_V850E2V3 }, 731 { "mpu10_tid", 2, PROCESSOR_V850E2V3 }, 732 { "mpu10_vmadr", 5, PROCESSOR_V850E2V3 }, 733 { "mpu10_vmecr", 3, PROCESSOR_V850E2V3 }, 734 { "mpu10_vmtid", 4, PROCESSOR_V850E2V3 }, 735 { "pid", 6, PROCESSOR_V850E2V3 }, 736 { "pmcr0", 4, PROCESSOR_V850E2V3 }, 737 { "pmis2", 14, PROCESSOR_V850E2V3 }, 738 { "psw", 5, PROCESSOR_ALL }, 739 { "scbp", 12, PROCESSOR_V850E2V3 }, 740 { "sccfg", 11, PROCESSOR_V850E2V3 }, 741 { "sr0", 0, PROCESSOR_ALL }, 742 { "sr1", 1, PROCESSOR_ALL }, 743 { "sr10", 10, PROCESSOR_ALL }, 744 { "sr11", 11, PROCESSOR_ALL }, 745 { "sr12", 12, PROCESSOR_ALL }, 746 { "sr13", 13, PROCESSOR_ALL }, 747 { "sr14", 14, PROCESSOR_ALL }, 748 { "sr15", 15, PROCESSOR_ALL }, 749 { "sr16", 16, PROCESSOR_ALL }, 750 { "sr17", 17, PROCESSOR_ALL }, 751 { "sr18", 18, PROCESSOR_ALL }, 752 { "sr19", 19, PROCESSOR_ALL }, 753 { "sr2", 2, PROCESSOR_ALL }, 754 { "sr20", 20, PROCESSOR_ALL }, 755 { "sr21", 21, PROCESSOR_ALL }, 756 { "sr22", 22, PROCESSOR_ALL }, 757 { "sr23", 23, PROCESSOR_ALL }, 758 { "sr24", 24, PROCESSOR_ALL }, 759 { "sr25", 25, PROCESSOR_ALL }, 760 { "sr26", 26, PROCESSOR_ALL }, 761 { "sr27", 27, PROCESSOR_ALL }, 762 { "sr28", 28, PROCESSOR_ALL }, 763 { "sr29", 29, PROCESSOR_ALL }, 764 { "sr3", 3, PROCESSOR_ALL }, 765 { "sr30", 30, PROCESSOR_ALL }, 766 { "sr31", 31, PROCESSOR_ALL }, 767 { "sr4", 4, PROCESSOR_ALL }, 768 { "sr5", 5, PROCESSOR_ALL }, 769 { "sr6", 6, PROCESSOR_ALL }, 770 { "sr7", 7, PROCESSOR_ALL }, 771 { "sr8", 8, PROCESSOR_ALL }, 772 { "sr9", 9, PROCESSOR_ALL }, 773 { "sw_base", 3, PROCESSOR_V850E2V3 }, 774 { "sw_cfg", 1, PROCESSOR_V850E2V3 }, 775 { "sw_ctl", 0, PROCESSOR_V850E2V3 }, 776 { "tid", 2, PROCESSOR_V850E2V3 }, 777 { "vmadr", 6, PROCESSOR_V850E2V3 }, 778 { "vmecr", 4, PROCESSOR_V850E2V3 }, 779 { "vmtid", 5, PROCESSOR_V850E2V3 }, 780 { "vsadr", 2, PROCESSOR_V850E2V3 }, 781 { "vsecr", 0, PROCESSOR_V850E2V3 }, 782 { "vstid", 1, PROCESSOR_V850E2V3 }, 783 }; 784 785 #define SYSREG_NAME_CNT \ 786 (sizeof (system_registers) / sizeof (struct reg_name)) 787 788 789 static const struct reg_name cc_names[] = 790 { 791 { "c", 0x1, PROCESSOR_ALL }, 792 { "e", 0x2, PROCESSOR_ALL }, 793 { "ge", 0xe, PROCESSOR_ALL }, 794 { "gt", 0xf, PROCESSOR_ALL }, 795 { "h", 0xb, PROCESSOR_ALL }, 796 { "l", 0x1, PROCESSOR_ALL }, 797 { "le", 0x7, PROCESSOR_ALL }, 798 { "lt", 0x6, PROCESSOR_ALL }, 799 { "n", 0x4, PROCESSOR_ALL }, 800 { "nc", 0x9, PROCESSOR_ALL }, 801 { "ne", 0xa, PROCESSOR_ALL }, 802 { "nh", 0x3, PROCESSOR_ALL }, 803 { "nl", 0x9, PROCESSOR_ALL }, 804 { "ns", 0xc, PROCESSOR_ALL }, 805 { "nv", 0x8, PROCESSOR_ALL }, 806 { "nz", 0xa, PROCESSOR_ALL }, 807 { "p", 0xc, PROCESSOR_ALL }, 808 { "s", 0x4, PROCESSOR_ALL }, 809 #define COND_SA_NUM 0xd 810 { "sa", COND_SA_NUM, PROCESSOR_ALL }, 811 { "t", 0x5, PROCESSOR_ALL }, 812 { "v", 0x0, PROCESSOR_ALL }, 813 { "z", 0x2, PROCESSOR_ALL }, 814 }; 815 816 #define CC_NAME_CNT \ 817 (sizeof (cc_names) / sizeof (struct reg_name)) 818 819 static const struct reg_name float_cc_names[] = 820 { 821 { "eq", 0x2, PROCESSOR_V850E2V3 }, /* true. */ 822 { "f", 0x0, PROCESSOR_V850E2V3 }, /* true. */ 823 { "ge", 0xd, PROCESSOR_V850E2V3 }, /* false. */ 824 { "gl", 0xb, PROCESSOR_V850E2V3 }, /* false. */ 825 { "gle", 0x9, PROCESSOR_V850E2V3 }, /* false. */ 826 { "gt", 0xf, PROCESSOR_V850E2V3 }, /* false. */ 827 { "le", 0xe, PROCESSOR_V850E2V3 }, /* true. */ 828 { "lt", 0xc, PROCESSOR_V850E2V3 }, /* true. */ 829 { "neq", 0x2, PROCESSOR_V850E2V3 }, /* false. */ 830 { "nge", 0xd, PROCESSOR_V850E2V3 }, /* true. */ 831 { "ngl", 0xb, PROCESSOR_V850E2V3 }, /* true. */ 832 { "ngle",0x9, PROCESSOR_V850E2V3 }, /* true. */ 833 { "ngt", 0xf, PROCESSOR_V850E2V3 }, /* true. */ 834 { "nle", 0xe, PROCESSOR_V850E2V3 }, /* false. */ 835 { "nlt", 0xc, PROCESSOR_V850E2V3 }, /* false. */ 836 { "oge", 0x5, PROCESSOR_V850E2V3 }, /* false. */ 837 { "ogl", 0x3, PROCESSOR_V850E2V3 }, /* false. */ 838 { "ogt", 0x7, PROCESSOR_V850E2V3 }, /* false. */ 839 { "ole", 0x6, PROCESSOR_V850E2V3 }, /* true. */ 840 { "olt", 0x4, PROCESSOR_V850E2V3 }, /* true. */ 841 { "or", 0x1, PROCESSOR_V850E2V3 }, /* false. */ 842 { "seq", 0xa, PROCESSOR_V850E2V3 }, /* true. */ 843 { "sf", 0x8, PROCESSOR_V850E2V3 }, /* true. */ 844 { "sne", 0xa, PROCESSOR_V850E2V3 }, /* false. */ 845 { "st", 0x8, PROCESSOR_V850E2V3 }, /* false. */ 846 { "t", 0x0, PROCESSOR_V850E2V3 }, /* false. */ 847 { "ueq", 0x3, PROCESSOR_V850E2V3 }, /* true. */ 848 { "uge", 0x4, PROCESSOR_V850E2V3 }, /* false. */ 849 { "ugt", 0x6, PROCESSOR_V850E2V3 }, /* false. */ 850 { "ule", 0x7, PROCESSOR_V850E2V3 }, /* true. */ 851 { "ult", 0x5, PROCESSOR_V850E2V3 }, /* true. */ 852 { "un", 0x1, PROCESSOR_V850E2V3 }, /* true. */ 853 }; 854 855 #define FLOAT_CC_NAME_CNT \ 856 (sizeof (float_cc_names) / sizeof (struct reg_name)) 857 858 /* Do a binary search of the given register table to see if NAME is a 859 valid regiter name. Return the register number from the array on 860 success, or -1 on failure. */ 861 862 static int 863 reg_name_search (const struct reg_name *regs, 864 int regcount, 865 const char *name, 866 bfd_boolean accept_numbers) 867 { 868 int middle, low, high; 869 int cmp; 870 symbolS *symbolP; 871 872 /* If the register name is a symbol, then evaluate it. */ 873 if ((symbolP = symbol_find (name)) != NULL) 874 { 875 /* If the symbol is an alias for another name then use that. 876 If the symbol is an alias for a number, then return the number. */ 877 if (symbol_equated_p (symbolP)) 878 name 879 = S_GET_NAME (symbol_get_value_expression (symbolP)->X_add_symbol); 880 else if (accept_numbers) 881 { 882 int reg = S_GET_VALUE (symbolP); 883 return reg; 884 } 885 886 /* Otherwise drop through and try parsing name normally. */ 887 } 888 889 low = 0; 890 high = regcount - 1; 891 892 do 893 { 894 middle = (low + high) / 2; 895 cmp = strcasecmp (name, regs[middle].name); 896 if (cmp < 0) 897 high = middle - 1; 898 else if (cmp > 0) 899 low = middle + 1; 900 else 901 return ((regs[middle].processors & processor_mask) 902 ? regs[middle].value 903 : -1); 904 } 905 while (low <= high); 906 return -1; 907 } 908 909 /* Summary of register_name(). 910 911 in: Input_line_pointer points to 1st char of operand. 912 913 out: An expressionS. 914 The operand may have been a register: in this case, X_op == O_register, 915 X_add_number is set to the register number, and truth is returned. 916 Input_line_pointer->(next non-blank) char after operand, or is in 917 its original state. */ 918 919 static bfd_boolean 920 register_name (expressionS *expressionP) 921 { 922 int reg_number; 923 char *name; 924 char *start; 925 char c; 926 927 /* Find the spelling of the operand. */ 928 start = name = input_line_pointer; 929 930 c = get_symbol_end (); 931 932 reg_number = reg_name_search (pre_defined_registers, REG_NAME_CNT, 933 name, FALSE); 934 935 /* Put back the delimiting char. */ 936 *input_line_pointer = c; 937 938 expressionP->X_add_symbol = NULL; 939 expressionP->X_op_symbol = NULL; 940 941 /* Look to see if it's in the register table. */ 942 if (reg_number >= 0) 943 { 944 expressionP->X_op = O_register; 945 expressionP->X_add_number = reg_number; 946 947 return TRUE; 948 } 949 950 /* Reset the line as if we had not done anything. */ 951 input_line_pointer = start; 952 953 expressionP->X_op = O_illegal; 954 955 return FALSE; 956 } 957 958 /* Summary of system_register_name(). 959 960 in: INPUT_LINE_POINTER points to 1st char of operand. 961 EXPRESSIONP points to an expression structure to be filled in. 962 ACCEPT_NUMBERS is true iff numerical register names may be used. 963 964 out: An expressionS structure in expressionP. 965 The operand may have been a register: in this case, X_op == O_register, 966 X_add_number is set to the register number, and truth is returned. 967 Input_line_pointer->(next non-blank) char after operand, or is in 968 its original state. */ 969 970 static bfd_boolean 971 system_register_name (expressionS *expressionP, 972 bfd_boolean accept_numbers) 973 { 974 int reg_number; 975 char *name; 976 char *start; 977 char c; 978 979 /* Find the spelling of the operand. */ 980 start = name = input_line_pointer; 981 982 c = get_symbol_end (); 983 reg_number = reg_name_search (system_registers, SYSREG_NAME_CNT, name, 984 accept_numbers); 985 986 /* Put back the delimiting char. */ 987 *input_line_pointer = c; 988 989 if (reg_number < 0 990 && accept_numbers) 991 { 992 /* Reset input_line pointer. */ 993 input_line_pointer = start; 994 995 if (ISDIGIT (*input_line_pointer)) 996 { 997 reg_number = strtol (input_line_pointer, &input_line_pointer, 0); 998 } 999 } 1000 1001 expressionP->X_add_symbol = NULL; 1002 expressionP->X_op_symbol = NULL; 1003 1004 /* Look to see if it's in the register table. */ 1005 if (reg_number >= 0) 1006 { 1007 expressionP->X_op = O_register; 1008 expressionP->X_add_number = reg_number; 1009 1010 return TRUE; 1011 } 1012 1013 /* Reset the line as if we had not done anything. */ 1014 input_line_pointer = start; 1015 1016 expressionP->X_op = O_illegal; 1017 1018 return FALSE; 1019 } 1020 1021 /* Summary of cc_name(). 1022 1023 in: INPUT_LINE_POINTER points to 1st char of operand. 1024 1025 out: An expressionS. 1026 The operand may have been a register: in this case, X_op == O_register, 1027 X_add_number is set to the register number, and truth is returned. 1028 Input_line_pointer->(next non-blank) char after operand, or is in 1029 its original state. */ 1030 1031 static bfd_boolean 1032 cc_name (expressionS *expressionP, 1033 bfd_boolean accept_numbers) 1034 { 1035 int reg_number; 1036 char *name; 1037 char *start; 1038 char c; 1039 1040 /* Find the spelling of the operand. */ 1041 start = name = input_line_pointer; 1042 1043 c = get_symbol_end (); 1044 reg_number = reg_name_search (cc_names, CC_NAME_CNT, name, accept_numbers); 1045 1046 /* Put back the delimiting char. */ 1047 *input_line_pointer = c; 1048 1049 if (reg_number < 0 1050 && accept_numbers) 1051 { 1052 /* Reset input_line pointer. */ 1053 input_line_pointer = start; 1054 1055 if (ISDIGIT (*input_line_pointer)) 1056 { 1057 reg_number = strtol (input_line_pointer, &input_line_pointer, 0); 1058 } 1059 } 1060 1061 expressionP->X_add_symbol = NULL; 1062 expressionP->X_op_symbol = NULL; 1063 1064 /* Look to see if it's in the register table. */ 1065 if (reg_number >= 0) 1066 { 1067 expressionP->X_op = O_constant; 1068 expressionP->X_add_number = reg_number; 1069 1070 return TRUE; 1071 } 1072 1073 /* Reset the line as if we had not done anything. */ 1074 input_line_pointer = start; 1075 1076 expressionP->X_op = O_illegal; 1077 expressionP->X_add_number = 0; 1078 1079 return FALSE; 1080 } 1081 1082 static bfd_boolean 1083 float_cc_name (expressionS *expressionP, 1084 bfd_boolean accept_numbers) 1085 { 1086 int reg_number; 1087 char *name; 1088 char *start; 1089 char c; 1090 1091 /* Find the spelling of the operand. */ 1092 start = name = input_line_pointer; 1093 1094 c = get_symbol_end (); 1095 reg_number = reg_name_search (float_cc_names, FLOAT_CC_NAME_CNT, name, accept_numbers); 1096 1097 /* Put back the delimiting char. */ 1098 *input_line_pointer = c; 1099 1100 if (reg_number < 0 1101 && accept_numbers) 1102 { 1103 /* Reset input_line pointer. */ 1104 input_line_pointer = start; 1105 1106 if (ISDIGIT (*input_line_pointer)) 1107 { 1108 reg_number = strtol (input_line_pointer, &input_line_pointer, 0); 1109 } 1110 } 1111 1112 expressionP->X_add_symbol = NULL; 1113 expressionP->X_op_symbol = NULL; 1114 1115 /* Look to see if it's in the register table. */ 1116 if (reg_number >= 0) 1117 { 1118 expressionP->X_op = O_constant; 1119 expressionP->X_add_number = reg_number; 1120 1121 return TRUE; 1122 } 1123 1124 /* Reset the line as if we had not done anything. */ 1125 input_line_pointer = start; 1126 1127 expressionP->X_op = O_illegal; 1128 expressionP->X_add_number = 0; 1129 1130 return FALSE; 1131 } 1132 1133 static void 1134 skip_white_space (void) 1135 { 1136 while (*input_line_pointer == ' ' 1137 || *input_line_pointer == '\t') 1138 ++input_line_pointer; 1139 } 1140 1141 /* Summary of parse_register_list (). 1142 1143 in: INPUT_LINE_POINTER points to 1st char of a list of registers. 1144 INSN is the partially constructed instruction. 1145 OPERAND is the operand being inserted. 1146 1147 out: NULL if the parse completed successfully, otherwise a 1148 pointer to an error message is returned. If the parse 1149 completes the correct bit fields in the instruction 1150 will be filled in. 1151 1152 Parses register lists with the syntax: 1153 1154 { rX } 1155 { rX, rY } 1156 { rX - rY } 1157 { rX - rY, rZ } 1158 etc 1159 1160 and also parses constant expressions whoes bits indicate the 1161 registers in the lists. The LSB in the expression refers to 1162 the lowest numbered permissible register in the register list, 1163 and so on upwards. System registers are considered to be very 1164 high numbers. */ 1165 1166 static char * 1167 parse_register_list (unsigned long *insn, 1168 const struct v850_operand *operand) 1169 { 1170 static int type1_regs[32] = 1171 { 1172 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1173 0, 0, 0, 0, 0, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 1174 }; 1175 1176 int *regs; 1177 expressionS exp; 1178 1179 /* Select a register array to parse. */ 1180 switch (operand->shift) 1181 { 1182 case 0xffe00001: regs = type1_regs; break; 1183 default: 1184 as_bad (_("unknown operand shift: %x\n"), operand->shift); 1185 return _("internal failure in parse_register_list"); 1186 } 1187 1188 skip_white_space (); 1189 1190 /* If the expression starts with a curly brace it is a register list. 1191 Otherwise it is a constant expression, whoes bits indicate which 1192 registers are to be included in the list. */ 1193 if (*input_line_pointer != '{') 1194 { 1195 int reg; 1196 int i; 1197 1198 expression (&exp); 1199 1200 if (exp.X_op != O_constant) 1201 return _("constant expression or register list expected"); 1202 1203 if (regs == type1_regs) 1204 { 1205 if (exp.X_add_number & 0xFFFFF000) 1206 return _("high bits set in register list expression"); 1207 1208 for (reg = 20; reg < 32; reg++) 1209 if (exp.X_add_number & (1 << (reg - 20))) 1210 { 1211 for (i = 0; i < 32; i++) 1212 if (regs[i] == reg) 1213 *insn |= (1 << i); 1214 } 1215 } 1216 1217 return NULL; 1218 } 1219 1220 input_line_pointer++; 1221 1222 /* Parse the register list until a terminator (closing curly brace or 1223 new-line) is found. */ 1224 for (;;) 1225 { 1226 skip_white_space (); 1227 1228 if (register_name (&exp)) 1229 { 1230 int i; 1231 1232 /* Locate the given register in the list, and if it is there, 1233 insert the corresponding bit into the instruction. */ 1234 for (i = 0; i < 32; i++) 1235 { 1236 if (regs[i] == exp.X_add_number) 1237 { 1238 *insn |= (1 << i); 1239 break; 1240 } 1241 } 1242 1243 if (i == 32) 1244 return _("illegal register included in list"); 1245 } 1246 else if (system_register_name (&exp, TRUE)) 1247 { 1248 if (regs == type1_regs) 1249 { 1250 return _("system registers cannot be included in list"); 1251 } 1252 } 1253 1254 if (*input_line_pointer == '}') 1255 { 1256 input_line_pointer++; 1257 break; 1258 } 1259 else if (*input_line_pointer == ',') 1260 { 1261 input_line_pointer++; 1262 continue; 1263 } 1264 else if (*input_line_pointer == '-') 1265 { 1266 /* We have encountered a range of registers: rX - rY. */ 1267 int j; 1268 expressionS exp2; 1269 1270 /* Skip the dash. */ 1271 ++input_line_pointer; 1272 1273 /* Get the second register in the range. */ 1274 if (! register_name (&exp2)) 1275 { 1276 return _("second register should follow dash in register list"); 1277 } 1278 1279 if (exp.X_add_number > exp2.X_add_number) 1280 { 1281 return _("second register should be greater than first register"); 1282 } 1283 1284 /* Add the rest of the registers in the range. */ 1285 for (j = exp.X_add_number + 1; j <= exp2.X_add_number; j++) 1286 { 1287 int i; 1288 1289 /* Locate the given register in the list, and if it is there, 1290 insert the corresponding bit into the instruction. */ 1291 for (i = 0; i < 32; i++) 1292 { 1293 if (regs[i] == j) 1294 { 1295 *insn |= (1 << i); 1296 break; 1297 } 1298 } 1299 1300 if (i == 32) 1301 return _("illegal register included in list"); 1302 } 1303 1304 exp = exp2; 1305 } 1306 else 1307 break; 1308 } 1309 1310 return NULL; 1311 } 1312 1313 const char *md_shortopts = "m:"; 1314 1315 struct option md_longopts[] = 1316 { 1317 #define OPTION_DISP_SIZE_DEFAULT_22 (OPTION_MD_BASE) 1318 {"disp-size-default-22", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_22}, 1319 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 1) 1320 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32}, 1321 {NULL, no_argument, NULL, 0} 1322 }; 1323 1324 size_t md_longopts_size = sizeof (md_longopts); 1325 1326 void 1327 md_show_usage (FILE *stream) 1328 { 1329 fprintf (stream, _(" V850 options:\n")); 1330 fprintf (stream, _(" -mwarn-signed-overflow Warn if signed immediate values overflow\n")); 1331 fprintf (stream, _(" -mwarn-unsigned-overflow Warn if unsigned immediate values overflow\n")); 1332 fprintf (stream, _(" -mv850 The code is targeted at the v850\n")); 1333 fprintf (stream, _(" -mv850e The code is targeted at the v850e\n")); 1334 fprintf (stream, _(" -mv850e1 The code is targeted at the v850e1\n")); 1335 fprintf (stream, _(" -mv850e2 The code is targeted at the v850e2\n")); 1336 fprintf (stream, _(" -mv850e2v3 The code is targeted at the v850e2v3\n")); 1337 fprintf (stream, _(" -mrelax Enable relaxation\n")); 1338 fprintf (stream, _(" --disp-size-default-22 branch displacement with unknown size is 22 bits (default)\n")); 1339 fprintf (stream, _(" --disp-size-default-32 branch displacement with unknown size is 32 bits\n")); 1340 fprintf (stream, _(" -mextension enable extension opcode support\n")); 1341 fprintf (stream, _(" -mno-bcond17 disable b<cond> disp17 instruction\n")); 1342 fprintf (stream, _(" -mno-stld23 disable st/ld offset23 instruction\n")); 1343 } 1344 1345 int 1346 md_parse_option (int c, char *arg) 1347 { 1348 if (c != 'm') 1349 { 1350 switch (c) 1351 { 1352 case OPTION_DISP_SIZE_DEFAULT_22: 1353 default_disp_size = 22; 1354 return 1; 1355 1356 case OPTION_DISP_SIZE_DEFAULT_32: 1357 default_disp_size = 32; 1358 return 1; 1359 } 1360 return 0; 1361 } 1362 1363 if (strcmp (arg, "warn-signed-overflow") == 0) 1364 warn_signed_overflows = TRUE; 1365 1366 else if (strcmp (arg, "warn-unsigned-overflow") == 0) 1367 warn_unsigned_overflows = TRUE; 1368 1369 else if (strcmp (arg, "v850") == 0) 1370 { 1371 machine = 0; 1372 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); 1373 } 1374 else if (strcmp (arg, "v850e") == 0) 1375 { 1376 machine = bfd_mach_v850e; 1377 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); 1378 } 1379 else if (strcmp (arg, "v850e1") == 0) 1380 { 1381 machine = bfd_mach_v850e1; 1382 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E1); 1383 } 1384 else if (strcmp (arg, "v850e2") == 0) 1385 { 1386 machine = bfd_mach_v850e2; 1387 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2); 1388 } 1389 else if (strcmp (arg, "v850e2v3") == 0) 1390 { 1391 machine = bfd_mach_v850e2v3; 1392 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3); 1393 } 1394 else if (strcmp (arg, "extension") == 0) 1395 { 1396 processor_mask |= PROCESSOR_OPTION_EXTENSION | PROCESSOR_OPTION_ALIAS;; 1397 } 1398 else if (strcmp (arg, "no-bcond17") == 0) 1399 { 1400 no_bcond17 = 1; 1401 } 1402 else if (strcmp (arg, "no-stld23") == 0) 1403 { 1404 no_stld23 = 1; 1405 } 1406 else if (strcmp (arg, "relax") == 0) 1407 v850_relax = 1; 1408 else 1409 return 0; 1410 1411 return 1; 1412 } 1413 1414 symbolS * 1415 md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 1416 { 1417 return 0; 1418 } 1419 1420 char * 1421 md_atof (int type, char *litp, int *sizep) 1422 { 1423 return ieee_md_atof (type, litp, sizep, FALSE); 1424 } 1425 1426 /* Very gross. */ 1427 1428 void 1429 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, 1430 asection *sec, 1431 fragS *fragP) 1432 { 1433 union u 1434 { 1435 bfd_reloc_code_real_type fx_r_type; 1436 char * fr_opcode; 1437 } 1438 opcode_converter; 1439 subseg_change (sec, 0); 1440 1441 opcode_converter.fr_opcode = fragP->fr_opcode; 1442 1443 subseg_change (sec, 0); 1444 1445 /* In range conditional or unconditional branch. */ 1446 if (fragP->fr_subtype == SUBYPTE_COND_9_22 1447 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22 1448 || fragP->fr_subtype == SUBYPTE_COND_9_22_32 1449 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 1450 || fragP->fr_subtype == SUBYPTE_COND_9_17_22 1451 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 1452 || fragP->fr_subtype == SUBYPTE_SA_9_22 1453 || fragP->fr_subtype == SUBYPTE_SA_9_22_32 1454 || fragP->fr_subtype == SUBYPTE_SA_9_17_22 1455 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32) 1456 1457 { 1458 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 1459 fragP->fr_offset, 1, 1460 BFD_RELOC_UNUSED + opcode_converter.fx_r_type); 1461 fragP->fr_fix += 2; 1462 } 1463 /* V850e2r-v3 17bit conditional branch. */ 1464 else if (fragP->fr_subtype == SUBYPTE_COND_9_17_22 + 1 1465 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 1 1466 || fragP->fr_subtype == SUBYPTE_SA_9_17_22 + 1 1467 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 1) 1468 { 1469 unsigned char *buffer = 1470 (unsigned char *) (fragP->fr_fix + fragP->fr_literal); 1471 1472 buffer[0] &= 0x0f; /* Use condition. */ 1473 buffer[0] |= 0xe0; 1474 buffer[1] = 0x07; 1475 1476 /* Now create the unconditional branch + fixup to the final 1477 target. */ 1478 md_number_to_chars ((char *) buffer + 2, 0x0001, 2); 1479 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 1480 fragP->fr_offset, 1, BFD_RELOC_V850_17_PCREL); 1481 fragP->fr_fix += 4; 1482 } 1483 /* Out of range conditional branch. Emit a branch around a 22bit jump. */ 1484 else if (fragP->fr_subtype == SUBYPTE_COND_9_22 + 1 1485 || fragP->fr_subtype == SUBYPTE_COND_9_22_32 + 1 1486 || fragP->fr_subtype == SUBYPTE_COND_9_17_22 + 2 1487 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 2) 1488 { 1489 unsigned char *buffer = 1490 (unsigned char *) (fragP->fr_fix + fragP->fr_literal); 1491 1492 /* Reverse the condition of the first branch. */ 1493 buffer[0] ^= 0x08; 1494 /* Mask off all the displacement bits. */ 1495 buffer[0] &= 0x8f; 1496 buffer[1] &= 0x07; 1497 /* Now set the displacement bits so that we branch 1498 around the unconditional branch. */ 1499 buffer[0] |= 0x30; 1500 1501 /* Now create the unconditional branch + fixup to the final 1502 target. */ 1503 md_number_to_chars ((char *) buffer + 2, 0x00000780, 4); 1504 fix_new (fragP, fragP->fr_fix + 2, 4, fragP->fr_symbol, 1505 fragP->fr_offset, 1, BFD_RELOC_V850_22_PCREL); 1506 fragP->fr_fix += 6; 1507 } 1508 /* Out of range conditional branch. Emit a branch around a 32bit jump. */ 1509 else if (fragP->fr_subtype == SUBYPTE_COND_9_22_32 + 2 1510 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 3) 1511 { 1512 unsigned char *buffer = 1513 (unsigned char *) (fragP->fr_fix + fragP->fr_literal); 1514 1515 /* Reverse the condition of the first branch. */ 1516 buffer[0] ^= 0x08; 1517 /* Mask off all the displacement bits. */ 1518 buffer[0] &= 0x8f; 1519 buffer[1] &= 0x07; 1520 /* Now set the displacement bits so that we branch 1521 around the unconditional branch. */ 1522 buffer[0] |= 0x40; 1523 1524 /* Now create the unconditional branch + fixup to the final 1525 target. */ 1526 md_number_to_chars ((char *) buffer + 2, 0x02e0, 2); 1527 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol, 1528 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL); 1529 fragP->fr_fix += 8; 1530 } 1531 /* Out of range unconditional branch. Emit a 22bit jump. */ 1532 else if (fragP->fr_subtype == SUBYPTE_UNCOND_9_22 + 1 1533 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 + 1) 1534 { 1535 md_number_to_chars (fragP->fr_fix + fragP->fr_literal, 0x00000780, 4); 1536 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 1537 fragP->fr_offset, 1, BFD_RELOC_V850_22_PCREL); 1538 fragP->fr_fix += 4; 1539 } 1540 /* Out of range unconditional branch. Emit a 32bit jump. */ 1541 else if (fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 + 2) 1542 { 1543 md_number_to_chars (fragP->fr_fix + fragP->fr_literal, 0x02e0, 2); 1544 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol, 1545 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL); 1546 fragP->fr_fix += 6; 1547 } 1548 /* Out of range SA conditional branch. Emit a branch to a 22bit jump. */ 1549 else if (fragP->fr_subtype == SUBYPTE_SA_9_22 + 1 1550 || fragP->fr_subtype == SUBYPTE_SA_9_22_32 + 1 1551 || fragP->fr_subtype == SUBYPTE_SA_9_17_22 + 2 1552 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 2) 1553 { 1554 unsigned char *buffer = 1555 (unsigned char *) (fragP->fr_fix + fragP->fr_literal); 1556 1557 /* bsa .+4 */ 1558 buffer[0] &= 0x8f; 1559 buffer[0] |= 0x20; 1560 buffer[1] &= 0x07; 1561 1562 /* br .+6 */ 1563 md_number_to_chars ((char *) buffer + 2, 0x05b5, 2); 1564 1565 /* Now create the unconditional branch + fixup to the final 1566 target. */ 1567 /* jr SYM */ 1568 md_number_to_chars ((char *) buffer + 4, 0x00000780, 4); 1569 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol, 1570 fragP->fr_offset, 1, 1571 BFD_RELOC_V850_22_PCREL); 1572 fragP->fr_fix += 8; 1573 } 1574 /* Out of range SA conditional branch. Emit a branch around a 32bit jump. */ 1575 else if (fragP->fr_subtype == SUBYPTE_SA_9_22_32 + 2 1576 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 3) 1577 { 1578 unsigned char *buffer = 1579 (unsigned char *) (fragP->fr_fix + fragP->fr_literal); 1580 1581 /* bsa .+2 */ 1582 buffer[0] &= 0x8f; 1583 buffer[0] |= 0x20; 1584 buffer[1] &= 0x07; 1585 1586 /* br .+8 */ 1587 md_number_to_chars ((char *) buffer + 2, 0x05c5, 2); 1588 1589 /* Now create the unconditional branch + fixup to the final 1590 target. */ 1591 /* jr SYM */ 1592 md_number_to_chars ((char *) buffer + 4, 0x02e0, 2); 1593 fix_new (fragP, fragP->fr_fix + 6, 4, fragP->fr_symbol, 1594 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL); 1595 1596 fragP->fr_fix += 10; 1597 } 1598 else 1599 abort (); 1600 } 1601 1602 valueT 1603 md_section_align (asection *seg, valueT addr) 1604 { 1605 int align = bfd_get_section_alignment (stdoutput, seg); 1606 return ((addr + (1 << align) - 1) & (-1 << align)); 1607 } 1608 1609 void 1610 md_begin (void) 1611 { 1612 char *prev_name = ""; 1613 const struct v850_opcode *op; 1614 1615 if (strncmp (TARGET_CPU, "v850e2v3", 8) == 0) 1616 { 1617 if (machine == -1) 1618 machine = bfd_mach_v850e2v3; 1619 1620 if (!processor_mask) 1621 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3); 1622 } 1623 else if (strncmp (TARGET_CPU, "v850e2", 6) == 0) 1624 { 1625 if (machine == -1) 1626 machine = bfd_mach_v850e2; 1627 1628 if (!processor_mask) 1629 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2); 1630 } 1631 else if (strncmp (TARGET_CPU, "v850e1", 6) == 0) 1632 { 1633 if (machine == -1) 1634 machine = bfd_mach_v850e1; 1635 1636 if (!processor_mask) 1637 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E1); 1638 } 1639 else if (strncmp (TARGET_CPU, "v850e", 5) == 0) 1640 { 1641 if (machine == -1) 1642 machine = bfd_mach_v850e; 1643 1644 if (!processor_mask) 1645 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); 1646 } 1647 else if (strncmp (TARGET_CPU, "v850", 4) == 0) 1648 { 1649 if (machine == -1) 1650 machine = 0; 1651 1652 if (!processor_mask) 1653 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); 1654 } 1655 else 1656 /* xgettext:c-format */ 1657 as_bad (_("Unable to determine default target processor from string: %s"), 1658 TARGET_CPU); 1659 1660 v850_hash = hash_new (); 1661 1662 /* Insert unique names into hash table. The V850 instruction set 1663 has many identical opcode names that have different opcodes based 1664 on the operands. This hash table then provides a quick index to 1665 the first opcode with a particular name in the opcode table. */ 1666 op = v850_opcodes; 1667 while (op->name) 1668 { 1669 if (strcmp (prev_name, op->name)) 1670 { 1671 prev_name = (char *) op->name; 1672 hash_insert (v850_hash, op->name, (char *) op); 1673 } 1674 op++; 1675 } 1676 1677 v850_seg_table[BSS_SECTION].s = bss_section; 1678 bfd_set_arch_mach (stdoutput, TARGET_ARCH, machine); 1679 } 1680 1681 1682 static bfd_reloc_code_real_type 1683 handle_hi016 (const struct v850_operand *operand, const char **errmsg) 1684 { 1685 if (operand == NULL) 1686 return BFD_RELOC_HI16; 1687 1688 if (operand->default_reloc == BFD_RELOC_HI16) 1689 return BFD_RELOC_HI16; 1690 1691 if (operand->default_reloc == BFD_RELOC_HI16_S) 1692 return BFD_RELOC_HI16; 1693 1694 if (operand->default_reloc == BFD_RELOC_16) 1695 return BFD_RELOC_HI16; 1696 1697 *errmsg = _("hi0() relocation used on an instruction which does " 1698 "not support it"); 1699 return BFD_RELOC_64; /* Used to indicate an error condition. */ 1700 } 1701 1702 static bfd_reloc_code_real_type 1703 handle_hi16 (const struct v850_operand *operand, const char **errmsg) 1704 { 1705 if (operand == NULL) 1706 return BFD_RELOC_HI16_S; 1707 1708 if (operand->default_reloc == BFD_RELOC_HI16_S) 1709 return BFD_RELOC_HI16_S; 1710 1711 if (operand->default_reloc == BFD_RELOC_HI16) 1712 return BFD_RELOC_HI16_S; 1713 1714 if (operand->default_reloc == BFD_RELOC_16) 1715 return BFD_RELOC_HI16_S; 1716 1717 *errmsg = _("hi() relocation used on an instruction which does " 1718 "not support it"); 1719 return BFD_RELOC_64; /* Used to indicate an error condition. */ 1720 } 1721 1722 static bfd_reloc_code_real_type 1723 handle_lo16 (const struct v850_operand *operand, const char **errmsg) 1724 { 1725 if (operand == NULL) 1726 return BFD_RELOC_LO16; 1727 1728 if (operand->default_reloc == BFD_RELOC_LO16) 1729 return BFD_RELOC_LO16; 1730 1731 if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET) 1732 return BFD_RELOC_V850_LO16_SPLIT_OFFSET; 1733 1734 if (operand->default_reloc == BFD_RELOC_V850_16_S1) 1735 return BFD_RELOC_V850_LO16_S1; 1736 1737 if (operand->default_reloc == BFD_RELOC_16) 1738 return BFD_RELOC_LO16; 1739 1740 *errmsg = _("lo() relocation used on an instruction which does " 1741 "not support it"); 1742 return BFD_RELOC_64; /* Used to indicate an error condition. */ 1743 } 1744 1745 static bfd_reloc_code_real_type 1746 handle_ctoff (const struct v850_operand *operand, const char **errmsg) 1747 { 1748 if (operand == NULL) 1749 return BFD_RELOC_V850_CALLT_16_16_OFFSET; 1750 1751 if (operand->default_reloc == BFD_RELOC_V850_CALLT_6_7_OFFSET) 1752 return operand->default_reloc; 1753 1754 if (operand->default_reloc == BFD_RELOC_V850_16_S1) 1755 return BFD_RELOC_V850_CALLT_15_16_OFFSET; 1756 1757 if (operand->default_reloc == BFD_RELOC_16) 1758 return BFD_RELOC_V850_CALLT_16_16_OFFSET; 1759 1760 *errmsg = _("ctoff() relocation used on an instruction which does not support it"); 1761 return BFD_RELOC_64; /* Used to indicate an error condition. */ 1762 } 1763 1764 static bfd_reloc_code_real_type 1765 handle_sdaoff (const struct v850_operand *operand, const char **errmsg) 1766 { 1767 if (operand == NULL) 1768 return BFD_RELOC_V850_SDA_16_16_OFFSET; 1769 1770 if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET) 1771 return BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET; 1772 1773 if (operand->default_reloc == BFD_RELOC_16) 1774 return BFD_RELOC_V850_SDA_16_16_OFFSET; 1775 1776 if (operand->default_reloc == BFD_RELOC_V850_16_S1) 1777 return BFD_RELOC_V850_SDA_15_16_OFFSET; 1778 1779 *errmsg = _("sdaoff() relocation used on an instruction which does not support it"); 1780 return BFD_RELOC_64; /* Used to indicate an error condition. */ 1781 } 1782 1783 static bfd_reloc_code_real_type 1784 handle_zdaoff (const struct v850_operand *operand, const char **errmsg) 1785 { 1786 if (operand == NULL) 1787 return BFD_RELOC_V850_ZDA_16_16_OFFSET; 1788 1789 if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET) 1790 return BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET; 1791 1792 if (operand->default_reloc == BFD_RELOC_16) 1793 return BFD_RELOC_V850_ZDA_16_16_OFFSET; 1794 1795 if (operand->default_reloc == BFD_RELOC_V850_16_S1) 1796 return BFD_RELOC_V850_ZDA_15_16_OFFSET; 1797 1798 *errmsg = _("zdaoff() relocation used on an instruction which does not support it"); 1799 return BFD_RELOC_64; /* Used to indicate an error condition. */ 1800 } 1801 1802 static bfd_reloc_code_real_type 1803 handle_tdaoff (const struct v850_operand *operand, const char **errmsg) 1804 { 1805 if (operand == NULL) 1806 /* Data item, not an instruction. */ 1807 return BFD_RELOC_V850_TDA_16_16_OFFSET; 1808 1809 switch (operand->default_reloc) 1810 { 1811 /* sld.hu, operand: D5-4. */ 1812 case BFD_RELOC_V850_TDA_4_5_OFFSET: 1813 /* sld.bu, operand: D4. */ 1814 case BFD_RELOC_V850_TDA_4_4_OFFSET: 1815 /* sld.w/sst.w, operand: D8_6. */ 1816 case BFD_RELOC_V850_TDA_6_8_OFFSET: 1817 /* sld.h/sst.h, operand: D8_7. */ 1818 case BFD_RELOC_V850_TDA_7_8_OFFSET: 1819 /* sld.b/sst.b, operand: D7. */ 1820 case BFD_RELOC_V850_TDA_7_7_OFFSET: 1821 return operand->default_reloc; 1822 default: 1823 break; 1824 } 1825 1826 if (operand->default_reloc == BFD_RELOC_16 && operand->shift == 16) 1827 /* set1 & chums, operands: D16. */ 1828 return BFD_RELOC_V850_TDA_16_16_OFFSET; 1829 1830 *errmsg = _("tdaoff() relocation used on an instruction which does not support it"); 1831 /* Used to indicate an error condition. */ 1832 return BFD_RELOC_64; 1833 } 1834 1835 /* Warning: The code in this function relies upon the definitions 1836 in the v850_operands[] array (defined in opcodes/v850-opc.c) 1837 matching the hard coded values contained herein. */ 1838 1839 static bfd_reloc_code_real_type 1840 v850_reloc_prefix (const struct v850_operand *operand, const char **errmsg) 1841 { 1842 bfd_boolean paren_skipped = FALSE; 1843 1844 /* Skip leading opening parenthesis. */ 1845 if (*input_line_pointer == '(') 1846 { 1847 ++input_line_pointer; 1848 paren_skipped = TRUE; 1849 } 1850 1851 #define CHECK_(name, reloc) \ 1852 if (strncmp (input_line_pointer, name "(", strlen (name) + 1) == 0) \ 1853 { \ 1854 input_line_pointer += strlen (name); \ 1855 return reloc; \ 1856 } 1857 1858 CHECK_ ("hi0", handle_hi016(operand, errmsg) ); 1859 CHECK_ ("hi", handle_hi16(operand, errmsg) ); 1860 CHECK_ ("lo", handle_lo16 (operand, errmsg) ); 1861 CHECK_ ("sdaoff", handle_sdaoff (operand, errmsg)); 1862 CHECK_ ("zdaoff", handle_zdaoff (operand, errmsg)); 1863 CHECK_ ("tdaoff", handle_tdaoff (operand, errmsg)); 1864 CHECK_ ("hilo", BFD_RELOC_32); 1865 CHECK_ ("lo23", BFD_RELOC_V850_23); 1866 CHECK_ ("ctoff", handle_ctoff (operand, errmsg) ); 1867 1868 /* Restore skipped parenthesis. */ 1869 if (paren_skipped) 1870 --input_line_pointer; 1871 1872 return BFD_RELOC_UNUSED; 1873 } 1874 1875 /* Insert an operand value into an instruction. */ 1876 1877 static unsigned long 1878 v850_insert_operand (unsigned long insn, 1879 const struct v850_operand *operand, 1880 offsetT val, 1881 const char **errmsg) 1882 { 1883 if (operand->insert) 1884 { 1885 const char *message = NULL; 1886 1887 insn = operand->insert (insn, val, &message); 1888 if (message != NULL) 1889 { 1890 if ((operand->flags & V850_OPERAND_SIGNED) 1891 && ! warn_signed_overflows 1892 && v850_msg_is_out_of_range (message)) 1893 { 1894 /* Skip warning... */ 1895 } 1896 else if ((operand->flags & V850_OPERAND_SIGNED) == 0 1897 && ! warn_unsigned_overflows 1898 && v850_msg_is_out_of_range (message)) 1899 { 1900 /* Skip warning... */ 1901 } 1902 else 1903 { 1904 if (errmsg != NULL) 1905 *errmsg = message; 1906 } 1907 } 1908 } 1909 else if (operand->bits == -1 1910 || operand->flags & V850E_IMMEDIATE16 1911 || operand->flags & V850E_IMMEDIATE23 1912 || operand->flags & V850E_IMMEDIATE32) 1913 { 1914 abort (); 1915 } 1916 else 1917 { 1918 if (operand->bits < 32) 1919 { 1920 long min, max; 1921 1922 if ((operand->flags & V850_OPERAND_SIGNED) != 0) 1923 { 1924 if (! warn_signed_overflows) 1925 max = (1 << operand->bits) - 1; 1926 else 1927 max = (1 << (operand->bits - 1)) - 1; 1928 1929 min = -(1 << (operand->bits - 1)); 1930 } 1931 else 1932 { 1933 max = (1 << operand->bits) - 1; 1934 1935 if (! warn_unsigned_overflows) 1936 min = -(1 << (operand->bits - 1)); 1937 else 1938 min = 0; 1939 } 1940 1941 /* Some people write constants with the sign extension done by 1942 hand but only up to 32 bits. This shouldn't really be valid, 1943 but, to permit this code to assemble on a 64-bit host, we 1944 sign extend the 32-bit value to 64 bits if so doing makes the 1945 value valid. */ 1946 if (val > max 1947 && (offsetT) (val - 0x80000000 - 0x80000000) >= min 1948 && (offsetT) (val - 0x80000000 - 0x80000000) <= max) 1949 val = val - 0x80000000 - 0x80000000; 1950 1951 /* Similarly, people write expressions like ~(1<<15), and expect 1952 this to be OK for a 32-bit unsigned value. */ 1953 else if (val < min 1954 && (offsetT) (val + 0x80000000 + 0x80000000) >= min 1955 && (offsetT) (val + 0x80000000 + 0x80000000) <= max) 1956 val = val + 0x80000000 + 0x80000000; 1957 1958 else if (val < (offsetT) min || val > (offsetT) max) 1959 { 1960 char buf [128]; 1961 1962 /* Restore min and mix to expected values for decimal ranges. */ 1963 if ((operand->flags & V850_OPERAND_SIGNED) 1964 && ! warn_signed_overflows) 1965 max = (1 << (operand->bits - 1)) - 1; 1966 1967 if (! (operand->flags & V850_OPERAND_SIGNED) 1968 && ! warn_unsigned_overflows) 1969 min = 0; 1970 1971 sprintf (buf, _("operand out of range (%d is not between %d and %d)"), 1972 (int) val, (int) min, (int) max); 1973 *errmsg = buf; 1974 } 1975 1976 insn |= (((long) val & ((1 << operand->bits) - 1)) << operand->shift); 1977 } 1978 else 1979 { 1980 insn |= (((long) val) << operand->shift); 1981 } 1982 } 1983 1984 return insn; 1985 } 1986 1987 static char copy_of_instruction[128]; 1989 1990 void 1991 md_assemble (char *str) 1992 { 1993 char *s; 1994 char *start_of_operands; 1995 struct v850_opcode *opcode; 1996 struct v850_opcode *next_opcode; 1997 const unsigned char *opindex_ptr; 1998 int next_opindex; 1999 int relaxable = 0; 2000 unsigned long insn; 2001 unsigned long insn_size; 2002 char *f; 2003 int i; 2004 int match; 2005 bfd_boolean extra_data_after_insn = FALSE; 2006 unsigned extra_data_len = 0; 2007 unsigned long extra_data = 0; 2008 char *saved_input_line_pointer; 2009 char most_match_errmsg[1024]; 2010 int most_match_count = -1; 2011 2012 strncpy (copy_of_instruction, str, sizeof (copy_of_instruction) - 1); 2013 most_match_errmsg[0] = 0; 2014 2015 /* Get the opcode. */ 2016 for (s = str; *s != '\0' && ! ISSPACE (*s); s++) 2017 continue; 2018 2019 if (*s != '\0') 2020 *s++ = '\0'; 2021 2022 /* Find the first opcode with the proper name. */ 2023 opcode = (struct v850_opcode *) hash_find (v850_hash, str); 2024 if (opcode == NULL) 2025 { 2026 /* xgettext:c-format */ 2027 as_bad (_("Unrecognized opcode: `%s'"), str); 2028 ignore_rest_of_line (); 2029 return; 2030 } 2031 2032 str = s; 2033 while (ISSPACE (*str)) 2034 ++str; 2035 2036 start_of_operands = str; 2037 2038 saved_input_line_pointer = input_line_pointer; 2039 2040 for (;;) 2041 { 2042 const char *errmsg = NULL; 2043 const char *warningmsg = NULL; 2044 2045 match = 0; 2046 opindex_ptr = opcode->operands; 2047 2048 if (no_stld23) 2049 { 2050 if ((strncmp (opcode->name, "st.", 3) == 0 2051 && v850_operands[opcode->operands[1]].bits == 23) 2052 || (strncmp (opcode->name, "ld.", 3) == 0 2053 && v850_operands[opcode->operands[0]].bits == 23)) 2054 { 2055 errmsg = _("st/ld offset 23 instruction was disabled ."); 2056 goto error; 2057 } 2058 } 2059 2060 if ((opcode->processors & processor_mask & PROCESSOR_MASK) == 0 2061 || (((opcode->processors & ~PROCESSOR_MASK) != 0) 2062 && ((opcode->processors & processor_mask & ~PROCESSOR_MASK) == 0))) 2063 { 2064 errmsg = _("Target processor does not support this instruction."); 2065 goto error; 2066 } 2067 2068 relaxable = 0; 2069 fc = 0; 2070 next_opindex = 0; 2071 insn = opcode->opcode; 2072 extra_data_len = 0; 2073 extra_data_after_insn = FALSE; 2074 2075 input_line_pointer = str = start_of_operands; 2076 2077 for (opindex_ptr = opcode->operands; *opindex_ptr != 0; opindex_ptr++) 2078 { 2079 const struct v850_operand *operand; 2080 char *hold; 2081 expressionS ex; 2082 bfd_reloc_code_real_type reloc; 2083 2084 if (next_opindex == 0) 2085 operand = &v850_operands[*opindex_ptr]; 2086 else 2087 { 2088 operand = &v850_operands[next_opindex]; 2089 next_opindex = 0; 2090 } 2091 2092 errmsg = NULL; 2093 2094 while (*str == ' ') 2095 ++str; 2096 2097 if (operand->flags & V850_OPERAND_BANG 2098 && *str == '!') 2099 ++str; 2100 else if (operand->flags & V850_OPERAND_PERCENT 2101 && *str == '%') 2102 ++str; 2103 2104 if (*str == ',' || *str == '[' || *str == ']') 2105 ++str; 2106 2107 while (*str == ' ') 2108 ++str; 2109 2110 if (operand->flags & V850_OPERAND_RELAX) 2111 relaxable = 1; 2112 2113 /* Gather the operand. */ 2114 hold = input_line_pointer; 2115 input_line_pointer = str; 2116 2117 /* lo(), hi(), hi0(), etc... */ 2118 if ((reloc = v850_reloc_prefix (operand, &errmsg)) != BFD_RELOC_UNUSED) 2119 { 2120 /* This is a fake reloc, used to indicate an error condition. */ 2121 if (reloc == BFD_RELOC_64) 2122 { 2123 /* match = 1; */ 2124 goto error; 2125 } 2126 2127 expression (&ex); 2128 2129 if (ex.X_op == O_constant) 2130 { 2131 switch (reloc) 2132 { 2133 case BFD_RELOC_V850_ZDA_16_16_OFFSET: 2134 case BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET: 2135 case BFD_RELOC_V850_ZDA_15_16_OFFSET: 2136 /* To cope with "not1 7, zdaoff(0xfffff006)[r0]" 2137 and the like. */ 2138 /* Fall through. */ 2139 2140 case BFD_RELOC_LO16: 2141 case BFD_RELOC_V850_LO16_S1: 2142 case BFD_RELOC_V850_LO16_SPLIT_OFFSET: 2143 { 2144 /* Truncate, then sign extend the value. */ 2145 ex.X_add_number = SEXT16 (ex.X_add_number); 2146 break; 2147 } 2148 2149 case BFD_RELOC_HI16: 2150 { 2151 /* Truncate, then sign extend the value. */ 2152 ex.X_add_number = SEXT16 (ex.X_add_number >> 16); 2153 break; 2154 } 2155 2156 case BFD_RELOC_HI16_S: 2157 { 2158 /* Truncate, then sign extend the value. */ 2159 int temp = (ex.X_add_number >> 16) & 0xffff; 2160 2161 temp += (ex.X_add_number >> 15) & 1; 2162 2163 ex.X_add_number = SEXT16 (temp); 2164 break; 2165 } 2166 2167 case BFD_RELOC_V850_23: 2168 if ((operand->flags & V850E_IMMEDIATE23) == 0) 2169 { 2170 errmsg = _("immediate operand is too large"); 2171 goto error; 2172 } 2173 break; 2174 2175 case BFD_RELOC_32: 2176 case BFD_RELOC_V850_32_ABS: 2177 case BFD_RELOC_V850_32_PCREL: 2178 if ((operand->flags & V850E_IMMEDIATE32) == 0) 2179 { 2180 errmsg = _("immediate operand is too large"); 2181 goto error; 2182 } 2183 2184 break; 2185 2186 default: 2187 fprintf (stderr, "reloc: %d\n", reloc); 2188 as_bad (_("AAARG -> unhandled constant reloc")); 2189 break; 2190 } 2191 2192 if (operand->flags & V850E_IMMEDIATE32) 2193 { 2194 extra_data_after_insn = TRUE; 2195 extra_data_len = 4; 2196 extra_data = 0; 2197 } 2198 else if (operand->flags & V850E_IMMEDIATE23) 2199 { 2200 if (reloc != BFD_RELOC_V850_23) 2201 { 2202 errmsg = _("immediate operand is too large"); 2203 goto error; 2204 } 2205 extra_data_after_insn = TRUE; 2206 extra_data_len = 2; 2207 extra_data = 0; 2208 } 2209 else if ((operand->flags & V850E_IMMEDIATE16) 2210 || (operand->flags & V850E_IMMEDIATE16HI)) 2211 { 2212 if (operand->flags & V850E_IMMEDIATE16HI 2213 && reloc != BFD_RELOC_HI16 2214 && reloc != BFD_RELOC_HI16_S) 2215 { 2216 errmsg = _("immediate operand is too large"); 2217 goto error; 2218 } 2219 else if (operand->flags & V850E_IMMEDIATE16 2220 && reloc != BFD_RELOC_LO16) 2221 { 2222 errmsg = _("immediate operand is too large"); 2223 goto error; 2224 } 2225 2226 extra_data_after_insn = TRUE; 2227 extra_data_len = 2; 2228 extra_data = 0; 2229 } 2230 2231 if (fc > MAX_INSN_FIXUPS) 2232 as_fatal (_("too many fixups")); 2233 2234 fixups[fc].exp = ex; 2235 fixups[fc].opindex = *opindex_ptr; 2236 fixups[fc].reloc = reloc; 2237 fc++; 2238 } 2239 else /* ex.X_op != O_constant. */ 2240 { 2241 if ((reloc == BFD_RELOC_32 2242 || reloc == BFD_RELOC_V850_32_ABS 2243 || reloc == BFD_RELOC_V850_32_PCREL) 2244 && operand->bits < 32) 2245 { 2246 errmsg = _("immediate operand is too large"); 2247 goto error; 2248 } 2249 else if (reloc == BFD_RELOC_V850_23 2250 && (operand->flags & V850E_IMMEDIATE23) == 0) 2251 { 2252 errmsg = _("immediate operand is too large"); 2253 goto error; 2254 } 2255 else if ((reloc == BFD_RELOC_HI16 2256 || reloc == BFD_RELOC_HI16_S) 2257 && operand->bits < 16) 2258 { 2259 errmsg = _("immediate operand is too large"); 2260 goto error; 2261 } 2262 2263 if (operand->flags & V850E_IMMEDIATE32) 2264 { 2265 extra_data_after_insn = TRUE; 2266 extra_data_len = 4; 2267 extra_data = 0; 2268 } 2269 else if (operand->flags & V850E_IMMEDIATE23) 2270 { 2271 if (reloc != BFD_RELOC_V850_23) 2272 { 2273 errmsg = _("immediate operand is too large"); 2274 goto error; 2275 } 2276 extra_data_after_insn = TRUE; 2277 extra_data_len = 2; 2278 extra_data = 0; 2279 } 2280 else if ((operand->flags & V850E_IMMEDIATE16) 2281 || (operand->flags & V850E_IMMEDIATE16HI)) 2282 { 2283 if (operand->flags & V850E_IMMEDIATE16HI 2284 && reloc != BFD_RELOC_HI16 2285 && reloc != BFD_RELOC_HI16_S) 2286 { 2287 errmsg = _("immediate operand is too large"); 2288 goto error; 2289 } 2290 else if (operand->flags & V850E_IMMEDIATE16 2291 && reloc != BFD_RELOC_LO16) 2292 { 2293 errmsg = _("immediate operand is too large"); 2294 goto error; 2295 } 2296 2297 extra_data_after_insn = TRUE; 2298 extra_data_len = 2; 2299 extra_data = 0; 2300 } 2301 2302 if (fc > MAX_INSN_FIXUPS) 2303 as_fatal (_("too many fixups")); 2304 2305 fixups[fc].exp = ex; 2306 fixups[fc].opindex = *opindex_ptr; 2307 fixups[fc].reloc = reloc; 2308 fc++; 2309 } 2310 } 2311 else if (operand->flags & V850E_IMMEDIATE16 2312 || operand->flags & V850E_IMMEDIATE16HI) 2313 { 2314 expression (&ex); 2315 2316 switch (ex.X_op) 2317 { 2318 case O_constant: 2319 if (operand->flags & V850E_IMMEDIATE16HI) 2320 { 2321 if (ex.X_add_number & 0xffff) 2322 { 2323 errmsg = _("constant too big to fit into instruction"); 2324 goto error; 2325 } 2326 2327 ex.X_add_number >>= 16; 2328 } 2329 if (operand->flags & V850E_IMMEDIATE16) 2330 { 2331 if (ex.X_add_number & 0xffff0000) 2332 { 2333 errmsg = _("constant too big to fit into instruction"); 2334 goto error; 2335 } 2336 } 2337 break; 2338 2339 case O_illegal: 2340 errmsg = _("illegal operand"); 2341 goto error; 2342 2343 case O_absent: 2344 errmsg = _("missing operand"); 2345 goto error; 2346 2347 default: 2348 if (fc >= MAX_INSN_FIXUPS) 2349 as_fatal (_("too many fixups")); 2350 2351 fixups[fc].exp = ex; 2352 fixups[fc].opindex = *opindex_ptr; 2353 fixups[fc].reloc = operand->default_reloc; 2354 ++fc; 2355 2356 ex.X_add_number = 0; 2357 break; 2358 } 2359 2360 extra_data_after_insn = TRUE; 2361 extra_data_len = 2; 2362 extra_data = ex.X_add_number; 2363 } 2364 else if (operand->flags & V850E_IMMEDIATE23) 2365 { 2366 expression (&ex); 2367 2368 switch (ex.X_op) 2369 { 2370 case O_constant: 2371 break; 2372 2373 case O_illegal: 2374 errmsg = _("illegal operand"); 2375 goto error; 2376 2377 case O_absent: 2378 errmsg = _("missing operand"); 2379 goto error; 2380 2381 default: 2382 break; 2383 } 2384 2385 if (fc >= MAX_INSN_FIXUPS) 2386 as_fatal (_("too many fixups")); 2387 2388 fixups[fc].exp = ex; 2389 fixups[fc].opindex = *opindex_ptr; 2390 fixups[fc].reloc = operand->default_reloc; 2391 ++fc; 2392 2393 extra_data_after_insn = TRUE; 2394 extra_data_len = 2; 2395 extra_data = 0; 2396 } 2397 else if (operand->flags & V850E_IMMEDIATE32) 2398 { 2399 expression (&ex); 2400 2401 switch (ex.X_op) 2402 { 2403 case O_constant: 2404 if ((operand->default_reloc == BFD_RELOC_V850_32_ABS 2405 || operand->default_reloc == BFD_RELOC_V850_32_PCREL) 2406 && (ex.X_add_number & 1)) 2407 { 2408 errmsg = _("odd number cannot be used here"); 2409 goto error; 2410 } 2411 break; 2412 2413 case O_illegal: 2414 errmsg = _("illegal operand"); 2415 goto error; 2416 2417 case O_absent: 2418 errmsg = _("missing operand"); 2419 goto error; 2420 2421 default: 2422 if (fc >= MAX_INSN_FIXUPS) 2423 as_fatal (_("too many fixups")); 2424 2425 fixups[fc].exp = ex; 2426 fixups[fc].opindex = *opindex_ptr; 2427 fixups[fc].reloc = operand->default_reloc; 2428 ++fc; 2429 2430 ex.X_add_number = 0; 2431 break; 2432 } 2433 2434 extra_data_after_insn = TRUE; 2435 extra_data_len = 4; 2436 extra_data = ex.X_add_number; 2437 } 2438 else if (operand->flags & V850E_OPERAND_REG_LIST) 2439 { 2440 errmsg = parse_register_list (&insn, operand); 2441 2442 if (errmsg) 2443 goto error; 2444 } 2445 else 2446 { 2447 errmsg = NULL; 2448 2449 if ((operand->flags & V850_OPERAND_REG) != 0) 2450 { 2451 if (!register_name (&ex)) 2452 { 2453 errmsg = _("invalid register name"); 2454 } 2455 2456 if ((operand->flags & V850_NOT_R0) 2457 && ex.X_add_number == 0) 2458 { 2459 errmsg = _("register r0 cannot be used here"); 2460 } 2461 2462 if (operand->flags & V850_REG_EVEN) 2463 { 2464 if (ex.X_add_number % 2) 2465 errmsg = _("odd register cannot be used here"); 2466 ex.X_add_number = ex.X_add_number / 2; 2467 } 2468 2469 } 2470 else if ((operand->flags & V850_OPERAND_SRG) != 0) 2471 { 2472 if (!system_register_name (&ex, TRUE)) 2473 { 2474 errmsg = _("invalid system register name"); 2475 } 2476 } 2477 else if ((operand->flags & V850_OPERAND_EP) != 0) 2478 { 2479 char *start = input_line_pointer; 2480 char c = get_symbol_end (); 2481 2482 if (strcmp (start, "ep") != 0 && strcmp (start, "r30") != 0) 2483 { 2484 /* Put things back the way we found them. */ 2485 *input_line_pointer = c; 2486 input_line_pointer = start; 2487 errmsg = _("expected EP register"); 2488 goto error; 2489 } 2490 2491 *input_line_pointer = c; 2492 str = input_line_pointer; 2493 input_line_pointer = hold; 2494 2495 while (*str == ' ' || *str == ',' 2496 || *str == '[' || *str == ']') 2497 ++str; 2498 continue; 2499 } 2500 else if ((operand->flags & V850_OPERAND_CC) != 0) 2501 { 2502 if (!cc_name (&ex, TRUE)) 2503 { 2504 errmsg = _("invalid condition code name"); 2505 } 2506 2507 if ((operand->flags & V850_NOT_SA) 2508 && ex.X_add_number == COND_SA_NUM) 2509 { 2510 errmsg = _("condition sa cannot be used here"); 2511 } 2512 } 2513 else if ((operand->flags & V850_OPERAND_FLOAT_CC) != 0) 2514 { 2515 if (!float_cc_name (&ex, TRUE)) 2516 { 2517 errmsg = _("invalid condition code name"); 2518 } 2519 } 2520 else if ((register_name (&ex) 2521 && (operand->flags & V850_OPERAND_REG) == 0)) 2522 { 2523 char c; 2524 int exists = 0; 2525 2526 /* It is possible that an alias has been defined that 2527 matches a register name. For example the code may 2528 include a ".set ZERO, 0" directive, which matches 2529 the register name "zero". Attempt to reparse the 2530 field as an expression, and only complain if we 2531 cannot generate a constant. */ 2532 2533 input_line_pointer = str; 2534 2535 c = get_symbol_end (); 2536 2537 if (symbol_find (str) != NULL) 2538 exists = 1; 2539 2540 *input_line_pointer = c; 2541 input_line_pointer = str; 2542 2543 expression (&ex); 2544 2545 if (ex.X_op != O_constant) 2546 { 2547 /* If this register is actually occurring too early on 2548 the parsing of the instruction, (because another 2549 field is missing) then report this. */ 2550 if (opindex_ptr[1] != 0 2551 && ((v850_operands[opindex_ptr[1]].flags 2552 & V850_OPERAND_REG) 2553 ||(v850_operands[opindex_ptr[1]].flags 2554 & V850_OPERAND_VREG))) 2555 errmsg = _("syntax error: value is missing before the register name"); 2556 else 2557 errmsg = _("syntax error: register not expected"); 2558 2559 /* If we created a symbol in the process of this 2560 test then delete it now, so that it will not 2561 be output with the real symbols... */ 2562 if (exists == 0 2563 && ex.X_op == O_symbol) 2564 symbol_remove (ex.X_add_symbol, 2565 &symbol_rootP, &symbol_lastP); 2566 } 2567 } 2568 else if (system_register_name (&ex, FALSE) 2569 && (operand->flags & V850_OPERAND_SRG) == 0) 2570 { 2571 errmsg = _("syntax error: system register not expected"); 2572 } 2573 else if (cc_name (&ex, FALSE) 2574 && (operand->flags & V850_OPERAND_CC) == 0) 2575 { 2576 errmsg = _("syntax error: condition code not expected"); 2577 } 2578 else if (float_cc_name (&ex, FALSE) 2579 && (operand->flags & V850_OPERAND_FLOAT_CC) == 0) 2580 { 2581 errmsg = _("syntax error: condition code not expected"); 2582 } 2583 else 2584 { 2585 expression (&ex); 2586 2587 if ((operand->flags & V850_NOT_IMM0) 2588 && ex.X_op == O_constant 2589 && ex.X_add_number == 0) 2590 { 2591 errmsg = _("immediate 0 cannot be used here"); 2592 } 2593 2594 /* Special case: 2595 If we are assembling a MOV/JARL/JR instruction and the immediate 2596 value does not fit into the bits available then create a 2597 fake error so that the next MOV/JARL/JR instruction will be 2598 selected. This one has a 32 bit immediate field. */ 2599 2600 if ((strcmp (opcode->name, "mov") == 0 2601 || strcmp (opcode->name, "jarl") == 0 2602 || strcmp (opcode->name, "jr") == 0) 2603 && ex.X_op == O_constant 2604 && (ex.X_add_number < (-(1 << (operand->bits - 1))) 2605 || ex.X_add_number > ((1 << (operand->bits - 1)) - 1))) 2606 { 2607 errmsg = _("immediate operand is too large"); 2608 } 2609 2610 if ((strcmp (opcode->name, "jarl") == 0 2611 || strcmp (opcode->name, "jr") == 0) 2612 && ex.X_op != O_constant 2613 && operand->bits != default_disp_size) 2614 { 2615 errmsg = _("immediate operand is not match"); 2616 } 2617 } 2618 2619 if (errmsg) 2620 goto error; 2621 2622 switch (ex.X_op) 2623 { 2624 case O_illegal: 2625 errmsg = _("illegal operand"); 2626 goto error; 2627 case O_absent: 2628 errmsg = _("missing operand"); 2629 goto error; 2630 case O_register: 2631 if ((operand->flags 2632 & (V850_OPERAND_REG | V850_OPERAND_SRG | V850_OPERAND_VREG)) == 0) 2633 { 2634 errmsg = _("invalid operand"); 2635 goto error; 2636 } 2637 2638 insn = v850_insert_operand (insn, operand, 2639 ex.X_add_number, 2640 &warningmsg); 2641 2642 break; 2643 2644 case O_constant: 2645 insn = v850_insert_operand (insn, operand, ex.X_add_number, 2646 &warningmsg); 2647 break; 2648 2649 default: 2650 /* We need to generate a fixup for this expression. */ 2651 if (fc >= MAX_INSN_FIXUPS) 2652 as_fatal (_("too many fixups")); 2653 2654 fixups[fc].exp = ex; 2655 fixups[fc].opindex = *opindex_ptr; 2656 fixups[fc].reloc = BFD_RELOC_UNUSED; 2657 ++fc; 2658 break; 2659 } 2660 } 2661 2662 str = input_line_pointer; 2663 input_line_pointer = hold; 2664 2665 while (*str == ' ' || *str == ',' || *str == '[' || *str == ']' 2666 || *str == ')') 2667 ++str; 2668 } 2669 2670 while (ISSPACE (*str)) 2671 ++str; 2672 2673 if (*str == '\0') 2674 match = 1; 2675 2676 error: 2677 if (match == 0) 2678 { 2679 if ((opindex_ptr - opcode->operands) >= most_match_count) 2680 { 2681 most_match_count = opindex_ptr - opcode->operands; 2682 if (errmsg != NULL) 2683 strncpy (most_match_errmsg, errmsg, sizeof (most_match_errmsg)-1); 2684 } 2685 2686 next_opcode = opcode + 1; 2687 if (next_opcode->name != NULL 2688 && strcmp (next_opcode->name, opcode->name) == 0) 2689 { 2690 opcode = next_opcode; 2691 2692 /* Skip versions that are not supported by the target 2693 processor. */ 2694 if ((opcode->processors & processor_mask) == 0) 2695 goto error; 2696 2697 continue; 2698 } 2699 2700 if (most_match_errmsg[0] == 0) 2701 /* xgettext:c-format. */ 2702 as_bad (_("junk at end of line: `%s'"), str); 2703 else 2704 as_bad ("%s: %s", copy_of_instruction, most_match_errmsg); 2705 2706 if (*input_line_pointer == ']') 2707 ++input_line_pointer; 2708 2709 ignore_rest_of_line (); 2710 input_line_pointer = saved_input_line_pointer; 2711 return; 2712 } 2713 2714 if (warningmsg != NULL) 2715 as_warn ("%s", warningmsg); 2716 break; 2717 } 2718 2719 input_line_pointer = str; 2720 2721 /* Tie dwarf2 debug info to the address at the start of the insn. 2722 We can't do this after the insn has been output as the current 2723 frag may have been closed off. eg. by frag_var. */ 2724 dwarf2_emit_insn (0); 2725 2726 /* Write out the instruction. */ 2727 2728 if (relaxable && fc > 0) 2729 { 2730 insn_size = 2; 2731 fc = 0; 2732 2733 if (strcmp (opcode->name, "br") == 0 2734 || strcmp (opcode->name, "jbr") == 0) 2735 { 2736 if ((processor_mask & PROCESSOR_V850E2_ALL) == 0 || default_disp_size == 22) 2737 { 2738 f = frag_var (rs_machine_dependent, 4, 2, SUBYPTE_UNCOND_9_22, 2739 fixups[0].exp.X_add_symbol, 2740 fixups[0].exp.X_add_number, 2741 (char *)(size_t) fixups[0].opindex); 2742 md_number_to_chars (f, insn, insn_size); 2743 md_number_to_chars (f + 2, 0, 2); 2744 } 2745 else 2746 { 2747 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_UNCOND_9_22_32, 2748 fixups[0].exp.X_add_symbol, 2749 fixups[0].exp.X_add_number, 2750 (char *)(size_t) fixups[0].opindex); 2751 md_number_to_chars (f, insn, insn_size); 2752 md_number_to_chars (f + 2, 0, 4); 2753 } 2754 } 2755 else /* b<cond>, j<cond>. */ 2756 { 2757 if (default_disp_size == 22 2758 || (processor_mask & PROCESSOR_V850E2_ALL) == 0) 2759 { 2760 if (processor_mask & PROCESSOR_V850E2V3 && !no_bcond17) 2761 { 2762 if (strcmp (opcode->name, "bsa") == 0) 2763 { 2764 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_SA_9_17_22, 2765 fixups[0].exp.X_add_symbol, 2766 fixups[0].exp.X_add_number, 2767 (char *)(size_t) fixups[0].opindex); 2768 md_number_to_chars (f, insn, insn_size); 2769 md_number_to_chars (f + 2, 0, 6); 2770 } 2771 else 2772 { 2773 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_COND_9_17_22, 2774 fixups[0].exp.X_add_symbol, 2775 fixups[0].exp.X_add_number, 2776 (char *)(size_t) fixups[0].opindex); 2777 md_number_to_chars (f, insn, insn_size); 2778 md_number_to_chars (f + 2, 0, 4); 2779 } 2780 } 2781 else 2782 { 2783 if (strcmp (opcode->name, "bsa") == 0) 2784 { 2785 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_SA_9_22, 2786 fixups[0].exp.X_add_symbol, 2787 fixups[0].exp.X_add_number, 2788 (char *)(size_t) fixups[0].opindex); 2789 md_number_to_chars (f, insn, insn_size); 2790 md_number_to_chars (f + 2, 0, 6); 2791 } 2792 else 2793 { 2794 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_COND_9_22, 2795 fixups[0].exp.X_add_symbol, 2796 fixups[0].exp.X_add_number, 2797 (char *)(size_t) fixups[0].opindex); 2798 md_number_to_chars (f, insn, insn_size); 2799 md_number_to_chars (f + 2, 0, 4); 2800 } 2801 } 2802 } 2803 else 2804 { 2805 if (processor_mask & PROCESSOR_V850E2V3 && !no_bcond17) 2806 { 2807 if (strcmp (opcode->name, "bsa") == 0) 2808 { 2809 f = frag_var (rs_machine_dependent, 10, 8, SUBYPTE_SA_9_17_22_32, 2810 fixups[0].exp.X_add_symbol, 2811 fixups[0].exp.X_add_number, 2812 (char *)(size_t) fixups[0].opindex); 2813 md_number_to_chars (f, insn, insn_size); 2814 md_number_to_chars (f + 2, 0, 8); 2815 } 2816 else 2817 { 2818 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_COND_9_17_22_32, 2819 fixups[0].exp.X_add_symbol, 2820 fixups[0].exp.X_add_number, 2821 (char *)(size_t) fixups[0].opindex); 2822 md_number_to_chars (f, insn, insn_size); 2823 md_number_to_chars (f + 2, 0, 6); 2824 } 2825 } 2826 else 2827 { 2828 if (strcmp (opcode->name, "bsa") == 0) 2829 { 2830 f = frag_var (rs_machine_dependent, 10, 8, SUBYPTE_SA_9_22_32, 2831 fixups[0].exp.X_add_symbol, 2832 fixups[0].exp.X_add_number, 2833 (char *)(size_t) fixups[0].opindex); 2834 md_number_to_chars (f, insn, insn_size); 2835 md_number_to_chars (f + 2, 0, 8); 2836 } 2837 else 2838 { 2839 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_COND_9_22_32, 2840 fixups[0].exp.X_add_symbol, 2841 fixups[0].exp.X_add_number, 2842 (char *)(size_t) fixups[0].opindex); 2843 md_number_to_chars (f, insn, insn_size); 2844 md_number_to_chars (f + 2, 0, 6); 2845 } 2846 } 2847 } 2848 } 2849 } 2850 else 2851 { 2852 /* Four byte insns have an opcode with the two high bits on. */ 2853 if ((insn & 0x0600) == 0x0600) 2854 insn_size = 4; 2855 else 2856 insn_size = 2; 2857 2858 /* Special case: 32 bit MOV. */ 2859 if ((insn & 0xffe0) == 0x0620) 2860 insn_size = 2; 2861 2862 /* Special case: 32 bit JARL,JMP,JR. */ 2863 if ((insn & 0x1ffe0) == 0x2e0 /* JARL. */ 2864 || (insn & 0x1ffe0) == 0x6e0 /* JMP. */ 2865 || (insn & 0x1ffff) == 0x2e0) /* JR. */ 2866 insn_size = 2; 2867 2868 f = frag_more (insn_size); 2869 md_number_to_chars (f, insn, insn_size); 2870 2871 if (extra_data_after_insn) 2872 { 2873 f = frag_more (extra_data_len); 2874 md_number_to_chars (f, extra_data, extra_data_len); 2875 2876 extra_data_after_insn = FALSE; 2877 } 2878 } 2879 2880 /* Create any fixups. At this point we do not use a 2881 bfd_reloc_code_real_type, but instead just use the 2882 BFD_RELOC_UNUSED plus the operand index. This lets us easily 2883 handle fixups for any operand type, although that is admittedly 2884 not a very exciting feature. We pick a BFD reloc type in 2885 md_apply_fix. */ 2886 for (i = 0; i < fc; i++) 2887 { 2888 const struct v850_operand *operand; 2889 bfd_reloc_code_real_type reloc; 2890 2891 operand = &v850_operands[fixups[i].opindex]; 2892 2893 reloc = fixups[i].reloc; 2894 2895 if (reloc != BFD_RELOC_UNUSED) 2896 { 2897 reloc_howto_type *reloc_howto = 2898 bfd_reloc_type_lookup (stdoutput, reloc); 2899 int size; 2900 int address; 2901 fixS *fixP; 2902 2903 if (!reloc_howto) 2904 abort (); 2905 2906 size = bfd_get_reloc_size (reloc_howto); 2907 2908 /* XXX This will abort on an R_V850_8 reloc - 2909 is this reloc actually used? */ 2910 if (size != 2 && size != 4) 2911 abort (); 2912 2913 if (extra_data_len == 0) 2914 { 2915 address = (f - frag_now->fr_literal) + insn_size - size; 2916 } 2917 else 2918 { 2919 address = (f - frag_now->fr_literal) + extra_data_len - size; 2920 } 2921 2922 if ((operand->flags & V850E_IMMEDIATE32) && (operand->flags & V850_PCREL)) 2923 { 2924 fixups[i].exp.X_add_number += 2; 2925 } 2926 else if (operand->default_reloc == BFD_RELOC_V850_16_PCREL) 2927 { 2928 fixups[i].exp.X_add_number += 2; 2929 address += 2; 2930 } 2931 2932 /* fprintf (stderr, "0x%x %d %ld\n", address, size, fixups[i].exp.X_add_number); */ 2933 fixP = fix_new_exp (frag_now, address, size, 2934 &fixups[i].exp, 2935 reloc_howto->pc_relative, 2936 reloc); 2937 2938 fixP->tc_fix_data = (void *) operand; 2939 2940 switch (reloc) 2941 { 2942 case BFD_RELOC_LO16: 2943 case BFD_RELOC_V850_LO16_S1: 2944 case BFD_RELOC_V850_LO16_SPLIT_OFFSET: 2945 case BFD_RELOC_HI16: 2946 case BFD_RELOC_HI16_S: 2947 fixP->fx_no_overflow = 1; 2948 break; 2949 default: 2950 break; 2951 } 2952 } 2953 else 2954 { 2955 fix_new_exp (frag_now, 2956 f - frag_now->fr_literal, 4, 2957 & fixups[i].exp, 2958 (operand->flags & V850_PCREL) != 0, 2959 (bfd_reloc_code_real_type) (fixups[i].opindex 2960 + (int) BFD_RELOC_UNUSED)); 2961 } 2962 } 2963 2964 input_line_pointer = saved_input_line_pointer; 2965 } 2966 2967 /* If while processing a fixup, a reloc really needs to be created 2968 then it is done here. */ 2969 2970 arelent * 2971 tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp) 2972 { 2973 arelent *reloc; 2974 2975 reloc = xmalloc (sizeof (arelent)); 2976 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); 2977 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 2978 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 2979 2980 if ( fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY 2981 || fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT 2982 || fixp->fx_r_type == BFD_RELOC_V850_LONGCALL 2983 || fixp->fx_r_type == BFD_RELOC_V850_LONGJUMP 2984 || fixp->fx_r_type == BFD_RELOC_V850_ALIGN) 2985 reloc->addend = fixp->fx_offset; 2986 else 2987 { 2988 #if 0 2989 if (fixp->fx_r_type == BFD_RELOC_32 2990 && fixp->fx_pcrel) 2991 fixp->fx_r_type = BFD_RELOC_32_PCREL; 2992 #endif 2993 2994 reloc->addend = fixp->fx_addnumber; 2995 } 2996 2997 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); 2998 2999 if (reloc->howto == NULL) 3000 { 3001 as_bad_where (fixp->fx_file, fixp->fx_line, 3002 /* xgettext:c-format */ 3003 _("reloc %d not supported by object file format"), 3004 (int) fixp->fx_r_type); 3005 3006 xfree (reloc); 3007 3008 return NULL; 3009 } 3010 3011 return reloc; 3012 } 3013 3014 void 3015 v850_handle_align (fragS * frag) 3016 { 3017 if (v850_relax 3018 && frag->fr_type == rs_align 3019 && frag->fr_address + frag->fr_fix > 0 3020 && frag->fr_offset > 1 3021 && now_seg != bss_section 3022 && now_seg != v850_seg_table[SBSS_SECTION].s 3023 && now_seg != v850_seg_table[TBSS_SECTION].s 3024 && now_seg != v850_seg_table[ZBSS_SECTION].s) 3025 fix_new (frag, frag->fr_fix, 2, & abs_symbol, frag->fr_offset, 0, 3026 BFD_RELOC_V850_ALIGN); 3027 } 3028 3029 /* Return current size of variable part of frag. */ 3030 3031 int 3032 md_estimate_size_before_relax (fragS *fragp, asection *seg ATTRIBUTE_UNUSED) 3033 { 3034 if (fragp->fr_subtype >= sizeof (md_relax_table) / sizeof (md_relax_table[0])) 3035 abort (); 3036 3037 return md_relax_table[fragp->fr_subtype].rlx_length; 3038 } 3039 3040 long 3041 v850_pcrel_from_section (fixS *fixp, segT section) 3042 { 3043 /* If the symbol is undefined, or in a section other than our own, 3044 or it is weak (in which case it may well be in another section, 3045 then let the linker figure it out. */ 3046 if (fixp->fx_addsy != (symbolS *) NULL 3047 && (! S_IS_DEFINED (fixp->fx_addsy) 3048 || S_IS_WEAK (fixp->fx_addsy) 3049 || (S_GET_SEGMENT (fixp->fx_addsy) != section))) 3050 return 0; 3051 3052 return fixp->fx_frag->fr_address + fixp->fx_where; 3053 } 3054 3055 void 3056 md_apply_fix (fixS *fixP, valueT *valueP, segT seg ATTRIBUTE_UNUSED) 3057 { 3058 valueT value = * valueP; 3059 char *where; 3060 3061 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 3062 || fixP->fx_r_type == BFD_RELOC_V850_LONGCALL 3063 || fixP->fx_r_type == BFD_RELOC_V850_LONGJUMP 3064 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 3065 { 3066 fixP->fx_done = 0; 3067 return; 3068 } 3069 3070 if (fixP->fx_addsy == (symbolS *) NULL) 3071 fixP->fx_addnumber = value, 3072 fixP->fx_done = 1; 3073 3074 else if (fixP->fx_pcrel) 3075 fixP->fx_addnumber = fixP->fx_offset; 3076 3077 else 3078 { 3079 value = fixP->fx_offset; 3080 if (fixP->fx_subsy != (symbolS *) NULL) 3081 { 3082 if (S_GET_SEGMENT (fixP->fx_subsy) == absolute_section) 3083 value -= S_GET_VALUE (fixP->fx_subsy); 3084 else 3085 /* We don't actually support subtracting a symbol. */ 3086 as_bad_where (fixP->fx_file, fixP->fx_line, 3087 _("expression too complex")); 3088 } 3089 fixP->fx_addnumber = value; 3090 } 3091 3092 if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED) 3093 { 3094 int opindex; 3095 const struct v850_operand *operand; 3096 unsigned long insn; 3097 const char *errmsg = NULL; 3098 3099 opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED; 3100 operand = &v850_operands[opindex]; 3101 3102 /* Fetch the instruction, insert the fully resolved operand 3103 value, and stuff the instruction back again. 3104 3105 Note the instruction has been stored in little endian 3106 format! */ 3107 where = fixP->fx_frag->fr_literal + fixP->fx_where; 3108 3109 if (fixP->fx_size > 2) 3110 insn = bfd_getl32 ((unsigned char *) where); 3111 else 3112 insn = bfd_getl16 ((unsigned char *) where); 3113 3114 insn = v850_insert_operand (insn, operand, (offsetT) value, 3115 &errmsg); 3116 if (errmsg) 3117 as_warn_where (fixP->fx_file, fixP->fx_line, "%s", errmsg); 3118 3119 if (fixP->fx_size > 2) 3120 bfd_putl32 ((bfd_vma) insn, (unsigned char *) where); 3121 else 3122 bfd_putl16 ((bfd_vma) insn, (unsigned char *) where); 3123 3124 if (fixP->fx_done) 3125 /* Nothing else to do here. */ 3126 return; 3127 3128 /* Determine a BFD reloc value based on the operand information. 3129 We are only prepared to turn a few of the operands into relocs. */ 3130 3131 if (operand->default_reloc == BFD_RELOC_NONE) 3132 { 3133 as_bad_where (fixP->fx_file, fixP->fx_line, 3134 _("unresolved expression that must be resolved")); 3135 fixP->fx_done = 1; 3136 return; 3137 } 3138 3139 { 3140 fixP->fx_r_type = operand->default_reloc; 3141 if (operand->default_reloc == BFD_RELOC_V850_16_PCREL) 3142 { 3143 fixP->fx_where += 2; 3144 fixP->fx_size = 2; 3145 fixP->fx_addnumber += 2; 3146 } 3147 } 3148 } 3149 else if (fixP->fx_done) 3150 { 3151 /* We still have to insert the value into memory! */ 3152 where = fixP->fx_frag->fr_literal + fixP->fx_where; 3153 3154 if (fixP->tc_fix_data != NULL 3155 && ((struct v850_operand *) fixP->tc_fix_data)->insert != NULL) 3156 { 3157 const char * message = NULL; 3158 struct v850_operand * operand = (struct v850_operand *) fixP->tc_fix_data; 3159 unsigned long insn; 3160 3161 /* The variable "where" currently points at the exact point inside 3162 the insn where we need to insert the value. But we need to 3163 extract the entire insn so we probably need to move "where" 3164 back a few bytes. */ 3165 3166 if (fixP->fx_size == 2) 3167 where -= 2; 3168 else if (fixP->fx_size == 1) 3169 where -= 3; 3170 3171 insn = bfd_getl32 ((unsigned char *) where); 3172 3173 /* Use the operand's insertion procedure, if present, in order to 3174 make sure that the value is correctly stored in the insn. */ 3175 insn = operand->insert (insn, (offsetT) value, & message); 3176 /* Ignore message even if it is set. */ 3177 3178 bfd_putl32 ((bfd_vma) insn, (unsigned char *) where); 3179 } 3180 else 3181 { 3182 switch (fixP->fx_r_type) 3183 { 3184 case BFD_RELOC_V850_32_ABS: 3185 case BFD_RELOC_V850_32_PCREL: 3186 bfd_putl32 (value & 0xfffffffe, (unsigned char *) where); 3187 break; 3188 3189 case BFD_RELOC_32: 3190 bfd_putl32 (value, (unsigned char *) where); 3191 break; 3192 3193 case BFD_RELOC_V850_23: 3194 bfd_putl32 (((value & 0x7f) << 4) | ((value & 0x7fff80) << (16-7)) 3195 | (bfd_getl32 (where) & ~((0x7f << 4) | (0xffff << 16))), 3196 (unsigned char *) where); 3197 break; 3198 3199 case BFD_RELOC_16: 3200 case BFD_RELOC_HI16: 3201 case BFD_RELOC_HI16_S: 3202 case BFD_RELOC_LO16: 3203 case BFD_RELOC_V850_ZDA_16_16_OFFSET: 3204 case BFD_RELOC_V850_SDA_16_16_OFFSET: 3205 case BFD_RELOC_V850_TDA_16_16_OFFSET: 3206 case BFD_RELOC_V850_CALLT_16_16_OFFSET: 3207 bfd_putl16 (value & 0xffff, (unsigned char *) where); 3208 break; 3209 3210 case BFD_RELOC_8: 3211 *where = value & 0xff; 3212 break; 3213 3214 case BFD_RELOC_V850_9_PCREL: 3215 bfd_putl16 (((value & 0x1f0) << 7) | ((value & 0x0e) << 3) 3216 | (bfd_getl16 (where) & ~((0x1f0 << 7) | (0x0e << 3))), where); 3217 break; 3218 3219 case BFD_RELOC_V850_17_PCREL: 3220 bfd_putl32 (((value & 0x10000) >> (16 - 4)) | ((value & 0xfffe) << 16) 3221 | (bfd_getl32 (where) & ~((0x10000 >> (16 - 4)) | (0xfffe << 16))), where); 3222 break; 3223 3224 case BFD_RELOC_V850_16_PCREL: 3225 bfd_putl16 (-value & 0xfffe, (unsigned char *) where); 3226 break; 3227 3228 case BFD_RELOC_V850_22_PCREL: 3229 bfd_putl32 (((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16) 3230 | (bfd_getl32 (where) & ~((0xfffe << 16) | (0x3f0000 >> 16))), where); 3231 break; 3232 3233 case BFD_RELOC_V850_16_S1: 3234 case BFD_RELOC_V850_LO16_S1: 3235 case BFD_RELOC_V850_ZDA_15_16_OFFSET: 3236 case BFD_RELOC_V850_SDA_15_16_OFFSET: 3237 bfd_putl16 (value & 0xfffe, (unsigned char *) where); 3238 break; 3239 3240 case BFD_RELOC_V850_16_SPLIT_OFFSET: 3241 case BFD_RELOC_V850_LO16_SPLIT_OFFSET: 3242 case BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET: 3243 case BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET: 3244 bfd_putl32 (((value << 16) & 0xfffe0000) 3245 | ((value << 5) & 0x20) 3246 | (bfd_getl32 (where) & ~0xfffe0020), where); 3247 break; 3248 3249 case BFD_RELOC_V850_TDA_6_8_OFFSET: 3250 *where = (*where & ~0x7e) | ((value >> 1) & 0x7e); 3251 break; 3252 3253 case BFD_RELOC_V850_TDA_7_8_OFFSET: 3254 *where = (*where & ~0x7f) | ((value >> 1) & 0x7f); 3255 break; 3256 3257 case BFD_RELOC_V850_TDA_7_7_OFFSET: 3258 *where = (*where & ~0x7f) | (value & 0x7f); 3259 break; 3260 3261 case BFD_RELOC_V850_TDA_4_5_OFFSET: 3262 *where = (*where & ~0xf) | ((value >> 1) & 0xf); 3263 break; 3264 3265 case BFD_RELOC_V850_TDA_4_4_OFFSET: 3266 *where = (*where & ~0xf) | (value & 0xf); 3267 break; 3268 3269 case BFD_RELOC_V850_CALLT_6_7_OFFSET: 3270 *where = (*where & ~0x3f) | (value & 0x3f); 3271 break; 3272 3273 default: 3274 abort (); 3275 } 3276 } 3277 } 3278 } 3279 3280 /* Parse a cons expression. We have to handle hi(), lo(), etc 3281 on the v850. */ 3282 3283 void 3284 parse_cons_expression_v850 (expressionS *exp) 3285 { 3286 const char *errmsg; 3287 /* See if there's a reloc prefix like hi() we have to handle. */ 3288 hold_cons_reloc = v850_reloc_prefix (NULL, &errmsg); 3289 3290 /* Do normal expression parsing. */ 3291 expression (exp); 3292 } 3293 3294 /* Create a fixup for a cons expression. If parse_cons_expression_v850 3295 found a reloc prefix, then we use that reloc, else we choose an 3296 appropriate one based on the size of the expression. */ 3297 3298 void 3299 cons_fix_new_v850 (fragS *frag, 3300 int where, 3301 int size, 3302 expressionS *exp) 3303 { 3304 if (hold_cons_reloc == BFD_RELOC_UNUSED) 3305 { 3306 if (size == 4) 3307 hold_cons_reloc = BFD_RELOC_32; 3308 if (size == 2) 3309 hold_cons_reloc = BFD_RELOC_16; 3310 if (size == 1) 3311 hold_cons_reloc = BFD_RELOC_8; 3312 } 3313 3314 if (exp != NULL) 3315 fix_new_exp (frag, where, size, exp, 0, hold_cons_reloc); 3316 else 3317 fix_new (frag, where, size, NULL, 0, 0, hold_cons_reloc); 3318 3319 hold_cons_reloc = BFD_RELOC_UNUSED; 3320 } 3321 3322 bfd_boolean 3323 v850_fix_adjustable (fixS *fixP) 3324 { 3325 if (fixP->fx_addsy == NULL) 3326 return 1; 3327 3328 /* Don't adjust function names. */ 3329 if (S_IS_FUNCTION (fixP->fx_addsy)) 3330 return 0; 3331 3332 /* We need the symbol name for the VTABLE entries. */ 3333 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 3334 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 3335 return 0; 3336 3337 return 1; 3338 } 3339 3340 int 3341 v850_force_relocation (struct fix *fixP) 3342 { 3343 if (fixP->fx_r_type == BFD_RELOC_V850_LONGCALL 3344 || fixP->fx_r_type == BFD_RELOC_V850_LONGJUMP) 3345 return 1; 3346 3347 if (v850_relax 3348 && (fixP->fx_pcrel 3349 || fixP->fx_r_type == BFD_RELOC_V850_ALIGN 3350 || fixP->fx_r_type == BFD_RELOC_V850_9_PCREL 3351 || fixP->fx_r_type == BFD_RELOC_V850_16_PCREL 3352 || fixP->fx_r_type == BFD_RELOC_V850_17_PCREL 3353 || fixP->fx_r_type == BFD_RELOC_V850_22_PCREL 3354 || fixP->fx_r_type == BFD_RELOC_V850_32_PCREL 3355 || fixP->fx_r_type >= BFD_RELOC_UNUSED)) 3356 return 1; 3357 3358 return generic_force_reloc (fixP); 3359 } 3360
Indexes created Thu May 14 00:25:00 UTC 2026