tc-v850.c revision 1.1.1.9
1 /* tc-v850.c -- Assembler code for the NEC V850 2 Copyright (C) 1996-2025 Free Software Foundation, Inc. 3 4 This file is part of GAS, the GNU Assembler. 5 6 GAS is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GAS is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GAS; see the file COPYING. If not, write to 18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, 19 Boston, MA 02110-1301, USA. */ 20 21 #include "as.h" 22 #include "safe-ctype.h" 23 #include "subsegs.h" 24 #include "opcode/v850.h" 25 #include "dwarf2dbg.h" 26 27 /* Sign-extend a 16-bit number. */ 28 #define SEXT16(x) ((((x) & 0xffff) ^ (~0x7fff)) + 0x8000) 29 30 /* Set to TRUE if we want to be pedantic about signed overflows. */ 31 static bool warn_signed_overflows = false; 32 static bool warn_unsigned_overflows = false; 33 34 /* Non-zero if floating point insns are not being used. */ 35 static signed int soft_float = -1; 36 37 /* Indicates the target BFD machine number. */ 38 static int machine = -1; 39 40 41 /* Indicates the target BFD architecture. */ 42 enum bfd_architecture v850_target_arch = bfd_arch_v850_rh850; 43 const char * v850_target_format = "elf32-v850-rh850"; 44 static flagword v850_e_flags = 0; 45 46 /* Indicates the target processor(s) for the assemble. */ 47 static int processor_mask = 0; 48 49 /* Structure to hold information about predefined registers. */ 51 struct reg_name 52 { 53 const char *name; 54 int value; 55 unsigned int processors; 56 }; 57 58 /* Generic assembler global variables which must be defined by all 59 targets. */ 60 61 /* Characters which always start a comment. */ 62 const char comment_chars[] = "#"; 63 64 /* Characters which start a comment at the beginning of a line. */ 65 const char line_comment_chars[] = ";#"; 66 67 /* Characters which may be used to separate multiple commands on a 68 single line. */ 69 const char line_separator_chars[] = ";"; 70 71 /* Characters which are used to indicate an exponent in a floating 72 point number. */ 73 const char EXP_CHARS[] = "eE"; 74 75 /* Characters which mean that a number is a floating point constant, 76 as in 0d1.0. */ 77 const char FLT_CHARS[] = "dD"; 78 79 const relax_typeS md_relax_table[] = 81 { 82 /* Conditional branches.(V850/V850E, max 22bit) */ 83 #define SUBYPTE_COND_9_22 0 84 {0xfe, -0x100, 2, SUBYPTE_COND_9_22 + 1}, 85 {0x1ffffe + 2, -0x200000 + 2, 6, 0}, 86 /* Conditional branches.(V850/V850E, max 22bit) */ 87 #define SUBYPTE_SA_9_22 2 88 {0xfe, -0x100, 2, SUBYPTE_SA_9_22 + 1}, 89 {0x1ffffe + 4, -0x200000 + 4, 8, 0}, 90 /* Unconditional branches.(V850/V850E, max 22bit) */ 91 #define SUBYPTE_UNCOND_9_22 4 92 {0xfe, -0x100, 2, SUBYPTE_UNCOND_9_22 + 1}, 93 {0x1ffffe, -0x200000, 4, 0}, 94 /* Conditional branches.(V850E2, max 32bit) */ 95 #define SUBYPTE_COND_9_22_32 6 96 {0xfe, -0x100, 2, SUBYPTE_COND_9_22_32 + 1}, 97 {0x1fffff + 2, -0x200000 + 2, 6, SUBYPTE_COND_9_22_32 + 2}, 98 {0x7ffffffe, -0x80000000, 8, 0}, 99 /* Conditional branches.(V850E2, max 32bit) */ 100 #define SUBYPTE_SA_9_22_32 9 101 {0xfe, -0x100, 2, SUBYPTE_SA_9_22_32 + 1}, 102 {0x1ffffe + 4, -0x200000 + 4, 8, SUBYPTE_SA_9_22_32 + 2}, 103 {0x7ffffffe, -0x80000000, 10, 0}, 104 /* Unconditional branches.(V850E2, max 32bit) */ 105 #define SUBYPTE_UNCOND_9_22_32 12 106 {0xfe, -0x100, 2, SUBYPTE_UNCOND_9_22_32 + 1}, 107 {0x1ffffe, -0x200000, 4, SUBYPTE_UNCOND_9_22_32 + 2}, 108 {0x7ffffffe, -0x80000000, 6, 0}, 109 /* Conditional branches.(V850E2R max 22bit) */ 110 #define SUBYPTE_COND_9_17_22 15 111 {0xfe, -0x100, 2, SUBYPTE_COND_9_17_22 + 1}, 112 {0xfffe, -0x10000, 4, SUBYPTE_COND_9_17_22 + 2}, 113 {0x1ffffe + 2, -0x200000 + 2, 6, 0}, 114 /* Conditional branches.(V850E2R max 22bit) */ 115 #define SUBYPTE_SA_9_17_22 18 116 {0xfe, -0x100, 2, SUBYPTE_SA_9_17_22 + 1}, 117 {0xfffe, -0x10000, 4, SUBYPTE_SA_9_17_22 + 2}, 118 {0x1ffffe + 4, -0x200000 + 4, 8, 0}, 119 /* Conditional branches.(V850E2R max 32bit) */ 120 #define SUBYPTE_COND_9_17_22_32 21 121 {0xfe, -0x100, 2, SUBYPTE_COND_9_17_22_32 + 1}, 122 {0xfffe, -0x10000, 4, SUBYPTE_COND_9_17_22_32 + 2}, 123 {0x1ffffe + 2, -0x200000 + 2, 6, SUBYPTE_COND_9_17_22_32 + 3}, 124 {0x7ffffffe, -0x80000000, 8, 0}, 125 /* Conditional branches.(V850E2R max 32bit) */ 126 #define SUBYPTE_SA_9_17_22_32 25 127 {0xfe, -0x100, 2, SUBYPTE_SA_9_17_22_32 + 1}, 128 {0xfffe, -0x10000, 4, SUBYPTE_SA_9_17_22_32 + 2}, 129 {0x1ffffe + 4, -0x200000 + 4, 8, SUBYPTE_SA_9_17_22_32 + 3}, 130 {0x7ffffffe, -0x80000000, 10, 0}, 131 /* Loop. (V850E2V4_UP, max 22-bit). */ 132 #define SUBYPTE_LOOP_16_22 29 133 {0x0, -0x0fffe, 4, SUBYPTE_LOOP_16_22 + 1}, 134 {0x1ffffe + 2, -0x200000 + 2, 6, 0}, 135 }; 136 137 static int v850_relax = 0; 138 139 /* Default branch disp size 22 or 32. */ 140 static int default_disp_size = 22; 141 142 /* Default no using bcond17. */ 143 static int no_bcond17 = 0; 144 145 /* Default no using ld/st 23bit offset. */ 146 static int no_stld23 = 0; 147 148 /* Fixups. */ 149 #define MAX_INSN_FIXUPS 5 150 151 struct v850_fixup 152 { 153 expressionS exp; 154 int opindex; 155 bfd_reloc_code_real_type reloc; 156 }; 157 158 struct v850_fixup fixups[MAX_INSN_FIXUPS]; 159 static int fc; 160 161 struct v850_seg_entry 162 { 163 segT s; 164 const char *name; 165 flagword flags; 166 }; 167 168 struct v850_seg_entry v850_seg_table[] = 169 { 170 { NULL, ".sdata", 171 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS 172 | SEC_SMALL_DATA }, 173 { NULL, ".tdata", 174 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS }, 175 { NULL, ".zdata", 176 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS }, 177 { NULL, ".sbss", 178 SEC_ALLOC | SEC_SMALL_DATA }, 179 { NULL, ".tbss", 180 SEC_ALLOC }, 181 { NULL, ".zbss", 182 SEC_ALLOC}, 183 { NULL, ".rosdata", 184 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_DATA 185 | SEC_HAS_CONTENTS | SEC_SMALL_DATA }, 186 { NULL, ".rozdata", 187 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_DATA 188 | SEC_HAS_CONTENTS }, 189 { NULL, ".scommon", 190 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS 191 | SEC_SMALL_DATA | SEC_IS_COMMON }, 192 { NULL, ".tcommon", 193 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS 194 | SEC_IS_COMMON }, 195 { NULL, ".zcommon", 196 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS 197 | SEC_IS_COMMON }, 198 { NULL, ".call_table_data", 199 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS }, 200 { NULL, ".call_table_text", 201 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_CODE 202 | SEC_HAS_CONTENTS}, 203 }; 204 205 #define SDATA_SECTION 0 206 #define TDATA_SECTION 1 207 #define ZDATA_SECTION 2 208 #define SBSS_SECTION 3 209 #define TBSS_SECTION 4 210 #define ZBSS_SECTION 5 211 #define ROSDATA_SECTION 6 212 #define ROZDATA_SECTION 7 213 #define SCOMMON_SECTION 8 214 #define TCOMMON_SECTION 9 215 #define ZCOMMON_SECTION 10 216 #define CALL_TABLE_DATA_SECTION 11 217 #define CALL_TABLE_TEXT_SECTION 12 218 219 static void 220 do_v850_seg (int i, subsegT sub) 221 { 222 struct v850_seg_entry *seg = v850_seg_table + i; 223 224 obj_elf_section_change_hook (); 225 226 if (seg->s != NULL) 227 subseg_set (seg->s, sub); 228 else 229 { 230 seg->s = subseg_new (seg->name, sub); 231 bfd_set_section_flags (seg->s, seg->flags); 232 if ((seg->flags & SEC_LOAD) == 0) 233 seg_info (seg->s)->bss = 1; 234 } 235 } 236 237 static void 238 v850_seg (int i) 239 { 240 subsegT sub = get_absolute_expression (); 241 242 do_v850_seg (i, sub); 243 demand_empty_rest_of_line (); 244 } 245 246 static void 247 v850_offset (int ignore ATTRIBUTE_UNUSED) 248 { 249 char *pfrag; 250 int temp = get_absolute_expression (); 251 252 pfrag = frag_var (rs_org, 1, 1, 0, NULL, temp, NULL); 253 *pfrag = 0; 254 255 demand_empty_rest_of_line (); 256 } 257 258 /* Copied from obj_elf_common() in gas/config/obj-elf.c. */ 259 260 static void 261 v850_comm (int area) 262 { 263 char *name; 264 char c; 265 char *p; 266 int temp; 267 unsigned int size; 268 symbolS *symbolP; 269 int have_align; 270 271 c = get_symbol_name (&name); 272 273 /* Just after name is now '\0'. */ 274 p = input_line_pointer; 275 *p = c; 276 277 SKIP_WHITESPACE (); 278 279 if (*input_line_pointer != ',') 280 { 281 as_bad (_("Expected comma after symbol-name")); 282 ignore_rest_of_line (); 283 return; 284 } 285 286 /* Skip ','. */ 287 input_line_pointer++; 288 289 if ((temp = get_absolute_expression ()) < 0) 290 { 291 /* xgettext:c-format */ 292 as_bad (_(".COMMon length (%d.) < 0! Ignored."), temp); 293 ignore_rest_of_line (); 294 return; 295 } 296 297 size = temp; 298 *p = 0; 299 symbolP = symbol_find_or_make (name); 300 *p = c; 301 302 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) 303 { 304 as_bad (_("Ignoring attempt to re-define symbol")); 305 ignore_rest_of_line (); 306 return; 307 } 308 309 if (S_GET_VALUE (symbolP) != 0) 310 { 311 if (S_GET_VALUE (symbolP) != size) 312 /* xgettext:c-format */ 313 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."), 314 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size); 315 } 316 317 know (symbol_get_frag (symbolP) == &zero_address_frag); 318 319 if (*input_line_pointer != ',') 320 have_align = 0; 321 else 322 { 323 have_align = 1; 324 input_line_pointer++; 325 SKIP_WHITESPACE (); 326 } 327 328 if (! have_align || *input_line_pointer != '"') 329 { 330 if (! have_align) 331 temp = 0; 332 else 333 { 334 temp = get_absolute_expression (); 335 336 if (temp < 0) 337 { 338 temp = 0; 339 as_warn (_("Common alignment negative; 0 assumed")); 340 } 341 } 342 343 if (symbol_get_obj (symbolP)->local) 344 { 345 segT old_sec; 346 int old_subsec; 347 char *pfrag; 348 int align; 349 flagword applicable; 350 351 old_sec = now_seg; 352 old_subsec = now_subseg; 353 354 applicable = bfd_applicable_section_flags (stdoutput); 355 356 applicable &= SEC_ALLOC; 357 358 switch (area) 359 { 360 case SCOMMON_SECTION: 361 do_v850_seg (SBSS_SECTION, 0); 362 break; 363 364 case ZCOMMON_SECTION: 365 do_v850_seg (ZBSS_SECTION, 0); 366 break; 367 368 case TCOMMON_SECTION: 369 do_v850_seg (TBSS_SECTION, 0); 370 break; 371 } 372 373 if (temp) 374 { 375 /* Convert to a power of 2 alignment. */ 376 for (align = 0; (temp & 1) == 0; temp >>= 1, ++align) 377 ; 378 379 if (temp != 1) 380 { 381 as_bad (_("Common alignment not a power of 2")); 382 ignore_rest_of_line (); 383 return; 384 } 385 } 386 else 387 align = 0; 388 389 record_alignment (now_seg, align); 390 391 if (align) 392 frag_align (align, 0, 0); 393 394 switch (area) 395 { 396 case SCOMMON_SECTION: 397 if (S_GET_SEGMENT (symbolP) == v850_seg_table[SBSS_SECTION].s) 398 symbol_get_frag (symbolP)->fr_symbol = 0; 399 break; 400 401 case ZCOMMON_SECTION: 402 if (S_GET_SEGMENT (symbolP) == v850_seg_table[ZBSS_SECTION].s) 403 symbol_get_frag (symbolP)->fr_symbol = 0; 404 break; 405 406 case TCOMMON_SECTION: 407 if (S_GET_SEGMENT (symbolP) == v850_seg_table[TBSS_SECTION].s) 408 symbol_get_frag (symbolP)->fr_symbol = 0; 409 break; 410 411 default: 412 abort (); 413 } 414 415 symbol_set_frag (symbolP, frag_now); 416 pfrag = frag_var (rs_org, 1, 1, 0, symbolP, size, NULL); 417 *pfrag = 0; 418 S_SET_SIZE (symbolP, size); 419 420 switch (area) 421 { 422 case SCOMMON_SECTION: 423 S_SET_SEGMENT (symbolP, v850_seg_table[SBSS_SECTION].s); 424 break; 425 426 case ZCOMMON_SECTION: 427 S_SET_SEGMENT (symbolP, v850_seg_table[ZBSS_SECTION].s); 428 break; 429 430 case TCOMMON_SECTION: 431 S_SET_SEGMENT (symbolP, v850_seg_table[TBSS_SECTION].s); 432 break; 433 434 default: 435 abort (); 436 } 437 438 S_CLEAR_EXTERNAL (symbolP); 439 obj_elf_section_change_hook (); 440 subseg_set (old_sec, old_subsec); 441 } 442 else 443 { 444 segT old_sec; 445 int old_subsec; 446 447 allocate_common: 448 old_sec = now_seg; 449 old_subsec = now_subseg; 450 451 S_SET_VALUE (symbolP, (valueT) size); 452 S_SET_ALIGN (symbolP, temp); 453 S_SET_EXTERNAL (symbolP); 454 455 switch (area) 456 { 457 case SCOMMON_SECTION: 458 case ZCOMMON_SECTION: 459 case TCOMMON_SECTION: 460 do_v850_seg (area, 0); 461 S_SET_SEGMENT (symbolP, v850_seg_table[area].s); 462 break; 463 464 default: 465 abort (); 466 } 467 468 obj_elf_section_change_hook (); 469 subseg_set (old_sec, old_subsec); 470 } 471 } 472 else 473 { 474 input_line_pointer++; 475 476 /* @@ Some use the dot, some don't. Can we get some consistency?? */ 477 if (*input_line_pointer == '.') 478 input_line_pointer++; 479 480 /* @@ Some say data, some say bss. */ 481 if (!startswith (input_line_pointer, "bss\"") 482 && !startswith (input_line_pointer, "data\"")) 483 { 484 while (*--input_line_pointer != '"') 485 ; 486 input_line_pointer--; 487 goto bad_common_segment; 488 } 489 490 while (*input_line_pointer++ != '"') 491 ; 492 493 goto allocate_common; 494 } 495 496 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; 497 498 demand_empty_rest_of_line (); 499 return; 500 501 { 502 bad_common_segment: 503 p = input_line_pointer; 504 while (*p && *p != '\n') 505 p++; 506 c = *p; 507 *p = '\0'; 508 as_bad (_("bad .common segment %s"), input_line_pointer + 1); 509 *p = c; 510 input_line_pointer = p; 511 ignore_rest_of_line (); 512 return; 513 } 514 } 515 516 static void 517 set_machine (int number) 518 { 519 machine = number; 520 bfd_set_arch_mach (stdoutput, v850_target_arch, machine); 521 522 switch (machine) 523 { 524 case 0: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); break; 525 case bfd_mach_v850: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); break; 526 case bfd_mach_v850e: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); break; 527 case bfd_mach_v850e1: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); break; 528 case bfd_mach_v850e2: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2); break; 529 case bfd_mach_v850e2v3:SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3); break; 530 case bfd_mach_v850e3v5: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5); break; 531 } 532 } 533 534 static void 535 v850_longcode (int type) 536 { 537 expressionS ex; 538 539 if (! v850_relax) 540 { 541 if (type == 1) 542 as_warn (_(".longcall pseudo-op seen when not relaxing")); 543 else 544 as_warn (_(".longjump pseudo-op seen when not relaxing")); 545 } 546 547 expression (&ex); 548 549 if (ex.X_op != O_symbol || ex.X_add_number != 0) 550 { 551 as_bad (_("bad .longcall format")); 552 ignore_rest_of_line (); 553 554 return; 555 } 556 557 if (type == 1) 558 fix_new_exp (frag_now, frag_now_fix (), 4, & ex, 1, 559 BFD_RELOC_V850_LONGCALL); 560 else 561 fix_new_exp (frag_now, frag_now_fix (), 4, & ex, 1, 562 BFD_RELOC_V850_LONGJUMP); 563 564 demand_empty_rest_of_line (); 565 } 566 567 /* The target specific pseudo-ops which we support. */ 568 const pseudo_typeS md_pseudo_table[] = 569 { 570 { "sdata", v850_seg, SDATA_SECTION }, 571 { "tdata", v850_seg, TDATA_SECTION }, 572 { "zdata", v850_seg, ZDATA_SECTION }, 573 { "sbss", v850_seg, SBSS_SECTION }, 574 { "tbss", v850_seg, TBSS_SECTION }, 575 { "zbss", v850_seg, ZBSS_SECTION }, 576 { "rosdata", v850_seg, ROSDATA_SECTION }, 577 { "rozdata", v850_seg, ROZDATA_SECTION }, 578 { "offset", v850_offset, 0 }, 579 { "word", cons, 4 }, 580 { "zcomm", v850_comm, ZCOMMON_SECTION }, 581 { "scomm", v850_comm, SCOMMON_SECTION }, 582 { "tcomm", v850_comm, TCOMMON_SECTION }, 583 { "v850", set_machine, 0 }, 584 { "call_table_data", v850_seg, CALL_TABLE_DATA_SECTION }, 585 { "call_table_text", v850_seg, CALL_TABLE_TEXT_SECTION }, 586 { "v850e", set_machine, bfd_mach_v850e }, 587 { "v850e1", set_machine, bfd_mach_v850e1 }, 588 { "v850e2", set_machine, bfd_mach_v850e2 }, 589 { "v850e2v3", set_machine, bfd_mach_v850e2v3 }, 590 { "v850e2v4", set_machine, bfd_mach_v850e3v5 }, 591 { "v850e3v5", set_machine, bfd_mach_v850e3v5 }, 592 { "longcall", v850_longcode, 1 }, 593 { "longjump", v850_longcode, 2 }, 594 { NULL, NULL, 0 } 595 }; 596 597 /* Opcode hash table. */ 598 static htab_t v850_hash; 599 600 /* This table is sorted. Suitable for searching by a binary search. */ 601 static const struct reg_name pre_defined_registers[] = 602 { 603 { "ep", 30, PROCESSOR_ALL }, /* ep - element ptr. */ 604 { "gp", 4, PROCESSOR_ALL }, /* gp - global ptr. */ 605 { "hp", 2, PROCESSOR_ALL }, /* hp - handler stack ptr. */ 606 { "lp", 31, PROCESSOR_ALL }, /* lp - link ptr. */ 607 { "r0", 0, PROCESSOR_ALL }, 608 { "r1", 1, PROCESSOR_ALL }, 609 { "r10", 10, PROCESSOR_ALL }, 610 { "r11", 11, PROCESSOR_ALL }, 611 { "r12", 12, PROCESSOR_ALL }, 612 { "r13", 13, PROCESSOR_ALL }, 613 { "r14", 14, PROCESSOR_ALL }, 614 { "r15", 15, PROCESSOR_ALL }, 615 { "r16", 16, PROCESSOR_ALL }, 616 { "r17", 17, PROCESSOR_ALL }, 617 { "r18", 18, PROCESSOR_ALL }, 618 { "r19", 19, PROCESSOR_ALL }, 619 { "r2", 2, PROCESSOR_ALL }, 620 { "r20", 20, PROCESSOR_ALL }, 621 { "r21", 21, PROCESSOR_ALL }, 622 { "r22", 22, PROCESSOR_ALL }, 623 { "r23", 23, PROCESSOR_ALL }, 624 { "r24", 24, PROCESSOR_ALL }, 625 { "r25", 25, PROCESSOR_ALL }, 626 { "r26", 26, PROCESSOR_ALL }, 627 { "r27", 27, PROCESSOR_ALL }, 628 { "r28", 28, PROCESSOR_ALL }, 629 { "r29", 29, PROCESSOR_ALL }, 630 { "r3", 3, PROCESSOR_ALL }, 631 { "r30", 30, PROCESSOR_ALL }, 632 { "r31", 31, PROCESSOR_ALL }, 633 { "r4", 4, PROCESSOR_ALL }, 634 { "r5", 5, PROCESSOR_ALL }, 635 { "r6", 6, PROCESSOR_ALL }, 636 { "r7", 7, PROCESSOR_ALL }, 637 { "r8", 8, PROCESSOR_ALL }, 638 { "r9", 9, PROCESSOR_ALL }, 639 { "sp", 3, PROCESSOR_ALL }, /* sp - stack ptr. */ 640 { "tp", 5, PROCESSOR_ALL }, /* tp - text ptr. */ 641 { "zero", 0, PROCESSOR_ALL }, 642 }; 643 644 #define REG_NAME_CNT \ 645 (sizeof (pre_defined_registers) / sizeof (struct reg_name)) 646 647 static const struct reg_name system_registers[] = 648 { 649 { "asid", 23, PROCESSOR_NOT_V850 }, 650 { "bpam", 25, PROCESSOR_NOT_V850 }, 651 { "bpav", 24, PROCESSOR_NOT_V850 }, 652 { "bpc", 22, PROCESSOR_NOT_V850 }, 653 { "bpdm", 27, PROCESSOR_NOT_V850 }, 654 { "bpdv", 26, PROCESSOR_NOT_V850 }, 655 { "bsel", 31, PROCESSOR_V850E2_UP }, 656 { "cfg", 7, PROCESSOR_V850E2V3_UP }, 657 { "ctbp", 20, PROCESSOR_NOT_V850 }, 658 { "ctpc", 16, PROCESSOR_NOT_V850 }, 659 { "ctpsw", 17, PROCESSOR_NOT_V850 }, 660 { "dbic", 15, PROCESSOR_V850E2_UP }, 661 { "dbpc", 18, PROCESSOR_NOT_V850 }, 662 { "dbpsw", 19, PROCESSOR_NOT_V850 }, 663 { "dbwr", 30, PROCESSOR_V850E2_UP }, 664 { "dir", 21, PROCESSOR_NOT_V850 }, 665 { "dpa0l", 16, PROCESSOR_V850E2V3_UP }, 666 { "dpa0u", 17, PROCESSOR_V850E2V3_UP }, 667 { "dpa1l", 18, PROCESSOR_V850E2V3_UP }, 668 { "dpa1u", 19, PROCESSOR_V850E2V3_UP }, 669 { "dpa2l", 20, PROCESSOR_V850E2V3_UP }, 670 { "dpa2u", 21, PROCESSOR_V850E2V3_UP }, 671 { "dpa3l", 22, PROCESSOR_V850E2V3_UP }, 672 { "dpa3u", 23, PROCESSOR_V850E2V3_UP }, 673 { "dpa4l", 24, PROCESSOR_V850E2V3_UP }, 674 { "dpa4u", 25, PROCESSOR_V850E2V3_UP }, 675 { "dpa5l", 26, PROCESSOR_V850E2V3_UP }, 676 { "dpa5u", 27, PROCESSOR_V850E2V3_UP }, 677 { "ecr", 4, PROCESSOR_ALL }, 678 { "eh_base", 3, PROCESSOR_V850E2V3_UP }, 679 { "eh_cfg", 1, PROCESSOR_V850E2V3_UP }, 680 { "eh_reset", 2, PROCESSOR_V850E2V3_UP }, 681 { "eiic", 13, PROCESSOR_V850E2_UP }, 682 { "eipc", 0, PROCESSOR_ALL }, 683 { "eipsw", 1, PROCESSOR_ALL }, 684 { "eiwr", 28, PROCESSOR_V850E2_UP }, 685 { "feic", 14, PROCESSOR_V850E2_UP }, 686 { "fepc", 2, PROCESSOR_ALL }, 687 { "fepsw", 3, PROCESSOR_ALL }, 688 { "fewr", 29, PROCESSOR_V850E2_UP }, 689 { "fpcc", 9, PROCESSOR_V850E2V3_UP }, 690 { "fpcfg", 10, PROCESSOR_V850E2V3_UP }, 691 { "fpec", 11, PROCESSOR_V850E2V3_UP }, 692 { "fpepc", 7, PROCESSOR_V850E2V3_UP }, 693 { "fpspc", 27, PROCESSOR_V850E2V3_UP }, 694 { "fpsr", 6, PROCESSOR_V850E2V3_UP }, 695 { "fpst", 8, PROCESSOR_V850E2V3_UP }, 696 { "ipa0l", 6, PROCESSOR_V850E2V3_UP }, 697 { "ipa0u", 7, PROCESSOR_V850E2V3_UP }, 698 { "ipa1l", 8, PROCESSOR_V850E2V3_UP }, 699 { "ipa1u", 9, PROCESSOR_V850E2V3_UP }, 700 { "ipa2l", 10, PROCESSOR_V850E2V3_UP }, 701 { "ipa2u", 11, PROCESSOR_V850E2V3_UP }, 702 { "ipa3l", 12, PROCESSOR_V850E2V3_UP }, 703 { "ipa3u", 13, PROCESSOR_V850E2V3_UP }, 704 { "ipa4l", 14, PROCESSOR_V850E2V3_UP }, 705 { "ipa4u", 15, PROCESSOR_V850E2V3_UP }, 706 { "mca", 24, PROCESSOR_V850E2V3_UP }, 707 { "mcc", 26, PROCESSOR_V850E2V3_UP }, 708 { "mcr", 27, PROCESSOR_V850E2V3_UP }, 709 { "mcs", 25, PROCESSOR_V850E2V3_UP }, 710 { "mpc", 1, PROCESSOR_V850E2V3_UP }, 711 { "mpm", 0, PROCESSOR_V850E2V3_UP }, 712 { "mpu10_dpa0l", 16, PROCESSOR_V850E2V3_UP }, 713 { "mpu10_dpa0u", 17, PROCESSOR_V850E2V3_UP }, 714 { "mpu10_dpa1l", 18, PROCESSOR_V850E2V3_UP }, 715 { "mpu10_dpa1u", 19, PROCESSOR_V850E2V3_UP }, 716 { "mpu10_dpa2l", 20, PROCESSOR_V850E2V3_UP }, 717 { "mpu10_dpa2u", 21, PROCESSOR_V850E2V3_UP }, 718 { "mpu10_dpa3l", 22, PROCESSOR_V850E2V3_UP }, 719 { "mpu10_dpa3u", 23, PROCESSOR_V850E2V3_UP }, 720 { "mpu10_dpa4l", 24, PROCESSOR_V850E2V3_UP }, 721 { "mpu10_dpa4u", 25, PROCESSOR_V850E2V3_UP }, 722 { "mpu10_dpa5l", 26, PROCESSOR_V850E2V3_UP }, 723 { "mpu10_dpa5u", 27, PROCESSOR_V850E2V3_UP }, 724 { "mpu10_ipa0l", 6, PROCESSOR_V850E2V3_UP }, 725 { "mpu10_ipa0u", 7, PROCESSOR_V850E2V3_UP }, 726 { "mpu10_ipa1l", 8, PROCESSOR_V850E2V3_UP }, 727 { "mpu10_ipa1u", 9, PROCESSOR_V850E2V3_UP }, 728 { "mpu10_ipa2l", 10, PROCESSOR_V850E2V3_UP }, 729 { "mpu10_ipa2u", 11, PROCESSOR_V850E2V3_UP }, 730 { "mpu10_ipa3l", 12, PROCESSOR_V850E2V3_UP }, 731 { "mpu10_ipa3u", 13, PROCESSOR_V850E2V3_UP }, 732 { "mpu10_ipa4l", 14, PROCESSOR_V850E2V3_UP }, 733 { "mpu10_ipa4u", 15, PROCESSOR_V850E2V3_UP }, 734 { "mpu10_mpc", 1, PROCESSOR_V850E2V3_UP }, 735 { "mpu10_mpm", 0, PROCESSOR_V850E2V3_UP }, 736 { "mpu10_tid", 2, PROCESSOR_V850E2V3_UP }, 737 { "mpu10_vmadr", 5, PROCESSOR_V850E2V3_UP }, 738 { "mpu10_vmecr", 3, PROCESSOR_V850E2V3_UP }, 739 { "mpu10_vmtid", 4, PROCESSOR_V850E2V3_UP }, 740 { "pid", 6, PROCESSOR_V850E2V3_UP }, 741 { "pmcr0", 4, PROCESSOR_V850E2V3_UP }, 742 { "pmis2", 14, PROCESSOR_V850E2V3_UP }, 743 { "psw", 5, PROCESSOR_ALL }, 744 { "scbp", 12, PROCESSOR_V850E2V3_UP }, 745 { "sccfg", 11, PROCESSOR_V850E2V3_UP }, 746 { "sr0", 0, PROCESSOR_ALL }, 747 { "sr1", 1, PROCESSOR_ALL }, 748 { "sr10", 10, PROCESSOR_ALL }, 749 { "sr11", 11, PROCESSOR_ALL }, 750 { "sr12", 12, PROCESSOR_ALL }, 751 { "sr13", 13, PROCESSOR_ALL }, 752 { "sr14", 14, PROCESSOR_ALL }, 753 { "sr15", 15, PROCESSOR_ALL }, 754 { "sr16", 16, PROCESSOR_ALL }, 755 { "sr17", 17, PROCESSOR_ALL }, 756 { "sr18", 18, PROCESSOR_ALL }, 757 { "sr19", 19, PROCESSOR_ALL }, 758 { "sr2", 2, PROCESSOR_ALL }, 759 { "sr20", 20, PROCESSOR_ALL }, 760 { "sr21", 21, PROCESSOR_ALL }, 761 { "sr22", 22, PROCESSOR_ALL }, 762 { "sr23", 23, PROCESSOR_ALL }, 763 { "sr24", 24, PROCESSOR_ALL }, 764 { "sr25", 25, PROCESSOR_ALL }, 765 { "sr26", 26, PROCESSOR_ALL }, 766 { "sr27", 27, PROCESSOR_ALL }, 767 { "sr28", 28, PROCESSOR_ALL }, 768 { "sr29", 29, PROCESSOR_ALL }, 769 { "sr3", 3, PROCESSOR_ALL }, 770 { "sr30", 30, PROCESSOR_ALL }, 771 { "sr31", 31, PROCESSOR_ALL }, 772 { "sr4", 4, PROCESSOR_ALL }, 773 { "sr5", 5, PROCESSOR_ALL }, 774 { "sr6", 6, PROCESSOR_ALL }, 775 { "sr7", 7, PROCESSOR_ALL }, 776 { "sr8", 8, PROCESSOR_ALL }, 777 { "sr9", 9, PROCESSOR_ALL }, 778 { "sw_base", 3, PROCESSOR_V850E2V3_UP }, 779 { "sw_cfg", 1, PROCESSOR_V850E2V3_UP }, 780 { "sw_ctl", 0, PROCESSOR_V850E2V3_UP }, 781 { "tid", 2, PROCESSOR_V850E2V3_UP }, 782 { "vmadr", 6, PROCESSOR_V850E2V3_UP }, 783 { "vmecr", 4, PROCESSOR_V850E2V3_UP }, 784 { "vmtid", 5, PROCESSOR_V850E2V3_UP }, 785 { "vsadr", 2, PROCESSOR_V850E2V3_UP }, 786 { "vsecr", 0, PROCESSOR_V850E2V3_UP }, 787 { "vstid", 1, PROCESSOR_V850E2V3_UP }, 788 }; 789 790 #define SYSREG_NAME_CNT \ 791 (sizeof (system_registers) / sizeof (struct reg_name)) 792 793 794 static const struct reg_name cc_names[] = 795 { 796 { "c", 0x1, PROCESSOR_ALL }, 797 { "e", 0x2, PROCESSOR_ALL }, 798 { "ge", 0xe, PROCESSOR_ALL }, 799 { "gt", 0xf, PROCESSOR_ALL }, 800 { "h", 0xb, PROCESSOR_ALL }, 801 { "l", 0x1, PROCESSOR_ALL }, 802 { "le", 0x7, PROCESSOR_ALL }, 803 { "lt", 0x6, PROCESSOR_ALL }, 804 { "n", 0x4, PROCESSOR_ALL }, 805 { "nc", 0x9, PROCESSOR_ALL }, 806 { "ne", 0xa, PROCESSOR_ALL }, 807 { "nh", 0x3, PROCESSOR_ALL }, 808 { "nl", 0x9, PROCESSOR_ALL }, 809 { "ns", 0xc, PROCESSOR_ALL }, 810 { "nv", 0x8, PROCESSOR_ALL }, 811 { "nz", 0xa, PROCESSOR_ALL }, 812 { "p", 0xc, PROCESSOR_ALL }, 813 { "s", 0x4, PROCESSOR_ALL }, 814 #define COND_SA_NUM 0xd 815 { "sa", COND_SA_NUM, PROCESSOR_ALL }, 816 { "t", 0x5, PROCESSOR_ALL }, 817 { "v", 0x0, PROCESSOR_ALL }, 818 { "z", 0x2, PROCESSOR_ALL }, 819 }; 820 821 #define CC_NAME_CNT \ 822 (sizeof (cc_names) / sizeof (struct reg_name)) 823 824 static const struct reg_name float_cc_names[] = 825 { 826 { "eq", 0x2, PROCESSOR_V850E2V3_UP }, /* true. */ 827 { "f", 0x0, PROCESSOR_V850E2V3_UP }, /* true. */ 828 { "ge", 0xd, PROCESSOR_V850E2V3_UP }, /* false. */ 829 { "gl", 0xb, PROCESSOR_V850E2V3_UP }, /* false. */ 830 { "gle", 0x9, PROCESSOR_V850E2V3_UP }, /* false. */ 831 { "gt", 0xf, PROCESSOR_V850E2V3_UP }, /* false. */ 832 { "le", 0xe, PROCESSOR_V850E2V3_UP }, /* true. */ 833 { "lt", 0xc, PROCESSOR_V850E2V3_UP }, /* true. */ 834 { "neq", 0x2, PROCESSOR_V850E2V3_UP }, /* false. */ 835 { "nge", 0xd, PROCESSOR_V850E2V3_UP }, /* true. */ 836 { "ngl", 0xb, PROCESSOR_V850E2V3_UP }, /* true. */ 837 { "ngle",0x9, PROCESSOR_V850E2V3_UP }, /* true. */ 838 { "ngt", 0xf, PROCESSOR_V850E2V3_UP }, /* true. */ 839 { "nle", 0xe, PROCESSOR_V850E2V3_UP }, /* false. */ 840 { "nlt", 0xc, PROCESSOR_V850E2V3_UP }, /* false. */ 841 { "oge", 0x5, PROCESSOR_V850E2V3_UP }, /* false. */ 842 { "ogl", 0x3, PROCESSOR_V850E2V3_UP }, /* false. */ 843 { "ogt", 0x7, PROCESSOR_V850E2V3_UP }, /* false. */ 844 { "ole", 0x6, PROCESSOR_V850E2V3_UP }, /* true. */ 845 { "olt", 0x4, PROCESSOR_V850E2V3_UP }, /* true. */ 846 { "or", 0x1, PROCESSOR_V850E2V3_UP }, /* false. */ 847 { "seq", 0xa, PROCESSOR_V850E2V3_UP }, /* true. */ 848 { "sf", 0x8, PROCESSOR_V850E2V3_UP }, /* true. */ 849 { "sne", 0xa, PROCESSOR_V850E2V3_UP }, /* false. */ 850 { "st", 0x8, PROCESSOR_V850E2V3_UP }, /* false. */ 851 { "t", 0x0, PROCESSOR_V850E2V3_UP }, /* false. */ 852 { "ueq", 0x3, PROCESSOR_V850E2V3_UP }, /* true. */ 853 { "uge", 0x4, PROCESSOR_V850E2V3_UP }, /* false. */ 854 { "ugt", 0x6, PROCESSOR_V850E2V3_UP }, /* false. */ 855 { "ule", 0x7, PROCESSOR_V850E2V3_UP }, /* true. */ 856 { "ult", 0x5, PROCESSOR_V850E2V3_UP }, /* true. */ 857 { "un", 0x1, PROCESSOR_V850E2V3_UP }, /* true. */ 858 }; 859 860 #define FLOAT_CC_NAME_CNT \ 861 (sizeof (float_cc_names) / sizeof (struct reg_name)) 862 863 864 static const struct reg_name cacheop_names[] = 865 { 866 { "cfald", 0x44, PROCESSOR_V850E3V5_UP }, 867 { "cfali", 0x40, PROCESSOR_V850E3V5_UP }, 868 { "chbid", 0x04, PROCESSOR_V850E3V5_UP }, 869 { "chbii", 0x00, PROCESSOR_V850E3V5_UP }, 870 { "chbiwbd", 0x06, PROCESSOR_V850E3V5_UP }, 871 { "chbwbd", 0x07, PROCESSOR_V850E3V5_UP }, 872 { "cibid", 0x24, PROCESSOR_V850E3V5_UP }, 873 { "cibii", 0x20, PROCESSOR_V850E3V5_UP }, 874 { "cibiwbd", 0x26, PROCESSOR_V850E3V5_UP }, 875 { "cibwbd", 0x27, PROCESSOR_V850E3V5_UP }, 876 { "cildd", 0x65, PROCESSOR_V850E3V5_UP }, 877 { "cildi", 0x61, PROCESSOR_V850E3V5_UP }, 878 { "cistd", 0x64, PROCESSOR_V850E3V5_UP }, 879 { "cisti", 0x60, PROCESSOR_V850E3V5_UP }, 880 }; 881 882 #define CACHEOP_NAME_CNT \ 883 (sizeof (cacheop_names) / sizeof (struct reg_name)) 884 885 static const struct reg_name prefop_names[] = 886 { 887 { "prefd", 0x04, PROCESSOR_V850E3V5_UP }, 888 { "prefi", 0x00, PROCESSOR_V850E3V5_UP }, 889 }; 890 891 #define PREFOP_NAME_CNT \ 892 (sizeof (prefop_names) / sizeof (struct reg_name)) 893 894 static const struct reg_name vector_registers[] = 895 { 896 { "vr0", 0, PROCESSOR_V850E3V5_UP }, 897 { "vr1", 1, PROCESSOR_V850E3V5_UP }, 898 { "vr10", 10, PROCESSOR_V850E3V5_UP }, 899 { "vr11", 11, PROCESSOR_V850E3V5_UP }, 900 { "vr12", 12, PROCESSOR_V850E3V5_UP }, 901 { "vr13", 13, PROCESSOR_V850E3V5_UP }, 902 { "vr14", 14, PROCESSOR_V850E3V5_UP }, 903 { "vr15", 15, PROCESSOR_V850E3V5_UP }, 904 { "vr16", 16, PROCESSOR_V850E3V5_UP }, 905 { "vr17", 17, PROCESSOR_V850E3V5_UP }, 906 { "vr18", 18, PROCESSOR_V850E3V5_UP }, 907 { "vr19", 19, PROCESSOR_V850E3V5_UP }, 908 { "vr2", 2, PROCESSOR_V850E3V5_UP }, 909 { "vr20", 20, PROCESSOR_V850E3V5_UP }, 910 { "vr21", 21, PROCESSOR_V850E3V5_UP }, 911 { "vr22", 22, PROCESSOR_V850E3V5_UP }, 912 { "vr23", 23, PROCESSOR_V850E3V5_UP }, 913 { "vr24", 24, PROCESSOR_V850E3V5_UP }, 914 { "vr25", 25, PROCESSOR_V850E3V5_UP }, 915 { "vr26", 26, PROCESSOR_V850E3V5_UP }, 916 { "vr27", 27, PROCESSOR_V850E3V5_UP }, 917 { "vr28", 28, PROCESSOR_V850E3V5_UP }, 918 { "vr29", 29, PROCESSOR_V850E3V5_UP }, 919 { "vr3", 3, PROCESSOR_V850E3V5_UP }, 920 { "vr30", 30, PROCESSOR_V850E3V5_UP }, 921 { "vr31", 31, PROCESSOR_V850E3V5_UP }, 922 { "vr4", 4, PROCESSOR_V850E3V5_UP }, 923 { "vr5", 5, PROCESSOR_V850E3V5_UP }, 924 { "vr6", 6, PROCESSOR_V850E3V5_UP }, 925 { "vr7", 7, PROCESSOR_V850E3V5_UP }, 926 { "vr8", 8, PROCESSOR_V850E3V5_UP }, 927 { "vr9", 9, PROCESSOR_V850E3V5_UP }, 928 }; 929 930 #define VREG_NAME_CNT \ 931 (sizeof (vector_registers) / sizeof (struct reg_name)) 932 933 /* Do a binary search of the given register table to see if NAME is a 934 valid register name. Return the register number from the array on 935 success, or -1 on failure. */ 936 937 static int 938 reg_name_search (const struct reg_name *regs, 939 int regcount, 940 const char *name, 941 bool accept_numbers) 942 { 943 int middle, low, high; 944 int cmp; 945 symbolS *symbolP; 946 947 /* If the register name is a symbol, then evaluate it. */ 948 if ((symbolP = symbol_find (name)) != NULL) 949 { 950 /* If the symbol is an alias for another name then use that. 951 If the symbol is an alias for a number, then return the number. */ 952 if (symbol_equated_p (symbolP)) 953 name 954 = S_GET_NAME (symbol_get_value_expression (symbolP)->X_add_symbol); 955 else if (accept_numbers) 956 { 957 int reg = S_GET_VALUE (symbolP); 958 return reg; 959 } 960 961 /* Otherwise drop through and try parsing name normally. */ 962 } 963 964 low = 0; 965 high = regcount - 1; 966 967 do 968 { 969 middle = (low + high) / 2; 970 cmp = strcasecmp (name, regs[middle].name); 971 if (cmp < 0) 972 high = middle - 1; 973 else if (cmp > 0) 974 low = middle + 1; 975 else 976 return ((regs[middle].processors & processor_mask) 977 ? regs[middle].value 978 : -1); 979 } 980 while (low <= high); 981 return -1; 982 } 983 984 /* Summary of register_name(). 985 986 in: Input_line_pointer points to 1st char of operand. 987 988 out: An expressionS. 989 The operand may have been a register: in this case, X_op == O_register, 990 X_add_number is set to the register number, and truth is returned. 991 Input_line_pointer->(next non-blank) char after operand, or is in 992 its original state. */ 993 994 static bool 995 register_name (expressionS *expressionP) 996 { 997 int reg_number; 998 char *name; 999 char *start; 1000 char c; 1001 1002 /* Find the spelling of the operand. */ 1003 start = input_line_pointer; 1004 c = get_symbol_name (&name); 1005 1006 reg_number = reg_name_search (pre_defined_registers, REG_NAME_CNT, 1007 name, false); 1008 1009 /* Put back the delimiting char. */ 1010 (void) restore_line_pointer (c); 1011 1012 expressionP->X_add_symbol = NULL; 1013 expressionP->X_op_symbol = NULL; 1014 1015 /* Look to see if it's in the register table. */ 1016 if (reg_number >= 0) 1017 { 1018 expressionP->X_op = O_register; 1019 expressionP->X_add_number = reg_number; 1020 1021 return true; 1022 } 1023 1024 /* Reset the line as if we had not done anything. */ 1025 input_line_pointer = start; 1026 1027 expressionP->X_op = O_illegal; 1028 1029 return false; 1030 } 1031 1032 /* Summary of system_register_name(). 1033 1034 in: INPUT_LINE_POINTER points to 1st char of operand. 1035 EXPRESSIONP points to an expression structure to be filled in. 1036 ACCEPT_NUMBERS is true iff numerical register names may be used. 1037 1038 out: An expressionS structure in expressionP. 1039 The operand may have been a register: in this case, X_op == O_register, 1040 X_add_number is set to the register number, and truth is returned. 1041 Input_line_pointer->(next non-blank) char after operand, or is in 1042 its original state. */ 1043 1044 static bool 1045 system_register_name (expressionS *expressionP, 1046 bool accept_numbers) 1047 { 1048 int reg_number; 1049 char *name; 1050 char *start; 1051 char c; 1052 1053 /* Find the spelling of the operand. */ 1054 start = input_line_pointer; 1055 c = get_symbol_name (&name); 1056 reg_number = reg_name_search (system_registers, SYSREG_NAME_CNT, name, 1057 accept_numbers); 1058 1059 /* Put back the delimiting char. */ 1060 (void) restore_line_pointer (c); 1061 1062 if (reg_number < 0 1063 && accept_numbers) 1064 { 1065 /* Reset input_line pointer. */ 1066 input_line_pointer = start; 1067 1068 if (ISDIGIT (*input_line_pointer)) 1069 { 1070 reg_number = strtol (input_line_pointer, &input_line_pointer, 0); 1071 } 1072 } 1073 1074 expressionP->X_add_symbol = NULL; 1075 expressionP->X_op_symbol = NULL; 1076 1077 /* Look to see if it's in the register table. */ 1078 if (reg_number >= 0) 1079 { 1080 expressionP->X_op = O_register; 1081 expressionP->X_add_number = reg_number; 1082 1083 return true; 1084 } 1085 1086 /* Reset the line as if we had not done anything. */ 1087 input_line_pointer = start; 1088 1089 expressionP->X_op = O_illegal; 1090 1091 return false; 1092 } 1093 1094 /* Summary of cc_name(). 1095 1096 in: INPUT_LINE_POINTER points to 1st char of operand. 1097 1098 out: An expressionS. 1099 The operand may have been a register: in this case, X_op == O_register, 1100 X_add_number is set to the register number, and truth is returned. 1101 Input_line_pointer->(next non-blank) char after operand, or is in 1102 its original state. */ 1103 1104 static bool 1105 cc_name (expressionS *expressionP, 1106 bool accept_numbers) 1107 { 1108 int reg_number; 1109 char *name; 1110 char *start; 1111 char c; 1112 1113 /* Find the spelling of the operand. */ 1114 start = input_line_pointer; 1115 c = get_symbol_name (&name); 1116 reg_number = reg_name_search (cc_names, CC_NAME_CNT, name, accept_numbers); 1117 1118 /* Put back the delimiting char. */ 1119 (void) restore_line_pointer (c); 1120 1121 if (reg_number < 0 1122 && accept_numbers) 1123 { 1124 /* Reset input_line pointer. */ 1125 input_line_pointer = start; 1126 1127 if (ISDIGIT (*input_line_pointer)) 1128 { 1129 reg_number = strtol (input_line_pointer, &input_line_pointer, 0); 1130 } 1131 } 1132 1133 expressionP->X_add_symbol = NULL; 1134 expressionP->X_op_symbol = NULL; 1135 1136 /* Look to see if it's in the register table. */ 1137 if (reg_number >= 0) 1138 { 1139 expressionP->X_op = O_constant; 1140 expressionP->X_add_number = reg_number; 1141 1142 return true; 1143 } 1144 1145 /* Reset the line as if we had not done anything. */ 1146 input_line_pointer = start; 1147 1148 expressionP->X_op = O_illegal; 1149 expressionP->X_add_number = 0; 1150 1151 return false; 1152 } 1153 1154 static bool 1155 float_cc_name (expressionS *expressionP, 1156 bool accept_numbers) 1157 { 1158 int reg_number; 1159 char *name; 1160 char *start; 1161 char c; 1162 1163 /* Find the spelling of the operand. */ 1164 start = input_line_pointer; 1165 c = get_symbol_name (&name); 1166 reg_number = reg_name_search (float_cc_names, FLOAT_CC_NAME_CNT, name, accept_numbers); 1167 1168 /* Put back the delimiting char. */ 1169 (void) restore_line_pointer (c); 1170 1171 if (reg_number < 0 1172 && accept_numbers) 1173 { 1174 /* Reset input_line pointer. */ 1175 input_line_pointer = start; 1176 1177 if (ISDIGIT (*input_line_pointer)) 1178 { 1179 reg_number = strtol (input_line_pointer, &input_line_pointer, 0); 1180 } 1181 } 1182 1183 expressionP->X_add_symbol = NULL; 1184 expressionP->X_op_symbol = NULL; 1185 1186 /* Look to see if it's in the register table. */ 1187 if (reg_number >= 0) 1188 { 1189 expressionP->X_op = O_constant; 1190 expressionP->X_add_number = reg_number; 1191 1192 return true; 1193 } 1194 1195 /* Reset the line as if we had not done anything. */ 1196 input_line_pointer = start; 1197 1198 expressionP->X_op = O_illegal; 1199 expressionP->X_add_number = 0; 1200 1201 return false; 1202 } 1203 1204 static bool 1205 cacheop_name (expressionS * expressionP, 1206 bool accept_numbers) 1207 { 1208 int reg_number; 1209 char *name; 1210 char *start; 1211 char c; 1212 1213 /* Find the spelling of the operand. */ 1214 start = input_line_pointer; 1215 c = get_symbol_name (&name); 1216 reg_number = reg_name_search (cacheop_names, CACHEOP_NAME_CNT, name, accept_numbers); 1217 1218 /* Put back the delimiting char. */ 1219 (void) restore_line_pointer (c); 1220 1221 if (reg_number < 0 1222 && accept_numbers) 1223 { 1224 /* Reset input_line pointer. */ 1225 input_line_pointer = start; 1226 1227 if (ISDIGIT (*input_line_pointer)) 1228 reg_number = strtol (input_line_pointer, &input_line_pointer, 0); 1229 } 1230 1231 expressionP->X_add_symbol = NULL; 1232 expressionP->X_op_symbol = NULL; 1233 1234 /* Look to see if it's in the register table. */ 1235 if (reg_number >= 0) 1236 { 1237 expressionP->X_op = O_constant; 1238 expressionP->X_add_number = reg_number; 1239 1240 return true; 1241 } 1242 1243 /* Reset the line as if we had not done anything. */ 1244 input_line_pointer = start; 1245 1246 expressionP->X_op = O_illegal; 1247 expressionP->X_add_number = 0; 1248 1249 return false; 1250 } 1251 1252 static bool 1253 prefop_name (expressionS * expressionP, 1254 bool accept_numbers) 1255 { 1256 int reg_number; 1257 char *name; 1258 char *start; 1259 char c; 1260 1261 /* Find the spelling of the operand. */ 1262 start = input_line_pointer; 1263 c = get_symbol_name (&name); 1264 reg_number = reg_name_search (prefop_names, PREFOP_NAME_CNT, name, accept_numbers); 1265 1266 /* Put back the delimiting char. */ 1267 (void) restore_line_pointer (c); 1268 1269 if (reg_number < 0 1270 && accept_numbers) 1271 { 1272 /* Reset input_line pointer. */ 1273 input_line_pointer = start; 1274 1275 if (ISDIGIT (*input_line_pointer)) 1276 reg_number = strtol (input_line_pointer, &input_line_pointer, 0); 1277 } 1278 1279 expressionP->X_add_symbol = NULL; 1280 expressionP->X_op_symbol = NULL; 1281 1282 /* Look to see if it's in the register table. */ 1283 if (reg_number >= 0) 1284 { 1285 expressionP->X_op = O_constant; 1286 expressionP->X_add_number = reg_number; 1287 1288 return true; 1289 } 1290 1291 /* Reset the line as if we had not done anything. */ 1292 input_line_pointer = start; 1293 1294 expressionP->X_op = O_illegal; 1295 expressionP->X_add_number = 0; 1296 1297 return false; 1298 } 1299 1300 static bool 1301 vector_register_name (expressionS *expressionP) 1302 { 1303 int reg_number; 1304 char *name; 1305 char *start; 1306 char c; 1307 1308 /* Find the spelling of the operand. */ 1309 start = input_line_pointer; 1310 c = get_symbol_name (&name); 1311 1312 reg_number = reg_name_search (vector_registers, VREG_NAME_CNT, 1313 name, false); 1314 1315 /* Put back the delimiting char. */ 1316 (void) restore_line_pointer (c); 1317 1318 expressionP->X_add_symbol = NULL; 1319 expressionP->X_op_symbol = NULL; 1320 1321 /* Look to see if it's in the register table. */ 1322 if (reg_number >= 0) 1323 { 1324 expressionP->X_op = O_register; 1325 expressionP->X_add_number = reg_number; 1326 1327 return true; 1328 } 1329 1330 /* Reset the line as if we had not done anything. */ 1331 input_line_pointer = start; 1332 1333 expressionP->X_op = O_illegal; 1334 1335 return false; 1336 } 1337 1338 static void 1339 skip_white_space (void) 1340 { 1341 while (is_whitespace (*input_line_pointer)) 1342 ++input_line_pointer; 1343 } 1344 1345 /* Summary of parse_register_list (). 1346 1347 in: INPUT_LINE_POINTER points to 1st char of a list of registers. 1348 INSN is the partially constructed instruction. 1349 OPERAND is the operand being inserted. 1350 1351 out: NULL if the parse completed successfully, otherwise a 1352 pointer to an error message is returned. If the parse 1353 completes the correct bit fields in the instruction 1354 will be filled in. 1355 1356 Parses register lists with the syntax: 1357 1358 { rX } 1359 { rX, rY } 1360 { rX - rY } 1361 { rX - rY, rZ } 1362 etc 1363 1364 and also parses constant expressions whose bits indicate the 1365 registers in the lists. The LSB in the expression refers to 1366 the lowest numbered permissible register in the register list, 1367 and so on upwards. System registers are considered to be very 1368 high numbers. */ 1369 1370 static const char * 1371 parse_register_list (unsigned long *insn, 1372 const struct v850_operand *operand) 1373 { 1374 static int type1_regs[32] = 1375 { 1376 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1377 0, 0, 0, 0, 0, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 1378 }; 1379 1380 int *regs; 1381 expressionS exp; 1382 1383 /* Select a register array to parse. */ 1384 switch (operand->shift) 1385 { 1386 case 0xffe00001: regs = type1_regs; break; 1387 default: 1388 as_bad (_("unknown operand shift: %x\n"), operand->shift); 1389 return _("internal failure in parse_register_list"); 1390 } 1391 1392 skip_white_space (); 1393 1394 /* If the expression starts with a curly brace it is a register list. 1395 Otherwise it is a constant expression, whose bits indicate which 1396 registers are to be included in the list. */ 1397 if (*input_line_pointer != '{') 1398 { 1399 int reg; 1400 int i; 1401 1402 expression (&exp); 1403 1404 if (exp.X_op != O_constant) 1405 return _("constant expression or register list expected"); 1406 1407 if (regs == type1_regs) 1408 { 1409 if (exp.X_add_number & 0xFFFFF000) 1410 return _("high bits set in register list expression"); 1411 1412 for (reg = 20; reg < 32; reg++) 1413 if (exp.X_add_number & (1 << (reg - 20))) 1414 { 1415 for (i = 0; i < 32; i++) 1416 if (regs[i] == reg) 1417 *insn |= (1 << i); 1418 } 1419 } 1420 1421 return NULL; 1422 } 1423 1424 input_line_pointer++; 1425 1426 /* Parse the register list until a terminator (closing curly brace or 1427 new-line) is found. */ 1428 for (;;) 1429 { 1430 skip_white_space (); 1431 1432 if (register_name (&exp)) 1433 { 1434 int i; 1435 1436 /* Locate the given register in the list, and if it is there, 1437 insert the corresponding bit into the instruction. */ 1438 for (i = 0; i < 32; i++) 1439 { 1440 if (regs[i] == exp.X_add_number) 1441 { 1442 *insn |= 1u << i; 1443 break; 1444 } 1445 } 1446 1447 if (i == 32) 1448 return _("illegal register included in list"); 1449 } 1450 else if (system_register_name (&exp, true)) 1451 { 1452 if (regs == type1_regs) 1453 { 1454 return _("system registers cannot be included in list"); 1455 } 1456 } 1457 1458 if (*input_line_pointer == '}') 1459 { 1460 input_line_pointer++; 1461 break; 1462 } 1463 else if (*input_line_pointer == ',') 1464 { 1465 input_line_pointer++; 1466 continue; 1467 } 1468 else if (*input_line_pointer == '-') 1469 { 1470 /* We have encountered a range of registers: rX - rY. */ 1471 int j; 1472 expressionS exp2; 1473 1474 /* Skip the dash. */ 1475 ++input_line_pointer; 1476 1477 /* Get the second register in the range. */ 1478 if (! register_name (&exp2)) 1479 { 1480 return _("second register should follow dash in register list"); 1481 } 1482 1483 if (exp.X_add_number > exp2.X_add_number) 1484 { 1485 return _("second register should be greater than first register"); 1486 } 1487 1488 /* Add the rest of the registers in the range. */ 1489 for (j = exp.X_add_number + 1; j <= exp2.X_add_number; j++) 1490 { 1491 int i; 1492 1493 /* Locate the given register in the list, and if it is there, 1494 insert the corresponding bit into the instruction. */ 1495 for (i = 0; i < 32; i++) 1496 { 1497 if (regs[i] == j) 1498 { 1499 *insn |= (1 << i); 1500 break; 1501 } 1502 } 1503 1504 if (i == 32) 1505 return _("illegal register included in list"); 1506 } 1507 1508 exp = exp2; 1509 } 1510 else 1511 break; 1512 } 1513 1514 return NULL; 1515 } 1516 1517 const char md_shortopts[] = "m:"; 1518 1519 const struct option md_longopts[] = 1520 { 1521 #define OPTION_DISP_SIZE_DEFAULT_22 (OPTION_MD_BASE) 1522 {"disp-size-default-22", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_22}, 1523 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 1) 1524 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32}, 1525 {NULL, no_argument, NULL, 0} 1526 }; 1527 1528 const size_t md_longopts_size = sizeof (md_longopts); 1529 1530 static bool v850_data_8 = false; 1531 1532 void 1533 md_show_usage (FILE *stream) 1534 { 1535 fprintf (stream, _(" V850 options:\n")); 1536 fprintf (stream, _(" -mwarn-signed-overflow Warn if signed immediate values overflow\n")); 1537 fprintf (stream, _(" -mwarn-unsigned-overflow Warn if unsigned immediate values overflow\n")); 1538 fprintf (stream, _(" -mv850 The code is targeted at the v850\n")); 1539 fprintf (stream, _(" -mv850e The code is targeted at the v850e\n")); 1540 fprintf (stream, _(" -mv850e1 The code is targeted at the v850e1\n")); 1541 fprintf (stream, _(" -mv850e2 The code is targeted at the v850e2\n")); 1542 fprintf (stream, _(" -mv850e2v3 The code is targeted at the v850e2v3\n")); 1543 fprintf (stream, _(" -mv850e2v4 Alias for -mv850e3v5\n")); 1544 fprintf (stream, _(" -mv850e3v5 The code is targeted at the v850e3v5\n")); 1545 fprintf (stream, _(" -mrelax Enable relaxation\n")); 1546 fprintf (stream, _(" --disp-size-default-22 branch displacement with unknown size is 22 bits (default)\n")); 1547 fprintf (stream, _(" --disp-size-default-32 branch displacement with unknown size is 32 bits\n")); 1548 fprintf (stream, _(" -mextension enable extension opcode support\n")); 1549 fprintf (stream, _(" -mno-bcond17 disable b<cond> disp17 instruction\n")); 1550 fprintf (stream, _(" -mno-stld23 disable st/ld offset23 instruction\n")); 1551 fprintf (stream, _(" -mgcc-abi Mark the binary as using the old GCC ABI\n")); 1552 fprintf (stream, _(" -mrh850-abi Mark the binary as using the RH850 ABI (default)\n")); 1553 fprintf (stream, _(" -m8byte-align Mark the binary as using 64-bit alignment\n")); 1554 fprintf (stream, _(" -m4byte-align Mark the binary as using 32-bit alignment (default)\n")); 1555 fprintf (stream, _(" -msoft-float Mark the binary as not using FP insns (default for pre e2v3)\n")); 1556 fprintf (stream, _(" -mhard-float Mark the binary as using FP insns (default for e2v3 and up)\n")); 1557 } 1558 1559 int 1560 md_parse_option (int c, const char *arg) 1561 { 1562 if (c != 'm') 1563 { 1564 switch (c) 1565 { 1566 case OPTION_DISP_SIZE_DEFAULT_22: 1567 default_disp_size = 22; 1568 return 1; 1569 1570 case OPTION_DISP_SIZE_DEFAULT_32: 1571 default_disp_size = 32; 1572 return 1; 1573 } 1574 return 0; 1575 } 1576 1577 if (strcmp (arg, "warn-signed-overflow") == 0) 1578 warn_signed_overflows = true; 1579 1580 else if (strcmp (arg, "warn-unsigned-overflow") == 0) 1581 warn_unsigned_overflows = true; 1582 1583 else if (strcmp (arg, "v850") == 0) 1584 { 1585 machine = 0; 1586 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); 1587 } 1588 else if (strcmp (arg, "v850e") == 0) 1589 { 1590 machine = bfd_mach_v850e; 1591 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); 1592 } 1593 else if (strcmp (arg, "v850e1") == 0) 1594 { 1595 machine = bfd_mach_v850e1; 1596 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E1); 1597 } 1598 else if (strcmp (arg, "v850e2") == 0) 1599 { 1600 machine = bfd_mach_v850e2; 1601 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2); 1602 } 1603 else if (strcmp (arg, "v850e2v3") == 0) 1604 { 1605 machine = bfd_mach_v850e2v3; 1606 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3); 1607 } 1608 else if (strcmp (arg, "v850e2v4") == 0) 1609 { 1610 machine = bfd_mach_v850e3v5; 1611 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5); 1612 } 1613 else if (strcmp (arg, "v850e3v5") == 0) 1614 { 1615 machine = bfd_mach_v850e3v5; 1616 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5); 1617 } 1618 else if (strcmp (arg, "extension") == 0) 1619 { 1620 processor_mask |= PROCESSOR_OPTION_EXTENSION | PROCESSOR_OPTION_ALIAS; 1621 } 1622 else if (strcmp (arg, "no-bcond17") == 0) 1623 { 1624 no_bcond17 = 1; 1625 } 1626 else if (strcmp (arg, "no-stld23") == 0) 1627 { 1628 no_stld23 = 1; 1629 } 1630 else if (strcmp (arg, "relax") == 0) 1631 v850_relax = 1; 1632 else if (strcmp (arg, "gcc-abi") == 0) 1633 { 1634 v850_target_arch = bfd_arch_v850; 1635 v850_target_format = "elf32-v850"; 1636 } 1637 else if (strcmp (arg, "rh850-abi") == 0) 1638 { 1639 v850_target_arch = bfd_arch_v850_rh850; 1640 v850_target_format = "elf32-v850-rh850"; 1641 } 1642 else if (strcmp (arg, "8byte-align") == 0) 1643 { 1644 v850_data_8 = true; 1645 v850_e_flags |= EF_RH850_DATA_ALIGN8; 1646 } 1647 else if (strcmp (arg, "4byte-align") == 0) 1648 { 1649 v850_data_8 = false; 1650 v850_e_flags &= ~ EF_RH850_DATA_ALIGN8; 1651 } 1652 else if (strcmp (arg, "soft-float") == 0) 1653 soft_float = 1; 1654 else if (strcmp (arg, "hard-float") == 0) 1655 soft_float = 0; 1656 else 1657 return 0; 1658 1659 return 1; 1660 } 1661 1662 symbolS * 1663 md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 1664 { 1665 return 0; 1666 } 1667 1668 const char * 1669 md_atof (int type, char *litp, int *sizep) 1670 { 1671 return ieee_md_atof (type, litp, sizep, false); 1672 } 1673 1674 /* Very gross. */ 1675 1676 void 1677 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, 1678 asection *sec ATTRIBUTE_UNUSED, 1679 fragS *fragP) 1680 { 1681 unsigned int opindex = (uintptr_t) fragP->fr_opcode; 1682 1683 if (fragP->fr_subtype == SUBYPTE_LOOP_16_22) 1684 { 1685 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 1686 fragP->fr_offset, 1, BFD_RELOC_UNUSED + opindex); 1687 fragP->fr_fix += 4; 1688 } 1689 else if (fragP->fr_subtype == SUBYPTE_LOOP_16_22 + 1) 1690 { 1691 char *buffer = fragP->fr_literal + fragP->fr_fix; 1692 int loop_reg = buffer[0] & 0x1f; 1693 1694 /* Add -1.reg. */ 1695 md_number_to_chars (buffer, 0x025f | (loop_reg << 11), 2); 1696 /* Now create the conditional branch + fixup to the final target. */ 1697 /* 0x000107ea = bne LBL(disp17). */ 1698 md_number_to_chars (buffer + 2, 0x000107ea, 4); 1699 fix_new (fragP, fragP->fr_fix + 2, 4, fragP->fr_symbol, 1700 fragP->fr_offset, 1, BFD_RELOC_V850_17_PCREL); 1701 fragP->fr_fix += 6; 1702 } 1703 /* In range conditional or unconditional branch. */ 1704 else if (fragP->fr_subtype == SUBYPTE_COND_9_22 1705 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22 1706 || fragP->fr_subtype == SUBYPTE_COND_9_22_32 1707 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 1708 || fragP->fr_subtype == SUBYPTE_COND_9_17_22 1709 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 1710 || fragP->fr_subtype == SUBYPTE_SA_9_22 1711 || fragP->fr_subtype == SUBYPTE_SA_9_22_32 1712 || fragP->fr_subtype == SUBYPTE_SA_9_17_22 1713 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32) 1714 1715 { 1716 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 1717 fragP->fr_offset, 1, BFD_RELOC_UNUSED + opindex); 1718 fragP->fr_fix += 2; 1719 } 1720 /* V850e2r-v3 17bit conditional branch. */ 1721 else if (fragP->fr_subtype == SUBYPTE_COND_9_17_22 + 1 1722 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 1 1723 || fragP->fr_subtype == SUBYPTE_SA_9_17_22 + 1 1724 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 1) 1725 { 1726 char *buffer = fragP->fr_literal + fragP->fr_fix; 1727 1728 buffer[0] &= 0x0f; /* Use condition. */ 1729 buffer[0] |= 0xe0; 1730 buffer[1] = 0x07; 1731 1732 /* Now create the unconditional branch + fixup to the final 1733 target. */ 1734 md_number_to_chars (buffer + 2, 0x0001, 2); 1735 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 1736 fragP->fr_offset, 1, BFD_RELOC_V850_17_PCREL); 1737 fragP->fr_fix += 4; 1738 } 1739 /* Out of range conditional branch. Emit a branch around a 22bit jump. */ 1740 else if (fragP->fr_subtype == SUBYPTE_COND_9_22 + 1 1741 || fragP->fr_subtype == SUBYPTE_COND_9_22_32 + 1 1742 || fragP->fr_subtype == SUBYPTE_COND_9_17_22 + 2 1743 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 2) 1744 { 1745 char *buffer = fragP->fr_literal + fragP->fr_fix; 1746 1747 /* Reverse the condition of the first branch. */ 1748 buffer[0] ^= 0x08; 1749 /* Mask off all the displacement bits. */ 1750 buffer[0] &= 0x8f; 1751 buffer[1] &= 0x07; 1752 /* Now set the displacement bits so that we branch 1753 around the unconditional branch. */ 1754 buffer[0] |= 0x30; 1755 1756 /* Now create the unconditional branch + fixup to the final 1757 target. */ 1758 md_number_to_chars (buffer + 2, 0x00000780, 4); 1759 fix_new (fragP, fragP->fr_fix + 2, 4, fragP->fr_symbol, 1760 fragP->fr_offset, 1, BFD_RELOC_V850_22_PCREL); 1761 fragP->fr_fix += 6; 1762 } 1763 /* Out of range conditional branch. Emit a branch around a 32bit jump. */ 1764 else if (fragP->fr_subtype == SUBYPTE_COND_9_22_32 + 2 1765 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 3) 1766 { 1767 char *buffer = fragP->fr_literal + fragP->fr_fix; 1768 1769 /* Reverse the condition of the first branch. */ 1770 buffer[0] ^= 0x08; 1771 /* Mask off all the displacement bits. */ 1772 buffer[0] &= 0x8f; 1773 buffer[1] &= 0x07; 1774 /* Now set the displacement bits so that we branch 1775 around the unconditional branch. */ 1776 buffer[0] |= 0x40; 1777 1778 /* Now create the unconditional branch + fixup to the final 1779 target. */ 1780 md_number_to_chars (buffer + 2, 0x02e0, 2); 1781 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol, 1782 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL); 1783 fragP->fr_fix += 8; 1784 } 1785 /* Out of range unconditional branch. Emit a 22bit jump. */ 1786 else if (fragP->fr_subtype == SUBYPTE_UNCOND_9_22 + 1 1787 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 + 1) 1788 { 1789 md_number_to_chars (fragP->fr_fix + fragP->fr_literal, 0x00000780, 4); 1790 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 1791 fragP->fr_offset, 1, BFD_RELOC_V850_22_PCREL); 1792 fragP->fr_fix += 4; 1793 } 1794 /* Out of range unconditional branch. Emit a 32bit jump. */ 1795 else if (fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 + 2) 1796 { 1797 md_number_to_chars (fragP->fr_fix + fragP->fr_literal, 0x02e0, 2); 1798 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol, 1799 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL); 1800 fragP->fr_fix += 6; 1801 } 1802 /* Out of range SA conditional branch. Emit a branch to a 22bit jump. */ 1803 else if (fragP->fr_subtype == SUBYPTE_SA_9_22 + 1 1804 || fragP->fr_subtype == SUBYPTE_SA_9_22_32 + 1 1805 || fragP->fr_subtype == SUBYPTE_SA_9_17_22 + 2 1806 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 2) 1807 { 1808 char *buffer = fragP->fr_literal + fragP->fr_fix; 1809 1810 /* bsa .+4 */ 1811 buffer[0] &= 0x8f; 1812 buffer[0] |= 0x20; 1813 buffer[1] &= 0x07; 1814 1815 /* br .+6 */ 1816 md_number_to_chars (buffer + 2, 0x05b5, 2); 1817 1818 /* Now create the unconditional branch + fixup to the final 1819 target. */ 1820 /* jr SYM */ 1821 md_number_to_chars (buffer + 4, 0x00000780, 4); 1822 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol, 1823 fragP->fr_offset, 1, BFD_RELOC_V850_22_PCREL); 1824 fragP->fr_fix += 8; 1825 } 1826 /* Out of range SA conditional branch. Emit a branch around a 32bit jump. */ 1827 else if (fragP->fr_subtype == SUBYPTE_SA_9_22_32 + 2 1828 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 3) 1829 { 1830 char *buffer = fragP->fr_literal + fragP->fr_fix; 1831 1832 /* bsa .+2 */ 1833 buffer[0] &= 0x8f; 1834 buffer[0] |= 0x20; 1835 buffer[1] &= 0x07; 1836 1837 /* br .+8 */ 1838 md_number_to_chars (buffer + 2, 0x05c5, 2); 1839 1840 /* Now create the unconditional branch + fixup to the final 1841 target. */ 1842 /* jr SYM */ 1843 md_number_to_chars (buffer + 4, 0x02e0, 2); 1844 fix_new (fragP, fragP->fr_fix + 6, 4, fragP->fr_symbol, 1845 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL); 1846 1847 fragP->fr_fix += 10; 1848 } 1849 else 1850 abort (); 1851 } 1852 1853 valueT 1854 md_section_align (asection *seg, valueT addr) 1855 { 1856 int align = bfd_section_alignment (seg); 1857 return ((addr + (1 << align) - 1) & -(1 << align)); 1858 } 1859 1860 void 1861 md_begin (void) 1862 { 1863 const char *prev_name = ""; 1864 const struct v850_opcode *op; 1865 1866 if (startswith (TARGET_CPU, "v850e3v5")) 1867 { 1868 if (machine == -1) 1869 machine = bfd_mach_v850e3v5; 1870 1871 if (!processor_mask) 1872 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5); 1873 } 1874 else if (startswith (TARGET_CPU, "v850e2v4")) 1875 { 1876 if (machine == -1) 1877 machine = bfd_mach_v850e3v5; 1878 1879 if (!processor_mask) 1880 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5); 1881 } 1882 else if (startswith (TARGET_CPU, "v850e2v3")) 1883 { 1884 if (machine == -1) 1885 machine = bfd_mach_v850e2v3; 1886 1887 if (!processor_mask) 1888 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3); 1889 } 1890 else if (startswith (TARGET_CPU, "v850e2")) 1891 { 1892 if (machine == -1) 1893 machine = bfd_mach_v850e2; 1894 1895 if (!processor_mask) 1896 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2); 1897 } 1898 else if (startswith (TARGET_CPU, "v850e1")) 1899 { 1900 if (machine == -1) 1901 machine = bfd_mach_v850e1; 1902 1903 if (!processor_mask) 1904 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E1); 1905 } 1906 else if (startswith (TARGET_CPU, "v850e")) 1907 { 1908 if (machine == -1) 1909 machine = bfd_mach_v850e; 1910 1911 if (!processor_mask) 1912 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); 1913 } 1914 else if (startswith (TARGET_CPU, "v850")) 1915 { 1916 if (machine == -1) 1917 machine = 0; 1918 1919 if (!processor_mask) 1920 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); 1921 } 1922 else 1923 /* xgettext:c-format */ 1924 as_bad (_("Unable to determine default target processor from string: %s"), 1925 TARGET_CPU); 1926 1927 if (soft_float == -1) 1928 soft_float = machine < bfd_mach_v850e2v3; 1929 1930 v850_hash = str_htab_create (); 1931 1932 /* Insert unique names into hash table. The V850 instruction set 1933 has many identical opcode names that have different opcodes based 1934 on the operands. This hash table then provides a quick index to 1935 the first opcode with a particular name in the opcode table. */ 1936 op = v850_opcodes; 1937 while (op->name) 1938 { 1939 if (strcmp (prev_name, op->name)) 1940 { 1941 prev_name = op->name; 1942 str_hash_insert (v850_hash, op->name, op, 0); 1943 } 1944 op++; 1945 } 1946 1947 bfd_set_arch_mach (stdoutput, v850_target_arch, machine); 1948 bfd_set_private_flags (stdoutput, v850_e_flags); 1949 } 1950 1951 1952 static bfd_reloc_code_real_type 1953 handle_hi016 (const struct v850_operand *operand, const char **errmsg) 1954 { 1955 if (operand == NULL) 1956 return BFD_RELOC_HI16; 1957 1958 if (operand->default_reloc == BFD_RELOC_HI16) 1959 return BFD_RELOC_HI16; 1960 1961 if (operand->default_reloc == BFD_RELOC_HI16_S) 1962 return BFD_RELOC_HI16; 1963 1964 if (operand->default_reloc == BFD_RELOC_16) 1965 return BFD_RELOC_HI16; 1966 1967 *errmsg = _("hi0() relocation used on an instruction which does " 1968 "not support it"); 1969 return BFD_RELOC_64; /* Used to indicate an error condition. */ 1970 } 1971 1972 static bfd_reloc_code_real_type 1973 handle_hi16 (const struct v850_operand *operand, const char **errmsg) 1974 { 1975 if (operand == NULL) 1976 return BFD_RELOC_HI16_S; 1977 1978 if (operand->default_reloc == BFD_RELOC_HI16_S) 1979 return BFD_RELOC_HI16_S; 1980 1981 if (operand->default_reloc == BFD_RELOC_HI16) 1982 return BFD_RELOC_HI16_S; 1983 1984 if (operand->default_reloc == BFD_RELOC_16) 1985 return BFD_RELOC_HI16_S; 1986 1987 *errmsg = _("hi() relocation used on an instruction which does " 1988 "not support it"); 1989 return BFD_RELOC_64; /* Used to indicate an error condition. */ 1990 } 1991 1992 static bfd_reloc_code_real_type 1993 handle_lo16 (const struct v850_operand *operand, const char **errmsg) 1994 { 1995 if (operand == NULL) 1996 return BFD_RELOC_LO16; 1997 1998 switch (operand->default_reloc) 1999 { 2000 case BFD_RELOC_LO16: return BFD_RELOC_LO16; 2001 case BFD_RELOC_V850_LO16_SPLIT_OFFSET: return BFD_RELOC_V850_LO16_SPLIT_OFFSET; 2002 case BFD_RELOC_V850_16_SPLIT_OFFSET: return BFD_RELOC_V850_LO16_SPLIT_OFFSET; 2003 case BFD_RELOC_V850_16_S1: return BFD_RELOC_V850_LO16_S1; 2004 case BFD_RELOC_16: return BFD_RELOC_LO16; 2005 default: 2006 *errmsg = _("lo() relocation used on an instruction which does " 2007 "not support it"); 2008 return BFD_RELOC_64; /* Used to indicate an error condition. */ 2009 } 2010 } 2011 2012 static bfd_reloc_code_real_type 2013 handle_ctoff (const struct v850_operand *operand, const char **errmsg) 2014 { 2015 if (v850_target_arch == bfd_arch_v850_rh850) 2016 { 2017 *errmsg = _("ctoff() is not supported by the rh850 ABI. Use -mgcc-abi instead"); 2018 return BFD_RELOC_64; /* Used to indicate an error condition. */ 2019 } 2020 2021 if (operand == NULL) 2022 return BFD_RELOC_V850_CALLT_16_16_OFFSET; 2023 2024 if (operand->default_reloc == BFD_RELOC_V850_CALLT_6_7_OFFSET) 2025 return operand->default_reloc; 2026 2027 if (operand->default_reloc == BFD_RELOC_V850_16_S1) 2028 return BFD_RELOC_V850_CALLT_15_16_OFFSET; 2029 2030 if (operand->default_reloc == BFD_RELOC_16) 2031 return BFD_RELOC_V850_CALLT_16_16_OFFSET; 2032 2033 *errmsg = _("ctoff() relocation used on an instruction which does not support it"); 2034 return BFD_RELOC_64; /* Used to indicate an error condition. */ 2035 } 2036 2037 static bfd_reloc_code_real_type 2038 handle_sdaoff (const struct v850_operand *operand, const char **errmsg) 2039 { 2040 if (operand == NULL) 2041 return BFD_RELOC_V850_SDA_16_16_OFFSET; 2042 2043 if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET) 2044 return BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET; 2045 2046 if (operand->default_reloc == BFD_RELOC_16) 2047 return BFD_RELOC_V850_SDA_16_16_OFFSET; 2048 2049 if (operand->default_reloc == BFD_RELOC_V850_16_S1) 2050 return BFD_RELOC_V850_SDA_15_16_OFFSET; 2051 2052 *errmsg = _("sdaoff() relocation used on an instruction which does not support it"); 2053 return BFD_RELOC_64; /* Used to indicate an error condition. */ 2054 } 2055 2056 static bfd_reloc_code_real_type 2057 handle_zdaoff (const struct v850_operand *operand, const char **errmsg) 2058 { 2059 if (operand == NULL) 2060 return BFD_RELOC_V850_ZDA_16_16_OFFSET; 2061 2062 if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET) 2063 return BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET; 2064 2065 if (operand->default_reloc == BFD_RELOC_16) 2066 return BFD_RELOC_V850_ZDA_16_16_OFFSET; 2067 2068 if (operand->default_reloc == BFD_RELOC_V850_16_S1) 2069 return BFD_RELOC_V850_ZDA_15_16_OFFSET; 2070 2071 *errmsg = _("zdaoff() relocation used on an instruction which does not support it"); 2072 return BFD_RELOC_64; /* Used to indicate an error condition. */ 2073 } 2074 2075 static bfd_reloc_code_real_type 2076 handle_tdaoff (const struct v850_operand *operand, const char **errmsg) 2077 { 2078 if (operand == NULL) 2079 /* Data item, not an instruction. */ 2080 return BFD_RELOC_V850_TDA_16_16_OFFSET; 2081 2082 switch (operand->default_reloc) 2083 { 2084 /* sld.hu, operand: D5-4. */ 2085 case BFD_RELOC_V850_TDA_4_5_OFFSET: 2086 /* sld.bu, operand: D4. */ 2087 case BFD_RELOC_V850_TDA_4_4_OFFSET: 2088 /* sld.w/sst.w, operand: D8_6. */ 2089 case BFD_RELOC_V850_TDA_6_8_OFFSET: 2090 /* sld.h/sst.h, operand: D8_7. */ 2091 case BFD_RELOC_V850_TDA_7_8_OFFSET: 2092 /* sld.b/sst.b, operand: D7. */ 2093 case BFD_RELOC_V850_TDA_7_7_OFFSET: 2094 return operand->default_reloc; 2095 default: 2096 break; 2097 } 2098 2099 if (operand->default_reloc == BFD_RELOC_16 && operand->shift == 16) 2100 /* set1 & chums, operands: D16. */ 2101 return BFD_RELOC_V850_TDA_16_16_OFFSET; 2102 2103 *errmsg = _("tdaoff() relocation used on an instruction which does not support it"); 2104 /* Used to indicate an error condition. */ 2105 return BFD_RELOC_64; 2106 } 2107 2108 /* Warning: The code in this function relies upon the definitions 2109 in the v850_operands[] array (defined in opcodes/v850-opc.c) 2110 matching the hard coded values contained herein. */ 2111 2112 static bfd_reloc_code_real_type 2113 v850_reloc_prefix (const struct v850_operand *operand, const char **errmsg) 2114 { 2115 bool paren_skipped = false; 2116 2117 /* Skip leading opening parenthesis. */ 2118 if (*input_line_pointer == '(') 2119 { 2120 ++input_line_pointer; 2121 paren_skipped = true; 2122 } 2123 2124 #define CHECK_(name, reloc) \ 2125 if (strncmp (input_line_pointer, name "(", strlen (name) + 1) == 0) \ 2126 { \ 2127 input_line_pointer += strlen (name); \ 2128 return reloc; \ 2129 } 2130 2131 CHECK_ ("hi0", handle_hi016 (operand, errmsg)); 2132 CHECK_ ("hi", handle_hi16 (operand, errmsg)); 2133 CHECK_ ("lo", handle_lo16 (operand, errmsg)); 2134 CHECK_ ("sdaoff", handle_sdaoff (operand, errmsg)); 2135 CHECK_ ("zdaoff", handle_zdaoff (operand, errmsg)); 2136 CHECK_ ("tdaoff", handle_tdaoff (operand, errmsg)); 2137 CHECK_ ("hilo", BFD_RELOC_32); 2138 CHECK_ ("lo23", BFD_RELOC_V850_23); 2139 CHECK_ ("ctoff", handle_ctoff (operand, errmsg)); 2140 2141 /* Restore skipped parenthesis. */ 2142 if (paren_skipped) 2143 --input_line_pointer; 2144 2145 return BFD_RELOC_NONE; 2146 } 2147 2148 /* Insert an operand value into an instruction. */ 2149 2150 static unsigned long 2151 v850_insert_operand (unsigned long insn, 2152 const struct v850_operand *operand, 2153 offsetT val, 2154 const char **errmsg) 2155 { 2156 if (operand->insert) 2157 { 2158 const char *message = NULL; 2159 2160 insn = operand->insert (insn, val, &message); 2161 if (message != NULL) 2162 { 2163 if ((operand->flags & V850_OPERAND_SIGNED) 2164 && ! warn_signed_overflows 2165 && v850_msg_is_out_of_range (message)) 2166 { 2167 /* Skip warning... */ 2168 } 2169 else if ((operand->flags & V850_OPERAND_SIGNED) == 0 2170 && ! warn_unsigned_overflows 2171 && v850_msg_is_out_of_range (message)) 2172 { 2173 /* Skip warning... */ 2174 } 2175 else 2176 { 2177 if (errmsg != NULL) 2178 *errmsg = message; 2179 } 2180 } 2181 } 2182 else if (operand->bits == -1 2183 || operand->flags & V850E_IMMEDIATE16 2184 || operand->flags & V850E_IMMEDIATE23 2185 || operand->flags & V850E_IMMEDIATE32) 2186 { 2187 abort (); 2188 } 2189 else 2190 { 2191 if (operand->bits < 32) 2192 { 2193 long min, max; 2194 2195 if ((operand->flags & V850_OPERAND_SIGNED) != 0) 2196 { 2197 if (! warn_signed_overflows) 2198 max = (1 << operand->bits) - 1; 2199 else 2200 max = (1 << (operand->bits - 1)) - 1; 2201 2202 min = -(1 << (operand->bits - 1)); 2203 } 2204 else 2205 { 2206 max = (1 << operand->bits) - 1; 2207 2208 if (! warn_unsigned_overflows) 2209 min = -(1 << (operand->bits - 1)); 2210 else 2211 min = 0; 2212 } 2213 2214 /* Some people write constants with the sign extension done by 2215 hand but only up to 32 bits. This shouldn't really be valid, 2216 but, to permit this code to assemble on a 64-bit host, we 2217 sign extend the 32-bit value to 64 bits if so doing makes the 2218 value valid. */ 2219 if (val > max 2220 && (offsetT) (val - 0x80000000 - 0x80000000) >= min 2221 && (offsetT) (val - 0x80000000 - 0x80000000) <= max) 2222 val = val - 0x80000000 - 0x80000000; 2223 2224 /* Similarly, people write expressions like ~(1<<15), and expect 2225 this to be OK for a 32-bit unsigned value. */ 2226 else if (val < min 2227 && (offsetT) (val + 0x80000000 + 0x80000000) >= min 2228 && (offsetT) (val + 0x80000000 + 0x80000000) <= max) 2229 val = val + 0x80000000 + 0x80000000; 2230 2231 else if (val < (offsetT) min || val > (offsetT) max) 2232 { 2233 static char buf [128]; 2234 2235 /* Restore min and mix to expected values for decimal ranges. */ 2236 if ((operand->flags & V850_OPERAND_SIGNED) 2237 && ! warn_signed_overflows) 2238 max = (1 << (operand->bits - 1)) - 1; 2239 2240 if (! (operand->flags & V850_OPERAND_SIGNED) 2241 && ! warn_unsigned_overflows) 2242 min = 0; 2243 2244 sprintf (buf, _("operand out of range (%d is not between %d and %d)"), 2245 (int) val, (int) min, (int) max); 2246 *errmsg = buf; 2247 } 2248 2249 insn |= (((long) val & ((1 << operand->bits) - 1)) << operand->shift); 2250 } 2251 else 2252 { 2253 insn |= (((long) val) << operand->shift); 2254 } 2255 } 2256 2257 return insn; 2258 } 2259 2260 static char copy_of_instruction[128]; 2262 2263 void 2264 md_assemble (char *str) 2265 { 2266 char *s; 2267 char *start_of_operands; 2268 struct v850_opcode *opcode; 2269 struct v850_opcode *next_opcode; 2270 const unsigned char *opindex_ptr; 2271 int next_opindex; 2272 int relaxable = 0; 2273 unsigned long insn = 0; 2274 unsigned long insn_size; 2275 char *f = NULL; 2276 int i; 2277 int match; 2278 bool extra_data_after_insn = false; 2279 unsigned extra_data_len = 0; 2280 unsigned long extra_data = 0; 2281 char *saved_input_line_pointer; 2282 char most_match_errmsg[1024]; 2283 int most_match_count = -1; 2284 2285 strncpy (copy_of_instruction, str, sizeof (copy_of_instruction) - 1); 2286 most_match_errmsg[0] = 0; 2287 2288 /* Get the opcode. */ 2289 for (s = str; ! is_end_of_stmt (*s) && ! is_whitespace (*s); s++) 2290 continue; 2291 2292 if (*s != '\0') 2293 *s++ = '\0'; 2294 2295 /* Find the first opcode with the proper name. */ 2296 opcode = str_hash_find (v850_hash, str); 2297 if (opcode == NULL) 2298 { 2299 /* xgettext:c-format */ 2300 as_bad (_("Unrecognized opcode: `%s'"), str); 2301 ignore_rest_of_line (); 2302 return; 2303 } 2304 2305 str = s; 2306 while (is_whitespace (*str)) 2307 ++str; 2308 2309 start_of_operands = str; 2310 2311 saved_input_line_pointer = input_line_pointer; 2312 2313 for (;;) 2314 { 2315 const char *errmsg = NULL; 2316 const char *warningmsg = NULL; 2317 2318 match = 0; 2319 opindex_ptr = opcode->operands; 2320 2321 if (no_stld23) 2322 { 2323 if ((startswith (opcode->name, "st.") 2324 && v850_operands[opcode->operands[1]].bits == 23) 2325 || (startswith (opcode->name, "ld.") 2326 && v850_operands[opcode->operands[0]].bits == 23)) 2327 { 2328 errmsg = _("st/ld offset 23 instruction was disabled ."); 2329 goto error; 2330 } 2331 } 2332 2333 if ((opcode->processors & processor_mask & PROCESSOR_MASK) == 0 2334 || (((opcode->processors & ~PROCESSOR_MASK) != 0) 2335 && ((opcode->processors & processor_mask & ~PROCESSOR_MASK) == 0))) 2336 { 2337 errmsg = _("Target processor does not support this instruction."); 2338 goto error; 2339 } 2340 2341 relaxable = 0; 2342 fc = 0; 2343 next_opindex = 0; 2344 insn = opcode->opcode; 2345 extra_data_len = 0; 2346 extra_data_after_insn = false; 2347 2348 input_line_pointer = str = start_of_operands; 2349 2350 for (opindex_ptr = opcode->operands; *opindex_ptr != 0; opindex_ptr++) 2351 { 2352 const struct v850_operand *operand; 2353 char *hold; 2354 expressionS ex; 2355 bfd_reloc_code_real_type reloc; 2356 2357 if (next_opindex == 0) 2358 operand = &v850_operands[*opindex_ptr]; 2359 else 2360 { 2361 operand = &v850_operands[next_opindex]; 2362 next_opindex = 0; 2363 } 2364 2365 errmsg = NULL; 2366 2367 while (is_whitespace (*str)) 2368 ++str; 2369 2370 if (operand->flags & V850_OPERAND_BANG 2371 && *str == '!') 2372 ++str; 2373 else if (operand->flags & V850_OPERAND_PERCENT 2374 && *str == '%') 2375 ++str; 2376 2377 if (*str == ',' || *str == '[' || *str == ']') 2378 ++str; 2379 2380 while (is_whitespace (*str)) 2381 ++str; 2382 2383 if ( (strcmp (opcode->name, "pushsp") == 0 2384 || strcmp (opcode->name, "popsp") == 0 2385 || strcmp (opcode->name, "dbpush") == 0) 2386 && (*str == '-')) 2387 ++str; 2388 2389 if (operand->flags & V850_OPERAND_RELAX) 2390 relaxable = 1; 2391 2392 /* Gather the operand. */ 2393 hold = input_line_pointer; 2394 input_line_pointer = str; 2395 2396 /* lo(), hi(), hi0(), etc... */ 2397 if ((reloc = v850_reloc_prefix (operand, &errmsg)) != BFD_RELOC_NONE) 2398 { 2399 /* This is a fake reloc, used to indicate an error condition. */ 2400 if (reloc == BFD_RELOC_64) 2401 { 2402 /* match = 1; */ 2403 goto error; 2404 } 2405 2406 expression (&ex); 2407 2408 if (ex.X_op == O_constant) 2409 { 2410 switch (reloc) 2411 { 2412 case BFD_RELOC_V850_ZDA_16_16_OFFSET: 2413 case BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET: 2414 case BFD_RELOC_V850_ZDA_15_16_OFFSET: 2415 /* To cope with "not1 7, zdaoff(0xfffff006)[r0]" 2416 and the like. */ 2417 /* Fall through. */ 2418 2419 case BFD_RELOC_LO16: 2420 case BFD_RELOC_V850_LO16_S1: 2421 case BFD_RELOC_V850_LO16_SPLIT_OFFSET: 2422 { 2423 /* Truncate, then sign extend the value. */ 2424 ex.X_add_number = SEXT16 (ex.X_add_number); 2425 break; 2426 } 2427 2428 case BFD_RELOC_HI16: 2429 { 2430 /* Truncate, then sign extend the value. */ 2431 ex.X_add_number = SEXT16 (ex.X_add_number >> 16); 2432 break; 2433 } 2434 2435 case BFD_RELOC_HI16_S: 2436 { 2437 /* Truncate, then sign extend the value. */ 2438 int temp = (ex.X_add_number >> 16) & 0xffff; 2439 2440 temp += (ex.X_add_number >> 15) & 1; 2441 2442 ex.X_add_number = SEXT16 (temp); 2443 break; 2444 } 2445 2446 case BFD_RELOC_V850_23: 2447 if ((operand->flags & V850E_IMMEDIATE23) == 0) 2448 { 2449 errmsg = _("immediate operand is too large"); 2450 goto error; 2451 } 2452 break; 2453 2454 case BFD_RELOC_32: 2455 case BFD_RELOC_V850_32_ABS: 2456 case BFD_RELOC_V850_32_PCREL: 2457 if ((operand->flags & V850E_IMMEDIATE32) == 0) 2458 { 2459 errmsg = _("immediate operand is too large"); 2460 goto error; 2461 } 2462 2463 break; 2464 2465 default: 2466 as_bad (_("AAARG -> unhandled constant reloc: %d"), reloc); 2467 break; 2468 } 2469 2470 if (operand->flags & V850E_IMMEDIATE32) 2471 { 2472 extra_data_after_insn = true; 2473 extra_data_len = 4; 2474 extra_data = 0; 2475 } 2476 else if (operand->flags & V850E_IMMEDIATE23) 2477 { 2478 if (reloc != BFD_RELOC_V850_23) 2479 { 2480 errmsg = _("immediate operand is too large"); 2481 goto error; 2482 } 2483 extra_data_after_insn = true; 2484 extra_data_len = 2; 2485 extra_data = 0; 2486 } 2487 else if ((operand->flags & V850E_IMMEDIATE16) 2488 || (operand->flags & V850E_IMMEDIATE16HI)) 2489 { 2490 if (operand->flags & V850E_IMMEDIATE16HI 2491 && reloc != BFD_RELOC_HI16 2492 && reloc != BFD_RELOC_HI16_S) 2493 { 2494 errmsg = _("immediate operand is too large"); 2495 goto error; 2496 } 2497 else if (operand->flags & V850E_IMMEDIATE16 2498 && reloc != BFD_RELOC_LO16) 2499 { 2500 errmsg = _("immediate operand is too large"); 2501 goto error; 2502 } 2503 2504 extra_data_after_insn = true; 2505 extra_data_len = 2; 2506 extra_data = 0; 2507 } 2508 2509 if (fc > MAX_INSN_FIXUPS) 2510 as_fatal (_("too many fixups")); 2511 2512 fixups[fc].exp = ex; 2513 fixups[fc].opindex = *opindex_ptr; 2514 fixups[fc].reloc = reloc; 2515 fc++; 2516 } 2517 else /* ex.X_op != O_constant. */ 2518 { 2519 if ((reloc == BFD_RELOC_32 2520 || reloc == BFD_RELOC_V850_32_ABS 2521 || reloc == BFD_RELOC_V850_32_PCREL) 2522 && operand->bits < 32) 2523 { 2524 errmsg = _("immediate operand is too large"); 2525 goto error; 2526 } 2527 else if (reloc == BFD_RELOC_V850_23 2528 && (operand->flags & V850E_IMMEDIATE23) == 0) 2529 { 2530 errmsg = _("immediate operand is too large"); 2531 goto error; 2532 } 2533 else if ((reloc == BFD_RELOC_HI16 2534 || reloc == BFD_RELOC_HI16_S) 2535 && operand->bits < 16) 2536 { 2537 errmsg = _("immediate operand is too large"); 2538 goto error; 2539 } 2540 2541 if (operand->flags & V850E_IMMEDIATE32) 2542 { 2543 extra_data_after_insn = true; 2544 extra_data_len = 4; 2545 extra_data = 0; 2546 } 2547 else if (operand->flags & V850E_IMMEDIATE23) 2548 { 2549 if (reloc != BFD_RELOC_V850_23) 2550 { 2551 errmsg = _("immediate operand is too large"); 2552 goto error; 2553 } 2554 extra_data_after_insn = true; 2555 extra_data_len = 2; 2556 extra_data = 0; 2557 } 2558 else if ((operand->flags & V850E_IMMEDIATE16) 2559 || (operand->flags & V850E_IMMEDIATE16HI)) 2560 { 2561 if (operand->flags & V850E_IMMEDIATE16HI 2562 && reloc != BFD_RELOC_HI16 2563 && reloc != BFD_RELOC_HI16_S) 2564 { 2565 errmsg = _("immediate operand is too large"); 2566 goto error; 2567 } 2568 else if (operand->flags & V850E_IMMEDIATE16 2569 && reloc != BFD_RELOC_LO16) 2570 { 2571 errmsg = _("immediate operand is too large"); 2572 goto error; 2573 } 2574 2575 extra_data_after_insn = true; 2576 extra_data_len = 2; 2577 extra_data = 0; 2578 } 2579 2580 if (fc > MAX_INSN_FIXUPS) 2581 as_fatal (_("too many fixups")); 2582 2583 fixups[fc].exp = ex; 2584 fixups[fc].opindex = *opindex_ptr; 2585 fixups[fc].reloc = reloc; 2586 fc++; 2587 } 2588 } 2589 else if (operand->flags & V850E_IMMEDIATE16 2590 || operand->flags & V850E_IMMEDIATE16HI) 2591 { 2592 expression (&ex); 2593 2594 switch (ex.X_op) 2595 { 2596 case O_constant: 2597 if (operand->flags & V850E_IMMEDIATE16HI) 2598 { 2599 if (ex.X_add_number & 0xffff) 2600 { 2601 errmsg = _("constant too big to fit into instruction"); 2602 goto error; 2603 } 2604 2605 ex.X_add_number >>= 16; 2606 } 2607 if (operand->flags & V850E_IMMEDIATE16) 2608 { 2609 if ((ex.X_add_number & 0xffff8000) 2610 && ((ex.X_add_number & 0xffff8000) != 0xffff8000)) 2611 { 2612 errmsg = _("constant too big to fit into instruction"); 2613 goto error; 2614 } 2615 } 2616 break; 2617 2618 case O_illegal: 2619 errmsg = _("illegal operand"); 2620 goto error; 2621 2622 case O_absent: 2623 errmsg = _("missing operand"); 2624 goto error; 2625 2626 default: 2627 if (fc >= MAX_INSN_FIXUPS) 2628 as_fatal (_("too many fixups")); 2629 2630 fixups[fc].exp = ex; 2631 fixups[fc].opindex = *opindex_ptr; 2632 fixups[fc].reloc = operand->default_reloc; 2633 ++fc; 2634 2635 ex.X_add_number = 0; 2636 break; 2637 } 2638 2639 extra_data_after_insn = true; 2640 extra_data_len = 2; 2641 extra_data = ex.X_add_number; 2642 } 2643 else if (operand->flags & V850E_IMMEDIATE23) 2644 { 2645 expression (&ex); 2646 2647 switch (ex.X_op) 2648 { 2649 case O_constant: 2650 break; 2651 2652 case O_illegal: 2653 errmsg = _("illegal operand"); 2654 goto error; 2655 2656 case O_absent: 2657 errmsg = _("missing operand"); 2658 goto error; 2659 2660 default: 2661 break; 2662 } 2663 2664 if (fc >= MAX_INSN_FIXUPS) 2665 as_fatal (_("too many fixups")); 2666 2667 fixups[fc].exp = ex; 2668 fixups[fc].opindex = *opindex_ptr; 2669 fixups[fc].reloc = operand->default_reloc; 2670 ++fc; 2671 2672 extra_data_after_insn = true; 2673 extra_data_len = 2; 2674 extra_data = 0; 2675 } 2676 else if (operand->flags & V850E_IMMEDIATE32) 2677 { 2678 expression (&ex); 2679 2680 switch (ex.X_op) 2681 { 2682 case O_constant: 2683 if ((operand->default_reloc == BFD_RELOC_V850_32_ABS 2684 || operand->default_reloc == BFD_RELOC_V850_32_PCREL) 2685 && (ex.X_add_number & 1)) 2686 { 2687 errmsg = _("odd number cannot be used here"); 2688 goto error; 2689 } 2690 break; 2691 2692 case O_illegal: 2693 errmsg = _("illegal operand"); 2694 goto error; 2695 2696 case O_absent: 2697 errmsg = _("missing operand"); 2698 goto error; 2699 2700 default: 2701 if (fc >= MAX_INSN_FIXUPS) 2702 as_fatal (_("too many fixups")); 2703 2704 fixups[fc].exp = ex; 2705 fixups[fc].opindex = *opindex_ptr; 2706 fixups[fc].reloc = operand->default_reloc; 2707 ++fc; 2708 2709 ex.X_add_number = 0; 2710 break; 2711 } 2712 2713 extra_data_after_insn = true; 2714 extra_data_len = 4; 2715 extra_data = ex.X_add_number; 2716 } 2717 else if (operand->flags & V850E_OPERAND_REG_LIST) 2718 { 2719 errmsg = parse_register_list (&insn, operand); 2720 2721 if (errmsg) 2722 goto error; 2723 } 2724 else 2725 { 2726 errmsg = NULL; 2727 2728 if ((operand->flags & V850_OPERAND_REG) != 0) 2729 { 2730 if (!register_name (&ex)) 2731 { 2732 errmsg = _("invalid register name"); 2733 } 2734 2735 if ((operand->flags & V850_NOT_R0) 2736 && ex.X_add_number == 0) 2737 { 2738 errmsg = _("register r0 cannot be used here"); 2739 } 2740 2741 if (operand->flags & V850_REG_EVEN) 2742 { 2743 if (ex.X_add_number % 2) 2744 errmsg = _("odd register cannot be used here"); 2745 ex.X_add_number = ex.X_add_number / 2; 2746 } 2747 2748 } 2749 else if ((operand->flags & V850_OPERAND_SRG) != 0) 2750 { 2751 if (!system_register_name (&ex, true)) 2752 { 2753 errmsg = _("invalid system register name"); 2754 } 2755 } 2756 else if ((operand->flags & V850_OPERAND_EP) != 0) 2757 { 2758 char *start = input_line_pointer; 2759 char *name; 2760 char c = get_symbol_name (&name); 2761 2762 if (strcmp (name, "ep") != 0 && strcmp (name, "r30") != 0) 2763 { 2764 /* Put things back the way we found them. */ 2765 (void) restore_line_pointer (c); 2766 input_line_pointer = start; 2767 errmsg = _("expected EP register"); 2768 goto error; 2769 } 2770 2771 (void) restore_line_pointer (c); 2772 str = input_line_pointer; 2773 input_line_pointer = hold; 2774 2775 while (is_whitespace (*str) || *str == ',' 2776 || *str == '[' || *str == ']') 2777 ++str; 2778 continue; 2779 } 2780 else if ((operand->flags & V850_OPERAND_CC) != 0) 2781 { 2782 if (!cc_name (&ex, true)) 2783 { 2784 errmsg = _("invalid condition code name"); 2785 } 2786 2787 if ((operand->flags & V850_NOT_SA) 2788 && ex.X_add_number == COND_SA_NUM) 2789 { 2790 errmsg = _("condition sa cannot be used here"); 2791 } 2792 } 2793 else if ((operand->flags & V850_OPERAND_FLOAT_CC) != 0) 2794 { 2795 if (!float_cc_name (&ex, true)) 2796 { 2797 errmsg = _("invalid condition code name"); 2798 } 2799 } 2800 else if ((operand->flags & V850_OPERAND_CACHEOP) != 0) 2801 { 2802 if (!cacheop_name (&ex, true)) 2803 errmsg = _("invalid cache operation name"); 2804 } 2805 else if ((operand->flags & V850_OPERAND_PREFOP) != 0) 2806 { 2807 if (!prefop_name (&ex, true)) 2808 errmsg = _("invalid pref operation name"); 2809 } 2810 else if ((operand->flags & V850_OPERAND_VREG) != 0) 2811 { 2812 if (!vector_register_name (&ex)) 2813 errmsg = _("invalid vector register name"); 2814 } 2815 else if ((register_name (&ex) 2816 && (operand->flags & V850_OPERAND_REG) == 0)) 2817 { 2818 char *name; 2819 char c; 2820 int exists = 0; 2821 2822 /* It is possible that an alias has been defined that 2823 matches a register name. For example the code may 2824 include a ".set ZERO, 0" directive, which matches 2825 the register name "zero". Attempt to reparse the 2826 field as an expression, and only complain if we 2827 cannot generate a constant. */ 2828 2829 input_line_pointer = str; 2830 2831 c = get_symbol_name (&name); 2832 2833 if (symbol_find (name) != NULL) 2834 exists = 1; 2835 2836 (void) restore_line_pointer (c); 2837 input_line_pointer = str; 2838 2839 expression (&ex); 2840 2841 if (ex.X_op != O_constant) 2842 { 2843 /* If this register is actually occurring too early on 2844 the parsing of the instruction, (because another 2845 field is missing) then report this. */ 2846 if (opindex_ptr[1] != 0 2847 && ((v850_operands[opindex_ptr[1]].flags 2848 & V850_OPERAND_REG) 2849 ||(v850_operands[opindex_ptr[1]].flags 2850 & V850_OPERAND_VREG))) 2851 errmsg = _("syntax error: value is missing before the register name"); 2852 else 2853 errmsg = _("syntax error: register not expected"); 2854 2855 /* If we created a symbol in the process of this 2856 test then delete it now, so that it will not 2857 be output with the real symbols... */ 2858 if (exists == 0 2859 && ex.X_op == O_symbol) 2860 symbol_remove (ex.X_add_symbol, 2861 &symbol_rootP, &symbol_lastP); 2862 } 2863 } 2864 else if (system_register_name (&ex, false) 2865 && (operand->flags & V850_OPERAND_SRG) == 0) 2866 { 2867 errmsg = _("syntax error: system register not expected"); 2868 } 2869 else if (cc_name (&ex, false) 2870 && (operand->flags & V850_OPERAND_CC) == 0) 2871 { 2872 errmsg = _("syntax error: condition code not expected"); 2873 } 2874 else if (float_cc_name (&ex, false) 2875 && (operand->flags & V850_OPERAND_FLOAT_CC) == 0) 2876 { 2877 errmsg = _("syntax error: condition code not expected"); 2878 } 2879 else if (vector_register_name (&ex) 2880 && (operand->flags & V850_OPERAND_VREG) == 0) 2881 { 2882 errmsg = _("syntax error: vector register not expected"); 2883 } 2884 else 2885 { 2886 expression (&ex); 2887 resolve_register (&ex); 2888 2889 if ((operand->flags & V850_NOT_IMM0) 2890 && ex.X_op == O_constant 2891 && ex.X_add_number == 0) 2892 { 2893 errmsg = _("immediate 0 cannot be used here"); 2894 } 2895 2896 /* Special case: 2897 If we are assembling a MOV/JARL/JR instruction and the immediate 2898 value does not fit into the bits available then create a 2899 fake error so that the next MOV/JARL/JR instruction will be 2900 selected. This one has a 32 bit immediate field. */ 2901 2902 if ((strcmp (opcode->name, "mov") == 0 2903 || strcmp (opcode->name, "jarl") == 0 2904 || strcmp (opcode->name, "jr") == 0) 2905 && ex.X_op == O_constant 2906 && (ex.X_add_number < (-(1 << (operand->bits - 1))) 2907 || ex.X_add_number > ((1 << (operand->bits - 1)) - 1))) 2908 { 2909 errmsg = _("immediate operand is too large"); 2910 } 2911 2912 if ((strcmp (opcode->name, "jarl") == 0 2913 || strcmp (opcode->name, "jr") == 0) 2914 && ex.X_op != O_constant 2915 && operand->bits != default_disp_size) 2916 { 2917 errmsg = _("immediate operand is not match"); 2918 } 2919 2920 /* Special case2 : 2921 If we are assembling a ld/st instruction and the immediate 2922 value does not fit into the bits available then create a 2923 fake error so that the next ld/st instruction will be 2924 selected. */ 2925 if ( ( (startswith (opcode->name, "st.")) 2926 || (startswith (opcode->name, "ld."))) 2927 && ex.X_op == O_constant 2928 && (ex.X_add_number < (-(1 << (operand->bits - 1))) 2929 || ex.X_add_number > ((1 << (operand->bits - 1)) - 1))) 2930 errmsg = _("displacement is too large"); 2931 } 2932 2933 if (errmsg) 2934 goto error; 2935 2936 switch (ex.X_op) 2937 { 2938 case O_illegal: 2939 errmsg = _("illegal operand"); 2940 goto error; 2941 case O_absent: 2942 errmsg = _("missing operand"); 2943 goto error; 2944 case O_register: 2945 if ((operand->flags 2946 & (V850_OPERAND_REG | V850_OPERAND_SRG | V850_OPERAND_VREG)) == 0) 2947 { 2948 errmsg = _("invalid operand"); 2949 goto error; 2950 } 2951 2952 insn = v850_insert_operand (insn, operand, 2953 ex.X_add_number, 2954 &warningmsg); 2955 2956 break; 2957 2958 case O_constant: 2959 insn = v850_insert_operand (insn, operand, ex.X_add_number, 2960 &warningmsg); 2961 break; 2962 2963 default: 2964 /* We need to generate a fixup for this expression. */ 2965 if (fc >= MAX_INSN_FIXUPS) 2966 as_fatal (_("too many fixups")); 2967 2968 fixups[fc].exp = ex; 2969 fixups[fc].opindex = *opindex_ptr; 2970 fixups[fc].reloc = BFD_RELOC_NONE; 2971 ++fc; 2972 break; 2973 } 2974 } 2975 2976 str = input_line_pointer; 2977 input_line_pointer = hold; 2978 2979 while (is_whitespace (*str) || *str == ',' || *str == '[' || *str == ']' 2980 || *str == ')') 2981 ++str; 2982 } 2983 2984 while (is_whitespace (*str)) 2985 ++str; 2986 2987 if (*str == '\0') 2988 match = 1; 2989 2990 error: 2991 if (match == 0) 2992 { 2993 if ((opindex_ptr - opcode->operands) >= most_match_count) 2994 { 2995 most_match_count = opindex_ptr - opcode->operands; 2996 if (errmsg != NULL) 2997 strncpy (most_match_errmsg, errmsg, sizeof (most_match_errmsg)-1); 2998 } 2999 3000 next_opcode = opcode + 1; 3001 if (next_opcode->name != NULL 3002 && strcmp (next_opcode->name, opcode->name) == 0) 3003 { 3004 opcode = next_opcode; 3005 3006 /* Skip versions that are not supported by the target 3007 processor. */ 3008 if ((opcode->processors & processor_mask) == 0) 3009 goto error; 3010 3011 continue; 3012 } 3013 3014 if (most_match_errmsg[0] == 0) 3015 /* xgettext:c-format. */ 3016 as_bad (_("junk at end of line: `%s'"), str); 3017 else 3018 as_bad ("%s: %s", copy_of_instruction, most_match_errmsg); 3019 3020 if (*input_line_pointer == ']') 3021 ++input_line_pointer; 3022 3023 ignore_rest_of_line (); 3024 input_line_pointer = saved_input_line_pointer; 3025 return; 3026 } 3027 3028 if (warningmsg != NULL) 3029 as_warn ("%s", warningmsg); 3030 break; 3031 } 3032 3033 input_line_pointer = str; 3034 3035 /* Tie dwarf2 debug info to the address at the start of the insn. 3036 We can't do this after the insn has been output as the current 3037 frag may have been closed off. eg. by frag_var. */ 3038 dwarf2_emit_insn (0); 3039 3040 /* Write out the instruction. */ 3041 if (relaxable && fc > 0) 3042 { 3043 insn_size = 2; 3044 fc = 0; 3045 3046 if (strcmp (opcode->name, "loop") == 0) 3047 { 3048 if (((processor_mask & PROCESSOR_V850E3V5_UP) == 0) || default_disp_size == 22) 3049 { 3050 insn_size = 4; 3051 f = frag_var (rs_machine_dependent, 6, 2, SUBYPTE_LOOP_16_22, 3052 fixups[0].exp.X_add_symbol, 3053 fixups[0].exp.X_add_number, 3054 (char *) (uintptr_t) fixups[0].opindex); 3055 md_number_to_chars (f, insn, insn_size); 3056 md_number_to_chars (f+4, 0, 4); 3057 } 3058 else 3059 { 3060 as_bad (_("loop: 32-bit displacement not supported")); 3061 } 3062 } 3063 else if (strcmp (opcode->name, "br") == 0 3064 || strcmp (opcode->name, "jbr") == 0) 3065 { 3066 if ((processor_mask & PROCESSOR_V850E2_UP) == 0 || default_disp_size == 22) 3067 { 3068 f = frag_var (rs_machine_dependent, 4, 2, SUBYPTE_UNCOND_9_22, 3069 fixups[0].exp.X_add_symbol, 3070 fixups[0].exp.X_add_number, 3071 (char *) (uintptr_t) fixups[0].opindex); 3072 md_number_to_chars (f, insn, insn_size); 3073 md_number_to_chars (f + 2, 0, 2); 3074 } 3075 else 3076 { 3077 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_UNCOND_9_22_32, 3078 fixups[0].exp.X_add_symbol, 3079 fixups[0].exp.X_add_number, 3080 (char *) (uintptr_t) fixups[0].opindex); 3081 md_number_to_chars (f, insn, insn_size); 3082 md_number_to_chars (f + 2, 0, 4); 3083 } 3084 } 3085 else /* b<cond>, j<cond>. */ 3086 { 3087 if (default_disp_size == 22 3088 || (processor_mask & PROCESSOR_V850E2_UP) == 0) 3089 { 3090 if (processor_mask & PROCESSOR_V850E2V3_UP && !no_bcond17) 3091 { 3092 if (strcmp (opcode->name, "bsa") == 0) 3093 { 3094 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_SA_9_17_22, 3095 fixups[0].exp.X_add_symbol, 3096 fixups[0].exp.X_add_number, 3097 (char *) (uintptr_t) fixups[0].opindex); 3098 md_number_to_chars (f, insn, insn_size); 3099 md_number_to_chars (f + 2, 0, 6); 3100 } 3101 else 3102 { 3103 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_COND_9_17_22, 3104 fixups[0].exp.X_add_symbol, 3105 fixups[0].exp.X_add_number, 3106 (char *) (uintptr_t) fixups[0].opindex); 3107 md_number_to_chars (f, insn, insn_size); 3108 md_number_to_chars (f + 2, 0, 4); 3109 } 3110 } 3111 else 3112 { 3113 if (strcmp (opcode->name, "bsa") == 0) 3114 { 3115 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_SA_9_22, 3116 fixups[0].exp.X_add_symbol, 3117 fixups[0].exp.X_add_number, 3118 (char *) (uintptr_t) fixups[0].opindex); 3119 md_number_to_chars (f, insn, insn_size); 3120 md_number_to_chars (f + 2, 0, 6); 3121 } 3122 else 3123 { 3124 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_COND_9_22, 3125 fixups[0].exp.X_add_symbol, 3126 fixups[0].exp.X_add_number, 3127 (char *) (uintptr_t) fixups[0].opindex); 3128 md_number_to_chars (f, insn, insn_size); 3129 md_number_to_chars (f + 2, 0, 4); 3130 } 3131 } 3132 } 3133 else 3134 { 3135 if (processor_mask & PROCESSOR_V850E2V3_UP && !no_bcond17) 3136 { 3137 if (strcmp (opcode->name, "bsa") == 0) 3138 { 3139 f = frag_var (rs_machine_dependent, 10, 8, SUBYPTE_SA_9_17_22_32, 3140 fixups[0].exp.X_add_symbol, 3141 fixups[0].exp.X_add_number, 3142 (char *) (uintptr_t) fixups[0].opindex); 3143 md_number_to_chars (f, insn, insn_size); 3144 md_number_to_chars (f + 2, 0, 8); 3145 } 3146 else 3147 { 3148 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_COND_9_17_22_32, 3149 fixups[0].exp.X_add_symbol, 3150 fixups[0].exp.X_add_number, 3151 (char *) (uintptr_t) fixups[0].opindex); 3152 md_number_to_chars (f, insn, insn_size); 3153 md_number_to_chars (f + 2, 0, 6); 3154 } 3155 } 3156 else 3157 { 3158 if (strcmp (opcode->name, "bsa") == 0) 3159 { 3160 f = frag_var (rs_machine_dependent, 10, 8, SUBYPTE_SA_9_22_32, 3161 fixups[0].exp.X_add_symbol, 3162 fixups[0].exp.X_add_number, 3163 (char *) (uintptr_t) fixups[0].opindex); 3164 md_number_to_chars (f, insn, insn_size); 3165 md_number_to_chars (f + 2, 0, 8); 3166 } 3167 else 3168 { 3169 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_COND_9_22_32, 3170 fixups[0].exp.X_add_symbol, 3171 fixups[0].exp.X_add_number, 3172 (char *) (uintptr_t) fixups[0].opindex); 3173 md_number_to_chars (f, insn, insn_size); 3174 md_number_to_chars (f + 2, 0, 6); 3175 } 3176 } 3177 } 3178 } 3179 } 3180 else 3181 { 3182 /* Four byte insns have an opcode with the two high bits on. */ 3183 if ((insn & 0x0600) == 0x0600) 3184 insn_size = 4; 3185 else 3186 insn_size = 2; 3187 3188 /* Special case: 32 bit MOV. */ 3189 if ((insn & 0xffe0) == 0x0620) 3190 insn_size = 2; 3191 3192 /* Special case: 32 bit JARL,JMP,JR. */ 3193 if ((insn & 0x1ffe0) == 0x2e0 /* JARL. */ 3194 || (insn & 0x1ffe0) == 0x6e0 /* JMP. */ 3195 || (insn & 0x1ffff) == 0x2e0) /* JR. */ 3196 insn_size = 2; 3197 3198 if (obstack_room (& frchain_now->frch_obstack) < (insn_size + extra_data_len)) 3199 { 3200 frag_wane (frag_now); 3201 frag_new (0); 3202 } 3203 3204 f = frag_more (insn_size); 3205 md_number_to_chars (f, insn, insn_size); 3206 3207 if (extra_data_after_insn) 3208 { 3209 f = frag_more (extra_data_len); 3210 md_number_to_chars (f, extra_data, extra_data_len); 3211 3212 extra_data_after_insn = false; 3213 } 3214 } 3215 3216 /* Create any fixups. At this point we do not use a 3217 bfd_reloc_code_real_type, but instead just use the 3218 BFD_RELOC_UNUSED plus the operand index. This lets us easily 3219 handle fixups for any operand type, although that is admittedly 3220 not a very exciting feature. We pick a BFD reloc type in 3221 md_apply_fix. */ 3222 for (i = 0; i < fc; i++) 3223 { 3224 const struct v850_operand *operand; 3225 bfd_reloc_code_real_type reloc; 3226 3227 operand = &v850_operands[fixups[i].opindex]; 3228 3229 reloc = fixups[i].reloc; 3230 3231 if (reloc != BFD_RELOC_NONE) 3232 { 3233 reloc_howto_type *reloc_howto = 3234 bfd_reloc_type_lookup (stdoutput, reloc); 3235 int size; 3236 int address; 3237 fixS *fixP; 3238 3239 if (!reloc_howto) 3240 abort (); 3241 3242 size = bfd_get_reloc_size (reloc_howto); 3243 3244 /* XXX This will abort on an R_V850_8 reloc - 3245 is this reloc actually used? */ 3246 if (size != 2 && size != 4) 3247 abort (); 3248 3249 if (extra_data_len == 0) 3250 { 3251 address = (f - frag_now->fr_literal) + insn_size - size; 3252 } 3253 else 3254 { 3255 address = (f - frag_now->fr_literal) + extra_data_len - size; 3256 } 3257 3258 if ((operand->flags & V850E_IMMEDIATE32) && (operand->flags & V850_PCREL)) 3259 { 3260 fixups[i].exp.X_add_number += 2; 3261 } 3262 else if (operand->default_reloc == BFD_RELOC_V850_16_PCREL) 3263 { 3264 fixups[i].exp.X_add_number += 2; 3265 address += 2; 3266 } 3267 3268 /* fprintf (stderr, "0x%x %d %ld\n", address, size, fixups[i].exp.X_add_number); */ 3269 fixP = fix_new_exp (frag_now, address, size, 3270 &fixups[i].exp, 3271 reloc_howto->pc_relative, 3272 reloc); 3273 3274 fixP->tc_fix_data = (void *) operand; 3275 3276 switch (reloc) 3277 { 3278 case BFD_RELOC_LO16: 3279 case BFD_RELOC_V850_LO16_S1: 3280 case BFD_RELOC_V850_LO16_SPLIT_OFFSET: 3281 case BFD_RELOC_HI16: 3282 case BFD_RELOC_HI16_S: 3283 fixP->fx_no_overflow = 1; 3284 break; 3285 default: 3286 break; 3287 } 3288 } 3289 else 3290 { 3291 gas_assert (f != NULL); 3292 fix_new_exp (frag_now, 3293 f - frag_now->fr_literal, 4, 3294 & fixups[i].exp, 3295 (operand->flags & V850_PCREL) != 0, 3296 fixups[i].opindex + BFD_RELOC_UNUSED); 3297 } 3298 } 3299 3300 input_line_pointer = saved_input_line_pointer; 3301 } 3302 3303 /* If while processing a fixup, a reloc really needs to be created 3304 then it is done here. */ 3305 3306 arelent * 3307 tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp) 3308 { 3309 arelent *reloc; 3310 3311 reloc = notes_alloc (sizeof (arelent)); 3312 reloc->sym_ptr_ptr = notes_alloc (sizeof (asymbol *)); 3313 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 3314 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 3315 3316 if ( fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY 3317 || fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT 3318 || fixp->fx_r_type == BFD_RELOC_V850_LONGCALL 3319 || fixp->fx_r_type == BFD_RELOC_V850_LONGJUMP 3320 || fixp->fx_r_type == BFD_RELOC_V850_ALIGN) 3321 reloc->addend = fixp->fx_offset; 3322 else 3323 { 3324 #if 0 3325 if (fixp->fx_r_type == BFD_RELOC_32 3326 && fixp->fx_pcrel) 3327 fixp->fx_r_type = BFD_RELOC_32_PCREL; 3328 #endif 3329 3330 reloc->addend = fixp->fx_addnumber; 3331 } 3332 3333 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); 3334 3335 if (reloc->howto == NULL) 3336 { 3337 as_bad_where (fixp->fx_file, fixp->fx_line, 3338 /* xgettext:c-format */ 3339 _("reloc %d not supported by object file format"), 3340 (int) fixp->fx_r_type); 3341 return NULL; 3342 } 3343 3344 return reloc; 3345 } 3346 3347 void 3348 v850_handle_align (fragS * frag) 3349 { 3350 if (v850_relax 3351 && frag->fr_type == rs_align 3352 && frag->fr_address + frag->fr_fix > 0 3353 && frag->fr_offset > 1 3354 && now_seg != bss_section 3355 && now_seg != v850_seg_table[SBSS_SECTION].s 3356 && now_seg != v850_seg_table[TBSS_SECTION].s 3357 && now_seg != v850_seg_table[ZBSS_SECTION].s) 3358 fix_new (frag, frag->fr_fix, 2, & abs_symbol, frag->fr_offset, 0, 3359 BFD_RELOC_V850_ALIGN); 3360 } 3361 3362 /* Return current size of variable part of frag. */ 3363 3364 int 3365 md_estimate_size_before_relax (fragS *fragp, asection *seg ATTRIBUTE_UNUSED) 3366 { 3367 if (fragp->fr_subtype >= sizeof (md_relax_table) / sizeof (md_relax_table[0])) 3368 abort (); 3369 3370 return md_relax_table[fragp->fr_subtype].rlx_length; 3371 } 3372 3373 long 3374 v850_pcrel_from_section (fixS *fixp, segT section) 3375 { 3376 /* If the symbol is undefined, or in a section other than our own, 3377 or it is weak (in which case it may well be in another section, 3378 then let the linker figure it out. */ 3379 if (fixp->fx_addsy != NULL 3380 && (! S_IS_DEFINED (fixp->fx_addsy) 3381 || S_IS_WEAK (fixp->fx_addsy) 3382 || (S_GET_SEGMENT (fixp->fx_addsy) != section))) 3383 return 0; 3384 3385 return fixp->fx_frag->fr_address + fixp->fx_where; 3386 } 3387 3388 void 3389 md_apply_fix (fixS *fixP, valueT *valueP, segT seg ATTRIBUTE_UNUSED) 3390 { 3391 valueT value = * valueP; 3392 char *where; 3393 3394 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 3395 || fixP->fx_r_type == BFD_RELOC_V850_LONGCALL 3396 || fixP->fx_r_type == BFD_RELOC_V850_LONGJUMP 3397 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 3398 { 3399 fixP->fx_done = 0; 3400 return; 3401 } 3402 3403 if (fixP->fx_addsy == NULL) 3404 fixP->fx_addnumber = value, 3405 fixP->fx_done = 1; 3406 3407 else if (fixP->fx_pcrel) 3408 fixP->fx_addnumber = fixP->fx_offset; 3409 3410 else 3411 { 3412 value = fixP->fx_offset; 3413 if (fixP->fx_subsy != NULL) 3414 { 3415 if (S_GET_SEGMENT (fixP->fx_subsy) == absolute_section) 3416 value -= S_GET_VALUE (fixP->fx_subsy); 3417 else 3418 /* We don't actually support subtracting a symbol. */ 3419 as_bad_subtract (fixP); 3420 } 3421 fixP->fx_addnumber = value; 3422 } 3423 3424 if (fixP->fx_r_type >= BFD_RELOC_UNUSED) 3425 { 3426 int opindex; 3427 const struct v850_operand *operand; 3428 unsigned long insn; 3429 const char *errmsg = NULL; 3430 3431 opindex = fixP->fx_r_type - BFD_RELOC_UNUSED; 3432 operand = &v850_operands[opindex]; 3433 3434 /* Fetch the instruction, insert the fully resolved operand 3435 value, and stuff the instruction back again. 3436 3437 Note the instruction has been stored in little endian 3438 format! */ 3439 where = fixP->fx_frag->fr_literal + fixP->fx_where; 3440 3441 if (fixP->fx_size > 2) 3442 insn = bfd_getl32 (where); 3443 else 3444 insn = bfd_getl16 (where); 3445 3446 /* When inserting loop offsets a backwards displacement 3447 is encoded as a positive value. */ 3448 if (operand->flags & V850_INVERSE_PCREL) 3449 value = - value; 3450 3451 insn = v850_insert_operand (insn, operand, (offsetT) value, 3452 &errmsg); 3453 if (errmsg) 3454 as_warn_where (fixP->fx_file, fixP->fx_line, "%s", errmsg); 3455 3456 if (fixP->fx_size > 2) 3457 bfd_putl32 (insn, where); 3458 else 3459 bfd_putl16 (insn, where); 3460 3461 if (fixP->fx_done) 3462 /* Nothing else to do here. */ 3463 return; 3464 3465 /* Determine a BFD reloc value based on the operand information. 3466 We are only prepared to turn a few of the operands into relocs. */ 3467 3468 if (operand->default_reloc == BFD_RELOC_NONE) 3469 { 3470 as_bad_where (fixP->fx_file, fixP->fx_line, 3471 _("unresolved expression that must be resolved")); 3472 fixP->fx_done = 1; 3473 return; 3474 } 3475 3476 { 3477 fixP->fx_r_type = operand->default_reloc; 3478 if (operand->default_reloc == BFD_RELOC_V850_16_PCREL) 3479 { 3480 fixP->fx_where += 2; 3481 fixP->fx_size = 2; 3482 fixP->fx_addnumber += 2; 3483 } 3484 } 3485 } 3486 else if (fixP->fx_done) 3487 { 3488 /* We still have to insert the value into memory! */ 3489 where = fixP->fx_frag->fr_literal + fixP->fx_where; 3490 3491 if (fixP->tc_fix_data != NULL 3492 && ((struct v850_operand *) fixP->tc_fix_data)->insert != NULL) 3493 { 3494 const char * message = NULL; 3495 struct v850_operand * operand = fixP->tc_fix_data; 3496 unsigned long insn; 3497 3498 /* The variable "where" currently points at the exact point inside 3499 the insn where we need to insert the value. But we need to 3500 extract the entire insn so we probably need to move "where" 3501 back a few bytes. */ 3502 3503 if (fixP->fx_size == 2) 3504 where -= 2; 3505 else if (fixP->fx_size == 1) 3506 where -= 3; 3507 3508 insn = bfd_getl32 (where); 3509 3510 /* Use the operand's insertion procedure, if present, in order to 3511 make sure that the value is correctly stored in the insn. */ 3512 insn = operand->insert (insn, (offsetT) value, & message); 3513 /* Ignore message even if it is set. */ 3514 3515 bfd_putl32 (insn, where); 3516 } 3517 else 3518 { 3519 switch (fixP->fx_r_type) 3520 { 3521 case BFD_RELOC_V850_32_ABS: 3522 case BFD_RELOC_V850_32_PCREL: 3523 bfd_putl32 (value & 0xfffffffe, where); 3524 break; 3525 3526 case BFD_RELOC_32: 3527 bfd_putl32 (value, where); 3528 break; 3529 3530 case BFD_RELOC_V850_23: 3531 bfd_putl32 (((value & 0x7f) << 4) | ((value & 0x7fff80) << (16-7)) 3532 | (bfd_getl32 (where) & ~((0x7f << 4) | (0xffff << 16))), 3533 where); 3534 break; 3535 3536 case BFD_RELOC_16: 3537 case BFD_RELOC_HI16: 3538 case BFD_RELOC_HI16_S: 3539 case BFD_RELOC_LO16: 3540 case BFD_RELOC_V850_ZDA_16_16_OFFSET: 3541 case BFD_RELOC_V850_SDA_16_16_OFFSET: 3542 case BFD_RELOC_V850_TDA_16_16_OFFSET: 3543 case BFD_RELOC_V850_CALLT_16_16_OFFSET: 3544 bfd_putl16 (value & 0xffff, where); 3545 break; 3546 3547 case BFD_RELOC_8: 3548 *where = value & 0xff; 3549 break; 3550 3551 case BFD_RELOC_V850_9_PCREL: 3552 bfd_putl16 (((value & 0x1f0) << 7) | ((value & 0x0e) << 3) 3553 | (bfd_getl16 (where) & ~((0x1f0 << 7) | (0x0e << 3))), where); 3554 break; 3555 3556 case BFD_RELOC_V850_17_PCREL: 3557 bfd_putl32 (((value & 0x10000) >> (16 - 4)) | ((value & 0xfffe) << 16) 3558 | (bfd_getl32 (where) & ~((0x10000 >> (16 - 4)) | (0xfffe << 16))), where); 3559 break; 3560 3561 case BFD_RELOC_V850_16_PCREL: 3562 bfd_putl16 ((-value & 0xfffe) | (bfd_getl16 (where + 2) & 0x0001), 3563 where + 2); 3564 break; 3565 3566 case BFD_RELOC_V850_22_PCREL: 3567 bfd_putl32 (((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16) 3568 | (bfd_getl32 (where) & ~((0xfffe << 16) | (0x3f0000 >> 16))), where); 3569 break; 3570 3571 case BFD_RELOC_V850_16_S1: 3572 case BFD_RELOC_V850_LO16_S1: 3573 case BFD_RELOC_V850_ZDA_15_16_OFFSET: 3574 case BFD_RELOC_V850_SDA_15_16_OFFSET: 3575 bfd_putl16 (value & 0xfffe, where); 3576 break; 3577 3578 case BFD_RELOC_V850_16_SPLIT_OFFSET: 3579 case BFD_RELOC_V850_LO16_SPLIT_OFFSET: 3580 case BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET: 3581 case BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET: 3582 bfd_putl32 (((value << 16) & 0xfffe0000) 3583 | ((value << 5) & 0x20) 3584 | (bfd_getl32 (where) & ~0xfffe0020), where); 3585 break; 3586 3587 case BFD_RELOC_V850_TDA_6_8_OFFSET: 3588 *where = (*where & ~0x7e) | ((value >> 1) & 0x7e); 3589 break; 3590 3591 case BFD_RELOC_V850_TDA_7_8_OFFSET: 3592 *where = (*where & ~0x7f) | ((value >> 1) & 0x7f); 3593 break; 3594 3595 case BFD_RELOC_V850_TDA_7_7_OFFSET: 3596 *where = (*where & ~0x7f) | (value & 0x7f); 3597 break; 3598 3599 case BFD_RELOC_V850_TDA_4_5_OFFSET: 3600 *where = (*where & ~0xf) | ((value >> 1) & 0xf); 3601 break; 3602 3603 case BFD_RELOC_V850_TDA_4_4_OFFSET: 3604 *where = (*where & ~0xf) | (value & 0xf); 3605 break; 3606 3607 case BFD_RELOC_V850_CALLT_6_7_OFFSET: 3608 *where = (*where & ~0x3f) | (value & 0x3f); 3609 break; 3610 3611 default: 3612 abort (); 3613 } 3614 } 3615 } 3616 } 3617 3618 /* Parse a cons expression. We have to handle hi(), lo(), etc 3619 on the v850. */ 3620 3621 bfd_reloc_code_real_type 3622 parse_cons_expression_v850 (expressionS *exp) 3623 { 3624 const char *errmsg; 3625 bfd_reloc_code_real_type r; 3626 3627 /* See if there's a reloc prefix like hi() we have to handle. */ 3628 r = v850_reloc_prefix (NULL, &errmsg); 3629 3630 /* Do normal expression parsing. */ 3631 expression (exp); 3632 return r; 3633 } 3634 3635 /* Create a fixup for a cons expression. If parse_cons_expression_v850 3636 found a reloc prefix, then we use that reloc, else we choose an 3637 appropriate one based on the size of the expression. */ 3638 3639 void 3640 cons_fix_new_v850 (fragS *frag, 3641 int where, 3642 int size, 3643 expressionS *exp, 3644 bfd_reloc_code_real_type r) 3645 { 3646 if (r == BFD_RELOC_NONE) 3647 { 3648 if (size == 4) 3649 r = BFD_RELOC_32; 3650 if (size == 2) 3651 r = BFD_RELOC_16; 3652 if (size == 1) 3653 r = BFD_RELOC_8; 3654 } 3655 3656 if (exp != NULL) 3657 fix_new_exp (frag, where, size, exp, 0, r); 3658 else 3659 fix_new (frag, where, size, NULL, 0, 0, r); 3660 } 3661 3662 bool 3663 v850_fix_adjustable (fixS *fixP) 3664 { 3665 if (fixP->fx_addsy == NULL) 3666 return 1; 3667 3668 /* Don't adjust function names. */ 3669 if (S_IS_FUNCTION (fixP->fx_addsy)) 3670 return 0; 3671 3672 /* We need the symbol name for the VTABLE entries. */ 3673 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 3674 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 3675 return 0; 3676 3677 return 1; 3678 } 3679 3680 int 3681 v850_force_relocation (struct fix *fixP) 3682 { 3683 if (fixP->fx_r_type == BFD_RELOC_V850_LONGCALL 3684 || fixP->fx_r_type == BFD_RELOC_V850_LONGJUMP) 3685 return 1; 3686 3687 if (v850_relax 3688 && (fixP->fx_pcrel 3689 || fixP->fx_r_type == BFD_RELOC_V850_ALIGN 3690 || fixP->fx_r_type == BFD_RELOC_V850_9_PCREL 3691 || fixP->fx_r_type == BFD_RELOC_V850_16_PCREL 3692 || fixP->fx_r_type == BFD_RELOC_V850_17_PCREL 3693 || fixP->fx_r_type == BFD_RELOC_V850_22_PCREL 3694 || fixP->fx_r_type == BFD_RELOC_V850_32_PCREL 3695 || fixP->fx_r_type >= BFD_RELOC_UNUSED)) 3696 return 1; 3697 3698 return generic_force_reloc (fixP); 3699 } 3700 3701 /* Create a v850 note section. */ 3702 void 3703 v850_md_finish (void) 3704 { 3705 segT note_sec; 3706 segT orig_seg = now_seg; 3707 subsegT orig_subseg = now_subseg; 3708 enum v850_notes id; 3709 3710 note_sec = subseg_new (V850_NOTE_SECNAME, 0); 3711 bfd_set_section_flags (note_sec, SEC_HAS_CONTENTS | SEC_READONLY | SEC_MERGE); 3712 bfd_set_section_alignment (note_sec, 2); 3713 3714 /* Provide default values for all of the notes. */ 3715 for (id = V850_NOTE_ALIGNMENT; id <= NUM_V850_NOTES; id++) 3716 { 3717 int val = 0; 3718 char * p; 3719 3720 /* Follow the standard note section layout: 3721 First write the length of the name string. */ 3722 p = frag_more (4); 3723 md_number_to_chars (p, 4, 4); 3724 3725 /* Next comes the length of the "descriptor", i.e., the actual data. */ 3726 p = frag_more (4); 3727 md_number_to_chars (p, 4, 4); 3728 3729 /* Write the note type. */ 3730 p = frag_more (4); 3731 md_number_to_chars (p, id, 4); 3732 3733 /* Write the name field. */ 3734 p = frag_more (4); 3735 memcpy (p, V850_NOTE_NAME, 4); 3736 3737 /* Finally, write the descriptor. */ 3738 p = frag_more (4); 3739 switch (id) 3740 { 3741 case V850_NOTE_ALIGNMENT: 3742 val = v850_data_8 ? EF_RH850_DATA_ALIGN8 : EF_RH850_DATA_ALIGN4; 3743 break; 3744 3745 case V850_NOTE_DATA_SIZE: 3746 /* GCC does not currently support an option 3747 for 32-bit doubles with the V850 backend. */ 3748 val = EF_RH850_DOUBLE64; 3749 break; 3750 3751 case V850_NOTE_FPU_INFO: 3752 if (! soft_float) 3753 switch (machine) 3754 { 3755 case bfd_mach_v850e3v5: val = EF_RH850_FPU30; break; 3756 case bfd_mach_v850e2v3: val = EF_RH850_FPU20; break; 3757 default: break; 3758 } 3759 break; 3760 3761 default: 3762 break; 3763 } 3764 md_number_to_chars (p, val, 4); 3765 } 3766 3767 /* Paranoia - we probably do not need this. */ 3768 subseg_set (orig_seg, orig_subseg); 3769 } 3770
Indexes created Thu May 14 00:25:00 UTC 2026