aarch64.h revision 1.1.1.1.4.2
1 /* AArch64 assembler/disassembler support. 2 3 Copyright 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc. 4 Contributed by ARM Ltd. 5 6 This file is part of GNU Binutils. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the license, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; see the file COPYING3. If not, 20 see <http://www.gnu.org/licenses/>. */ 21 22 #ifndef OPCODE_AARCH64_H 23 #define OPCODE_AARCH64_H 24 25 #include "bfd.h" 26 #include "bfd_stdint.h" 27 #include <assert.h> 28 #include <stdlib.h> 29 30 /* The offset for pc-relative addressing is currently defined to be 0. */ 31 #define AARCH64_PCREL_OFFSET 0 32 33 typedef uint32_t aarch64_insn; 34 35 /* The following bitmasks control CPU features. */ 36 #define AARCH64_FEATURE_V8 0x00000001 /* All processors. */ 37 #define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */ 38 #define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */ 39 #define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */ 40 41 /* Architectures are the sum of the base and extensions. */ 42 #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ 43 AARCH64_FEATURE_FP \ 44 | AARCH64_FEATURE_SIMD) 45 #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) 46 #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */ 47 48 /* CPU-specific features */ 49 typedef unsigned long aarch64_feature_set; 50 51 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \ 52 (((CPU) & (FEAT)) != 0) 53 54 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \ 55 do { \ 56 (TARG) = (F1) | (F2); \ 57 } while (0) 58 59 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \ 60 do { \ 61 (TARG) = (F1) &~ (F2); \ 62 } while (0) 63 64 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc)) 65 66 #define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT) \ 67 (((OPC) & (FEAT)) != 0) 68 69 enum aarch64_operand_class 70 { 71 AARCH64_OPND_CLASS_NIL, 72 AARCH64_OPND_CLASS_INT_REG, 73 AARCH64_OPND_CLASS_MODIFIED_REG, 74 AARCH64_OPND_CLASS_FP_REG, 75 AARCH64_OPND_CLASS_SIMD_REG, 76 AARCH64_OPND_CLASS_SIMD_ELEMENT, 77 AARCH64_OPND_CLASS_SISD_REG, 78 AARCH64_OPND_CLASS_SIMD_REGLIST, 79 AARCH64_OPND_CLASS_CP_REG, 80 AARCH64_OPND_CLASS_ADDRESS, 81 AARCH64_OPND_CLASS_IMMEDIATE, 82 AARCH64_OPND_CLASS_SYSTEM, 83 }; 84 85 /* Operand code that helps both parsing and coding. 86 Keep AARCH64_OPERANDS synced. */ 87 88 enum aarch64_opnd 89 { 90 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/ 91 92 AARCH64_OPND_Rd, /* Integer register as destination. */ 93 AARCH64_OPND_Rn, /* Integer register as source. */ 94 AARCH64_OPND_Rm, /* Integer register as source. */ 95 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */ 96 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */ 97 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */ 98 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */ 99 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */ 100 101 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */ 102 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */ 103 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */ 104 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */ 105 106 AARCH64_OPND_Fd, /* Floating-point Fd. */ 107 AARCH64_OPND_Fn, /* Floating-point Fn. */ 108 AARCH64_OPND_Fm, /* Floating-point Fm. */ 109 AARCH64_OPND_Fa, /* Floating-point Fa. */ 110 AARCH64_OPND_Ft, /* Floating-point Ft. */ 111 AARCH64_OPND_Ft2, /* Floating-point Ft2. */ 112 113 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */ 114 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */ 115 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */ 116 117 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */ 118 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */ 119 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */ 120 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */ 121 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */ 122 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */ 123 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */ 124 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */ 125 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */ 126 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */ 127 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single 128 structure to all lanes. */ 129 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */ 130 131 AARCH64_OPND_Cn, /* Co-processor register in CRn field. */ 132 AARCH64_OPND_Cm, /* Co-processor register in CRm field. */ 133 134 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */ 135 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */ 136 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */ 137 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */ 138 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */ 139 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */ 140 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction 141 (no encoding). */ 142 AARCH64_OPND_IMM0, /* Immediate for #0. */ 143 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */ 144 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */ 145 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */ 146 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */ 147 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */ 148 AARCH64_OPND_IMM, /* Immediate. */ 149 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */ 150 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */ 151 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */ 152 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */ 153 AARCH64_OPND_BIT_NUM, /* Immediate. */ 154 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */ 155 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */ 156 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for 157 each condition flag. */ 158 159 AARCH64_OPND_LIMM, /* Logical Immediate. */ 160 AARCH64_OPND_AIMM, /* Arithmetic immediate. */ 161 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */ 162 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */ 163 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */ 164 165 AARCH64_OPND_COND, /* Standard condition as the last operand. */ 166 167 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */ 168 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */ 169 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */ 170 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */ 171 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */ 172 173 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */ 174 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */ 175 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */ 176 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */ 177 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is 178 negative or unaligned and there is 179 no writeback allowed. This operand code 180 is only used to support the programmer- 181 friendly feature of using LDR/STR as the 182 the mnemonic name for LDUR/STUR instructions 183 wherever there is no ambiguity. */ 184 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */ 185 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */ 186 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */ 187 188 AARCH64_OPND_SYSREG, /* System register operand. */ 189 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */ 190 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */ 191 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */ 192 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */ 193 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */ 194 AARCH64_OPND_BARRIER, /* Barrier operand. */ 195 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */ 196 AARCH64_OPND_PRFOP, /* Prefetch operation. */ 197 }; 198 199 /* Qualifier constrains an operand. It either specifies a variant of an 200 operand type or limits values available to an operand type. 201 202 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */ 203 204 enum aarch64_opnd_qualifier 205 { 206 /* Indicating no further qualification on an operand. */ 207 AARCH64_OPND_QLF_NIL, 208 209 /* Qualifying an operand which is a general purpose (integer) register; 210 indicating the operand data size or a specific register. */ 211 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */ 212 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */ 213 AARCH64_OPND_QLF_WSP, /* WSP. */ 214 AARCH64_OPND_QLF_SP, /* SP. */ 215 216 /* Qualifying an operand which is a floating-point register, a SIMD 217 vector element or a SIMD vector element list; indicating operand data 218 size or the size of each SIMD vector element in the case of a SIMD 219 vector element list. 220 These qualifiers are also used to qualify an address operand to 221 indicate the size of data element a load/store instruction is 222 accessing. 223 They are also used for the immediate shift operand in e.g. SSHR. Such 224 a use is only for the ease of operand encoding/decoding and qualifier 225 sequence matching; such a use should not be applied widely; use the value 226 constraint qualifiers for immediate operands wherever possible. */ 227 AARCH64_OPND_QLF_S_B, 228 AARCH64_OPND_QLF_S_H, 229 AARCH64_OPND_QLF_S_S, 230 AARCH64_OPND_QLF_S_D, 231 AARCH64_OPND_QLF_S_Q, 232 233 /* Qualifying an operand which is a SIMD vector register or a SIMD vector 234 register list; indicating register shape. 235 They are also used for the immediate shift operand in e.g. SSHR. Such 236 a use is only for the ease of operand encoding/decoding and qualifier 237 sequence matching; such a use should not be applied widely; use the value 238 constraint qualifiers for immediate operands wherever possible. */ 239 AARCH64_OPND_QLF_V_8B, 240 AARCH64_OPND_QLF_V_16B, 241 AARCH64_OPND_QLF_V_4H, 242 AARCH64_OPND_QLF_V_8H, 243 AARCH64_OPND_QLF_V_2S, 244 AARCH64_OPND_QLF_V_4S, 245 AARCH64_OPND_QLF_V_1D, 246 AARCH64_OPND_QLF_V_2D, 247 AARCH64_OPND_QLF_V_1Q, 248 249 /* Constraint on value. */ 250 AARCH64_OPND_QLF_imm_0_7, 251 AARCH64_OPND_QLF_imm_0_15, 252 AARCH64_OPND_QLF_imm_0_31, 253 AARCH64_OPND_QLF_imm_0_63, 254 AARCH64_OPND_QLF_imm_1_32, 255 AARCH64_OPND_QLF_imm_1_64, 256 257 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros 258 or shift-ones. */ 259 AARCH64_OPND_QLF_LSL, 260 AARCH64_OPND_QLF_MSL, 261 262 /* Special qualifier helping retrieve qualifier information during the 263 decoding time (currently not in use). */ 264 AARCH64_OPND_QLF_RETRIEVE, 265 }; 266 267 /* Instruction class. */ 269 270 enum aarch64_insn_class 271 { 272 addsub_carry, 273 addsub_ext, 274 addsub_imm, 275 addsub_shift, 276 asimdall, 277 asimddiff, 278 asimdelem, 279 asimdext, 280 asimdimm, 281 asimdins, 282 asimdmisc, 283 asimdperm, 284 asimdsame, 285 asimdshf, 286 asimdtbl, 287 asisddiff, 288 asisdelem, 289 asisdlse, 290 asisdlsep, 291 asisdlso, 292 asisdlsop, 293 asisdmisc, 294 asisdone, 295 asisdpair, 296 asisdsame, 297 asisdshf, 298 bitfield, 299 branch_imm, 300 branch_reg, 301 compbranch, 302 condbranch, 303 condcmp_imm, 304 condcmp_reg, 305 condsel, 306 cryptoaes, 307 cryptosha2, 308 cryptosha3, 309 dp_1src, 310 dp_2src, 311 dp_3src, 312 exception, 313 extract, 314 float2fix, 315 float2int, 316 floatccmp, 317 floatcmp, 318 floatdp1, 319 floatdp2, 320 floatdp3, 321 floatimm, 322 floatsel, 323 ldst_immpost, 324 ldst_immpre, 325 ldst_imm9, /* immpost or immpre */ 326 ldst_pos, 327 ldst_regoff, 328 ldst_unpriv, 329 ldst_unscaled, 330 ldstexcl, 331 ldstnapair_offs, 332 ldstpair_off, 333 ldstpair_indexed, 334 loadlit, 335 log_imm, 336 log_shift, 337 movewide, 338 pcreladdr, 339 ic_system, 340 testbranch, 341 }; 342 343 /* Opcode enumerators. */ 344 345 enum aarch64_op 346 { 347 OP_NIL, 348 OP_STRB_POS, 349 OP_LDRB_POS, 350 OP_LDRSB_POS, 351 OP_STRH_POS, 352 OP_LDRH_POS, 353 OP_LDRSH_POS, 354 OP_STR_POS, 355 OP_LDR_POS, 356 OP_STRF_POS, 357 OP_LDRF_POS, 358 OP_LDRSW_POS, 359 OP_PRFM_POS, 360 361 OP_STURB, 362 OP_LDURB, 363 OP_LDURSB, 364 OP_STURH, 365 OP_LDURH, 366 OP_LDURSH, 367 OP_STUR, 368 OP_LDUR, 369 OP_STURV, 370 OP_LDURV, 371 OP_LDURSW, 372 OP_PRFUM, 373 374 OP_LDR_LIT, 375 OP_LDRV_LIT, 376 OP_LDRSW_LIT, 377 OP_PRFM_LIT, 378 379 OP_ADD, 380 OP_B, 381 OP_BL, 382 383 OP_MOVN, 384 OP_MOVZ, 385 OP_MOVK, 386 387 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */ 388 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */ 389 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */ 390 391 OP_MOV_V, /* MOV alias for moving vector register. */ 392 393 OP_ASR_IMM, 394 OP_LSR_IMM, 395 OP_LSL_IMM, 396 397 OP_BIC, 398 399 OP_UBFX, 400 OP_BFXIL, 401 OP_SBFX, 402 OP_SBFIZ, 403 OP_BFI, 404 OP_UBFIZ, 405 OP_UXTB, 406 OP_UXTH, 407 OP_UXTW, 408 409 OP_V_MOVI_B, 410 411 OP_CINC, 412 OP_CINV, 413 OP_CNEG, 414 OP_CSET, 415 OP_CSETM, 416 417 OP_FCVT, 418 OP_FCVTN, 419 OP_FCVTN2, 420 OP_FCVTL, 421 OP_FCVTL2, 422 OP_FCVTXN_S, /* Scalar version. */ 423 424 OP_ROR_IMM, 425 426 OP_SXTL, 427 OP_SXTL2, 428 OP_UXTL, 429 OP_UXTL2, 430 431 OP_TOTAL_NUM, /* Pseudo. */ 432 }; 433 434 /* Maximum number of operands an instruction can have. */ 435 #define AARCH64_MAX_OPND_NUM 6 436 /* Maximum number of qualifier sequences an instruction can have. */ 437 #define AARCH64_MAX_QLF_SEQ_NUM 10 438 /* Operand qualifier typedef; optimized for the size. */ 439 typedef unsigned char aarch64_opnd_qualifier_t; 440 /* Operand qualifier sequence typedef. */ 441 typedef aarch64_opnd_qualifier_t \ 442 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM]; 443 444 /* FIXME: improve the efficiency. */ 445 static inline bfd_boolean 446 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers) 447 { 448 int i; 449 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) 450 if (qualifiers[i] != AARCH64_OPND_QLF_NIL) 451 return FALSE; 452 return TRUE; 453 } 454 455 /* This structure holds information for a particular opcode. */ 456 457 struct aarch64_opcode 458 { 459 /* The name of the mnemonic. */ 460 const char *name; 461 462 /* The opcode itself. Those bits which will be filled in with 463 operands are zeroes. */ 464 aarch64_insn opcode; 465 466 /* The opcode mask. This is used by the disassembler. This is a 467 mask containing ones indicating those bits which must match the 468 opcode field, and zeroes indicating those bits which need not 469 match (and are presumably filled in by operands). */ 470 aarch64_insn mask; 471 472 /* Instruction class. */ 473 enum aarch64_insn_class iclass; 474 475 /* Enumerator identifier. */ 476 enum aarch64_op op; 477 478 /* Which architecture variant provides this instruction. */ 479 const aarch64_feature_set *avariant; 480 481 /* An array of operand codes. Each code is an index into the 482 operand table. They appear in the order which the operands must 483 appear in assembly code, and are terminated by a zero. */ 484 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM]; 485 486 /* A list of operand qualifier code sequence. Each operand qualifier 487 code qualifies the corresponding operand code. Each operand 488 qualifier sequence specifies a valid opcode variant and related 489 constraint on operands. */ 490 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM]; 491 492 /* Flags providing information about this instruction */ 493 uint32_t flags; 494 }; 495 496 typedef struct aarch64_opcode aarch64_opcode; 497 498 /* Table describing all the AArch64 opcodes. */ 499 extern aarch64_opcode aarch64_opcode_table[]; 500 501 /* Opcode flags. */ 502 #define F_ALIAS (1 << 0) 503 #define F_HAS_ALIAS (1 << 1) 504 /* Disassembly preference priority 1-3 (the larger the higher). If nothing 505 is specified, it is the priority 0 by default, i.e. the lowest priority. */ 506 #define F_P1 (1 << 2) 507 #define F_P2 (2 << 2) 508 #define F_P3 (3 << 2) 509 /* Flag an instruction that is truly conditional executed, e.g. b.cond. */ 510 #define F_COND (1 << 4) 511 /* Instruction has the field of 'sf'. */ 512 #define F_SF (1 << 5) 513 /* Instruction has the field of 'size:Q'. */ 514 #define F_SIZEQ (1 << 6) 515 /* Floating-point instruction has the field of 'type'. */ 516 #define F_FPTYPE (1 << 7) 517 /* AdvSIMD scalar instruction has the field of 'size'. */ 518 #define F_SSIZE (1 << 8) 519 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */ 520 #define F_T (1 << 9) 521 /* Size of GPR operand in AdvSIMD instructions encoded in Q. */ 522 #define F_GPRSIZE_IN_Q (1 << 10) 523 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */ 524 #define F_LDS_SIZE (1 << 11) 525 /* Optional operand; assume maximum of 1 operand can be optional. */ 526 #define F_OPD0_OPT (1 << 12) 527 #define F_OPD1_OPT (2 << 12) 528 #define F_OPD2_OPT (3 << 12) 529 #define F_OPD3_OPT (4 << 12) 530 #define F_OPD4_OPT (5 << 12) 531 /* Default value for the optional operand when omitted from the assembly. */ 532 #define F_DEFAULT(X) (((X) & 0x1f) << 15) 533 /* Instruction that is an alias of another instruction needs to be 534 encoded/decoded by converting it to/from the real form, followed by 535 the encoding/decoding according to the rules of the real opcode. 536 This compares to the direct coding using the alias's information. 537 N.B. this flag requires F_ALIAS to be used together. */ 538 #define F_CONV (1 << 20) 539 /* Use together with F_ALIAS to indicate an alias opcode is a programmer 540 friendly pseudo instruction available only in the assembly code (thus will 541 not show up in the disassembly). */ 542 #define F_PSEUDO (1 << 21) 543 /* Instruction has miscellaneous encoding/decoding rules. */ 544 #define F_MISC (1 << 22) 545 /* Instruction has the field of 'N'; used in conjunction with F_SF. */ 546 #define F_N (1 << 23) 547 /* Opcode dependent field. */ 548 #define F_OD(X) (((X) & 0x7) << 24) 549 /* Next bit is 27. */ 550 551 static inline bfd_boolean 552 alias_opcode_p (const aarch64_opcode *opcode) 553 { 554 return (opcode->flags & F_ALIAS) ? TRUE : FALSE; 555 } 556 557 static inline bfd_boolean 558 opcode_has_alias (const aarch64_opcode *opcode) 559 { 560 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE; 561 } 562 563 /* Priority for disassembling preference. */ 564 static inline int 565 opcode_priority (const aarch64_opcode *opcode) 566 { 567 return (opcode->flags >> 2) & 0x3; 568 } 569 570 static inline bfd_boolean 571 pseudo_opcode_p (const aarch64_opcode *opcode) 572 { 573 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE; 574 } 575 576 static inline bfd_boolean 577 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx) 578 { 579 return (((opcode->flags >> 12) & 0x7) == idx + 1) 580 ? TRUE : FALSE; 581 } 582 583 static inline aarch64_insn 584 get_optional_operand_default_value (const aarch64_opcode *opcode) 585 { 586 return (opcode->flags >> 15) & 0x1f; 587 } 588 589 static inline unsigned int 590 get_opcode_dependent_value (const aarch64_opcode *opcode) 591 { 592 return (opcode->flags >> 24) & 0x7; 593 } 594 595 static inline bfd_boolean 596 opcode_has_special_coder (const aarch64_opcode *opcode) 597 { 598 return (opcode->flags & (F_SF | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T 599 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE 600 : FALSE; 601 } 602 603 struct aarch64_name_value_pair 605 { 606 const char *name; 607 aarch64_insn value; 608 }; 609 610 extern const struct aarch64_name_value_pair aarch64_operand_modifiers []; 611 extern const struct aarch64_name_value_pair aarch64_sys_regs []; 612 extern const struct aarch64_name_value_pair aarch64_pstatefields []; 613 extern const struct aarch64_name_value_pair aarch64_barrier_options [16]; 614 extern const struct aarch64_name_value_pair aarch64_prfops [32]; 615 616 typedef struct 617 { 618 const char *template; 619 uint32_t value; 620 int has_xt; 621 } aarch64_sys_ins_reg; 622 623 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic []; 624 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc []; 625 extern const aarch64_sys_ins_reg aarch64_sys_regs_at []; 626 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi []; 627 628 /* Shift/extending operator kinds. 629 N.B. order is important; keep aarch64_operand_modifiers synced. */ 630 enum aarch64_modifier_kind 631 { 632 AARCH64_MOD_NONE, 633 AARCH64_MOD_MSL, 634 AARCH64_MOD_ROR, 635 AARCH64_MOD_ASR, 636 AARCH64_MOD_LSR, 637 AARCH64_MOD_LSL, 638 AARCH64_MOD_UXTB, 639 AARCH64_MOD_UXTH, 640 AARCH64_MOD_UXTW, 641 AARCH64_MOD_UXTX, 642 AARCH64_MOD_SXTB, 643 AARCH64_MOD_SXTH, 644 AARCH64_MOD_SXTW, 645 AARCH64_MOD_SXTX, 646 }; 647 648 bfd_boolean 649 aarch64_extend_operator_p (enum aarch64_modifier_kind); 650 651 enum aarch64_modifier_kind 652 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *); 653 /* Condition. */ 654 655 typedef struct 656 { 657 /* A list of names with the first one as the disassembly preference; 658 terminated by NULL if fewer than 3. */ 659 const char *names[3]; 660 aarch64_insn value; 661 } aarch64_cond; 662 663 extern const aarch64_cond aarch64_conds[16]; 664 665 const aarch64_cond* get_cond_from_value (aarch64_insn value); 666 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond); 667 668 /* Structure representing an operand. */ 670 671 struct aarch64_opnd_info 672 { 673 enum aarch64_opnd type; 674 aarch64_opnd_qualifier_t qualifier; 675 int idx; 676 677 union 678 { 679 struct 680 { 681 unsigned regno; 682 } reg; 683 struct 684 { 685 unsigned regno : 5; 686 unsigned index : 4; 687 } reglane; 688 /* e.g. LVn. */ 689 struct 690 { 691 unsigned first_regno : 5; 692 unsigned num_regs : 3; 693 /* 1 if it is a list of reg element. */ 694 unsigned has_index : 1; 695 /* Lane index; valid only when has_index is 1. */ 696 unsigned index : 4; 697 } reglist; 698 /* e.g. immediate or pc relative address offset. */ 699 struct 700 { 701 int64_t value; 702 unsigned is_fp : 1; 703 } imm; 704 /* e.g. address in STR (register offset). */ 705 struct 706 { 707 unsigned base_regno; 708 struct 709 { 710 union 711 { 712 int imm; 713 unsigned regno; 714 }; 715 unsigned is_reg; 716 } offset; 717 unsigned pcrel : 1; /* PC-relative. */ 718 unsigned writeback : 1; 719 unsigned preind : 1; /* Pre-indexed. */ 720 unsigned postind : 1; /* Post-indexed. */ 721 } addr; 722 const aarch64_cond *cond; 723 /* The encoding of the system register. */ 724 aarch64_insn sysreg; 725 /* The encoding of the PSTATE field. */ 726 aarch64_insn pstatefield; 727 const aarch64_sys_ins_reg *sysins_op; 728 const struct aarch64_name_value_pair *barrier; 729 const struct aarch64_name_value_pair *prfop; 730 }; 731 732 /* Operand shifter; in use when the operand is a register offset address, 733 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */ 734 struct 735 { 736 enum aarch64_modifier_kind kind; 737 int amount; 738 unsigned operator_present: 1; /* Only valid during encoding. */ 739 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */ 740 unsigned amount_present: 1; 741 } shifter; 742 743 unsigned skip:1; /* Operand is not completed if there is a fixup needed 744 to be done on it. In some (but not all) of these 745 cases, we need to tell libopcodes to skip the 746 constraint checking and the encoding for this 747 operand, so that the libopcodes can pick up the 748 right opcode before the operand is fixed-up. This 749 flag should only be used during the 750 assembling/encoding. */ 751 unsigned present:1; /* Whether this operand is present in the assembly 752 line; not used during the disassembly. */ 753 }; 754 755 typedef struct aarch64_opnd_info aarch64_opnd_info; 756 757 /* Structure representing an instruction. 758 759 It is used during both the assembling and disassembling. The assembler 760 fills an aarch64_inst after a successful parsing and then passes it to the 761 encoding routine to do the encoding. During the disassembling, the 762 disassembler calls the decoding routine to decode a binary instruction; on a 763 successful return, such a structure will be filled with information of the 764 instruction; then the disassembler uses the information to print out the 765 instruction. */ 766 767 struct aarch64_inst 768 { 769 /* The value of the binary instruction. */ 770 aarch64_insn value; 771 772 /* Corresponding opcode entry. */ 773 const aarch64_opcode *opcode; 774 775 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */ 776 const aarch64_cond *cond; 777 778 /* Operands information. */ 779 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM]; 780 }; 781 782 typedef struct aarch64_inst aarch64_inst; 783 784 /* Diagnosis related declaration and interface. */ 786 787 /* Operand error kind enumerators. 788 789 AARCH64_OPDE_RECOVERABLE 790 Less severe error found during the parsing, very possibly because that 791 GAS has picked up a wrong instruction template for the parsing. 792 793 AARCH64_OPDE_SYNTAX_ERROR 794 General syntax error; it can be either a user error, or simply because 795 that GAS is trying a wrong instruction template. 796 797 AARCH64_OPDE_FATAL_SYNTAX_ERROR 798 Definitely a user syntax error. 799 800 AARCH64_OPDE_INVALID_VARIANT 801 No syntax error, but the operands are not a valid combination, e.g. 802 FMOV D0,S0 803 804 AARCH64_OPDE_OUT_OF_RANGE 805 Error about some immediate value out of a valid range. 806 807 AARCH64_OPDE_UNALIGNED 808 Error about some immediate value not properly aligned (i.e. not being a 809 multiple times of a certain value). 810 811 AARCH64_OPDE_REG_LIST 812 Error about the register list operand having unexpected number of 813 registers. 814 815 AARCH64_OPDE_OTHER_ERROR 816 Error of the highest severity and used for any severe issue that does not 817 fall into any of the above categories. 818 819 The enumerators are only interesting to GAS. They are declared here (in 820 libopcodes) because that some errors are detected (and then notified to GAS) 821 by libopcodes (rather than by GAS solely). 822 823 The first three errors are only deteced by GAS while the 824 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as 825 only libopcodes has the information about the valid variants of each 826 instruction. 827 828 The enumerators have an increasing severity. This is helpful when there are 829 multiple instruction templates available for a given mnemonic name (e.g. 830 FMOV); this mechanism will help choose the most suitable template from which 831 the generated diagnostics can most closely describe the issues, if any. */ 832 833 enum aarch64_operand_error_kind 834 { 835 AARCH64_OPDE_NIL, 836 AARCH64_OPDE_RECOVERABLE, 837 AARCH64_OPDE_SYNTAX_ERROR, 838 AARCH64_OPDE_FATAL_SYNTAX_ERROR, 839 AARCH64_OPDE_INVALID_VARIANT, 840 AARCH64_OPDE_OUT_OF_RANGE, 841 AARCH64_OPDE_UNALIGNED, 842 AARCH64_OPDE_REG_LIST, 843 AARCH64_OPDE_OTHER_ERROR 844 }; 845 846 /* N.B. GAS assumes that this structure work well with shallow copy. */ 847 struct aarch64_operand_error 848 { 849 enum aarch64_operand_error_kind kind; 850 int index; 851 const char *error; 852 int data[3]; /* Some data for extra information. */ 853 }; 854 855 typedef struct aarch64_operand_error aarch64_operand_error; 856 857 /* Encoding entrypoint. */ 858 859 int aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *, 860 aarch64_insn *, aarch64_opnd_qualifier_t *, 861 aarch64_operand_error *); 862 863 const aarch64_opcode* aarch64_replace_opcode (struct aarch64_inst *, 864 const aarch64_opcode *); 865 866 /* Given the opcode enumerator OP, return the pointer to the corresponding 867 opcode entry. */ 868 869 const aarch64_opcode* aarch64_get_opcode (enum aarch64_op); 870 871 /* Generate the string representation of an operand. */ 872 void aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *, 873 const aarch64_opnd_info *, int, int *, bfd_vma *); 874 875 /* Miscellaneous interface. */ 876 877 int aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd); 878 879 aarch64_opnd_qualifier_t 880 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int, 881 const aarch64_opnd_qualifier_t, int); 882 883 int aarch64_num_of_operands (const aarch64_opcode *); 884 885 int aarch64_stack_pointer_p (const aarch64_opnd_info *); 886 int aarch64_zero_register_p (const aarch64_opnd_info *); 887 888 /* Given an operand qualifier, return the expected data element size 889 of a qualified operand. */ 890 unsigned char aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t); 891 enum aarch64_operand_class aarch64_get_operand_class (enum aarch64_opnd); 892 const char* aarch64_get_operand_name (enum aarch64_opnd); 893 const char* aarch64_get_operand_desc (enum aarch64_opnd); 894 895 #ifdef DEBUG_AARCH64 896 extern int debug_dump; 897 void aarch64_verbose (const char *str, ...) 898 __attribute__ ((format (printf, 1, 2))); 899 #define DEBUG_TRACE(M, ...) { \ 900 if (debug_dump) \ 901 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ 902 } 903 #define DEBUG_TRACE_IF(C, M, ...) { \ 904 if (debug_dump && (C)) \ 905 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ 906 } 907 #else /* !DEBUG_AARCH64 */ 908 #define DEBUG_TRACE(M, ...) ; 909 #define DEBUG_TRACE_IF(C, M, ...) ; 910 #endif /* DEBUG_AARCH64 */ 911 912 #endif /* OPCODE_AARCH64_H */ 913
Indexes created Thu Apr 02 00:23:07 UTC 2026