aarch64.h revision 1.1.1.5
1 /* AArch64 assembler/disassembler support. 2 3 Copyright (C) 2009-2018 Free Software Foundation, Inc. 4 Contributed by ARM Ltd. 5 6 This file is part of GNU Binutils. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the license, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; see the file COPYING3. If not, 20 see <http://www.gnu.org/licenses/>. */ 21 22 #ifndef OPCODE_AARCH64_H 23 #define OPCODE_AARCH64_H 24 25 #include "bfd.h" 26 #include "bfd_stdint.h" 27 #include <assert.h> 28 #include <stdlib.h> 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 /* The offset for pc-relative addressing is currently defined to be 0. */ 35 #define AARCH64_PCREL_OFFSET 0 36 37 typedef uint32_t aarch64_insn; 38 39 /* The following bitmasks control CPU features. */ 40 #define AARCH64_FEATURE_SHA2 0x200000000ULL /* SHA2 instructions. */ 41 #define AARCH64_FEATURE_AES 0x800000000ULL /* AES instructions. */ 42 #define AARCH64_FEATURE_V8_4 0x000000800ULL /* ARMv8.4 processors. */ 43 #define AARCH64_FEATURE_SM4 0x100000000ULL /* SM3 & SM4 instructions. */ 44 #define AARCH64_FEATURE_SHA3 0x400000000ULL /* SHA3 instructions. */ 45 #define AARCH64_FEATURE_V8 0x00000001 /* All processors. */ 46 #define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */ 47 #define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */ 48 #define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */ 49 #define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */ 50 #define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */ 51 #define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */ 52 #define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */ 53 #define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */ 54 #define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */ 55 #define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */ 56 #define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */ 57 #define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */ 58 #define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */ 59 #define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */ 60 #define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */ 61 #define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */ 62 #define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */ 63 #define AARCH64_FEATURE_DOTPROD 0x080000000 /* Dot Product instructions. */ 64 #define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins. */ 65 66 /* Architectures are the sum of the base and extensions. */ 67 #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ 68 AARCH64_FEATURE_FP \ 69 | AARCH64_FEATURE_SIMD) 70 #define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \ 71 AARCH64_FEATURE_CRC \ 72 | AARCH64_FEATURE_V8_1 \ 73 | AARCH64_FEATURE_LSE \ 74 | AARCH64_FEATURE_PAN \ 75 | AARCH64_FEATURE_LOR \ 76 | AARCH64_FEATURE_RDMA) 77 #define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \ 78 AARCH64_FEATURE_V8_2 \ 79 | AARCH64_FEATURE_RAS) 80 #define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \ 81 AARCH64_FEATURE_V8_3 \ 82 | AARCH64_FEATURE_RCPC \ 83 | AARCH64_FEATURE_COMPNUM) 84 #define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \ 85 AARCH64_FEATURE_V8_4 \ 86 | AARCH64_FEATURE_DOTPROD \ 87 | AARCH64_FEATURE_F16_FML) 88 89 #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) 90 #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */ 91 92 /* CPU-specific features. */ 93 typedef unsigned long long aarch64_feature_set; 94 95 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \ 96 ((~(CPU) & (FEAT)) == 0) 97 98 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \ 99 (((CPU) & (FEAT)) != 0) 100 101 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \ 102 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT) 103 104 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \ 105 do \ 106 { \ 107 (TARG) = (F1) | (F2); \ 108 } \ 109 while (0) 110 111 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \ 112 do \ 113 { \ 114 (TARG) = (F1) &~ (F2); \ 115 } \ 116 while (0) 117 118 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc)) 119 120 enum aarch64_operand_class 121 { 122 AARCH64_OPND_CLASS_NIL, 123 AARCH64_OPND_CLASS_INT_REG, 124 AARCH64_OPND_CLASS_MODIFIED_REG, 125 AARCH64_OPND_CLASS_FP_REG, 126 AARCH64_OPND_CLASS_SIMD_REG, 127 AARCH64_OPND_CLASS_SIMD_ELEMENT, 128 AARCH64_OPND_CLASS_SISD_REG, 129 AARCH64_OPND_CLASS_SIMD_REGLIST, 130 AARCH64_OPND_CLASS_SVE_REG, 131 AARCH64_OPND_CLASS_PRED_REG, 132 AARCH64_OPND_CLASS_ADDRESS, 133 AARCH64_OPND_CLASS_IMMEDIATE, 134 AARCH64_OPND_CLASS_SYSTEM, 135 AARCH64_OPND_CLASS_COND, 136 }; 137 138 /* Operand code that helps both parsing and coding. 139 Keep AARCH64_OPERANDS synced. */ 140 141 enum aarch64_opnd 142 { 143 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/ 144 145 AARCH64_OPND_Rd, /* Integer register as destination. */ 146 AARCH64_OPND_Rn, /* Integer register as source. */ 147 AARCH64_OPND_Rm, /* Integer register as source. */ 148 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */ 149 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */ 150 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */ 151 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */ 152 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */ 153 154 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */ 155 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */ 156 AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */ 157 AARCH64_OPND_PAIRREG, /* Paired register operand. */ 158 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */ 159 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */ 160 161 AARCH64_OPND_Fd, /* Floating-point Fd. */ 162 AARCH64_OPND_Fn, /* Floating-point Fn. */ 163 AARCH64_OPND_Fm, /* Floating-point Fm. */ 164 AARCH64_OPND_Fa, /* Floating-point Fa. */ 165 AARCH64_OPND_Ft, /* Floating-point Ft. */ 166 AARCH64_OPND_Ft2, /* Floating-point Ft2. */ 167 168 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */ 169 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */ 170 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */ 171 172 AARCH64_OPND_Va, /* AdvSIMD Vector Va. */ 173 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */ 174 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */ 175 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */ 176 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */ 177 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */ 178 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */ 179 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */ 180 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */ 181 AARCH64_OPND_Em16, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when 182 qualifier is S_H. */ 183 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */ 184 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */ 185 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single 186 structure to all lanes. */ 187 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */ 188 189 AARCH64_OPND_CRn, /* Co-processor register in CRn field. */ 190 AARCH64_OPND_CRm, /* Co-processor register in CRm field. */ 191 192 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */ 193 AARCH64_OPND_MASK, /* AdvSIMD EXT index operand. */ 194 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */ 195 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */ 196 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */ 197 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */ 198 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */ 199 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction 200 (no encoding). */ 201 AARCH64_OPND_IMM0, /* Immediate for #0. */ 202 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */ 203 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */ 204 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */ 205 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */ 206 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */ 207 AARCH64_OPND_IMM, /* Immediate. */ 208 AARCH64_OPND_IMM_2, /* Immediate. */ 209 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */ 210 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */ 211 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */ 212 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */ 213 AARCH64_OPND_BIT_NUM, /* Immediate. */ 214 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */ 215 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */ 216 AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */ 217 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for 218 each condition flag. */ 219 220 AARCH64_OPND_LIMM, /* Logical Immediate. */ 221 AARCH64_OPND_AIMM, /* Arithmetic immediate. */ 222 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */ 223 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */ 224 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */ 225 AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */ 226 AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */ 227 AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */ 228 229 AARCH64_OPND_COND, /* Standard condition as the last operand. */ 230 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */ 231 232 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */ 233 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */ 234 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */ 235 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */ 236 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */ 237 238 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */ 239 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */ 240 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */ 241 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */ 242 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is 243 negative or unaligned and there is 244 no writeback allowed. This operand code 245 is only used to support the programmer- 246 friendly feature of using LDR/STR as the 247 the mnemonic name for LDUR/STUR instructions 248 wherever there is no ambiguity. */ 249 AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */ 250 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */ 251 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */ 252 AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */ 253 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */ 254 255 AARCH64_OPND_SYSREG, /* System register operand. */ 256 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */ 257 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */ 258 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */ 259 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */ 260 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */ 261 AARCH64_OPND_BARRIER, /* Barrier operand. */ 262 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */ 263 AARCH64_OPND_PRFOP, /* Prefetch operation. */ 264 AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */ 265 266 AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */ 267 AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */ 268 AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */ 269 AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */ 270 AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */ 271 AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */ 272 AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */ 273 AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */ 274 AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */ 275 AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */ 276 AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */ 277 AARCH64_OPND_SVE_ADDR_R, /* SVE [<Xn|SP>]. */ 278 AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */ 279 AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */ 280 AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */ 281 AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */ 282 AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */ 283 AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */ 284 AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */ 285 AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */ 286 AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */ 287 AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */ 288 AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */ 289 AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */ 290 AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW]. 291 Bit 14 controls S/U choice. */ 292 AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW]. 293 Bit 22 controls S/U choice. */ 294 AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1]. 295 Bit 14 controls S/U choice. */ 296 AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1]. 297 Bit 22 controls S/U choice. */ 298 AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2]. 299 Bit 14 controls S/U choice. */ 300 AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2]. 301 Bit 22 controls S/U choice. */ 302 AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3]. 303 Bit 14 controls S/U choice. */ 304 AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3]. 305 Bit 22 controls S/U choice. */ 306 AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */ 307 AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */ 308 AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */ 309 AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */ 310 AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */ 311 AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */ 312 AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */ 313 AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */ 314 AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */ 315 AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */ 316 AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */ 317 AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */ 318 AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */ 319 AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */ 320 AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */ 321 AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */ 322 AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */ 323 AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */ 324 AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */ 325 AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */ 326 AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */ 327 AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */ 328 AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */ 329 AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */ 330 AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */ 331 AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */ 332 AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */ 333 AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */ 334 AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */ 335 AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */ 336 AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */ 337 AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */ 338 AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */ 339 AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */ 340 AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */ 341 AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */ 342 AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */ 343 AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */ 344 AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */ 345 AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */ 346 AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */ 347 AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */ 348 AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */ 349 AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */ 350 AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */ 351 AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */ 352 AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */ 353 AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */ 354 AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */ 355 AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */ 356 AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */ 357 AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */ 358 AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */ 359 AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */ 360 AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */ 361 AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */ 362 AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */ 363 AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */ 364 AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */ 365 AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */ 366 AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */ 367 }; 368 369 /* Qualifier constrains an operand. It either specifies a variant of an 370 operand type or limits values available to an operand type. 371 372 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */ 373 374 enum aarch64_opnd_qualifier 375 { 376 /* Indicating no further qualification on an operand. */ 377 AARCH64_OPND_QLF_NIL, 378 379 /* Qualifying an operand which is a general purpose (integer) register; 380 indicating the operand data size or a specific register. */ 381 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */ 382 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */ 383 AARCH64_OPND_QLF_WSP, /* WSP. */ 384 AARCH64_OPND_QLF_SP, /* SP. */ 385 386 /* Qualifying an operand which is a floating-point register, a SIMD 387 vector element or a SIMD vector element list; indicating operand data 388 size or the size of each SIMD vector element in the case of a SIMD 389 vector element list. 390 These qualifiers are also used to qualify an address operand to 391 indicate the size of data element a load/store instruction is 392 accessing. 393 They are also used for the immediate shift operand in e.g. SSHR. Such 394 a use is only for the ease of operand encoding/decoding and qualifier 395 sequence matching; such a use should not be applied widely; use the value 396 constraint qualifiers for immediate operands wherever possible. */ 397 AARCH64_OPND_QLF_S_B, 398 AARCH64_OPND_QLF_S_H, 399 AARCH64_OPND_QLF_S_S, 400 AARCH64_OPND_QLF_S_D, 401 AARCH64_OPND_QLF_S_Q, 402 /* This type qualifier has a special meaning in that it means that 4 x 1 byte 403 are selected by the instruction. Other than that it has no difference 404 with AARCH64_OPND_QLF_S_B in encoding. It is here purely for syntactical 405 reasons and is an exception from normal AArch64 disassembly scheme. */ 406 AARCH64_OPND_QLF_S_4B, 407 408 /* Qualifying an operand which is a SIMD vector register or a SIMD vector 409 register list; indicating register shape. 410 They are also used for the immediate shift operand in e.g. SSHR. Such 411 a use is only for the ease of operand encoding/decoding and qualifier 412 sequence matching; such a use should not be applied widely; use the value 413 constraint qualifiers for immediate operands wherever possible. */ 414 AARCH64_OPND_QLF_V_4B, 415 AARCH64_OPND_QLF_V_8B, 416 AARCH64_OPND_QLF_V_16B, 417 AARCH64_OPND_QLF_V_2H, 418 AARCH64_OPND_QLF_V_4H, 419 AARCH64_OPND_QLF_V_8H, 420 AARCH64_OPND_QLF_V_2S, 421 AARCH64_OPND_QLF_V_4S, 422 AARCH64_OPND_QLF_V_1D, 423 AARCH64_OPND_QLF_V_2D, 424 AARCH64_OPND_QLF_V_1Q, 425 426 AARCH64_OPND_QLF_P_Z, 427 AARCH64_OPND_QLF_P_M, 428 429 /* Constraint on value. */ 430 AARCH64_OPND_QLF_CR, /* CRn, CRm. */ 431 AARCH64_OPND_QLF_imm_0_7, 432 AARCH64_OPND_QLF_imm_0_15, 433 AARCH64_OPND_QLF_imm_0_31, 434 AARCH64_OPND_QLF_imm_0_63, 435 AARCH64_OPND_QLF_imm_1_32, 436 AARCH64_OPND_QLF_imm_1_64, 437 438 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros 439 or shift-ones. */ 440 AARCH64_OPND_QLF_LSL, 441 AARCH64_OPND_QLF_MSL, 442 443 /* Special qualifier helping retrieve qualifier information during the 444 decoding time (currently not in use). */ 445 AARCH64_OPND_QLF_RETRIEVE, 446 }; 447 448 /* Instruction class. */ 450 451 enum aarch64_insn_class 452 { 453 addsub_carry, 454 addsub_ext, 455 addsub_imm, 456 addsub_shift, 457 asimdall, 458 asimddiff, 459 asimdelem, 460 asimdext, 461 asimdimm, 462 asimdins, 463 asimdmisc, 464 asimdperm, 465 asimdsame, 466 asimdshf, 467 asimdtbl, 468 asisddiff, 469 asisdelem, 470 asisdlse, 471 asisdlsep, 472 asisdlso, 473 asisdlsop, 474 asisdmisc, 475 asisdone, 476 asisdpair, 477 asisdsame, 478 asisdshf, 479 bitfield, 480 branch_imm, 481 branch_reg, 482 compbranch, 483 condbranch, 484 condcmp_imm, 485 condcmp_reg, 486 condsel, 487 cryptoaes, 488 cryptosha2, 489 cryptosha3, 490 dp_1src, 491 dp_2src, 492 dp_3src, 493 exception, 494 extract, 495 float2fix, 496 float2int, 497 floatccmp, 498 floatcmp, 499 floatdp1, 500 floatdp2, 501 floatdp3, 502 floatimm, 503 floatsel, 504 ldst_immpost, 505 ldst_immpre, 506 ldst_imm9, /* immpost or immpre */ 507 ldst_imm10, /* LDRAA/LDRAB */ 508 ldst_pos, 509 ldst_regoff, 510 ldst_unpriv, 511 ldst_unscaled, 512 ldstexcl, 513 ldstnapair_offs, 514 ldstpair_off, 515 ldstpair_indexed, 516 loadlit, 517 log_imm, 518 log_shift, 519 lse_atomic, 520 movewide, 521 pcreladdr, 522 ic_system, 523 sve_cpy, 524 sve_index, 525 sve_limm, 526 sve_misc, 527 sve_movprfx, 528 sve_pred_zm, 529 sve_shift_pred, 530 sve_shift_unpred, 531 sve_size_bhs, 532 sve_size_bhsd, 533 sve_size_hsd, 534 sve_size_sd, 535 testbranch, 536 cryptosm3, 537 cryptosm4, 538 dotproduct, 539 }; 540 541 /* Opcode enumerators. */ 542 543 enum aarch64_op 544 { 545 OP_NIL, 546 OP_STRB_POS, 547 OP_LDRB_POS, 548 OP_LDRSB_POS, 549 OP_STRH_POS, 550 OP_LDRH_POS, 551 OP_LDRSH_POS, 552 OP_STR_POS, 553 OP_LDR_POS, 554 OP_STRF_POS, 555 OP_LDRF_POS, 556 OP_LDRSW_POS, 557 OP_PRFM_POS, 558 559 OP_STURB, 560 OP_LDURB, 561 OP_LDURSB, 562 OP_STURH, 563 OP_LDURH, 564 OP_LDURSH, 565 OP_STUR, 566 OP_LDUR, 567 OP_STURV, 568 OP_LDURV, 569 OP_LDURSW, 570 OP_PRFUM, 571 572 OP_LDR_LIT, 573 OP_LDRV_LIT, 574 OP_LDRSW_LIT, 575 OP_PRFM_LIT, 576 577 OP_ADD, 578 OP_B, 579 OP_BL, 580 581 OP_MOVN, 582 OP_MOVZ, 583 OP_MOVK, 584 585 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */ 586 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */ 587 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */ 588 589 OP_MOV_V, /* MOV alias for moving vector register. */ 590 591 OP_ASR_IMM, 592 OP_LSR_IMM, 593 OP_LSL_IMM, 594 595 OP_BIC, 596 597 OP_UBFX, 598 OP_BFXIL, 599 OP_SBFX, 600 OP_SBFIZ, 601 OP_BFI, 602 OP_BFC, /* ARMv8.2. */ 603 OP_UBFIZ, 604 OP_UXTB, 605 OP_UXTH, 606 OP_UXTW, 607 608 OP_CINC, 609 OP_CINV, 610 OP_CNEG, 611 OP_CSET, 612 OP_CSETM, 613 614 OP_FCVT, 615 OP_FCVTN, 616 OP_FCVTN2, 617 OP_FCVTL, 618 OP_FCVTL2, 619 OP_FCVTXN_S, /* Scalar version. */ 620 621 OP_ROR_IMM, 622 623 OP_SXTL, 624 OP_SXTL2, 625 OP_UXTL, 626 OP_UXTL2, 627 628 OP_MOV_P_P, 629 OP_MOV_Z_P_Z, 630 OP_MOV_Z_V, 631 OP_MOV_Z_Z, 632 OP_MOV_Z_Zi, 633 OP_MOVM_P_P_P, 634 OP_MOVS_P_P, 635 OP_MOVZS_P_P_P, 636 OP_MOVZ_P_P_P, 637 OP_NOTS_P_P_P_Z, 638 OP_NOT_P_P_P_Z, 639 640 OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */ 641 642 OP_TOTAL_NUM, /* Pseudo. */ 643 }; 644 645 /* Maximum number of operands an instruction can have. */ 646 #define AARCH64_MAX_OPND_NUM 6 647 /* Maximum number of qualifier sequences an instruction can have. */ 648 #define AARCH64_MAX_QLF_SEQ_NUM 10 649 /* Operand qualifier typedef; optimized for the size. */ 650 typedef unsigned char aarch64_opnd_qualifier_t; 651 /* Operand qualifier sequence typedef. */ 652 typedef aarch64_opnd_qualifier_t \ 653 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM]; 654 655 /* FIXME: improve the efficiency. */ 656 static inline bfd_boolean 657 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers) 658 { 659 int i; 660 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) 661 if (qualifiers[i] != AARCH64_OPND_QLF_NIL) 662 return FALSE; 663 return TRUE; 664 } 665 666 /* This structure holds information for a particular opcode. */ 667 668 struct aarch64_opcode 669 { 670 /* The name of the mnemonic. */ 671 const char *name; 672 673 /* The opcode itself. Those bits which will be filled in with 674 operands are zeroes. */ 675 aarch64_insn opcode; 676 677 /* The opcode mask. This is used by the disassembler. This is a 678 mask containing ones indicating those bits which must match the 679 opcode field, and zeroes indicating those bits which need not 680 match (and are presumably filled in by operands). */ 681 aarch64_insn mask; 682 683 /* Instruction class. */ 684 enum aarch64_insn_class iclass; 685 686 /* Enumerator identifier. */ 687 enum aarch64_op op; 688 689 /* Which architecture variant provides this instruction. */ 690 const aarch64_feature_set *avariant; 691 692 /* An array of operand codes. Each code is an index into the 693 operand table. They appear in the order which the operands must 694 appear in assembly code, and are terminated by a zero. */ 695 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM]; 696 697 /* A list of operand qualifier code sequence. Each operand qualifier 698 code qualifies the corresponding operand code. Each operand 699 qualifier sequence specifies a valid opcode variant and related 700 constraint on operands. */ 701 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM]; 702 703 /* Flags providing information about this instruction */ 704 uint32_t flags; 705 706 /* If nonzero, this operand and operand 0 are both registers and 707 are required to have the same register number. */ 708 unsigned char tied_operand; 709 710 /* If non-NULL, a function to verify that a given instruction is valid. */ 711 bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn); 712 }; 713 714 typedef struct aarch64_opcode aarch64_opcode; 715 716 /* Table describing all the AArch64 opcodes. */ 717 extern aarch64_opcode aarch64_opcode_table[]; 718 719 /* Opcode flags. */ 720 #define F_ALIAS (1 << 0) 721 #define F_HAS_ALIAS (1 << 1) 722 /* Disassembly preference priority 1-3 (the larger the higher). If nothing 723 is specified, it is the priority 0 by default, i.e. the lowest priority. */ 724 #define F_P1 (1 << 2) 725 #define F_P2 (2 << 2) 726 #define F_P3 (3 << 2) 727 /* Flag an instruction that is truly conditional executed, e.g. b.cond. */ 728 #define F_COND (1 << 4) 729 /* Instruction has the field of 'sf'. */ 730 #define F_SF (1 << 5) 731 /* Instruction has the field of 'size:Q'. */ 732 #define F_SIZEQ (1 << 6) 733 /* Floating-point instruction has the field of 'type'. */ 734 #define F_FPTYPE (1 << 7) 735 /* AdvSIMD scalar instruction has the field of 'size'. */ 736 #define F_SSIZE (1 << 8) 737 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */ 738 #define F_T (1 << 9) 739 /* Size of GPR operand in AdvSIMD instructions encoded in Q. */ 740 #define F_GPRSIZE_IN_Q (1 << 10) 741 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */ 742 #define F_LDS_SIZE (1 << 11) 743 /* Optional operand; assume maximum of 1 operand can be optional. */ 744 #define F_OPD0_OPT (1 << 12) 745 #define F_OPD1_OPT (2 << 12) 746 #define F_OPD2_OPT (3 << 12) 747 #define F_OPD3_OPT (4 << 12) 748 #define F_OPD4_OPT (5 << 12) 749 /* Default value for the optional operand when omitted from the assembly. */ 750 #define F_DEFAULT(X) (((X) & 0x1f) << 15) 751 /* Instruction that is an alias of another instruction needs to be 752 encoded/decoded by converting it to/from the real form, followed by 753 the encoding/decoding according to the rules of the real opcode. 754 This compares to the direct coding using the alias's information. 755 N.B. this flag requires F_ALIAS to be used together. */ 756 #define F_CONV (1 << 20) 757 /* Use together with F_ALIAS to indicate an alias opcode is a programmer 758 friendly pseudo instruction available only in the assembly code (thus will 759 not show up in the disassembly). */ 760 #define F_PSEUDO (1 << 21) 761 /* Instruction has miscellaneous encoding/decoding rules. */ 762 #define F_MISC (1 << 22) 763 /* Instruction has the field of 'N'; used in conjunction with F_SF. */ 764 #define F_N (1 << 23) 765 /* Opcode dependent field. */ 766 #define F_OD(X) (((X) & 0x7) << 24) 767 /* Instruction has the field of 'sz'. */ 768 #define F_LSE_SZ (1 << 27) 769 /* Require an exact qualifier match, even for NIL qualifiers. */ 770 #define F_STRICT (1ULL << 28) 771 /* This system instruction is used to read system registers. */ 772 #define F_SYS_READ (1ULL << 29) 773 /* This system instruction is used to write system registers. */ 774 #define F_SYS_WRITE (1ULL << 30) 775 /* Next bit is 31. */ 776 777 static inline bfd_boolean 778 alias_opcode_p (const aarch64_opcode *opcode) 779 { 780 return (opcode->flags & F_ALIAS) ? TRUE : FALSE; 781 } 782 783 static inline bfd_boolean 784 opcode_has_alias (const aarch64_opcode *opcode) 785 { 786 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE; 787 } 788 789 /* Priority for disassembling preference. */ 790 static inline int 791 opcode_priority (const aarch64_opcode *opcode) 792 { 793 return (opcode->flags >> 2) & 0x3; 794 } 795 796 static inline bfd_boolean 797 pseudo_opcode_p (const aarch64_opcode *opcode) 798 { 799 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE; 800 } 801 802 static inline bfd_boolean 803 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx) 804 { 805 return (((opcode->flags >> 12) & 0x7) == idx + 1) 806 ? TRUE : FALSE; 807 } 808 809 static inline aarch64_insn 810 get_optional_operand_default_value (const aarch64_opcode *opcode) 811 { 812 return (opcode->flags >> 15) & 0x1f; 813 } 814 815 static inline unsigned int 816 get_opcode_dependent_value (const aarch64_opcode *opcode) 817 { 818 return (opcode->flags >> 24) & 0x7; 819 } 820 821 static inline bfd_boolean 822 opcode_has_special_coder (const aarch64_opcode *opcode) 823 { 824 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T 825 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE 826 : FALSE; 827 } 828 829 struct aarch64_name_value_pair 831 { 832 const char * name; 833 aarch64_insn value; 834 }; 835 836 extern const struct aarch64_name_value_pair aarch64_operand_modifiers []; 837 extern const struct aarch64_name_value_pair aarch64_barrier_options [16]; 838 extern const struct aarch64_name_value_pair aarch64_prfops [32]; 839 extern const struct aarch64_name_value_pair aarch64_hint_options []; 840 841 typedef struct 842 { 843 const char * name; 844 aarch64_insn value; 845 uint32_t flags; 846 } aarch64_sys_reg; 847 848 extern const aarch64_sys_reg aarch64_sys_regs []; 849 extern const aarch64_sys_reg aarch64_pstatefields []; 850 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *); 851 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set, 852 const aarch64_sys_reg *); 853 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set, 854 const aarch64_sys_reg *); 855 856 typedef struct 857 { 858 const char *name; 859 uint32_t value; 860 uint32_t flags ; 861 } aarch64_sys_ins_reg; 862 863 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *); 864 extern bfd_boolean 865 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set, 866 const aarch64_sys_ins_reg *); 867 868 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic []; 869 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc []; 870 extern const aarch64_sys_ins_reg aarch64_sys_regs_at []; 871 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi []; 872 873 /* Shift/extending operator kinds. 874 N.B. order is important; keep aarch64_operand_modifiers synced. */ 875 enum aarch64_modifier_kind 876 { 877 AARCH64_MOD_NONE, 878 AARCH64_MOD_MSL, 879 AARCH64_MOD_ROR, 880 AARCH64_MOD_ASR, 881 AARCH64_MOD_LSR, 882 AARCH64_MOD_LSL, 883 AARCH64_MOD_UXTB, 884 AARCH64_MOD_UXTH, 885 AARCH64_MOD_UXTW, 886 AARCH64_MOD_UXTX, 887 AARCH64_MOD_SXTB, 888 AARCH64_MOD_SXTH, 889 AARCH64_MOD_SXTW, 890 AARCH64_MOD_SXTX, 891 AARCH64_MOD_MUL, 892 AARCH64_MOD_MUL_VL, 893 }; 894 895 bfd_boolean 896 aarch64_extend_operator_p (enum aarch64_modifier_kind); 897 898 enum aarch64_modifier_kind 899 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *); 900 /* Condition. */ 901 902 typedef struct 903 { 904 /* A list of names with the first one as the disassembly preference; 905 terminated by NULL if fewer than 3. */ 906 const char *names[4]; 907 aarch64_insn value; 908 } aarch64_cond; 909 910 extern const aarch64_cond aarch64_conds[16]; 911 912 const aarch64_cond* get_cond_from_value (aarch64_insn value); 913 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond); 914 915 /* Structure representing an operand. */ 917 918 struct aarch64_opnd_info 919 { 920 enum aarch64_opnd type; 921 aarch64_opnd_qualifier_t qualifier; 922 int idx; 923 924 union 925 { 926 struct 927 { 928 unsigned regno; 929 } reg; 930 struct 931 { 932 unsigned int regno; 933 int64_t index; 934 } reglane; 935 /* e.g. LVn. */ 936 struct 937 { 938 unsigned first_regno : 5; 939 unsigned num_regs : 3; 940 /* 1 if it is a list of reg element. */ 941 unsigned has_index : 1; 942 /* Lane index; valid only when has_index is 1. */ 943 int64_t index; 944 } reglist; 945 /* e.g. immediate or pc relative address offset. */ 946 struct 947 { 948 int64_t value; 949 unsigned is_fp : 1; 950 } imm; 951 /* e.g. address in STR (register offset). */ 952 struct 953 { 954 unsigned base_regno; 955 struct 956 { 957 union 958 { 959 int imm; 960 unsigned regno; 961 }; 962 unsigned is_reg; 963 } offset; 964 unsigned pcrel : 1; /* PC-relative. */ 965 unsigned writeback : 1; 966 unsigned preind : 1; /* Pre-indexed. */ 967 unsigned postind : 1; /* Post-indexed. */ 968 } addr; 969 970 struct 971 { 972 /* The encoding of the system register. */ 973 aarch64_insn value; 974 975 /* The system register flags. */ 976 uint32_t flags; 977 } sysreg; 978 979 const aarch64_cond *cond; 980 /* The encoding of the PSTATE field. */ 981 aarch64_insn pstatefield; 982 const aarch64_sys_ins_reg *sysins_op; 983 const struct aarch64_name_value_pair *barrier; 984 const struct aarch64_name_value_pair *hint_option; 985 const struct aarch64_name_value_pair *prfop; 986 }; 987 988 /* Operand shifter; in use when the operand is a register offset address, 989 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */ 990 struct 991 { 992 enum aarch64_modifier_kind kind; 993 unsigned operator_present: 1; /* Only valid during encoding. */ 994 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */ 995 unsigned amount_present: 1; 996 int64_t amount; 997 } shifter; 998 999 unsigned skip:1; /* Operand is not completed if there is a fixup needed 1000 to be done on it. In some (but not all) of these 1001 cases, we need to tell libopcodes to skip the 1002 constraint checking and the encoding for this 1003 operand, so that the libopcodes can pick up the 1004 right opcode before the operand is fixed-up. This 1005 flag should only be used during the 1006 assembling/encoding. */ 1007 unsigned present:1; /* Whether this operand is present in the assembly 1008 line; not used during the disassembly. */ 1009 }; 1010 1011 typedef struct aarch64_opnd_info aarch64_opnd_info; 1012 1013 /* Structure representing an instruction. 1014 1015 It is used during both the assembling and disassembling. The assembler 1016 fills an aarch64_inst after a successful parsing and then passes it to the 1017 encoding routine to do the encoding. During the disassembling, the 1018 disassembler calls the decoding routine to decode a binary instruction; on a 1019 successful return, such a structure will be filled with information of the 1020 instruction; then the disassembler uses the information to print out the 1021 instruction. */ 1022 1023 struct aarch64_inst 1024 { 1025 /* The value of the binary instruction. */ 1026 aarch64_insn value; 1027 1028 /* Corresponding opcode entry. */ 1029 const aarch64_opcode *opcode; 1030 1031 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */ 1032 const aarch64_cond *cond; 1033 1034 /* Operands information. */ 1035 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM]; 1036 }; 1037 1038 typedef struct aarch64_inst aarch64_inst; 1039 1040 /* Diagnosis related declaration and interface. */ 1042 1043 /* Operand error kind enumerators. 1044 1045 AARCH64_OPDE_RECOVERABLE 1046 Less severe error found during the parsing, very possibly because that 1047 GAS has picked up a wrong instruction template for the parsing. 1048 1049 AARCH64_OPDE_SYNTAX_ERROR 1050 General syntax error; it can be either a user error, or simply because 1051 that GAS is trying a wrong instruction template. 1052 1053 AARCH64_OPDE_FATAL_SYNTAX_ERROR 1054 Definitely a user syntax error. 1055 1056 AARCH64_OPDE_INVALID_VARIANT 1057 No syntax error, but the operands are not a valid combination, e.g. 1058 FMOV D0,S0 1059 1060 AARCH64_OPDE_UNTIED_OPERAND 1061 The asm failed to use the same register for a destination operand 1062 and a tied source operand. 1063 1064 AARCH64_OPDE_OUT_OF_RANGE 1065 Error about some immediate value out of a valid range. 1066 1067 AARCH64_OPDE_UNALIGNED 1068 Error about some immediate value not properly aligned (i.e. not being a 1069 multiple times of a certain value). 1070 1071 AARCH64_OPDE_REG_LIST 1072 Error about the register list operand having unexpected number of 1073 registers. 1074 1075 AARCH64_OPDE_OTHER_ERROR 1076 Error of the highest severity and used for any severe issue that does not 1077 fall into any of the above categories. 1078 1079 The enumerators are only interesting to GAS. They are declared here (in 1080 libopcodes) because that some errors are detected (and then notified to GAS) 1081 by libopcodes (rather than by GAS solely). 1082 1083 The first three errors are only deteced by GAS while the 1084 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as 1085 only libopcodes has the information about the valid variants of each 1086 instruction. 1087 1088 The enumerators have an increasing severity. This is helpful when there are 1089 multiple instruction templates available for a given mnemonic name (e.g. 1090 FMOV); this mechanism will help choose the most suitable template from which 1091 the generated diagnostics can most closely describe the issues, if any. */ 1092 1093 enum aarch64_operand_error_kind 1094 { 1095 AARCH64_OPDE_NIL, 1096 AARCH64_OPDE_RECOVERABLE, 1097 AARCH64_OPDE_SYNTAX_ERROR, 1098 AARCH64_OPDE_FATAL_SYNTAX_ERROR, 1099 AARCH64_OPDE_INVALID_VARIANT, 1100 AARCH64_OPDE_UNTIED_OPERAND, 1101 AARCH64_OPDE_OUT_OF_RANGE, 1102 AARCH64_OPDE_UNALIGNED, 1103 AARCH64_OPDE_REG_LIST, 1104 AARCH64_OPDE_OTHER_ERROR 1105 }; 1106 1107 /* N.B. GAS assumes that this structure work well with shallow copy. */ 1108 struct aarch64_operand_error 1109 { 1110 enum aarch64_operand_error_kind kind; 1111 int index; 1112 const char *error; 1113 int data[3]; /* Some data for extra information. */ 1114 bfd_boolean non_fatal; 1115 }; 1116 1117 typedef struct aarch64_operand_error aarch64_operand_error; 1118 1119 /* Encoding entrypoint. */ 1120 1121 extern int 1122 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *, 1123 aarch64_insn *, aarch64_opnd_qualifier_t *, 1124 aarch64_operand_error *); 1125 1126 extern const aarch64_opcode * 1127 aarch64_replace_opcode (struct aarch64_inst *, 1128 const aarch64_opcode *); 1129 1130 /* Given the opcode enumerator OP, return the pointer to the corresponding 1131 opcode entry. */ 1132 1133 extern const aarch64_opcode * 1134 aarch64_get_opcode (enum aarch64_op); 1135 1136 /* Generate the string representation of an operand. */ 1137 extern void 1138 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *, 1139 const aarch64_opnd_info *, int, int *, bfd_vma *, 1140 char **); 1141 1142 /* Miscellaneous interface. */ 1143 1144 extern int 1145 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd); 1146 1147 extern aarch64_opnd_qualifier_t 1148 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int, 1149 const aarch64_opnd_qualifier_t, int); 1150 1151 extern int 1152 aarch64_num_of_operands (const aarch64_opcode *); 1153 1154 extern int 1155 aarch64_stack_pointer_p (const aarch64_opnd_info *); 1156 1157 extern int 1158 aarch64_zero_register_p (const aarch64_opnd_info *); 1159 1160 extern int 1161 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean, 1162 aarch64_operand_error *errors); 1163 1164 /* Given an operand qualifier, return the expected data element size 1165 of a qualified operand. */ 1166 extern unsigned char 1167 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t); 1168 1169 extern enum aarch64_operand_class 1170 aarch64_get_operand_class (enum aarch64_opnd); 1171 1172 extern const char * 1173 aarch64_get_operand_name (enum aarch64_opnd); 1174 1175 extern const char * 1176 aarch64_get_operand_desc (enum aarch64_opnd); 1177 1178 extern bfd_boolean 1179 aarch64_sve_dupm_mov_immediate_p (uint64_t, int); 1180 1181 #ifdef DEBUG_AARCH64 1182 extern int debug_dump; 1183 1184 extern void 1185 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2))); 1186 1187 #define DEBUG_TRACE(M, ...) \ 1188 { \ 1189 if (debug_dump) \ 1190 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ 1191 } 1192 1193 #define DEBUG_TRACE_IF(C, M, ...) \ 1194 { \ 1195 if (debug_dump && (C)) \ 1196 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ 1197 } 1198 #else /* !DEBUG_AARCH64 */ 1199 #define DEBUG_TRACE(M, ...) ; 1200 #define DEBUG_TRACE_IF(C, M, ...) ; 1201 #endif /* DEBUG_AARCH64 */ 1202 1203 extern const char *const aarch64_sve_pattern_array[32]; 1204 extern const char *const aarch64_sve_prfop_array[16]; 1205 1206 #ifdef __cplusplus 1207 } 1208 #endif 1209 1210 #endif /* OPCODE_AARCH64_H */ 1211
Indexes created Thu Apr 02 00:23:07 UTC 2026