m32r-desc.h revision 1.1.1.4.12.1
1 /* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */ 2 /* CPU data header for m32r. 3 4 THIS FILE IS MACHINE GENERATED WITH CGEN. 5 6 Copyright (C) 1996-2018 Free Software Foundation, Inc. 7 8 This file is part of the GNU Binutils and/or GDB, the GNU debugger. 9 10 This file is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 3, or (at your option) 13 any later version. 14 15 It is distributed in the hope that it will be useful, but WITHOUT 16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 18 License for more details. 19 20 You should have received a copy of the GNU General Public License along 21 with this program; if not, write to the Free Software Foundation, Inc., 22 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 23 24 */ 25 26 #ifndef M32R_CPU_H 27 #define M32R_CPU_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #define CGEN_ARCH m32r 34 35 /* Given symbol S, return m32r_cgen_<S>. */ 36 #define CGEN_SYM(s) m32r##_cgen_##s 37 38 39 /* Selected cpu families. */ 40 #define HAVE_CPU_M32RBF 41 #define HAVE_CPU_M32RXF 42 #define HAVE_CPU_M32R2F 43 44 #define CGEN_INSN_LSB0_P 0 45 46 /* Minimum size of any insn (in bytes). */ 47 #define CGEN_MIN_INSN_SIZE 2 48 49 /* Maximum size of any insn (in bytes). */ 50 #define CGEN_MAX_INSN_SIZE 4 51 52 #define CGEN_INT_INSN_P 1 53 54 /* Maximum number of syntax elements in an instruction. */ 55 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 15 56 57 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. 58 e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands 59 we can't hash on everything up to the space. */ 60 #define CGEN_MNEMONIC_OPERANDS 61 62 /* Maximum number of fields in an instruction. */ 63 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 7 64 65 /* Enums. */ 66 67 /* Enum declaration for insn format enums. */ 68 typedef enum insn_op1 { 69 OP1_0, OP1_1, OP1_2, OP1_3 70 , OP1_4, OP1_5, OP1_6, OP1_7 71 , OP1_8, OP1_9, OP1_10, OP1_11 72 , OP1_12, OP1_13, OP1_14, OP1_15 73 } INSN_OP1; 74 75 /* Enum declaration for op2 enums. */ 76 typedef enum insn_op2 { 77 OP2_0, OP2_1, OP2_2, OP2_3 78 , OP2_4, OP2_5, OP2_6, OP2_7 79 , OP2_8, OP2_9, OP2_10, OP2_11 80 , OP2_12, OP2_13, OP2_14, OP2_15 81 } INSN_OP2; 82 83 /* Enum declaration for . */ 84 typedef enum gr_names { 85 H_GR_FP = 13, H_GR_LR = 14, H_GR_SP = 15, H_GR_R0 = 0 86 , H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4 87 , H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8 88 , H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12 89 , H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15 90 } GR_NAMES; 91 92 /* Enum declaration for . */ 93 typedef enum cr_names { 94 H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3 95 , H_CR_BPC = 6, H_CR_BBPSW = 8, H_CR_BBPC = 14, H_CR_EVB = 5 96 , H_CR_CR0 = 0, H_CR_CR1 = 1, H_CR_CR2 = 2, H_CR_CR3 = 3 97 , H_CR_CR4 = 4, H_CR_CR5 = 5, H_CR_CR6 = 6, H_CR_CR7 = 7 98 , H_CR_CR8 = 8, H_CR_CR9 = 9, H_CR_CR10 = 10, H_CR_CR11 = 11 99 , H_CR_CR12 = 12, H_CR_CR13 = 13, H_CR_CR14 = 14, H_CR_CR15 = 15 100 } CR_NAMES; 101 102 /* Attributes. */ 103 104 /* Enum declaration for machine type selection. */ 105 typedef enum mach_attr { 106 MACH_BASE, MACH_M32R, MACH_M32RX, MACH_M32R2 107 , MACH_MAX 108 } MACH_ATTR; 109 110 /* Enum declaration for instruction set selection. */ 111 typedef enum isa_attr { 112 ISA_M32R, ISA_MAX 113 } ISA_ATTR; 114 115 /* Enum declaration for parallel execution pipeline selection. */ 116 typedef enum pipe_attr { 117 PIPE_NONE, PIPE_O, PIPE_S, PIPE_OS 118 , PIPE_O_OS 119 } PIPE_ATTR; 120 121 /* Number of architecture variants. */ 122 #define MAX_ISAS 1 123 #define MAX_MACHS ((int) MACH_MAX) 124 125 /* Ifield support. */ 126 127 /* Ifield attribute indices. */ 128 129 /* Enum declaration for cgen_ifld attrs. */ 130 typedef enum cgen_ifld_attr { 131 CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED 132 , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_RELOC, CGEN_IFLD_END_BOOLS 133 , CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS 134 } CGEN_IFLD_ATTR; 135 136 /* Number of non-boolean elements in cgen_ifld_attr. */ 137 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) 138 139 /* cgen_ifld attribute accessor macros. */ 140 #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) 141 #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0) 142 #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) 143 #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0) 144 #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0) 145 #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0) 146 #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0) 147 #define CGEN_ATTR_CGEN_IFLD_RELOC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RELOC)) != 0) 148 149 /* Enum declaration for m32r ifield types. */ 150 typedef enum ifield_type { 151 M32R_F_NIL, M32R_F_ANYOF, M32R_F_OP1, M32R_F_OP2 152 , M32R_F_COND, M32R_F_R1, M32R_F_R2, M32R_F_SIMM8 153 , M32R_F_SIMM16, M32R_F_SHIFT_OP2, M32R_F_UIMM3, M32R_F_UIMM4 154 , M32R_F_UIMM5, M32R_F_UIMM8, M32R_F_UIMM16, M32R_F_UIMM24 155 , M32R_F_HI16, M32R_F_DISP8, M32R_F_DISP16, M32R_F_DISP24 156 , M32R_F_OP23, M32R_F_OP3, M32R_F_ACC, M32R_F_ACCS 157 , M32R_F_ACCD, M32R_F_BITS67, M32R_F_BIT4, M32R_F_BIT14 158 , M32R_F_IMM1, M32R_F_MAX 159 } IFIELD_TYPE; 160 161 #define MAX_IFLD ((int) M32R_F_MAX) 162 163 /* Hardware attribute indices. */ 164 165 /* Enum declaration for cgen_hw attrs. */ 166 typedef enum cgen_hw_attr { 167 CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE 168 , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS 169 } CGEN_HW_ATTR; 170 171 /* Number of non-boolean elements in cgen_hw_attr. */ 172 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) 173 174 /* cgen_hw attribute accessor macros. */ 175 #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) 176 #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0) 177 #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0) 178 #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0) 179 #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0) 180 181 /* Enum declaration for m32r hardware types. */ 182 typedef enum cgen_hw_type { 183 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR 184 , HW_H_IADDR, HW_H_PC, HW_H_HI16, HW_H_SLO16 185 , HW_H_ULO16, HW_H_GR, HW_H_CR, HW_H_ACCUM 186 , HW_H_ACCUMS, HW_H_COND, HW_H_PSW, HW_H_BPSW 187 , HW_H_BBPSW, HW_H_LOCK, HW_MAX 188 } CGEN_HW_TYPE; 189 190 #define MAX_HW ((int) HW_MAX) 191 192 /* Operand attribute indices. */ 193 194 /* Enum declaration for cgen_operand attrs. */ 195 typedef enum cgen_operand_attr { 196 CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT 197 , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY 198 , CGEN_OPERAND_RELOC, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH 199 , CGEN_OPERAND_END_NBOOLS 200 } CGEN_OPERAND_ATTR; 201 202 /* Number of non-boolean elements in cgen_operand_attr. */ 203 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) 204 205 /* cgen_operand attribute accessor macros. */ 206 #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) 207 #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0) 208 #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) 209 #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) 210 #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) 211 #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0) 212 #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0) 213 #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0) 214 #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) 215 #define CGEN_ATTR_CGEN_OPERAND_RELOC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELOC)) != 0) 216 217 /* Enum declaration for m32r operand types. */ 218 typedef enum cgen_operand_type { 219 M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1 220 , M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8 221 , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM3, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5 222 , M32R_OPERAND_UIMM8, M32R_OPERAND_UIMM16, M32R_OPERAND_IMM1, M32R_OPERAND_ACCD 223 , M32R_OPERAND_ACCS, M32R_OPERAND_ACC, M32R_OPERAND_HASH, M32R_OPERAND_HI16 224 , M32R_OPERAND_SLO16, M32R_OPERAND_ULO16, M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8 225 , M32R_OPERAND_DISP16, M32R_OPERAND_DISP24, M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM 226 , M32R_OPERAND_MAX 227 } CGEN_OPERAND_TYPE; 228 229 /* Number of operands types. */ 230 #define MAX_OPERANDS 28 231 232 /* Maximum number of operands referenced by any insn. */ 233 #define MAX_OPERAND_INSTANCES 11 234 235 /* Insn attribute indices. */ 236 237 /* Enum declaration for cgen_insn attrs. */ 238 typedef enum cgen_insn_attr { 239 CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI 240 , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED 241 , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_FILL_SLOT, CGEN_INSN_SPECIAL 242 , CGEN_INSN_SPECIAL_M32R, CGEN_INSN_SPECIAL_FLOAT, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31 243 , CGEN_INSN_MACH, CGEN_INSN_PIPE, CGEN_INSN_END_NBOOLS 244 } CGEN_INSN_ATTR; 245 246 /* Number of non-boolean elements in cgen_insn_attr. */ 247 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) 248 249 /* cgen_insn attribute accessor macros. */ 250 #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) 251 #define CGEN_ATTR_CGEN_INSN_PIPE_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_PIPE-CGEN_INSN_START_NBOOLS-1].nonbitset) 252 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0) 253 #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0) 254 #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0) 255 #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0) 256 #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0) 257 #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0) 258 #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0) 259 #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0) 260 #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0) 261 #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0) 262 #define CGEN_ATTR_CGEN_INSN_FILL_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_FILL_SLOT)) != 0) 263 #define CGEN_ATTR_CGEN_INSN_SPECIAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SPECIAL)) != 0) 264 #define CGEN_ATTR_CGEN_INSN_SPECIAL_M32R_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SPECIAL_M32R)) != 0) 265 #define CGEN_ATTR_CGEN_INSN_SPECIAL_FLOAT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SPECIAL_FLOAT)) != 0) 266 267 /* cgen.h uses things we just defined. */ 268 #include "opcode/cgen.h" 269 270 extern const struct cgen_ifld m32r_cgen_ifld_table[]; 271 272 /* Attributes. */ 273 extern const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[]; 274 extern const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[]; 275 extern const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[]; 276 extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[]; 277 278 /* Hardware decls. */ 279 280 extern CGEN_KEYWORD m32r_cgen_opval_gr_names; 281 extern CGEN_KEYWORD m32r_cgen_opval_cr_names; 282 extern CGEN_KEYWORD m32r_cgen_opval_h_accums; 283 284 extern const CGEN_HW_ENTRY m32r_cgen_hw_table[]; 285 286 287 288 #ifdef __cplusplus 289 } 290 #endif 291 292 #endif /* M32R_CPU_H */ 293
Indexes created Sat Feb 28 05:31:39 UTC 2026