mips-dis.c revision 1.1.1.1
1 /* Print mips instructions for GDB, the GNU debugger, or for objdump. 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 3 2000, 2001, 2002, 2003, 2005, 2007, 2008 4 Free Software Foundation, Inc. 5 Contributed by Nobuyuki Hikichi(hikichi (at) sra.co.jp). 6 7 This file is part of the GNU opcodes library. 8 9 This library is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 It is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program; if not, write to the Free Software 21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 22 MA 02110-1301, USA. */ 23 24 #include "sysdep.h" 25 #include "dis-asm.h" 26 #include "libiberty.h" 27 #include "opcode/mips.h" 28 #include "opintl.h" 29 30 /* FIXME: These are needed to figure out if the code is mips16 or 31 not. The low bit of the address is often a good indicator. No 32 symbol table is available when this code runs out in an embedded 33 system as when it is used for disassembler support in a monitor. */ 34 35 #if !defined(EMBEDDED_ENV) 36 #define SYMTAB_AVAILABLE 1 37 #include "elf-bfd.h" 38 #include "elf/mips.h" 39 #endif 40 41 /* Mips instructions are at maximum this many bytes long. */ 42 #define INSNLEN 4 43 44 45 /* FIXME: These should be shared with gdb somehow. */ 47 48 struct mips_cp0sel_name 49 { 50 unsigned int cp0reg; 51 unsigned int sel; 52 const char * const name; 53 }; 54 55 /* The mips16 registers. */ 56 static const unsigned int mips16_to_32_reg_map[] = 57 { 58 16, 17, 2, 3, 4, 5, 6, 7 59 }; 60 61 #define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]] 62 63 64 static const char * const mips_gpr_names_numeric[32] = 65 { 66 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 67 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 68 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 69 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 70 }; 71 72 static const char * const mips_gpr_names_oldabi[32] = 73 { 74 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 75 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", 76 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 77 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 78 }; 79 80 static const char * const mips_gpr_names_newabi[32] = 81 { 82 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 83 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", 84 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 85 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 86 }; 87 88 static const char * const mips_fpr_names_numeric[32] = 89 { 90 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 91 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 92 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 93 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31" 94 }; 95 96 static const char * const mips_fpr_names_32[32] = 97 { 98 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f", 99 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f", 100 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f", 101 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f" 102 }; 103 104 static const char * const mips_fpr_names_n32[32] = 105 { 106 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3", 107 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", 108 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9", 109 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13" 110 }; 111 112 static const char * const mips_fpr_names_64[32] = 113 { 114 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3", 115 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", 116 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11", 117 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7" 118 }; 119 120 static const char * const mips_cp0_names_numeric[32] = 121 { 122 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 123 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 124 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 125 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 126 }; 127 128 static const char * const mips_cp0_names_r3000[32] = 129 { 130 "c0_index", "c0_random", "c0_entrylo", "$3", 131 "c0_context", "$5", "$6", "$7", 132 "c0_badvaddr", "$9", "c0_entryhi", "$11", 133 "c0_sr", "c0_cause", "c0_epc", "c0_prid", 134 "$16", "$17", "$18", "$19", 135 "$20", "$21", "$22", "$23", 136 "$24", "$25", "$26", "$27", 137 "$28", "$29", "$30", "$31", 138 }; 139 140 static const char * const mips_cp0_names_r4000[32] = 141 { 142 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 143 "c0_context", "c0_pagemask", "c0_wired", "$7", 144 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 145 "c0_sr", "c0_cause", "c0_epc", "c0_prid", 146 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 147 "c0_xcontext", "$21", "$22", "$23", 148 "$24", "$25", "c0_ecc", "c0_cacheerr", 149 "c0_taglo", "c0_taghi", "c0_errorepc", "$31", 150 }; 151 152 static const char * const mips_cp0_names_mips3264[32] = 153 { 154 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 155 "c0_context", "c0_pagemask", "c0_wired", "$7", 156 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 157 "c0_status", "c0_cause", "c0_epc", "c0_prid", 158 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 159 "c0_xcontext", "$21", "$22", "c0_debug", 160 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", 161 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", 162 }; 163 164 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = 165 { 166 { 16, 1, "c0_config1" }, 167 { 16, 2, "c0_config2" }, 168 { 16, 3, "c0_config3" }, 169 { 18, 1, "c0_watchlo,1" }, 170 { 18, 2, "c0_watchlo,2" }, 171 { 18, 3, "c0_watchlo,3" }, 172 { 18, 4, "c0_watchlo,4" }, 173 { 18, 5, "c0_watchlo,5" }, 174 { 18, 6, "c0_watchlo,6" }, 175 { 18, 7, "c0_watchlo,7" }, 176 { 19, 1, "c0_watchhi,1" }, 177 { 19, 2, "c0_watchhi,2" }, 178 { 19, 3, "c0_watchhi,3" }, 179 { 19, 4, "c0_watchhi,4" }, 180 { 19, 5, "c0_watchhi,5" }, 181 { 19, 6, "c0_watchhi,6" }, 182 { 19, 7, "c0_watchhi,7" }, 183 { 25, 1, "c0_perfcnt,1" }, 184 { 25, 2, "c0_perfcnt,2" }, 185 { 25, 3, "c0_perfcnt,3" }, 186 { 25, 4, "c0_perfcnt,4" }, 187 { 25, 5, "c0_perfcnt,5" }, 188 { 25, 6, "c0_perfcnt,6" }, 189 { 25, 7, "c0_perfcnt,7" }, 190 { 27, 1, "c0_cacheerr,1" }, 191 { 27, 2, "c0_cacheerr,2" }, 192 { 27, 3, "c0_cacheerr,3" }, 193 { 28, 1, "c0_datalo" }, 194 { 29, 1, "c0_datahi" } 195 }; 196 197 static const char * const mips_cp0_names_mips3264r2[32] = 198 { 199 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 200 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena", 201 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 202 "c0_status", "c0_cause", "c0_epc", "c0_prid", 203 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 204 "c0_xcontext", "$21", "$22", "c0_debug", 205 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", 206 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", 207 }; 208 209 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = 210 { 211 { 4, 1, "c0_contextconfig" }, 212 { 0, 1, "c0_mvpcontrol" }, 213 { 0, 2, "c0_mvpconf0" }, 214 { 0, 3, "c0_mvpconf1" }, 215 { 1, 1, "c0_vpecontrol" }, 216 { 1, 2, "c0_vpeconf0" }, 217 { 1, 3, "c0_vpeconf1" }, 218 { 1, 4, "c0_yqmask" }, 219 { 1, 5, "c0_vpeschedule" }, 220 { 1, 6, "c0_vpeschefback" }, 221 { 2, 1, "c0_tcstatus" }, 222 { 2, 2, "c0_tcbind" }, 223 { 2, 3, "c0_tcrestart" }, 224 { 2, 4, "c0_tchalt" }, 225 { 2, 5, "c0_tccontext" }, 226 { 2, 6, "c0_tcschedule" }, 227 { 2, 7, "c0_tcschefback" }, 228 { 5, 1, "c0_pagegrain" }, 229 { 6, 1, "c0_srsconf0" }, 230 { 6, 2, "c0_srsconf1" }, 231 { 6, 3, "c0_srsconf2" }, 232 { 6, 4, "c0_srsconf3" }, 233 { 6, 5, "c0_srsconf4" }, 234 { 12, 1, "c0_intctl" }, 235 { 12, 2, "c0_srsctl" }, 236 { 12, 3, "c0_srsmap" }, 237 { 15, 1, "c0_ebase" }, 238 { 16, 1, "c0_config1" }, 239 { 16, 2, "c0_config2" }, 240 { 16, 3, "c0_config3" }, 241 { 18, 1, "c0_watchlo,1" }, 242 { 18, 2, "c0_watchlo,2" }, 243 { 18, 3, "c0_watchlo,3" }, 244 { 18, 4, "c0_watchlo,4" }, 245 { 18, 5, "c0_watchlo,5" }, 246 { 18, 6, "c0_watchlo,6" }, 247 { 18, 7, "c0_watchlo,7" }, 248 { 19, 1, "c0_watchhi,1" }, 249 { 19, 2, "c0_watchhi,2" }, 250 { 19, 3, "c0_watchhi,3" }, 251 { 19, 4, "c0_watchhi,4" }, 252 { 19, 5, "c0_watchhi,5" }, 253 { 19, 6, "c0_watchhi,6" }, 254 { 19, 7, "c0_watchhi,7" }, 255 { 23, 1, "c0_tracecontrol" }, 256 { 23, 2, "c0_tracecontrol2" }, 257 { 23, 3, "c0_usertracedata" }, 258 { 23, 4, "c0_tracebpc" }, 259 { 25, 1, "c0_perfcnt,1" }, 260 { 25, 2, "c0_perfcnt,2" }, 261 { 25, 3, "c0_perfcnt,3" }, 262 { 25, 4, "c0_perfcnt,4" }, 263 { 25, 5, "c0_perfcnt,5" }, 264 { 25, 6, "c0_perfcnt,6" }, 265 { 25, 7, "c0_perfcnt,7" }, 266 { 27, 1, "c0_cacheerr,1" }, 267 { 27, 2, "c0_cacheerr,2" }, 268 { 27, 3, "c0_cacheerr,3" }, 269 { 28, 1, "c0_datalo" }, 270 { 28, 2, "c0_taglo1" }, 271 { 28, 3, "c0_datalo1" }, 272 { 28, 4, "c0_taglo2" }, 273 { 28, 5, "c0_datalo2" }, 274 { 28, 6, "c0_taglo3" }, 275 { 28, 7, "c0_datalo3" }, 276 { 29, 1, "c0_datahi" }, 277 { 29, 2, "c0_taghi1" }, 278 { 29, 3, "c0_datahi1" }, 279 { 29, 4, "c0_taghi2" }, 280 { 29, 5, "c0_datahi2" }, 281 { 29, 6, "c0_taghi3" }, 282 { 29, 7, "c0_datahi3" }, 283 }; 284 285 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */ 286 static const char * const mips_cp0_names_sb1[32] = 287 { 288 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 289 "c0_context", "c0_pagemask", "c0_wired", "$7", 290 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 291 "c0_status", "c0_cause", "c0_epc", "c0_prid", 292 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 293 "c0_xcontext", "$21", "$22", "c0_debug", 294 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i", 295 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave", 296 }; 297 298 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = 299 { 300 { 16, 1, "c0_config1" }, 301 { 18, 1, "c0_watchlo,1" }, 302 { 19, 1, "c0_watchhi,1" }, 303 { 22, 0, "c0_perftrace" }, 304 { 23, 3, "c0_edebug" }, 305 { 25, 1, "c0_perfcnt,1" }, 306 { 25, 2, "c0_perfcnt,2" }, 307 { 25, 3, "c0_perfcnt,3" }, 308 { 25, 4, "c0_perfcnt,4" }, 309 { 25, 5, "c0_perfcnt,5" }, 310 { 25, 6, "c0_perfcnt,6" }, 311 { 25, 7, "c0_perfcnt,7" }, 312 { 26, 1, "c0_buserr_pa" }, 313 { 27, 1, "c0_cacheerr_d" }, 314 { 27, 3, "c0_cacheerr_d_pa" }, 315 { 28, 1, "c0_datalo_i" }, 316 { 28, 2, "c0_taglo_d" }, 317 { 28, 3, "c0_datalo_d" }, 318 { 29, 1, "c0_datahi_i" }, 319 { 29, 2, "c0_taghi_d" }, 320 { 29, 3, "c0_datahi_d" }, 321 }; 322 323 static const char * const mips_hwr_names_numeric[32] = 324 { 325 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 326 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 327 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 328 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 329 }; 330 331 static const char * const mips_hwr_names_mips3264r2[32] = 332 { 333 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres", 334 "$4", "$5", "$6", "$7", 335 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 336 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 337 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 338 }; 339 340 struct mips_abi_choice 341 { 342 const char * name; 343 const char * const *gpr_names; 344 const char * const *fpr_names; 345 }; 346 347 struct mips_abi_choice mips_abi_choices[] = 348 { 349 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric }, 350 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 }, 351 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 }, 352 { "64", mips_gpr_names_newabi, mips_fpr_names_64 }, 353 }; 354 355 struct mips_arch_choice 356 { 357 const char *name; 358 int bfd_mach_valid; 359 unsigned long bfd_mach; 360 int processor; 361 int isa; 362 const char * const *cp0_names; 363 const struct mips_cp0sel_name *cp0sel_names; 364 unsigned int cp0sel_names_len; 365 const char * const *hwr_names; 366 }; 367 368 const struct mips_arch_choice mips_arch_choices[] = 369 { 370 { "numeric", 0, 0, 0, 0, 371 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 372 373 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, 374 mips_cp0_names_r3000, NULL, 0, mips_hwr_names_numeric }, 375 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, 376 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 377 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, 378 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric }, 379 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, 380 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 381 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, 382 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 383 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, 384 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 385 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, 386 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 387 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, 388 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 389 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, 390 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric }, 391 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, 392 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 393 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, 394 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 395 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, 396 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 397 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, 398 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 399 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, 400 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 401 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, 402 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 403 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 404 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 405 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 406 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 407 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, 408 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 409 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, 410 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 411 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, 412 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 413 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, 414 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 415 416 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs. 417 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See 418 _MIPS32 Architecture For Programmers Volume I: Introduction to the 419 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95), 420 page 1. */ 421 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32, 422 ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS, 423 mips_cp0_names_mips3264, 424 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), 425 mips_hwr_names_numeric }, 426 427 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2, 428 (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2 429 | INSN_MIPS3D | INSN_MT), 430 mips_cp0_names_mips3264r2, 431 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 432 mips_hwr_names_mips3264r2 }, 433 434 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */ 435 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64, 436 ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX, 437 mips_cp0_names_mips3264, 438 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), 439 mips_hwr_names_numeric }, 440 441 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2, 442 (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2 443 | INSN_DSP64 | INSN_MT | INSN_MDMX), 444 mips_cp0_names_mips3264r2, 445 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 446 mips_hwr_names_mips3264r2 }, 447 448 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1, 449 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1, 450 mips_cp0_names_sb1, 451 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1), 452 mips_hwr_names_numeric }, 453 454 { "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E, 455 ISA_MIPS3 | INSN_LOONGSON_2E, mips_cp0_names_numeric, 456 NULL, 0, mips_hwr_names_numeric }, 457 458 { "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F, 459 ISA_MIPS3 | INSN_LOONGSON_2F, mips_cp0_names_numeric, 460 NULL, 0, mips_hwr_names_numeric }, 461 462 { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON, 463 ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_numeric, NULL, 0, 464 mips_hwr_names_numeric }, 465 466 /* This entry, mips16, is here only for ISA/processor selection; do 467 not print its name. */ 468 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16, 469 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 470 }; 471 472 /* ISA and processor type to disassemble for, and register names to use. 473 set_default_mips_dis_options and parse_mips_dis_options fill in these 474 values. */ 475 static int mips_processor; 476 static int mips_isa; 477 static const char * const *mips_gpr_names; 478 static const char * const *mips_fpr_names; 479 static const char * const *mips_cp0_names; 480 static const struct mips_cp0sel_name *mips_cp0sel_names; 481 static int mips_cp0sel_names_len; 482 static const char * const *mips_hwr_names; 483 484 /* Other options */ 485 static int no_aliases; /* If set disassemble as most general inst. */ 486 487 static const struct mips_abi_choice * 489 choose_abi_by_name (const char *name, unsigned int namelen) 490 { 491 const struct mips_abi_choice *c; 492 unsigned int i; 493 494 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++) 495 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0 496 && strlen (mips_abi_choices[i].name) == namelen) 497 c = &mips_abi_choices[i]; 498 499 return c; 500 } 501 502 static const struct mips_arch_choice * 503 choose_arch_by_name (const char *name, unsigned int namelen) 504 { 505 const struct mips_arch_choice *c = NULL; 506 unsigned int i; 507 508 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) 509 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0 510 && strlen (mips_arch_choices[i].name) == namelen) 511 c = &mips_arch_choices[i]; 512 513 return c; 514 } 515 516 static const struct mips_arch_choice * 517 choose_arch_by_number (unsigned long mach) 518 { 519 static unsigned long hint_bfd_mach; 520 static const struct mips_arch_choice *hint_arch_choice; 521 const struct mips_arch_choice *c; 522 unsigned int i; 523 524 /* We optimize this because even if the user specifies no 525 flags, this will be done for every instruction! */ 526 if (hint_bfd_mach == mach 527 && hint_arch_choice != NULL 528 && hint_arch_choice->bfd_mach == hint_bfd_mach) 529 return hint_arch_choice; 530 531 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) 532 { 533 if (mips_arch_choices[i].bfd_mach_valid 534 && mips_arch_choices[i].bfd_mach == mach) 535 { 536 c = &mips_arch_choices[i]; 537 hint_bfd_mach = mach; 538 hint_arch_choice = c; 539 } 540 } 541 return c; 542 } 543 544 /* Check if the object uses NewABI conventions. */ 545 546 static int 547 is_newabi (Elf_Internal_Ehdr *header) 548 { 549 /* There are no old-style ABIs which use 64-bit ELF. */ 550 if (header->e_ident[EI_CLASS] == ELFCLASS64) 551 return 1; 552 553 /* If a 32-bit ELF file, n32 is a new-style ABI. */ 554 if ((header->e_flags & EF_MIPS_ABI2) != 0) 555 return 1; 556 557 return 0; 558 } 559 560 static void 561 set_default_mips_dis_options (struct disassemble_info *info) 562 { 563 const struct mips_arch_choice *chosen_arch; 564 565 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names, 566 and numeric FPR, CP0 register, and HWR names. */ 567 mips_isa = ISA_MIPS3; 568 mips_processor = CPU_R3000; 569 mips_gpr_names = mips_gpr_names_oldabi; 570 mips_fpr_names = mips_fpr_names_numeric; 571 mips_cp0_names = mips_cp0_names_numeric; 572 mips_cp0sel_names = NULL; 573 mips_cp0sel_names_len = 0; 574 mips_hwr_names = mips_hwr_names_numeric; 575 no_aliases = 0; 576 577 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */ 578 if (info->flavour == bfd_target_elf_flavour && info->section != NULL) 579 { 580 Elf_Internal_Ehdr *header; 581 582 header = elf_elfheader (info->section->owner); 583 if (is_newabi (header)) 584 mips_gpr_names = mips_gpr_names_newabi; 585 } 586 587 /* Set ISA, architecture, and cp0 register names as best we can. */ 588 #if ! SYMTAB_AVAILABLE 589 /* This is running out on a target machine, not in a host tool. 590 FIXME: Where does mips_target_info come from? */ 591 target_processor = mips_target_info.processor; 592 mips_isa = mips_target_info.isa; 593 #else 594 chosen_arch = choose_arch_by_number (info->mach); 595 if (chosen_arch != NULL) 596 { 597 mips_processor = chosen_arch->processor; 598 mips_isa = chosen_arch->isa; 599 mips_cp0_names = chosen_arch->cp0_names; 600 mips_cp0sel_names = chosen_arch->cp0sel_names; 601 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 602 mips_hwr_names = chosen_arch->hwr_names; 603 } 604 #endif 605 } 606 607 static void 608 parse_mips_dis_option (const char *option, unsigned int len) 609 { 610 unsigned int i, optionlen, vallen; 611 const char *val; 612 const struct mips_abi_choice *chosen_abi; 613 const struct mips_arch_choice *chosen_arch; 614 615 /* Try to match options that are simple flags */ 616 if (CONST_STRNEQ (option, "no-aliases")) 617 { 618 no_aliases = 1; 619 return; 620 } 621 622 /* Look for the = that delimits the end of the option name. */ 623 for (i = 0; i < len; i++) 624 if (option[i] == '=') 625 break; 626 627 if (i == 0) /* Invalid option: no name before '='. */ 628 return; 629 if (i == len) /* Invalid option: no '='. */ 630 return; 631 if (i == (len - 1)) /* Invalid option: no value after '='. */ 632 return; 633 634 optionlen = i; 635 val = option + (optionlen + 1); 636 vallen = len - (optionlen + 1); 637 638 if (strncmp ("gpr-names", option, optionlen) == 0 639 && strlen ("gpr-names") == optionlen) 640 { 641 chosen_abi = choose_abi_by_name (val, vallen); 642 if (chosen_abi != NULL) 643 mips_gpr_names = chosen_abi->gpr_names; 644 return; 645 } 646 647 if (strncmp ("fpr-names", option, optionlen) == 0 648 && strlen ("fpr-names") == optionlen) 649 { 650 chosen_abi = choose_abi_by_name (val, vallen); 651 if (chosen_abi != NULL) 652 mips_fpr_names = chosen_abi->fpr_names; 653 return; 654 } 655 656 if (strncmp ("cp0-names", option, optionlen) == 0 657 && strlen ("cp0-names") == optionlen) 658 { 659 chosen_arch = choose_arch_by_name (val, vallen); 660 if (chosen_arch != NULL) 661 { 662 mips_cp0_names = chosen_arch->cp0_names; 663 mips_cp0sel_names = chosen_arch->cp0sel_names; 664 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 665 } 666 return; 667 } 668 669 if (strncmp ("hwr-names", option, optionlen) == 0 670 && strlen ("hwr-names") == optionlen) 671 { 672 chosen_arch = choose_arch_by_name (val, vallen); 673 if (chosen_arch != NULL) 674 mips_hwr_names = chosen_arch->hwr_names; 675 return; 676 } 677 678 if (strncmp ("reg-names", option, optionlen) == 0 679 && strlen ("reg-names") == optionlen) 680 { 681 /* We check both ABI and ARCH here unconditionally, so 682 that "numeric" will do the desirable thing: select 683 numeric register names for all registers. Other than 684 that, a given name probably won't match both. */ 685 chosen_abi = choose_abi_by_name (val, vallen); 686 if (chosen_abi != NULL) 687 { 688 mips_gpr_names = chosen_abi->gpr_names; 689 mips_fpr_names = chosen_abi->fpr_names; 690 } 691 chosen_arch = choose_arch_by_name (val, vallen); 692 if (chosen_arch != NULL) 693 { 694 mips_cp0_names = chosen_arch->cp0_names; 695 mips_cp0sel_names = chosen_arch->cp0sel_names; 696 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 697 mips_hwr_names = chosen_arch->hwr_names; 698 } 699 return; 700 } 701 702 /* Invalid option. */ 703 } 704 705 static void 706 parse_mips_dis_options (const char *options) 707 { 708 const char *option_end; 709 710 if (options == NULL) 711 return; 712 713 while (*options != '\0') 714 { 715 /* Skip empty options. */ 716 if (*options == ',') 717 { 718 options++; 719 continue; 720 } 721 722 /* We know that *options is neither NUL or a comma. */ 723 option_end = options + 1; 724 while (*option_end != ',' && *option_end != '\0') 725 option_end++; 726 727 parse_mips_dis_option (options, option_end - options); 728 729 /* Go on to the next one. If option_end points to a comma, it 730 will be skipped above. */ 731 options = option_end; 732 } 733 } 734 735 static const struct mips_cp0sel_name * 736 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names, 737 unsigned int len, 738 unsigned int cp0reg, 739 unsigned int sel) 740 { 741 unsigned int i; 742 743 for (i = 0; i < len; i++) 744 if (names[i].cp0reg == cp0reg && names[i].sel == sel) 745 return &names[i]; 746 return NULL; 747 } 748 749 /* Print insn arguments for 32/64-bit code. */ 751 752 static void 753 print_insn_args (const char *d, 754 register unsigned long int l, 755 bfd_vma pc, 756 struct disassemble_info *info, 757 const struct mips_opcode *opp) 758 { 759 int op, delta; 760 unsigned int lsb, msb, msbd; 761 762 lsb = 0; 763 764 for (; *d != '\0'; d++) 765 { 766 switch (*d) 767 { 768 case ',': 769 case '(': 770 case ')': 771 case '[': 772 case ']': 773 (*info->fprintf_func) (info->stream, "%c", *d); 774 break; 775 776 case '+': 777 /* Extension character; switch for second char. */ 778 d++; 779 switch (*d) 780 { 781 case '\0': 782 /* xgettext:c-format */ 783 (*info->fprintf_func) (info->stream, 784 _("# internal error, incomplete extension sequence (+)")); 785 return; 786 787 case 'A': 788 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT; 789 (*info->fprintf_func) (info->stream, "0x%x", lsb); 790 break; 791 792 case 'B': 793 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB; 794 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); 795 break; 796 797 case '1': 798 (*info->fprintf_func) (info->stream, "0x%lx", 799 (l >> OP_SH_UDI1) & OP_MASK_UDI1); 800 break; 801 802 case '2': 803 (*info->fprintf_func) (info->stream, "0x%lx", 804 (l >> OP_SH_UDI2) & OP_MASK_UDI2); 805 break; 806 807 case '3': 808 (*info->fprintf_func) (info->stream, "0x%lx", 809 (l >> OP_SH_UDI3) & OP_MASK_UDI3); 810 break; 811 812 case '4': 813 (*info->fprintf_func) (info->stream, "0x%lx", 814 (l >> OP_SH_UDI4) & OP_MASK_UDI4); 815 break; 816 817 case 'C': 818 case 'H': 819 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD; 820 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1); 821 break; 822 823 case 'D': 824 { 825 const struct mips_cp0sel_name *n; 826 unsigned int cp0reg, sel; 827 828 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD; 829 sel = (l >> OP_SH_SEL) & OP_MASK_SEL; 830 831 /* CP0 register including 'sel' code for mtcN (et al.), to be 832 printed textually if known. If not known, print both 833 CP0 register name and sel numerically since CP0 register 834 with sel 0 may have a name unrelated to register being 835 printed. */ 836 n = lookup_mips_cp0sel_name(mips_cp0sel_names, 837 mips_cp0sel_names_len, cp0reg, sel); 838 if (n != NULL) 839 (*info->fprintf_func) (info->stream, "%s", n->name); 840 else 841 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel); 842 break; 843 } 844 845 case 'E': 846 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32; 847 (*info->fprintf_func) (info->stream, "0x%x", lsb); 848 break; 849 850 case 'F': 851 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32; 852 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); 853 break; 854 855 case 'G': 856 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32; 857 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1); 858 break; 859 860 case 't': /* Coprocessor 0 reg name */ 861 (*info->fprintf_func) (info->stream, "%s", 862 mips_cp0_names[(l >> OP_SH_RT) & 863 OP_MASK_RT]); 864 break; 865 866 case 'T': /* Coprocessor 0 reg name */ 867 { 868 const struct mips_cp0sel_name *n; 869 unsigned int cp0reg, sel; 870 871 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; 872 sel = (l >> OP_SH_SEL) & OP_MASK_SEL; 873 874 /* CP0 register including 'sel' code for mftc0, to be 875 printed textually if known. If not known, print both 876 CP0 register name and sel numerically since CP0 register 877 with sel 0 may have a name unrelated to register being 878 printed. */ 879 n = lookup_mips_cp0sel_name(mips_cp0sel_names, 880 mips_cp0sel_names_len, cp0reg, sel); 881 if (n != NULL) 882 (*info->fprintf_func) (info->stream, "%s", n->name); 883 else 884 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel); 885 break; 886 } 887 888 case 'x': /* bbit bit index */ 889 (*info->fprintf_func) (info->stream, "0x%lx", 890 (l >> OP_SH_BBITIND) & OP_MASK_BBITIND); 891 break; 892 893 case 'p': /* cins, cins32, exts and exts32 position */ 894 (*info->fprintf_func) (info->stream, "0x%lx", 895 (l >> OP_SH_CINSPOS) & OP_MASK_CINSPOS); 896 break; 897 898 case 's': /* cins and exts length-minus-one */ 899 (*info->fprintf_func) (info->stream, "0x%lx", 900 (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1); 901 break; 902 903 case 'S': /* cins32 and exts32 length-minus-one field */ 904 (*info->fprintf_func) (info->stream, "0x%lx", 905 (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1); 906 break; 907 908 case 'Q': /* seqi/snei immediate field */ 909 op = (l >> OP_SH_SEQI) & OP_MASK_SEQI; 910 /* Sign-extend it. */ 911 op = (op ^ 512) - 512; 912 (*info->fprintf_func) (info->stream, "%d", op); 913 break; 914 915 default: 916 /* xgettext:c-format */ 917 (*info->fprintf_func) (info->stream, 918 _("# internal error, undefined extension sequence (+%c)"), 919 *d); 920 return; 921 } 922 break; 923 924 case '2': 925 (*info->fprintf_func) (info->stream, "0x%lx", 926 (l >> OP_SH_BP) & OP_MASK_BP); 927 break; 928 929 case '3': 930 (*info->fprintf_func) (info->stream, "0x%lx", 931 (l >> OP_SH_SA3) & OP_MASK_SA3); 932 break; 933 934 case '4': 935 (*info->fprintf_func) (info->stream, "0x%lx", 936 (l >> OP_SH_SA4) & OP_MASK_SA4); 937 break; 938 939 case '5': 940 (*info->fprintf_func) (info->stream, "0x%lx", 941 (l >> OP_SH_IMM8) & OP_MASK_IMM8); 942 break; 943 944 case '6': 945 (*info->fprintf_func) (info->stream, "0x%lx", 946 (l >> OP_SH_RS) & OP_MASK_RS); 947 break; 948 949 case '7': 950 (*info->fprintf_func) (info->stream, "$ac%ld", 951 (l >> OP_SH_DSPACC) & OP_MASK_DSPACC); 952 break; 953 954 case '8': 955 (*info->fprintf_func) (info->stream, "0x%lx", 956 (l >> OP_SH_WRDSP) & OP_MASK_WRDSP); 957 break; 958 959 case '9': 960 (*info->fprintf_func) (info->stream, "$ac%ld", 961 (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S); 962 break; 963 964 case '0': /* dsp 6-bit signed immediate in bit 20 */ 965 delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT); 966 if (delta & 0x20) /* test sign bit */ 967 delta |= ~OP_MASK_DSPSFT; 968 (*info->fprintf_func) (info->stream, "%d", delta); 969 break; 970 971 case ':': /* dsp 7-bit signed immediate in bit 19 */ 972 delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7); 973 if (delta & 0x40) /* test sign bit */ 974 delta |= ~OP_MASK_DSPSFT_7; 975 (*info->fprintf_func) (info->stream, "%d", delta); 976 break; 977 978 case '\'': 979 (*info->fprintf_func) (info->stream, "0x%lx", 980 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP); 981 break; 982 983 case '@': /* dsp 10-bit signed immediate in bit 16 */ 984 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10); 985 if (delta & 0x200) /* test sign bit */ 986 delta |= ~OP_MASK_IMM10; 987 (*info->fprintf_func) (info->stream, "%d", delta); 988 break; 989 990 case '!': 991 (*info->fprintf_func) (info->stream, "%ld", 992 (l >> OP_SH_MT_U) & OP_MASK_MT_U); 993 break; 994 995 case '$': 996 (*info->fprintf_func) (info->stream, "%ld", 997 (l >> OP_SH_MT_H) & OP_MASK_MT_H); 998 break; 999 1000 case '*': 1001 (*info->fprintf_func) (info->stream, "$ac%ld", 1002 (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T); 1003 break; 1004 1005 case '&': 1006 (*info->fprintf_func) (info->stream, "$ac%ld", 1007 (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D); 1008 break; 1009 1010 case 'g': 1011 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */ 1012 (*info->fprintf_func) (info->stream, "$%ld", 1013 (l >> OP_SH_RD) & OP_MASK_RD); 1014 break; 1015 1016 case 's': 1017 case 'b': 1018 case 'r': 1019 case 'v': 1020 (*info->fprintf_func) (info->stream, "%s", 1021 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]); 1022 break; 1023 1024 case 't': 1025 case 'w': 1026 (*info->fprintf_func) (info->stream, "%s", 1027 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); 1028 break; 1029 1030 case 'i': 1031 case 'u': 1032 (*info->fprintf_func) (info->stream, "0x%lx", 1033 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE); 1034 break; 1035 1036 case 'j': /* Same as i, but sign-extended. */ 1037 case 'o': 1038 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; 1039 if (delta & 0x8000) 1040 delta |= ~0xffff; 1041 (*info->fprintf_func) (info->stream, "%d", 1042 delta); 1043 break; 1044 1045 case 'h': 1046 (*info->fprintf_func) (info->stream, "0x%x", 1047 (unsigned int) ((l >> OP_SH_PREFX) 1048 & OP_MASK_PREFX)); 1049 break; 1050 1051 case 'k': 1052 (*info->fprintf_func) (info->stream, "0x%x", 1053 (unsigned int) ((l >> OP_SH_CACHE) 1054 & OP_MASK_CACHE)); 1055 break; 1056 1057 case 'a': 1058 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff) 1059 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2)); 1060 /* For gdb disassembler, force odd address on jalx. */ 1061 if (info->flavour == bfd_target_unknown_flavour 1062 && strcmp (opp->name, "jalx") == 0) 1063 info->target |= 1; 1064 (*info->print_address_func) (info->target, info); 1065 break; 1066 1067 case 'p': 1068 /* Sign extend the displacement. */ 1069 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; 1070 if (delta & 0x8000) 1071 delta |= ~0xffff; 1072 info->target = (delta << 2) + pc + INSNLEN; 1073 (*info->print_address_func) (info->target, info); 1074 break; 1075 1076 case 'd': 1077 (*info->fprintf_func) (info->stream, "%s", 1078 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]); 1079 break; 1080 1081 case 'U': 1082 { 1083 /* First check for both rd and rt being equal. */ 1084 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD; 1085 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) 1086 (*info->fprintf_func) (info->stream, "%s", 1087 mips_gpr_names[reg]); 1088 else 1089 { 1090 /* If one is zero use the other. */ 1091 if (reg == 0) 1092 (*info->fprintf_func) (info->stream, "%s", 1093 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); 1094 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) 1095 (*info->fprintf_func) (info->stream, "%s", 1096 mips_gpr_names[reg]); 1097 else /* Bogus, result depends on processor. */ 1098 (*info->fprintf_func) (info->stream, "%s or %s", 1099 mips_gpr_names[reg], 1100 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); 1101 } 1102 } 1103 break; 1104 1105 case 'z': 1106 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); 1107 break; 1108 1109 case '<': 1110 (*info->fprintf_func) (info->stream, "0x%lx", 1111 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT); 1112 break; 1113 1114 case 'c': 1115 (*info->fprintf_func) (info->stream, "0x%lx", 1116 (l >> OP_SH_CODE) & OP_MASK_CODE); 1117 break; 1118 1119 case 'q': 1120 (*info->fprintf_func) (info->stream, "0x%lx", 1121 (l >> OP_SH_CODE2) & OP_MASK_CODE2); 1122 break; 1123 1124 case 'C': 1125 (*info->fprintf_func) (info->stream, "0x%lx", 1126 (l >> OP_SH_COPZ) & OP_MASK_COPZ); 1127 break; 1128 1129 case 'B': 1130 (*info->fprintf_func) (info->stream, "0x%lx", 1131 1132 (l >> OP_SH_CODE20) & OP_MASK_CODE20); 1133 break; 1134 1135 case 'J': 1136 (*info->fprintf_func) (info->stream, "0x%lx", 1137 (l >> OP_SH_CODE19) & OP_MASK_CODE19); 1138 break; 1139 1140 case 'S': 1141 case 'V': 1142 (*info->fprintf_func) (info->stream, "%s", 1143 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]); 1144 break; 1145 1146 case 'T': 1147 case 'W': 1148 (*info->fprintf_func) (info->stream, "%s", 1149 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]); 1150 break; 1151 1152 case 'D': 1153 (*info->fprintf_func) (info->stream, "%s", 1154 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]); 1155 break; 1156 1157 case 'R': 1158 (*info->fprintf_func) (info->stream, "%s", 1159 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]); 1160 break; 1161 1162 case 'E': 1163 /* Coprocessor register for lwcN instructions, et al. 1164 1165 Note that there is no load/store cp0 instructions, and 1166 that FPU (cp1) instructions disassemble this field using 1167 'T' format. Therefore, until we gain understanding of 1168 cp2 register names, we can simply print the register 1169 numbers. */ 1170 (*info->fprintf_func) (info->stream, "$%ld", 1171 (l >> OP_SH_RT) & OP_MASK_RT); 1172 break; 1173 1174 case 'G': 1175 /* Coprocessor register for mtcN instructions, et al. Note 1176 that FPU (cp1) instructions disassemble this field using 1177 'S' format. Therefore, we only need to worry about cp0, 1178 cp2, and cp3. */ 1179 op = (l >> OP_SH_OP) & OP_MASK_OP; 1180 if (op == OP_OP_COP0) 1181 (*info->fprintf_func) (info->stream, "%s", 1182 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]); 1183 else 1184 (*info->fprintf_func) (info->stream, "$%ld", 1185 (l >> OP_SH_RD) & OP_MASK_RD); 1186 break; 1187 1188 case 'K': 1189 (*info->fprintf_func) (info->stream, "%s", 1190 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]); 1191 break; 1192 1193 case 'N': 1194 (*info->fprintf_func) (info->stream, 1195 ((opp->pinfo & (FP_D | FP_S)) != 0 1196 ? "$fcc%ld" : "$cc%ld"), 1197 (l >> OP_SH_BCC) & OP_MASK_BCC); 1198 break; 1199 1200 case 'M': 1201 (*info->fprintf_func) (info->stream, "$fcc%ld", 1202 (l >> OP_SH_CCC) & OP_MASK_CCC); 1203 break; 1204 1205 case 'P': 1206 (*info->fprintf_func) (info->stream, "%ld", 1207 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG); 1208 break; 1209 1210 case 'e': 1211 (*info->fprintf_func) (info->stream, "%ld", 1212 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE); 1213 break; 1214 1215 case '%': 1216 (*info->fprintf_func) (info->stream, "%ld", 1217 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN); 1218 break; 1219 1220 case 'H': 1221 (*info->fprintf_func) (info->stream, "%ld", 1222 (l >> OP_SH_SEL) & OP_MASK_SEL); 1223 break; 1224 1225 case 'O': 1226 (*info->fprintf_func) (info->stream, "%ld", 1227 (l >> OP_SH_ALN) & OP_MASK_ALN); 1228 break; 1229 1230 case 'Q': 1231 { 1232 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL; 1233 1234 if ((vsel & 0x10) == 0) 1235 { 1236 int fmt; 1237 1238 vsel &= 0x0f; 1239 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1) 1240 if ((vsel & 1) == 0) 1241 break; 1242 (*info->fprintf_func) (info->stream, "$v%ld[%d]", 1243 (l >> OP_SH_FT) & OP_MASK_FT, 1244 vsel >> 1); 1245 } 1246 else if ((vsel & 0x08) == 0) 1247 { 1248 (*info->fprintf_func) (info->stream, "$v%ld", 1249 (l >> OP_SH_FT) & OP_MASK_FT); 1250 } 1251 else 1252 { 1253 (*info->fprintf_func) (info->stream, "0x%lx", 1254 (l >> OP_SH_FT) & OP_MASK_FT); 1255 } 1256 } 1257 break; 1258 1259 case 'X': 1260 (*info->fprintf_func) (info->stream, "$v%ld", 1261 (l >> OP_SH_FD) & OP_MASK_FD); 1262 break; 1263 1264 case 'Y': 1265 (*info->fprintf_func) (info->stream, "$v%ld", 1266 (l >> OP_SH_FS) & OP_MASK_FS); 1267 break; 1268 1269 case 'Z': 1270 (*info->fprintf_func) (info->stream, "$v%ld", 1271 (l >> OP_SH_FT) & OP_MASK_FT); 1272 break; 1273 1274 default: 1275 /* xgettext:c-format */ 1276 (*info->fprintf_func) (info->stream, 1277 _("# internal error, undefined modifier (%c)"), 1278 *d); 1279 return; 1280 } 1281 } 1282 } 1283 1284 /* Print the mips instruction at address MEMADDR in debugged memory, 1286 on using INFO. Returns length of the instruction, in bytes, which is 1287 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if 1288 this is little-endian code. */ 1289 1290 static int 1291 print_insn_mips (bfd_vma memaddr, 1292 unsigned long int word, 1293 struct disassemble_info *info) 1294 { 1295 const struct mips_opcode *op; 1296 static bfd_boolean init = 0; 1297 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1]; 1298 1299 /* Build a hash table to shorten the search time. */ 1300 if (! init) 1301 { 1302 unsigned int i; 1303 1304 for (i = 0; i <= OP_MASK_OP; i++) 1305 { 1306 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++) 1307 { 1308 if (op->pinfo == INSN_MACRO 1309 || (no_aliases && (op->pinfo2 & INSN2_ALIAS))) 1310 continue; 1311 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP)) 1312 { 1313 mips_hash[i] = op; 1314 break; 1315 } 1316 } 1317 } 1318 1319 init = 1; 1320 } 1321 1322 info->bytes_per_chunk = INSNLEN; 1323 info->display_endian = info->endian; 1324 info->insn_info_valid = 1; 1325 info->branch_delay_insns = 0; 1326 info->data_size = 0; 1327 info->insn_type = dis_nonbranch; 1328 info->target = 0; 1329 info->target2 = 0; 1330 1331 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP]; 1332 if (op != NULL) 1333 { 1334 for (; op < &mips_opcodes[NUMOPCODES]; op++) 1335 { 1336 if (op->pinfo != INSN_MACRO 1337 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) 1338 && (word & op->mask) == op->match) 1339 { 1340 const char *d; 1341 1342 /* We always allow to disassemble the jalx instruction. */ 1343 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor) 1344 && strcmp (op->name, "jalx")) 1345 continue; 1346 1347 /* Figure out instruction type and branch delay information. */ 1348 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) 1349 { 1350 if ((info->insn_type & INSN_WRITE_GPR_31) != 0) 1351 info->insn_type = dis_jsr; 1352 else 1353 info->insn_type = dis_branch; 1354 info->branch_delay_insns = 1; 1355 } 1356 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY 1357 | INSN_COND_BRANCH_LIKELY)) != 0) 1358 { 1359 if ((info->insn_type & INSN_WRITE_GPR_31) != 0) 1360 info->insn_type = dis_condjsr; 1361 else 1362 info->insn_type = dis_condbranch; 1363 info->branch_delay_insns = 1; 1364 } 1365 else if ((op->pinfo & (INSN_STORE_MEMORY 1366 | INSN_LOAD_MEMORY_DELAY)) != 0) 1367 info->insn_type = dis_dref; 1368 1369 (*info->fprintf_func) (info->stream, "%s", op->name); 1370 1371 d = op->args; 1372 if (d != NULL && *d != '\0') 1373 { 1374 (*info->fprintf_func) (info->stream, "\t"); 1375 print_insn_args (d, word, memaddr, info, op); 1376 } 1377 1378 return INSNLEN; 1379 } 1380 } 1381 } 1382 1383 /* Handle undefined instructions. */ 1384 info->insn_type = dis_noninsn; 1385 (*info->fprintf_func) (info->stream, "0x%lx", word); 1386 return INSNLEN; 1387 } 1388 1389 /* Disassemble an operand for a mips16 instruction. */ 1391 1392 static void 1393 print_mips16_insn_arg (char type, 1394 const struct mips_opcode *op, 1395 int l, 1396 bfd_boolean use_extend, 1397 int extend, 1398 bfd_vma memaddr, 1399 struct disassemble_info *info) 1400 { 1401 switch (type) 1402 { 1403 case ',': 1404 case '(': 1405 case ')': 1406 (*info->fprintf_func) (info->stream, "%c", type); 1407 break; 1408 1409 case 'y': 1410 case 'w': 1411 (*info->fprintf_func) (info->stream, "%s", 1412 mips16_reg_names(((l >> MIPS16OP_SH_RY) 1413 & MIPS16OP_MASK_RY))); 1414 break; 1415 1416 case 'x': 1417 case 'v': 1418 (*info->fprintf_func) (info->stream, "%s", 1419 mips16_reg_names(((l >> MIPS16OP_SH_RX) 1420 & MIPS16OP_MASK_RX))); 1421 break; 1422 1423 case 'z': 1424 (*info->fprintf_func) (info->stream, "%s", 1425 mips16_reg_names(((l >> MIPS16OP_SH_RZ) 1426 & MIPS16OP_MASK_RZ))); 1427 break; 1428 1429 case 'Z': 1430 (*info->fprintf_func) (info->stream, "%s", 1431 mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z) 1432 & MIPS16OP_MASK_MOVE32Z))); 1433 break; 1434 1435 case '0': 1436 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); 1437 break; 1438 1439 case 'S': 1440 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]); 1441 break; 1442 1443 case 'P': 1444 (*info->fprintf_func) (info->stream, "$pc"); 1445 break; 1446 1447 case 'R': 1448 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]); 1449 break; 1450 1451 case 'X': 1452 (*info->fprintf_func) (info->stream, "%s", 1453 mips_gpr_names[((l >> MIPS16OP_SH_REGR32) 1454 & MIPS16OP_MASK_REGR32)]); 1455 break; 1456 1457 case 'Y': 1458 (*info->fprintf_func) (info->stream, "%s", 1459 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]); 1460 break; 1461 1462 case '<': 1463 case '>': 1464 case '[': 1465 case ']': 1466 case '4': 1467 case '5': 1468 case 'H': 1469 case 'W': 1470 case 'D': 1471 case 'j': 1472 case '6': 1473 case '8': 1474 case 'V': 1475 case 'C': 1476 case 'U': 1477 case 'k': 1478 case 'K': 1479 case 'p': 1480 case 'q': 1481 case 'A': 1482 case 'B': 1483 case 'E': 1484 { 1485 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch; 1486 1487 shift = 0; 1488 signedp = 0; 1489 extbits = 16; 1490 pcrel = 0; 1491 extu = 0; 1492 branch = 0; 1493 switch (type) 1494 { 1495 case '<': 1496 nbits = 3; 1497 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; 1498 extbits = 5; 1499 extu = 1; 1500 break; 1501 case '>': 1502 nbits = 3; 1503 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; 1504 extbits = 5; 1505 extu = 1; 1506 break; 1507 case '[': 1508 nbits = 3; 1509 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; 1510 extbits = 6; 1511 extu = 1; 1512 break; 1513 case ']': 1514 nbits = 3; 1515 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; 1516 extbits = 6; 1517 extu = 1; 1518 break; 1519 case '4': 1520 nbits = 4; 1521 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4; 1522 signedp = 1; 1523 extbits = 15; 1524 break; 1525 case '5': 1526 nbits = 5; 1527 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 1528 info->insn_type = dis_dref; 1529 info->data_size = 1; 1530 break; 1531 case 'H': 1532 nbits = 5; 1533 shift = 1; 1534 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 1535 info->insn_type = dis_dref; 1536 info->data_size = 2; 1537 break; 1538 case 'W': 1539 nbits = 5; 1540 shift = 2; 1541 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 1542 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0 1543 && (op->pinfo & MIPS16_INSN_READ_SP) == 0) 1544 { 1545 info->insn_type = dis_dref; 1546 info->data_size = 4; 1547 } 1548 break; 1549 case 'D': 1550 nbits = 5; 1551 shift = 3; 1552 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 1553 info->insn_type = dis_dref; 1554 info->data_size = 8; 1555 break; 1556 case 'j': 1557 nbits = 5; 1558 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 1559 signedp = 1; 1560 break; 1561 case '6': 1562 nbits = 6; 1563 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; 1564 break; 1565 case '8': 1566 nbits = 8; 1567 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 1568 break; 1569 case 'V': 1570 nbits = 8; 1571 shift = 2; 1572 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 1573 /* FIXME: This might be lw, or it might be addiu to $sp or 1574 $pc. We assume it's load. */ 1575 info->insn_type = dis_dref; 1576 info->data_size = 4; 1577 break; 1578 case 'C': 1579 nbits = 8; 1580 shift = 3; 1581 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 1582 info->insn_type = dis_dref; 1583 info->data_size = 8; 1584 break; 1585 case 'U': 1586 nbits = 8; 1587 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 1588 extu = 1; 1589 break; 1590 case 'k': 1591 nbits = 8; 1592 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 1593 signedp = 1; 1594 break; 1595 case 'K': 1596 nbits = 8; 1597 shift = 3; 1598 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 1599 signedp = 1; 1600 break; 1601 case 'p': 1602 nbits = 8; 1603 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 1604 signedp = 1; 1605 pcrel = 1; 1606 branch = 1; 1607 info->insn_type = dis_condbranch; 1608 break; 1609 case 'q': 1610 nbits = 11; 1611 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11; 1612 signedp = 1; 1613 pcrel = 1; 1614 branch = 1; 1615 info->insn_type = dis_branch; 1616 break; 1617 case 'A': 1618 nbits = 8; 1619 shift = 2; 1620 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 1621 pcrel = 1; 1622 /* FIXME: This can be lw or la. We assume it is lw. */ 1623 info->insn_type = dis_dref; 1624 info->data_size = 4; 1625 break; 1626 case 'B': 1627 nbits = 5; 1628 shift = 3; 1629 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 1630 pcrel = 1; 1631 info->insn_type = dis_dref; 1632 info->data_size = 8; 1633 break; 1634 case 'E': 1635 nbits = 5; 1636 shift = 2; 1637 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 1638 pcrel = 1; 1639 break; 1640 default: 1641 abort (); 1642 } 1643 1644 if (! use_extend) 1645 { 1646 if (signedp && immed >= (1 << (nbits - 1))) 1647 immed -= 1 << nbits; 1648 immed <<= shift; 1649 if ((type == '<' || type == '>' || type == '[' || type == ']') 1650 && immed == 0) 1651 immed = 8; 1652 } 1653 else 1654 { 1655 if (extbits == 16) 1656 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0); 1657 else if (extbits == 15) 1658 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0); 1659 else 1660 immed = ((extend >> 6) & 0x1f) | (extend & 0x20); 1661 immed &= (1 << extbits) - 1; 1662 if (! extu && immed >= (1 << (extbits - 1))) 1663 immed -= 1 << extbits; 1664 } 1665 1666 if (! pcrel) 1667 (*info->fprintf_func) (info->stream, "%d", immed); 1668 else 1669 { 1670 bfd_vma baseaddr; 1671 1672 if (branch) 1673 { 1674 immed *= 2; 1675 baseaddr = memaddr + 2; 1676 } 1677 else if (use_extend) 1678 baseaddr = memaddr - 2; 1679 else 1680 { 1681 int status; 1682 bfd_byte buffer[2]; 1683 1684 baseaddr = memaddr; 1685 1686 /* If this instruction is in the delay slot of a jr 1687 instruction, the base address is the address of the 1688 jr instruction. If it is in the delay slot of jalr 1689 instruction, the base address is the address of the 1690 jalr instruction. This test is unreliable: we have 1691 no way of knowing whether the previous word is 1692 instruction or data. */ 1693 status = (*info->read_memory_func) (memaddr - 4, buffer, 2, 1694 info); 1695 if (status == 0 1696 && (((info->endian == BFD_ENDIAN_BIG 1697 ? bfd_getb16 (buffer) 1698 : bfd_getl16 (buffer)) 1699 & 0xf800) == 0x1800)) 1700 baseaddr = memaddr - 4; 1701 else 1702 { 1703 status = (*info->read_memory_func) (memaddr - 2, buffer, 1704 2, info); 1705 if (status == 0 1706 && (((info->endian == BFD_ENDIAN_BIG 1707 ? bfd_getb16 (buffer) 1708 : bfd_getl16 (buffer)) 1709 & 0xf81f) == 0xe800)) 1710 baseaddr = memaddr - 2; 1711 } 1712 } 1713 info->target = (baseaddr & ~((1 << shift) - 1)) + immed; 1714 if (pcrel && branch 1715 && info->flavour == bfd_target_unknown_flavour) 1716 /* For gdb disassembler, maintain odd address. */ 1717 info->target |= 1; 1718 (*info->print_address_func) (info->target, info); 1719 } 1720 } 1721 break; 1722 1723 case 'a': 1724 { 1725 int jalx = l & 0x400; 1726 1727 if (! use_extend) 1728 extend = 0; 1729 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2); 1730 if (!jalx && info->flavour == bfd_target_unknown_flavour) 1731 /* For gdb disassembler, maintain odd address. */ 1732 l |= 1; 1733 } 1734 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l; 1735 (*info->print_address_func) (info->target, info); 1736 info->insn_type = dis_jsr; 1737 info->branch_delay_insns = 1; 1738 break; 1739 1740 case 'l': 1741 case 'L': 1742 { 1743 int need_comma, amask, smask; 1744 1745 need_comma = 0; 1746 1747 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; 1748 1749 amask = (l >> 3) & 7; 1750 1751 if (amask > 0 && amask < 5) 1752 { 1753 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]); 1754 if (amask > 1) 1755 (*info->fprintf_func) (info->stream, "-%s", 1756 mips_gpr_names[amask + 3]); 1757 need_comma = 1; 1758 } 1759 1760 smask = (l >> 1) & 3; 1761 if (smask == 3) 1762 { 1763 (*info->fprintf_func) (info->stream, "%s??", 1764 need_comma ? "," : ""); 1765 need_comma = 1; 1766 } 1767 else if (smask > 0) 1768 { 1769 (*info->fprintf_func) (info->stream, "%s%s", 1770 need_comma ? "," : "", 1771 mips_gpr_names[16]); 1772 if (smask > 1) 1773 (*info->fprintf_func) (info->stream, "-%s", 1774 mips_gpr_names[smask + 15]); 1775 need_comma = 1; 1776 } 1777 1778 if (l & 1) 1779 { 1780 (*info->fprintf_func) (info->stream, "%s%s", 1781 need_comma ? "," : "", 1782 mips_gpr_names[31]); 1783 need_comma = 1; 1784 } 1785 1786 if (amask == 5 || amask == 6) 1787 { 1788 (*info->fprintf_func) (info->stream, "%s$f0", 1789 need_comma ? "," : ""); 1790 if (amask == 6) 1791 (*info->fprintf_func) (info->stream, "-$f1"); 1792 } 1793 } 1794 break; 1795 1796 case 'm': 1797 case 'M': 1798 /* MIPS16e save/restore. */ 1799 { 1800 int need_comma = 0; 1801 int amask, args, statics; 1802 int nsreg, smask; 1803 int framesz; 1804 int i, j; 1805 1806 l = l & 0x7f; 1807 if (use_extend) 1808 l |= extend << 16; 1809 1810 amask = (l >> 16) & 0xf; 1811 if (amask == MIPS16_ALL_ARGS) 1812 { 1813 args = 4; 1814 statics = 0; 1815 } 1816 else if (amask == MIPS16_ALL_STATICS) 1817 { 1818 args = 0; 1819 statics = 4; 1820 } 1821 else 1822 { 1823 args = amask >> 2; 1824 statics = amask & 3; 1825 } 1826 1827 if (args > 0) { 1828 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]); 1829 if (args > 1) 1830 (*info->fprintf_func) (info->stream, "-%s", 1831 mips_gpr_names[4 + args - 1]); 1832 need_comma = 1; 1833 } 1834 1835 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8; 1836 if (framesz == 0 && !use_extend) 1837 framesz = 128; 1838 1839 (*info->fprintf_func) (info->stream, "%s%d", 1840 need_comma ? "," : "", 1841 framesz); 1842 1843 if (l & 0x40) /* $ra */ 1844 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]); 1845 1846 nsreg = (l >> 24) & 0x7; 1847 smask = 0; 1848 if (l & 0x20) /* $s0 */ 1849 smask |= 1 << 0; 1850 if (l & 0x10) /* $s1 */ 1851 smask |= 1 << 1; 1852 if (nsreg > 0) /* $s2-$s8 */ 1853 smask |= ((1 << nsreg) - 1) << 2; 1854 1855 /* Find first set static reg bit. */ 1856 for (i = 0; i < 9; i++) 1857 { 1858 if (smask & (1 << i)) 1859 { 1860 (*info->fprintf_func) (info->stream, ",%s", 1861 mips_gpr_names[i == 8 ? 30 : (16 + i)]); 1862 /* Skip over string of set bits. */ 1863 for (j = i; smask & (2 << j); j++) 1864 continue; 1865 if (j > i) 1866 (*info->fprintf_func) (info->stream, "-%s", 1867 mips_gpr_names[j == 8 ? 30 : (16 + j)]); 1868 i = j + 1; 1869 } 1870 } 1871 1872 /* Statics $ax - $a3. */ 1873 if (statics == 1) 1874 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]); 1875 else if (statics > 0) 1876 (*info->fprintf_func) (info->stream, ",%s-%s", 1877 mips_gpr_names[7 - statics + 1], 1878 mips_gpr_names[7]); 1879 } 1880 break; 1881 1882 default: 1883 /* xgettext:c-format */ 1884 (*info->fprintf_func) 1885 (info->stream, 1886 _("# internal disassembler error, unrecognised modifier (%c)"), 1887 type); 1888 abort (); 1889 } 1890 } 1891 1892 /* Disassemble mips16 instructions. */ 1893 1894 static int 1895 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) 1896 { 1897 int status; 1898 bfd_byte buffer[2]; 1899 int length; 1900 int insn; 1901 bfd_boolean use_extend; 1902 int extend = 0; 1903 const struct mips_opcode *op, *opend; 1904 1905 info->bytes_per_chunk = 2; 1906 info->display_endian = info->endian; 1907 info->insn_info_valid = 1; 1908 info->branch_delay_insns = 0; 1909 info->data_size = 0; 1910 info->insn_type = dis_nonbranch; 1911 info->target = 0; 1912 info->target2 = 0; 1913 1914 status = (*info->read_memory_func) (memaddr, buffer, 2, info); 1915 if (status != 0) 1916 { 1917 (*info->memory_error_func) (status, memaddr, info); 1918 return -1; 1919 } 1920 1921 length = 2; 1922 1923 if (info->endian == BFD_ENDIAN_BIG) 1924 insn = bfd_getb16 (buffer); 1925 else 1926 insn = bfd_getl16 (buffer); 1927 1928 /* Handle the extend opcode specially. */ 1929 use_extend = FALSE; 1930 if ((insn & 0xf800) == 0xf000) 1931 { 1932 use_extend = TRUE; 1933 extend = insn & 0x7ff; 1934 1935 memaddr += 2; 1936 1937 status = (*info->read_memory_func) (memaddr, buffer, 2, info); 1938 if (status != 0) 1939 { 1940 (*info->fprintf_func) (info->stream, "extend 0x%x", 1941 (unsigned int) extend); 1942 (*info->memory_error_func) (status, memaddr, info); 1943 return -1; 1944 } 1945 1946 if (info->endian == BFD_ENDIAN_BIG) 1947 insn = bfd_getb16 (buffer); 1948 else 1949 insn = bfd_getl16 (buffer); 1950 1951 /* Check for an extend opcode followed by an extend opcode. */ 1952 if ((insn & 0xf800) == 0xf000) 1953 { 1954 (*info->fprintf_func) (info->stream, "extend 0x%x", 1955 (unsigned int) extend); 1956 info->insn_type = dis_noninsn; 1957 return length; 1958 } 1959 1960 length += 2; 1961 } 1962 1963 /* FIXME: Should probably use a hash table on the major opcode here. */ 1964 1965 opend = mips16_opcodes + bfd_mips16_num_opcodes; 1966 for (op = mips16_opcodes; op < opend; op++) 1967 { 1968 if (op->pinfo != INSN_MACRO 1969 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) 1970 && (insn & op->mask) == op->match) 1971 { 1972 const char *s; 1973 1974 if (strchr (op->args, 'a') != NULL) 1975 { 1976 if (use_extend) 1977 { 1978 (*info->fprintf_func) (info->stream, "extend 0x%x", 1979 (unsigned int) extend); 1980 info->insn_type = dis_noninsn; 1981 return length - 2; 1982 } 1983 1984 use_extend = FALSE; 1985 1986 memaddr += 2; 1987 1988 status = (*info->read_memory_func) (memaddr, buffer, 2, 1989 info); 1990 if (status == 0) 1991 { 1992 use_extend = TRUE; 1993 if (info->endian == BFD_ENDIAN_BIG) 1994 extend = bfd_getb16 (buffer); 1995 else 1996 extend = bfd_getl16 (buffer); 1997 length += 2; 1998 } 1999 } 2000 2001 (*info->fprintf_func) (info->stream, "%s", op->name); 2002 if (op->args[0] != '\0') 2003 (*info->fprintf_func) (info->stream, "\t"); 2004 2005 for (s = op->args; *s != '\0'; s++) 2006 { 2007 if (*s == ',' 2008 && s[1] == 'w' 2009 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX) 2010 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY))) 2011 { 2012 /* Skip the register and the comma. */ 2013 ++s; 2014 continue; 2015 } 2016 if (*s == ',' 2017 && s[1] == 'v' 2018 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ) 2019 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX))) 2020 { 2021 /* Skip the register and the comma. */ 2022 ++s; 2023 continue; 2024 } 2025 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr, 2026 info); 2027 } 2028 2029 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) 2030 { 2031 info->branch_delay_insns = 1; 2032 if (info->insn_type != dis_jsr) 2033 info->insn_type = dis_branch; 2034 } 2035 2036 return length; 2037 } 2038 } 2039 2040 if (use_extend) 2041 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000); 2042 (*info->fprintf_func) (info->stream, "0x%x", insn); 2043 info->insn_type = dis_noninsn; 2044 2045 return length; 2046 } 2047 2048 /* In an environment where we do not know the symbol type of the 2049 instruction we are forced to assume that the low order bit of the 2050 instructions' address may mark it as a mips16 instruction. If we 2051 are single stepping, or the pc is within the disassembled function, 2052 this works. Otherwise, we need a clue. Sometimes. */ 2053 2054 static int 2055 _print_insn_mips (bfd_vma memaddr, 2056 struct disassemble_info *info, 2057 enum bfd_endian endianness) 2058 { 2059 bfd_byte buffer[INSNLEN]; 2060 int status; 2061 2062 set_default_mips_dis_options (info); 2063 parse_mips_dis_options (info->disassembler_options); 2064 2065 #if 1 2066 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */ 2067 /* Only a few tools will work this way. */ 2068 if (memaddr & 0x01) 2069 return print_insn_mips16 (memaddr, info); 2070 #endif 2071 2072 #if SYMTAB_AVAILABLE 2073 if (info->mach == bfd_mach_mips16 2074 || (info->symbols != NULL 2075 && bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour 2076 && ELF_ST_IS_MIPS16 ((*(elf_symbol_type **) info->symbols) 2077 ->internal_elf_sym.st_other))) 2078 return print_insn_mips16 (memaddr, info); 2079 #endif 2080 2081 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info); 2082 if (status == 0) 2083 { 2084 unsigned long insn; 2085 2086 if (endianness == BFD_ENDIAN_BIG) 2087 insn = (unsigned long) bfd_getb32 (buffer); 2088 else 2089 insn = (unsigned long) bfd_getl32 (buffer); 2090 2091 return print_insn_mips (memaddr, insn, info); 2092 } 2093 else 2094 { 2095 (*info->memory_error_func) (status, memaddr, info); 2096 return -1; 2097 } 2098 } 2099 2100 int 2101 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info) 2102 { 2103 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG); 2104 } 2105 2106 int 2107 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info) 2108 { 2109 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE); 2110 } 2111 2112 void 2114 print_mips_disassembler_options (FILE *stream) 2115 { 2116 unsigned int i; 2117 2118 fprintf (stream, _("\n\ 2119 The following MIPS specific disassembler options are supported for use\n\ 2120 with the -M switch (multiple options should be separated by commas):\n")); 2121 2122 fprintf (stream, _("\n\ 2123 gpr-names=ABI Print GPR names according to specified ABI.\n\ 2124 Default: based on binary being disassembled.\n")); 2125 2126 fprintf (stream, _("\n\ 2127 fpr-names=ABI Print FPR names according to specified ABI.\n\ 2128 Default: numeric.\n")); 2129 2130 fprintf (stream, _("\n\ 2131 cp0-names=ARCH Print CP0 register names according to\n\ 2132 specified architecture.\n\ 2133 Default: based on binary being disassembled.\n")); 2134 2135 fprintf (stream, _("\n\ 2136 hwr-names=ARCH Print HWR names according to specified \n\ 2137 architecture.\n\ 2138 Default: based on binary being disassembled.\n")); 2139 2140 fprintf (stream, _("\n\ 2141 reg-names=ABI Print GPR and FPR names according to\n\ 2142 specified ABI.\n")); 2143 2144 fprintf (stream, _("\n\ 2145 reg-names=ARCH Print CP0 register and HWR names according to\n\ 2146 specified architecture.\n")); 2147 2148 fprintf (stream, _("\n\ 2149 For the options above, the following values are supported for \"ABI\":\n\ 2150 ")); 2151 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++) 2152 fprintf (stream, " %s", mips_abi_choices[i].name); 2153 fprintf (stream, _("\n")); 2154 2155 fprintf (stream, _("\n\ 2156 For the options above, The following values are supported for \"ARCH\":\n\ 2157 ")); 2158 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++) 2159 if (*mips_arch_choices[i].name != '\0') 2160 fprintf (stream, " %s", mips_arch_choices[i].name); 2161 fprintf (stream, _("\n")); 2162 2163 fprintf (stream, _("\n")); 2164 } 2165
Indexes created Fri Apr 03 00:24:04 UTC 2026