mips-dis.c revision 1.3.8.1
1 /* Print mips instructions for GDB, the GNU debugger, or for objdump. 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 3 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009, 2012 4 Free Software Foundation, Inc. 5 Contributed by Nobuyuki Hikichi(hikichi (at) sra.co.jp). 6 7 This file is part of the GNU opcodes library. 8 9 This library is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 It is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program; if not, write to the Free Software 21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 22 MA 02110-1301, USA. */ 23 24 #include "sysdep.h" 25 #include "dis-asm.h" 26 #include "libiberty.h" 27 #include "opcode/mips.h" 28 #include "opintl.h" 29 30 /* FIXME: These are needed to figure out if the code is mips16 or 31 not. The low bit of the address is often a good indicator. No 32 symbol table is available when this code runs out in an embedded 33 system as when it is used for disassembler support in a monitor. */ 34 35 #if !defined(EMBEDDED_ENV) 36 #define SYMTAB_AVAILABLE 1 37 #include "elf-bfd.h" 38 #include "elf/mips.h" 39 #endif 40 41 /* Mips instructions are at maximum this many bytes long. */ 42 #define INSNLEN 4 43 44 45 /* FIXME: These should be shared with gdb somehow. */ 47 48 struct mips_cp0sel_name 49 { 50 unsigned int cp0reg; 51 unsigned int sel; 52 const char * const name; 53 }; 54 55 /* The mips16 registers. */ 56 static const unsigned int mips16_to_32_reg_map[] = 57 { 58 16, 17, 2, 3, 4, 5, 6, 7 59 }; 60 61 /* The microMIPS registers with type b. */ 62 #define micromips_to_32_reg_b_map mips16_to_32_reg_map 63 64 /* The microMIPS registers with type c. */ 65 #define micromips_to_32_reg_c_map mips16_to_32_reg_map 66 67 /* The microMIPS registers with type d. */ 68 #define micromips_to_32_reg_d_map mips16_to_32_reg_map 69 70 /* The microMIPS registers with type e. */ 71 #define micromips_to_32_reg_e_map mips16_to_32_reg_map 72 73 /* The microMIPS registers with type f. */ 74 #define micromips_to_32_reg_f_map mips16_to_32_reg_map 75 76 /* The microMIPS registers with type g. */ 77 #define micromips_to_32_reg_g_map mips16_to_32_reg_map 78 79 /* The microMIPS registers with type h. */ 80 static const unsigned int micromips_to_32_reg_h_map[] = 81 { 82 5, 5, 6, 4, 4, 4, 4, 4 83 }; 84 85 /* The microMIPS registers with type i. */ 86 static const unsigned int micromips_to_32_reg_i_map[] = 87 { 88 6, 7, 7, 21, 22, 5, 6, 7 89 }; 90 91 /* The microMIPS registers with type j: 32 registers. */ 92 93 /* The microMIPS registers with type l. */ 94 #define micromips_to_32_reg_l_map mips16_to_32_reg_map 95 96 /* The microMIPS registers with type m. */ 97 static const unsigned int micromips_to_32_reg_m_map[] = 98 { 99 0, 17, 2, 3, 16, 18, 19, 20 100 }; 101 102 /* The microMIPS registers with type n. */ 103 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map 104 105 /* The microMIPS registers with type p: 32 registers. */ 106 107 /* The microMIPS registers with type q. */ 108 static const unsigned int micromips_to_32_reg_q_map[] = 109 { 110 0, 17, 2, 3, 4, 5, 6, 7 111 }; 112 113 /* reg type s is $29. */ 114 115 /* reg type t is the same as the last register. */ 116 117 /* reg type y is $31. */ 118 119 /* reg type z is $0. */ 120 121 /* micromips imm B type. */ 122 static const int micromips_imm_b_map[8] = 123 { 124 1, 4, 8, 12, 16, 20, 24, -1 125 }; 126 127 /* micromips imm C type. */ 128 static const int micromips_imm_c_map[16] = 129 { 130 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535 131 }; 132 133 /* micromips imm D type: (-512..511)<<1. */ 134 /* micromips imm E type: (-64..63)<<1. */ 135 /* micromips imm F type: (0..63). */ 136 /* micromips imm G type: (-1..14). */ 137 /* micromips imm H type: (0..15)<<1. */ 138 /* micromips imm I type: (-1..126). */ 139 /* micromips imm J type: (0..15)<<2. */ 140 /* micromips imm L type: (0..15). */ 141 /* micromips imm M type: (1..8). */ 142 /* micromips imm W type: (0..63)<<2. */ 143 /* micromips imm X type: (-8..7). */ 144 /* micromips imm Y type: (-258..-3, 2..257)<<2. */ 145 146 #define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]] 147 148 149 static const char * const mips_gpr_names_numeric[32] = 150 { 151 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 152 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 153 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 154 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 155 }; 156 157 static const char * const mips_gpr_names_oldabi[32] = 158 { 159 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 160 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", 161 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 162 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 163 }; 164 165 static const char * const mips_gpr_names_newabi[32] = 166 { 167 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 168 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", 169 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 170 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 171 }; 172 173 static const char * const mips_fpr_names_numeric[32] = 174 { 175 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 176 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 177 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 178 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31" 179 }; 180 181 static const char * const mips_fpr_names_32[32] = 182 { 183 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f", 184 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f", 185 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f", 186 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f" 187 }; 188 189 static const char * const mips_fpr_names_n32[32] = 190 { 191 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3", 192 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", 193 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9", 194 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13" 195 }; 196 197 static const char * const mips_fpr_names_64[32] = 198 { 199 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3", 200 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", 201 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11", 202 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7" 203 }; 204 205 static const char * const mips_cp0_names_numeric[32] = 206 { 207 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 208 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 209 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 210 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 211 }; 212 213 static const char * const mips_cp0_names_r3000[32] = 214 { 215 "c0_index", "c0_random", "c0_entrylo", "$3", 216 "c0_context", "$5", "$6", "$7", 217 "c0_badvaddr", "$9", "c0_entryhi", "$11", 218 "c0_sr", "c0_cause", "c0_epc", "c0_prid", 219 "$16", "$17", "$18", "$19", 220 "$20", "$21", "$22", "$23", 221 "$24", "$25", "$26", "$27", 222 "$28", "$29", "$30", "$31", 223 }; 224 225 static const char * const mips_cp0_names_r4000[32] = 226 { 227 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 228 "c0_context", "c0_pagemask", "c0_wired", "$7", 229 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 230 "c0_sr", "c0_cause", "c0_epc", "c0_prid", 231 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 232 "c0_xcontext", "$21", "$22", "$23", 233 "$24", "$25", "c0_ecc", "c0_cacheerr", 234 "c0_taglo", "c0_taghi", "c0_errorepc", "$31", 235 }; 236 237 static const char * const mips_cp0_names_mips3264[32] = 238 { 239 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 240 "c0_context", "c0_pagemask", "c0_wired", "$7", 241 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 242 "c0_status", "c0_cause", "c0_epc", "c0_prid", 243 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 244 "c0_xcontext", "$21", "$22", "c0_debug", 245 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", 246 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", 247 }; 248 249 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = 250 { 251 { 16, 1, "c0_config1" }, 252 { 16, 2, "c0_config2" }, 253 { 16, 3, "c0_config3" }, 254 { 18, 1, "c0_watchlo,1" }, 255 { 18, 2, "c0_watchlo,2" }, 256 { 18, 3, "c0_watchlo,3" }, 257 { 18, 4, "c0_watchlo,4" }, 258 { 18, 5, "c0_watchlo,5" }, 259 { 18, 6, "c0_watchlo,6" }, 260 { 18, 7, "c0_watchlo,7" }, 261 { 19, 1, "c0_watchhi,1" }, 262 { 19, 2, "c0_watchhi,2" }, 263 { 19, 3, "c0_watchhi,3" }, 264 { 19, 4, "c0_watchhi,4" }, 265 { 19, 5, "c0_watchhi,5" }, 266 { 19, 6, "c0_watchhi,6" }, 267 { 19, 7, "c0_watchhi,7" }, 268 { 25, 1, "c0_perfcnt,1" }, 269 { 25, 2, "c0_perfcnt,2" }, 270 { 25, 3, "c0_perfcnt,3" }, 271 { 25, 4, "c0_perfcnt,4" }, 272 { 25, 5, "c0_perfcnt,5" }, 273 { 25, 6, "c0_perfcnt,6" }, 274 { 25, 7, "c0_perfcnt,7" }, 275 { 27, 1, "c0_cacheerr,1" }, 276 { 27, 2, "c0_cacheerr,2" }, 277 { 27, 3, "c0_cacheerr,3" }, 278 { 28, 1, "c0_datalo" }, 279 { 29, 1, "c0_datahi" } 280 }; 281 282 static const char * const mips_cp0_names_mips3264r2[32] = 283 { 284 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 285 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena", 286 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 287 "c0_status", "c0_cause", "c0_epc", "c0_prid", 288 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 289 "c0_xcontext", "$21", "$22", "c0_debug", 290 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", 291 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", 292 }; 293 294 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = 295 { 296 { 4, 1, "c0_contextconfig" }, 297 { 0, 1, "c0_mvpcontrol" }, 298 { 0, 2, "c0_mvpconf0" }, 299 { 0, 3, "c0_mvpconf1" }, 300 { 1, 1, "c0_vpecontrol" }, 301 { 1, 2, "c0_vpeconf0" }, 302 { 1, 3, "c0_vpeconf1" }, 303 { 1, 4, "c0_yqmask" }, 304 { 1, 5, "c0_vpeschedule" }, 305 { 1, 6, "c0_vpeschefback" }, 306 { 2, 1, "c0_tcstatus" }, 307 { 2, 2, "c0_tcbind" }, 308 { 2, 3, "c0_tcrestart" }, 309 { 2, 4, "c0_tchalt" }, 310 { 2, 5, "c0_tccontext" }, 311 { 2, 6, "c0_tcschedule" }, 312 { 2, 7, "c0_tcschefback" }, 313 { 5, 1, "c0_pagegrain" }, 314 { 6, 1, "c0_srsconf0" }, 315 { 6, 2, "c0_srsconf1" }, 316 { 6, 3, "c0_srsconf2" }, 317 { 6, 4, "c0_srsconf3" }, 318 { 6, 5, "c0_srsconf4" }, 319 { 12, 1, "c0_intctl" }, 320 { 12, 2, "c0_srsctl" }, 321 { 12, 3, "c0_srsmap" }, 322 { 15, 1, "c0_ebase" }, 323 { 16, 1, "c0_config1" }, 324 { 16, 2, "c0_config2" }, 325 { 16, 3, "c0_config3" }, 326 { 18, 1, "c0_watchlo,1" }, 327 { 18, 2, "c0_watchlo,2" }, 328 { 18, 3, "c0_watchlo,3" }, 329 { 18, 4, "c0_watchlo,4" }, 330 { 18, 5, "c0_watchlo,5" }, 331 { 18, 6, "c0_watchlo,6" }, 332 { 18, 7, "c0_watchlo,7" }, 333 { 19, 1, "c0_watchhi,1" }, 334 { 19, 2, "c0_watchhi,2" }, 335 { 19, 3, "c0_watchhi,3" }, 336 { 19, 4, "c0_watchhi,4" }, 337 { 19, 5, "c0_watchhi,5" }, 338 { 19, 6, "c0_watchhi,6" }, 339 { 19, 7, "c0_watchhi,7" }, 340 { 23, 1, "c0_tracecontrol" }, 341 { 23, 2, "c0_tracecontrol2" }, 342 { 23, 3, "c0_usertracedata" }, 343 { 23, 4, "c0_tracebpc" }, 344 { 25, 1, "c0_perfcnt,1" }, 345 { 25, 2, "c0_perfcnt,2" }, 346 { 25, 3, "c0_perfcnt,3" }, 347 { 25, 4, "c0_perfcnt,4" }, 348 { 25, 5, "c0_perfcnt,5" }, 349 { 25, 6, "c0_perfcnt,6" }, 350 { 25, 7, "c0_perfcnt,7" }, 351 { 27, 1, "c0_cacheerr,1" }, 352 { 27, 2, "c0_cacheerr,2" }, 353 { 27, 3, "c0_cacheerr,3" }, 354 { 28, 1, "c0_datalo" }, 355 { 28, 2, "c0_taglo1" }, 356 { 28, 3, "c0_datalo1" }, 357 { 28, 4, "c0_taglo2" }, 358 { 28, 5, "c0_datalo2" }, 359 { 28, 6, "c0_taglo3" }, 360 { 28, 7, "c0_datalo3" }, 361 { 29, 1, "c0_datahi" }, 362 { 29, 2, "c0_taghi1" }, 363 { 29, 3, "c0_datahi1" }, 364 { 29, 4, "c0_taghi2" }, 365 { 29, 5, "c0_datahi2" }, 366 { 29, 6, "c0_taghi3" }, 367 { 29, 7, "c0_datahi3" }, 368 }; 369 370 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */ 371 static const char * const mips_cp0_names_sb1[32] = 372 { 373 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 374 "c0_context", "c0_pagemask", "c0_wired", "$7", 375 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 376 "c0_status", "c0_cause", "c0_epc", "c0_prid", 377 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 378 "c0_xcontext", "$21", "$22", "c0_debug", 379 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i", 380 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave", 381 }; 382 383 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = 384 { 385 { 16, 1, "c0_config1" }, 386 { 18, 1, "c0_watchlo,1" }, 387 { 19, 1, "c0_watchhi,1" }, 388 { 22, 0, "c0_perftrace" }, 389 { 23, 3, "c0_edebug" }, 390 { 25, 1, "c0_perfcnt,1" }, 391 { 25, 2, "c0_perfcnt,2" }, 392 { 25, 3, "c0_perfcnt,3" }, 393 { 25, 4, "c0_perfcnt,4" }, 394 { 25, 5, "c0_perfcnt,5" }, 395 { 25, 6, "c0_perfcnt,6" }, 396 { 25, 7, "c0_perfcnt,7" }, 397 { 26, 1, "c0_buserr_pa" }, 398 { 27, 1, "c0_cacheerr_d" }, 399 { 27, 3, "c0_cacheerr_d_pa" }, 400 { 28, 1, "c0_datalo_i" }, 401 { 28, 2, "c0_taglo_d" }, 402 { 28, 3, "c0_datalo_d" }, 403 { 29, 1, "c0_datahi_i" }, 404 { 29, 2, "c0_taghi_d" }, 405 { 29, 3, "c0_datahi_d" }, 406 }; 407 408 /* Xlr cop0 register names. */ 409 static const char * const mips_cp0_names_xlr[32] = { 410 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 411 "c0_context", "c0_pagemask", "c0_wired", "$7", 412 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 413 "c0_status", "c0_cause", "c0_epc", "c0_prid", 414 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 415 "c0_xcontext", "$21", "$22", "c0_debug", 416 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i", 417 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave", 418 }; 419 420 /* XLR's CP0 Select Registers. */ 421 422 static const struct mips_cp0sel_name mips_cp0sel_names_xlr[] = { 423 { 9, 6, "c0_extintreq" }, 424 { 9, 7, "c0_extintmask" }, 425 { 15, 1, "c0_ebase" }, 426 { 16, 1, "c0_config1" }, 427 { 16, 2, "c0_config2" }, 428 { 16, 3, "c0_config3" }, 429 { 16, 7, "c0_procid2" }, 430 { 18, 1, "c0_watchlo,1" }, 431 { 18, 2, "c0_watchlo,2" }, 432 { 18, 3, "c0_watchlo,3" }, 433 { 18, 4, "c0_watchlo,4" }, 434 { 18, 5, "c0_watchlo,5" }, 435 { 18, 6, "c0_watchlo,6" }, 436 { 18, 7, "c0_watchlo,7" }, 437 { 19, 1, "c0_watchhi,1" }, 438 { 19, 2, "c0_watchhi,2" }, 439 { 19, 3, "c0_watchhi,3" }, 440 { 19, 4, "c0_watchhi,4" }, 441 { 19, 5, "c0_watchhi,5" }, 442 { 19, 6, "c0_watchhi,6" }, 443 { 19, 7, "c0_watchhi,7" }, 444 { 25, 1, "c0_perfcnt,1" }, 445 { 25, 2, "c0_perfcnt,2" }, 446 { 25, 3, "c0_perfcnt,3" }, 447 { 25, 4, "c0_perfcnt,4" }, 448 { 25, 5, "c0_perfcnt,5" }, 449 { 25, 6, "c0_perfcnt,6" }, 450 { 25, 7, "c0_perfcnt,7" }, 451 { 27, 1, "c0_cacheerr,1" }, 452 { 27, 2, "c0_cacheerr,2" }, 453 { 27, 3, "c0_cacheerr,3" }, 454 { 28, 1, "c0_datalo" }, 455 { 29, 1, "c0_datahi" } 456 }; 457 458 static const char * const mips_hwr_names_numeric[32] = 459 { 460 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 461 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 462 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 463 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 464 }; 465 466 static const char * const mips_hwr_names_mips3264r2[32] = 467 { 468 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres", 469 "$4", "$5", "$6", "$7", 470 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 471 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 472 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 473 }; 474 475 struct mips_abi_choice 476 { 477 const char * name; 478 const char * const *gpr_names; 479 const char * const *fpr_names; 480 }; 481 482 struct mips_abi_choice mips_abi_choices[] = 483 { 484 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric }, 485 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 }, 486 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 }, 487 { "64", mips_gpr_names_newabi, mips_fpr_names_64 }, 488 }; 489 490 struct mips_arch_choice 491 { 492 const char *name; 493 int bfd_mach_valid; 494 unsigned long bfd_mach; 495 int processor; 496 int isa; 497 const char * const *cp0_names; 498 const struct mips_cp0sel_name *cp0sel_names; 499 unsigned int cp0sel_names_len; 500 const char * const *hwr_names; 501 }; 502 503 const struct mips_arch_choice mips_arch_choices[] = 504 { 505 { "numeric", 0, 0, 0, 0, 506 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 507 508 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, 509 mips_cp0_names_r3000, NULL, 0, mips_hwr_names_numeric }, 510 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, 511 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 512 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, 513 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric }, 514 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, 515 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 516 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, 517 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 518 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, 519 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 520 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, 521 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 522 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, 523 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 524 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, 525 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric }, 526 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, 527 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 528 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, 529 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 530 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, 531 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 532 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, 533 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 534 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, 535 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 536 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, 537 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 538 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 539 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 540 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 541 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 542 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, 543 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 544 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, 545 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 546 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, 547 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 548 { "r14000", 1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4, 549 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 550 { "r16000", 1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4, 551 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 552 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, 553 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 554 555 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs. 556 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See 557 _MIPS32 Architecture For Programmers Volume I: Introduction to the 558 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95), 559 page 1. */ 560 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32, 561 ISA_MIPS32 | INSN_SMARTMIPS, 562 mips_cp0_names_mips3264, 563 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), 564 mips_hwr_names_numeric }, 565 566 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2, 567 (ISA_MIPS32R2 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2 568 | INSN_MIPS3D | INSN_MT | INSN_MCU), 569 mips_cp0_names_mips3264r2, 570 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 571 mips_hwr_names_mips3264r2 }, 572 573 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */ 574 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64, 575 ISA_MIPS64 | INSN_MIPS3D | INSN_MDMX, 576 mips_cp0_names_mips3264, 577 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), 578 mips_hwr_names_numeric }, 579 580 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2, 581 (ISA_MIPS64R2 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2 582 | INSN_DSP64 | INSN_MT | INSN_MDMX | INSN_MCU), 583 mips_cp0_names_mips3264r2, 584 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 585 mips_hwr_names_mips3264r2 }, 586 587 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1, 588 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1, 589 mips_cp0_names_sb1, 590 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1), 591 mips_hwr_names_numeric }, 592 593 { "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E, 594 ISA_MIPS3 | INSN_LOONGSON_2E, mips_cp0_names_numeric, 595 NULL, 0, mips_hwr_names_numeric }, 596 597 { "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F, 598 ISA_MIPS3 | INSN_LOONGSON_2F, mips_cp0_names_numeric, 599 NULL, 0, mips_hwr_names_numeric }, 600 601 { "loongson3a", 1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A, 602 ISA_MIPS64 | INSN_LOONGSON_3A, mips_cp0_names_numeric, 603 NULL, 0, mips_hwr_names_numeric }, 604 605 { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON, 606 ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_numeric, NULL, 0, 607 mips_hwr_names_numeric }, 608 609 { "octeon+", 1, bfd_mach_mips_octeonp, CPU_OCTEONP, 610 ISA_MIPS64R2 | INSN_OCTEONP, mips_cp0_names_numeric, 611 NULL, 0, mips_hwr_names_numeric }, 612 613 { "octeon2", 1, bfd_mach_mips_octeon2, CPU_OCTEON2, 614 ISA_MIPS64R2 | INSN_OCTEON2, mips_cp0_names_numeric, 615 NULL, 0, mips_hwr_names_numeric }, 616 617 { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR, 618 ISA_MIPS64 | INSN_XLR, 619 mips_cp0_names_xlr, 620 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr), 621 mips_hwr_names_numeric }, 622 623 /* XLP is mostly like XLR, with the prominent exception it is being 624 MIPS64R2. */ 625 { "xlp", 1, bfd_mach_mips_xlr, CPU_XLR, 626 ISA_MIPS64R2 | INSN_XLR, 627 mips_cp0_names_xlr, 628 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr), 629 mips_hwr_names_numeric }, 630 631 /* This entry, mips16, is here only for ISA/processor selection; do 632 not print its name. */ 633 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3, 634 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 635 }; 636 637 /* ISA and processor type to disassemble for, and register names to use. 638 set_default_mips_dis_options and parse_mips_dis_options fill in these 639 values. */ 640 static int mips_processor; 641 static int mips_isa; 642 static int micromips_ase; 643 static const char * const *mips_gpr_names; 644 static const char * const *mips_fpr_names; 645 static const char * const *mips_cp0_names; 646 static const struct mips_cp0sel_name *mips_cp0sel_names; 647 static int mips_cp0sel_names_len; 648 static const char * const *mips_hwr_names; 649 650 /* Other options */ 651 static int no_aliases; /* If set disassemble as most general inst. */ 652 653 static const struct mips_abi_choice * 655 choose_abi_by_name (const char *name, unsigned int namelen) 656 { 657 const struct mips_abi_choice *c; 658 unsigned int i; 659 660 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++) 661 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0 662 && strlen (mips_abi_choices[i].name) == namelen) 663 c = &mips_abi_choices[i]; 664 665 return c; 666 } 667 668 static const struct mips_arch_choice * 669 choose_arch_by_name (const char *name, unsigned int namelen) 670 { 671 const struct mips_arch_choice *c = NULL; 672 unsigned int i; 673 674 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) 675 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0 676 && strlen (mips_arch_choices[i].name) == namelen) 677 c = &mips_arch_choices[i]; 678 679 return c; 680 } 681 682 static const struct mips_arch_choice * 683 choose_arch_by_number (unsigned long mach) 684 { 685 static unsigned long hint_bfd_mach; 686 static const struct mips_arch_choice *hint_arch_choice; 687 const struct mips_arch_choice *c; 688 unsigned int i; 689 690 /* We optimize this because even if the user specifies no 691 flags, this will be done for every instruction! */ 692 if (hint_bfd_mach == mach 693 && hint_arch_choice != NULL 694 && hint_arch_choice->bfd_mach == hint_bfd_mach) 695 return hint_arch_choice; 696 697 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) 698 { 699 if (mips_arch_choices[i].bfd_mach_valid 700 && mips_arch_choices[i].bfd_mach == mach) 701 { 702 c = &mips_arch_choices[i]; 703 hint_bfd_mach = mach; 704 hint_arch_choice = c; 705 } 706 } 707 return c; 708 } 709 710 /* Check if the object uses NewABI conventions. */ 711 712 static int 713 is_newabi (Elf_Internal_Ehdr *header) 714 { 715 /* There are no old-style ABIs which use 64-bit ELF. */ 716 if (header->e_ident[EI_CLASS] == ELFCLASS64) 717 return 1; 718 719 /* If a 32-bit ELF file, n32 is a new-style ABI. */ 720 if ((header->e_flags & EF_MIPS_ABI2) != 0) 721 return 1; 722 723 return 0; 724 } 725 726 /* Check if the object has microMIPS ASE code. */ 727 728 static int 729 is_micromips (Elf_Internal_Ehdr *header) 730 { 731 if ((header->e_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0) 732 return 1; 733 734 return 0; 735 } 736 737 static void 738 set_default_mips_dis_options (struct disassemble_info *info) 739 { 740 const struct mips_arch_choice *chosen_arch; 741 742 /* Defaults: mipsIII/r3000 (?!), no microMIPS ASE (any compressed code 743 is MIPS16 ASE) (o)32-style ("oldabi") GPR names, and numeric FPR, 744 CP0 register, and HWR names. */ 745 mips_isa = ISA_MIPS3; 746 mips_processor = CPU_R3000; 747 micromips_ase = 0; 748 mips_gpr_names = mips_gpr_names_oldabi; 749 mips_fpr_names = mips_fpr_names_numeric; 750 mips_cp0_names = mips_cp0_names_numeric; 751 mips_cp0sel_names = NULL; 752 mips_cp0sel_names_len = 0; 753 mips_hwr_names = mips_hwr_names_numeric; 754 no_aliases = 0; 755 756 /* Update settings according to the ELF file header flags. */ 757 if (info->flavour == bfd_target_elf_flavour && info->section != NULL) 758 { 759 Elf_Internal_Ehdr *header; 760 761 header = elf_elfheader (info->section->owner); 762 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */ 763 if (is_newabi (header)) 764 mips_gpr_names = mips_gpr_names_newabi; 765 /* If a microMIPS binary, then don't use MIPS16 bindings. */ 766 micromips_ase = is_micromips (header); 767 } 768 769 /* Set ISA, architecture, and cp0 register names as best we can. */ 770 #if ! SYMTAB_AVAILABLE 771 /* This is running out on a target machine, not in a host tool. 772 FIXME: Where does mips_target_info come from? */ 773 target_processor = mips_target_info.processor; 774 mips_isa = mips_target_info.isa; 775 #else 776 chosen_arch = choose_arch_by_number (info->mach); 777 if (chosen_arch != NULL) 778 { 779 mips_processor = chosen_arch->processor; 780 mips_isa = chosen_arch->isa; 781 mips_cp0_names = chosen_arch->cp0_names; 782 mips_cp0sel_names = chosen_arch->cp0sel_names; 783 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 784 mips_hwr_names = chosen_arch->hwr_names; 785 } 786 #endif 787 } 788 789 static void 790 parse_mips_dis_option (const char *option, unsigned int len) 791 { 792 unsigned int i, optionlen, vallen; 793 const char *val; 794 const struct mips_abi_choice *chosen_abi; 795 const struct mips_arch_choice *chosen_arch; 796 797 /* Try to match options that are simple flags */ 798 if (CONST_STRNEQ (option, "no-aliases")) 799 { 800 no_aliases = 1; 801 return; 802 } 803 804 /* Look for the = that delimits the end of the option name. */ 805 for (i = 0; i < len; i++) 806 if (option[i] == '=') 807 break; 808 809 if (i == 0) /* Invalid option: no name before '='. */ 810 return; 811 if (i == len) /* Invalid option: no '='. */ 812 return; 813 if (i == (len - 1)) /* Invalid option: no value after '='. */ 814 return; 815 816 optionlen = i; 817 val = option + (optionlen + 1); 818 vallen = len - (optionlen + 1); 819 820 if (strncmp ("gpr-names", option, optionlen) == 0 821 && strlen ("gpr-names") == optionlen) 822 { 823 chosen_abi = choose_abi_by_name (val, vallen); 824 if (chosen_abi != NULL) 825 mips_gpr_names = chosen_abi->gpr_names; 826 return; 827 } 828 829 if (strncmp ("fpr-names", option, optionlen) == 0 830 && strlen ("fpr-names") == optionlen) 831 { 832 chosen_abi = choose_abi_by_name (val, vallen); 833 if (chosen_abi != NULL) 834 mips_fpr_names = chosen_abi->fpr_names; 835 return; 836 } 837 838 if (strncmp ("cp0-names", option, optionlen) == 0 839 && strlen ("cp0-names") == optionlen) 840 { 841 chosen_arch = choose_arch_by_name (val, vallen); 842 if (chosen_arch != NULL) 843 { 844 mips_cp0_names = chosen_arch->cp0_names; 845 mips_cp0sel_names = chosen_arch->cp0sel_names; 846 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 847 } 848 return; 849 } 850 851 if (strncmp ("hwr-names", option, optionlen) == 0 852 && strlen ("hwr-names") == optionlen) 853 { 854 chosen_arch = choose_arch_by_name (val, vallen); 855 if (chosen_arch != NULL) 856 mips_hwr_names = chosen_arch->hwr_names; 857 return; 858 } 859 860 if (strncmp ("reg-names", option, optionlen) == 0 861 && strlen ("reg-names") == optionlen) 862 { 863 /* We check both ABI and ARCH here unconditionally, so 864 that "numeric" will do the desirable thing: select 865 numeric register names for all registers. Other than 866 that, a given name probably won't match both. */ 867 chosen_abi = choose_abi_by_name (val, vallen); 868 if (chosen_abi != NULL) 869 { 870 mips_gpr_names = chosen_abi->gpr_names; 871 mips_fpr_names = chosen_abi->fpr_names; 872 } 873 chosen_arch = choose_arch_by_name (val, vallen); 874 if (chosen_arch != NULL) 875 { 876 mips_cp0_names = chosen_arch->cp0_names; 877 mips_cp0sel_names = chosen_arch->cp0sel_names; 878 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 879 mips_hwr_names = chosen_arch->hwr_names; 880 } 881 return; 882 } 883 884 /* Invalid option. */ 885 } 886 887 static void 888 parse_mips_dis_options (const char *options) 889 { 890 const char *option_end; 891 892 if (options == NULL) 893 return; 894 895 while (*options != '\0') 896 { 897 /* Skip empty options. */ 898 if (*options == ',') 899 { 900 options++; 901 continue; 902 } 903 904 /* We know that *options is neither NUL or a comma. */ 905 option_end = options + 1; 906 while (*option_end != ',' && *option_end != '\0') 907 option_end++; 908 909 parse_mips_dis_option (options, option_end - options); 910 911 /* Go on to the next one. If option_end points to a comma, it 912 will be skipped above. */ 913 options = option_end; 914 } 915 } 916 917 static const struct mips_cp0sel_name * 918 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names, 919 unsigned int len, 920 unsigned int cp0reg, 921 unsigned int sel) 922 { 923 unsigned int i; 924 925 for (i = 0; i < len; i++) 926 if (names[i].cp0reg == cp0reg && names[i].sel == sel) 927 return &names[i]; 928 return NULL; 929 } 930 931 /* Print insn arguments for 32/64-bit code. */ 933 934 static void 935 print_insn_args (const char *d, 936 int l, 937 bfd_vma pc, 938 struct disassemble_info *info, 939 const struct mips_opcode *opp) 940 { 941 const fprintf_ftype infprintf = info->fprintf_func; 942 unsigned int lsb, msb, msbd; 943 void *is = info->stream; 944 int op; 945 946 lsb = 0; 947 948 #define GET_OP(insn, field) \ 949 (((insn) >> OP_SH_##field) & OP_MASK_##field) 950 #define GET_OP_S(insn, field) \ 951 ((GET_OP (insn, field) ^ ((OP_MASK_##field >> 1) + 1)) \ 952 - ((OP_MASK_##field >> 1) + 1)) 953 for (; *d != '\0'; d++) 954 { 955 switch (*d) 956 { 957 case ',': 958 case '(': 959 case ')': 960 case '[': 961 case ']': 962 infprintf (is, "%c", *d); 963 break; 964 965 case '+': 966 /* Extension character; switch for second char. */ 967 d++; 968 switch (*d) 969 { 970 case '\0': 971 /* xgettext:c-format */ 972 infprintf (is, 973 _("# internal error, " 974 "incomplete extension sequence (+)")); 975 return; 976 977 case 'A': 978 lsb = GET_OP (l, SHAMT); 979 infprintf (is, "0x%x", lsb); 980 break; 981 982 case 'B': 983 msb = GET_OP (l, INSMSB); 984 infprintf (is, "0x%x", msb - lsb + 1); 985 break; 986 987 case '1': 988 infprintf (is, "0x%x", GET_OP (l, UDI1)); 989 break; 990 991 case '2': 992 infprintf (is, "0x%x", GET_OP (l, UDI2)); 993 break; 994 995 case '3': 996 infprintf (is, "0x%x", GET_OP (l, UDI3)); 997 break; 998 999 case '4': 1000 infprintf (is, "0x%x", GET_OP (l, UDI4)); 1001 break; 1002 1003 case 'C': 1004 case 'H': 1005 msbd = GET_OP (l, EXTMSBD); 1006 infprintf (is, "0x%x", msbd + 1); 1007 break; 1008 1009 case 'D': 1010 { 1011 const struct mips_cp0sel_name *n; 1012 unsigned int cp0reg, sel; 1013 1014 cp0reg = GET_OP (l, RD); 1015 sel = GET_OP (l, SEL); 1016 1017 /* CP0 register including 'sel' code for mtcN (et al.), to be 1018 printed textually if known. If not known, print both 1019 CP0 register name and sel numerically since CP0 register 1020 with sel 0 may have a name unrelated to register being 1021 printed. */ 1022 n = lookup_mips_cp0sel_name(mips_cp0sel_names, 1023 mips_cp0sel_names_len, cp0reg, sel); 1024 if (n != NULL) 1025 infprintf (is, "%s", n->name); 1026 else 1027 infprintf (is, "$%d,%d", cp0reg, sel); 1028 break; 1029 } 1030 1031 case 'E': 1032 lsb = GET_OP (l, SHAMT) + 32; 1033 infprintf (is, "0x%x", lsb); 1034 break; 1035 1036 case 'F': 1037 msb = GET_OP (l, INSMSB) + 32; 1038 infprintf (is, "0x%x", msb - lsb + 1); 1039 break; 1040 1041 case 'G': 1042 msbd = GET_OP (l, EXTMSBD) + 32; 1043 infprintf (is, "0x%x", msbd + 1); 1044 break; 1045 1046 case 't': /* Coprocessor 0 reg name */ 1047 infprintf (is, "%s", mips_cp0_names[GET_OP (l, RT)]); 1048 break; 1049 1050 case 'T': /* Coprocessor 0 reg name */ 1051 { 1052 const struct mips_cp0sel_name *n; 1053 unsigned int cp0reg, sel; 1054 1055 cp0reg = GET_OP (l, RT); 1056 sel = GET_OP (l, SEL); 1057 1058 /* CP0 register including 'sel' code for mftc0, to be 1059 printed textually if known. If not known, print both 1060 CP0 register name and sel numerically since CP0 register 1061 with sel 0 may have a name unrelated to register being 1062 printed. */ 1063 n = lookup_mips_cp0sel_name(mips_cp0sel_names, 1064 mips_cp0sel_names_len, cp0reg, sel); 1065 if (n != NULL) 1066 infprintf (is, "%s", n->name); 1067 else 1068 infprintf (is, "$%d,%d", cp0reg, sel); 1069 break; 1070 } 1071 1072 case 'x': /* bbit bit index */ 1073 infprintf (is, "0x%x", GET_OP (l, BBITIND)); 1074 break; 1075 1076 case 'p': /* cins, cins32, exts and exts32 position */ 1077 infprintf (is, "0x%x", GET_OP (l, CINSPOS)); 1078 break; 1079 1080 case 's': /* cins and exts length-minus-one */ 1081 infprintf (is, "0x%x", GET_OP (l, CINSLM1)); 1082 break; 1083 1084 case 'S': /* cins32 and exts32 length-minus-one field */ 1085 infprintf (is, "0x%x", GET_OP (l, CINSLM1)); 1086 break; 1087 1088 case 'Q': /* seqi/snei immediate field */ 1089 infprintf (is, "%d", GET_OP_S (l, SEQI)); 1090 break; 1091 1092 case 'a': /* 8-bit signed offset in bit 6 */ 1093 infprintf (is, "%d", GET_OP_S (l, OFFSET_A)); 1094 break; 1095 1096 case 'b': /* 8-bit signed offset in bit 3 */ 1097 infprintf (is, "%d", GET_OP_S (l, OFFSET_B)); 1098 break; 1099 1100 case 'c': /* 9-bit signed offset in bit 6 */ 1101 /* Left shift 4 bits to print the real offset. */ 1102 infprintf (is, "%d", GET_OP_S (l, OFFSET_C) << 4); 1103 break; 1104 1105 case 'z': 1106 infprintf (is, "%s", mips_gpr_names[GET_OP (l, RZ)]); 1107 break; 1108 1109 case 'Z': 1110 infprintf (is, "%s", mips_fpr_names[GET_OP (l, FZ)]); 1111 break; 1112 1113 default: 1114 /* xgettext:c-format */ 1115 infprintf (is, 1116 _("# internal error, " 1117 "undefined extension sequence (+%c)"), 1118 *d); 1119 return; 1120 } 1121 break; 1122 1123 case '2': 1124 infprintf (is, "0x%x", GET_OP (l, BP)); 1125 break; 1126 1127 case '3': 1128 infprintf (is, "0x%x", GET_OP (l, SA3)); 1129 break; 1130 1131 case '4': 1132 infprintf (is, "0x%x", GET_OP (l, SA4)); 1133 break; 1134 1135 case '5': 1136 infprintf (is, "0x%x", GET_OP (l, IMM8)); 1137 break; 1138 1139 case '6': 1140 infprintf (is, "0x%x", GET_OP (l, RS)); 1141 break; 1142 1143 case '7': 1144 infprintf (is, "$ac%d", GET_OP (l, DSPACC)); 1145 break; 1146 1147 case '8': 1148 infprintf (is, "0x%x", GET_OP (l, WRDSP)); 1149 break; 1150 1151 case '9': 1152 infprintf (is, "$ac%d", GET_OP (l, DSPACC_S)); 1153 break; 1154 1155 case '0': /* dsp 6-bit signed immediate in bit 20 */ 1156 infprintf (is, "%d", GET_OP_S (l, DSPSFT)); 1157 break; 1158 1159 case ':': /* dsp 7-bit signed immediate in bit 19 */ 1160 infprintf (is, "%d", GET_OP_S (l, DSPSFT_7)); 1161 break; 1162 1163 case '~': 1164 infprintf (is, "%d", GET_OP_S (l, OFFSET12)); 1165 break; 1166 1167 case '\\': 1168 infprintf (is, "0x%x", GET_OP (l, 3BITPOS)); 1169 break; 1170 1171 case '\'': 1172 infprintf (is, "0x%x", GET_OP (l, RDDSP)); 1173 break; 1174 1175 case '@': /* dsp 10-bit signed immediate in bit 16 */ 1176 infprintf (is, "%d", GET_OP_S (l, IMM10)); 1177 break; 1178 1179 case '!': 1180 infprintf (is, "%d", GET_OP (l, MT_U)); 1181 break; 1182 1183 case '$': 1184 infprintf (is, "%d", GET_OP (l, MT_H)); 1185 break; 1186 1187 case '*': 1188 infprintf (is, "$ac%d", GET_OP (l, MTACC_T)); 1189 break; 1190 1191 case '&': 1192 infprintf (is, "$ac%d", GET_OP (l, MTACC_D)); 1193 break; 1194 1195 case 'g': 1196 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */ 1197 infprintf (is, "$%d", GET_OP (l, RD)); 1198 break; 1199 1200 case 's': 1201 case 'b': 1202 case 'r': 1203 case 'v': 1204 infprintf (is, "%s", mips_gpr_names[GET_OP (l, RS)]); 1205 break; 1206 1207 case 't': 1208 case 'w': 1209 infprintf (is, "%s", mips_gpr_names[GET_OP (l, RT)]); 1210 break; 1211 1212 case 'i': 1213 case 'u': 1214 infprintf (is, "0x%x", GET_OP (l, IMMEDIATE)); 1215 break; 1216 1217 case 'j': /* Same as i, but sign-extended. */ 1218 case 'o': 1219 infprintf (is, "%d", GET_OP_S (l, DELTA)); 1220 break; 1221 1222 case 'h': 1223 infprintf (is, "0x%x", GET_OP (l, PREFX)); 1224 break; 1225 1226 case 'k': 1227 infprintf (is, "0x%x", GET_OP (l, CACHE)); 1228 break; 1229 1230 case 'a': 1231 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff) 1232 | (GET_OP (l, TARGET) << 2)); 1233 /* For gdb disassembler, force odd address on jalx. */ 1234 if (info->flavour == bfd_target_unknown_flavour 1235 && strcmp (opp->name, "jalx") == 0) 1236 info->target |= 1; 1237 (*info->print_address_func) (info->target, info); 1238 break; 1239 1240 case 'p': 1241 /* Sign extend the displacement. */ 1242 info->target = (GET_OP_S (l, DELTA) << 2) + pc + INSNLEN; 1243 (*info->print_address_func) (info->target, info); 1244 break; 1245 1246 case 'd': 1247 infprintf (is, "%s", mips_gpr_names[GET_OP (l, RD)]); 1248 break; 1249 1250 case 'U': 1251 { 1252 /* First check for both rd and rt being equal. */ 1253 unsigned int reg = GET_OP (l, RD); 1254 if (reg == GET_OP (l, RT)) 1255 infprintf (is, "%s", mips_gpr_names[reg]); 1256 else 1257 { 1258 /* If one is zero use the other. */ 1259 if (reg == 0) 1260 infprintf (is, "%s", mips_gpr_names[GET_OP (l, RT)]); 1261 else if (GET_OP (l, RT) == 0) 1262 infprintf (is, "%s", mips_gpr_names[reg]); 1263 else /* Bogus, result depends on processor. */ 1264 infprintf (is, "%s or %s", 1265 mips_gpr_names[reg], 1266 mips_gpr_names[GET_OP (l, RT)]); 1267 } 1268 } 1269 break; 1270 1271 case 'z': 1272 infprintf (is, "%s", mips_gpr_names[0]); 1273 break; 1274 1275 case '<': 1276 case '1': 1277 infprintf (is, "0x%x", GET_OP (l, SHAMT)); 1278 break; 1279 1280 case 'c': 1281 infprintf (is, "0x%x", GET_OP (l, CODE)); 1282 break; 1283 1284 case 'q': 1285 infprintf (is, "0x%x", GET_OP (l, CODE2)); 1286 break; 1287 1288 case 'C': 1289 infprintf (is, "0x%x", GET_OP (l, COPZ)); 1290 break; 1291 1292 case 'B': 1293 infprintf (is, "0x%x", GET_OP (l, CODE20)); 1294 break; 1295 1296 case 'J': 1297 infprintf (is, "0x%x", GET_OP (l, CODE19)); 1298 break; 1299 1300 case 'S': 1301 case 'V': 1302 infprintf (is, "%s", mips_fpr_names[GET_OP (l, FS)]); 1303 break; 1304 1305 case 'T': 1306 case 'W': 1307 infprintf (is, "%s", mips_fpr_names[GET_OP (l, FT)]); 1308 break; 1309 1310 case 'D': 1311 infprintf (is, "%s", mips_fpr_names[GET_OP (l, FD)]); 1312 break; 1313 1314 case 'R': 1315 infprintf (is, "%s", mips_fpr_names[GET_OP (l, FR)]); 1316 break; 1317 1318 case 'E': 1319 /* Coprocessor register for lwcN instructions, et al. 1320 1321 Note that there is no load/store cp0 instructions, and 1322 that FPU (cp1) instructions disassemble this field using 1323 'T' format. Therefore, until we gain understanding of 1324 cp2 register names, we can simply print the register 1325 numbers. */ 1326 infprintf (is, "$%d", GET_OP (l, RT)); 1327 break; 1328 1329 case 'G': 1330 /* Coprocessor register for mtcN instructions, et al. Note 1331 that FPU (cp1) instructions disassemble this field using 1332 'S' format. Therefore, we only need to worry about cp0, 1333 cp2, and cp3. */ 1334 op = GET_OP (l, OP); 1335 if (op == OP_OP_COP0) 1336 infprintf (is, "%s", mips_cp0_names[GET_OP (l, RD)]); 1337 else 1338 infprintf (is, "$%d", GET_OP (l, RD)); 1339 break; 1340 1341 case 'K': 1342 infprintf (is, "%s", mips_hwr_names[GET_OP (l, RD)]); 1343 break; 1344 1345 case 'N': 1346 infprintf (is, 1347 (opp->pinfo & (FP_D | FP_S)) != 0 ? "$fcc%d" : "$cc%d", 1348 GET_OP (l, BCC)); 1349 break; 1350 1351 case 'M': 1352 infprintf (is, "$fcc%d", GET_OP (l, CCC)); 1353 break; 1354 1355 case 'P': 1356 infprintf (is, "%d", GET_OP (l, PERFREG)); 1357 break; 1358 1359 case 'e': 1360 infprintf (is, "%d", GET_OP (l, VECBYTE)); 1361 break; 1362 1363 case '%': 1364 infprintf (is, "%d", GET_OP (l, VECALIGN)); 1365 break; 1366 1367 case 'H': 1368 infprintf (is, "%d", GET_OP (l, SEL)); 1369 break; 1370 1371 case 'O': 1372 infprintf (is, "%d", GET_OP (l, ALN)); 1373 break; 1374 1375 case 'Q': 1376 { 1377 unsigned int vsel = GET_OP (l, VSEL); 1378 1379 if ((vsel & 0x10) == 0) 1380 { 1381 int fmt; 1382 1383 vsel &= 0x0f; 1384 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1) 1385 if ((vsel & 1) == 0) 1386 break; 1387 infprintf (is, "$v%d[%d]", GET_OP (l, FT), vsel >> 1); 1388 } 1389 else if ((vsel & 0x08) == 0) 1390 { 1391 infprintf (is, "$v%d", GET_OP (l, FT)); 1392 } 1393 else 1394 { 1395 infprintf (is, "0x%x", GET_OP (l, FT)); 1396 } 1397 } 1398 break; 1399 1400 case 'X': 1401 infprintf (is, "$v%d", GET_OP (l, FD)); 1402 break; 1403 1404 case 'Y': 1405 infprintf (is, "$v%d", GET_OP (l, FS)); 1406 break; 1407 1408 case 'Z': 1409 infprintf (is, "$v%d", GET_OP (l, FT)); 1410 break; 1411 1412 default: 1413 /* xgettext:c-format */ 1414 infprintf (is, _("# internal error, undefined modifier (%c)"), *d); 1415 return; 1416 } 1417 } 1418 } 1419 1420 /* Print the mips instruction at address MEMADDR in debugged memory, 1422 on using INFO. Returns length of the instruction, in bytes, which is 1423 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if 1424 this is little-endian code. */ 1425 1426 static int 1427 print_insn_mips (bfd_vma memaddr, 1428 int word, 1429 struct disassemble_info *info) 1430 { 1431 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1]; 1432 const fprintf_ftype infprintf = info->fprintf_func; 1433 const struct mips_opcode *op; 1434 static bfd_boolean init = 0; 1435 void *is = info->stream; 1436 1437 /* Build a hash table to shorten the search time. */ 1438 if (! init) 1439 { 1440 unsigned int i; 1441 1442 for (i = 0; i <= OP_MASK_OP; i++) 1443 { 1444 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++) 1445 { 1446 if (op->pinfo == INSN_MACRO 1447 || (no_aliases && (op->pinfo2 & INSN2_ALIAS))) 1448 continue; 1449 if (i == GET_OP (op->match, OP)) 1450 { 1451 mips_hash[i] = op; 1452 break; 1453 } 1454 } 1455 } 1456 1457 init = 1; 1458 } 1459 1460 info->bytes_per_chunk = INSNLEN; 1461 info->display_endian = info->endian; 1462 info->insn_info_valid = 1; 1463 info->branch_delay_insns = 0; 1464 info->data_size = 0; 1465 info->insn_type = dis_nonbranch; 1466 info->target = 0; 1467 info->target2 = 0; 1468 1469 op = mips_hash[GET_OP (word, OP)]; 1470 if (op != NULL) 1471 { 1472 for (; op < &mips_opcodes[NUMOPCODES]; op++) 1473 { 1474 if (op->pinfo != INSN_MACRO 1475 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) 1476 && (word & op->mask) == op->match) 1477 { 1478 const char *d; 1479 1480 /* We always allow to disassemble the jalx instruction. */ 1481 if (!opcode_is_member (op, mips_isa, mips_processor) 1482 && strcmp (op->name, "jalx")) 1483 continue; 1484 1485 /* Figure out instruction type and branch delay information. */ 1486 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) 1487 { 1488 if ((op->pinfo & (INSN_WRITE_GPR_31 1489 | INSN_WRITE_GPR_D)) != 0) 1490 info->insn_type = dis_jsr; 1491 else 1492 info->insn_type = dis_branch; 1493 info->branch_delay_insns = 1; 1494 } 1495 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY 1496 | INSN_COND_BRANCH_LIKELY)) != 0) 1497 { 1498 if ((op->pinfo & INSN_WRITE_GPR_31) != 0) 1499 info->insn_type = dis_condjsr; 1500 else 1501 info->insn_type = dis_condbranch; 1502 info->branch_delay_insns = 1; 1503 } 1504 else if ((op->pinfo & (INSN_STORE_MEMORY 1505 | INSN_LOAD_MEMORY_DELAY)) != 0) 1506 info->insn_type = dis_dref; 1507 1508 infprintf (is, "%s", op->name); 1509 1510 d = op->args; 1511 if (d != NULL && *d != '\0') 1512 { 1513 infprintf (is, "\t"); 1514 print_insn_args (d, word, memaddr, info, op); 1515 } 1516 1517 return INSNLEN; 1518 } 1519 } 1520 } 1521 #undef GET_OP_S 1522 #undef GET_OP 1523 1524 /* Handle undefined instructions. */ 1525 info->insn_type = dis_noninsn; 1526 infprintf (is, "0x%x", word); 1527 return INSNLEN; 1528 } 1529 1530 /* Disassemble an operand for a mips16 instruction. */ 1532 1533 static void 1534 print_mips16_insn_arg (char type, 1535 const struct mips_opcode *op, 1536 int l, 1537 bfd_boolean use_extend, 1538 int extend, 1539 bfd_vma memaddr, 1540 struct disassemble_info *info) 1541 { 1542 const fprintf_ftype infprintf = info->fprintf_func; 1543 void *is = info->stream; 1544 1545 #define GET_OP(insn, field) \ 1546 (((insn) >> MIPS16OP_SH_##field) & MIPS16OP_MASK_##field) 1547 #define GET_OP_S(insn, field) \ 1548 ((GET_OP (insn, field) ^ ((MIPS16OP_MASK_##field >> 1) + 1)) \ 1549 - ((MIPS16OP_MASK_##field >> 1) + 1)) 1550 switch (type) 1551 { 1552 case ',': 1553 case '(': 1554 case ')': 1555 infprintf (is, "%c", type); 1556 break; 1557 1558 case 'y': 1559 case 'w': 1560 infprintf (is, "%s", mips16_reg_names (GET_OP (l, RY))); 1561 break; 1562 1563 case 'x': 1564 case 'v': 1565 infprintf (is, "%s", mips16_reg_names (GET_OP (l, RX))); 1566 break; 1567 1568 case 'z': 1569 infprintf (is, "%s", mips16_reg_names (GET_OP (l, RZ))); 1570 break; 1571 1572 case 'Z': 1573 infprintf (is, "%s", mips16_reg_names (GET_OP (l, MOVE32Z))); 1574 break; 1575 1576 case '0': 1577 infprintf (is, "%s", mips_gpr_names[0]); 1578 break; 1579 1580 case 'S': 1581 infprintf (is, "%s", mips_gpr_names[29]); 1582 break; 1583 1584 case 'P': 1585 infprintf (is, "$pc"); 1586 break; 1587 1588 case 'R': 1589 infprintf (is, "%s", mips_gpr_names[31]); 1590 break; 1591 1592 case 'X': 1593 infprintf (is, "%s", mips_gpr_names[GET_OP (l, REGR32)]); 1594 break; 1595 1596 case 'Y': 1597 infprintf (is, "%s", mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]); 1598 break; 1599 1600 case '<': 1601 case '>': 1602 case '[': 1603 case ']': 1604 case '4': 1605 case '5': 1606 case 'H': 1607 case 'W': 1608 case 'D': 1609 case 'j': 1610 case '6': 1611 case '8': 1612 case 'V': 1613 case 'C': 1614 case 'U': 1615 case 'k': 1616 case 'K': 1617 case 'p': 1618 case 'q': 1619 case 'A': 1620 case 'B': 1621 case 'E': 1622 { 1623 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch; 1624 1625 shift = 0; 1626 signedp = 0; 1627 extbits = 16; 1628 pcrel = 0; 1629 extu = 0; 1630 branch = 0; 1631 switch (type) 1632 { 1633 case '<': 1634 nbits = 3; 1635 immed = GET_OP (l, RZ); 1636 extbits = 5; 1637 extu = 1; 1638 break; 1639 case '>': 1640 nbits = 3; 1641 immed = GET_OP (l, RX); 1642 extbits = 5; 1643 extu = 1; 1644 break; 1645 case '[': 1646 nbits = 3; 1647 immed = GET_OP (l, RZ); 1648 extbits = 6; 1649 extu = 1; 1650 break; 1651 case ']': 1652 nbits = 3; 1653 immed = GET_OP (l, RX); 1654 extbits = 6; 1655 extu = 1; 1656 break; 1657 case '4': 1658 nbits = 4; 1659 immed = GET_OP (l, IMM4); 1660 signedp = 1; 1661 extbits = 15; 1662 break; 1663 case '5': 1664 nbits = 5; 1665 immed = GET_OP (l, IMM5); 1666 info->insn_type = dis_dref; 1667 info->data_size = 1; 1668 break; 1669 case 'H': 1670 nbits = 5; 1671 shift = 1; 1672 immed = GET_OP (l, IMM5); 1673 info->insn_type = dis_dref; 1674 info->data_size = 2; 1675 break; 1676 case 'W': 1677 nbits = 5; 1678 shift = 2; 1679 immed = GET_OP (l, IMM5); 1680 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0 1681 && (op->pinfo & MIPS16_INSN_READ_SP) == 0) 1682 { 1683 info->insn_type = dis_dref; 1684 info->data_size = 4; 1685 } 1686 break; 1687 case 'D': 1688 nbits = 5; 1689 shift = 3; 1690 immed = GET_OP (l, IMM5); 1691 info->insn_type = dis_dref; 1692 info->data_size = 8; 1693 break; 1694 case 'j': 1695 nbits = 5; 1696 immed = GET_OP (l, IMM5); 1697 signedp = 1; 1698 break; 1699 case '6': 1700 nbits = 6; 1701 immed = GET_OP (l, IMM6); 1702 break; 1703 case '8': 1704 nbits = 8; 1705 immed = GET_OP (l, IMM8); 1706 break; 1707 case 'V': 1708 nbits = 8; 1709 shift = 2; 1710 immed = GET_OP (l, IMM8); 1711 /* FIXME: This might be lw, or it might be addiu to $sp or 1712 $pc. We assume it's load. */ 1713 info->insn_type = dis_dref; 1714 info->data_size = 4; 1715 break; 1716 case 'C': 1717 nbits = 8; 1718 shift = 3; 1719 immed = GET_OP (l, IMM8); 1720 info->insn_type = dis_dref; 1721 info->data_size = 8; 1722 break; 1723 case 'U': 1724 nbits = 8; 1725 immed = GET_OP (l, IMM8); 1726 extu = 1; 1727 break; 1728 case 'k': 1729 nbits = 8; 1730 immed = GET_OP (l, IMM8); 1731 signedp = 1; 1732 break; 1733 case 'K': 1734 nbits = 8; 1735 shift = 3; 1736 immed = GET_OP (l, IMM8); 1737 signedp = 1; 1738 break; 1739 case 'p': 1740 nbits = 8; 1741 immed = GET_OP (l, IMM8); 1742 signedp = 1; 1743 pcrel = 1; 1744 branch = 1; 1745 break; 1746 case 'q': 1747 nbits = 11; 1748 immed = GET_OP (l, IMM11); 1749 signedp = 1; 1750 pcrel = 1; 1751 branch = 1; 1752 break; 1753 case 'A': 1754 nbits = 8; 1755 shift = 2; 1756 immed = GET_OP (l, IMM8); 1757 pcrel = 1; 1758 /* FIXME: This can be lw or la. We assume it is lw. */ 1759 info->insn_type = dis_dref; 1760 info->data_size = 4; 1761 break; 1762 case 'B': 1763 nbits = 5; 1764 shift = 3; 1765 immed = GET_OP (l, IMM5); 1766 pcrel = 1; 1767 info->insn_type = dis_dref; 1768 info->data_size = 8; 1769 break; 1770 case 'E': 1771 nbits = 5; 1772 shift = 2; 1773 immed = GET_OP (l, IMM5); 1774 pcrel = 1; 1775 break; 1776 default: 1777 abort (); 1778 } 1779 1780 if (! use_extend) 1781 { 1782 if (signedp && immed >= (1 << (nbits - 1))) 1783 immed -= 1 << nbits; 1784 immed <<= shift; 1785 if ((type == '<' || type == '>' || type == '[' || type == ']') 1786 && immed == 0) 1787 immed = 8; 1788 } 1789 else 1790 { 1791 if (extbits == 16) 1792 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0); 1793 else if (extbits == 15) 1794 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0); 1795 else 1796 immed = ((extend >> 6) & 0x1f) | (extend & 0x20); 1797 immed &= (1 << extbits) - 1; 1798 if (! extu && immed >= (1 << (extbits - 1))) 1799 immed -= 1 << extbits; 1800 } 1801 1802 if (! pcrel) 1803 infprintf (is, "%d", immed); 1804 else 1805 { 1806 bfd_vma baseaddr; 1807 1808 if (branch) 1809 { 1810 immed *= 2; 1811 baseaddr = memaddr + 2; 1812 } 1813 else if (use_extend) 1814 baseaddr = memaddr - 2; 1815 else 1816 { 1817 int status; 1818 bfd_byte buffer[2]; 1819 1820 baseaddr = memaddr; 1821 1822 /* If this instruction is in the delay slot of a jr 1823 instruction, the base address is the address of the 1824 jr instruction. If it is in the delay slot of jalr 1825 instruction, the base address is the address of the 1826 jalr instruction. This test is unreliable: we have 1827 no way of knowing whether the previous word is 1828 instruction or data. */ 1829 status = (*info->read_memory_func) (memaddr - 4, buffer, 2, 1830 info); 1831 if (status == 0 1832 && (((info->endian == BFD_ENDIAN_BIG 1833 ? bfd_getb16 (buffer) 1834 : bfd_getl16 (buffer)) 1835 & 0xf800) == 0x1800)) 1836 baseaddr = memaddr - 4; 1837 else 1838 { 1839 status = (*info->read_memory_func) (memaddr - 2, buffer, 1840 2, info); 1841 if (status == 0 1842 && (((info->endian == BFD_ENDIAN_BIG 1843 ? bfd_getb16 (buffer) 1844 : bfd_getl16 (buffer)) 1845 & 0xf81f) == 0xe800)) 1846 baseaddr = memaddr - 2; 1847 } 1848 } 1849 info->target = (baseaddr & ~((1 << shift) - 1)) + immed; 1850 if (pcrel && branch 1851 && info->flavour == bfd_target_unknown_flavour) 1852 /* For gdb disassembler, maintain odd address. */ 1853 info->target |= 1; 1854 (*info->print_address_func) (info->target, info); 1855 } 1856 } 1857 break; 1858 1859 case 'a': 1860 { 1861 int jalx = l & 0x400; 1862 1863 if (! use_extend) 1864 extend = 0; 1865 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2); 1866 if (!jalx && info->flavour == bfd_target_unknown_flavour) 1867 /* For gdb disassembler, maintain odd address. */ 1868 l |= 1; 1869 } 1870 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l; 1871 (*info->print_address_func) (info->target, info); 1872 break; 1873 1874 case 'l': 1875 case 'L': 1876 { 1877 int need_comma, amask, smask; 1878 1879 need_comma = 0; 1880 1881 l = GET_OP (l, IMM6); 1882 1883 amask = (l >> 3) & 7; 1884 1885 if (amask > 0 && amask < 5) 1886 { 1887 infprintf (is, "%s", mips_gpr_names[4]); 1888 if (amask > 1) 1889 infprintf (is, "-%s", mips_gpr_names[amask + 3]); 1890 need_comma = 1; 1891 } 1892 1893 smask = (l >> 1) & 3; 1894 if (smask == 3) 1895 { 1896 infprintf (is, "%s??", need_comma ? "," : ""); 1897 need_comma = 1; 1898 } 1899 else if (smask > 0) 1900 { 1901 infprintf (is, "%s%s", need_comma ? "," : "", mips_gpr_names[16]); 1902 if (smask > 1) 1903 infprintf (is, "-%s", mips_gpr_names[smask + 15]); 1904 need_comma = 1; 1905 } 1906 1907 if (l & 1) 1908 { 1909 infprintf (is, "%s%s", need_comma ? "," : "", mips_gpr_names[31]); 1910 need_comma = 1; 1911 } 1912 1913 if (amask == 5 || amask == 6) 1914 { 1915 infprintf (is, "%s$f0", need_comma ? "," : ""); 1916 if (amask == 6) 1917 infprintf (is, "-$f1"); 1918 } 1919 } 1920 break; 1921 1922 case 'm': 1923 case 'M': 1924 /* MIPS16e save/restore. */ 1925 { 1926 int need_comma = 0; 1927 int amask, args, statics; 1928 int nsreg, smask; 1929 int framesz; 1930 int i, j; 1931 1932 l = l & 0x7f; 1933 if (use_extend) 1934 l |= extend << 16; 1935 1936 amask = (l >> 16) & 0xf; 1937 if (amask == MIPS16_ALL_ARGS) 1938 { 1939 args = 4; 1940 statics = 0; 1941 } 1942 else if (amask == MIPS16_ALL_STATICS) 1943 { 1944 args = 0; 1945 statics = 4; 1946 } 1947 else 1948 { 1949 args = amask >> 2; 1950 statics = amask & 3; 1951 } 1952 1953 if (args > 0) { 1954 infprintf (is, "%s", mips_gpr_names[4]); 1955 if (args > 1) 1956 infprintf (is, "-%s", mips_gpr_names[4 + args - 1]); 1957 need_comma = 1; 1958 } 1959 1960 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8; 1961 if (framesz == 0 && !use_extend) 1962 framesz = 128; 1963 1964 infprintf (is, "%s%d", need_comma ? "," : "", framesz); 1965 1966 if (l & 0x40) /* $ra */ 1967 infprintf (is, ",%s", mips_gpr_names[31]); 1968 1969 nsreg = (l >> 24) & 0x7; 1970 smask = 0; 1971 if (l & 0x20) /* $s0 */ 1972 smask |= 1 << 0; 1973 if (l & 0x10) /* $s1 */ 1974 smask |= 1 << 1; 1975 if (nsreg > 0) /* $s2-$s8 */ 1976 smask |= ((1 << nsreg) - 1) << 2; 1977 1978 /* Find first set static reg bit. */ 1979 for (i = 0; i < 9; i++) 1980 { 1981 if (smask & (1 << i)) 1982 { 1983 infprintf (is, ",%s", mips_gpr_names[i == 8 ? 30 : (16 + i)]); 1984 /* Skip over string of set bits. */ 1985 for (j = i; smask & (2 << j); j++) 1986 continue; 1987 if (j > i) 1988 infprintf (is, "-%s", mips_gpr_names[j == 8 ? 30 : (16 + j)]); 1989 i = j + 1; 1990 } 1991 } 1992 1993 /* Statics $ax - $a3. */ 1994 if (statics == 1) 1995 infprintf (is, ",%s", mips_gpr_names[7]); 1996 else if (statics > 0) 1997 infprintf (is, ",%s-%s", 1998 mips_gpr_names[7 - statics + 1], 1999 mips_gpr_names[7]); 2000 } 2001 break; 2002 2003 default: 2004 /* xgettext:c-format */ 2005 infprintf (is, 2006 _("# internal disassembler error, " 2007 "unrecognised modifier (%c)"), 2008 type); 2009 abort (); 2010 } 2011 } 2012 2013 /* Disassemble mips16 instructions. */ 2014 2015 static int 2016 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) 2017 { 2018 const fprintf_ftype infprintf = info->fprintf_func; 2019 int status; 2020 bfd_byte buffer[2]; 2021 int length; 2022 int insn; 2023 bfd_boolean use_extend; 2024 int extend = 0; 2025 const struct mips_opcode *op, *opend; 2026 void *is = info->stream; 2027 2028 info->bytes_per_chunk = 2; 2029 info->display_endian = info->endian; 2030 info->insn_info_valid = 1; 2031 info->branch_delay_insns = 0; 2032 info->data_size = 0; 2033 info->insn_type = dis_nonbranch; 2034 info->target = 0; 2035 info->target2 = 0; 2036 2037 status = (*info->read_memory_func) (memaddr, buffer, 2, info); 2038 if (status != 0) 2039 { 2040 (*info->memory_error_func) (status, memaddr, info); 2041 return -1; 2042 } 2043 2044 length = 2; 2045 2046 if (info->endian == BFD_ENDIAN_BIG) 2047 insn = bfd_getb16 (buffer); 2048 else 2049 insn = bfd_getl16 (buffer); 2050 2051 /* Handle the extend opcode specially. */ 2052 use_extend = FALSE; 2053 if ((insn & 0xf800) == 0xf000) 2054 { 2055 use_extend = TRUE; 2056 extend = insn & 0x7ff; 2057 2058 memaddr += 2; 2059 2060 status = (*info->read_memory_func) (memaddr, buffer, 2, info); 2061 if (status != 0) 2062 { 2063 infprintf (is, "extend 0x%x", (unsigned int) extend); 2064 (*info->memory_error_func) (status, memaddr, info); 2065 return -1; 2066 } 2067 2068 if (info->endian == BFD_ENDIAN_BIG) 2069 insn = bfd_getb16 (buffer); 2070 else 2071 insn = bfd_getl16 (buffer); 2072 2073 /* Check for an extend opcode followed by an extend opcode. */ 2074 if ((insn & 0xf800) == 0xf000) 2075 { 2076 infprintf (is, "extend 0x%x", (unsigned int) extend); 2077 info->insn_type = dis_noninsn; 2078 return length; 2079 } 2080 2081 length += 2; 2082 } 2083 2084 /* FIXME: Should probably use a hash table on the major opcode here. */ 2085 2086 opend = mips16_opcodes + bfd_mips16_num_opcodes; 2087 for (op = mips16_opcodes; op < opend; op++) 2088 { 2089 if (op->pinfo != INSN_MACRO 2090 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) 2091 && (insn & op->mask) == op->match) 2092 { 2093 const char *s; 2094 2095 if (strchr (op->args, 'a') != NULL) 2096 { 2097 if (use_extend) 2098 { 2099 infprintf (is, "extend 0x%x", (unsigned int) extend); 2100 info->insn_type = dis_noninsn; 2101 return length - 2; 2102 } 2103 2104 use_extend = FALSE; 2105 2106 memaddr += 2; 2107 2108 status = (*info->read_memory_func) (memaddr, buffer, 2, 2109 info); 2110 if (status == 0) 2111 { 2112 use_extend = TRUE; 2113 if (info->endian == BFD_ENDIAN_BIG) 2114 extend = bfd_getb16 (buffer); 2115 else 2116 extend = bfd_getl16 (buffer); 2117 length += 2; 2118 } 2119 } 2120 2121 infprintf (is, "%s", op->name); 2122 if (op->args[0] != '\0') 2123 infprintf (is, "\t"); 2124 2125 for (s = op->args; *s != '\0'; s++) 2126 { 2127 if (*s == ',' 2128 && s[1] == 'w' 2129 && GET_OP (insn, RX) == GET_OP (insn, RY)) 2130 { 2131 /* Skip the register and the comma. */ 2132 ++s; 2133 continue; 2134 } 2135 if (*s == ',' 2136 && s[1] == 'v' 2137 && GET_OP (insn, RZ) == GET_OP (insn, RX)) 2138 { 2139 /* Skip the register and the comma. */ 2140 ++s; 2141 continue; 2142 } 2143 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr, 2144 info); 2145 } 2146 2147 /* Figure out branch instruction type and delay slot information. */ 2148 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) 2149 info->branch_delay_insns = 1; 2150 if ((op->pinfo & (INSN_UNCOND_BRANCH_DELAY 2151 | MIPS16_INSN_UNCOND_BRANCH)) != 0) 2152 { 2153 if ((op->pinfo & INSN_WRITE_GPR_31) != 0) 2154 info->insn_type = dis_jsr; 2155 else 2156 info->insn_type = dis_branch; 2157 } 2158 else if ((op->pinfo & MIPS16_INSN_COND_BRANCH) != 0) 2159 info->insn_type = dis_condbranch; 2160 2161 return length; 2162 } 2163 } 2164 #undef GET_OP_S 2165 #undef GET_OP 2166 2167 if (use_extend) 2168 infprintf (is, "0x%x", extend | 0xf000); 2169 infprintf (is, "0x%x", insn); 2170 info->insn_type = dis_noninsn; 2171 2172 return length; 2173 } 2174 2175 /* Disassemble microMIPS instructions. */ 2176 2177 static int 2178 print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info) 2179 { 2180 const fprintf_ftype infprintf = info->fprintf_func; 2181 const struct mips_opcode *op, *opend; 2182 unsigned int lsb, msbd, msb; 2183 void *is = info->stream; 2184 unsigned int regno; 2185 bfd_byte buffer[2]; 2186 int lastregno = 0; 2187 int higher; 2188 int length; 2189 int status; 2190 int delta; 2191 int immed; 2192 int insn; 2193 2194 lsb = 0; 2195 2196 info->bytes_per_chunk = 2; 2197 info->display_endian = info->endian; 2198 info->insn_info_valid = 1; 2199 info->branch_delay_insns = 0; 2200 info->data_size = 0; 2201 info->insn_type = dis_nonbranch; 2202 info->target = 0; 2203 info->target2 = 0; 2204 2205 status = (*info->read_memory_func) (memaddr, buffer, 2, info); 2206 if (status != 0) 2207 { 2208 (*info->memory_error_func) (status, memaddr, info); 2209 return -1; 2210 } 2211 2212 length = 2; 2213 2214 if (info->endian == BFD_ENDIAN_BIG) 2215 insn = bfd_getb16 (buffer); 2216 else 2217 insn = bfd_getl16 (buffer); 2218 2219 if ((insn & 0xfc00) == 0x7c00) 2220 { 2221 /* This is a 48-bit microMIPS instruction. */ 2222 higher = insn; 2223 2224 status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info); 2225 if (status != 0) 2226 { 2227 infprintf (is, "micromips 0x%x", higher); 2228 (*info->memory_error_func) (status, memaddr + 2, info); 2229 return -1; 2230 } 2231 if (info->endian == BFD_ENDIAN_BIG) 2232 insn = bfd_getb16 (buffer); 2233 else 2234 insn = bfd_getl16 (buffer); 2235 higher = (higher << 16) | insn; 2236 2237 status = (*info->read_memory_func) (memaddr + 4, buffer, 2, info); 2238 if (status != 0) 2239 { 2240 infprintf (is, "micromips 0x%x", higher); 2241 (*info->memory_error_func) (status, memaddr + 4, info); 2242 return -1; 2243 } 2244 if (info->endian == BFD_ENDIAN_BIG) 2245 insn = bfd_getb16 (buffer); 2246 else 2247 insn = bfd_getl16 (buffer); 2248 infprintf (is, "0x%x%04x (48-bit insn)", higher, insn); 2249 2250 info->insn_type = dis_noninsn; 2251 return 6; 2252 } 2253 else if ((insn & 0x1c00) == 0x0000 || (insn & 0x1000) == 0x1000) 2254 { 2255 /* This is a 32-bit microMIPS instruction. */ 2256 higher = insn; 2257 2258 status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info); 2259 if (status != 0) 2260 { 2261 infprintf (is, "micromips 0x%x", higher); 2262 (*info->memory_error_func) (status, memaddr + 2, info); 2263 return -1; 2264 } 2265 2266 if (info->endian == BFD_ENDIAN_BIG) 2267 insn = bfd_getb16 (buffer); 2268 else 2269 insn = bfd_getl16 (buffer); 2270 2271 insn = insn | (higher << 16); 2272 2273 length += 2; 2274 } 2275 2276 /* FIXME: Should probably use a hash table on the major opcode here. */ 2277 2278 #define GET_OP(insn, field) \ 2279 (((insn) >> MICROMIPSOP_SH_##field) & MICROMIPSOP_MASK_##field) 2280 #define GET_OP_S(insn, field) \ 2281 ((GET_OP (insn, field) ^ ((MICROMIPSOP_MASK_##field >> 1) + 1)) \ 2282 - ((MICROMIPSOP_MASK_##field >> 1) + 1)) 2283 opend = micromips_opcodes + bfd_micromips_num_opcodes; 2284 for (op = micromips_opcodes; op < opend; op++) 2285 { 2286 if (op->pinfo != INSN_MACRO 2287 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) 2288 && (insn & op->mask) == op->match 2289 && ((length == 2 && (op->mask & 0xffff0000) == 0) 2290 || (length == 4 && (op->mask & 0xffff0000) != 0))) 2291 { 2292 const char *s; 2293 2294 infprintf (is, "%s", op->name); 2295 if (op->args[0] != '\0') 2296 infprintf (is, "\t"); 2297 2298 for (s = op->args; *s != '\0'; s++) 2299 { 2300 switch (*s) 2301 { 2302 case ',': 2303 case '(': 2304 case ')': 2305 infprintf (is, "%c", *s); 2306 break; 2307 2308 case '.': 2309 infprintf (is, "%d", GET_OP_S (insn, OFFSET10)); 2310 break; 2311 2312 case '1': 2313 infprintf (is, "0x%x", GET_OP (insn, STYPE)); 2314 break; 2315 2316 case '2': 2317 infprintf (is, "0x%x", GET_OP (insn, BP)); 2318 break; 2319 2320 case '3': 2321 infprintf (is, "0x%x", GET_OP (insn, SA3)); 2322 break; 2323 2324 case '4': 2325 infprintf (is, "0x%x", GET_OP (insn, SA4)); 2326 break; 2327 2328 case '5': 2329 infprintf (is, "0x%x", GET_OP (insn, IMM8)); 2330 break; 2331 2332 case '6': 2333 infprintf (is, "0x%x", GET_OP (insn, RS)); 2334 break; 2335 2336 case '7': 2337 infprintf (is, "$ac%d", GET_OP (insn, DSPACC)); 2338 break; 2339 2340 case '8': 2341 infprintf (is, "0x%x", GET_OP (insn, WRDSP)); 2342 break; 2343 2344 case '0': /* DSP 6-bit signed immediate in bit 16. */ 2345 delta = (GET_OP (insn, DSPSFT) ^ 0x20) - 0x20; 2346 infprintf (is, "%d", delta); 2347 break; 2348 2349 case '<': 2350 infprintf (is, "0x%x", GET_OP (insn, SHAMT)); 2351 break; 2352 2353 case '\\': 2354 infprintf (is, "0x%x", GET_OP (insn, 3BITPOS)); 2355 break; 2356 2357 case '^': 2358 infprintf (is, "0x%x", GET_OP (insn, RD)); 2359 break; 2360 2361 case '|': 2362 infprintf (is, "0x%x", GET_OP (insn, TRAP)); 2363 break; 2364 2365 case '~': 2366 infprintf (is, "%d", GET_OP_S (insn, OFFSET12)); 2367 break; 2368 2369 case 'a': 2370 if (strcmp (op->name, "jalx") == 0) 2371 info->target = (((memaddr + 4) & ~(bfd_vma) 0x0fffffff) 2372 | (GET_OP (insn, TARGET) << 2)); 2373 else 2374 info->target = (((memaddr + 4) & ~(bfd_vma) 0x07ffffff) 2375 | (GET_OP (insn, TARGET) << 1)); 2376 /* For gdb disassembler, force odd address on jalx. */ 2377 if (info->flavour == bfd_target_unknown_flavour 2378 && strcmp (op->name, "jalx") == 0) 2379 info->target |= 1; 2380 (*info->print_address_func) (info->target, info); 2381 break; 2382 2383 case 'b': 2384 case 'r': 2385 case 's': 2386 case 'v': 2387 infprintf (is, "%s", mips_gpr_names[GET_OP (insn, RS)]); 2388 break; 2389 2390 case 'c': 2391 infprintf (is, "0x%x", GET_OP (insn, CODE)); 2392 break; 2393 2394 case 'd': 2395 infprintf (is, "%s", mips_gpr_names[GET_OP (insn, RD)]); 2396 break; 2397 2398 case 'h': 2399 infprintf (is, "0x%x", GET_OP (insn, PREFX)); 2400 break; 2401 2402 case 'i': 2403 case 'u': 2404 infprintf (is, "0x%x", GET_OP (insn, IMMEDIATE)); 2405 break; 2406 2407 case 'j': /* Same as i, but sign-extended. */ 2408 case 'o': 2409 infprintf (is, "%d", GET_OP_S (insn, DELTA)); 2410 break; 2411 2412 case 'k': 2413 infprintf (is, "0x%x", GET_OP (insn, CACHE)); 2414 break; 2415 2416 case 'n': 2417 { 2418 int s_reg_encode; 2419 2420 immed = GET_OP (insn, RT); 2421 s_reg_encode = immed & 0xf; 2422 if (s_reg_encode != 0) 2423 { 2424 if (s_reg_encode == 1) 2425 infprintf (is, "%s", mips_gpr_names[16]); 2426 else if (s_reg_encode < 9) 2427 infprintf (is, "%s-%s", 2428 mips_gpr_names[16], 2429 mips_gpr_names[15 + s_reg_encode]); 2430 else if (s_reg_encode == 9) 2431 infprintf (is, "%s-%s,%s", 2432 mips_gpr_names[16], 2433 mips_gpr_names[23], 2434 mips_gpr_names[30]); 2435 else 2436 infprintf (is, "UNKNOWN"); 2437 } 2438 2439 if (immed & 0x10) /* For ra. */ 2440 { 2441 if (s_reg_encode == 0) 2442 infprintf (is, "%s", mips_gpr_names[31]); 2443 else 2444 infprintf (is, ",%s", mips_gpr_names[31]); 2445 } 2446 break; 2447 } 2448 2449 case 'p': 2450 /* Sign-extend the displacement. */ 2451 delta = GET_OP_S (insn, DELTA); 2452 info->target = (delta << 1) + memaddr + length; 2453 (*info->print_address_func) (info->target, info); 2454 break; 2455 2456 case 'q': 2457 infprintf (is, "0x%x", GET_OP (insn, CODE2)); 2458 break; 2459 2460 case 't': 2461 case 'w': 2462 infprintf (is, "%s", mips_gpr_names[GET_OP (insn, RT)]); 2463 break; 2464 2465 case 'y': 2466 infprintf (is, "%s", mips_gpr_names[GET_OP (insn, RS3)]); 2467 break; 2468 2469 case 'z': 2470 infprintf (is, "%s", mips_gpr_names[0]); 2471 break; 2472 2473 case '@': /* DSP 10-bit signed immediate in bit 16. */ 2474 delta = (GET_OP (insn, IMM10) ^ 0x200) - 0x200; 2475 infprintf (is, "%d", delta); 2476 break; 2477 2478 case 'B': 2479 infprintf (is, "0x%x", GET_OP (insn, CODE10)); 2480 break; 2481 2482 case 'C': 2483 infprintf (is, "0x%x", GET_OP (insn, COPZ)); 2484 break; 2485 2486 case 'D': 2487 infprintf (is, "%s", mips_fpr_names[GET_OP (insn, FD)]); 2488 break; 2489 2490 case 'E': 2491 /* Coprocessor register for lwcN instructions, et al. 2492 2493 Note that there is no load/store cp0 instructions, and 2494 that FPU (cp1) instructions disassemble this field using 2495 'T' format. Therefore, until we gain understanding of 2496 cp2 register names, we can simply print the register 2497 numbers. */ 2498 infprintf (is, "$%d", GET_OP (insn, RT)); 2499 break; 2500 2501 case 'G': 2502 /* Coprocessor register for mtcN instructions, et al. Note 2503 that FPU (cp1) instructions disassemble this field using 2504 'S' format. Therefore, we only need to worry about cp0, 2505 cp2, and cp3. 2506 The microMIPS encoding does not have a coprocessor 2507 identifier field as such, so we must work out the 2508 coprocessor number by looking at the opcode. */ 2509 switch (insn 2510 & ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT) 2511 | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS))) 2512 { 2513 case 0x000000fc: /* mfc0 */ 2514 case 0x000002fc: /* mtc0 */ 2515 case 0x580000fc: /* dmfc0 */ 2516 case 0x580002fc: /* dmtc0 */ 2517 infprintf (is, "%s", mips_cp0_names[GET_OP (insn, RS)]); 2518 break; 2519 default: 2520 infprintf (is, "$%d", GET_OP (insn, RS)); 2521 break; 2522 } 2523 break; 2524 2525 case 'H': 2526 infprintf (is, "%d", GET_OP (insn, SEL)); 2527 break; 2528 2529 case 'K': 2530 infprintf (is, "%s", mips_hwr_names[GET_OP (insn, RS)]); 2531 break; 2532 2533 case 'M': 2534 infprintf (is, "$fcc%d", GET_OP (insn, CCC)); 2535 break; 2536 2537 case 'N': 2538 infprintf (is, 2539 (op->pinfo & (FP_D | FP_S)) != 0 2540 ? "$fcc%d" : "$cc%d", 2541 GET_OP (insn, BCC)); 2542 break; 2543 2544 case 'R': 2545 infprintf (is, "%s", mips_fpr_names[GET_OP (insn, FR)]); 2546 break; 2547 2548 case 'S': 2549 case 'V': 2550 infprintf (is, "%s", mips_fpr_names[GET_OP (insn, FS)]); 2551 break; 2552 2553 case 'T': 2554 infprintf (is, "%s", mips_fpr_names[GET_OP (insn, FT)]); 2555 break; 2556 2557 case '+': 2558 /* Extension character; switch for second char. */ 2559 s++; 2560 switch (*s) 2561 { 2562 case 'A': 2563 lsb = GET_OP (insn, EXTLSB); 2564 infprintf (is, "0x%x", lsb); 2565 break; 2566 2567 case 'B': 2568 msb = GET_OP (insn, INSMSB); 2569 infprintf (is, "0x%x", msb - lsb + 1); 2570 break; 2571 2572 case 'C': 2573 case 'H': 2574 msbd = GET_OP (insn, EXTMSBD); 2575 infprintf (is, "0x%x", msbd + 1); 2576 break; 2577 2578 case 'D': 2579 { 2580 const struct mips_cp0sel_name *n; 2581 unsigned int cp0reg, sel; 2582 2583 cp0reg = GET_OP (insn, RS); 2584 sel = GET_OP (insn, SEL); 2585 2586 /* CP0 register including 'sel' code for mtcN 2587 (et al.), to be printed textually if known. 2588 If not known, print both CP0 register name and 2589 sel numerically since CP0 register with sel 0 may 2590 have a name unrelated to register being printed. */ 2591 n = lookup_mips_cp0sel_name (mips_cp0sel_names, 2592 mips_cp0sel_names_len, 2593 cp0reg, sel); 2594 if (n != NULL) 2595 infprintf (is, "%s", n->name); 2596 else 2597 infprintf (is, "$%d,%d", cp0reg, sel); 2598 break; 2599 } 2600 2601 case 'E': 2602 lsb = GET_OP (insn, EXTLSB) + 32; 2603 infprintf (is, "0x%x", lsb); 2604 break; 2605 2606 case 'F': 2607 msb = GET_OP (insn, INSMSB) + 32; 2608 infprintf (is, "0x%x", msb - lsb + 1); 2609 break; 2610 2611 case 'G': 2612 msbd = GET_OP (insn, EXTMSBD) + 32; 2613 infprintf (is, "0x%x", msbd + 1); 2614 break; 2615 2616 default: 2617 /* xgettext:c-format */ 2618 infprintf (is, 2619 _("# internal disassembler error, " 2620 "unrecognized modifier (+%c)"), 2621 *s); 2622 abort (); 2623 } 2624 break; 2625 2626 case 'm': 2627 /* Extension character; switch for second char. */ 2628 s++; 2629 switch (*s) 2630 { 2631 case 'a': /* global pointer. */ 2632 infprintf (is, "%s", mips_gpr_names[28]); 2633 break; 2634 2635 case 'b': 2636 regno = micromips_to_32_reg_b_map[GET_OP (insn, MB)]; 2637 infprintf (is, "%s", mips_gpr_names[regno]); 2638 break; 2639 2640 case 'c': 2641 regno = micromips_to_32_reg_c_map[GET_OP (insn, MC)]; 2642 infprintf (is, "%s", mips_gpr_names[regno]); 2643 break; 2644 2645 case 'd': 2646 regno = micromips_to_32_reg_d_map[GET_OP (insn, MD)]; 2647 infprintf (is, "%s", mips_gpr_names[regno]); 2648 break; 2649 2650 case 'e': 2651 regno = micromips_to_32_reg_e_map[GET_OP (insn, ME)]; 2652 infprintf (is, "%s", mips_gpr_names[regno]); 2653 break; 2654 2655 case 'f': 2656 /* Save lastregno for "mt" to print out later. */ 2657 lastregno = micromips_to_32_reg_f_map[GET_OP (insn, MF)]; 2658 infprintf (is, "%s", mips_gpr_names[lastregno]); 2659 break; 2660 2661 case 'g': 2662 regno = micromips_to_32_reg_g_map[GET_OP (insn, MG)]; 2663 infprintf (is, "%s", mips_gpr_names[regno]); 2664 break; 2665 2666 case 'h': 2667 regno = micromips_to_32_reg_h_map[GET_OP (insn, MH)]; 2668 infprintf (is, "%s", mips_gpr_names[regno]); 2669 break; 2670 2671 case 'i': 2672 regno = micromips_to_32_reg_i_map[GET_OP (insn, MI)]; 2673 infprintf (is, "%s", mips_gpr_names[regno]); 2674 break; 2675 2676 case 'j': 2677 infprintf (is, "%s", mips_gpr_names[GET_OP (insn, MJ)]); 2678 break; 2679 2680 case 'l': 2681 regno = micromips_to_32_reg_l_map[GET_OP (insn, ML)]; 2682 infprintf (is, "%s", mips_gpr_names[regno]); 2683 break; 2684 2685 case 'm': 2686 regno = micromips_to_32_reg_m_map[GET_OP (insn, MM)]; 2687 infprintf (is, "%s", mips_gpr_names[regno]); 2688 break; 2689 2690 case 'n': 2691 regno = micromips_to_32_reg_n_map[GET_OP (insn, MN)]; 2692 infprintf (is, "%s", mips_gpr_names[regno]); 2693 break; 2694 2695 case 'p': 2696 /* Save lastregno for "mt" to print out later. */ 2697 lastregno = GET_OP (insn, MP); 2698 infprintf (is, "%s", mips_gpr_names[lastregno]); 2699 break; 2700 2701 case 'q': 2702 regno = micromips_to_32_reg_q_map[GET_OP (insn, MQ)]; 2703 infprintf (is, "%s", mips_gpr_names[regno]); 2704 break; 2705 2706 case 'r': /* program counter. */ 2707 infprintf (is, "$pc"); 2708 break; 2709 2710 case 's': /* stack pointer. */ 2711 lastregno = 29; 2712 infprintf (is, "%s", mips_gpr_names[29]); 2713 break; 2714 2715 case 't': 2716 infprintf (is, "%s", mips_gpr_names[lastregno]); 2717 break; 2718 2719 case 'z': /* $0. */ 2720 infprintf (is, "%s", mips_gpr_names[0]); 2721 break; 2722 2723 case 'A': 2724 /* Sign-extend the immediate. */ 2725 immed = GET_OP_S (insn, IMMA) << 2; 2726 infprintf (is, "%d", immed); 2727 break; 2728 2729 case 'B': 2730 immed = micromips_imm_b_map[GET_OP (insn, IMMB)]; 2731 infprintf (is, "%d", immed); 2732 break; 2733 2734 case 'C': 2735 immed = micromips_imm_c_map[GET_OP (insn, IMMC)]; 2736 infprintf (is, "0x%x", immed); 2737 break; 2738 2739 case 'D': 2740 /* Sign-extend the displacement. */ 2741 delta = GET_OP_S (insn, IMMD); 2742 info->target = (delta << 1) + memaddr + length; 2743 (*info->print_address_func) (info->target, info); 2744 break; 2745 2746 case 'E': 2747 /* Sign-extend the displacement. */ 2748 delta = GET_OP_S (insn, IMME); 2749 info->target = (delta << 1) + memaddr + length; 2750 (*info->print_address_func) (info->target, info); 2751 break; 2752 2753 case 'F': 2754 immed = GET_OP (insn, IMMF); 2755 infprintf (is, "0x%x", immed); 2756 break; 2757 2758 case 'G': 2759 immed = (insn >> MICROMIPSOP_SH_IMMG) + 1; 2760 immed = (immed & MICROMIPSOP_MASK_IMMG) - 1; 2761 infprintf (is, "%d", immed); 2762 break; 2763 2764 case 'H': 2765 immed = GET_OP (insn, IMMH) << 1; 2766 infprintf (is, "%d", immed); 2767 break; 2768 2769 case 'I': 2770 immed = (insn >> MICROMIPSOP_SH_IMMI) + 1; 2771 immed = (immed & MICROMIPSOP_MASK_IMMI) - 1; 2772 infprintf (is, "%d", immed); 2773 break; 2774 2775 case 'J': 2776 immed = GET_OP (insn, IMMJ) << 2; 2777 infprintf (is, "%d", immed); 2778 break; 2779 2780 case 'L': 2781 immed = GET_OP (insn, IMML); 2782 infprintf (is, "%d", immed); 2783 break; 2784 2785 case 'M': 2786 immed = (insn >> MICROMIPSOP_SH_IMMM) - 1; 2787 immed = (immed & MICROMIPSOP_MASK_IMMM) + 1; 2788 infprintf (is, "%d", immed); 2789 break; 2790 2791 case 'N': 2792 immed = GET_OP (insn, IMMN); 2793 if (immed == 0) 2794 infprintf (is, "%s,%s", 2795 mips_gpr_names[16], 2796 mips_gpr_names[31]); 2797 else 2798 infprintf (is, "%s-%s,%s", 2799 mips_gpr_names[16], 2800 mips_gpr_names[16 + immed], 2801 mips_gpr_names[31]); 2802 break; 2803 2804 case 'O': 2805 immed = GET_OP (insn, IMMO); 2806 infprintf (is, "0x%x", immed); 2807 break; 2808 2809 case 'P': 2810 immed = GET_OP (insn, IMMP) << 2; 2811 infprintf (is, "%d", immed); 2812 break; 2813 2814 case 'Q': 2815 /* Sign-extend the immediate. */ 2816 immed = GET_OP_S (insn, IMMQ) << 2; 2817 infprintf (is, "%d", immed); 2818 break; 2819 2820 case 'U': 2821 immed = GET_OP (insn, IMMU) << 2; 2822 infprintf (is, "%d", immed); 2823 break; 2824 2825 case 'W': 2826 immed = GET_OP (insn, IMMW) << 2; 2827 infprintf (is, "%d", immed); 2828 break; 2829 2830 case 'X': 2831 /* Sign-extend the immediate. */ 2832 immed = GET_OP_S (insn, IMMX); 2833 infprintf (is, "%d", immed); 2834 break; 2835 2836 case 'Y': 2837 /* Sign-extend the immediate. */ 2838 immed = GET_OP_S (insn, IMMY) << 2; 2839 if ((unsigned int) (immed + 8) < 16) 2840 immed ^= 0x400; 2841 infprintf (is, "%d", immed); 2842 break; 2843 2844 default: 2845 /* xgettext:c-format */ 2846 infprintf (is, 2847 _("# internal disassembler error, " 2848 "unrecognized modifier (m%c)"), 2849 *s); 2850 abort (); 2851 } 2852 break; 2853 2854 default: 2855 /* xgettext:c-format */ 2856 infprintf (is, 2857 _("# internal disassembler error, " 2858 "unrecognized modifier (%c)"), 2859 *s); 2860 abort (); 2861 } 2862 } 2863 2864 /* Figure out instruction type and branch delay information. */ 2865 if ((op->pinfo 2866 & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY)) != 0) 2867 info->branch_delay_insns = 1; 2868 if (((op->pinfo & INSN_UNCOND_BRANCH_DELAY) 2869 | (op->pinfo2 & INSN2_UNCOND_BRANCH)) != 0) 2870 { 2871 if ((op->pinfo & (INSN_WRITE_GPR_31 | INSN_WRITE_GPR_T)) != 0) 2872 info->insn_type = dis_jsr; 2873 else 2874 info->insn_type = dis_branch; 2875 } 2876 else if (((op->pinfo & INSN_COND_BRANCH_DELAY) 2877 | (op->pinfo2 & INSN2_COND_BRANCH)) != 0) 2878 { 2879 if ((op->pinfo & INSN_WRITE_GPR_31) != 0) 2880 info->insn_type = dis_condjsr; 2881 else 2882 info->insn_type = dis_condbranch; 2883 } 2884 else if ((op->pinfo 2885 & (INSN_STORE_MEMORY | INSN_LOAD_MEMORY_DELAY)) != 0) 2886 info->insn_type = dis_dref; 2887 2888 return length; 2889 } 2890 } 2891 #undef GET_OP_S 2892 #undef GET_OP 2893 2894 infprintf (is, "0x%x", insn); 2895 info->insn_type = dis_noninsn; 2896 2897 return length; 2898 } 2899 2900 /* Return 1 if a symbol associated with the location being disassembled 2901 indicates a compressed (MIPS16 or microMIPS) mode. We iterate over 2902 all the symbols at the address being considered assuming if at least 2903 one of them indicates code compression, then such code has been 2904 genuinely produced here (other symbols could have been derived from 2905 function symbols defined elsewhere or could define data). Otherwise, 2906 return 0. */ 2907 2908 static bfd_boolean 2909 is_compressed_mode_p (struct disassemble_info *info) 2910 { 2911 elf_symbol_type *symbol; 2912 int pos; 2913 int i; 2914 2915 for (i = 0; i < info->num_symbols; i++) 2916 { 2917 pos = info->symtab_pos + i; 2918 2919 if (bfd_asymbol_flavour (info->symtab[pos]) != bfd_target_elf_flavour) 2920 continue; 2921 2922 symbol = (elf_symbol_type *) info->symtab[pos]; 2923 if ((!micromips_ase 2924 && ELF_ST_IS_MIPS16 (symbol->internal_elf_sym.st_other)) 2925 || (micromips_ase 2926 && ELF_ST_IS_MICROMIPS (symbol->internal_elf_sym.st_other))) 2927 return 1; 2928 } 2929 2930 return 0; 2931 } 2932 2933 /* In an environment where we do not know the symbol type of the 2934 instruction we are forced to assume that the low order bit of the 2935 instructions' address may mark it as a mips16 instruction. If we 2936 are single stepping, or the pc is within the disassembled function, 2937 this works. Otherwise, we need a clue. Sometimes. */ 2938 2939 static int 2940 _print_insn_mips (bfd_vma memaddr, 2941 struct disassemble_info *info, 2942 enum bfd_endian endianness) 2943 { 2944 int (*print_insn_compr) (bfd_vma, struct disassemble_info *); 2945 bfd_byte buffer[INSNLEN]; 2946 int status; 2947 2948 set_default_mips_dis_options (info); 2949 parse_mips_dis_options (info->disassembler_options); 2950 2951 if (info->mach == bfd_mach_mips16) 2952 return print_insn_mips16 (memaddr, info); 2953 if (info->mach == bfd_mach_mips_micromips) 2954 return print_insn_micromips (memaddr, info); 2955 2956 print_insn_compr = !micromips_ase ? print_insn_mips16 : print_insn_micromips; 2957 2958 #if 1 2959 /* FIXME: If odd address, this is CLEARLY a compressed instruction. */ 2960 /* Only a few tools will work this way. */ 2961 if (memaddr & 0x01) 2962 return print_insn_compr (memaddr, info); 2963 #endif 2964 2965 #if SYMTAB_AVAILABLE 2966 if (is_compressed_mode_p (info)) 2967 return print_insn_compr (memaddr, info); 2968 #endif 2969 2970 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info); 2971 if (status == 0) 2972 { 2973 int insn; 2974 2975 if (endianness == BFD_ENDIAN_BIG) 2976 insn = bfd_getb32 (buffer); 2977 else 2978 insn = bfd_getl32 (buffer); 2979 2980 return print_insn_mips (memaddr, insn, info); 2981 } 2982 else 2983 { 2984 (*info->memory_error_func) (status, memaddr, info); 2985 return -1; 2986 } 2987 } 2988 2989 int 2990 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info) 2991 { 2992 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG); 2993 } 2994 2995 int 2996 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info) 2997 { 2998 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE); 2999 } 3000 3001 void 3003 print_mips_disassembler_options (FILE *stream) 3004 { 3005 unsigned int i; 3006 3007 fprintf (stream, _("\n\ 3008 The following MIPS specific disassembler options are supported for use\n\ 3009 with the -M switch (multiple options should be separated by commas):\n")); 3010 3011 fprintf (stream, _("\n\ 3012 gpr-names=ABI Print GPR names according to specified ABI.\n\ 3013 Default: based on binary being disassembled.\n")); 3014 3015 fprintf (stream, _("\n\ 3016 fpr-names=ABI Print FPR names according to specified ABI.\n\ 3017 Default: numeric.\n")); 3018 3019 fprintf (stream, _("\n\ 3020 cp0-names=ARCH Print CP0 register names according to\n\ 3021 specified architecture.\n\ 3022 Default: based on binary being disassembled.\n")); 3023 3024 fprintf (stream, _("\n\ 3025 hwr-names=ARCH Print HWR names according to specified \n\ 3026 architecture.\n\ 3027 Default: based on binary being disassembled.\n")); 3028 3029 fprintf (stream, _("\n\ 3030 reg-names=ABI Print GPR and FPR names according to\n\ 3031 specified ABI.\n")); 3032 3033 fprintf (stream, _("\n\ 3034 reg-names=ARCH Print CP0 register and HWR names according to\n\ 3035 specified architecture.\n")); 3036 3037 fprintf (stream, _("\n\ 3038 For the options above, the following values are supported for \"ABI\":\n\ 3039 ")); 3040 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++) 3041 fprintf (stream, " %s", mips_abi_choices[i].name); 3042 fprintf (stream, _("\n")); 3043 3044 fprintf (stream, _("\n\ 3045 For the options above, The following values are supported for \"ARCH\":\n\ 3046 ")); 3047 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++) 3048 if (*mips_arch_choices[i].name != '\0') 3049 fprintf (stream, " %s", mips_arch_choices[i].name); 3050 fprintf (stream, _("\n")); 3051 3052 fprintf (stream, _("\n")); 3053 } 3054
Indexes created Mon Mar 30 00:23:01 UTC 2026