mips-dis.c revision 1.7
1 /* Print mips instructions for GDB, the GNU debugger, or for objdump. 2 Copyright (C) 1989-2018 Free Software Foundation, Inc. 3 Contributed by Nobuyuki Hikichi(hikichi (at) sra.co.jp). 4 5 This file is part of the GNU opcodes library. 6 7 This library is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 It is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; if not, write to the Free Software 19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 20 MA 02110-1301, USA. */ 21 22 #include "sysdep.h" 23 #include "disassemble.h" 24 #include "libiberty.h" 25 #include "opcode/mips.h" 26 #include "opintl.h" 27 28 /* FIXME: These are needed to figure out if the code is mips16 or 29 not. The low bit of the address is often a good indicator. No 30 symbol table is available when this code runs out in an embedded 31 system as when it is used for disassembler support in a monitor. */ 32 33 #if !defined(EMBEDDED_ENV) 34 #define SYMTAB_AVAILABLE 1 35 #include "elf-bfd.h" 36 #include "elf/mips.h" 37 #endif 38 39 /* Mips instructions are at maximum this many bytes long. */ 40 #define INSNLEN 4 41 42 43 /* FIXME: These should be shared with gdb somehow. */ 45 46 struct mips_cp0sel_name 47 { 48 unsigned int cp0reg; 49 unsigned int sel; 50 const char * const name; 51 }; 52 53 static const char * const mips_gpr_names_numeric[32] = 54 { 55 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 56 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 57 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 58 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 59 }; 60 61 static const char * const mips_gpr_names_oldabi[32] = 62 { 63 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 64 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", 65 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 66 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 67 }; 68 69 static const char * const mips_gpr_names_newabi[32] = 70 { 71 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 72 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", 73 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 74 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 75 }; 76 77 static const char * const mips_fpr_names_numeric[32] = 78 { 79 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 80 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 81 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 82 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31" 83 }; 84 85 static const char * const mips_fpr_names_32[32] = 86 { 87 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f", 88 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f", 89 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f", 90 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f" 91 }; 92 93 static const char * const mips_fpr_names_n32[32] = 94 { 95 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3", 96 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", 97 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9", 98 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13" 99 }; 100 101 static const char * const mips_fpr_names_64[32] = 102 { 103 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3", 104 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", 105 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11", 106 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7" 107 }; 108 109 static const char * const mips_cp0_names_numeric[32] = 110 { 111 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 112 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 113 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 114 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 115 }; 116 117 static const char * const mips_cp1_names_numeric[32] = 118 { 119 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 120 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 121 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 122 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 123 }; 124 125 static const char * const mips_cp0_names_r3000[32] = 126 { 127 "c0_index", "c0_random", "c0_entrylo", "$3", 128 "c0_context", "$5", "$6", "$7", 129 "c0_badvaddr", "$9", "c0_entryhi", "$11", 130 "c0_sr", "c0_cause", "c0_epc", "c0_prid", 131 "$16", "$17", "$18", "$19", 132 "$20", "$21", "$22", "$23", 133 "$24", "$25", "$26", "$27", 134 "$28", "$29", "$30", "$31", 135 }; 136 137 static const char * const mips_cp0_names_r4000[32] = 138 { 139 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 140 "c0_context", "c0_pagemask", "c0_wired", "$7", 141 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 142 "c0_sr", "c0_cause", "c0_epc", "c0_prid", 143 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 144 "c0_xcontext", "$21", "$22", "$23", 145 "$24", "$25", "c0_ecc", "c0_cacheerr", 146 "c0_taglo", "c0_taghi", "c0_errorepc", "$31", 147 }; 148 149 static const char * const mips_cp0_names_r5900[32] = 150 { 151 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 152 "c0_context", "c0_pagemask", "c0_wired", "$7", 153 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 154 "c0_sr", "c0_cause", "c0_epc", "c0_prid", 155 "c0_config", "$17", "$18", "$19", 156 "$20", "$21", "$22", "c0_badpaddr", 157 "c0_depc", "c0_perfcnt", "$26", "$27", 158 "c0_taglo", "c0_taghi", "c0_errorepc", "$31" 159 }; 160 161 static const char * const mips_cp0_names_mips3264[32] = 162 { 163 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 164 "c0_context", "c0_pagemask", "c0_wired", "$7", 165 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 166 "c0_status", "c0_cause", "c0_epc", "c0_prid", 167 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 168 "c0_xcontext", "$21", "$22", "c0_debug", 169 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", 170 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", 171 }; 172 173 static const char * const mips_cp1_names_mips3264[32] = 174 { 175 "c1_fir", "c1_ufr", "$2", "$3", 176 "c1_unfr", "$5", "$6", "$7", 177 "$8", "$9", "$10", "$11", 178 "$12", "$13", "$14", "$15", 179 "$16", "$17", "$18", "$19", 180 "$20", "$21", "$22", "$23", 181 "$24", "c1_fccr", "c1_fexr", "$27", 182 "c1_fenr", "$29", "$30", "c1_fcsr" 183 }; 184 185 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = 186 { 187 { 16, 1, "c0_config1" }, 188 { 16, 2, "c0_config2" }, 189 { 16, 3, "c0_config3" }, 190 { 18, 1, "c0_watchlo,1" }, 191 { 18, 2, "c0_watchlo,2" }, 192 { 18, 3, "c0_watchlo,3" }, 193 { 18, 4, "c0_watchlo,4" }, 194 { 18, 5, "c0_watchlo,5" }, 195 { 18, 6, "c0_watchlo,6" }, 196 { 18, 7, "c0_watchlo,7" }, 197 { 19, 1, "c0_watchhi,1" }, 198 { 19, 2, "c0_watchhi,2" }, 199 { 19, 3, "c0_watchhi,3" }, 200 { 19, 4, "c0_watchhi,4" }, 201 { 19, 5, "c0_watchhi,5" }, 202 { 19, 6, "c0_watchhi,6" }, 203 { 19, 7, "c0_watchhi,7" }, 204 { 25, 1, "c0_perfcnt,1" }, 205 { 25, 2, "c0_perfcnt,2" }, 206 { 25, 3, "c0_perfcnt,3" }, 207 { 25, 4, "c0_perfcnt,4" }, 208 { 25, 5, "c0_perfcnt,5" }, 209 { 25, 6, "c0_perfcnt,6" }, 210 { 25, 7, "c0_perfcnt,7" }, 211 { 27, 1, "c0_cacheerr,1" }, 212 { 27, 2, "c0_cacheerr,2" }, 213 { 27, 3, "c0_cacheerr,3" }, 214 { 28, 1, "c0_datalo" }, 215 { 29, 1, "c0_datahi" } 216 }; 217 218 static const char * const mips_cp0_names_mips3264r2[32] = 219 { 220 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 221 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena", 222 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 223 "c0_status", "c0_cause", "c0_epc", "c0_prid", 224 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 225 "c0_xcontext", "$21", "$22", "c0_debug", 226 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", 227 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", 228 }; 229 230 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = 231 { 232 { 4, 1, "c0_contextconfig" }, 233 { 0, 1, "c0_mvpcontrol" }, 234 { 0, 2, "c0_mvpconf0" }, 235 { 0, 3, "c0_mvpconf1" }, 236 { 1, 1, "c0_vpecontrol" }, 237 { 1, 2, "c0_vpeconf0" }, 238 { 1, 3, "c0_vpeconf1" }, 239 { 1, 4, "c0_yqmask" }, 240 { 1, 5, "c0_vpeschedule" }, 241 { 1, 6, "c0_vpeschefback" }, 242 { 2, 1, "c0_tcstatus" }, 243 { 2, 2, "c0_tcbind" }, 244 { 2, 3, "c0_tcrestart" }, 245 { 2, 4, "c0_tchalt" }, 246 { 2, 5, "c0_tccontext" }, 247 { 2, 6, "c0_tcschedule" }, 248 { 2, 7, "c0_tcschefback" }, 249 { 5, 1, "c0_pagegrain" }, 250 { 6, 1, "c0_srsconf0" }, 251 { 6, 2, "c0_srsconf1" }, 252 { 6, 3, "c0_srsconf2" }, 253 { 6, 4, "c0_srsconf3" }, 254 { 6, 5, "c0_srsconf4" }, 255 { 12, 1, "c0_intctl" }, 256 { 12, 2, "c0_srsctl" }, 257 { 12, 3, "c0_srsmap" }, 258 { 15, 1, "c0_ebase" }, 259 { 16, 1, "c0_config1" }, 260 { 16, 2, "c0_config2" }, 261 { 16, 3, "c0_config3" }, 262 { 18, 1, "c0_watchlo,1" }, 263 { 18, 2, "c0_watchlo,2" }, 264 { 18, 3, "c0_watchlo,3" }, 265 { 18, 4, "c0_watchlo,4" }, 266 { 18, 5, "c0_watchlo,5" }, 267 { 18, 6, "c0_watchlo,6" }, 268 { 18, 7, "c0_watchlo,7" }, 269 { 19, 1, "c0_watchhi,1" }, 270 { 19, 2, "c0_watchhi,2" }, 271 { 19, 3, "c0_watchhi,3" }, 272 { 19, 4, "c0_watchhi,4" }, 273 { 19, 5, "c0_watchhi,5" }, 274 { 19, 6, "c0_watchhi,6" }, 275 { 19, 7, "c0_watchhi,7" }, 276 { 23, 1, "c0_tracecontrol" }, 277 { 23, 2, "c0_tracecontrol2" }, 278 { 23, 3, "c0_usertracedata" }, 279 { 23, 4, "c0_tracebpc" }, 280 { 25, 1, "c0_perfcnt,1" }, 281 { 25, 2, "c0_perfcnt,2" }, 282 { 25, 3, "c0_perfcnt,3" }, 283 { 25, 4, "c0_perfcnt,4" }, 284 { 25, 5, "c0_perfcnt,5" }, 285 { 25, 6, "c0_perfcnt,6" }, 286 { 25, 7, "c0_perfcnt,7" }, 287 { 27, 1, "c0_cacheerr,1" }, 288 { 27, 2, "c0_cacheerr,2" }, 289 { 27, 3, "c0_cacheerr,3" }, 290 { 28, 1, "c0_datalo" }, 291 { 28, 2, "c0_taglo1" }, 292 { 28, 3, "c0_datalo1" }, 293 { 28, 4, "c0_taglo2" }, 294 { 28, 5, "c0_datalo2" }, 295 { 28, 6, "c0_taglo3" }, 296 { 28, 7, "c0_datalo3" }, 297 { 29, 1, "c0_datahi" }, 298 { 29, 2, "c0_taghi1" }, 299 { 29, 3, "c0_datahi1" }, 300 { 29, 4, "c0_taghi2" }, 301 { 29, 5, "c0_datahi2" }, 302 { 29, 6, "c0_taghi3" }, 303 { 29, 7, "c0_datahi3" }, 304 }; 305 306 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */ 307 static const char * const mips_cp0_names_sb1[32] = 308 { 309 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 310 "c0_context", "c0_pagemask", "c0_wired", "$7", 311 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 312 "c0_status", "c0_cause", "c0_epc", "c0_prid", 313 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 314 "c0_xcontext", "$21", "$22", "c0_debug", 315 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i", 316 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave", 317 }; 318 319 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = 320 { 321 { 16, 1, "c0_config1" }, 322 { 18, 1, "c0_watchlo,1" }, 323 { 19, 1, "c0_watchhi,1" }, 324 { 22, 0, "c0_perftrace" }, 325 { 23, 3, "c0_edebug" }, 326 { 25, 1, "c0_perfcnt,1" }, 327 { 25, 2, "c0_perfcnt,2" }, 328 { 25, 3, "c0_perfcnt,3" }, 329 { 25, 4, "c0_perfcnt,4" }, 330 { 25, 5, "c0_perfcnt,5" }, 331 { 25, 6, "c0_perfcnt,6" }, 332 { 25, 7, "c0_perfcnt,7" }, 333 { 26, 1, "c0_buserr_pa" }, 334 { 27, 1, "c0_cacheerr_d" }, 335 { 27, 3, "c0_cacheerr_d_pa" }, 336 { 28, 1, "c0_datalo_i" }, 337 { 28, 2, "c0_taglo_d" }, 338 { 28, 3, "c0_datalo_d" }, 339 { 29, 1, "c0_datahi_i" }, 340 { 29, 2, "c0_taghi_d" }, 341 { 29, 3, "c0_datahi_d" }, 342 }; 343 344 /* Xlr cop0 register names. */ 345 static const char * const mips_cp0_names_xlr[32] = { 346 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 347 "c0_context", "c0_pagemask", "c0_wired", "$7", 348 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 349 "c0_status", "c0_cause", "c0_epc", "c0_prid", 350 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 351 "c0_xcontext", "$21", "$22", "c0_debug", 352 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i", 353 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave", 354 }; 355 356 /* XLR's CP0 Select Registers. */ 357 358 static const struct mips_cp0sel_name mips_cp0sel_names_xlr[] = { 359 { 9, 6, "c0_extintreq" }, 360 { 9, 7, "c0_extintmask" }, 361 { 15, 1, "c0_ebase" }, 362 { 16, 1, "c0_config1" }, 363 { 16, 2, "c0_config2" }, 364 { 16, 3, "c0_config3" }, 365 { 16, 7, "c0_procid2" }, 366 { 18, 1, "c0_watchlo,1" }, 367 { 18, 2, "c0_watchlo,2" }, 368 { 18, 3, "c0_watchlo,3" }, 369 { 18, 4, "c0_watchlo,4" }, 370 { 18, 5, "c0_watchlo,5" }, 371 { 18, 6, "c0_watchlo,6" }, 372 { 18, 7, "c0_watchlo,7" }, 373 { 19, 1, "c0_watchhi,1" }, 374 { 19, 2, "c0_watchhi,2" }, 375 { 19, 3, "c0_watchhi,3" }, 376 { 19, 4, "c0_watchhi,4" }, 377 { 19, 5, "c0_watchhi,5" }, 378 { 19, 6, "c0_watchhi,6" }, 379 { 19, 7, "c0_watchhi,7" }, 380 { 25, 1, "c0_perfcnt,1" }, 381 { 25, 2, "c0_perfcnt,2" }, 382 { 25, 3, "c0_perfcnt,3" }, 383 { 25, 4, "c0_perfcnt,4" }, 384 { 25, 5, "c0_perfcnt,5" }, 385 { 25, 6, "c0_perfcnt,6" }, 386 { 25, 7, "c0_perfcnt,7" }, 387 { 27, 1, "c0_cacheerr,1" }, 388 { 27, 2, "c0_cacheerr,2" }, 389 { 27, 3, "c0_cacheerr,3" }, 390 { 28, 1, "c0_datalo" }, 391 { 29, 1, "c0_datahi" } 392 }; 393 394 static const char * const mips_hwr_names_numeric[32] = 395 { 396 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 397 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 398 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 399 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 400 }; 401 402 static const char * const mips_hwr_names_mips3264r2[32] = 403 { 404 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres", 405 "$4", "$5", "$6", "$7", 406 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 407 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 408 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 409 }; 410 411 static const char * const msa_control_names[32] = 412 { 413 "msa_ir", "msa_csr", "msa_access", "msa_save", 414 "msa_modify", "msa_request", "msa_map", "msa_unmap", 415 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 416 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 417 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 418 }; 419 420 struct mips_abi_choice 421 { 422 const char * name; 423 const char * const *gpr_names; 424 const char * const *fpr_names; 425 }; 426 427 struct mips_abi_choice mips_abi_choices[] = 428 { 429 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric }, 430 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 }, 431 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 }, 432 { "64", mips_gpr_names_newabi, mips_fpr_names_64 }, 433 }; 434 435 struct mips_arch_choice 436 { 437 const char *name; 438 int bfd_mach_valid; 439 unsigned long bfd_mach; 440 int processor; 441 int isa; 442 int ase; 443 const char * const *cp0_names; 444 const struct mips_cp0sel_name *cp0sel_names; 445 unsigned int cp0sel_names_len; 446 const char * const *cp1_names; 447 const char * const *hwr_names; 448 }; 449 450 const struct mips_arch_choice mips_arch_choices[] = 451 { 452 { "numeric", 0, 0, 0, 0, 0, 453 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 454 mips_hwr_names_numeric }, 455 456 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, 0, 457 mips_cp0_names_r3000, NULL, 0, mips_cp1_names_numeric, 458 mips_hwr_names_numeric }, 459 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, 0, 460 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 461 mips_hwr_names_numeric }, 462 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, 0, 463 mips_cp0_names_r4000, NULL, 0, mips_cp1_names_numeric, 464 mips_hwr_names_numeric }, 465 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, 0, 466 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 467 mips_hwr_names_numeric }, 468 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, 0, 469 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 470 mips_hwr_names_numeric }, 471 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, 0, 472 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 473 mips_hwr_names_numeric }, 474 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, 0, 475 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 476 mips_hwr_names_numeric }, 477 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, 0, 478 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 479 mips_hwr_names_numeric }, 480 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, 0, 481 mips_cp0_names_r4000, NULL, 0, mips_cp1_names_numeric, 482 mips_hwr_names_numeric }, 483 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, 0, 484 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 485 mips_hwr_names_numeric }, 486 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, 0, 487 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 488 mips_hwr_names_numeric }, 489 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, 0, 490 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 491 mips_hwr_names_numeric }, 492 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, 0, 493 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 494 mips_hwr_names_numeric }, 495 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, 0, 496 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 497 mips_hwr_names_numeric }, 498 { "r5900", 1, bfd_mach_mips5900, CPU_R5900, ISA_MIPS3, 0, 499 mips_cp0_names_r5900, NULL, 0, mips_cp1_names_numeric, 500 mips_hwr_names_numeric }, 501 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, 0, 502 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 503 mips_hwr_names_numeric }, 504 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0, 505 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 506 mips_hwr_names_numeric }, 507 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0, 508 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 509 mips_hwr_names_numeric }, 510 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, 0, 511 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 512 mips_hwr_names_numeric }, 513 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, 0, 514 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 515 mips_hwr_names_numeric }, 516 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, 0, 517 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 518 mips_hwr_names_numeric }, 519 { "r14000", 1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4, 0, 520 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 521 mips_hwr_names_numeric }, 522 { "r16000", 1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4, 0, 523 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 524 mips_hwr_names_numeric }, 525 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, 0, 526 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 527 mips_hwr_names_numeric }, 528 529 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs. 530 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See 531 _MIPS32 Architecture For Programmers Volume I: Introduction to the 532 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95), 533 page 1. */ 534 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32, 535 ISA_MIPS32, ASE_SMARTMIPS, 536 mips_cp0_names_mips3264, 537 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), 538 mips_cp1_names_mips3264, mips_hwr_names_numeric }, 539 540 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2, 541 ISA_MIPS32R2, 542 (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D 543 | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA), 544 mips_cp0_names_mips3264r2, 545 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 546 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, 547 548 { "mips32r3", 1, bfd_mach_mipsisa32r3, CPU_MIPS32R3, 549 ISA_MIPS32R3, 550 (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D 551 | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA), 552 mips_cp0_names_mips3264r2, 553 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 554 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, 555 556 { "mips32r5", 1, bfd_mach_mipsisa32r5, CPU_MIPS32R5, 557 ISA_MIPS32R5, 558 (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D 559 | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA), 560 mips_cp0_names_mips3264r2, 561 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 562 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, 563 564 { "mips32r6", 1, bfd_mach_mipsisa32r6, CPU_MIPS32R6, 565 ISA_MIPS32R6, 566 (ASE_EVA | ASE_MSA | ASE_VIRT | ASE_XPA | ASE_MCU | ASE_MT | ASE_DSP 567 | ASE_DSPR2 | ASE_DSPR3), 568 mips_cp0_names_mips3264r2, 569 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 570 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, 571 572 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */ 573 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64, 574 ISA_MIPS64, ASE_MIPS3D | ASE_MDMX, 575 mips_cp0_names_mips3264, 576 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), 577 mips_cp1_names_mips3264, mips_hwr_names_numeric }, 578 579 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2, 580 ISA_MIPS64R2, 581 (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT 582 | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA), 583 mips_cp0_names_mips3264r2, 584 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 585 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, 586 587 { "mips64r3", 1, bfd_mach_mipsisa64r3, CPU_MIPS64R3, 588 ISA_MIPS64R3, 589 (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT 590 | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA), 591 mips_cp0_names_mips3264r2, 592 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 593 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, 594 595 { "mips64r5", 1, bfd_mach_mipsisa64r5, CPU_MIPS64R5, 596 ISA_MIPS64R5, 597 (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT 598 | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA), 599 mips_cp0_names_mips3264r2, 600 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 601 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, 602 603 { "mips64r6", 1, bfd_mach_mipsisa64r6, CPU_MIPS64R6, 604 ISA_MIPS64R6, 605 (ASE_EVA | ASE_MSA | ASE_MSA64 | ASE_XPA | ASE_VIRT | ASE_VIRT64 606 | ASE_MCU | ASE_MT | ASE_DSP | ASE_DSPR2 | ASE_DSPR3), 607 mips_cp0_names_mips3264r2, 608 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 609 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, 610 611 { "interaptiv-mr2", 1, bfd_mach_mips_interaptiv_mr2, CPU_INTERAPTIV_MR2, 612 ISA_MIPS32R3, 613 ASE_MT | ASE_EVA | ASE_DSP | ASE_DSPR2 | ASE_MIPS16E2 | ASE_MIPS16E2_MT, 614 mips_cp0_names_mips3264r2, 615 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 616 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, 617 618 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1, 619 ISA_MIPS64 | INSN_SB1, ASE_MIPS3D, 620 mips_cp0_names_sb1, 621 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1), 622 mips_cp1_names_mips3264, mips_hwr_names_numeric }, 623 624 { "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E, 625 ISA_MIPS3 | INSN_LOONGSON_2E, 0, mips_cp0_names_numeric, 626 NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric }, 627 628 { "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F, 629 ISA_MIPS3 | INSN_LOONGSON_2F, 0, mips_cp0_names_numeric, 630 NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric }, 631 632 { "loongson3a", 1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A, 633 ISA_MIPS64R2 | INSN_LOONGSON_3A, 0, mips_cp0_names_numeric, 634 NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric }, 635 636 { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON, 637 ISA_MIPS64R2 | INSN_OCTEON, 0, mips_cp0_names_numeric, NULL, 0, 638 mips_cp1_names_mips3264, mips_hwr_names_numeric }, 639 640 { "octeon+", 1, bfd_mach_mips_octeonp, CPU_OCTEONP, 641 ISA_MIPS64R2 | INSN_OCTEONP, 0, mips_cp0_names_numeric, 642 NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric }, 643 644 { "octeon2", 1, bfd_mach_mips_octeon2, CPU_OCTEON2, 645 ISA_MIPS64R2 | INSN_OCTEON2, 0, mips_cp0_names_numeric, 646 NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric }, 647 648 { "octeon3", 1, bfd_mach_mips_octeon3, CPU_OCTEON3, 649 ISA_MIPS64R5 | INSN_OCTEON3, ASE_VIRT | ASE_VIRT64, 650 mips_cp0_names_numeric, 651 NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric }, 652 653 { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR, 654 ISA_MIPS64 | INSN_XLR, 0, 655 mips_cp0_names_xlr, 656 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr), 657 mips_cp1_names_mips3264, mips_hwr_names_numeric }, 658 659 /* XLP is mostly like XLR, with the prominent exception it is being 660 MIPS64R2. */ 661 { "xlp", 1, bfd_mach_mips_xlr, CPU_XLR, 662 ISA_MIPS64R2 | INSN_XLR, 0, 663 mips_cp0_names_xlr, 664 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr), 665 mips_cp1_names_mips3264, mips_hwr_names_numeric }, 666 667 /* This entry, mips16, is here only for ISA/processor selection; do 668 not print its name. */ 669 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS64, 670 ASE_MIPS16E2 | ASE_MIPS16E2_MT, 671 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 672 mips_hwr_names_numeric }, 673 }; 674 675 /* ISA and processor type to disassemble for, and register names to use. 676 set_default_mips_dis_options and parse_mips_dis_options fill in these 677 values. */ 678 static int mips_processor; 679 static int mips_isa; 680 static int mips_ase; 681 static int micromips_ase; 682 static const char * const *mips_gpr_names; 683 static const char * const *mips_fpr_names; 684 static const char * const *mips_cp0_names; 685 static const struct mips_cp0sel_name *mips_cp0sel_names; 686 static int mips_cp0sel_names_len; 687 static const char * const *mips_cp1_names; 688 static const char * const *mips_hwr_names; 689 690 /* Other options */ 691 static int no_aliases; /* If set disassemble as most general inst. */ 692 693 static const struct mips_abi_choice * 695 choose_abi_by_name (const char *name, unsigned int namelen) 696 { 697 const struct mips_abi_choice *c; 698 unsigned int i; 699 700 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++) 701 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0 702 && strlen (mips_abi_choices[i].name) == namelen) 703 c = &mips_abi_choices[i]; 704 705 return c; 706 } 707 708 static const struct mips_arch_choice * 709 choose_arch_by_name (const char *name, unsigned int namelen) 710 { 711 const struct mips_arch_choice *c = NULL; 712 unsigned int i; 713 714 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) 715 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0 716 && strlen (mips_arch_choices[i].name) == namelen) 717 c = &mips_arch_choices[i]; 718 719 return c; 720 } 721 722 static const struct mips_arch_choice * 723 choose_arch_by_number (unsigned long mach) 724 { 725 static unsigned long hint_bfd_mach; 726 static const struct mips_arch_choice *hint_arch_choice; 727 const struct mips_arch_choice *c; 728 unsigned int i; 729 730 /* We optimize this because even if the user specifies no 731 flags, this will be done for every instruction! */ 732 if (hint_bfd_mach == mach 733 && hint_arch_choice != NULL 734 && hint_arch_choice->bfd_mach == hint_bfd_mach) 735 return hint_arch_choice; 736 737 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) 738 { 739 if (mips_arch_choices[i].bfd_mach_valid 740 && mips_arch_choices[i].bfd_mach == mach) 741 { 742 c = &mips_arch_choices[i]; 743 hint_bfd_mach = mach; 744 hint_arch_choice = c; 745 } 746 } 747 return c; 748 } 749 750 /* Check if the object uses NewABI conventions. */ 751 752 static int 753 is_newabi (Elf_Internal_Ehdr *header) 754 { 755 /* There are no old-style ABIs which use 64-bit ELF. */ 756 if (header->e_ident[EI_CLASS] == ELFCLASS64) 757 return 1; 758 759 /* If a 32-bit ELF file, n32 is a new-style ABI. */ 760 if ((header->e_flags & EF_MIPS_ABI2) != 0) 761 return 1; 762 763 return 0; 764 } 765 766 /* Check if the object has microMIPS ASE code. */ 767 768 static int 769 is_micromips (Elf_Internal_Ehdr *header) 770 { 771 if ((header->e_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0) 772 return 1; 773 774 return 0; 775 } 776 777 /* Convert ASE flags from .MIPS.abiflags to internal values. */ 778 779 static unsigned long 780 mips_convert_abiflags_ases (unsigned long afl_ases) 781 { 782 unsigned long opcode_ases = 0; 783 784 if (afl_ases & AFL_ASE_DSP) 785 opcode_ases |= ASE_DSP; 786 if (afl_ases & AFL_ASE_DSPR2) 787 opcode_ases |= ASE_DSPR2; 788 if (afl_ases & AFL_ASE_EVA) 789 opcode_ases |= ASE_EVA; 790 if (afl_ases & AFL_ASE_MCU) 791 opcode_ases |= ASE_MCU; 792 if (afl_ases & AFL_ASE_MDMX) 793 opcode_ases |= ASE_MDMX; 794 if (afl_ases & AFL_ASE_MIPS3D) 795 opcode_ases |= ASE_MIPS3D; 796 if (afl_ases & AFL_ASE_MT) 797 opcode_ases |= ASE_MT; 798 if (afl_ases & AFL_ASE_SMARTMIPS) 799 opcode_ases |= ASE_SMARTMIPS; 800 if (afl_ases & AFL_ASE_VIRT) 801 opcode_ases |= ASE_VIRT; 802 if (afl_ases & AFL_ASE_MSA) 803 opcode_ases |= ASE_MSA; 804 if (afl_ases & AFL_ASE_XPA) 805 opcode_ases |= ASE_XPA; 806 if (afl_ases & AFL_ASE_DSPR3) 807 opcode_ases |= ASE_DSPR3; 808 if (afl_ases & AFL_ASE_MIPS16E2) 809 opcode_ases |= ASE_MIPS16E2; 810 return opcode_ases; 811 } 812 813 /* Calculate combination ASE flags from regular ASE flags. */ 814 815 static unsigned long 816 mips_calculate_combination_ases (unsigned long opcode_ases) 817 { 818 unsigned long combination_ases = 0; 819 820 if ((opcode_ases & (ASE_XPA | ASE_VIRT)) == (ASE_XPA | ASE_VIRT)) 821 combination_ases |= ASE_XPA_VIRT; 822 if ((opcode_ases & (ASE_MIPS16E2 | ASE_MT)) == (ASE_MIPS16E2 | ASE_MT)) 823 combination_ases |= ASE_MIPS16E2_MT; 824 return combination_ases; 825 } 826 827 static void 828 set_default_mips_dis_options (struct disassemble_info *info) 829 { 830 const struct mips_arch_choice *chosen_arch; 831 832 /* Defaults: mipsIII/r3000 (?!), no microMIPS ASE (any compressed code 833 is MIPS16 ASE) (o)32-style ("oldabi") GPR names, and numeric FPR, 834 CP0 register, and HWR names. */ 835 mips_isa = ISA_MIPS3; 836 mips_processor = CPU_R3000; 837 micromips_ase = 0; 838 mips_ase = 0; 839 mips_gpr_names = mips_gpr_names_oldabi; 840 mips_fpr_names = mips_fpr_names_numeric; 841 mips_cp0_names = mips_cp0_names_numeric; 842 mips_cp0sel_names = NULL; 843 mips_cp0sel_names_len = 0; 844 mips_cp1_names = mips_cp1_names_numeric; 845 mips_hwr_names = mips_hwr_names_numeric; 846 no_aliases = 0; 847 848 /* Set ISA, architecture, and cp0 register names as best we can. */ 849 #if ! SYMTAB_AVAILABLE 850 /* This is running out on a target machine, not in a host tool. 851 FIXME: Where does mips_target_info come from? */ 852 target_processor = mips_target_info.processor; 853 mips_isa = mips_target_info.isa; 854 mips_ase = mips_target_info.ase; 855 #else 856 chosen_arch = choose_arch_by_number (info->mach); 857 if (chosen_arch != NULL) 858 { 859 mips_processor = chosen_arch->processor; 860 mips_isa = chosen_arch->isa; 861 mips_ase = chosen_arch->ase; 862 mips_cp0_names = chosen_arch->cp0_names; 863 mips_cp0sel_names = chosen_arch->cp0sel_names; 864 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 865 mips_cp1_names = chosen_arch->cp1_names; 866 mips_hwr_names = chosen_arch->hwr_names; 867 } 868 869 /* Update settings according to the ELF file header flags. */ 870 if (info->flavour == bfd_target_elf_flavour && info->section != NULL) 871 { 872 struct bfd *abfd = info->section->owner; 873 Elf_Internal_Ehdr *header = elf_elfheader (abfd); 874 Elf_Internal_ABIFlags_v0 *abiflags = NULL; 875 876 /* We won't ever get here if !HAVE_BFD_MIPS_ELF_GET_ABIFLAGS, 877 because we won't then have a MIPS/ELF BFD, however we need 878 to guard against a link error in a `--enable-targets=...' 879 configuration with a 32-bit host where the MIPS target is 880 a secondary, or with MIPS/ECOFF configurations. */ 881 #ifdef HAVE_BFD_MIPS_ELF_GET_ABIFLAGS 882 abiflags = bfd_mips_elf_get_abiflags (abfd); 883 #endif 884 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */ 885 if (is_newabi (header)) 886 mips_gpr_names = mips_gpr_names_newabi; 887 /* If a microMIPS binary, then don't use MIPS16 bindings. */ 888 micromips_ase = is_micromips (header); 889 /* OR in any extra ASE flags set in ELF file structures. */ 890 if (abiflags) 891 mips_ase |= mips_convert_abiflags_ases (abiflags->ases); 892 else if (header->e_flags & EF_MIPS_ARCH_ASE_MDMX) 893 mips_ase |= ASE_MDMX; 894 } 895 #endif 896 mips_ase |= mips_calculate_combination_ases (mips_ase); 897 } 898 899 /* Parse an ASE disassembler option and set the corresponding global 900 ASE flag(s). Return TRUE if successful, FALSE otherwise. */ 901 902 static bfd_boolean 903 parse_mips_ase_option (const char *option) 904 { 905 if (CONST_STRNEQ (option, "msa")) 906 { 907 mips_ase |= ASE_MSA; 908 if ((mips_isa & INSN_ISA_MASK) == ISA_MIPS64R2 909 || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R3 910 || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R5 911 || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R6) 912 mips_ase |= ASE_MSA64; 913 return TRUE; 914 } 915 916 if (CONST_STRNEQ (option, "virt")) 917 { 918 mips_ase |= ASE_VIRT; 919 if (mips_isa & ISA_MIPS64R2 920 || mips_isa & ISA_MIPS64R3 921 || mips_isa & ISA_MIPS64R5 922 || mips_isa & ISA_MIPS64R6) 923 mips_ase |= ASE_VIRT64; 924 return TRUE; 925 } 926 927 if (CONST_STRNEQ (option, "xpa")) 928 { 929 mips_ase |= ASE_XPA; 930 return TRUE; 931 } 932 933 return FALSE; 934 } 935 936 static void 937 parse_mips_dis_option (const char *option, unsigned int len) 938 { 939 unsigned int i, optionlen, vallen; 940 const char *val; 941 const struct mips_abi_choice *chosen_abi; 942 const struct mips_arch_choice *chosen_arch; 943 944 /* Try to match options that are simple flags */ 945 if (CONST_STRNEQ (option, "no-aliases")) 946 { 947 no_aliases = 1; 948 return; 949 } 950 951 if (parse_mips_ase_option (option)) 952 { 953 mips_ase |= mips_calculate_combination_ases (mips_ase); 954 return; 955 } 956 957 /* Look for the = that delimits the end of the option name. */ 958 for (i = 0; i < len; i++) 959 if (option[i] == '=') 960 break; 961 962 if (i == 0) /* Invalid option: no name before '='. */ 963 return; 964 if (i == len) /* Invalid option: no '='. */ 965 return; 966 if (i == (len - 1)) /* Invalid option: no value after '='. */ 967 return; 968 969 optionlen = i; 970 val = option + (optionlen + 1); 971 vallen = len - (optionlen + 1); 972 973 if (strncmp ("gpr-names", option, optionlen) == 0 974 && strlen ("gpr-names") == optionlen) 975 { 976 chosen_abi = choose_abi_by_name (val, vallen); 977 if (chosen_abi != NULL) 978 mips_gpr_names = chosen_abi->gpr_names; 979 return; 980 } 981 982 if (strncmp ("fpr-names", option, optionlen) == 0 983 && strlen ("fpr-names") == optionlen) 984 { 985 chosen_abi = choose_abi_by_name (val, vallen); 986 if (chosen_abi != NULL) 987 mips_fpr_names = chosen_abi->fpr_names; 988 return; 989 } 990 991 if (strncmp ("cp0-names", option, optionlen) == 0 992 && strlen ("cp0-names") == optionlen) 993 { 994 chosen_arch = choose_arch_by_name (val, vallen); 995 if (chosen_arch != NULL) 996 { 997 mips_cp0_names = chosen_arch->cp0_names; 998 mips_cp0sel_names = chosen_arch->cp0sel_names; 999 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 1000 } 1001 return; 1002 } 1003 1004 if (strncmp ("cp1-names", option, optionlen) == 0 1005 && strlen ("cp1-names") == optionlen) 1006 { 1007 chosen_arch = choose_arch_by_name (val, vallen); 1008 if (chosen_arch != NULL) 1009 mips_cp1_names = chosen_arch->cp1_names; 1010 return; 1011 } 1012 1013 if (strncmp ("hwr-names", option, optionlen) == 0 1014 && strlen ("hwr-names") == optionlen) 1015 { 1016 chosen_arch = choose_arch_by_name (val, vallen); 1017 if (chosen_arch != NULL) 1018 mips_hwr_names = chosen_arch->hwr_names; 1019 return; 1020 } 1021 1022 if (strncmp ("reg-names", option, optionlen) == 0 1023 && strlen ("reg-names") == optionlen) 1024 { 1025 /* We check both ABI and ARCH here unconditionally, so 1026 that "numeric" will do the desirable thing: select 1027 numeric register names for all registers. Other than 1028 that, a given name probably won't match both. */ 1029 chosen_abi = choose_abi_by_name (val, vallen); 1030 if (chosen_abi != NULL) 1031 { 1032 mips_gpr_names = chosen_abi->gpr_names; 1033 mips_fpr_names = chosen_abi->fpr_names; 1034 } 1035 chosen_arch = choose_arch_by_name (val, vallen); 1036 if (chosen_arch != NULL) 1037 { 1038 mips_cp0_names = chosen_arch->cp0_names; 1039 mips_cp0sel_names = chosen_arch->cp0sel_names; 1040 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 1041 mips_cp1_names = chosen_arch->cp1_names; 1042 mips_hwr_names = chosen_arch->hwr_names; 1043 } 1044 return; 1045 } 1046 1047 /* Invalid option. */ 1048 } 1049 1050 static void 1051 parse_mips_dis_options (const char *options) 1052 { 1053 const char *option_end; 1054 1055 if (options == NULL) 1056 return; 1057 1058 while (*options != '\0') 1059 { 1060 /* Skip empty options. */ 1061 if (*options == ',') 1062 { 1063 options++; 1064 continue; 1065 } 1066 1067 /* We know that *options is neither NUL or a comma. */ 1068 option_end = options + 1; 1069 while (*option_end != ',' && *option_end != '\0') 1070 option_end++; 1071 1072 parse_mips_dis_option (options, option_end - options); 1073 1074 /* Go on to the next one. If option_end points to a comma, it 1075 will be skipped above. */ 1076 options = option_end; 1077 } 1078 } 1079 1080 static const struct mips_cp0sel_name * 1081 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names, 1082 unsigned int len, 1083 unsigned int cp0reg, 1084 unsigned int sel) 1085 { 1086 unsigned int i; 1087 1088 for (i = 0; i < len; i++) 1089 if (names[i].cp0reg == cp0reg && names[i].sel == sel) 1090 return &names[i]; 1091 return NULL; 1092 } 1093 1094 /* Print register REGNO, of type TYPE, for instruction OPCODE. */ 1095 1096 static void 1097 print_reg (struct disassemble_info *info, const struct mips_opcode *opcode, 1098 enum mips_reg_operand_type type, int regno) 1099 { 1100 switch (type) 1101 { 1102 case OP_REG_GP: 1103 info->fprintf_func (info->stream, "%s", mips_gpr_names[regno]); 1104 break; 1105 1106 case OP_REG_FP: 1107 info->fprintf_func (info->stream, "%s", mips_fpr_names[regno]); 1108 break; 1109 1110 case OP_REG_CCC: 1111 if (opcode->pinfo & (FP_D | FP_S)) 1112 info->fprintf_func (info->stream, "$fcc%d", regno); 1113 else 1114 info->fprintf_func (info->stream, "$cc%d", regno); 1115 break; 1116 1117 case OP_REG_VEC: 1118 if (opcode->membership & INSN_5400) 1119 info->fprintf_func (info->stream, "$f%d", regno); 1120 else 1121 info->fprintf_func (info->stream, "$v%d", regno); 1122 break; 1123 1124 case OP_REG_ACC: 1125 info->fprintf_func (info->stream, "$ac%d", regno); 1126 break; 1127 1128 case OP_REG_COPRO: 1129 if (opcode->name[strlen (opcode->name) - 1] == '0') 1130 info->fprintf_func (info->stream, "%s", mips_cp0_names[regno]); 1131 else if (opcode->name[strlen (opcode->name) - 1] == '1') 1132 info->fprintf_func (info->stream, "%s", mips_cp1_names[regno]); 1133 else 1134 info->fprintf_func (info->stream, "$%d", regno); 1135 break; 1136 1137 case OP_REG_HW: 1138 info->fprintf_func (info->stream, "%s", mips_hwr_names[regno]); 1139 break; 1140 1141 case OP_REG_VF: 1142 info->fprintf_func (info->stream, "$vf%d", regno); 1143 break; 1144 1145 case OP_REG_VI: 1146 info->fprintf_func (info->stream, "$vi%d", regno); 1147 break; 1148 1149 case OP_REG_R5900_I: 1150 info->fprintf_func (info->stream, "$I"); 1151 break; 1152 1153 case OP_REG_R5900_Q: 1154 info->fprintf_func (info->stream, "$Q"); 1155 break; 1156 1157 case OP_REG_R5900_R: 1158 info->fprintf_func (info->stream, "$R"); 1159 break; 1160 1161 case OP_REG_R5900_ACC: 1162 info->fprintf_func (info->stream, "$ACC"); 1163 break; 1164 1165 case OP_REG_MSA: 1166 info->fprintf_func (info->stream, "$w%d", regno); 1167 break; 1168 1169 case OP_REG_MSA_CTRL: 1170 info->fprintf_func (info->stream, "%s", msa_control_names[regno]); 1171 break; 1172 1173 } 1174 } 1175 1176 /* Used to track the state carried over from previous operands in 1178 an instruction. */ 1179 struct mips_print_arg_state { 1180 /* The value of the last OP_INT seen. We only use this for OP_MSB, 1181 where the value is known to be unsigned and small. */ 1182 unsigned int last_int; 1183 1184 /* The type and number of the last OP_REG seen. We only use this for 1185 OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG. */ 1186 enum mips_reg_operand_type last_reg_type; 1187 unsigned int last_regno; 1188 unsigned int dest_regno; 1189 unsigned int seen_dest; 1190 }; 1191 1192 /* Initialize STATE for the start of an instruction. */ 1193 1194 static inline void 1195 init_print_arg_state (struct mips_print_arg_state *state) 1196 { 1197 memset (state, 0, sizeof (*state)); 1198 } 1199 1200 /* Print OP_VU0_SUFFIX or OP_VU0_MATCH_SUFFIX operand OPERAND, 1201 whose value is given by UVAL. */ 1202 1203 static void 1204 print_vu0_channel (struct disassemble_info *info, 1205 const struct mips_operand *operand, unsigned int uval) 1206 { 1207 if (operand->size == 4) 1208 info->fprintf_func (info->stream, "%s%s%s%s", 1209 uval & 8 ? "x" : "", 1210 uval & 4 ? "y" : "", 1211 uval & 2 ? "z" : "", 1212 uval & 1 ? "w" : ""); 1213 else if (operand->size == 2) 1214 info->fprintf_func (info->stream, "%c", "xyzw"[uval]); 1215 else 1216 abort (); 1217 } 1218 1219 /* Record information about a register operand. */ 1220 1221 static void 1222 mips_seen_register (struct mips_print_arg_state *state, 1223 unsigned int regno, 1224 enum mips_reg_operand_type reg_type) 1225 { 1226 state->last_reg_type = reg_type; 1227 state->last_regno = regno; 1228 1229 if (!state->seen_dest) 1230 { 1231 state->seen_dest = 1; 1232 state->dest_regno = regno; 1233 } 1234 } 1235 1236 /* Print SAVE/RESTORE instruction operands according to the argument 1237 register mask AMASK, the number of static registers saved NSREG, 1238 the $ra, $s0 and $s1 register specifiers RA, S0 and S1 respectively, 1239 and the frame size FRAME_SIZE. */ 1240 1241 static void 1242 mips_print_save_restore (struct disassemble_info *info, unsigned int amask, 1243 unsigned int nsreg, unsigned int ra, 1244 unsigned int s0, unsigned int s1, 1245 unsigned int frame_size) 1246 { 1247 const fprintf_ftype infprintf = info->fprintf_func; 1248 unsigned int nargs, nstatics, smask, i, j; 1249 void *is = info->stream; 1250 const char *sep; 1251 1252 if (amask == MIPS_SVRS_ALL_ARGS) 1253 { 1254 nargs = 4; 1255 nstatics = 0; 1256 } 1257 else if (amask == MIPS_SVRS_ALL_STATICS) 1258 { 1259 nargs = 0; 1260 nstatics = 4; 1261 } 1262 else 1263 { 1264 nargs = amask >> 2; 1265 nstatics = amask & 3; 1266 } 1267 1268 sep = ""; 1269 if (nargs > 0) 1270 { 1271 infprintf (is, "%s", mips_gpr_names[4]); 1272 if (nargs > 1) 1273 infprintf (is, "-%s", mips_gpr_names[4 + nargs - 1]); 1274 sep = ","; 1275 } 1276 1277 infprintf (is, "%s%d", sep, frame_size); 1278 1279 if (ra) /* $ra */ 1280 infprintf (is, ",%s", mips_gpr_names[31]); 1281 1282 smask = 0; 1283 if (s0) /* $s0 */ 1284 smask |= 1 << 0; 1285 if (s1) /* $s1 */ 1286 smask |= 1 << 1; 1287 if (nsreg > 0) /* $s2-$s8 */ 1288 smask |= ((1 << nsreg) - 1) << 2; 1289 1290 for (i = 0; i < 9; i++) 1291 if (smask & (1 << i)) 1292 { 1293 infprintf (is, ",%s", mips_gpr_names[i == 8 ? 30 : (16 + i)]); 1294 /* Skip over string of set bits. */ 1295 for (j = i; smask & (2 << j); j++) 1296 continue; 1297 if (j > i) 1298 infprintf (is, "-%s", mips_gpr_names[j == 8 ? 30 : (16 + j)]); 1299 i = j + 1; 1300 } 1301 /* Statics $ax - $a3. */ 1302 if (nstatics == 1) 1303 infprintf (is, ",%s", mips_gpr_names[7]); 1304 else if (nstatics > 0) 1305 infprintf (is, ",%s-%s", 1306 mips_gpr_names[7 - nstatics + 1], 1307 mips_gpr_names[7]); 1308 } 1309 1310 1311 /* Print operand OPERAND of OPCODE, using STATE to track inter-operand state. 1312 UVAL is the encoding of the operand (shifted into bit 0) and BASE_PC is 1313 the base address for OP_PCREL operands. */ 1314 1315 static void 1316 print_insn_arg (struct disassemble_info *info, 1317 struct mips_print_arg_state *state, 1318 const struct mips_opcode *opcode, 1319 const struct mips_operand *operand, 1320 bfd_vma base_pc, 1321 unsigned int uval) 1322 { 1323 const fprintf_ftype infprintf = info->fprintf_func; 1324 void *is = info->stream; 1325 1326 switch (operand->type) 1327 { 1328 case OP_INT: 1329 { 1330 const struct mips_int_operand *int_op; 1331 1332 int_op = (const struct mips_int_operand *) operand; 1333 uval = mips_decode_int_operand (int_op, uval); 1334 state->last_int = uval; 1335 if (int_op->print_hex) 1336 infprintf (is, "0x%x", uval); 1337 else 1338 infprintf (is, "%d", uval); 1339 } 1340 break; 1341 1342 case OP_MAPPED_INT: 1343 { 1344 const struct mips_mapped_int_operand *mint_op; 1345 1346 mint_op = (const struct mips_mapped_int_operand *) operand; 1347 uval = mint_op->int_map[uval]; 1348 state->last_int = uval; 1349 if (mint_op->print_hex) 1350 infprintf (is, "0x%x", uval); 1351 else 1352 infprintf (is, "%d", uval); 1353 } 1354 break; 1355 1356 case OP_MSB: 1357 { 1358 const struct mips_msb_operand *msb_op; 1359 1360 msb_op = (const struct mips_msb_operand *) operand; 1361 uval += msb_op->bias; 1362 if (msb_op->add_lsb) 1363 uval -= state->last_int; 1364 infprintf (is, "0x%x", uval); 1365 } 1366 break; 1367 1368 case OP_REG: 1369 case OP_OPTIONAL_REG: 1370 { 1371 const struct mips_reg_operand *reg_op; 1372 1373 reg_op = (const struct mips_reg_operand *) operand; 1374 uval = mips_decode_reg_operand (reg_op, uval); 1375 print_reg (info, opcode, reg_op->reg_type, uval); 1376 1377 mips_seen_register (state, uval, reg_op->reg_type); 1378 } 1379 break; 1380 1381 case OP_REG_PAIR: 1382 { 1383 const struct mips_reg_pair_operand *pair_op; 1384 1385 pair_op = (const struct mips_reg_pair_operand *) operand; 1386 print_reg (info, opcode, pair_op->reg_type, 1387 pair_op->reg1_map[uval]); 1388 infprintf (is, ","); 1389 print_reg (info, opcode, pair_op->reg_type, 1390 pair_op->reg2_map[uval]); 1391 } 1392 break; 1393 1394 case OP_PCREL: 1395 { 1396 const struct mips_pcrel_operand *pcrel_op; 1397 1398 pcrel_op = (const struct mips_pcrel_operand *) operand; 1399 info->target = mips_decode_pcrel_operand (pcrel_op, base_pc, uval); 1400 1401 /* For jumps and branches clear the ISA bit except for 1402 the GDB disassembler. */ 1403 if (pcrel_op->include_isa_bit 1404 && info->flavour != bfd_target_unknown_flavour) 1405 info->target &= -2; 1406 1407 (*info->print_address_func) (info->target, info); 1408 } 1409 break; 1410 1411 case OP_PERF_REG: 1412 infprintf (is, "%d", uval); 1413 break; 1414 1415 case OP_ADDIUSP_INT: 1416 { 1417 int sval; 1418 1419 sval = mips_signed_operand (operand, uval) * 4; 1420 if (sval >= -8 && sval < 8) 1421 sval ^= 0x400; 1422 infprintf (is, "%d", sval); 1423 break; 1424 } 1425 1426 case OP_CLO_CLZ_DEST: 1427 { 1428 unsigned int reg1, reg2; 1429 1430 reg1 = uval & 31; 1431 reg2 = uval >> 5; 1432 /* If one is zero use the other. */ 1433 if (reg1 == reg2 || reg2 == 0) 1434 infprintf (is, "%s", mips_gpr_names[reg1]); 1435 else if (reg1 == 0) 1436 infprintf (is, "%s", mips_gpr_names[reg2]); 1437 else 1438 /* Bogus, result depends on processor. */ 1439 infprintf (is, "%s or %s", mips_gpr_names[reg1], 1440 mips_gpr_names[reg2]); 1441 } 1442 break; 1443 1444 case OP_SAME_RS_RT: 1445 case OP_CHECK_PREV: 1446 case OP_NON_ZERO_REG: 1447 { 1448 print_reg (info, opcode, OP_REG_GP, uval & 31); 1449 mips_seen_register (state, uval, OP_REG_GP); 1450 } 1451 break; 1452 1453 case OP_LWM_SWM_LIST: 1454 if (operand->size == 2) 1455 { 1456 if (uval == 0) 1457 infprintf (is, "%s,%s", 1458 mips_gpr_names[16], 1459 mips_gpr_names[31]); 1460 else 1461 infprintf (is, "%s-%s,%s", 1462 mips_gpr_names[16], 1463 mips_gpr_names[16 + uval], 1464 mips_gpr_names[31]); 1465 } 1466 else 1467 { 1468 int s_reg_encode; 1469 1470 s_reg_encode = uval & 0xf; 1471 if (s_reg_encode != 0) 1472 { 1473 if (s_reg_encode == 1) 1474 infprintf (is, "%s", mips_gpr_names[16]); 1475 else if (s_reg_encode < 9) 1476 infprintf (is, "%s-%s", 1477 mips_gpr_names[16], 1478 mips_gpr_names[15 + s_reg_encode]); 1479 else if (s_reg_encode == 9) 1480 infprintf (is, "%s-%s,%s", 1481 mips_gpr_names[16], 1482 mips_gpr_names[23], 1483 mips_gpr_names[30]); 1484 else 1485 infprintf (is, "UNKNOWN"); 1486 } 1487 1488 if (uval & 0x10) /* For ra. */ 1489 { 1490 if (s_reg_encode == 0) 1491 infprintf (is, "%s", mips_gpr_names[31]); 1492 else 1493 infprintf (is, ",%s", mips_gpr_names[31]); 1494 } 1495 } 1496 break; 1497 1498 case OP_ENTRY_EXIT_LIST: 1499 { 1500 const char *sep; 1501 unsigned int amask, smask; 1502 1503 sep = ""; 1504 amask = (uval >> 3) & 7; 1505 if (amask > 0 && amask < 5) 1506 { 1507 infprintf (is, "%s", mips_gpr_names[4]); 1508 if (amask > 1) 1509 infprintf (is, "-%s", mips_gpr_names[amask + 3]); 1510 sep = ","; 1511 } 1512 1513 smask = (uval >> 1) & 3; 1514 if (smask == 3) 1515 { 1516 infprintf (is, "%s??", sep); 1517 sep = ","; 1518 } 1519 else if (smask > 0) 1520 { 1521 infprintf (is, "%s%s", sep, mips_gpr_names[16]); 1522 if (smask > 1) 1523 infprintf (is, "-%s", mips_gpr_names[smask + 15]); 1524 sep = ","; 1525 } 1526 1527 if (uval & 1) 1528 { 1529 infprintf (is, "%s%s", sep, mips_gpr_names[31]); 1530 sep = ","; 1531 } 1532 1533 if (amask == 5 || amask == 6) 1534 { 1535 infprintf (is, "%s%s", sep, mips_fpr_names[0]); 1536 if (amask == 6) 1537 infprintf (is, "-%s", mips_fpr_names[1]); 1538 } 1539 } 1540 break; 1541 1542 case OP_SAVE_RESTORE_LIST: 1543 /* Should be handled by the caller due to complex behavior. */ 1544 abort (); 1545 1546 case OP_MDMX_IMM_REG: 1547 { 1548 unsigned int vsel; 1549 1550 vsel = uval >> 5; 1551 uval &= 31; 1552 if ((vsel & 0x10) == 0) 1553 { 1554 int fmt; 1555 1556 vsel &= 0x0f; 1557 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1) 1558 if ((vsel & 1) == 0) 1559 break; 1560 print_reg (info, opcode, OP_REG_VEC, uval); 1561 infprintf (is, "[%d]", vsel >> 1); 1562 } 1563 else if ((vsel & 0x08) == 0) 1564 print_reg (info, opcode, OP_REG_VEC, uval); 1565 else 1566 infprintf (is, "0x%x", uval); 1567 } 1568 break; 1569 1570 case OP_REPEAT_PREV_REG: 1571 print_reg (info, opcode, state->last_reg_type, state->last_regno); 1572 break; 1573 1574 case OP_REPEAT_DEST_REG: 1575 print_reg (info, opcode, state->last_reg_type, state->dest_regno); 1576 break; 1577 1578 case OP_PC: 1579 infprintf (is, "$pc"); 1580 break; 1581 1582 case OP_REG28: 1583 print_reg (info, opcode, OP_REG_GP, 28); 1584 break; 1585 1586 case OP_VU0_SUFFIX: 1587 case OP_VU0_MATCH_SUFFIX: 1588 print_vu0_channel (info, operand, uval); 1589 break; 1590 1591 case OP_IMM_INDEX: 1592 infprintf (is, "[%d]", uval); 1593 break; 1594 1595 case OP_REG_INDEX: 1596 infprintf (is, "["); 1597 print_reg (info, opcode, OP_REG_GP, uval); 1598 infprintf (is, "]"); 1599 break; 1600 } 1601 } 1602 1603 /* Validate the arguments for INSN, which is described by OPCODE. 1604 Use DECODE_OPERAND to get the encoding of each operand. */ 1605 1606 static bfd_boolean 1607 validate_insn_args (const struct mips_opcode *opcode, 1608 const struct mips_operand *(*decode_operand) (const char *), 1609 unsigned int insn) 1610 { 1611 struct mips_print_arg_state state; 1612 const struct mips_operand *operand; 1613 const char *s; 1614 unsigned int uval; 1615 1616 init_print_arg_state (&state); 1617 for (s = opcode->args; *s; ++s) 1618 { 1619 switch (*s) 1620 { 1621 case ',': 1622 case '(': 1623 case ')': 1624 break; 1625 1626 case '#': 1627 ++s; 1628 break; 1629 1630 default: 1631 operand = decode_operand (s); 1632 1633 if (operand) 1634 { 1635 uval = mips_extract_operand (operand, insn); 1636 switch (operand->type) 1637 { 1638 case OP_REG: 1639 case OP_OPTIONAL_REG: 1640 { 1641 const struct mips_reg_operand *reg_op; 1642 1643 reg_op = (const struct mips_reg_operand *) operand; 1644 uval = mips_decode_reg_operand (reg_op, uval); 1645 mips_seen_register (&state, uval, reg_op->reg_type); 1646 } 1647 break; 1648 1649 case OP_SAME_RS_RT: 1650 { 1651 unsigned int reg1, reg2; 1652 1653 reg1 = uval & 31; 1654 reg2 = uval >> 5; 1655 1656 if (reg1 != reg2 || reg1 == 0) 1657 return FALSE; 1658 } 1659 break; 1660 1661 case OP_CHECK_PREV: 1662 { 1663 const struct mips_check_prev_operand *prev_op; 1664 1665 prev_op = (const struct mips_check_prev_operand *) operand; 1666 1667 if (!prev_op->zero_ok && uval == 0) 1668 return FALSE; 1669 1670 if (((prev_op->less_than_ok && uval < state.last_regno) 1671 || (prev_op->greater_than_ok && uval > state.last_regno) 1672 || (prev_op->equal_ok && uval == state.last_regno))) 1673 break; 1674 1675 return FALSE; 1676 } 1677 1678 case OP_NON_ZERO_REG: 1679 { 1680 if (uval == 0) 1681 return FALSE; 1682 } 1683 break; 1684 1685 case OP_INT: 1686 case OP_MAPPED_INT: 1687 case OP_MSB: 1688 case OP_REG_PAIR: 1689 case OP_PCREL: 1690 case OP_PERF_REG: 1691 case OP_ADDIUSP_INT: 1692 case OP_CLO_CLZ_DEST: 1693 case OP_LWM_SWM_LIST: 1694 case OP_ENTRY_EXIT_LIST: 1695 case OP_MDMX_IMM_REG: 1696 case OP_REPEAT_PREV_REG: 1697 case OP_REPEAT_DEST_REG: 1698 case OP_PC: 1699 case OP_REG28: 1700 case OP_VU0_SUFFIX: 1701 case OP_VU0_MATCH_SUFFIX: 1702 case OP_IMM_INDEX: 1703 case OP_REG_INDEX: 1704 case OP_SAVE_RESTORE_LIST: 1705 break; 1706 } 1707 } 1708 if (*s == 'm' || *s == '+' || *s == '-') 1709 ++s; 1710 } 1711 } 1712 return TRUE; 1713 } 1714 1715 /* Print the arguments for INSN, which is described by OPCODE. 1716 Use DECODE_OPERAND to get the encoding of each operand. Use BASE_PC 1717 as the base of OP_PCREL operands, adjusting by LENGTH if the OP_PCREL 1718 operand is for a branch or jump. */ 1719 1720 static void 1721 print_insn_args (struct disassemble_info *info, 1722 const struct mips_opcode *opcode, 1723 const struct mips_operand *(*decode_operand) (const char *), 1724 unsigned int insn, bfd_vma insn_pc, unsigned int length) 1725 { 1726 const fprintf_ftype infprintf = info->fprintf_func; 1727 void *is = info->stream; 1728 struct mips_print_arg_state state; 1729 const struct mips_operand *operand; 1730 const char *s; 1731 1732 init_print_arg_state (&state); 1733 for (s = opcode->args; *s; ++s) 1734 { 1735 switch (*s) 1736 { 1737 case ',': 1738 case '(': 1739 case ')': 1740 infprintf (is, "%c", *s); 1741 break; 1742 1743 case '#': 1744 ++s; 1745 infprintf (is, "%c%c", *s, *s); 1746 break; 1747 1748 default: 1749 operand = decode_operand (s); 1750 if (!operand) 1751 { 1752 /* xgettext:c-format */ 1753 infprintf (is, 1754 _("# internal error, undefined operand in `%s %s'"), 1755 opcode->name, opcode->args); 1756 return; 1757 } 1758 1759 if (operand->type == OP_SAVE_RESTORE_LIST) 1760 { 1761 /* Handle this case here because of the complex behavior. */ 1762 unsigned int amask = (insn >> 15) & 0xf; 1763 unsigned int nsreg = (insn >> 23) & 0x7; 1764 unsigned int ra = insn & 0x1000; /* $ra */ 1765 unsigned int s0 = insn & 0x800; /* $s0 */ 1766 unsigned int s1 = insn & 0x400; /* $s1 */ 1767 unsigned int frame_size = (((insn >> 15) & 0xf0) 1768 | ((insn >> 6) & 0x0f)) * 8; 1769 mips_print_save_restore (info, amask, nsreg, ra, s0, s1, 1770 frame_size); 1771 } 1772 else if (operand->type == OP_REG 1773 && s[1] == ',' 1774 && s[2] == 'H' 1775 && opcode->name[strlen (opcode->name) - 1] == '0') 1776 { 1777 /* Coprocessor register 0 with sel field. */ 1778 const struct mips_cp0sel_name *n; 1779 unsigned int reg, sel; 1780 1781 reg = mips_extract_operand (operand, insn); 1782 s += 2; 1783 operand = decode_operand (s); 1784 sel = mips_extract_operand (operand, insn); 1785 1786 /* CP0 register including 'sel' code for mftc0, to be 1787 printed textually if known. If not known, print both 1788 CP0 register name and sel numerically since CP0 register 1789 with sel 0 may have a name unrelated to register being 1790 printed. */ 1791 n = lookup_mips_cp0sel_name (mips_cp0sel_names, 1792 mips_cp0sel_names_len, 1793 reg, sel); 1794 if (n != NULL) 1795 infprintf (is, "%s", n->name); 1796 else 1797 infprintf (is, "$%d,%d", reg, sel); 1798 } 1799 else 1800 { 1801 bfd_vma base_pc = insn_pc; 1802 1803 /* Adjust the PC relative base so that branch/jump insns use 1804 the following PC as the base but genuinely PC relative 1805 operands use the current PC. */ 1806 if (operand->type == OP_PCREL) 1807 { 1808 const struct mips_pcrel_operand *pcrel_op; 1809 1810 pcrel_op = (const struct mips_pcrel_operand *) operand; 1811 /* The include_isa_bit flag is sufficient to distinguish 1812 branch/jump from other PC relative operands. */ 1813 if (pcrel_op->include_isa_bit) 1814 base_pc += length; 1815 } 1816 1817 print_insn_arg (info, &state, opcode, operand, base_pc, 1818 mips_extract_operand (operand, insn)); 1819 } 1820 if (*s == 'm' || *s == '+' || *s == '-') 1821 ++s; 1822 break; 1823 } 1824 } 1825 } 1826 1827 /* Print the mips instruction at address MEMADDR in debugged memory, 1829 on using INFO. Returns length of the instruction, in bytes, which is 1830 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if 1831 this is little-endian code. */ 1832 1833 static int 1834 print_insn_mips (bfd_vma memaddr, 1835 int word, 1836 struct disassemble_info *info) 1837 { 1838 #define GET_OP(insn, field) \ 1839 (((insn) >> OP_SH_##field) & OP_MASK_##field) 1840 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1]; 1841 const fprintf_ftype infprintf = info->fprintf_func; 1842 const struct mips_opcode *op; 1843 static bfd_boolean init = 0; 1844 void *is = info->stream; 1845 1846 /* Build a hash table to shorten the search time. */ 1847 if (! init) 1848 { 1849 unsigned int i; 1850 1851 for (i = 0; i <= OP_MASK_OP; i++) 1852 { 1853 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++) 1854 { 1855 if (op->pinfo == INSN_MACRO 1856 || (no_aliases && (op->pinfo2 & INSN2_ALIAS))) 1857 continue; 1858 if (i == GET_OP (op->match, OP)) 1859 { 1860 mips_hash[i] = op; 1861 break; 1862 } 1863 } 1864 } 1865 1866 init = 1; 1867 } 1868 1869 info->bytes_per_chunk = INSNLEN; 1870 info->display_endian = info->endian; 1871 info->insn_info_valid = 1; 1872 info->branch_delay_insns = 0; 1873 info->data_size = 0; 1874 info->insn_type = dis_nonbranch; 1875 info->target = 0; 1876 info->target2 = 0; 1877 1878 op = mips_hash[GET_OP (word, OP)]; 1879 if (op != NULL) 1880 { 1881 for (; op < &mips_opcodes[NUMOPCODES]; op++) 1882 { 1883 if (op->pinfo != INSN_MACRO 1884 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) 1885 && (word & op->mask) == op->match) 1886 { 1887 /* We always disassemble the jalx instruction, except for MIPS r6. */ 1888 if (!opcode_is_member (op, mips_isa, mips_ase, mips_processor) 1889 && (strcmp (op->name, "jalx") 1890 || (mips_isa & INSN_ISA_MASK) == ISA_MIPS32R6 1891 || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R6)) 1892 continue; 1893 1894 /* Figure out instruction type and branch delay information. */ 1895 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) 1896 { 1897 if ((op->pinfo & (INSN_WRITE_GPR_31 | INSN_WRITE_1)) != 0) 1898 info->insn_type = dis_jsr; 1899 else 1900 info->insn_type = dis_branch; 1901 info->branch_delay_insns = 1; 1902 } 1903 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY 1904 | INSN_COND_BRANCH_LIKELY)) != 0) 1905 { 1906 if ((op->pinfo & INSN_WRITE_GPR_31) != 0) 1907 info->insn_type = dis_condjsr; 1908 else 1909 info->insn_type = dis_condbranch; 1910 info->branch_delay_insns = 1; 1911 } 1912 else if ((op->pinfo & (INSN_STORE_MEMORY 1913 | INSN_LOAD_MEMORY)) != 0) 1914 info->insn_type = dis_dref; 1915 1916 if (!validate_insn_args (op, decode_mips_operand, word)) 1917 continue; 1918 1919 infprintf (is, "%s", op->name); 1920 if (op->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) 1921 { 1922 unsigned int uval; 1923 1924 infprintf (is, "."); 1925 uval = mips_extract_operand (&mips_vu0_channel_mask, word); 1926 print_vu0_channel (info, &mips_vu0_channel_mask, uval); 1927 } 1928 1929 if (op->args[0]) 1930 { 1931 infprintf (is, "\t"); 1932 print_insn_args (info, op, decode_mips_operand, word, 1933 memaddr, 4); 1934 } 1935 1936 return INSNLEN; 1937 } 1938 } 1939 } 1940 #undef GET_OP 1941 1942 /* Handle undefined instructions. */ 1943 info->insn_type = dis_noninsn; 1944 infprintf (is, "0x%x", word); 1945 return INSNLEN; 1946 } 1947 1948 /* Disassemble an operand for a mips16 instruction. */ 1950 1951 static void 1952 print_mips16_insn_arg (struct disassemble_info *info, 1953 struct mips_print_arg_state *state, 1954 const struct mips_opcode *opcode, 1955 char type, bfd_vma memaddr, 1956 unsigned insn, bfd_boolean use_extend, 1957 unsigned extend, bfd_boolean is_offset) 1958 { 1959 const fprintf_ftype infprintf = info->fprintf_func; 1960 void *is = info->stream; 1961 const struct mips_operand *operand, *ext_operand; 1962 unsigned short ext_size; 1963 unsigned int uval; 1964 bfd_vma baseaddr; 1965 1966 if (!use_extend) 1967 extend = 0; 1968 1969 switch (type) 1970 { 1971 case ',': 1972 case '(': 1973 case ')': 1974 infprintf (is, "%c", type); 1975 break; 1976 1977 default: 1978 operand = decode_mips16_operand (type, FALSE); 1979 if (!operand) 1980 { 1981 /* xgettext:c-format */ 1982 infprintf (is, _("# internal error, undefined operand in `%s %s'"), 1983 opcode->name, opcode->args); 1984 return; 1985 } 1986 1987 if (operand->type == OP_SAVE_RESTORE_LIST) 1988 { 1989 /* Handle this case here because of the complex interaction 1990 with the EXTEND opcode. */ 1991 unsigned int amask = extend & 0xf; 1992 unsigned int nsreg = (extend >> 8) & 0x7; 1993 unsigned int ra = insn & 0x40; /* $ra */ 1994 unsigned int s0 = insn & 0x20; /* $s0 */ 1995 unsigned int s1 = insn & 0x10; /* $s1 */ 1996 unsigned int frame_size = ((extend & 0xf0) | (insn & 0x0f)) * 8; 1997 if (frame_size == 0 && !use_extend) 1998 frame_size = 128; 1999 mips_print_save_restore (info, amask, nsreg, ra, s0, s1, frame_size); 2000 break; 2001 } 2002 2003 if (is_offset && operand->type == OP_INT) 2004 { 2005 const struct mips_int_operand *int_op; 2006 2007 int_op = (const struct mips_int_operand *) operand; 2008 info->insn_type = dis_dref; 2009 info->data_size = 1 << int_op->shift; 2010 } 2011 2012 ext_size = 0; 2013 if (use_extend) 2014 { 2015 ext_operand = decode_mips16_operand (type, TRUE); 2016 if (ext_operand != operand 2017 || (operand->type == OP_INT && operand->lsb == 0 2018 && mips_opcode_32bit_p (opcode))) 2019 { 2020 ext_size = ext_operand->size; 2021 operand = ext_operand; 2022 } 2023 } 2024 if (operand->size == 26) 2025 uval = ((extend & 0x1f) << 21) | ((extend & 0x3e0) << 11) | insn; 2026 else if (ext_size == 16 || ext_size == 9) 2027 uval = ((extend & 0x1f) << 11) | (extend & 0x7e0) | (insn & 0x1f); 2028 else if (ext_size == 15) 2029 uval = ((extend & 0xf) << 11) | (extend & 0x7f0) | (insn & 0xf); 2030 else if (ext_size == 6) 2031 uval = ((extend >> 6) & 0x1f) | (extend & 0x20); 2032 else 2033 uval = mips_extract_operand (operand, (extend << 16) | insn); 2034 if (ext_size == 9) 2035 uval &= (1U << ext_size) - 1; 2036 2037 baseaddr = memaddr + 2; 2038 if (operand->type == OP_PCREL) 2039 { 2040 const struct mips_pcrel_operand *pcrel_op; 2041 2042 pcrel_op = (const struct mips_pcrel_operand *) operand; 2043 if (!pcrel_op->include_isa_bit && use_extend) 2044 baseaddr = memaddr - 2; 2045 else if (!pcrel_op->include_isa_bit) 2046 { 2047 bfd_byte buffer[2]; 2048 2049 /* If this instruction is in the delay slot of a JAL/JALX 2050 instruction, the base address is the address of the 2051 JAL/JALX instruction. If it is in the delay slot of 2052 a JR/JALR instruction, the base address is the address 2053 of the JR/JALR instruction. This test is unreliable: 2054 we have no way of knowing whether the previous word is 2055 instruction or data. */ 2056 if (info->read_memory_func (memaddr - 4, buffer, 2, info) == 0 2057 && (((info->endian == BFD_ENDIAN_BIG 2058 ? bfd_getb16 (buffer) 2059 : bfd_getl16 (buffer)) 2060 & 0xf800) == 0x1800)) 2061 baseaddr = memaddr - 4; 2062 else if (info->read_memory_func (memaddr - 2, buffer, 2, 2063 info) == 0 2064 && (((info->endian == BFD_ENDIAN_BIG 2065 ? bfd_getb16 (buffer) 2066 : bfd_getl16 (buffer)) 2067 & 0xf89f) == 0xe800) 2068 && (((info->endian == BFD_ENDIAN_BIG 2069 ? bfd_getb16 (buffer) 2070 : bfd_getl16 (buffer)) 2071 & 0x0060) != 0x0060)) 2072 baseaddr = memaddr - 2; 2073 else 2074 baseaddr = memaddr; 2075 } 2076 } 2077 2078 print_insn_arg (info, state, opcode, operand, baseaddr + 1, uval); 2079 break; 2080 } 2081 } 2082 2083 2084 /* Check if the given address is the last word of a MIPS16 PLT entry. 2085 This word is data and depending on the value it may interfere with 2086 disassembly of further PLT entries. We make use of the fact PLT 2087 symbols are marked BSF_SYNTHETIC. */ 2088 static bfd_boolean 2089 is_mips16_plt_tail (struct disassemble_info *info, bfd_vma addr) 2090 { 2091 if (info->symbols 2092 && info->symbols[0] 2093 && (info->symbols[0]->flags & BSF_SYNTHETIC) 2094 && addr == bfd_asymbol_value (info->symbols[0]) + 12) 2095 return TRUE; 2096 2097 return FALSE; 2098 } 2099 2100 /* Whether none, a 32-bit or a 16-bit instruction match has been done. */ 2101 2102 enum match_kind 2103 { 2104 MATCH_NONE, 2105 MATCH_FULL, 2106 MATCH_SHORT 2107 }; 2108 2109 /* Disassemble mips16 instructions. */ 2110 2111 static int 2112 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) 2113 { 2114 const fprintf_ftype infprintf = info->fprintf_func; 2115 int status; 2116 bfd_byte buffer[4]; 2117 const struct mips_opcode *op, *opend; 2118 struct mips_print_arg_state state; 2119 void *is = info->stream; 2120 bfd_boolean have_second; 2121 bfd_boolean extend_only; 2122 unsigned int second; 2123 unsigned int first; 2124 unsigned int full; 2125 2126 info->bytes_per_chunk = 2; 2127 info->display_endian = info->endian; 2128 info->insn_info_valid = 1; 2129 info->branch_delay_insns = 0; 2130 info->data_size = 0; 2131 info->target = 0; 2132 info->target2 = 0; 2133 2134 #define GET_OP(insn, field) \ 2135 (((insn) >> MIPS16OP_SH_##field) & MIPS16OP_MASK_##field) 2136 /* Decode PLT entry's GOT slot address word. */ 2137 if (is_mips16_plt_tail (info, memaddr)) 2138 { 2139 info->insn_type = dis_noninsn; 2140 status = (*info->read_memory_func) (memaddr, buffer, 4, info); 2141 if (status == 0) 2142 { 2143 unsigned int gotslot; 2144 2145 if (info->endian == BFD_ENDIAN_BIG) 2146 gotslot = bfd_getb32 (buffer); 2147 else 2148 gotslot = bfd_getl32 (buffer); 2149 infprintf (is, ".word\t0x%x", gotslot); 2150 2151 return 4; 2152 } 2153 } 2154 else 2155 { 2156 info->insn_type = dis_nonbranch; 2157 status = (*info->read_memory_func) (memaddr, buffer, 2, info); 2158 } 2159 if (status != 0) 2160 { 2161 (*info->memory_error_func) (status, memaddr, info); 2162 return -1; 2163 } 2164 2165 extend_only = FALSE; 2166 2167 if (info->endian == BFD_ENDIAN_BIG) 2168 first = bfd_getb16 (buffer); 2169 else 2170 first = bfd_getl16 (buffer); 2171 2172 status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info); 2173 if (status == 0) 2174 { 2175 have_second = TRUE; 2176 if (info->endian == BFD_ENDIAN_BIG) 2177 second = bfd_getb16 (buffer); 2178 else 2179 second = bfd_getl16 (buffer); 2180 full = (first << 16) | second; 2181 } 2182 else 2183 { 2184 have_second = FALSE; 2185 second = 0; 2186 full = first; 2187 } 2188 2189 /* FIXME: Should probably use a hash table on the major opcode here. */ 2190 2191 opend = mips16_opcodes + bfd_mips16_num_opcodes; 2192 for (op = mips16_opcodes; op < opend; op++) 2193 { 2194 enum match_kind match; 2195 2196 if (!opcode_is_member (op, mips_isa, mips_ase, mips_processor)) 2197 continue; 2198 2199 if (op->pinfo == INSN_MACRO 2200 || (no_aliases && (op->pinfo2 & INSN2_ALIAS))) 2201 match = MATCH_NONE; 2202 else if (mips_opcode_32bit_p (op)) 2203 { 2204 if (have_second 2205 && (full & op->mask) == op->match) 2206 match = MATCH_FULL; 2207 else 2208 match = MATCH_NONE; 2209 } 2210 else if ((first & op->mask) == op->match) 2211 { 2212 match = MATCH_SHORT; 2213 second = 0; 2214 full = first; 2215 } 2216 else if ((first & 0xf800) == 0xf000 2217 && have_second 2218 && !extend_only 2219 && (second & op->mask) == op->match) 2220 { 2221 if (op->pinfo2 & INSN2_SHORT_ONLY) 2222 { 2223 match = MATCH_NONE; 2224 extend_only = TRUE; 2225 } 2226 else 2227 match = MATCH_FULL; 2228 } 2229 else 2230 match = MATCH_NONE; 2231 2232 if (match != MATCH_NONE) 2233 { 2234 const char *s; 2235 2236 infprintf (is, "%s", op->name); 2237 if (op->args[0] != '\0') 2238 infprintf (is, "\t"); 2239 2240 init_print_arg_state (&state); 2241 for (s = op->args; *s != '\0'; s++) 2242 { 2243 if (*s == ',' 2244 && s[1] == 'w' 2245 && GET_OP (full, RX) == GET_OP (full, RY)) 2246 { 2247 /* Skip the register and the comma. */ 2248 ++s; 2249 continue; 2250 } 2251 if (*s == ',' 2252 && s[1] == 'v' 2253 && GET_OP (full, RZ) == GET_OP (full, RX)) 2254 { 2255 /* Skip the register and the comma. */ 2256 ++s; 2257 continue; 2258 } 2259 if (s[0] == 'N' 2260 && s[1] == ',' 2261 && s[2] == 'O' 2262 && op->name[strlen (op->name) - 1] == '0') 2263 { 2264 /* Coprocessor register 0 with sel field. */ 2265 const struct mips_cp0sel_name *n; 2266 const struct mips_operand *operand; 2267 unsigned int reg, sel; 2268 2269 operand = decode_mips16_operand (*s, TRUE); 2270 reg = mips_extract_operand (operand, (first << 16) | second); 2271 s += 2; 2272 operand = decode_mips16_operand (*s, TRUE); 2273 sel = mips_extract_operand (operand, (first << 16) | second); 2274 2275 /* CP0 register including 'sel' code for mftc0, to be 2276 printed textually if known. If not known, print both 2277 CP0 register name and sel numerically since CP0 register 2278 with sel 0 may have a name unrelated to register being 2279 printed. */ 2280 n = lookup_mips_cp0sel_name (mips_cp0sel_names, 2281 mips_cp0sel_names_len, 2282 reg, sel); 2283 if (n != NULL) 2284 infprintf (is, "%s", n->name); 2285 else 2286 infprintf (is, "$%d,%d", reg, sel); 2287 } 2288 else 2289 switch (match) 2290 { 2291 case MATCH_FULL: 2292 print_mips16_insn_arg (info, &state, op, *s, memaddr + 2, 2293 second, TRUE, first, s[1] == '('); 2294 break; 2295 case MATCH_SHORT: 2296 print_mips16_insn_arg (info, &state, op, *s, memaddr, 2297 first, FALSE, 0, s[1] == '('); 2298 break; 2299 case MATCH_NONE: /* Stop the compiler complaining. */ 2300 break; 2301 } 2302 } 2303 2304 /* Figure out branch instruction type and delay slot information. */ 2305 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) 2306 info->branch_delay_insns = 1; 2307 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 2308 || (op->pinfo2 & INSN2_UNCOND_BRANCH) != 0) 2309 { 2310 if ((op->pinfo & INSN_WRITE_GPR_31) != 0) 2311 info->insn_type = dis_jsr; 2312 else 2313 info->insn_type = dis_branch; 2314 } 2315 else if ((op->pinfo2 & INSN2_COND_BRANCH) != 0) 2316 info->insn_type = dis_condbranch; 2317 2318 return match == MATCH_FULL ? 4 : 2; 2319 } 2320 } 2321 #undef GET_OP 2322 2323 infprintf (is, "0x%x", first); 2324 info->insn_type = dis_noninsn; 2325 2326 return 2; 2327 } 2328 2329 /* Disassemble microMIPS instructions. */ 2330 2331 static int 2332 print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info) 2333 { 2334 const fprintf_ftype infprintf = info->fprintf_func; 2335 const struct mips_opcode *op, *opend; 2336 void *is = info->stream; 2337 bfd_byte buffer[2]; 2338 unsigned int higher; 2339 unsigned int length; 2340 int status; 2341 unsigned int insn; 2342 2343 info->bytes_per_chunk = 2; 2344 info->display_endian = info->endian; 2345 info->insn_info_valid = 1; 2346 info->branch_delay_insns = 0; 2347 info->data_size = 0; 2348 info->insn_type = dis_nonbranch; 2349 info->target = 0; 2350 info->target2 = 0; 2351 2352 status = (*info->read_memory_func) (memaddr, buffer, 2, info); 2353 if (status != 0) 2354 { 2355 (*info->memory_error_func) (status, memaddr, info); 2356 return -1; 2357 } 2358 2359 length = 2; 2360 2361 if (info->endian == BFD_ENDIAN_BIG) 2362 insn = bfd_getb16 (buffer); 2363 else 2364 insn = bfd_getl16 (buffer); 2365 2366 if ((insn & 0x1c00) == 0x0000 || (insn & 0x1000) == 0x1000) 2367 { 2368 /* This is a 32-bit microMIPS instruction. */ 2369 higher = insn; 2370 2371 status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info); 2372 if (status != 0) 2373 { 2374 infprintf (is, "micromips 0x%x", higher); 2375 (*info->memory_error_func) (status, memaddr + 2, info); 2376 return -1; 2377 } 2378 2379 if (info->endian == BFD_ENDIAN_BIG) 2380 insn = bfd_getb16 (buffer); 2381 else 2382 insn = bfd_getl16 (buffer); 2383 2384 insn = insn | (higher << 16); 2385 2386 length += 2; 2387 } 2388 2389 /* FIXME: Should probably use a hash table on the major opcode here. */ 2390 2391 opend = micromips_opcodes + bfd_micromips_num_opcodes; 2392 for (op = micromips_opcodes; op < opend; op++) 2393 { 2394 if (op->pinfo != INSN_MACRO 2395 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) 2396 && (insn & op->mask) == op->match 2397 && ((length == 2 && (op->mask & 0xffff0000) == 0) 2398 || (length == 4 && (op->mask & 0xffff0000) != 0))) 2399 { 2400 if (!validate_insn_args (op, decode_micromips_operand, insn)) 2401 continue; 2402 2403 infprintf (is, "%s", op->name); 2404 2405 if (op->args[0]) 2406 { 2407 infprintf (is, "\t"); 2408 print_insn_args (info, op, decode_micromips_operand, insn, 2409 memaddr + 1, length); 2410 } 2411 2412 /* Figure out instruction type and branch delay information. */ 2413 if ((op->pinfo 2414 & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY)) != 0) 2415 info->branch_delay_insns = 1; 2416 if (((op->pinfo & INSN_UNCOND_BRANCH_DELAY) 2417 | (op->pinfo2 & INSN2_UNCOND_BRANCH)) != 0) 2418 { 2419 if ((op->pinfo & (INSN_WRITE_GPR_31 | INSN_WRITE_1)) != 0) 2420 info->insn_type = dis_jsr; 2421 else 2422 info->insn_type = dis_branch; 2423 } 2424 else if (((op->pinfo & INSN_COND_BRANCH_DELAY) 2425 | (op->pinfo2 & INSN2_COND_BRANCH)) != 0) 2426 { 2427 if ((op->pinfo & INSN_WRITE_GPR_31) != 0) 2428 info->insn_type = dis_condjsr; 2429 else 2430 info->insn_type = dis_condbranch; 2431 } 2432 else if ((op->pinfo 2433 & (INSN_STORE_MEMORY | INSN_LOAD_MEMORY)) != 0) 2434 info->insn_type = dis_dref; 2435 2436 return length; 2437 } 2438 } 2439 2440 infprintf (is, "0x%x", insn); 2441 info->insn_type = dis_noninsn; 2442 2443 return length; 2444 } 2445 2446 /* Return 1 if a symbol associated with the location being disassembled 2447 indicates a compressed mode, either MIPS16 or microMIPS, according to 2448 MICROMIPS_P. We iterate over all the symbols at the address being 2449 considered assuming if at least one of them indicates code compression, 2450 then such code has been genuinely produced here (other symbols could 2451 have been derived from function symbols defined elsewhere or could 2452 define data). Otherwise, return 0. */ 2453 2454 static bfd_boolean 2455 is_compressed_mode_p (struct disassemble_info *info, bfd_boolean micromips_p) 2456 { 2457 int i; 2458 int l; 2459 2460 for (i = info->symtab_pos, l = i + info->num_symbols; i < l; i++) 2461 if (((info->symtab[i])->flags & BSF_SYNTHETIC) != 0 2462 && ((!micromips_p 2463 && ELF_ST_IS_MIPS16 ((*info->symbols)->udata.i)) 2464 || (micromips_p 2465 && ELF_ST_IS_MICROMIPS ((*info->symbols)->udata.i)))) 2466 return 1; 2467 else if (bfd_asymbol_flavour (info->symtab[i]) == bfd_target_elf_flavour 2468 && info->symtab[i]->section == info->section) 2469 { 2470 elf_symbol_type *symbol = (elf_symbol_type *) info->symtab[i]; 2471 if ((!micromips_p 2472 && ELF_ST_IS_MIPS16 (symbol->internal_elf_sym.st_other)) 2473 || (micromips_p 2474 && ELF_ST_IS_MICROMIPS (symbol->internal_elf_sym.st_other))) 2475 return 1; 2476 } 2477 2478 return 0; 2479 } 2480 2481 /* In an environment where we do not know the symbol type of the 2482 instruction we are forced to assume that the low order bit of the 2483 instructions' address may mark it as a mips16 instruction. If we 2484 are single stepping, or the pc is within the disassembled function, 2485 this works. Otherwise, we need a clue. Sometimes. */ 2486 2487 static int 2488 _print_insn_mips (bfd_vma memaddr, 2489 struct disassemble_info *info, 2490 enum bfd_endian endianness) 2491 { 2492 bfd_byte buffer[INSNLEN]; 2493 int status; 2494 2495 set_default_mips_dis_options (info); 2496 parse_mips_dis_options (info->disassembler_options); 2497 2498 if (info->mach == bfd_mach_mips16) 2499 return print_insn_mips16 (memaddr, info); 2500 if (info->mach == bfd_mach_mips_micromips) 2501 return print_insn_micromips (memaddr, info); 2502 2503 #if 1 2504 /* FIXME: If odd address, this is CLEARLY a compressed instruction. */ 2505 /* Only a few tools will work this way. */ 2506 if (memaddr & 0x01) 2507 { 2508 if (micromips_ase) 2509 return print_insn_micromips (memaddr, info); 2510 else 2511 return print_insn_mips16 (memaddr, info); 2512 } 2513 #endif 2514 2515 #if SYMTAB_AVAILABLE 2516 if (is_compressed_mode_p (info, TRUE)) 2517 return print_insn_micromips (memaddr, info); 2518 if (is_compressed_mode_p (info, FALSE)) 2519 return print_insn_mips16 (memaddr, info); 2520 #endif 2521 2522 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info); 2523 if (status == 0) 2524 { 2525 int insn; 2526 2527 if (endianness == BFD_ENDIAN_BIG) 2528 insn = bfd_getb32 (buffer); 2529 else 2530 insn = bfd_getl32 (buffer); 2531 2532 return print_insn_mips (memaddr, insn, info); 2533 } 2534 else 2535 { 2536 (*info->memory_error_func) (status, memaddr, info); 2537 return -1; 2538 } 2539 } 2540 2541 int 2542 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info) 2543 { 2544 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG); 2545 } 2546 2547 int 2548 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info) 2549 { 2550 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE); 2551 } 2552 2553 void 2555 print_mips_disassembler_options (FILE *stream) 2556 { 2557 unsigned int i; 2558 2559 fprintf (stream, _("\n\ 2560 The following MIPS specific disassembler options are supported for use\n\ 2561 with the -M switch (multiple options should be separated by commas):\n")); 2562 2563 fprintf (stream, _("\n\ 2564 no-aliases Use canonical instruction forms.\n")); 2565 2566 fprintf (stream, _("\n\ 2567 msa Recognize MSA instructions.\n")); 2568 2569 fprintf (stream, _("\n\ 2570 virt Recognize the virtualization ASE instructions.\n")); 2571 2572 fprintf (stream, _("\n\ 2573 xpa Recognize the eXtended Physical Address (XPA)\n\ 2574 ASE instructions.\n")); 2575 2576 fprintf (stream, _("\n\ 2577 gpr-names=ABI Print GPR names according to specified ABI.\n\ 2578 Default: based on binary being disassembled.\n")); 2579 2580 fprintf (stream, _("\n\ 2581 fpr-names=ABI Print FPR names according to specified ABI.\n\ 2582 Default: numeric.\n")); 2583 2584 fprintf (stream, _("\n\ 2585 cp0-names=ARCH Print CP0 register names according to\n\ 2586 specified architecture.\n\ 2587 Default: based on binary being disassembled.\n")); 2588 2589 fprintf (stream, _("\n\ 2590 hwr-names=ARCH Print HWR names according to specified \n\ 2591 architecture.\n\ 2592 Default: based on binary being disassembled.\n")); 2593 2594 fprintf (stream, _("\n\ 2595 reg-names=ABI Print GPR and FPR names according to\n\ 2596 specified ABI.\n")); 2597 2598 fprintf (stream, _("\n\ 2599 reg-names=ARCH Print CP0 register and HWR names according to\n\ 2600 specified architecture.\n")); 2601 2602 fprintf (stream, _("\n\ 2603 For the options above, the following values are supported for \"ABI\":\n\ 2604 ")); 2605 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++) 2606 fprintf (stream, " %s", mips_abi_choices[i].name); 2607 fprintf (stream, _("\n")); 2608 2609 fprintf (stream, _("\n\ 2610 For the options above, The following values are supported for \"ARCH\":\n\ 2611 ")); 2612 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++) 2613 if (*mips_arch_choices[i].name != '\0') 2614 fprintf (stream, " %s", mips_arch_choices[i].name); 2615 fprintf (stream, _("\n")); 2616 2617 fprintf (stream, _("\n")); 2618 } 2619
Indexes created Tue Mar 31 00:22:50 UTC 2026