mips-dis.c revision 1.8
1 /* Print mips instructions for GDB, the GNU debugger, or for objdump. 2 Copyright (C) 1989-2018 Free Software Foundation, Inc. 3 Contributed by Nobuyuki Hikichi(hikichi (at) sra.co.jp). 4 5 This file is part of the GNU opcodes library. 6 7 This library is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 It is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; if not, write to the Free Software 19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 20 MA 02110-1301, USA. */ 21 22 #include "sysdep.h" 23 #include "disassemble.h" 24 #include "libiberty.h" 25 #include "opcode/mips.h" 26 #include "opintl.h" 27 28 /* FIXME: These are needed to figure out if the code is mips16 or 29 not. The low bit of the address is often a good indicator. No 30 symbol table is available when this code runs out in an embedded 31 system as when it is used for disassembler support in a monitor. */ 32 33 #if !defined(EMBEDDED_ENV) 34 #define SYMTAB_AVAILABLE 1 35 #include "elf-bfd.h" 36 #include "elf/mips.h" 37 #endif 38 39 /* Mips instructions are at maximum this many bytes long. */ 40 #define INSNLEN 4 41 42 43 /* FIXME: These should be shared with gdb somehow. */ 45 46 struct mips_cp0sel_name 47 { 48 unsigned int cp0reg; 49 unsigned int sel; 50 const char * const name; 51 }; 52 53 static const char * const mips_gpr_names_numeric[32] = 54 { 55 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 56 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 57 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 58 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 59 }; 60 61 static const char * const mips_gpr_names_oldabi[32] = 62 { 63 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 64 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", 65 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 66 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 67 }; 68 69 static const char * const mips_gpr_names_newabi[32] = 70 { 71 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 72 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", 73 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 74 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 75 }; 76 77 static const char * const mips_fpr_names_numeric[32] = 78 { 79 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 80 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 81 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 82 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31" 83 }; 84 85 static const char * const mips_fpr_names_32[32] = 86 { 87 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f", 88 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f", 89 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f", 90 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f" 91 }; 92 93 static const char * const mips_fpr_names_n32[32] = 94 { 95 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3", 96 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", 97 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9", 98 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13" 99 }; 100 101 static const char * const mips_fpr_names_64[32] = 102 { 103 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3", 104 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", 105 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11", 106 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7" 107 }; 108 109 static const char * const mips_cp0_names_numeric[32] = 110 { 111 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 112 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 113 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 114 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 115 }; 116 117 static const char * const mips_cp1_names_numeric[32] = 118 { 119 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 120 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 121 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 122 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 123 }; 124 125 static const char * const mips_cp0_names_r3000[32] = 126 { 127 "c0_index", "c0_random", "c0_entrylo", "$3", 128 "c0_context", "$5", "$6", "$7", 129 "c0_badvaddr", "$9", "c0_entryhi", "$11", 130 "c0_sr", "c0_cause", "c0_epc", "c0_prid", 131 "$16", "$17", "$18", "$19", 132 "$20", "$21", "$22", "$23", 133 "$24", "$25", "$26", "$27", 134 "$28", "$29", "$30", "$31", 135 }; 136 137 static const char * const mips_cp0_names_r4000[32] = 138 { 139 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 140 "c0_context", "c0_pagemask", "c0_wired", "$7", 141 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 142 "c0_sr", "c0_cause", "c0_epc", "c0_prid", 143 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 144 "c0_xcontext", "$21", "$22", "$23", 145 "$24", "$25", "c0_ecc", "c0_cacheerr", 146 "c0_taglo", "c0_taghi", "c0_errorepc", "$31", 147 }; 148 149 static const char * const mips_cp0_names_r5900[32] = 150 { 151 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 152 "c0_context", "c0_pagemask", "c0_wired", "$7", 153 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 154 "c0_sr", "c0_cause", "c0_epc", "c0_prid", 155 "c0_config", "$17", "$18", "$19", 156 "$20", "$21", "$22", "c0_badpaddr", 157 "c0_depc", "c0_perfcnt", "$26", "$27", 158 "c0_taglo", "c0_taghi", "c0_errorepc", "$31" 159 }; 160 161 static const char * const mips_cp0_names_mips3264[32] = 162 { 163 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 164 "c0_context", "c0_pagemask", "c0_wired", "$7", 165 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 166 "c0_status", "c0_cause", "c0_epc", "c0_prid", 167 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 168 "c0_xcontext", "$21", "$22", "c0_debug", 169 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", 170 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", 171 }; 172 173 static const char * const mips_cp1_names_mips3264[32] = 174 { 175 "c1_fir", "c1_ufr", "$2", "$3", 176 "c1_unfr", "$5", "$6", "$7", 177 "$8", "$9", "$10", "$11", 178 "$12", "$13", "$14", "$15", 179 "$16", "$17", "$18", "$19", 180 "$20", "$21", "$22", "$23", 181 "$24", "c1_fccr", "c1_fexr", "$27", 182 "c1_fenr", "$29", "$30", "c1_fcsr" 183 }; 184 185 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = 186 { 187 { 16, 1, "c0_config1" }, 188 { 16, 2, "c0_config2" }, 189 { 16, 3, "c0_config3" }, 190 { 18, 1, "c0_watchlo,1" }, 191 { 18, 2, "c0_watchlo,2" }, 192 { 18, 3, "c0_watchlo,3" }, 193 { 18, 4, "c0_watchlo,4" }, 194 { 18, 5, "c0_watchlo,5" }, 195 { 18, 6, "c0_watchlo,6" }, 196 { 18, 7, "c0_watchlo,7" }, 197 { 19, 1, "c0_watchhi,1" }, 198 { 19, 2, "c0_watchhi,2" }, 199 { 19, 3, "c0_watchhi,3" }, 200 { 19, 4, "c0_watchhi,4" }, 201 { 19, 5, "c0_watchhi,5" }, 202 { 19, 6, "c0_watchhi,6" }, 203 { 19, 7, "c0_watchhi,7" }, 204 { 25, 1, "c0_perfcnt,1" }, 205 { 25, 2, "c0_perfcnt,2" }, 206 { 25, 3, "c0_perfcnt,3" }, 207 { 25, 4, "c0_perfcnt,4" }, 208 { 25, 5, "c0_perfcnt,5" }, 209 { 25, 6, "c0_perfcnt,6" }, 210 { 25, 7, "c0_perfcnt,7" }, 211 { 27, 1, "c0_cacheerr,1" }, 212 { 27, 2, "c0_cacheerr,2" }, 213 { 27, 3, "c0_cacheerr,3" }, 214 { 28, 1, "c0_datalo" }, 215 { 29, 1, "c0_datahi" } 216 }; 217 218 static const char * const mips_cp0_names_mips3264r2[32] = 219 { 220 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 221 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena", 222 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 223 "c0_status", "c0_cause", "c0_epc", "c0_prid", 224 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 225 "c0_xcontext", "$21", "$22", "c0_debug", 226 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", 227 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", 228 }; 229 230 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = 231 { 232 { 4, 1, "c0_contextconfig" }, 233 { 0, 1, "c0_mvpcontrol" }, 234 { 0, 2, "c0_mvpconf0" }, 235 { 0, 3, "c0_mvpconf1" }, 236 { 1, 1, "c0_vpecontrol" }, 237 { 1, 2, "c0_vpeconf0" }, 238 { 1, 3, "c0_vpeconf1" }, 239 { 1, 4, "c0_yqmask" }, 240 { 1, 5, "c0_vpeschedule" }, 241 { 1, 6, "c0_vpeschefback" }, 242 { 2, 1, "c0_tcstatus" }, 243 { 2, 2, "c0_tcbind" }, 244 { 2, 3, "c0_tcrestart" }, 245 { 2, 4, "c0_tchalt" }, 246 { 2, 5, "c0_tccontext" }, 247 { 2, 6, "c0_tcschedule" }, 248 { 2, 7, "c0_tcschefback" }, 249 { 5, 1, "c0_pagegrain" }, 250 { 6, 1, "c0_srsconf0" }, 251 { 6, 2, "c0_srsconf1" }, 252 { 6, 3, "c0_srsconf2" }, 253 { 6, 4, "c0_srsconf3" }, 254 { 6, 5, "c0_srsconf4" }, 255 { 12, 1, "c0_intctl" }, 256 { 12, 2, "c0_srsctl" }, 257 { 12, 3, "c0_srsmap" }, 258 { 15, 1, "c0_ebase" }, 259 { 16, 1, "c0_config1" }, 260 { 16, 2, "c0_config2" }, 261 { 16, 3, "c0_config3" }, 262 { 18, 1, "c0_watchlo,1" }, 263 { 18, 2, "c0_watchlo,2" }, 264 { 18, 3, "c0_watchlo,3" }, 265 { 18, 4, "c0_watchlo,4" }, 266 { 18, 5, "c0_watchlo,5" }, 267 { 18, 6, "c0_watchlo,6" }, 268 { 18, 7, "c0_watchlo,7" }, 269 { 19, 1, "c0_watchhi,1" }, 270 { 19, 2, "c0_watchhi,2" }, 271 { 19, 3, "c0_watchhi,3" }, 272 { 19, 4, "c0_watchhi,4" }, 273 { 19, 5, "c0_watchhi,5" }, 274 { 19, 6, "c0_watchhi,6" }, 275 { 19, 7, "c0_watchhi,7" }, 276 { 23, 1, "c0_tracecontrol" }, 277 { 23, 2, "c0_tracecontrol2" }, 278 { 23, 3, "c0_usertracedata" }, 279 { 23, 4, "c0_tracebpc" }, 280 { 25, 1, "c0_perfcnt,1" }, 281 { 25, 2, "c0_perfcnt,2" }, 282 { 25, 3, "c0_perfcnt,3" }, 283 { 25, 4, "c0_perfcnt,4" }, 284 { 25, 5, "c0_perfcnt,5" }, 285 { 25, 6, "c0_perfcnt,6" }, 286 { 25, 7, "c0_perfcnt,7" }, 287 { 27, 1, "c0_cacheerr,1" }, 288 { 27, 2, "c0_cacheerr,2" }, 289 { 27, 3, "c0_cacheerr,3" }, 290 { 28, 1, "c0_datalo" }, 291 { 28, 2, "c0_taglo1" }, 292 { 28, 3, "c0_datalo1" }, 293 { 28, 4, "c0_taglo2" }, 294 { 28, 5, "c0_datalo2" }, 295 { 28, 6, "c0_taglo3" }, 296 { 28, 7, "c0_datalo3" }, 297 { 29, 1, "c0_datahi" }, 298 { 29, 2, "c0_taghi1" }, 299 { 29, 3, "c0_datahi1" }, 300 { 29, 4, "c0_taghi2" }, 301 { 29, 5, "c0_datahi2" }, 302 { 29, 6, "c0_taghi3" }, 303 { 29, 7, "c0_datahi3" }, 304 }; 305 306 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */ 307 static const char * const mips_cp0_names_sb1[32] = 308 { 309 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 310 "c0_context", "c0_pagemask", "c0_wired", "$7", 311 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 312 "c0_status", "c0_cause", "c0_epc", "c0_prid", 313 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 314 "c0_xcontext", "$21", "$22", "c0_debug", 315 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i", 316 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave", 317 }; 318 319 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = 320 { 321 { 16, 1, "c0_config1" }, 322 { 18, 1, "c0_watchlo,1" }, 323 { 19, 1, "c0_watchhi,1" }, 324 { 22, 0, "c0_perftrace" }, 325 { 23, 3, "c0_edebug" }, 326 { 25, 1, "c0_perfcnt,1" }, 327 { 25, 2, "c0_perfcnt,2" }, 328 { 25, 3, "c0_perfcnt,3" }, 329 { 25, 4, "c0_perfcnt,4" }, 330 { 25, 5, "c0_perfcnt,5" }, 331 { 25, 6, "c0_perfcnt,6" }, 332 { 25, 7, "c0_perfcnt,7" }, 333 { 26, 1, "c0_buserr_pa" }, 334 { 27, 1, "c0_cacheerr_d" }, 335 { 27, 3, "c0_cacheerr_d_pa" }, 336 { 28, 1, "c0_datalo_i" }, 337 { 28, 2, "c0_taglo_d" }, 338 { 28, 3, "c0_datalo_d" }, 339 { 29, 1, "c0_datahi_i" }, 340 { 29, 2, "c0_taghi_d" }, 341 { 29, 3, "c0_datahi_d" }, 342 }; 343 344 /* Xlr cop0 register names. */ 345 static const char * const mips_cp0_names_xlr[32] = { 346 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 347 "c0_context", "c0_pagemask", "c0_wired", "$7", 348 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 349 "c0_status", "c0_cause", "c0_epc", "c0_prid", 350 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 351 "c0_xcontext", "$21", "$22", "c0_debug", 352 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i", 353 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave", 354 }; 355 356 /* XLR's CP0 Select Registers. */ 357 358 static const struct mips_cp0sel_name mips_cp0sel_names_xlr[] = { 359 { 9, 6, "c0_extintreq" }, 360 { 9, 7, "c0_extintmask" }, 361 { 15, 1, "c0_ebase" }, 362 { 16, 1, "c0_config1" }, 363 { 16, 2, "c0_config2" }, 364 { 16, 3, "c0_config3" }, 365 { 16, 7, "c0_procid2" }, 366 { 18, 1, "c0_watchlo,1" }, 367 { 18, 2, "c0_watchlo,2" }, 368 { 18, 3, "c0_watchlo,3" }, 369 { 18, 4, "c0_watchlo,4" }, 370 { 18, 5, "c0_watchlo,5" }, 371 { 18, 6, "c0_watchlo,6" }, 372 { 18, 7, "c0_watchlo,7" }, 373 { 19, 1, "c0_watchhi,1" }, 374 { 19, 2, "c0_watchhi,2" }, 375 { 19, 3, "c0_watchhi,3" }, 376 { 19, 4, "c0_watchhi,4" }, 377 { 19, 5, "c0_watchhi,5" }, 378 { 19, 6, "c0_watchhi,6" }, 379 { 19, 7, "c0_watchhi,7" }, 380 { 25, 1, "c0_perfcnt,1" }, 381 { 25, 2, "c0_perfcnt,2" }, 382 { 25, 3, "c0_perfcnt,3" }, 383 { 25, 4, "c0_perfcnt,4" }, 384 { 25, 5, "c0_perfcnt,5" }, 385 { 25, 6, "c0_perfcnt,6" }, 386 { 25, 7, "c0_perfcnt,7" }, 387 { 27, 1, "c0_cacheerr,1" }, 388 { 27, 2, "c0_cacheerr,2" }, 389 { 27, 3, "c0_cacheerr,3" }, 390 { 28, 1, "c0_datalo" }, 391 { 29, 1, "c0_datahi" } 392 }; 393 394 static const char * const mips_hwr_names_numeric[32] = 395 { 396 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 397 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 398 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 399 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 400 }; 401 402 static const char * const mips_hwr_names_mips3264r2[32] = 403 { 404 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres", 405 "$4", "$5", "$6", "$7", 406 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 407 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 408 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 409 }; 410 411 static const char * const msa_control_names[32] = 412 { 413 "msa_ir", "msa_csr", "msa_access", "msa_save", 414 "msa_modify", "msa_request", "msa_map", "msa_unmap", 415 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 416 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 417 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 418 }; 419 420 struct mips_abi_choice 421 { 422 const char * name; 423 const char * const *gpr_names; 424 const char * const *fpr_names; 425 }; 426 427 struct mips_abi_choice mips_abi_choices[] = 428 { 429 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric }, 430 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 }, 431 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 }, 432 { "64", mips_gpr_names_newabi, mips_fpr_names_64 }, 433 }; 434 435 struct mips_arch_choice 436 { 437 const char *name; 438 int bfd_mach_valid; 439 unsigned long bfd_mach; 440 int processor; 441 int isa; 442 int ase; 443 const char * const *cp0_names; 444 const struct mips_cp0sel_name *cp0sel_names; 445 unsigned int cp0sel_names_len; 446 const char * const *cp1_names; 447 const char * const *hwr_names; 448 }; 449 450 const struct mips_arch_choice mips_arch_choices[] = 451 { 452 { "numeric", 0, 0, 0, 0, 0, 453 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 454 mips_hwr_names_numeric }, 455 456 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, 0, 457 mips_cp0_names_r3000, NULL, 0, mips_cp1_names_numeric, 458 mips_hwr_names_numeric }, 459 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, 0, 460 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 461 mips_hwr_names_numeric }, 462 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, 0, 463 mips_cp0_names_r4000, NULL, 0, mips_cp1_names_numeric, 464 mips_hwr_names_numeric }, 465 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, 0, 466 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 467 mips_hwr_names_numeric }, 468 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, 0, 469 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 470 mips_hwr_names_numeric }, 471 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, 0, 472 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 473 mips_hwr_names_numeric }, 474 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, 0, 475 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 476 mips_hwr_names_numeric }, 477 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, 0, 478 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 479 mips_hwr_names_numeric }, 480 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, 0, 481 mips_cp0_names_r4000, NULL, 0, mips_cp1_names_numeric, 482 mips_hwr_names_numeric }, 483 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, 0, 484 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 485 mips_hwr_names_numeric }, 486 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, 0, 487 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 488 mips_hwr_names_numeric }, 489 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, 0, 490 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 491 mips_hwr_names_numeric }, 492 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, 0, 493 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 494 mips_hwr_names_numeric }, 495 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, 0, 496 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 497 mips_hwr_names_numeric }, 498 { "r5900", 1, bfd_mach_mips5900, CPU_R5900, ISA_MIPS3, 0, 499 mips_cp0_names_r5900, NULL, 0, mips_cp1_names_numeric, 500 mips_hwr_names_numeric }, 501 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, 0, 502 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 503 mips_hwr_names_numeric }, 504 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0, 505 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 506 mips_hwr_names_numeric }, 507 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0, 508 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 509 mips_hwr_names_numeric }, 510 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, 0, 511 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 512 mips_hwr_names_numeric }, 513 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, 0, 514 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 515 mips_hwr_names_numeric }, 516 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, 0, 517 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 518 mips_hwr_names_numeric }, 519 { "r14000", 1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4, 0, 520 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 521 mips_hwr_names_numeric }, 522 { "r16000", 1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4, 0, 523 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 524 mips_hwr_names_numeric }, 525 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, 0, 526 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 527 mips_hwr_names_numeric }, 528 529 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs. 530 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See 531 _MIPS32 Architecture For Programmers Volume I: Introduction to the 532 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95), 533 page 1. */ 534 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32, 535 ISA_MIPS32, ASE_SMARTMIPS, 536 mips_cp0_names_mips3264, 537 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), 538 mips_cp1_names_mips3264, mips_hwr_names_numeric }, 539 540 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2, 541 ISA_MIPS32R2, 542 (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D 543 | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA), 544 mips_cp0_names_mips3264r2, 545 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 546 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, 547 548 { "mips32r3", 1, bfd_mach_mipsisa32r3, CPU_MIPS32R3, 549 ISA_MIPS32R3, 550 (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D 551 | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA), 552 mips_cp0_names_mips3264r2, 553 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 554 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, 555 556 { "mips32r5", 1, bfd_mach_mipsisa32r5, CPU_MIPS32R5, 557 ISA_MIPS32R5, 558 (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D 559 | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA), 560 mips_cp0_names_mips3264r2, 561 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 562 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, 563 564 { "mips32r6", 1, bfd_mach_mipsisa32r6, CPU_MIPS32R6, 565 ISA_MIPS32R6, 566 (ASE_EVA | ASE_MSA | ASE_VIRT | ASE_XPA | ASE_MCU | ASE_MT | ASE_DSP 567 | ASE_DSPR2 | ASE_DSPR3 | ASE_CRC | ASE_GINV), 568 mips_cp0_names_mips3264r2, 569 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 570 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, 571 572 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */ 573 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64, 574 ISA_MIPS64, ASE_MIPS3D | ASE_MDMX, 575 mips_cp0_names_mips3264, 576 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), 577 mips_cp1_names_mips3264, mips_hwr_names_numeric }, 578 579 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2, 580 ISA_MIPS64R2, 581 (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT 582 | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA), 583 mips_cp0_names_mips3264r2, 584 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 585 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, 586 587 { "mips64r3", 1, bfd_mach_mipsisa64r3, CPU_MIPS64R3, 588 ISA_MIPS64R3, 589 (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT 590 | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA), 591 mips_cp0_names_mips3264r2, 592 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 593 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, 594 595 { "mips64r5", 1, bfd_mach_mipsisa64r5, CPU_MIPS64R5, 596 ISA_MIPS64R5, 597 (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT 598 | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA), 599 mips_cp0_names_mips3264r2, 600 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 601 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, 602 603 { "mips64r6", 1, bfd_mach_mipsisa64r6, CPU_MIPS64R6, 604 ISA_MIPS64R6, 605 (ASE_EVA | ASE_MSA | ASE_MSA64 | ASE_XPA | ASE_VIRT | ASE_VIRT64 606 | ASE_MCU | ASE_MT | ASE_DSP | ASE_DSPR2 | ASE_DSPR3 | ASE_CRC 607 | ASE_CRC64 | ASE_GINV), 608 mips_cp0_names_mips3264r2, 609 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 610 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, 611 612 { "interaptiv-mr2", 1, bfd_mach_mips_interaptiv_mr2, CPU_INTERAPTIV_MR2, 613 ISA_MIPS32R3, 614 ASE_MT | ASE_EVA | ASE_DSP | ASE_DSPR2 | ASE_MIPS16E2 | ASE_MIPS16E2_MT, 615 mips_cp0_names_mips3264r2, 616 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 617 mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, 618 619 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1, 620 ISA_MIPS64 | INSN_SB1, ASE_MIPS3D, 621 mips_cp0_names_sb1, 622 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1), 623 mips_cp1_names_mips3264, mips_hwr_names_numeric }, 624 625 { "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E, 626 ISA_MIPS3 | INSN_LOONGSON_2E, 0, mips_cp0_names_numeric, 627 NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric }, 628 629 { "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F, 630 ISA_MIPS3 | INSN_LOONGSON_2F, 0, mips_cp0_names_numeric, 631 NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric }, 632 633 { "loongson3a", 1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A, 634 ISA_MIPS64R2 | INSN_LOONGSON_3A, 0, mips_cp0_names_numeric, 635 NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric }, 636 637 { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON, 638 ISA_MIPS64R2 | INSN_OCTEON, 0, mips_cp0_names_numeric, NULL, 0, 639 mips_cp1_names_mips3264, mips_hwr_names_numeric }, 640 641 { "octeon+", 1, bfd_mach_mips_octeonp, CPU_OCTEONP, 642 ISA_MIPS64R2 | INSN_OCTEONP, 0, mips_cp0_names_numeric, 643 NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric }, 644 645 { "octeon2", 1, bfd_mach_mips_octeon2, CPU_OCTEON2, 646 ISA_MIPS64R2 | INSN_OCTEON2, 0, mips_cp0_names_numeric, 647 NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric }, 648 649 { "octeon3", 1, bfd_mach_mips_octeon3, CPU_OCTEON3, 650 ISA_MIPS64R5 | INSN_OCTEON3, ASE_VIRT | ASE_VIRT64, 651 mips_cp0_names_numeric, 652 NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric }, 653 654 { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR, 655 ISA_MIPS64 | INSN_XLR, 0, 656 mips_cp0_names_xlr, 657 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr), 658 mips_cp1_names_mips3264, mips_hwr_names_numeric }, 659 660 /* XLP is mostly like XLR, with the prominent exception it is being 661 MIPS64R2. */ 662 { "xlp", 1, bfd_mach_mips_xlr, CPU_XLR, 663 ISA_MIPS64R2 | INSN_XLR, 0, 664 mips_cp0_names_xlr, 665 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr), 666 mips_cp1_names_mips3264, mips_hwr_names_numeric }, 667 668 /* This entry, mips16, is here only for ISA/processor selection; do 669 not print its name. */ 670 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS64, 671 ASE_MIPS16E2 | ASE_MIPS16E2_MT, 672 mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, 673 mips_hwr_names_numeric }, 674 }; 675 676 /* ISA and processor type to disassemble for, and register names to use. 677 set_default_mips_dis_options and parse_mips_dis_options fill in these 678 values. */ 679 static int mips_processor; 680 static int mips_isa; 681 static int mips_ase; 682 static int micromips_ase; 683 static const char * const *mips_gpr_names; 684 static const char * const *mips_fpr_names; 685 static const char * const *mips_cp0_names; 686 static const struct mips_cp0sel_name *mips_cp0sel_names; 687 static int mips_cp0sel_names_len; 688 static const char * const *mips_cp1_names; 689 static const char * const *mips_hwr_names; 690 691 /* Other options */ 692 static int no_aliases; /* If set disassemble as most general inst. */ 693 694 static const struct mips_abi_choice * 696 choose_abi_by_name (const char *name, unsigned int namelen) 697 { 698 const struct mips_abi_choice *c; 699 unsigned int i; 700 701 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++) 702 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0 703 && strlen (mips_abi_choices[i].name) == namelen) 704 c = &mips_abi_choices[i]; 705 706 return c; 707 } 708 709 static const struct mips_arch_choice * 710 choose_arch_by_name (const char *name, unsigned int namelen) 711 { 712 const struct mips_arch_choice *c = NULL; 713 unsigned int i; 714 715 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) 716 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0 717 && strlen (mips_arch_choices[i].name) == namelen) 718 c = &mips_arch_choices[i]; 719 720 return c; 721 } 722 723 static const struct mips_arch_choice * 724 choose_arch_by_number (unsigned long mach) 725 { 726 static unsigned long hint_bfd_mach; 727 static const struct mips_arch_choice *hint_arch_choice; 728 const struct mips_arch_choice *c; 729 unsigned int i; 730 731 /* We optimize this because even if the user specifies no 732 flags, this will be done for every instruction! */ 733 if (hint_bfd_mach == mach 734 && hint_arch_choice != NULL 735 && hint_arch_choice->bfd_mach == hint_bfd_mach) 736 return hint_arch_choice; 737 738 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) 739 { 740 if (mips_arch_choices[i].bfd_mach_valid 741 && mips_arch_choices[i].bfd_mach == mach) 742 { 743 c = &mips_arch_choices[i]; 744 hint_bfd_mach = mach; 745 hint_arch_choice = c; 746 } 747 } 748 return c; 749 } 750 751 /* Check if the object uses NewABI conventions. */ 752 753 static int 754 is_newabi (Elf_Internal_Ehdr *header) 755 { 756 /* There are no old-style ABIs which use 64-bit ELF. */ 757 if (header->e_ident[EI_CLASS] == ELFCLASS64) 758 return 1; 759 760 /* If a 32-bit ELF file, n32 is a new-style ABI. */ 761 if ((header->e_flags & EF_MIPS_ABI2) != 0) 762 return 1; 763 764 return 0; 765 } 766 767 /* Check if the object has microMIPS ASE code. */ 768 769 static int 770 is_micromips (Elf_Internal_Ehdr *header) 771 { 772 if ((header->e_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0) 773 return 1; 774 775 return 0; 776 } 777 778 /* Convert ASE flags from .MIPS.abiflags to internal values. */ 779 780 static unsigned long 781 mips_convert_abiflags_ases (unsigned long afl_ases) 782 { 783 unsigned long opcode_ases = 0; 784 785 if (afl_ases & AFL_ASE_DSP) 786 opcode_ases |= ASE_DSP; 787 if (afl_ases & AFL_ASE_DSPR2) 788 opcode_ases |= ASE_DSPR2; 789 if (afl_ases & AFL_ASE_EVA) 790 opcode_ases |= ASE_EVA; 791 if (afl_ases & AFL_ASE_MCU) 792 opcode_ases |= ASE_MCU; 793 if (afl_ases & AFL_ASE_MDMX) 794 opcode_ases |= ASE_MDMX; 795 if (afl_ases & AFL_ASE_MIPS3D) 796 opcode_ases |= ASE_MIPS3D; 797 if (afl_ases & AFL_ASE_MT) 798 opcode_ases |= ASE_MT; 799 if (afl_ases & AFL_ASE_SMARTMIPS) 800 opcode_ases |= ASE_SMARTMIPS; 801 if (afl_ases & AFL_ASE_VIRT) 802 opcode_ases |= ASE_VIRT; 803 if (afl_ases & AFL_ASE_MSA) 804 opcode_ases |= ASE_MSA; 805 if (afl_ases & AFL_ASE_XPA) 806 opcode_ases |= ASE_XPA; 807 if (afl_ases & AFL_ASE_DSPR3) 808 opcode_ases |= ASE_DSPR3; 809 if (afl_ases & AFL_ASE_MIPS16E2) 810 opcode_ases |= ASE_MIPS16E2; 811 return opcode_ases; 812 } 813 814 /* Calculate combination ASE flags from regular ASE flags. */ 815 816 static unsigned long 817 mips_calculate_combination_ases (unsigned long opcode_ases) 818 { 819 unsigned long combination_ases = 0; 820 821 if ((opcode_ases & (ASE_XPA | ASE_VIRT)) == (ASE_XPA | ASE_VIRT)) 822 combination_ases |= ASE_XPA_VIRT; 823 if ((opcode_ases & (ASE_MIPS16E2 | ASE_MT)) == (ASE_MIPS16E2 | ASE_MT)) 824 combination_ases |= ASE_MIPS16E2_MT; 825 return combination_ases; 826 } 827 828 static void 829 set_default_mips_dis_options (struct disassemble_info *info) 830 { 831 const struct mips_arch_choice *chosen_arch; 832 833 /* Defaults: mipsIII/r3000 (?!), no microMIPS ASE (any compressed code 834 is MIPS16 ASE) (o)32-style ("oldabi") GPR names, and numeric FPR, 835 CP0 register, and HWR names. */ 836 mips_isa = ISA_MIPS3; 837 mips_processor = CPU_R3000; 838 micromips_ase = 0; 839 mips_ase = 0; 840 mips_gpr_names = mips_gpr_names_oldabi; 841 mips_fpr_names = mips_fpr_names_numeric; 842 mips_cp0_names = mips_cp0_names_numeric; 843 mips_cp0sel_names = NULL; 844 mips_cp0sel_names_len = 0; 845 mips_cp1_names = mips_cp1_names_numeric; 846 mips_hwr_names = mips_hwr_names_numeric; 847 no_aliases = 0; 848 849 /* Set ISA, architecture, and cp0 register names as best we can. */ 850 #if ! SYMTAB_AVAILABLE 851 /* This is running out on a target machine, not in a host tool. 852 FIXME: Where does mips_target_info come from? */ 853 target_processor = mips_target_info.processor; 854 mips_isa = mips_target_info.isa; 855 mips_ase = mips_target_info.ase; 856 #else 857 chosen_arch = choose_arch_by_number (info->mach); 858 if (chosen_arch != NULL) 859 { 860 mips_processor = chosen_arch->processor; 861 mips_isa = chosen_arch->isa; 862 mips_ase = chosen_arch->ase; 863 mips_cp0_names = chosen_arch->cp0_names; 864 mips_cp0sel_names = chosen_arch->cp0sel_names; 865 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 866 mips_cp1_names = chosen_arch->cp1_names; 867 mips_hwr_names = chosen_arch->hwr_names; 868 } 869 870 /* Update settings according to the ELF file header flags. */ 871 if (info->flavour == bfd_target_elf_flavour && info->section != NULL) 872 { 873 struct bfd *abfd = info->section->owner; 874 Elf_Internal_Ehdr *header = elf_elfheader (abfd); 875 Elf_Internal_ABIFlags_v0 *abiflags = NULL; 876 877 /* We won't ever get here if !HAVE_BFD_MIPS_ELF_GET_ABIFLAGS, 878 because we won't then have a MIPS/ELF BFD, however we need 879 to guard against a link error in a `--enable-targets=...' 880 configuration with a 32-bit host where the MIPS target is 881 a secondary, or with MIPS/ECOFF configurations. */ 882 #ifdef HAVE_BFD_MIPS_ELF_GET_ABIFLAGS 883 abiflags = bfd_mips_elf_get_abiflags (abfd); 884 #endif 885 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */ 886 if (is_newabi (header)) 887 mips_gpr_names = mips_gpr_names_newabi; 888 /* If a microMIPS binary, then don't use MIPS16 bindings. */ 889 micromips_ase = is_micromips (header); 890 /* OR in any extra ASE flags set in ELF file structures. */ 891 if (abiflags) 892 mips_ase |= mips_convert_abiflags_ases (abiflags->ases); 893 else if (header->e_flags & EF_MIPS_ARCH_ASE_MDMX) 894 mips_ase |= ASE_MDMX; 895 } 896 #endif 897 mips_ase |= mips_calculate_combination_ases (mips_ase); 898 } 899 900 /* Parse an ASE disassembler option and set the corresponding global 901 ASE flag(s). Return TRUE if successful, FALSE otherwise. */ 902 903 static bfd_boolean 904 parse_mips_ase_option (const char *option) 905 { 906 if (CONST_STRNEQ (option, "msa")) 907 { 908 mips_ase |= ASE_MSA; 909 if ((mips_isa & INSN_ISA_MASK) == ISA_MIPS64R2 910 || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R3 911 || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R5 912 || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R6) 913 mips_ase |= ASE_MSA64; 914 return TRUE; 915 } 916 917 if (CONST_STRNEQ (option, "virt")) 918 { 919 mips_ase |= ASE_VIRT; 920 if (mips_isa & ISA_MIPS64R2 921 || mips_isa & ISA_MIPS64R3 922 || mips_isa & ISA_MIPS64R5 923 || mips_isa & ISA_MIPS64R6) 924 mips_ase |= ASE_VIRT64; 925 return TRUE; 926 } 927 928 if (CONST_STRNEQ (option, "xpa")) 929 { 930 mips_ase |= ASE_XPA; 931 return TRUE; 932 } 933 934 if (CONST_STRNEQ (option, "ginv")) 935 { 936 mips_ase |= ASE_GINV; 937 return TRUE; 938 } 939 940 return FALSE; 941 } 942 943 static void 944 parse_mips_dis_option (const char *option, unsigned int len) 945 { 946 unsigned int i, optionlen, vallen; 947 const char *val; 948 const struct mips_abi_choice *chosen_abi; 949 const struct mips_arch_choice *chosen_arch; 950 951 /* Try to match options that are simple flags */ 952 if (CONST_STRNEQ (option, "no-aliases")) 953 { 954 no_aliases = 1; 955 return; 956 } 957 958 if (parse_mips_ase_option (option)) 959 { 960 mips_ase |= mips_calculate_combination_ases (mips_ase); 961 return; 962 } 963 964 /* Look for the = that delimits the end of the option name. */ 965 for (i = 0; i < len; i++) 966 if (option[i] == '=') 967 break; 968 969 if (i == 0) /* Invalid option: no name before '='. */ 970 return; 971 if (i == len) /* Invalid option: no '='. */ 972 return; 973 if (i == (len - 1)) /* Invalid option: no value after '='. */ 974 return; 975 976 optionlen = i; 977 val = option + (optionlen + 1); 978 vallen = len - (optionlen + 1); 979 980 if (strncmp ("gpr-names", option, optionlen) == 0 981 && strlen ("gpr-names") == optionlen) 982 { 983 chosen_abi = choose_abi_by_name (val, vallen); 984 if (chosen_abi != NULL) 985 mips_gpr_names = chosen_abi->gpr_names; 986 return; 987 } 988 989 if (strncmp ("fpr-names", option, optionlen) == 0 990 && strlen ("fpr-names") == optionlen) 991 { 992 chosen_abi = choose_abi_by_name (val, vallen); 993 if (chosen_abi != NULL) 994 mips_fpr_names = chosen_abi->fpr_names; 995 return; 996 } 997 998 if (strncmp ("cp0-names", option, optionlen) == 0 999 && strlen ("cp0-names") == optionlen) 1000 { 1001 chosen_arch = choose_arch_by_name (val, vallen); 1002 if (chosen_arch != NULL) 1003 { 1004 mips_cp0_names = chosen_arch->cp0_names; 1005 mips_cp0sel_names = chosen_arch->cp0sel_names; 1006 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 1007 } 1008 return; 1009 } 1010 1011 if (strncmp ("cp1-names", option, optionlen) == 0 1012 && strlen ("cp1-names") == optionlen) 1013 { 1014 chosen_arch = choose_arch_by_name (val, vallen); 1015 if (chosen_arch != NULL) 1016 mips_cp1_names = chosen_arch->cp1_names; 1017 return; 1018 } 1019 1020 if (strncmp ("hwr-names", option, optionlen) == 0 1021 && strlen ("hwr-names") == optionlen) 1022 { 1023 chosen_arch = choose_arch_by_name (val, vallen); 1024 if (chosen_arch != NULL) 1025 mips_hwr_names = chosen_arch->hwr_names; 1026 return; 1027 } 1028 1029 if (strncmp ("reg-names", option, optionlen) == 0 1030 && strlen ("reg-names") == optionlen) 1031 { 1032 /* We check both ABI and ARCH here unconditionally, so 1033 that "numeric" will do the desirable thing: select 1034 numeric register names for all registers. Other than 1035 that, a given name probably won't match both. */ 1036 chosen_abi = choose_abi_by_name (val, vallen); 1037 if (chosen_abi != NULL) 1038 { 1039 mips_gpr_names = chosen_abi->gpr_names; 1040 mips_fpr_names = chosen_abi->fpr_names; 1041 } 1042 chosen_arch = choose_arch_by_name (val, vallen); 1043 if (chosen_arch != NULL) 1044 { 1045 mips_cp0_names = chosen_arch->cp0_names; 1046 mips_cp0sel_names = chosen_arch->cp0sel_names; 1047 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 1048 mips_cp1_names = chosen_arch->cp1_names; 1049 mips_hwr_names = chosen_arch->hwr_names; 1050 } 1051 return; 1052 } 1053 1054 /* Invalid option. */ 1055 } 1056 1057 static void 1058 parse_mips_dis_options (const char *options) 1059 { 1060 const char *option_end; 1061 1062 if (options == NULL) 1063 return; 1064 1065 while (*options != '\0') 1066 { 1067 /* Skip empty options. */ 1068 if (*options == ',') 1069 { 1070 options++; 1071 continue; 1072 } 1073 1074 /* We know that *options is neither NUL or a comma. */ 1075 option_end = options + 1; 1076 while (*option_end != ',' && *option_end != '\0') 1077 option_end++; 1078 1079 parse_mips_dis_option (options, option_end - options); 1080 1081 /* Go on to the next one. If option_end points to a comma, it 1082 will be skipped above. */ 1083 options = option_end; 1084 } 1085 } 1086 1087 static const struct mips_cp0sel_name * 1088 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names, 1089 unsigned int len, 1090 unsigned int cp0reg, 1091 unsigned int sel) 1092 { 1093 unsigned int i; 1094 1095 for (i = 0; i < len; i++) 1096 if (names[i].cp0reg == cp0reg && names[i].sel == sel) 1097 return &names[i]; 1098 return NULL; 1099 } 1100 1101 /* Print register REGNO, of type TYPE, for instruction OPCODE. */ 1102 1103 static void 1104 print_reg (struct disassemble_info *info, const struct mips_opcode *opcode, 1105 enum mips_reg_operand_type type, int regno) 1106 { 1107 switch (type) 1108 { 1109 case OP_REG_GP: 1110 info->fprintf_func (info->stream, "%s", mips_gpr_names[regno]); 1111 break; 1112 1113 case OP_REG_FP: 1114 info->fprintf_func (info->stream, "%s", mips_fpr_names[regno]); 1115 break; 1116 1117 case OP_REG_CCC: 1118 if (opcode->pinfo & (FP_D | FP_S)) 1119 info->fprintf_func (info->stream, "$fcc%d", regno); 1120 else 1121 info->fprintf_func (info->stream, "$cc%d", regno); 1122 break; 1123 1124 case OP_REG_VEC: 1125 if (opcode->membership & INSN_5400) 1126 info->fprintf_func (info->stream, "$f%d", regno); 1127 else 1128 info->fprintf_func (info->stream, "$v%d", regno); 1129 break; 1130 1131 case OP_REG_ACC: 1132 info->fprintf_func (info->stream, "$ac%d", regno); 1133 break; 1134 1135 case OP_REG_COPRO: 1136 if (opcode->name[strlen (opcode->name) - 1] == '0') 1137 info->fprintf_func (info->stream, "%s", mips_cp0_names[regno]); 1138 else if (opcode->name[strlen (opcode->name) - 1] == '1') 1139 info->fprintf_func (info->stream, "%s", mips_cp1_names[regno]); 1140 else 1141 info->fprintf_func (info->stream, "$%d", regno); 1142 break; 1143 1144 case OP_REG_HW: 1145 info->fprintf_func (info->stream, "%s", mips_hwr_names[regno]); 1146 break; 1147 1148 case OP_REG_VF: 1149 info->fprintf_func (info->stream, "$vf%d", regno); 1150 break; 1151 1152 case OP_REG_VI: 1153 info->fprintf_func (info->stream, "$vi%d", regno); 1154 break; 1155 1156 case OP_REG_R5900_I: 1157 info->fprintf_func (info->stream, "$I"); 1158 break; 1159 1160 case OP_REG_R5900_Q: 1161 info->fprintf_func (info->stream, "$Q"); 1162 break; 1163 1164 case OP_REG_R5900_R: 1165 info->fprintf_func (info->stream, "$R"); 1166 break; 1167 1168 case OP_REG_R5900_ACC: 1169 info->fprintf_func (info->stream, "$ACC"); 1170 break; 1171 1172 case OP_REG_MSA: 1173 info->fprintf_func (info->stream, "$w%d", regno); 1174 break; 1175 1176 case OP_REG_MSA_CTRL: 1177 info->fprintf_func (info->stream, "%s", msa_control_names[regno]); 1178 break; 1179 1180 } 1181 } 1182 1183 /* Used to track the state carried over from previous operands in 1185 an instruction. */ 1186 struct mips_print_arg_state { 1187 /* The value of the last OP_INT seen. We only use this for OP_MSB, 1188 where the value is known to be unsigned and small. */ 1189 unsigned int last_int; 1190 1191 /* The type and number of the last OP_REG seen. We only use this for 1192 OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG. */ 1193 enum mips_reg_operand_type last_reg_type; 1194 unsigned int last_regno; 1195 unsigned int dest_regno; 1196 unsigned int seen_dest; 1197 }; 1198 1199 /* Initialize STATE for the start of an instruction. */ 1200 1201 static inline void 1202 init_print_arg_state (struct mips_print_arg_state *state) 1203 { 1204 memset (state, 0, sizeof (*state)); 1205 } 1206 1207 /* Print OP_VU0_SUFFIX or OP_VU0_MATCH_SUFFIX operand OPERAND, 1208 whose value is given by UVAL. */ 1209 1210 static void 1211 print_vu0_channel (struct disassemble_info *info, 1212 const struct mips_operand *operand, unsigned int uval) 1213 { 1214 if (operand->size == 4) 1215 info->fprintf_func (info->stream, "%s%s%s%s", 1216 uval & 8 ? "x" : "", 1217 uval & 4 ? "y" : "", 1218 uval & 2 ? "z" : "", 1219 uval & 1 ? "w" : ""); 1220 else if (operand->size == 2) 1221 info->fprintf_func (info->stream, "%c", "xyzw"[uval]); 1222 else 1223 abort (); 1224 } 1225 1226 /* Record information about a register operand. */ 1227 1228 static void 1229 mips_seen_register (struct mips_print_arg_state *state, 1230 unsigned int regno, 1231 enum mips_reg_operand_type reg_type) 1232 { 1233 state->last_reg_type = reg_type; 1234 state->last_regno = regno; 1235 1236 if (!state->seen_dest) 1237 { 1238 state->seen_dest = 1; 1239 state->dest_regno = regno; 1240 } 1241 } 1242 1243 /* Print SAVE/RESTORE instruction operands according to the argument 1244 register mask AMASK, the number of static registers saved NSREG, 1245 the $ra, $s0 and $s1 register specifiers RA, S0 and S1 respectively, 1246 and the frame size FRAME_SIZE. */ 1247 1248 static void 1249 mips_print_save_restore (struct disassemble_info *info, unsigned int amask, 1250 unsigned int nsreg, unsigned int ra, 1251 unsigned int s0, unsigned int s1, 1252 unsigned int frame_size) 1253 { 1254 const fprintf_ftype infprintf = info->fprintf_func; 1255 unsigned int nargs, nstatics, smask, i, j; 1256 void *is = info->stream; 1257 const char *sep; 1258 1259 if (amask == MIPS_SVRS_ALL_ARGS) 1260 { 1261 nargs = 4; 1262 nstatics = 0; 1263 } 1264 else if (amask == MIPS_SVRS_ALL_STATICS) 1265 { 1266 nargs = 0; 1267 nstatics = 4; 1268 } 1269 else 1270 { 1271 nargs = amask >> 2; 1272 nstatics = amask & 3; 1273 } 1274 1275 sep = ""; 1276 if (nargs > 0) 1277 { 1278 infprintf (is, "%s", mips_gpr_names[4]); 1279 if (nargs > 1) 1280 infprintf (is, "-%s", mips_gpr_names[4 + nargs - 1]); 1281 sep = ","; 1282 } 1283 1284 infprintf (is, "%s%d", sep, frame_size); 1285 1286 if (ra) /* $ra */ 1287 infprintf (is, ",%s", mips_gpr_names[31]); 1288 1289 smask = 0; 1290 if (s0) /* $s0 */ 1291 smask |= 1 << 0; 1292 if (s1) /* $s1 */ 1293 smask |= 1 << 1; 1294 if (nsreg > 0) /* $s2-$s8 */ 1295 smask |= ((1 << nsreg) - 1) << 2; 1296 1297 for (i = 0; i < 9; i++) 1298 if (smask & (1 << i)) 1299 { 1300 infprintf (is, ",%s", mips_gpr_names[i == 8 ? 30 : (16 + i)]); 1301 /* Skip over string of set bits. */ 1302 for (j = i; smask & (2 << j); j++) 1303 continue; 1304 if (j > i) 1305 infprintf (is, "-%s", mips_gpr_names[j == 8 ? 30 : (16 + j)]); 1306 i = j + 1; 1307 } 1308 /* Statics $ax - $a3. */ 1309 if (nstatics == 1) 1310 infprintf (is, ",%s", mips_gpr_names[7]); 1311 else if (nstatics > 0) 1312 infprintf (is, ",%s-%s", 1313 mips_gpr_names[7 - nstatics + 1], 1314 mips_gpr_names[7]); 1315 } 1316 1317 1318 /* Print operand OPERAND of OPCODE, using STATE to track inter-operand state. 1319 UVAL is the encoding of the operand (shifted into bit 0) and BASE_PC is 1320 the base address for OP_PCREL operands. */ 1321 1322 static void 1323 print_insn_arg (struct disassemble_info *info, 1324 struct mips_print_arg_state *state, 1325 const struct mips_opcode *opcode, 1326 const struct mips_operand *operand, 1327 bfd_vma base_pc, 1328 unsigned int uval) 1329 { 1330 const fprintf_ftype infprintf = info->fprintf_func; 1331 void *is = info->stream; 1332 1333 switch (operand->type) 1334 { 1335 case OP_INT: 1336 { 1337 const struct mips_int_operand *int_op; 1338 1339 int_op = (const struct mips_int_operand *) operand; 1340 uval = mips_decode_int_operand (int_op, uval); 1341 state->last_int = uval; 1342 if (int_op->print_hex) 1343 infprintf (is, "0x%x", uval); 1344 else 1345 infprintf (is, "%d", uval); 1346 } 1347 break; 1348 1349 case OP_MAPPED_INT: 1350 { 1351 const struct mips_mapped_int_operand *mint_op; 1352 1353 mint_op = (const struct mips_mapped_int_operand *) operand; 1354 uval = mint_op->int_map[uval]; 1355 state->last_int = uval; 1356 if (mint_op->print_hex) 1357 infprintf (is, "0x%x", uval); 1358 else 1359 infprintf (is, "%d", uval); 1360 } 1361 break; 1362 1363 case OP_MSB: 1364 { 1365 const struct mips_msb_operand *msb_op; 1366 1367 msb_op = (const struct mips_msb_operand *) operand; 1368 uval += msb_op->bias; 1369 if (msb_op->add_lsb) 1370 uval -= state->last_int; 1371 infprintf (is, "0x%x", uval); 1372 } 1373 break; 1374 1375 case OP_REG: 1376 case OP_OPTIONAL_REG: 1377 { 1378 const struct mips_reg_operand *reg_op; 1379 1380 reg_op = (const struct mips_reg_operand *) operand; 1381 uval = mips_decode_reg_operand (reg_op, uval); 1382 print_reg (info, opcode, reg_op->reg_type, uval); 1383 1384 mips_seen_register (state, uval, reg_op->reg_type); 1385 } 1386 break; 1387 1388 case OP_REG_PAIR: 1389 { 1390 const struct mips_reg_pair_operand *pair_op; 1391 1392 pair_op = (const struct mips_reg_pair_operand *) operand; 1393 print_reg (info, opcode, pair_op->reg_type, 1394 pair_op->reg1_map[uval]); 1395 infprintf (is, ","); 1396 print_reg (info, opcode, pair_op->reg_type, 1397 pair_op->reg2_map[uval]); 1398 } 1399 break; 1400 1401 case OP_PCREL: 1402 { 1403 const struct mips_pcrel_operand *pcrel_op; 1404 1405 pcrel_op = (const struct mips_pcrel_operand *) operand; 1406 info->target = mips_decode_pcrel_operand (pcrel_op, base_pc, uval); 1407 1408 /* For jumps and branches clear the ISA bit except for 1409 the GDB disassembler. */ 1410 if (pcrel_op->include_isa_bit 1411 && info->flavour != bfd_target_unknown_flavour) 1412 info->target &= -2; 1413 1414 (*info->print_address_func) (info->target, info); 1415 } 1416 break; 1417 1418 case OP_PERF_REG: 1419 infprintf (is, "%d", uval); 1420 break; 1421 1422 case OP_ADDIUSP_INT: 1423 { 1424 int sval; 1425 1426 sval = mips_signed_operand (operand, uval) * 4; 1427 if (sval >= -8 && sval < 8) 1428 sval ^= 0x400; 1429 infprintf (is, "%d", sval); 1430 break; 1431 } 1432 1433 case OP_CLO_CLZ_DEST: 1434 { 1435 unsigned int reg1, reg2; 1436 1437 reg1 = uval & 31; 1438 reg2 = uval >> 5; 1439 /* If one is zero use the other. */ 1440 if (reg1 == reg2 || reg2 == 0) 1441 infprintf (is, "%s", mips_gpr_names[reg1]); 1442 else if (reg1 == 0) 1443 infprintf (is, "%s", mips_gpr_names[reg2]); 1444 else 1445 /* Bogus, result depends on processor. */ 1446 infprintf (is, "%s or %s", mips_gpr_names[reg1], 1447 mips_gpr_names[reg2]); 1448 } 1449 break; 1450 1451 case OP_SAME_RS_RT: 1452 case OP_CHECK_PREV: 1453 case OP_NON_ZERO_REG: 1454 { 1455 print_reg (info, opcode, OP_REG_GP, uval & 31); 1456 mips_seen_register (state, uval, OP_REG_GP); 1457 } 1458 break; 1459 1460 case OP_LWM_SWM_LIST: 1461 if (operand->size == 2) 1462 { 1463 if (uval == 0) 1464 infprintf (is, "%s,%s", 1465 mips_gpr_names[16], 1466 mips_gpr_names[31]); 1467 else 1468 infprintf (is, "%s-%s,%s", 1469 mips_gpr_names[16], 1470 mips_gpr_names[16 + uval], 1471 mips_gpr_names[31]); 1472 } 1473 else 1474 { 1475 int s_reg_encode; 1476 1477 s_reg_encode = uval & 0xf; 1478 if (s_reg_encode != 0) 1479 { 1480 if (s_reg_encode == 1) 1481 infprintf (is, "%s", mips_gpr_names[16]); 1482 else if (s_reg_encode < 9) 1483 infprintf (is, "%s-%s", 1484 mips_gpr_names[16], 1485 mips_gpr_names[15 + s_reg_encode]); 1486 else if (s_reg_encode == 9) 1487 infprintf (is, "%s-%s,%s", 1488 mips_gpr_names[16], 1489 mips_gpr_names[23], 1490 mips_gpr_names[30]); 1491 else 1492 infprintf (is, "UNKNOWN"); 1493 } 1494 1495 if (uval & 0x10) /* For ra. */ 1496 { 1497 if (s_reg_encode == 0) 1498 infprintf (is, "%s", mips_gpr_names[31]); 1499 else 1500 infprintf (is, ",%s", mips_gpr_names[31]); 1501 } 1502 } 1503 break; 1504 1505 case OP_ENTRY_EXIT_LIST: 1506 { 1507 const char *sep; 1508 unsigned int amask, smask; 1509 1510 sep = ""; 1511 amask = (uval >> 3) & 7; 1512 if (amask > 0 && amask < 5) 1513 { 1514 infprintf (is, "%s", mips_gpr_names[4]); 1515 if (amask > 1) 1516 infprintf (is, "-%s", mips_gpr_names[amask + 3]); 1517 sep = ","; 1518 } 1519 1520 smask = (uval >> 1) & 3; 1521 if (smask == 3) 1522 { 1523 infprintf (is, "%s??", sep); 1524 sep = ","; 1525 } 1526 else if (smask > 0) 1527 { 1528 infprintf (is, "%s%s", sep, mips_gpr_names[16]); 1529 if (smask > 1) 1530 infprintf (is, "-%s", mips_gpr_names[smask + 15]); 1531 sep = ","; 1532 } 1533 1534 if (uval & 1) 1535 { 1536 infprintf (is, "%s%s", sep, mips_gpr_names[31]); 1537 sep = ","; 1538 } 1539 1540 if (amask == 5 || amask == 6) 1541 { 1542 infprintf (is, "%s%s", sep, mips_fpr_names[0]); 1543 if (amask == 6) 1544 infprintf (is, "-%s", mips_fpr_names[1]); 1545 } 1546 } 1547 break; 1548 1549 case OP_SAVE_RESTORE_LIST: 1550 /* Should be handled by the caller due to complex behavior. */ 1551 abort (); 1552 1553 case OP_MDMX_IMM_REG: 1554 { 1555 unsigned int vsel; 1556 1557 vsel = uval >> 5; 1558 uval &= 31; 1559 if ((vsel & 0x10) == 0) 1560 { 1561 int fmt; 1562 1563 vsel &= 0x0f; 1564 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1) 1565 if ((vsel & 1) == 0) 1566 break; 1567 print_reg (info, opcode, OP_REG_VEC, uval); 1568 infprintf (is, "[%d]", vsel >> 1); 1569 } 1570 else if ((vsel & 0x08) == 0) 1571 print_reg (info, opcode, OP_REG_VEC, uval); 1572 else 1573 infprintf (is, "0x%x", uval); 1574 } 1575 break; 1576 1577 case OP_REPEAT_PREV_REG: 1578 print_reg (info, opcode, state->last_reg_type, state->last_regno); 1579 break; 1580 1581 case OP_REPEAT_DEST_REG: 1582 print_reg (info, opcode, state->last_reg_type, state->dest_regno); 1583 break; 1584 1585 case OP_PC: 1586 infprintf (is, "$pc"); 1587 break; 1588 1589 case OP_REG28: 1590 print_reg (info, opcode, OP_REG_GP, 28); 1591 break; 1592 1593 case OP_VU0_SUFFIX: 1594 case OP_VU0_MATCH_SUFFIX: 1595 print_vu0_channel (info, operand, uval); 1596 break; 1597 1598 case OP_IMM_INDEX: 1599 infprintf (is, "[%d]", uval); 1600 break; 1601 1602 case OP_REG_INDEX: 1603 infprintf (is, "["); 1604 print_reg (info, opcode, OP_REG_GP, uval); 1605 infprintf (is, "]"); 1606 break; 1607 } 1608 } 1609 1610 /* Validate the arguments for INSN, which is described by OPCODE. 1611 Use DECODE_OPERAND to get the encoding of each operand. */ 1612 1613 static bfd_boolean 1614 validate_insn_args (const struct mips_opcode *opcode, 1615 const struct mips_operand *(*decode_operand) (const char *), 1616 unsigned int insn) 1617 { 1618 struct mips_print_arg_state state; 1619 const struct mips_operand *operand; 1620 const char *s; 1621 unsigned int uval; 1622 1623 init_print_arg_state (&state); 1624 for (s = opcode->args; *s; ++s) 1625 { 1626 switch (*s) 1627 { 1628 case ',': 1629 case '(': 1630 case ')': 1631 break; 1632 1633 case '#': 1634 ++s; 1635 break; 1636 1637 default: 1638 operand = decode_operand (s); 1639 1640 if (operand) 1641 { 1642 uval = mips_extract_operand (operand, insn); 1643 switch (operand->type) 1644 { 1645 case OP_REG: 1646 case OP_OPTIONAL_REG: 1647 { 1648 const struct mips_reg_operand *reg_op; 1649 1650 reg_op = (const struct mips_reg_operand *) operand; 1651 uval = mips_decode_reg_operand (reg_op, uval); 1652 mips_seen_register (&state, uval, reg_op->reg_type); 1653 } 1654 break; 1655 1656 case OP_SAME_RS_RT: 1657 { 1658 unsigned int reg1, reg2; 1659 1660 reg1 = uval & 31; 1661 reg2 = uval >> 5; 1662 1663 if (reg1 != reg2 || reg1 == 0) 1664 return FALSE; 1665 } 1666 break; 1667 1668 case OP_CHECK_PREV: 1669 { 1670 const struct mips_check_prev_operand *prev_op; 1671 1672 prev_op = (const struct mips_check_prev_operand *) operand; 1673 1674 if (!prev_op->zero_ok && uval == 0) 1675 return FALSE; 1676 1677 if (((prev_op->less_than_ok && uval < state.last_regno) 1678 || (prev_op->greater_than_ok && uval > state.last_regno) 1679 || (prev_op->equal_ok && uval == state.last_regno))) 1680 break; 1681 1682 return FALSE; 1683 } 1684 1685 case OP_NON_ZERO_REG: 1686 { 1687 if (uval == 0) 1688 return FALSE; 1689 } 1690 break; 1691 1692 case OP_INT: 1693 case OP_MAPPED_INT: 1694 case OP_MSB: 1695 case OP_REG_PAIR: 1696 case OP_PCREL: 1697 case OP_PERF_REG: 1698 case OP_ADDIUSP_INT: 1699 case OP_CLO_CLZ_DEST: 1700 case OP_LWM_SWM_LIST: 1701 case OP_ENTRY_EXIT_LIST: 1702 case OP_MDMX_IMM_REG: 1703 case OP_REPEAT_PREV_REG: 1704 case OP_REPEAT_DEST_REG: 1705 case OP_PC: 1706 case OP_REG28: 1707 case OP_VU0_SUFFIX: 1708 case OP_VU0_MATCH_SUFFIX: 1709 case OP_IMM_INDEX: 1710 case OP_REG_INDEX: 1711 case OP_SAVE_RESTORE_LIST: 1712 break; 1713 } 1714 } 1715 if (*s == 'm' || *s == '+' || *s == '-') 1716 ++s; 1717 } 1718 } 1719 return TRUE; 1720 } 1721 1722 /* Print the arguments for INSN, which is described by OPCODE. 1723 Use DECODE_OPERAND to get the encoding of each operand. Use BASE_PC 1724 as the base of OP_PCREL operands, adjusting by LENGTH if the OP_PCREL 1725 operand is for a branch or jump. */ 1726 1727 static void 1728 print_insn_args (struct disassemble_info *info, 1729 const struct mips_opcode *opcode, 1730 const struct mips_operand *(*decode_operand) (const char *), 1731 unsigned int insn, bfd_vma insn_pc, unsigned int length) 1732 { 1733 const fprintf_ftype infprintf = info->fprintf_func; 1734 void *is = info->stream; 1735 struct mips_print_arg_state state; 1736 const struct mips_operand *operand; 1737 const char *s; 1738 1739 init_print_arg_state (&state); 1740 for (s = opcode->args; *s; ++s) 1741 { 1742 switch (*s) 1743 { 1744 case ',': 1745 case '(': 1746 case ')': 1747 infprintf (is, "%c", *s); 1748 break; 1749 1750 case '#': 1751 ++s; 1752 infprintf (is, "%c%c", *s, *s); 1753 break; 1754 1755 default: 1756 operand = decode_operand (s); 1757 if (!operand) 1758 { 1759 /* xgettext:c-format */ 1760 infprintf (is, 1761 _("# internal error, undefined operand in `%s %s'"), 1762 opcode->name, opcode->args); 1763 return; 1764 } 1765 1766 if (operand->type == OP_SAVE_RESTORE_LIST) 1767 { 1768 /* Handle this case here because of the complex behavior. */ 1769 unsigned int amask = (insn >> 15) & 0xf; 1770 unsigned int nsreg = (insn >> 23) & 0x7; 1771 unsigned int ra = insn & 0x1000; /* $ra */ 1772 unsigned int s0 = insn & 0x800; /* $s0 */ 1773 unsigned int s1 = insn & 0x400; /* $s1 */ 1774 unsigned int frame_size = (((insn >> 15) & 0xf0) 1775 | ((insn >> 6) & 0x0f)) * 8; 1776 mips_print_save_restore (info, amask, nsreg, ra, s0, s1, 1777 frame_size); 1778 } 1779 else if (operand->type == OP_REG 1780 && s[1] == ',' 1781 && s[2] == 'H' 1782 && opcode->name[strlen (opcode->name) - 1] == '0') 1783 { 1784 /* Coprocessor register 0 with sel field. */ 1785 const struct mips_cp0sel_name *n; 1786 unsigned int reg, sel; 1787 1788 reg = mips_extract_operand (operand, insn); 1789 s += 2; 1790 operand = decode_operand (s); 1791 sel = mips_extract_operand (operand, insn); 1792 1793 /* CP0 register including 'sel' code for mftc0, to be 1794 printed textually if known. If not known, print both 1795 CP0 register name and sel numerically since CP0 register 1796 with sel 0 may have a name unrelated to register being 1797 printed. */ 1798 n = lookup_mips_cp0sel_name (mips_cp0sel_names, 1799 mips_cp0sel_names_len, 1800 reg, sel); 1801 if (n != NULL) 1802 infprintf (is, "%s", n->name); 1803 else 1804 infprintf (is, "$%d,%d", reg, sel); 1805 } 1806 else 1807 { 1808 bfd_vma base_pc = insn_pc; 1809 1810 /* Adjust the PC relative base so that branch/jump insns use 1811 the following PC as the base but genuinely PC relative 1812 operands use the current PC. */ 1813 if (operand->type == OP_PCREL) 1814 { 1815 const struct mips_pcrel_operand *pcrel_op; 1816 1817 pcrel_op = (const struct mips_pcrel_operand *) operand; 1818 /* The include_isa_bit flag is sufficient to distinguish 1819 branch/jump from other PC relative operands. */ 1820 if (pcrel_op->include_isa_bit) 1821 base_pc += length; 1822 } 1823 1824 print_insn_arg (info, &state, opcode, operand, base_pc, 1825 mips_extract_operand (operand, insn)); 1826 } 1827 if (*s == 'm' || *s == '+' || *s == '-') 1828 ++s; 1829 break; 1830 } 1831 } 1832 } 1833 1834 /* Print the mips instruction at address MEMADDR in debugged memory, 1836 on using INFO. Returns length of the instruction, in bytes, which is 1837 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if 1838 this is little-endian code. */ 1839 1840 static int 1841 print_insn_mips (bfd_vma memaddr, 1842 int word, 1843 struct disassemble_info *info) 1844 { 1845 #define GET_OP(insn, field) \ 1846 (((insn) >> OP_SH_##field) & OP_MASK_##field) 1847 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1]; 1848 const fprintf_ftype infprintf = info->fprintf_func; 1849 const struct mips_opcode *op; 1850 static bfd_boolean init = 0; 1851 void *is = info->stream; 1852 1853 /* Build a hash table to shorten the search time. */ 1854 if (! init) 1855 { 1856 unsigned int i; 1857 1858 for (i = 0; i <= OP_MASK_OP; i++) 1859 { 1860 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++) 1861 { 1862 if (op->pinfo == INSN_MACRO 1863 || (no_aliases && (op->pinfo2 & INSN2_ALIAS))) 1864 continue; 1865 if (i == GET_OP (op->match, OP)) 1866 { 1867 mips_hash[i] = op; 1868 break; 1869 } 1870 } 1871 } 1872 1873 init = 1; 1874 } 1875 1876 info->bytes_per_chunk = INSNLEN; 1877 info->display_endian = info->endian; 1878 info->insn_info_valid = 1; 1879 info->branch_delay_insns = 0; 1880 info->data_size = 0; 1881 info->insn_type = dis_nonbranch; 1882 info->target = 0; 1883 info->target2 = 0; 1884 1885 op = mips_hash[GET_OP (word, OP)]; 1886 if (op != NULL) 1887 { 1888 for (; op < &mips_opcodes[NUMOPCODES]; op++) 1889 { 1890 if (op->pinfo != INSN_MACRO 1891 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) 1892 && (word & op->mask) == op->match) 1893 { 1894 /* We always disassemble the jalx instruction, except for MIPS r6. */ 1895 if (!opcode_is_member (op, mips_isa, mips_ase, mips_processor) 1896 && (strcmp (op->name, "jalx") 1897 || (mips_isa & INSN_ISA_MASK) == ISA_MIPS32R6 1898 || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R6)) 1899 continue; 1900 1901 /* Figure out instruction type and branch delay information. */ 1902 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) 1903 { 1904 if ((op->pinfo & (INSN_WRITE_GPR_31 | INSN_WRITE_1)) != 0) 1905 info->insn_type = dis_jsr; 1906 else 1907 info->insn_type = dis_branch; 1908 info->branch_delay_insns = 1; 1909 } 1910 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY 1911 | INSN_COND_BRANCH_LIKELY)) != 0) 1912 { 1913 if ((op->pinfo & INSN_WRITE_GPR_31) != 0) 1914 info->insn_type = dis_condjsr; 1915 else 1916 info->insn_type = dis_condbranch; 1917 info->branch_delay_insns = 1; 1918 } 1919 else if ((op->pinfo & (INSN_STORE_MEMORY 1920 | INSN_LOAD_MEMORY)) != 0) 1921 info->insn_type = dis_dref; 1922 1923 if (!validate_insn_args (op, decode_mips_operand, word)) 1924 continue; 1925 1926 infprintf (is, "%s", op->name); 1927 if (op->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) 1928 { 1929 unsigned int uval; 1930 1931 infprintf (is, "."); 1932 uval = mips_extract_operand (&mips_vu0_channel_mask, word); 1933 print_vu0_channel (info, &mips_vu0_channel_mask, uval); 1934 } 1935 1936 if (op->args[0]) 1937 { 1938 infprintf (is, "\t"); 1939 print_insn_args (info, op, decode_mips_operand, word, 1940 memaddr, 4); 1941 } 1942 1943 return INSNLEN; 1944 } 1945 } 1946 } 1947 #undef GET_OP 1948 1949 /* Handle undefined instructions. */ 1950 info->insn_type = dis_noninsn; 1951 infprintf (is, "0x%x", word); 1952 return INSNLEN; 1953 } 1954 1955 /* Disassemble an operand for a mips16 instruction. */ 1957 1958 static void 1959 print_mips16_insn_arg (struct disassemble_info *info, 1960 struct mips_print_arg_state *state, 1961 const struct mips_opcode *opcode, 1962 char type, bfd_vma memaddr, 1963 unsigned insn, bfd_boolean use_extend, 1964 unsigned extend, bfd_boolean is_offset) 1965 { 1966 const fprintf_ftype infprintf = info->fprintf_func; 1967 void *is = info->stream; 1968 const struct mips_operand *operand, *ext_operand; 1969 unsigned short ext_size; 1970 unsigned int uval; 1971 bfd_vma baseaddr; 1972 1973 if (!use_extend) 1974 extend = 0; 1975 1976 switch (type) 1977 { 1978 case ',': 1979 case '(': 1980 case ')': 1981 infprintf (is, "%c", type); 1982 break; 1983 1984 default: 1985 operand = decode_mips16_operand (type, FALSE); 1986 if (!operand) 1987 { 1988 /* xgettext:c-format */ 1989 infprintf (is, _("# internal error, undefined operand in `%s %s'"), 1990 opcode->name, opcode->args); 1991 return; 1992 } 1993 1994 if (operand->type == OP_SAVE_RESTORE_LIST) 1995 { 1996 /* Handle this case here because of the complex interaction 1997 with the EXTEND opcode. */ 1998 unsigned int amask = extend & 0xf; 1999 unsigned int nsreg = (extend >> 8) & 0x7; 2000 unsigned int ra = insn & 0x40; /* $ra */ 2001 unsigned int s0 = insn & 0x20; /* $s0 */ 2002 unsigned int s1 = insn & 0x10; /* $s1 */ 2003 unsigned int frame_size = ((extend & 0xf0) | (insn & 0x0f)) * 8; 2004 if (frame_size == 0 && !use_extend) 2005 frame_size = 128; 2006 mips_print_save_restore (info, amask, nsreg, ra, s0, s1, frame_size); 2007 break; 2008 } 2009 2010 if (is_offset && operand->type == OP_INT) 2011 { 2012 const struct mips_int_operand *int_op; 2013 2014 int_op = (const struct mips_int_operand *) operand; 2015 info->insn_type = dis_dref; 2016 info->data_size = 1 << int_op->shift; 2017 } 2018 2019 ext_size = 0; 2020 if (use_extend) 2021 { 2022 ext_operand = decode_mips16_operand (type, TRUE); 2023 if (ext_operand != operand 2024 || (operand->type == OP_INT && operand->lsb == 0 2025 && mips_opcode_32bit_p (opcode))) 2026 { 2027 ext_size = ext_operand->size; 2028 operand = ext_operand; 2029 } 2030 } 2031 if (operand->size == 26) 2032 uval = ((extend & 0x1f) << 21) | ((extend & 0x3e0) << 11) | insn; 2033 else if (ext_size == 16 || ext_size == 9) 2034 uval = ((extend & 0x1f) << 11) | (extend & 0x7e0) | (insn & 0x1f); 2035 else if (ext_size == 15) 2036 uval = ((extend & 0xf) << 11) | (extend & 0x7f0) | (insn & 0xf); 2037 else if (ext_size == 6) 2038 uval = ((extend >> 6) & 0x1f) | (extend & 0x20); 2039 else 2040 uval = mips_extract_operand (operand, (extend << 16) | insn); 2041 if (ext_size == 9) 2042 uval &= (1U << ext_size) - 1; 2043 2044 baseaddr = memaddr + 2; 2045 if (operand->type == OP_PCREL) 2046 { 2047 const struct mips_pcrel_operand *pcrel_op; 2048 2049 pcrel_op = (const struct mips_pcrel_operand *) operand; 2050 if (!pcrel_op->include_isa_bit && use_extend) 2051 baseaddr = memaddr - 2; 2052 else if (!pcrel_op->include_isa_bit) 2053 { 2054 bfd_byte buffer[2]; 2055 2056 /* If this instruction is in the delay slot of a JAL/JALX 2057 instruction, the base address is the address of the 2058 JAL/JALX instruction. If it is in the delay slot of 2059 a JR/JALR instruction, the base address is the address 2060 of the JR/JALR instruction. This test is unreliable: 2061 we have no way of knowing whether the previous word is 2062 instruction or data. */ 2063 if (info->read_memory_func (memaddr - 4, buffer, 2, info) == 0 2064 && (((info->endian == BFD_ENDIAN_BIG 2065 ? bfd_getb16 (buffer) 2066 : bfd_getl16 (buffer)) 2067 & 0xf800) == 0x1800)) 2068 baseaddr = memaddr - 4; 2069 else if (info->read_memory_func (memaddr - 2, buffer, 2, 2070 info) == 0 2071 && (((info->endian == BFD_ENDIAN_BIG 2072 ? bfd_getb16 (buffer) 2073 : bfd_getl16 (buffer)) 2074 & 0xf89f) == 0xe800) 2075 && (((info->endian == BFD_ENDIAN_BIG 2076 ? bfd_getb16 (buffer) 2077 : bfd_getl16 (buffer)) 2078 & 0x0060) != 0x0060)) 2079 baseaddr = memaddr - 2; 2080 else 2081 baseaddr = memaddr; 2082 } 2083 } 2084 2085 print_insn_arg (info, state, opcode, operand, baseaddr + 1, uval); 2086 break; 2087 } 2088 } 2089 2090 2091 /* Check if the given address is the last word of a MIPS16 PLT entry. 2092 This word is data and depending on the value it may interfere with 2093 disassembly of further PLT entries. We make use of the fact PLT 2094 symbols are marked BSF_SYNTHETIC. */ 2095 static bfd_boolean 2096 is_mips16_plt_tail (struct disassemble_info *info, bfd_vma addr) 2097 { 2098 if (info->symbols 2099 && info->symbols[0] 2100 && (info->symbols[0]->flags & BSF_SYNTHETIC) 2101 && addr == bfd_asymbol_value (info->symbols[0]) + 12) 2102 return TRUE; 2103 2104 return FALSE; 2105 } 2106 2107 /* Whether none, a 32-bit or a 16-bit instruction match has been done. */ 2108 2109 enum match_kind 2110 { 2111 MATCH_NONE, 2112 MATCH_FULL, 2113 MATCH_SHORT 2114 }; 2115 2116 /* Disassemble mips16 instructions. */ 2117 2118 static int 2119 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) 2120 { 2121 const fprintf_ftype infprintf = info->fprintf_func; 2122 int status; 2123 bfd_byte buffer[4]; 2124 const struct mips_opcode *op, *opend; 2125 struct mips_print_arg_state state; 2126 void *is = info->stream; 2127 bfd_boolean have_second; 2128 bfd_boolean extend_only; 2129 unsigned int second; 2130 unsigned int first; 2131 unsigned int full; 2132 2133 info->bytes_per_chunk = 2; 2134 info->display_endian = info->endian; 2135 info->insn_info_valid = 1; 2136 info->branch_delay_insns = 0; 2137 info->data_size = 0; 2138 info->target = 0; 2139 info->target2 = 0; 2140 2141 #define GET_OP(insn, field) \ 2142 (((insn) >> MIPS16OP_SH_##field) & MIPS16OP_MASK_##field) 2143 /* Decode PLT entry's GOT slot address word. */ 2144 if (is_mips16_plt_tail (info, memaddr)) 2145 { 2146 info->insn_type = dis_noninsn; 2147 status = (*info->read_memory_func) (memaddr, buffer, 4, info); 2148 if (status == 0) 2149 { 2150 unsigned int gotslot; 2151 2152 if (info->endian == BFD_ENDIAN_BIG) 2153 gotslot = bfd_getb32 (buffer); 2154 else 2155 gotslot = bfd_getl32 (buffer); 2156 infprintf (is, ".word\t0x%x", gotslot); 2157 2158 return 4; 2159 } 2160 } 2161 else 2162 { 2163 info->insn_type = dis_nonbranch; 2164 status = (*info->read_memory_func) (memaddr, buffer, 2, info); 2165 } 2166 if (status != 0) 2167 { 2168 (*info->memory_error_func) (status, memaddr, info); 2169 return -1; 2170 } 2171 2172 extend_only = FALSE; 2173 2174 if (info->endian == BFD_ENDIAN_BIG) 2175 first = bfd_getb16 (buffer); 2176 else 2177 first = bfd_getl16 (buffer); 2178 2179 status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info); 2180 if (status == 0) 2181 { 2182 have_second = TRUE; 2183 if (info->endian == BFD_ENDIAN_BIG) 2184 second = bfd_getb16 (buffer); 2185 else 2186 second = bfd_getl16 (buffer); 2187 full = (first << 16) | second; 2188 } 2189 else 2190 { 2191 have_second = FALSE; 2192 second = 0; 2193 full = first; 2194 } 2195 2196 /* FIXME: Should probably use a hash table on the major opcode here. */ 2197 2198 opend = mips16_opcodes + bfd_mips16_num_opcodes; 2199 for (op = mips16_opcodes; op < opend; op++) 2200 { 2201 enum match_kind match; 2202 2203 if (!opcode_is_member (op, mips_isa, mips_ase, mips_processor)) 2204 continue; 2205 2206 if (op->pinfo == INSN_MACRO 2207 || (no_aliases && (op->pinfo2 & INSN2_ALIAS))) 2208 match = MATCH_NONE; 2209 else if (mips_opcode_32bit_p (op)) 2210 { 2211 if (have_second 2212 && (full & op->mask) == op->match) 2213 match = MATCH_FULL; 2214 else 2215 match = MATCH_NONE; 2216 } 2217 else if ((first & op->mask) == op->match) 2218 { 2219 match = MATCH_SHORT; 2220 second = 0; 2221 full = first; 2222 } 2223 else if ((first & 0xf800) == 0xf000 2224 && have_second 2225 && !extend_only 2226 && (second & op->mask) == op->match) 2227 { 2228 if (op->pinfo2 & INSN2_SHORT_ONLY) 2229 { 2230 match = MATCH_NONE; 2231 extend_only = TRUE; 2232 } 2233 else 2234 match = MATCH_FULL; 2235 } 2236 else 2237 match = MATCH_NONE; 2238 2239 if (match != MATCH_NONE) 2240 { 2241 const char *s; 2242 2243 infprintf (is, "%s", op->name); 2244 if (op->args[0] != '\0') 2245 infprintf (is, "\t"); 2246 2247 init_print_arg_state (&state); 2248 for (s = op->args; *s != '\0'; s++) 2249 { 2250 if (*s == ',' 2251 && s[1] == 'w' 2252 && GET_OP (full, RX) == GET_OP (full, RY)) 2253 { 2254 /* Skip the register and the comma. */ 2255 ++s; 2256 continue; 2257 } 2258 if (*s == ',' 2259 && s[1] == 'v' 2260 && GET_OP (full, RZ) == GET_OP (full, RX)) 2261 { 2262 /* Skip the register and the comma. */ 2263 ++s; 2264 continue; 2265 } 2266 if (s[0] == 'N' 2267 && s[1] == ',' 2268 && s[2] == 'O' 2269 && op->name[strlen (op->name) - 1] == '0') 2270 { 2271 /* Coprocessor register 0 with sel field. */ 2272 const struct mips_cp0sel_name *n; 2273 const struct mips_operand *operand; 2274 unsigned int reg, sel; 2275 2276 operand = decode_mips16_operand (*s, TRUE); 2277 reg = mips_extract_operand (operand, (first << 16) | second); 2278 s += 2; 2279 operand = decode_mips16_operand (*s, TRUE); 2280 sel = mips_extract_operand (operand, (first << 16) | second); 2281 2282 /* CP0 register including 'sel' code for mftc0, to be 2283 printed textually if known. If not known, print both 2284 CP0 register name and sel numerically since CP0 register 2285 with sel 0 may have a name unrelated to register being 2286 printed. */ 2287 n = lookup_mips_cp0sel_name (mips_cp0sel_names, 2288 mips_cp0sel_names_len, 2289 reg, sel); 2290 if (n != NULL) 2291 infprintf (is, "%s", n->name); 2292 else 2293 infprintf (is, "$%d,%d", reg, sel); 2294 } 2295 else 2296 switch (match) 2297 { 2298 case MATCH_FULL: 2299 print_mips16_insn_arg (info, &state, op, *s, memaddr + 2, 2300 second, TRUE, first, s[1] == '('); 2301 break; 2302 case MATCH_SHORT: 2303 print_mips16_insn_arg (info, &state, op, *s, memaddr, 2304 first, FALSE, 0, s[1] == '('); 2305 break; 2306 case MATCH_NONE: /* Stop the compiler complaining. */ 2307 break; 2308 } 2309 } 2310 2311 /* Figure out branch instruction type and delay slot information. */ 2312 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) 2313 info->branch_delay_insns = 1; 2314 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 2315 || (op->pinfo2 & INSN2_UNCOND_BRANCH) != 0) 2316 { 2317 if ((op->pinfo & INSN_WRITE_GPR_31) != 0) 2318 info->insn_type = dis_jsr; 2319 else 2320 info->insn_type = dis_branch; 2321 } 2322 else if ((op->pinfo2 & INSN2_COND_BRANCH) != 0) 2323 info->insn_type = dis_condbranch; 2324 2325 return match == MATCH_FULL ? 4 : 2; 2326 } 2327 } 2328 #undef GET_OP 2329 2330 infprintf (is, "0x%x", first); 2331 info->insn_type = dis_noninsn; 2332 2333 return 2; 2334 } 2335 2336 /* Disassemble microMIPS instructions. */ 2337 2338 static int 2339 print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info) 2340 { 2341 const fprintf_ftype infprintf = info->fprintf_func; 2342 const struct mips_opcode *op, *opend; 2343 void *is = info->stream; 2344 bfd_byte buffer[2]; 2345 unsigned int higher; 2346 unsigned int length; 2347 int status; 2348 unsigned int insn; 2349 2350 info->bytes_per_chunk = 2; 2351 info->display_endian = info->endian; 2352 info->insn_info_valid = 1; 2353 info->branch_delay_insns = 0; 2354 info->data_size = 0; 2355 info->insn_type = dis_nonbranch; 2356 info->target = 0; 2357 info->target2 = 0; 2358 2359 status = (*info->read_memory_func) (memaddr, buffer, 2, info); 2360 if (status != 0) 2361 { 2362 (*info->memory_error_func) (status, memaddr, info); 2363 return -1; 2364 } 2365 2366 length = 2; 2367 2368 if (info->endian == BFD_ENDIAN_BIG) 2369 insn = bfd_getb16 (buffer); 2370 else 2371 insn = bfd_getl16 (buffer); 2372 2373 if ((insn & 0x1c00) == 0x0000 || (insn & 0x1000) == 0x1000) 2374 { 2375 /* This is a 32-bit microMIPS instruction. */ 2376 higher = insn; 2377 2378 status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info); 2379 if (status != 0) 2380 { 2381 infprintf (is, "micromips 0x%x", higher); 2382 (*info->memory_error_func) (status, memaddr + 2, info); 2383 return -1; 2384 } 2385 2386 if (info->endian == BFD_ENDIAN_BIG) 2387 insn = bfd_getb16 (buffer); 2388 else 2389 insn = bfd_getl16 (buffer); 2390 2391 insn = insn | (higher << 16); 2392 2393 length += 2; 2394 } 2395 2396 /* FIXME: Should probably use a hash table on the major opcode here. */ 2397 2398 opend = micromips_opcodes + bfd_micromips_num_opcodes; 2399 for (op = micromips_opcodes; op < opend; op++) 2400 { 2401 if (op->pinfo != INSN_MACRO 2402 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) 2403 && (insn & op->mask) == op->match 2404 && ((length == 2 && (op->mask & 0xffff0000) == 0) 2405 || (length == 4 && (op->mask & 0xffff0000) != 0))) 2406 { 2407 if (!validate_insn_args (op, decode_micromips_operand, insn)) 2408 continue; 2409 2410 infprintf (is, "%s", op->name); 2411 2412 if (op->args[0]) 2413 { 2414 infprintf (is, "\t"); 2415 print_insn_args (info, op, decode_micromips_operand, insn, 2416 memaddr + 1, length); 2417 } 2418 2419 /* Figure out instruction type and branch delay information. */ 2420 if ((op->pinfo 2421 & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY)) != 0) 2422 info->branch_delay_insns = 1; 2423 if (((op->pinfo & INSN_UNCOND_BRANCH_DELAY) 2424 | (op->pinfo2 & INSN2_UNCOND_BRANCH)) != 0) 2425 { 2426 if ((op->pinfo & (INSN_WRITE_GPR_31 | INSN_WRITE_1)) != 0) 2427 info->insn_type = dis_jsr; 2428 else 2429 info->insn_type = dis_branch; 2430 } 2431 else if (((op->pinfo & INSN_COND_BRANCH_DELAY) 2432 | (op->pinfo2 & INSN2_COND_BRANCH)) != 0) 2433 { 2434 if ((op->pinfo & INSN_WRITE_GPR_31) != 0) 2435 info->insn_type = dis_condjsr; 2436 else 2437 info->insn_type = dis_condbranch; 2438 } 2439 else if ((op->pinfo 2440 & (INSN_STORE_MEMORY | INSN_LOAD_MEMORY)) != 0) 2441 info->insn_type = dis_dref; 2442 2443 return length; 2444 } 2445 } 2446 2447 infprintf (is, "0x%x", insn); 2448 info->insn_type = dis_noninsn; 2449 2450 return length; 2451 } 2452 2453 /* Return 1 if a symbol associated with the location being disassembled 2454 indicates a compressed mode, either MIPS16 or microMIPS, according to 2455 MICROMIPS_P. We iterate over all the symbols at the address being 2456 considered assuming if at least one of them indicates code compression, 2457 then such code has been genuinely produced here (other symbols could 2458 have been derived from function symbols defined elsewhere or could 2459 define data). Otherwise, return 0. */ 2460 2461 static bfd_boolean 2462 is_compressed_mode_p (struct disassemble_info *info, bfd_boolean micromips_p) 2463 { 2464 int i; 2465 int l; 2466 2467 for (i = info->symtab_pos, l = i + info->num_symbols; i < l; i++) 2468 if (((info->symtab[i])->flags & BSF_SYNTHETIC) != 0 2469 && ((!micromips_p 2470 && ELF_ST_IS_MIPS16 ((*info->symbols)->udata.i)) 2471 || (micromips_p 2472 && ELF_ST_IS_MICROMIPS ((*info->symbols)->udata.i)))) 2473 return 1; 2474 else if (bfd_asymbol_flavour (info->symtab[i]) == bfd_target_elf_flavour 2475 && info->symtab[i]->section == info->section) 2476 { 2477 elf_symbol_type *symbol = (elf_symbol_type *) info->symtab[i]; 2478 if ((!micromips_p 2479 && ELF_ST_IS_MIPS16 (symbol->internal_elf_sym.st_other)) 2480 || (micromips_p 2481 && ELF_ST_IS_MICROMIPS (symbol->internal_elf_sym.st_other))) 2482 return 1; 2483 } 2484 2485 return 0; 2486 } 2487 2488 /* In an environment where we do not know the symbol type of the 2489 instruction we are forced to assume that the low order bit of the 2490 instructions' address may mark it as a mips16 instruction. If we 2491 are single stepping, or the pc is within the disassembled function, 2492 this works. Otherwise, we need a clue. Sometimes. */ 2493 2494 static int 2495 _print_insn_mips (bfd_vma memaddr, 2496 struct disassemble_info *info, 2497 enum bfd_endian endianness) 2498 { 2499 bfd_byte buffer[INSNLEN]; 2500 int status; 2501 2502 set_default_mips_dis_options (info); 2503 parse_mips_dis_options (info->disassembler_options); 2504 2505 if (info->mach == bfd_mach_mips16) 2506 return print_insn_mips16 (memaddr, info); 2507 if (info->mach == bfd_mach_mips_micromips) 2508 return print_insn_micromips (memaddr, info); 2509 2510 #if 1 2511 /* FIXME: If odd address, this is CLEARLY a compressed instruction. */ 2512 /* Only a few tools will work this way. */ 2513 if (memaddr & 0x01) 2514 { 2515 if (micromips_ase) 2516 return print_insn_micromips (memaddr, info); 2517 else 2518 return print_insn_mips16 (memaddr, info); 2519 } 2520 #endif 2521 2522 #if SYMTAB_AVAILABLE 2523 if (is_compressed_mode_p (info, TRUE)) 2524 return print_insn_micromips (memaddr, info); 2525 if (is_compressed_mode_p (info, FALSE)) 2526 return print_insn_mips16 (memaddr, info); 2527 #endif 2528 2529 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info); 2530 if (status == 0) 2531 { 2532 int insn; 2533 2534 if (endianness == BFD_ENDIAN_BIG) 2535 insn = bfd_getb32 (buffer); 2536 else 2537 insn = bfd_getl32 (buffer); 2538 2539 return print_insn_mips (memaddr, insn, info); 2540 } 2541 else 2542 { 2543 (*info->memory_error_func) (status, memaddr, info); 2544 return -1; 2545 } 2546 } 2547 2548 int 2549 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info) 2550 { 2551 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG); 2552 } 2553 2554 int 2555 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info) 2556 { 2557 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE); 2558 } 2559 2560 void 2562 print_mips_disassembler_options (FILE *stream) 2563 { 2564 unsigned int i; 2565 2566 fprintf (stream, _("\n\ 2567 The following MIPS specific disassembler options are supported for use\n\ 2568 with the -M switch (multiple options should be separated by commas):\n")); 2569 2570 fprintf (stream, _("\n\ 2571 no-aliases Use canonical instruction forms.\n")); 2572 2573 fprintf (stream, _("\n\ 2574 msa Recognize MSA instructions.\n")); 2575 2576 fprintf (stream, _("\n\ 2577 virt Recognize the virtualization ASE instructions.\n")); 2578 2579 fprintf (stream, _("\n\ 2580 xpa Recognize the eXtended Physical Address (XPA)\n\ 2581 ASE instructions.\n")); 2582 2583 fprintf (stream, _("\n\ 2584 ginv Recognize the Global INValidate (GINV) ASE\n\ 2585 instructions.\n")); 2586 2587 fprintf (stream, _("\n\ 2588 gpr-names=ABI Print GPR names according to specified ABI.\n\ 2589 Default: based on binary being disassembled.\n")); 2590 2591 fprintf (stream, _("\n\ 2592 fpr-names=ABI Print FPR names according to specified ABI.\n\ 2593 Default: numeric.\n")); 2594 2595 fprintf (stream, _("\n\ 2596 cp0-names=ARCH Print CP0 register names according to\n\ 2597 specified architecture.\n\ 2598 Default: based on binary being disassembled.\n")); 2599 2600 fprintf (stream, _("\n\ 2601 hwr-names=ARCH Print HWR names according to specified \n\ 2602 architecture.\n\ 2603 Default: based on binary being disassembled.\n")); 2604 2605 fprintf (stream, _("\n\ 2606 reg-names=ABI Print GPR and FPR names according to\n\ 2607 specified ABI.\n")); 2608 2609 fprintf (stream, _("\n\ 2610 reg-names=ARCH Print CP0 register and HWR names according to\n\ 2611 specified architecture.\n")); 2612 2613 fprintf (stream, _("\n\ 2614 For the options above, the following values are supported for \"ABI\":\n\ 2615 ")); 2616 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++) 2617 fprintf (stream, " %s", mips_abi_choices[i].name); 2618 fprintf (stream, _("\n")); 2619 2620 fprintf (stream, _("\n\ 2621 For the options above, The following values are supported for \"ARCH\":\n\ 2622 ")); 2623 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++) 2624 if (*mips_arch_choices[i].name != '\0') 2625 fprintf (stream, " %s", mips_arch_choices[i].name); 2626 fprintf (stream, _("\n")); 2627 2628 fprintf (stream, _("\n")); 2629 } 2630
Indexes created Mon Mar 30 00:23:01 UTC 2026