1 1.10 mrg /* Copyright (C) 2011-2022 Free Software Foundation, Inc. 2 1.1 mrg Contributed by ARM Ltd. 3 1.1 mrg 4 1.1 mrg This file is part of GCC. 5 1.1 mrg 6 1.1 mrg GCC is free software; you can redistribute it and/or modify it 7 1.1 mrg under the terms of the GNU General Public License as published 8 1.1 mrg by the Free Software Foundation; either version 3, or (at your 9 1.1 mrg option) any later version. 10 1.1 mrg 11 1.1 mrg GCC is distributed in the hope that it will be useful, but WITHOUT 12 1.1 mrg ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 1.1 mrg or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14 1.1 mrg License for more details. 15 1.1 mrg 16 1.1 mrg You should have received a copy of the GNU General Public License 17 1.1 mrg along with GCC; see the file COPYING3. If not see 18 1.1 mrg <http://www.gnu.org/licenses/>. */ 19 1.1 mrg 20 1.1 mrg /* Definitions for option handling for AArch64. */ 21 1.1 mrg 22 1.1 mrg #ifndef GCC_AARCH64_OPTS_H 23 1.1 mrg #define GCC_AARCH64_OPTS_H 24 1.1 mrg 25 1.1 mrg /* The various cores that implement AArch64. */ 26 1.1 mrg enum aarch64_processor 27 1.1 mrg { 28 1.6 mrg #define AARCH64_CORE(NAME, INTERNAL_IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \ 29 1.3 mrg INTERNAL_IDENT, 30 1.1 mrg #include "aarch64-cores.def" 31 1.1 mrg /* Used to indicate that no processor has been specified. */ 32 1.1 mrg generic, 33 1.1 mrg /* Used to mark the end of the processor table. */ 34 1.1 mrg aarch64_none 35 1.1 mrg }; 36 1.1 mrg 37 1.4 mrg enum aarch64_arch 38 1.4 mrg { 39 1.4 mrg #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \ 40 1.4 mrg AARCH64_ARCH_##ARCH_IDENT, 41 1.4 mrg #include "aarch64-arches.def" 42 1.4 mrg aarch64_no_arch 43 1.4 mrg }; 44 1.4 mrg 45 1.1 mrg /* TLS types. */ 46 1.1 mrg enum aarch64_tls_type { 47 1.1 mrg TLS_TRADITIONAL, 48 1.1 mrg TLS_DESCRIPTORS 49 1.1 mrg }; 50 1.1 mrg 51 1.1 mrg /* The code model defines the address generation strategy. 52 1.1 mrg Most have a PIC and non-PIC variant. */ 53 1.1 mrg enum aarch64_code_model { 54 1.1 mrg /* Static code and data fit within a 1MB region. 55 1.1 mrg Not fully implemented, mostly treated as SMALL. */ 56 1.1 mrg AARCH64_CMODEL_TINY, 57 1.1 mrg /* Static code, data and GOT/PLT fit within a 1MB region. 58 1.1 mrg Not fully implemented, mostly treated as SMALL_PIC. */ 59 1.1 mrg AARCH64_CMODEL_TINY_PIC, 60 1.1 mrg /* Static code and data fit within a 4GB region. 61 1.1 mrg The default non-PIC code model. */ 62 1.1 mrg AARCH64_CMODEL_SMALL, 63 1.1 mrg /* Static code, data and GOT/PLT fit within a 4GB region. 64 1.1 mrg The default PIC code model. */ 65 1.1 mrg AARCH64_CMODEL_SMALL_PIC, 66 1.4 mrg /* -fpic for small memory model. 67 1.4 mrg GOT size to 28KiB (4K*8-4K) or 3580 entries. */ 68 1.4 mrg AARCH64_CMODEL_SMALL_SPIC, 69 1.1 mrg /* No assumptions about addresses of code and data. 70 1.1 mrg The PIC variant is not yet implemented. */ 71 1.1 mrg AARCH64_CMODEL_LARGE 72 1.1 mrg }; 73 1.1 mrg 74 1.6 mrg /* Function types -msign-return-address should sign. */ 75 1.6 mrg enum aarch64_function_type { 76 1.6 mrg /* Don't sign any function. */ 77 1.6 mrg AARCH64_FUNCTION_NONE, 78 1.6 mrg /* Non-leaf functions. */ 79 1.6 mrg AARCH64_FUNCTION_NON_LEAF, 80 1.6 mrg /* All functions. */ 81 1.6 mrg AARCH64_FUNCTION_ALL 82 1.6 mrg }; 83 1.6 mrg 84 1.7 mrg /* SVE vector register sizes. */ 85 1.7 mrg enum aarch64_sve_vector_bits_enum { 86 1.7 mrg SVE_SCALABLE, 87 1.8 mrg SVE_NOT_IMPLEMENTED = SVE_SCALABLE, 88 1.7 mrg SVE_128 = 128, 89 1.7 mrg SVE_256 = 256, 90 1.7 mrg SVE_512 = 512, 91 1.7 mrg SVE_1024 = 1024, 92 1.7 mrg SVE_2048 = 2048 93 1.7 mrg }; 94 1.7 mrg 95 1.8 mrg /* Where to get the canary for the stack protector. */ 96 1.8 mrg enum stack_protector_guard { 97 1.8 mrg SSP_SYSREG, /* per-thread canary in special system register */ 98 1.8 mrg SSP_GLOBAL /* global canary */ 99 1.8 mrg }; 100 1.8 mrg 101 1.1 mrg #endif 102
Indexes created Thu Jul 16 00:26:27 UTC 2026