aarch64-opts.h revision 1.4 1 1.4 mrg /* Copyright (C) 2011-2016 Free Software Foundation, Inc.
2 1.1 mrg Contributed by ARM Ltd.
3 1.1 mrg
4 1.1 mrg This file is part of GCC.
5 1.1 mrg
6 1.1 mrg GCC is free software; you can redistribute it and/or modify it
7 1.1 mrg under the terms of the GNU General Public License as published
8 1.1 mrg by the Free Software Foundation; either version 3, or (at your
9 1.1 mrg option) any later version.
10 1.1 mrg
11 1.1 mrg GCC is distributed in the hope that it will be useful, but WITHOUT
12 1.1 mrg ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 1.1 mrg or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 1.1 mrg License for more details.
15 1.1 mrg
16 1.1 mrg You should have received a copy of the GNU General Public License
17 1.1 mrg along with GCC; see the file COPYING3. If not see
18 1.1 mrg <http://www.gnu.org/licenses/>. */
19 1.1 mrg
20 1.1 mrg /* Definitions for option handling for AArch64. */
21 1.1 mrg
22 1.1 mrg #ifndef GCC_AARCH64_OPTS_H
23 1.1 mrg #define GCC_AARCH64_OPTS_H
24 1.1 mrg
25 1.1 mrg /* The various cores that implement AArch64. */
26 1.1 mrg enum aarch64_processor
27 1.1 mrg {
28 1.4 mrg #define AARCH64_CORE(NAME, INTERNAL_IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART) \
29 1.3 mrg INTERNAL_IDENT,
30 1.1 mrg #include "aarch64-cores.def"
31 1.1 mrg #undef AARCH64_CORE
32 1.1 mrg /* Used to indicate that no processor has been specified. */
33 1.1 mrg generic,
34 1.1 mrg /* Used to mark the end of the processor table. */
35 1.1 mrg aarch64_none
36 1.1 mrg };
37 1.1 mrg
38 1.4 mrg enum aarch64_arch
39 1.4 mrg {
40 1.4 mrg #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
41 1.4 mrg AARCH64_ARCH_##ARCH_IDENT,
42 1.4 mrg #include "aarch64-arches.def"
43 1.4 mrg #undef AARCH64_ARCH
44 1.4 mrg aarch64_no_arch
45 1.4 mrg };
46 1.4 mrg
47 1.1 mrg /* TLS types. */
48 1.1 mrg enum aarch64_tls_type {
49 1.1 mrg TLS_TRADITIONAL,
50 1.1 mrg TLS_DESCRIPTORS
51 1.1 mrg };
52 1.1 mrg
53 1.1 mrg /* The code model defines the address generation strategy.
54 1.1 mrg Most have a PIC and non-PIC variant. */
55 1.1 mrg enum aarch64_code_model {
56 1.1 mrg /* Static code and data fit within a 1MB region.
57 1.1 mrg Not fully implemented, mostly treated as SMALL. */
58 1.1 mrg AARCH64_CMODEL_TINY,
59 1.1 mrg /* Static code, data and GOT/PLT fit within a 1MB region.
60 1.1 mrg Not fully implemented, mostly treated as SMALL_PIC. */
61 1.1 mrg AARCH64_CMODEL_TINY_PIC,
62 1.1 mrg /* Static code and data fit within a 4GB region.
63 1.1 mrg The default non-PIC code model. */
64 1.1 mrg AARCH64_CMODEL_SMALL,
65 1.1 mrg /* Static code, data and GOT/PLT fit within a 4GB region.
66 1.1 mrg The default PIC code model. */
67 1.1 mrg AARCH64_CMODEL_SMALL_PIC,
68 1.4 mrg /* -fpic for small memory model.
69 1.4 mrg GOT size to 28KiB (4K*8-4K) or 3580 entries. */
70 1.4 mrg AARCH64_CMODEL_SMALL_SPIC,
71 1.1 mrg /* No assumptions about addresses of code and data.
72 1.1 mrg The PIC variant is not yet implemented. */
73 1.1 mrg AARCH64_CMODEL_LARGE
74 1.1 mrg };
75 1.1 mrg
76 1.1 mrg #endif
77