aarch64-protos.h revision 1.1
1 /* Machine description for AArch64 architecture. 2 Copyright (C) 2009-2013 Free Software Foundation, Inc. 3 Contributed by ARM Ltd. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GCC is distributed in the hope that it will be useful, but 13 WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 22 #ifndef GCC_AARCH64_PROTOS_H 23 #define GCC_AARCH64_PROTOS_H 24 25 /* 26 SYMBOL_CONTEXT_ADR 27 The symbol is used in a load-address operation. 28 SYMBOL_CONTEXT_MEM 29 The symbol is used as the address in a MEM. 30 */ 31 enum aarch64_symbol_context 32 { 33 SYMBOL_CONTEXT_MEM, 34 SYMBOL_CONTEXT_ADR 35 }; 36 37 /* SYMBOL_SMALL_ABSOLUTE: Generate symbol accesses through 38 high and lo relocs that calculate the base address using a PC 39 relative reloc. 40 So to get the address of foo, we generate 41 adrp x0, foo 42 add x0, x0, :lo12:foo 43 44 To load or store something to foo, we could use the corresponding 45 load store variants that generate an 46 ldr x0, [x0,:lo12:foo] 47 or 48 str x1, [x0, :lo12:foo] 49 50 This corresponds to the small code model of the compiler. 51 52 SYMBOL_SMALL_GOT: Similar to the one above but this 53 gives us the GOT entry of the symbol being referred to : 54 Thus calculating the GOT entry for foo is done using the 55 following sequence of instructions. The ADRP instruction 56 gets us to the page containing the GOT entry of the symbol 57 and the got_lo12 gets us the actual offset in it. 58 59 adrp x0, :got:foo 60 ldr x0, [x0, :gotoff_lo12:foo] 61 62 This corresponds to the small PIC model of the compiler. 63 64 SYMBOL_SMALL_TLSGD 65 SYMBOL_SMALL_TLSDESC 66 SYMBOL_SMALL_GOTTPREL 67 SYMBOL_SMALL_TPREL 68 Each of of these represents a thread-local symbol, and corresponds to the 69 thread local storage relocation operator for the symbol being referred to. 70 71 SYMBOL_FORCE_TO_MEM : Global variables are addressed using 72 constant pool. All variable addresses are spilled into constant 73 pools. The constant pools themselves are addressed using PC 74 relative accesses. This only works for the large code model. 75 */ 76 enum aarch64_symbol_type 77 { 78 SYMBOL_SMALL_ABSOLUTE, 79 SYMBOL_SMALL_GOT, 80 SYMBOL_SMALL_TLSGD, 81 SYMBOL_SMALL_TLSDESC, 82 SYMBOL_SMALL_GOTTPREL, 83 SYMBOL_SMALL_TPREL, 84 SYMBOL_FORCE_TO_MEM 85 }; 86 87 /* A set of tuning parameters contains references to size and time 88 cost models and vectors for address cost calculations, register 89 move costs and memory move costs. */ 90 91 /* Extra costs for specific insns. Only records the cost above a 92 single insn. */ 93 94 struct cpu_rtx_cost_table 95 { 96 const int memory_load; 97 const int memory_store; 98 const int register_shift; 99 const int int_divide; 100 const int float_divide; 101 const int double_divide; 102 const int int_multiply; 103 const int int_multiply_extend; 104 const int int_multiply_add; 105 const int int_multiply_extend_add; 106 const int float_multiply; 107 const int double_multiply; 108 }; 109 110 /* Additional cost for addresses. */ 111 struct cpu_addrcost_table 112 { 113 const int pre_modify; 114 const int post_modify; 115 const int register_offset; 116 const int register_extend; 117 const int imm_offset; 118 }; 119 120 /* Additional costs for register copies. Cost is for one register. */ 121 struct cpu_regmove_cost 122 { 123 const int GP2GP; 124 const int GP2FP; 125 const int FP2GP; 126 const int FP2FP; 127 }; 128 129 struct tune_params 130 { 131 const struct cpu_rtx_cost_table *const insn_extra_cost; 132 const struct cpu_addrcost_table *const addr_cost; 133 const struct cpu_regmove_cost *const regmove_cost; 134 const int memmov_cost; 135 }; 136 137 HOST_WIDE_INT aarch64_initial_elimination_offset (unsigned, unsigned); 138 bool aarch64_bitmask_imm (HOST_WIDE_INT val, enum machine_mode); 139 bool aarch64_constant_address_p (rtx); 140 bool aarch64_float_const_zero_rtx_p (rtx); 141 bool aarch64_function_arg_regno_p (unsigned); 142 bool aarch64_gen_movmemqi (rtx *); 143 bool aarch64_is_extend_from_extract (enum machine_mode, rtx, rtx); 144 bool aarch64_is_long_call_p (rtx); 145 bool aarch64_label_mentioned_p (rtx); 146 bool aarch64_legitimate_pic_operand_p (rtx); 147 bool aarch64_move_imm (HOST_WIDE_INT, enum machine_mode); 148 bool aarch64_pad_arg_upward (enum machine_mode, const_tree); 149 bool aarch64_pad_reg_upward (enum machine_mode, const_tree, bool); 150 bool aarch64_regno_ok_for_base_p (int, bool); 151 bool aarch64_regno_ok_for_index_p (int, bool); 152 bool aarch64_simd_imm_scalar_p (rtx x, enum machine_mode mode); 153 bool aarch64_simd_imm_zero_p (rtx, enum machine_mode); 154 bool aarch64_simd_shift_imm_p (rtx, enum machine_mode, bool); 155 bool aarch64_symbolic_address_p (rtx); 156 bool aarch64_symbolic_constant_p (rtx, enum aarch64_symbol_context, 157 enum aarch64_symbol_type *); 158 bool aarch64_uimm12_shift (HOST_WIDE_INT); 159 const char *aarch64_output_casesi (rtx *); 160 enum aarch64_symbol_type aarch64_classify_symbol (rtx, 161 enum aarch64_symbol_context); 162 enum aarch64_symbol_type aarch64_classify_tls_symbol (rtx); 163 enum reg_class aarch64_regno_regclass (unsigned); 164 int aarch64_asm_preferred_eh_data_format (int, int); 165 int aarch64_hard_regno_mode_ok (unsigned, enum machine_mode); 166 int aarch64_hard_regno_nregs (unsigned, enum machine_mode); 167 int aarch64_simd_attr_length_move (rtx); 168 int aarch64_simd_immediate_valid_for_move (rtx, enum machine_mode, rtx *, 169 int *, unsigned char *, int *, 170 int *); 171 int aarch64_uxt_size (int, HOST_WIDE_INT); 172 rtx aarch64_final_eh_return_addr (void); 173 rtx aarch64_legitimize_reload_address (rtx *, enum machine_mode, int, int, int); 174 const char *aarch64_output_move_struct (rtx *operands); 175 rtx aarch64_return_addr (int, rtx); 176 rtx aarch64_simd_gen_const_vector_dup (enum machine_mode, int); 177 bool aarch64_simd_mem_operand_p (rtx); 178 rtx aarch64_simd_vect_par_cnst_half (enum machine_mode, bool); 179 rtx aarch64_tls_get_addr (void); 180 unsigned aarch64_dbx_register_number (unsigned); 181 unsigned aarch64_trampoline_size (void); 182 void aarch64_asm_output_labelref (FILE *, const char *); 183 void aarch64_elf_asm_named_section (const char *, unsigned, tree); 184 void aarch64_expand_epilogue (bool); 185 void aarch64_expand_mov_immediate (rtx, rtx); 186 void aarch64_expand_prologue (void); 187 void aarch64_expand_vector_init (rtx, rtx); 188 void aarch64_function_profiler (FILE *, int); 189 void aarch64_init_cumulative_args (CUMULATIVE_ARGS *, const_tree, rtx, 190 const_tree, unsigned); 191 void aarch64_init_expanders (void); 192 void aarch64_print_operand (FILE *, rtx, char); 193 void aarch64_print_operand_address (FILE *, rtx); 194 195 /* Initialize builtins for SIMD intrinsics. */ 196 void init_aarch64_simd_builtins (void); 197 198 void aarch64_simd_const_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT); 199 void aarch64_simd_disambiguate_copy (rtx *, rtx *, rtx *, unsigned int); 200 201 /* Emit code to place a AdvSIMD pair result in memory locations (with equal 202 registers). */ 203 void aarch64_simd_emit_pair_result_insn (enum machine_mode, 204 rtx (*intfn) (rtx, rtx, rtx), rtx, 205 rtx); 206 207 /* Expand builtins for SIMD intrinsics. */ 208 rtx aarch64_simd_expand_builtin (int, tree, rtx); 209 210 void aarch64_simd_lane_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT); 211 212 /* Emit code for reinterprets. */ 213 void aarch64_simd_reinterpret (rtx, rtx); 214 215 void aarch64_split_128bit_move (rtx, rtx); 216 217 bool aarch64_split_128bit_move_p (rtx, rtx); 218 219 /* Check for a legitimate floating point constant for FMOV. */ 220 bool aarch64_float_const_representable_p (rtx); 221 222 #if defined (RTX_CODE) 223 224 bool aarch64_legitimate_address_p (enum machine_mode, rtx, RTX_CODE, bool); 225 enum machine_mode aarch64_select_cc_mode (RTX_CODE, rtx, rtx); 226 rtx aarch64_gen_compare_reg (RTX_CODE, rtx, rtx); 227 rtx aarch64_load_tp (rtx); 228 229 void aarch64_expand_compare_and_swap (rtx op[]); 230 void aarch64_split_compare_and_swap (rtx op[]); 231 void aarch64_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx); 232 233 #endif /* RTX_CODE */ 234 235 void aarch64_init_builtins (void); 236 rtx aarch64_expand_builtin (tree exp, 237 rtx target, 238 rtx subtarget ATTRIBUTE_UNUSED, 239 enum machine_mode mode ATTRIBUTE_UNUSED, 240 int ignore ATTRIBUTE_UNUSED); 241 tree aarch64_builtin_decl (unsigned, bool ATTRIBUTE_UNUSED); 242 243 tree 244 aarch64_builtin_vectorized_function (tree fndecl, 245 tree type_out, 246 tree type_in); 247 248 extern void aarch64_split_combinev16qi (rtx operands[3]); 249 extern void aarch64_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel); 250 extern bool aarch64_madd_needs_nop (rtx); 251 extern void aarch64_final_prescan_insn (rtx); 252 extern bool 253 aarch64_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel); 254 255 char* aarch64_output_simd_mov_immediate (rtx *, enum machine_mode, unsigned); 256 #endif /* GCC_AARCH64_PROTOS_H */ 257
Indexes created Wed Jul 15 00:26:21 UTC 2026