aarch64-protos.h revision 1.4
1 /* Machine description for AArch64 architecture. 2 Copyright (C) 2009-2016 Free Software Foundation, Inc. 3 Contributed by ARM Ltd. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GCC is distributed in the hope that it will be useful, but 13 WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 22 #ifndef GCC_AARCH64_PROTOS_H 23 #define GCC_AARCH64_PROTOS_H 24 25 #include "input.h" 26 27 /* SYMBOL_SMALL_ABSOLUTE: Generate symbol accesses through 28 high and lo relocs that calculate the base address using a PC 29 relative reloc. 30 So to get the address of foo, we generate 31 adrp x0, foo 32 add x0, x0, :lo12:foo 33 34 To load or store something to foo, we could use the corresponding 35 load store variants that generate an 36 ldr x0, [x0,:lo12:foo] 37 or 38 str x1, [x0, :lo12:foo] 39 40 This corresponds to the small code model of the compiler. 41 42 SYMBOL_SMALL_GOT_4G: Similar to the one above but this 43 gives us the GOT entry of the symbol being referred to : 44 Thus calculating the GOT entry for foo is done using the 45 following sequence of instructions. The ADRP instruction 46 gets us to the page containing the GOT entry of the symbol 47 and the got_lo12 gets us the actual offset in it, together 48 the base and offset, we can address 4G size GOT table. 49 50 adrp x0, :got:foo 51 ldr x0, [x0, :gotoff_lo12:foo] 52 53 This corresponds to the small PIC model of the compiler. 54 55 SYMBOL_SMALL_GOT_28K: Similar to SYMBOL_SMALL_GOT_4G, but used for symbol 56 restricted within 28K GOT table size. 57 58 ldr reg, [gp, #:gotpage_lo15:sym] 59 60 This corresponds to -fpic model for small memory model of the compiler. 61 62 SYMBOL_SMALL_TLSGD 63 SYMBOL_SMALL_TLSDESC 64 SYMBOL_SMALL_TLSIE 65 SYMBOL_TINY_TLSIE 66 SYMBOL_TLSLE12 67 SYMBOL_TLSLE24 68 SYMBOL_TLSLE32 69 SYMBOL_TLSLE48 70 Each of these represents a thread-local symbol, and corresponds to the 71 thread local storage relocation operator for the symbol being referred to. 72 73 SYMBOL_TINY_ABSOLUTE 74 75 Generate symbol accesses as a PC relative address using a single 76 instruction. To compute the address of symbol foo, we generate: 77 78 ADR x0, foo 79 80 SYMBOL_TINY_GOT 81 82 Generate symbol accesses via the GOT using a single PC relative 83 instruction. To compute the address of symbol foo, we generate: 84 85 ldr t0, :got:foo 86 87 The value of foo can subsequently read using: 88 89 ldrb t0, [t0] 90 91 SYMBOL_FORCE_TO_MEM : Global variables are addressed using 92 constant pool. All variable addresses are spilled into constant 93 pools. The constant pools themselves are addressed using PC 94 relative accesses. This only works for the large code model. 95 */ 96 enum aarch64_symbol_type 97 { 98 SYMBOL_SMALL_ABSOLUTE, 99 SYMBOL_SMALL_GOT_28K, 100 SYMBOL_SMALL_GOT_4G, 101 SYMBOL_SMALL_TLSGD, 102 SYMBOL_SMALL_TLSDESC, 103 SYMBOL_SMALL_TLSIE, 104 SYMBOL_TINY_ABSOLUTE, 105 SYMBOL_TINY_GOT, 106 SYMBOL_TINY_TLSIE, 107 SYMBOL_TLSLE12, 108 SYMBOL_TLSLE24, 109 SYMBOL_TLSLE32, 110 SYMBOL_TLSLE48, 111 SYMBOL_FORCE_TO_MEM 112 }; 113 114 /* A set of tuning parameters contains references to size and time 115 cost models and vectors for address cost calculations, register 116 move costs and memory move costs. */ 117 118 /* Scaled addressing modes can vary cost depending on the mode of the 119 value to be loaded/stored. QImode values cannot use scaled 120 addressing modes. */ 121 122 struct scale_addr_mode_cost 123 { 124 const int hi; 125 const int si; 126 const int di; 127 const int ti; 128 }; 129 130 /* Additional cost for addresses. */ 131 struct cpu_addrcost_table 132 { 133 const struct scale_addr_mode_cost addr_scale_costs; 134 const int pre_modify; 135 const int post_modify; 136 const int register_offset; 137 const int register_sextend; 138 const int register_zextend; 139 const int imm_offset; 140 }; 141 142 /* Additional costs for register copies. Cost is for one register. */ 143 struct cpu_regmove_cost 144 { 145 const int GP2GP; 146 const int GP2FP; 147 const int FP2GP; 148 const int FP2FP; 149 }; 150 151 /* Cost for vector insn classes. */ 152 struct cpu_vector_cost 153 { 154 const int scalar_stmt_cost; /* Cost of any scalar operation, 155 excluding load and store. */ 156 const int scalar_load_cost; /* Cost of scalar load. */ 157 const int scalar_store_cost; /* Cost of scalar store. */ 158 const int vec_stmt_cost; /* Cost of any vector operation, 159 excluding load, store, permute, 160 vector-to-scalar and 161 scalar-to-vector operation. */ 162 const int vec_permute_cost; /* Cost of permute operation. */ 163 const int vec_to_scalar_cost; /* Cost of vec-to-scalar operation. */ 164 const int scalar_to_vec_cost; /* Cost of scalar-to-vector 165 operation. */ 166 const int vec_align_load_cost; /* Cost of aligned vector load. */ 167 const int vec_unalign_load_cost; /* Cost of unaligned vector load. */ 168 const int vec_unalign_store_cost; /* Cost of unaligned vector store. */ 169 const int vec_store_cost; /* Cost of vector store. */ 170 const int cond_taken_branch_cost; /* Cost of taken branch. */ 171 const int cond_not_taken_branch_cost; /* Cost of not taken branch. */ 172 }; 173 174 /* Branch costs. */ 175 struct cpu_branch_cost 176 { 177 const int predictable; /* Predictable branch or optimizing for size. */ 178 const int unpredictable; /* Unpredictable branch or optimizing for speed. */ 179 }; 180 181 struct tune_params 182 { 183 const struct cpu_cost_table *insn_extra_cost; 184 const struct cpu_addrcost_table *addr_cost; 185 const struct cpu_regmove_cost *regmove_cost; 186 const struct cpu_vector_cost *vec_costs; 187 const struct cpu_branch_cost *branch_costs; 188 int memmov_cost; 189 int issue_rate; 190 unsigned int fusible_ops; 191 int function_align; 192 int jump_align; 193 int loop_align; 194 int int_reassoc_width; 195 int fp_reassoc_width; 196 int vec_reassoc_width; 197 int min_div_recip_mul_sf; 198 int min_div_recip_mul_df; 199 /* Value for aarch64_case_values_threshold; or 0 for the default. */ 200 unsigned int max_case_values; 201 /* Value for PARAM_L1_CACHE_LINE_SIZE; or 0 to use the default. */ 202 unsigned int cache_line_size; 203 204 /* An enum specifying how to take into account CPU autoprefetch capabilities 205 during instruction scheduling: 206 - AUTOPREFETCHER_OFF: Do not take autoprefetch capabilities into account. 207 - AUTOPREFETCHER_WEAK: Attempt to sort sequences of loads/store in order of 208 offsets but allow the pipeline hazard recognizer to alter that order to 209 maximize multi-issue opportunities. 210 - AUTOPREFETCHER_STRONG: Attempt to sort sequences of loads/store in order of 211 offsets and prefer this even if it restricts multi-issue opportunities. */ 212 213 enum aarch64_autoprefetch_model 214 { 215 AUTOPREFETCHER_OFF, 216 AUTOPREFETCHER_WEAK, 217 AUTOPREFETCHER_STRONG 218 } autoprefetcher_model; 219 220 unsigned int extra_tuning_flags; 221 }; 222 223 #define AARCH64_FUSION_PAIR(x, name) \ 224 AARCH64_FUSE_##name##_index, 225 /* Supported fusion operations. */ 226 enum aarch64_fusion_pairs_index 227 { 228 #include "aarch64-fusion-pairs.def" 229 AARCH64_FUSE_index_END 230 }; 231 #undef AARCH64_FUSION_PAIR 232 233 #define AARCH64_FUSION_PAIR(x, name) \ 234 AARCH64_FUSE_##name = (1u << AARCH64_FUSE_##name##_index), 235 /* Supported fusion operations. */ 236 enum aarch64_fusion_pairs 237 { 238 AARCH64_FUSE_NOTHING = 0, 239 #include "aarch64-fusion-pairs.def" 240 AARCH64_FUSE_ALL = (1u << AARCH64_FUSE_index_END) - 1 241 }; 242 #undef AARCH64_FUSION_PAIR 243 244 #define AARCH64_EXTRA_TUNING_OPTION(x, name) \ 245 AARCH64_EXTRA_TUNE_##name##_index, 246 /* Supported tuning flags indexes. */ 247 enum aarch64_extra_tuning_flags_index 248 { 249 #include "aarch64-tuning-flags.def" 250 AARCH64_EXTRA_TUNE_index_END 251 }; 252 #undef AARCH64_EXTRA_TUNING_OPTION 253 254 255 #define AARCH64_EXTRA_TUNING_OPTION(x, name) \ 256 AARCH64_EXTRA_TUNE_##name = (1u << AARCH64_EXTRA_TUNE_##name##_index), 257 /* Supported tuning flags. */ 258 enum aarch64_extra_tuning_flags 259 { 260 AARCH64_EXTRA_TUNE_NONE = 0, 261 #include "aarch64-tuning-flags.def" 262 AARCH64_EXTRA_TUNE_ALL = (1u << AARCH64_EXTRA_TUNE_index_END) - 1 263 }; 264 #undef AARCH64_EXTRA_TUNING_OPTION 265 266 /* Enum describing the various ways that the 267 aarch64_parse_{arch,tune,cpu,extension} functions can fail. 268 This way their callers can choose what kind of error to give. */ 269 270 enum aarch64_parse_opt_result 271 { 272 AARCH64_PARSE_OK, /* Parsing was successful. */ 273 AARCH64_PARSE_MISSING_ARG, /* Missing argument. */ 274 AARCH64_PARSE_INVALID_FEATURE, /* Invalid feature modifier. */ 275 AARCH64_PARSE_INVALID_ARG /* Invalid arch, tune, cpu arg. */ 276 }; 277 278 extern struct tune_params aarch64_tune_params; 279 280 HOST_WIDE_INT aarch64_initial_elimination_offset (unsigned, unsigned); 281 int aarch64_get_condition_code (rtx); 282 bool aarch64_bitmask_imm (HOST_WIDE_INT val, machine_mode); 283 int aarch64_branch_cost (bool, bool); 284 enum aarch64_symbol_type aarch64_classify_symbolic_expression (rtx); 285 bool aarch64_cannot_change_mode_class (machine_mode, 286 machine_mode, 287 enum reg_class); 288 bool aarch64_const_vec_all_same_int_p (rtx, HOST_WIDE_INT); 289 bool aarch64_constant_address_p (rtx); 290 bool aarch64_expand_movmem (rtx *); 291 bool aarch64_float_const_zero_rtx_p (rtx); 292 bool aarch64_function_arg_regno_p (unsigned); 293 bool aarch64_gen_movmemqi (rtx *); 294 bool aarch64_gimple_fold_builtin (gimple_stmt_iterator *); 295 bool aarch64_is_extend_from_extract (machine_mode, rtx, rtx); 296 bool aarch64_is_long_call_p (rtx); 297 bool aarch64_is_noplt_call_p (rtx); 298 bool aarch64_label_mentioned_p (rtx); 299 void aarch64_declare_function_name (FILE *, const char*, tree); 300 bool aarch64_legitimate_pic_operand_p (rtx); 301 bool aarch64_modes_tieable_p (machine_mode mode1, 302 machine_mode mode2); 303 bool aarch64_zero_extend_const_eq (machine_mode, rtx, machine_mode, rtx); 304 bool aarch64_move_imm (HOST_WIDE_INT, machine_mode); 305 bool aarch64_mov_operand_p (rtx, machine_mode); 306 int aarch64_simd_attr_length_rglist (enum machine_mode); 307 rtx aarch64_reverse_mask (enum machine_mode); 308 bool aarch64_offset_7bit_signed_scaled_p (machine_mode, HOST_WIDE_INT); 309 char *aarch64_output_scalar_simd_mov_immediate (rtx, machine_mode); 310 char *aarch64_output_simd_mov_immediate (rtx, machine_mode, unsigned); 311 bool aarch64_pad_arg_upward (machine_mode, const_tree); 312 bool aarch64_pad_reg_upward (machine_mode, const_tree, bool); 313 bool aarch64_regno_ok_for_base_p (int, bool); 314 bool aarch64_regno_ok_for_index_p (int, bool); 315 bool aarch64_simd_check_vect_par_cnst_half (rtx op, machine_mode mode, 316 bool high); 317 bool aarch64_simd_imm_scalar_p (rtx x, machine_mode mode); 318 bool aarch64_simd_imm_zero_p (rtx, machine_mode); 319 bool aarch64_simd_scalar_immediate_valid_for_move (rtx, machine_mode); 320 bool aarch64_simd_shift_imm_p (rtx, machine_mode, bool); 321 bool aarch64_simd_valid_immediate (rtx, machine_mode, bool, 322 struct simd_immediate_info *); 323 bool aarch64_symbolic_address_p (rtx); 324 bool aarch64_uimm12_shift (HOST_WIDE_INT); 325 bool aarch64_use_return_insn_p (void); 326 const char *aarch64_mangle_builtin_type (const_tree); 327 const char *aarch64_output_casesi (rtx *); 328 329 enum aarch64_symbol_type aarch64_classify_symbol (rtx, rtx); 330 enum aarch64_symbol_type aarch64_classify_tls_symbol (rtx); 331 enum reg_class aarch64_regno_regclass (unsigned); 332 int aarch64_asm_preferred_eh_data_format (int, int); 333 int aarch64_fpconst_pow_of_2 (rtx); 334 machine_mode aarch64_hard_regno_caller_save_mode (unsigned, unsigned, 335 machine_mode); 336 int aarch64_hard_regno_mode_ok (unsigned, machine_mode); 337 int aarch64_hard_regno_nregs (unsigned, machine_mode); 338 int aarch64_simd_attr_length_move (rtx_insn *); 339 int aarch64_uxt_size (int, HOST_WIDE_INT); 340 int aarch64_vec_fpconst_pow_of_2 (rtx); 341 rtx aarch64_eh_return_handler_rtx (void); 342 rtx aarch64_legitimize_reload_address (rtx *, machine_mode, int, int, int); 343 rtx aarch64_mask_from_zextract_ops (rtx, rtx); 344 const char *aarch64_output_move_struct (rtx *operands); 345 rtx aarch64_return_addr (int, rtx); 346 rtx aarch64_simd_gen_const_vector_dup (machine_mode, int); 347 bool aarch64_simd_mem_operand_p (rtx); 348 rtx aarch64_simd_vect_par_cnst_half (machine_mode, bool); 349 rtx aarch64_tls_get_addr (void); 350 tree aarch64_fold_builtin (tree, int, tree *, bool); 351 unsigned aarch64_dbx_register_number (unsigned); 352 unsigned aarch64_trampoline_size (void); 353 void aarch64_asm_output_labelref (FILE *, const char *); 354 void aarch64_cpu_cpp_builtins (cpp_reader *); 355 void aarch64_elf_asm_named_section (const char *, unsigned, tree); 356 const char * aarch64_gen_far_branch (rtx *, int, const char *, const char *); 357 const char * aarch64_output_probe_stack_range (rtx, rtx); 358 void aarch64_err_no_fpadvsimd (machine_mode, const char *); 359 void aarch64_expand_epilogue (bool); 360 void aarch64_expand_mov_immediate (rtx, rtx); 361 void aarch64_expand_prologue (void); 362 void aarch64_expand_vector_init (rtx, rtx); 363 void aarch64_init_cumulative_args (CUMULATIVE_ARGS *, const_tree, rtx, 364 const_tree, unsigned); 365 void aarch64_init_expanders (void); 366 void aarch64_init_simd_builtins (void); 367 void aarch64_emit_call_insn (rtx); 368 void aarch64_register_pragmas (void); 369 void aarch64_relayout_simd_types (void); 370 void aarch64_reset_previous_fndecl (void); 371 void aarch64_save_restore_target_globals (tree); 372 void aarch64_emit_approx_rsqrt (rtx, rtx); 373 374 /* Initialize builtins for SIMD intrinsics. */ 375 void init_aarch64_simd_builtins (void); 376 377 void aarch64_simd_emit_reg_reg_move (rtx *, enum machine_mode, unsigned int); 378 379 /* Expand builtins for SIMD intrinsics. */ 380 rtx aarch64_simd_expand_builtin (int, tree, rtx); 381 382 void aarch64_simd_lane_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT, const_tree); 383 384 void aarch64_split_128bit_move (rtx, rtx); 385 386 bool aarch64_split_128bit_move_p (rtx, rtx); 387 388 void aarch64_split_simd_combine (rtx, rtx, rtx); 389 390 void aarch64_split_simd_move (rtx, rtx); 391 392 /* Check for a legitimate floating point constant for FMOV. */ 393 bool aarch64_float_const_representable_p (rtx); 394 395 #if defined (RTX_CODE) 396 397 bool aarch64_legitimate_address_p (machine_mode, rtx, RTX_CODE, bool); 398 machine_mode aarch64_select_cc_mode (RTX_CODE, rtx, rtx); 399 rtx aarch64_gen_compare_reg (RTX_CODE, rtx, rtx); 400 rtx aarch64_load_tp (rtx); 401 402 void aarch64_expand_compare_and_swap (rtx op[]); 403 void aarch64_split_compare_and_swap (rtx op[]); 404 void aarch64_gen_atomic_cas (rtx, rtx, rtx, rtx, rtx); 405 406 bool aarch64_atomic_ldop_supported_p (enum rtx_code); 407 void aarch64_gen_atomic_ldop (enum rtx_code, rtx, rtx, rtx, rtx, rtx); 408 void aarch64_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx); 409 410 bool aarch64_gen_adjusted_ldpstp (rtx *, bool, enum machine_mode, RTX_CODE); 411 #endif /* RTX_CODE */ 412 413 void aarch64_init_builtins (void); 414 415 bool aarch64_process_target_attr (tree, const char*); 416 void aarch64_override_options_internal (struct gcc_options *); 417 418 rtx aarch64_expand_builtin (tree exp, 419 rtx target, 420 rtx subtarget ATTRIBUTE_UNUSED, 421 machine_mode mode ATTRIBUTE_UNUSED, 422 int ignore ATTRIBUTE_UNUSED); 423 tree aarch64_builtin_decl (unsigned, bool ATTRIBUTE_UNUSED); 424 tree aarch64_builtin_rsqrt (unsigned int); 425 tree aarch64_builtin_vectorized_function (unsigned int, tree, tree); 426 427 extern void aarch64_split_combinev16qi (rtx operands[3]); 428 extern void aarch64_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel); 429 extern bool aarch64_madd_needs_nop (rtx_insn *); 430 extern void aarch64_final_prescan_insn (rtx_insn *); 431 extern bool 432 aarch64_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel); 433 void aarch64_atomic_assign_expand_fenv (tree *, tree *, tree *); 434 int aarch64_ccmp_mode_to_code (enum machine_mode mode); 435 436 bool extract_base_offset_in_addr (rtx mem, rtx *base, rtx *offset); 437 bool aarch64_operands_ok_for_ldpstp (rtx *, bool, enum machine_mode); 438 bool aarch64_operands_adjust_ok_for_ldpstp (rtx *, bool, enum machine_mode); 439 extern bool aarch64_nopcrelative_literal_loads; 440 441 extern void aarch64_asm_output_pool_epilogue (FILE *, const char *, 442 tree, HOST_WIDE_INT); 443 444 /* Defined in common/config/aarch64-common.c. */ 445 bool aarch64_handle_option (struct gcc_options *, struct gcc_options *, 446 const struct cl_decoded_option *, location_t); 447 const char *aarch64_rewrite_selected_cpu (const char *name); 448 enum aarch64_parse_opt_result aarch64_parse_extension (const char *, 449 unsigned long *); 450 std::string aarch64_get_extension_string_for_isa_flags (unsigned long, 451 unsigned long); 452 453 #endif /* GCC_AARCH64_PROTOS_H */ 454
Indexes created Wed Jul 15 00:26:21 UTC 2026