aarch64-simd-builtins.def revision 1.1
1 1.1 mrg /* Machine description for AArch64 architecture. 2 1.1 mrg Copyright (C) 2012-2013 Free Software Foundation, Inc. 3 1.1 mrg Contributed by ARM Ltd. 4 1.1 mrg 5 1.1 mrg This file is part of GCC. 6 1.1 mrg 7 1.1 mrg GCC is free software; you can redistribute it and/or modify it 8 1.1 mrg under the terms of the GNU General Public License as published by 9 1.1 mrg the Free Software Foundation; either version 3, or (at your option) 10 1.1 mrg any later version. 11 1.1 mrg 12 1.1 mrg GCC is distributed in the hope that it will be useful, but 13 1.1 mrg WITHOUT ANY WARRANTY; without even the implied warranty of 14 1.1 mrg MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 1.1 mrg General Public License for more details. 16 1.1 mrg 17 1.1 mrg You should have received a copy of the GNU General Public License 18 1.1 mrg along with GCC; see the file COPYING3. If not see 19 1.1 mrg <http://www.gnu.org/licenses/>. */ 20 1.1 mrg 21 1.1 mrg /* In the list below, the BUILTIN_<ITERATOR> macros should 22 1.1 mrg correspond to the iterator used to construct the instruction's 23 1.1 mrg patterns in aarch64-simd.md. A helpful idiom to follow when 24 1.1 mrg adding new builtins is to add a line for each pattern in the md 25 1.1 mrg file. Thus, ADDP, which has one pattern defined for the VD_BHSI 26 1.1 mrg iterator, and one for DImode, has two entries below. */ 27 1.1 mrg 28 1.1 mrg BUILTIN_VD_RE (CREATE, create) 29 1.1 mrg BUILTIN_VQ_S (GETLANE, get_lane_signed) 30 1.1 mrg BUILTIN_VDQ (GETLANE, get_lane_unsigned) 31 1.1 mrg BUILTIN_VDQF (GETLANE, get_lane) 32 1.1 mrg VAR1 (GETLANE, get_lane, di) 33 1.1 mrg BUILTIN_VDC (COMBINE, combine) 34 1.1 mrg BUILTIN_VB (BINOP, pmul) 35 1.1 mrg BUILTIN_VDQF (UNOP, sqrt) 36 1.1 mrg BUILTIN_VD_BHSI (BINOP, addp) 37 1.1 mrg VAR1 (UNOP, addp, di) 38 1.1 mrg 39 1.1 mrg BUILTIN_VD_RE (REINTERP, reinterpretdi) 40 1.1 mrg BUILTIN_VDC (REINTERP, reinterpretv8qi) 41 1.1 mrg BUILTIN_VDC (REINTERP, reinterpretv4hi) 42 1.1 mrg BUILTIN_VDC (REINTERP, reinterpretv2si) 43 1.1 mrg BUILTIN_VDC (REINTERP, reinterpretv2sf) 44 1.1 mrg BUILTIN_VQ (REINTERP, reinterpretv16qi) 45 1.1 mrg BUILTIN_VQ (REINTERP, reinterpretv8hi) 46 1.1 mrg BUILTIN_VQ (REINTERP, reinterpretv4si) 47 1.1 mrg BUILTIN_VQ (REINTERP, reinterpretv4sf) 48 1.1 mrg BUILTIN_VQ (REINTERP, reinterpretv2di) 49 1.1 mrg BUILTIN_VQ (REINTERP, reinterpretv2df) 50 1.1 mrg 51 1.1 mrg BUILTIN_VDQ_I (BINOP, dup_lane) 52 1.1 mrg BUILTIN_SDQ_I (BINOP, dup_lane) 53 1.1 mrg /* Implemented by aarch64_<sur>q<r>shl<mode>. */ 54 1.1 mrg BUILTIN_VSDQ_I (BINOP, sqshl) 55 1.1 mrg BUILTIN_VSDQ_I (BINOP, uqshl) 56 1.1 mrg BUILTIN_VSDQ_I (BINOP, sqrshl) 57 1.1 mrg BUILTIN_VSDQ_I (BINOP, uqrshl) 58 1.1 mrg /* Implemented by aarch64_<su_optab><optab><mode>. */ 59 1.1 mrg BUILTIN_VSDQ_I (BINOP, sqadd) 60 1.1 mrg BUILTIN_VSDQ_I (BINOP, uqadd) 61 1.1 mrg BUILTIN_VSDQ_I (BINOP, sqsub) 62 1.1 mrg BUILTIN_VSDQ_I (BINOP, uqsub) 63 1.1 mrg /* Implemented by aarch64_<sur>qadd<mode>. */ 64 1.1 mrg BUILTIN_VSDQ_I (BINOP, suqadd) 65 1.1 mrg BUILTIN_VSDQ_I (BINOP, usqadd) 66 1.1 mrg 67 1.1 mrg /* Implemented by aarch64_get_dreg<VSTRUCT:mode><VDC:mode>. */ 68 1.1 mrg BUILTIN_VDC (GETLANE, get_dregoi) 69 1.1 mrg BUILTIN_VDC (GETLANE, get_dregci) 70 1.1 mrg BUILTIN_VDC (GETLANE, get_dregxi) 71 1.1 mrg /* Implemented by aarch64_get_qreg<VSTRUCT:mode><VQ:mode>. */ 72 1.1 mrg BUILTIN_VQ (GETLANE, get_qregoi) 73 1.1 mrg BUILTIN_VQ (GETLANE, get_qregci) 74 1.1 mrg BUILTIN_VQ (GETLANE, get_qregxi) 75 1.1 mrg /* Implemented by aarch64_set_qreg<VSTRUCT:mode><VQ:mode>. */ 76 1.1 mrg BUILTIN_VQ (SETLANE, set_qregoi) 77 1.1 mrg BUILTIN_VQ (SETLANE, set_qregci) 78 1.1 mrg BUILTIN_VQ (SETLANE, set_qregxi) 79 1.1 mrg /* Implemented by aarch64_ld<VSTRUCT:nregs><VDC:mode>. */ 80 1.1 mrg BUILTIN_VDC (LOADSTRUCT, ld2) 81 1.1 mrg BUILTIN_VDC (LOADSTRUCT, ld3) 82 1.1 mrg BUILTIN_VDC (LOADSTRUCT, ld4) 83 1.1 mrg /* Implemented by aarch64_ld<VSTRUCT:nregs><VQ:mode>. */ 84 1.1 mrg BUILTIN_VQ (LOADSTRUCT, ld2) 85 1.1 mrg BUILTIN_VQ (LOADSTRUCT, ld3) 86 1.1 mrg BUILTIN_VQ (LOADSTRUCT, ld4) 87 1.1 mrg /* Implemented by aarch64_st<VSTRUCT:nregs><VDC:mode>. */ 88 1.1 mrg BUILTIN_VDC (STORESTRUCT, st2) 89 1.1 mrg BUILTIN_VDC (STORESTRUCT, st3) 90 1.1 mrg BUILTIN_VDC (STORESTRUCT, st4) 91 1.1 mrg /* Implemented by aarch64_st<VSTRUCT:nregs><VQ:mode>. */ 92 1.1 mrg BUILTIN_VQ (STORESTRUCT, st2) 93 1.1 mrg BUILTIN_VQ (STORESTRUCT, st3) 94 1.1 mrg BUILTIN_VQ (STORESTRUCT, st4) 95 1.1 mrg 96 1.1 mrg BUILTIN_VQW (BINOP, saddl2) 97 1.1 mrg BUILTIN_VQW (BINOP, uaddl2) 98 1.1 mrg BUILTIN_VQW (BINOP, ssubl2) 99 1.1 mrg BUILTIN_VQW (BINOP, usubl2) 100 1.1 mrg BUILTIN_VQW (BINOP, saddw2) 101 1.1 mrg BUILTIN_VQW (BINOP, uaddw2) 102 1.1 mrg BUILTIN_VQW (BINOP, ssubw2) 103 1.1 mrg BUILTIN_VQW (BINOP, usubw2) 104 1.1 mrg /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>. */ 105 1.1 mrg BUILTIN_VDW (BINOP, saddl) 106 1.1 mrg BUILTIN_VDW (BINOP, uaddl) 107 1.1 mrg BUILTIN_VDW (BINOP, ssubl) 108 1.1 mrg BUILTIN_VDW (BINOP, usubl) 109 1.1 mrg /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>. */ 110 1.1 mrg BUILTIN_VDW (BINOP, saddw) 111 1.1 mrg BUILTIN_VDW (BINOP, uaddw) 112 1.1 mrg BUILTIN_VDW (BINOP, ssubw) 113 1.1 mrg BUILTIN_VDW (BINOP, usubw) 114 1.1 mrg /* Implemented by aarch64_<sur>h<addsub><mode>. */ 115 1.1 mrg BUILTIN_VQ_S (BINOP, shadd) 116 1.1 mrg BUILTIN_VQ_S (BINOP, uhadd) 117 1.1 mrg BUILTIN_VQ_S (BINOP, srhadd) 118 1.1 mrg BUILTIN_VQ_S (BINOP, urhadd) 119 1.1 mrg /* Implemented by aarch64_<sur><addsub>hn<mode>. */ 120 1.1 mrg BUILTIN_VQN (BINOP, addhn) 121 1.1 mrg BUILTIN_VQN (BINOP, raddhn) 122 1.1 mrg /* Implemented by aarch64_<sur><addsub>hn2<mode>. */ 123 1.1 mrg BUILTIN_VQN (TERNOP, addhn2) 124 1.1 mrg BUILTIN_VQN (TERNOP, raddhn2) 125 1.1 mrg 126 1.1 mrg BUILTIN_VSQN_HSDI (UNOP, sqmovun) 127 1.1 mrg /* Implemented by aarch64_<sur>qmovn<mode>. */ 128 1.1 mrg BUILTIN_VSQN_HSDI (UNOP, sqmovn) 129 1.1 mrg BUILTIN_VSQN_HSDI (UNOP, uqmovn) 130 1.1 mrg /* Implemented by aarch64_s<optab><mode>. */ 131 1.1 mrg BUILTIN_VSDQ_I_BHSI (UNOP, sqabs) 132 1.1 mrg BUILTIN_VSDQ_I_BHSI (UNOP, sqneg) 133 1.1 mrg 134 1.1 mrg BUILTIN_VSD_HSI (QUADOP, sqdmlal_lane) 135 1.1 mrg BUILTIN_VSD_HSI (QUADOP, sqdmlsl_lane) 136 1.1 mrg BUILTIN_VSD_HSI (QUADOP, sqdmlal_laneq) 137 1.1 mrg BUILTIN_VSD_HSI (QUADOP, sqdmlsl_laneq) 138 1.1 mrg BUILTIN_VQ_HSI (TERNOP, sqdmlal2) 139 1.1 mrg BUILTIN_VQ_HSI (TERNOP, sqdmlsl2) 140 1.1 mrg BUILTIN_VQ_HSI (QUADOP, sqdmlal2_lane) 141 1.1 mrg BUILTIN_VQ_HSI (QUADOP, sqdmlsl2_lane) 142 1.1 mrg BUILTIN_VQ_HSI (QUADOP, sqdmlal2_laneq) 143 1.1 mrg BUILTIN_VQ_HSI (QUADOP, sqdmlsl2_laneq) 144 1.1 mrg BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n) 145 1.1 mrg BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n) 146 1.1 mrg /* Implemented by aarch64_sqdml<SBINQOPS:as>l<mode>. */ 147 1.1 mrg BUILTIN_VSD_HSI (TERNOP, sqdmlal) 148 1.1 mrg BUILTIN_VSD_HSI (TERNOP, sqdmlsl) 149 1.1 mrg /* Implemented by aarch64_sqdml<SBINQOPS:as>l_n<mode>. */ 150 1.1 mrg BUILTIN_VD_HSI (TERNOP, sqdmlal_n) 151 1.1 mrg BUILTIN_VD_HSI (TERNOP, sqdmlsl_n) 152 1.1 mrg 153 1.1 mrg BUILTIN_VSD_HSI (BINOP, sqdmull) 154 1.1 mrg BUILTIN_VSD_HSI (TERNOP, sqdmull_lane) 155 1.1 mrg BUILTIN_VD_HSI (TERNOP, sqdmull_laneq) 156 1.1 mrg BUILTIN_VD_HSI (BINOP, sqdmull_n) 157 1.1 mrg BUILTIN_VQ_HSI (BINOP, sqdmull2) 158 1.1 mrg BUILTIN_VQ_HSI (TERNOP, sqdmull2_lane) 159 1.1 mrg BUILTIN_VQ_HSI (TERNOP, sqdmull2_laneq) 160 1.1 mrg BUILTIN_VQ_HSI (BINOP, sqdmull2_n) 161 1.1 mrg /* Implemented by aarch64_sq<r>dmulh<mode>. */ 162 1.1 mrg BUILTIN_VSDQ_HSI (BINOP, sqdmulh) 163 1.1 mrg BUILTIN_VSDQ_HSI (BINOP, sqrdmulh) 164 1.1 mrg /* Implemented by aarch64_sq<r>dmulh_lane<q><mode>. */ 165 1.1 mrg BUILTIN_VDQHS (TERNOP, sqdmulh_lane) 166 1.1 mrg BUILTIN_VDQHS (TERNOP, sqdmulh_laneq) 167 1.1 mrg BUILTIN_VDQHS (TERNOP, sqrdmulh_lane) 168 1.1 mrg BUILTIN_VDQHS (TERNOP, sqrdmulh_laneq) 169 1.1 mrg BUILTIN_SD_HSI (TERNOP, sqdmulh_lane) 170 1.1 mrg BUILTIN_SD_HSI (TERNOP, sqrdmulh_lane) 171 1.1 mrg 172 1.1 mrg BUILTIN_VSDQ_I_DI (BINOP, sshl_n) 173 1.1 mrg BUILTIN_VSDQ_I_DI (BINOP, ushl_n) 174 1.1 mrg /* Implemented by aarch64_<sur>shl<mode>. */ 175 1.1 mrg BUILTIN_VSDQ_I_DI (BINOP, sshl) 176 1.1 mrg BUILTIN_VSDQ_I_DI (BINOP, ushl) 177 1.1 mrg BUILTIN_VSDQ_I_DI (BINOP, srshl) 178 1.1 mrg BUILTIN_VSDQ_I_DI (BINOP, urshl) 179 1.1 mrg 180 1.1 mrg BUILTIN_VSDQ_I_DI (SHIFTIMM, sshr_n) 181 1.1 mrg BUILTIN_VSDQ_I_DI (SHIFTIMM, ushr_n) 182 1.1 mrg /* Implemented by aarch64_<sur>shr_n<mode>. */ 183 1.1 mrg BUILTIN_VSDQ_I_DI (SHIFTIMM, srshr_n) 184 1.1 mrg BUILTIN_VSDQ_I_DI (SHIFTIMM, urshr_n) 185 1.1 mrg /* Implemented by aarch64_<sur>sra_n<mode>. */ 186 1.1 mrg BUILTIN_VSDQ_I_DI (SHIFTACC, ssra_n) 187 1.1 mrg BUILTIN_VSDQ_I_DI (SHIFTACC, usra_n) 188 1.1 mrg BUILTIN_VSDQ_I_DI (SHIFTACC, srsra_n) 189 1.1 mrg BUILTIN_VSDQ_I_DI (SHIFTACC, ursra_n) 190 1.1 mrg /* Implemented by aarch64_<sur>shll_n<mode>. */ 191 1.1 mrg BUILTIN_VDW (SHIFTIMM, sshll_n) 192 1.1 mrg BUILTIN_VDW (SHIFTIMM, ushll_n) 193 1.1 mrg /* Implemented by aarch64_<sur>shll2_n<mode>. */ 194 1.1 mrg BUILTIN_VQW (SHIFTIMM, sshll2_n) 195 1.1 mrg BUILTIN_VQW (SHIFTIMM, ushll2_n) 196 1.1 mrg /* Implemented by aarch64_<sur>q<r>shr<u>n_n<mode>. */ 197 1.1 mrg BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrun_n) 198 1.1 mrg BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrun_n) 199 1.1 mrg BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrn_n) 200 1.1 mrg BUILTIN_VSQN_HSDI (SHIFTIMM, uqshrn_n) 201 1.1 mrg BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrn_n) 202 1.1 mrg BUILTIN_VSQN_HSDI (SHIFTIMM, uqrshrn_n) 203 1.1 mrg /* Implemented by aarch64_<sur>s<lr>i_n<mode>. */ 204 1.1 mrg BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssri_n) 205 1.1 mrg BUILTIN_VSDQ_I_DI (SHIFTINSERT, usri_n) 206 1.1 mrg BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssli_n) 207 1.1 mrg BUILTIN_VSDQ_I_DI (SHIFTINSERT, usli_n) 208 1.1 mrg /* Implemented by aarch64_<sur>qshl<u>_n<mode>. */ 209 1.1 mrg BUILTIN_VSDQ_I (SHIFTIMM, sqshlu_n) 210 1.1 mrg BUILTIN_VSDQ_I (SHIFTIMM, sqshl_n) 211 1.1 mrg BUILTIN_VSDQ_I (SHIFTIMM, uqshl_n) 212 1.1 mrg 213 1.1 mrg /* Implemented by aarch64_cm<cmp><mode>. */ 214 1.1 mrg BUILTIN_VSDQ_I_DI (BINOP, cmeq) 215 1.1 mrg BUILTIN_VSDQ_I_DI (BINOP, cmge) 216 1.1 mrg BUILTIN_VSDQ_I_DI (BINOP, cmgt) 217 1.1 mrg BUILTIN_VSDQ_I_DI (BINOP, cmle) 218 1.1 mrg BUILTIN_VSDQ_I_DI (BINOP, cmlt) 219 1.1 mrg /* Implemented by aarch64_cm<cmp><mode>. */ 220 1.1 mrg BUILTIN_VSDQ_I_DI (BINOP, cmgeu) 221 1.1 mrg BUILTIN_VSDQ_I_DI (BINOP, cmgtu) 222 1.1 mrg BUILTIN_VSDQ_I_DI (BINOP, cmtst) 223 1.1 mrg 224 1.1 mrg /* Implemented by aarch64_<fmaxmin><mode>. */ 225 1.1 mrg BUILTIN_VDQF (BINOP, fmax) 226 1.1 mrg BUILTIN_VDQF (BINOP, fmin) 227 1.1 mrg /* Implemented by aarch64_<maxmin><mode>. */ 228 1.1 mrg BUILTIN_VDQ_BHSI (BINOP, smax) 229 1.1 mrg BUILTIN_VDQ_BHSI (BINOP, smin) 230 1.1 mrg BUILTIN_VDQ_BHSI (BINOP, umax) 231 1.1 mrg BUILTIN_VDQ_BHSI (BINOP, umin) 232 1.1 mrg 233 1.1 mrg /* Implemented by aarch64_frint<frint_suffix><mode>. */ 234 1.1 mrg BUILTIN_VDQF (UNOP, frintz) 235 1.1 mrg BUILTIN_VDQF (UNOP, frintp) 236 1.1 mrg BUILTIN_VDQF (UNOP, frintm) 237 1.1 mrg BUILTIN_VDQF (UNOP, frinti) 238 1.1 mrg BUILTIN_VDQF (UNOP, frintx) 239 1.1 mrg BUILTIN_VDQF (UNOP, frinta) 240 1.1 mrg 241 1.1 mrg /* Implemented by aarch64_fcvt<frint_suffix><su><mode>. */ 242 1.1 mrg BUILTIN_VDQF (UNOP, fcvtzs) 243 1.1 mrg BUILTIN_VDQF (UNOP, fcvtzu) 244 1.1 mrg BUILTIN_VDQF (UNOP, fcvtas) 245 1.1 mrg BUILTIN_VDQF (UNOP, fcvtau) 246 1.1 mrg BUILTIN_VDQF (UNOP, fcvtps) 247 1.1 mrg BUILTIN_VDQF (UNOP, fcvtpu) 248 1.1 mrg BUILTIN_VDQF (UNOP, fcvtms) 249 1.1 mrg BUILTIN_VDQF (UNOP, fcvtmu) 250 1.1 mrg 251 1.1 mrg /* Implemented by 252 1.1 mrg aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>. */ 253 1.1 mrg BUILTIN_VALL (BINOP, zip1) 254 1.1 mrg BUILTIN_VALL (BINOP, zip2) 255 1.1 mrg BUILTIN_VALL (BINOP, uzp1) 256 1.1 mrg BUILTIN_VALL (BINOP, uzp2) 257 1.1 mrg BUILTIN_VALL (BINOP, trn1) 258 1.1 mrg BUILTIN_VALL (BINOP, trn2) 259 1.1 mrg 260 1.1 mrg /* Implemented by aarch64_ld1<VALL:mode>. */ 261 1.1 mrg BUILTIN_VALL (LOAD1, ld1) 262 1.1 mrg 263 1.1 mrg /* Implemented by aarch64_st1<VALL:mode>. */ 264 1.1 mrg BUILTIN_VALL (STORE1, st1) 265 1.1 mrg 266
Indexes created Wed Jul 22 00:25:13 UTC 2026