aarch64-simd-builtins.def revision 1.4
1 1.1 mrg /* Machine description for AArch64 architecture. 2 1.4 mrg Copyright (C) 2012-2016 Free Software Foundation, Inc. 3 1.1 mrg Contributed by ARM Ltd. 4 1.1 mrg 5 1.1 mrg This file is part of GCC. 6 1.1 mrg 7 1.1 mrg GCC is free software; you can redistribute it and/or modify it 8 1.1 mrg under the terms of the GNU General Public License as published by 9 1.1 mrg the Free Software Foundation; either version 3, or (at your option) 10 1.1 mrg any later version. 11 1.1 mrg 12 1.1 mrg GCC is distributed in the hope that it will be useful, but 13 1.1 mrg WITHOUT ANY WARRANTY; without even the implied warranty of 14 1.1 mrg MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 1.1 mrg General Public License for more details. 16 1.1 mrg 17 1.1 mrg You should have received a copy of the GNU General Public License 18 1.1 mrg along with GCC; see the file COPYING3. If not see 19 1.1 mrg <http://www.gnu.org/licenses/>. */ 20 1.1 mrg 21 1.3 mrg /* In the list below, the BUILTIN_<ITERATOR> macros expand to create 22 1.3 mrg builtins for each of the modes described by <ITERATOR>. When adding 23 1.3 mrg new builtins to this list, a helpful idiom to follow is to add 24 1.3 mrg a line for each pattern in the md file. Thus, ADDP, which has one 25 1.3 mrg pattern defined for the VD_BHSI iterator, and one for DImode, has two 26 1.3 mrg entries below. 27 1.3 mrg 28 1.3 mrg Parameter 1 is the 'type' of the intrinsic. This is used to 29 1.3 mrg describe the type modifiers (for example; unsigned) applied to 30 1.3 mrg each of the parameters to the intrinsic function. 31 1.3 mrg 32 1.3 mrg Parameter 2 is the name of the intrinsic. This is appended 33 1.3 mrg to `__builtin_aarch64_<name><mode>` to give the intrinsic name 34 1.3 mrg as exported to the front-ends. 35 1.3 mrg 36 1.3 mrg Parameter 3 describes how to map from the name to the CODE_FOR_ 37 1.3 mrg macro holding the RTL pattern for the intrinsic. This mapping is: 38 1.3 mrg 0 - CODE_FOR_aarch64_<name><mode> 39 1.3 mrg 1-9 - CODE_FOR_<name><mode><1-9> 40 1.3 mrg 10 - CODE_FOR_<name><mode>. */ 41 1.3 mrg 42 1.3 mrg BUILTIN_VDC (COMBINE, combine, 0) 43 1.3 mrg BUILTIN_VB (BINOP, pmul, 0) 44 1.4 mrg BUILTIN_VALLF (BINOP, fmulx, 0) 45 1.3 mrg BUILTIN_VDQF_DF (UNOP, sqrt, 2) 46 1.3 mrg BUILTIN_VD_BHSI (BINOP, addp, 0) 47 1.3 mrg VAR1 (UNOP, addp, 0, di) 48 1.3 mrg BUILTIN_VDQ_BHSI (UNOP, clrsb, 2) 49 1.3 mrg BUILTIN_VDQ_BHSI (UNOP, clz, 2) 50 1.3 mrg BUILTIN_VS (UNOP, ctz, 2) 51 1.3 mrg BUILTIN_VB (UNOP, popcount, 2) 52 1.1 mrg 53 1.1 mrg /* Implemented by aarch64_<sur>q<r>shl<mode>. */ 54 1.3 mrg BUILTIN_VSDQ_I (BINOP, sqshl, 0) 55 1.3 mrg BUILTIN_VSDQ_I (BINOP_UUS, uqshl, 0) 56 1.3 mrg BUILTIN_VSDQ_I (BINOP, sqrshl, 0) 57 1.3 mrg BUILTIN_VSDQ_I (BINOP_UUS, uqrshl, 0) 58 1.1 mrg /* Implemented by aarch64_<su_optab><optab><mode>. */ 59 1.3 mrg BUILTIN_VSDQ_I (BINOP, sqadd, 0) 60 1.3 mrg BUILTIN_VSDQ_I (BINOPU, uqadd, 0) 61 1.3 mrg BUILTIN_VSDQ_I (BINOP, sqsub, 0) 62 1.3 mrg BUILTIN_VSDQ_I (BINOPU, uqsub, 0) 63 1.1 mrg /* Implemented by aarch64_<sur>qadd<mode>. */ 64 1.3 mrg BUILTIN_VSDQ_I (BINOP_SSU, suqadd, 0) 65 1.3 mrg BUILTIN_VSDQ_I (BINOP_UUS, usqadd, 0) 66 1.1 mrg 67 1.1 mrg /* Implemented by aarch64_get_dreg<VSTRUCT:mode><VDC:mode>. */ 68 1.3 mrg BUILTIN_VDC (GETREG, get_dregoi, 0) 69 1.3 mrg BUILTIN_VDC (GETREG, get_dregci, 0) 70 1.3 mrg BUILTIN_VDC (GETREG, get_dregxi, 0) 71 1.1 mrg /* Implemented by aarch64_get_qreg<VSTRUCT:mode><VQ:mode>. */ 72 1.3 mrg BUILTIN_VQ (GETREG, get_qregoi, 0) 73 1.3 mrg BUILTIN_VQ (GETREG, get_qregci, 0) 74 1.3 mrg BUILTIN_VQ (GETREG, get_qregxi, 0) 75 1.1 mrg /* Implemented by aarch64_set_qreg<VSTRUCT:mode><VQ:mode>. */ 76 1.3 mrg BUILTIN_VQ (SETREG, set_qregoi, 0) 77 1.3 mrg BUILTIN_VQ (SETREG, set_qregci, 0) 78 1.3 mrg BUILTIN_VQ (SETREG, set_qregxi, 0) 79 1.1 mrg /* Implemented by aarch64_ld<VSTRUCT:nregs><VDC:mode>. */ 80 1.3 mrg BUILTIN_VDC (LOADSTRUCT, ld2, 0) 81 1.3 mrg BUILTIN_VDC (LOADSTRUCT, ld3, 0) 82 1.3 mrg BUILTIN_VDC (LOADSTRUCT, ld4, 0) 83 1.1 mrg /* Implemented by aarch64_ld<VSTRUCT:nregs><VQ:mode>. */ 84 1.3 mrg BUILTIN_VQ (LOADSTRUCT, ld2, 0) 85 1.3 mrg BUILTIN_VQ (LOADSTRUCT, ld3, 0) 86 1.3 mrg BUILTIN_VQ (LOADSTRUCT, ld4, 0) 87 1.3 mrg /* Implemented by aarch64_ld<VSTRUCT:nregs>r<VALLDIF:mode>. */ 88 1.3 mrg BUILTIN_VALLDIF (LOADSTRUCT, ld2r, 0) 89 1.3 mrg BUILTIN_VALLDIF (LOADSTRUCT, ld3r, 0) 90 1.3 mrg BUILTIN_VALLDIF (LOADSTRUCT, ld4r, 0) 91 1.3 mrg /* Implemented by aarch64_ld<VSTRUCT:nregs>_lane<VQ:mode>. */ 92 1.4 mrg BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld2_lane, 0) 93 1.4 mrg BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld3_lane, 0) 94 1.4 mrg BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld4_lane, 0) 95 1.1 mrg /* Implemented by aarch64_st<VSTRUCT:nregs><VDC:mode>. */ 96 1.3 mrg BUILTIN_VDC (STORESTRUCT, st2, 0) 97 1.3 mrg BUILTIN_VDC (STORESTRUCT, st3, 0) 98 1.3 mrg BUILTIN_VDC (STORESTRUCT, st4, 0) 99 1.1 mrg /* Implemented by aarch64_st<VSTRUCT:nregs><VQ:mode>. */ 100 1.3 mrg BUILTIN_VQ (STORESTRUCT, st2, 0) 101 1.3 mrg BUILTIN_VQ (STORESTRUCT, st3, 0) 102 1.3 mrg BUILTIN_VQ (STORESTRUCT, st4, 0) 103 1.3 mrg 104 1.4 mrg BUILTIN_VALLDIF (STORESTRUCT_LANE, st2_lane, 0) 105 1.4 mrg BUILTIN_VALLDIF (STORESTRUCT_LANE, st3_lane, 0) 106 1.4 mrg BUILTIN_VALLDIF (STORESTRUCT_LANE, st4_lane, 0) 107 1.3 mrg 108 1.3 mrg BUILTIN_VQW (BINOP, saddl2, 0) 109 1.3 mrg BUILTIN_VQW (BINOP, uaddl2, 0) 110 1.3 mrg BUILTIN_VQW (BINOP, ssubl2, 0) 111 1.3 mrg BUILTIN_VQW (BINOP, usubl2, 0) 112 1.3 mrg BUILTIN_VQW (BINOP, saddw2, 0) 113 1.3 mrg BUILTIN_VQW (BINOP, uaddw2, 0) 114 1.3 mrg BUILTIN_VQW (BINOP, ssubw2, 0) 115 1.3 mrg BUILTIN_VQW (BINOP, usubw2, 0) 116 1.1 mrg /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>. */ 117 1.3 mrg BUILTIN_VD_BHSI (BINOP, saddl, 0) 118 1.3 mrg BUILTIN_VD_BHSI (BINOP, uaddl, 0) 119 1.3 mrg BUILTIN_VD_BHSI (BINOP, ssubl, 0) 120 1.3 mrg BUILTIN_VD_BHSI (BINOP, usubl, 0) 121 1.1 mrg /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>. */ 122 1.3 mrg BUILTIN_VD_BHSI (BINOP, saddw, 0) 123 1.3 mrg BUILTIN_VD_BHSI (BINOP, uaddw, 0) 124 1.3 mrg BUILTIN_VD_BHSI (BINOP, ssubw, 0) 125 1.3 mrg BUILTIN_VD_BHSI (BINOP, usubw, 0) 126 1.1 mrg /* Implemented by aarch64_<sur>h<addsub><mode>. */ 127 1.3 mrg BUILTIN_VDQ_BHSI (BINOP, shadd, 0) 128 1.3 mrg BUILTIN_VDQ_BHSI (BINOP, shsub, 0) 129 1.3 mrg BUILTIN_VDQ_BHSI (BINOP, uhadd, 0) 130 1.3 mrg BUILTIN_VDQ_BHSI (BINOP, uhsub, 0) 131 1.3 mrg BUILTIN_VDQ_BHSI (BINOP, srhadd, 0) 132 1.3 mrg BUILTIN_VDQ_BHSI (BINOP, urhadd, 0) 133 1.1 mrg /* Implemented by aarch64_<sur><addsub>hn<mode>. */ 134 1.3 mrg BUILTIN_VQN (BINOP, addhn, 0) 135 1.3 mrg BUILTIN_VQN (BINOP, subhn, 0) 136 1.3 mrg BUILTIN_VQN (BINOP, raddhn, 0) 137 1.3 mrg BUILTIN_VQN (BINOP, rsubhn, 0) 138 1.1 mrg /* Implemented by aarch64_<sur><addsub>hn2<mode>. */ 139 1.3 mrg BUILTIN_VQN (TERNOP, addhn2, 0) 140 1.3 mrg BUILTIN_VQN (TERNOP, subhn2, 0) 141 1.3 mrg BUILTIN_VQN (TERNOP, raddhn2, 0) 142 1.3 mrg BUILTIN_VQN (TERNOP, rsubhn2, 0) 143 1.1 mrg 144 1.3 mrg BUILTIN_VSQN_HSDI (UNOP, sqmovun, 0) 145 1.1 mrg /* Implemented by aarch64_<sur>qmovn<mode>. */ 146 1.3 mrg BUILTIN_VSQN_HSDI (UNOP, sqmovn, 0) 147 1.3 mrg BUILTIN_VSQN_HSDI (UNOP, uqmovn, 0) 148 1.1 mrg /* Implemented by aarch64_s<optab><mode>. */ 149 1.3 mrg BUILTIN_VSDQ_I (UNOP, sqabs, 0) 150 1.3 mrg BUILTIN_VSDQ_I (UNOP, sqneg, 0) 151 1.1 mrg 152 1.1 mrg /* Implemented by aarch64_sqdml<SBINQOPS:as>l<mode>. */ 153 1.3 mrg BUILTIN_VSD_HSI (TERNOP, sqdmlal, 0) 154 1.3 mrg BUILTIN_VSD_HSI (TERNOP, sqdmlsl, 0) 155 1.3 mrg /* Implemented by aarch64_sqdml<SBINQOPS:as>l_lane<mode>. */ 156 1.3 mrg BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlal_lane, 0) 157 1.3 mrg BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlsl_lane, 0) 158 1.3 mrg /* Implemented by aarch64_sqdml<SBINQOPS:as>l_laneq<mode>. */ 159 1.3 mrg BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlal_laneq, 0) 160 1.3 mrg BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlsl_laneq, 0) 161 1.1 mrg /* Implemented by aarch64_sqdml<SBINQOPS:as>l_n<mode>. */ 162 1.3 mrg BUILTIN_VD_HSI (TERNOP, sqdmlal_n, 0) 163 1.3 mrg BUILTIN_VD_HSI (TERNOP, sqdmlsl_n, 0) 164 1.1 mrg 165 1.3 mrg BUILTIN_VQ_HSI (TERNOP, sqdmlal2, 0) 166 1.3 mrg BUILTIN_VQ_HSI (TERNOP, sqdmlsl2, 0) 167 1.3 mrg BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlal2_lane, 0) 168 1.3 mrg BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlsl2_lane, 0) 169 1.3 mrg BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlal2_laneq, 0) 170 1.3 mrg BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlsl2_laneq, 0) 171 1.3 mrg BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n, 0) 172 1.3 mrg BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n, 0) 173 1.3 mrg 174 1.3 mrg BUILTIN_VSD_HSI (BINOP, sqdmull, 0) 175 1.3 mrg BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_lane, 0) 176 1.3 mrg BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_laneq, 0) 177 1.3 mrg BUILTIN_VD_HSI (BINOP, sqdmull_n, 0) 178 1.3 mrg BUILTIN_VQ_HSI (BINOP, sqdmull2, 0) 179 1.3 mrg BUILTIN_VQ_HSI (TERNOP_LANE, sqdmull2_lane, 0) 180 1.3 mrg BUILTIN_VQ_HSI (TERNOP_LANE, sqdmull2_laneq, 0) 181 1.3 mrg BUILTIN_VQ_HSI (BINOP, sqdmull2_n, 0) 182 1.1 mrg /* Implemented by aarch64_sq<r>dmulh<mode>. */ 183 1.3 mrg BUILTIN_VSDQ_HSI (BINOP, sqdmulh, 0) 184 1.3 mrg BUILTIN_VSDQ_HSI (BINOP, sqrdmulh, 0) 185 1.1 mrg /* Implemented by aarch64_sq<r>dmulh_lane<q><mode>. */ 186 1.3 mrg BUILTIN_VSDQ_HSI (TERNOP_LANE, sqdmulh_lane, 0) 187 1.3 mrg BUILTIN_VSDQ_HSI (TERNOP_LANE, sqdmulh_laneq, 0) 188 1.3 mrg BUILTIN_VSDQ_HSI (TERNOP_LANE, sqrdmulh_lane, 0) 189 1.3 mrg BUILTIN_VSDQ_HSI (TERNOP_LANE, sqrdmulh_laneq, 0) 190 1.1 mrg 191 1.3 mrg BUILTIN_VSDQ_I_DI (BINOP, ashl, 3) 192 1.1 mrg /* Implemented by aarch64_<sur>shl<mode>. */ 193 1.3 mrg BUILTIN_VSDQ_I_DI (BINOP, sshl, 0) 194 1.3 mrg BUILTIN_VSDQ_I_DI (BINOP_UUS, ushl, 0) 195 1.3 mrg BUILTIN_VSDQ_I_DI (BINOP, srshl, 0) 196 1.3 mrg BUILTIN_VSDQ_I_DI (BINOP_UUS, urshl, 0) 197 1.3 mrg 198 1.3 mrg BUILTIN_VDQ_I (SHIFTIMM, ashr, 3) 199 1.3 mrg VAR1 (SHIFTIMM, ashr_simd, 0, di) 200 1.3 mrg BUILTIN_VDQ_I (SHIFTIMM, lshr, 3) 201 1.3 mrg VAR1 (USHIFTIMM, lshr_simd, 0, di) 202 1.1 mrg /* Implemented by aarch64_<sur>shr_n<mode>. */ 203 1.3 mrg BUILTIN_VSDQ_I_DI (SHIFTIMM, srshr_n, 0) 204 1.3 mrg BUILTIN_VSDQ_I_DI (USHIFTIMM, urshr_n, 0) 205 1.1 mrg /* Implemented by aarch64_<sur>sra_n<mode>. */ 206 1.3 mrg BUILTIN_VSDQ_I_DI (SHIFTACC, ssra_n, 0) 207 1.3 mrg BUILTIN_VSDQ_I_DI (USHIFTACC, usra_n, 0) 208 1.3 mrg BUILTIN_VSDQ_I_DI (SHIFTACC, srsra_n, 0) 209 1.3 mrg BUILTIN_VSDQ_I_DI (USHIFTACC, ursra_n, 0) 210 1.1 mrg /* Implemented by aarch64_<sur>shll_n<mode>. */ 211 1.3 mrg BUILTIN_VD_BHSI (SHIFTIMM, sshll_n, 0) 212 1.3 mrg BUILTIN_VD_BHSI (USHIFTIMM, ushll_n, 0) 213 1.1 mrg /* Implemented by aarch64_<sur>shll2_n<mode>. */ 214 1.3 mrg BUILTIN_VQW (SHIFTIMM, sshll2_n, 0) 215 1.3 mrg BUILTIN_VQW (SHIFTIMM, ushll2_n, 0) 216 1.1 mrg /* Implemented by aarch64_<sur>q<r>shr<u>n_n<mode>. */ 217 1.3 mrg BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrun_n, 0) 218 1.3 mrg BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrun_n, 0) 219 1.3 mrg BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrn_n, 0) 220 1.3 mrg BUILTIN_VSQN_HSDI (USHIFTIMM, uqshrn_n, 0) 221 1.3 mrg BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrn_n, 0) 222 1.3 mrg BUILTIN_VSQN_HSDI (USHIFTIMM, uqrshrn_n, 0) 223 1.1 mrg /* Implemented by aarch64_<sur>s<lr>i_n<mode>. */ 224 1.3 mrg BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssri_n, 0) 225 1.3 mrg BUILTIN_VSDQ_I_DI (USHIFTACC, usri_n, 0) 226 1.3 mrg BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssli_n, 0) 227 1.3 mrg BUILTIN_VSDQ_I_DI (USHIFTACC, usli_n, 0) 228 1.1 mrg /* Implemented by aarch64_<sur>qshl<u>_n<mode>. */ 229 1.3 mrg BUILTIN_VSDQ_I (SHIFTIMM_USS, sqshlu_n, 0) 230 1.3 mrg BUILTIN_VSDQ_I (SHIFTIMM, sqshl_n, 0) 231 1.3 mrg BUILTIN_VSDQ_I (USHIFTIMM, uqshl_n, 0) 232 1.3 mrg 233 1.3 mrg /* Implemented by aarch64_reduc_plus_<mode>. */ 234 1.3 mrg BUILTIN_VALL (UNOP, reduc_plus_scal_, 10) 235 1.3 mrg 236 1.3 mrg /* Implemented by reduc_<maxmin_uns>_scal_<mode> (producing scalar). */ 237 1.3 mrg BUILTIN_VDQIF (UNOP, reduc_smax_scal_, 10) 238 1.3 mrg BUILTIN_VDQIF (UNOP, reduc_smin_scal_, 10) 239 1.3 mrg BUILTIN_VDQ_BHSI (UNOPU, reduc_umax_scal_, 10) 240 1.3 mrg BUILTIN_VDQ_BHSI (UNOPU, reduc_umin_scal_, 10) 241 1.3 mrg BUILTIN_VDQF (UNOP, reduc_smax_nan_scal_, 10) 242 1.3 mrg BUILTIN_VDQF (UNOP, reduc_smin_nan_scal_, 10) 243 1.3 mrg 244 1.3 mrg /* Implemented by <maxmin><mode>3. 245 1.3 mrg smax variants map to fmaxnm, 246 1.3 mrg smax_nan variants map to fmax. */ 247 1.4 mrg BUILTIN_VDQ_BHSI (BINOP, smax, 3) 248 1.4 mrg BUILTIN_VDQ_BHSI (BINOP, smin, 3) 249 1.3 mrg BUILTIN_VDQ_BHSI (BINOP, umax, 3) 250 1.3 mrg BUILTIN_VDQ_BHSI (BINOP, umin, 3) 251 1.3 mrg BUILTIN_VDQF (BINOP, smax_nan, 3) 252 1.3 mrg BUILTIN_VDQF (BINOP, smin_nan, 3) 253 1.3 mrg 254 1.4 mrg /* Implemented by <fmaxmin><mode>3. */ 255 1.4 mrg BUILTIN_VDQF (BINOP, fmax, 3) 256 1.4 mrg BUILTIN_VDQF (BINOP, fmin, 3) 257 1.4 mrg 258 1.3 mrg /* Implemented by aarch64_<maxmin_uns>p<mode>. */ 259 1.3 mrg BUILTIN_VDQ_BHSI (BINOP, smaxp, 0) 260 1.3 mrg BUILTIN_VDQ_BHSI (BINOP, sminp, 0) 261 1.3 mrg BUILTIN_VDQ_BHSI (BINOP, umaxp, 0) 262 1.3 mrg BUILTIN_VDQ_BHSI (BINOP, uminp, 0) 263 1.3 mrg BUILTIN_VDQF (BINOP, smaxp, 0) 264 1.3 mrg BUILTIN_VDQF (BINOP, sminp, 0) 265 1.3 mrg BUILTIN_VDQF (BINOP, smax_nanp, 0) 266 1.3 mrg BUILTIN_VDQF (BINOP, smin_nanp, 0) 267 1.3 mrg 268 1.3 mrg /* Implemented by <frint_pattern><mode>2. */ 269 1.3 mrg BUILTIN_VDQF (UNOP, btrunc, 2) 270 1.3 mrg BUILTIN_VDQF (UNOP, ceil, 2) 271 1.3 mrg BUILTIN_VDQF (UNOP, floor, 2) 272 1.3 mrg BUILTIN_VDQF (UNOP, nearbyint, 2) 273 1.3 mrg BUILTIN_VDQF (UNOP, rint, 2) 274 1.3 mrg BUILTIN_VDQF (UNOP, round, 2) 275 1.3 mrg BUILTIN_VDQF_DF (UNOP, frintn, 2) 276 1.3 mrg 277 1.3 mrg /* Implemented by l<fcvt_pattern><su_optab><VQDF:mode><vcvt_target>2. */ 278 1.3 mrg VAR1 (UNOP, lbtruncv2sf, 2, v2si) 279 1.3 mrg VAR1 (UNOP, lbtruncv4sf, 2, v4si) 280 1.3 mrg VAR1 (UNOP, lbtruncv2df, 2, v2di) 281 1.3 mrg 282 1.4 mrg VAR1 (UNOPUS, lbtruncuv2sf, 2, v2si) 283 1.4 mrg VAR1 (UNOPUS, lbtruncuv4sf, 2, v4si) 284 1.4 mrg VAR1 (UNOPUS, lbtruncuv2df, 2, v2di) 285 1.3 mrg 286 1.3 mrg VAR1 (UNOP, lroundv2sf, 2, v2si) 287 1.3 mrg VAR1 (UNOP, lroundv4sf, 2, v4si) 288 1.3 mrg VAR1 (UNOP, lroundv2df, 2, v2di) 289 1.3 mrg /* Implemented by l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2. */ 290 1.3 mrg VAR1 (UNOP, lroundsf, 2, si) 291 1.3 mrg VAR1 (UNOP, lrounddf, 2, di) 292 1.3 mrg 293 1.4 mrg VAR1 (UNOPUS, lrounduv2sf, 2, v2si) 294 1.4 mrg VAR1 (UNOPUS, lrounduv4sf, 2, v4si) 295 1.4 mrg VAR1 (UNOPUS, lrounduv2df, 2, v2di) 296 1.4 mrg VAR1 (UNOPUS, lroundusf, 2, si) 297 1.4 mrg VAR1 (UNOPUS, lroundudf, 2, di) 298 1.3 mrg 299 1.3 mrg VAR1 (UNOP, lceilv2sf, 2, v2si) 300 1.3 mrg VAR1 (UNOP, lceilv4sf, 2, v4si) 301 1.3 mrg VAR1 (UNOP, lceilv2df, 2, v2di) 302 1.3 mrg 303 1.4 mrg VAR1 (UNOPUS, lceiluv2sf, 2, v2si) 304 1.4 mrg VAR1 (UNOPUS, lceiluv4sf, 2, v4si) 305 1.4 mrg VAR1 (UNOPUS, lceiluv2df, 2, v2di) 306 1.4 mrg VAR1 (UNOPUS, lceilusf, 2, si) 307 1.4 mrg VAR1 (UNOPUS, lceiludf, 2, di) 308 1.3 mrg 309 1.3 mrg VAR1 (UNOP, lfloorv2sf, 2, v2si) 310 1.3 mrg VAR1 (UNOP, lfloorv4sf, 2, v4si) 311 1.3 mrg VAR1 (UNOP, lfloorv2df, 2, v2di) 312 1.3 mrg 313 1.4 mrg VAR1 (UNOPUS, lflooruv2sf, 2, v2si) 314 1.4 mrg VAR1 (UNOPUS, lflooruv4sf, 2, v4si) 315 1.4 mrg VAR1 (UNOPUS, lflooruv2df, 2, v2di) 316 1.4 mrg VAR1 (UNOPUS, lfloorusf, 2, si) 317 1.4 mrg VAR1 (UNOPUS, lfloorudf, 2, di) 318 1.3 mrg 319 1.3 mrg VAR1 (UNOP, lfrintnv2sf, 2, v2si) 320 1.3 mrg VAR1 (UNOP, lfrintnv4sf, 2, v4si) 321 1.3 mrg VAR1 (UNOP, lfrintnv2df, 2, v2di) 322 1.3 mrg VAR1 (UNOP, lfrintnsf, 2, si) 323 1.3 mrg VAR1 (UNOP, lfrintndf, 2, di) 324 1.3 mrg 325 1.4 mrg VAR1 (UNOPUS, lfrintnuv2sf, 2, v2si) 326 1.4 mrg VAR1 (UNOPUS, lfrintnuv4sf, 2, v4si) 327 1.4 mrg VAR1 (UNOPUS, lfrintnuv2df, 2, v2di) 328 1.4 mrg VAR1 (UNOPUS, lfrintnusf, 2, si) 329 1.4 mrg VAR1 (UNOPUS, lfrintnudf, 2, di) 330 1.3 mrg 331 1.3 mrg /* Implemented by <optab><fcvt_target><VDQF:mode>2. */ 332 1.3 mrg VAR1 (UNOP, floatv2si, 2, v2sf) 333 1.3 mrg VAR1 (UNOP, floatv4si, 2, v4sf) 334 1.3 mrg VAR1 (UNOP, floatv2di, 2, v2df) 335 1.3 mrg 336 1.3 mrg VAR1 (UNOP, floatunsv2si, 2, v2sf) 337 1.3 mrg VAR1 (UNOP, floatunsv4si, 2, v4sf) 338 1.3 mrg VAR1 (UNOP, floatunsv2di, 2, v2df) 339 1.3 mrg 340 1.3 mrg VAR5 (UNOPU, bswap, 2, v4hi, v8hi, v2si, v4si, v2di) 341 1.3 mrg 342 1.3 mrg BUILTIN_VB (UNOP, rbit, 0) 343 1.1 mrg 344 1.1 mrg /* Implemented by 345 1.1 mrg aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>. */ 346 1.3 mrg BUILTIN_VALL (BINOP, zip1, 0) 347 1.3 mrg BUILTIN_VALL (BINOP, zip2, 0) 348 1.3 mrg BUILTIN_VALL (BINOP, uzp1, 0) 349 1.3 mrg BUILTIN_VALL (BINOP, uzp2, 0) 350 1.3 mrg BUILTIN_VALL (BINOP, trn1, 0) 351 1.3 mrg BUILTIN_VALL (BINOP, trn2, 0) 352 1.3 mrg 353 1.3 mrg /* Implemented by 354 1.3 mrg aarch64_frecp<FRECP:frecp_suffix><mode>. */ 355 1.3 mrg BUILTIN_GPF (UNOP, frecpe, 0) 356 1.3 mrg BUILTIN_GPF (BINOP, frecps, 0) 357 1.3 mrg BUILTIN_GPF (UNOP, frecpx, 0) 358 1.3 mrg 359 1.3 mrg BUILTIN_VDQ_SI (UNOP, urecpe, 0) 360 1.3 mrg 361 1.3 mrg BUILTIN_VDQF (UNOP, frecpe, 0) 362 1.3 mrg BUILTIN_VDQF (BINOP, frecps, 0) 363 1.3 mrg 364 1.3 mrg /* Implemented by a mixture of abs2 patterns. Note the DImode builtin is 365 1.3 mrg only ever used for the int64x1_t intrinsic, there is no scalar version. */ 366 1.3 mrg BUILTIN_VSDQ_I_DI (UNOP, abs, 0) 367 1.3 mrg BUILTIN_VDQF (UNOP, abs, 2) 368 1.3 mrg 369 1.4 mrg BUILTIN_VQ_HSF (UNOP, vec_unpacks_hi_, 10) 370 1.3 mrg VAR1 (BINOP, float_truncate_hi_, 0, v4sf) 371 1.4 mrg VAR1 (BINOP, float_truncate_hi_, 0, v8hf) 372 1.3 mrg 373 1.3 mrg VAR1 (UNOP, float_extend_lo_, 0, v2df) 374 1.4 mrg VAR1 (UNOP, float_extend_lo_, 0, v4sf) 375 1.4 mrg BUILTIN_VDF (UNOP, float_truncate_lo_, 0) 376 1.1 mrg 377 1.4 mrg /* Implemented by aarch64_ld1<VALL_F16:mode>. */ 378 1.4 mrg BUILTIN_VALL_F16 (LOAD1, ld1, 0) 379 1.1 mrg 380 1.4 mrg /* Implemented by aarch64_st1<VALL_F16:mode>. */ 381 1.4 mrg BUILTIN_VALL_F16 (STORE1, st1, 0) 382 1.3 mrg 383 1.3 mrg /* Implemented by fma<mode>4. */ 384 1.3 mrg BUILTIN_VDQF (TERNOP, fma, 4) 385 1.3 mrg 386 1.3 mrg /* Implemented by aarch64_simd_bsl<mode>. */ 387 1.3 mrg BUILTIN_VDQQH (BSL_P, simd_bsl, 0) 388 1.3 mrg BUILTIN_VSDQ_I_DI (BSL_U, simd_bsl, 0) 389 1.3 mrg BUILTIN_VALLDIF (BSL_S, simd_bsl, 0) 390 1.3 mrg 391 1.3 mrg /* Implemented by aarch64_crypto_aes<op><mode>. */ 392 1.3 mrg VAR1 (BINOPU, crypto_aese, 0, v16qi) 393 1.3 mrg VAR1 (BINOPU, crypto_aesd, 0, v16qi) 394 1.3 mrg VAR1 (UNOPU, crypto_aesmc, 0, v16qi) 395 1.3 mrg VAR1 (UNOPU, crypto_aesimc, 0, v16qi) 396 1.3 mrg 397 1.3 mrg /* Implemented by aarch64_crypto_sha1<op><mode>. */ 398 1.3 mrg VAR1 (UNOPU, crypto_sha1h, 0, si) 399 1.3 mrg VAR1 (BINOPU, crypto_sha1su1, 0, v4si) 400 1.3 mrg VAR1 (TERNOPU, crypto_sha1c, 0, v4si) 401 1.3 mrg VAR1 (TERNOPU, crypto_sha1m, 0, v4si) 402 1.3 mrg VAR1 (TERNOPU, crypto_sha1p, 0, v4si) 403 1.3 mrg VAR1 (TERNOPU, crypto_sha1su0, 0, v4si) 404 1.3 mrg 405 1.3 mrg /* Implemented by aarch64_crypto_sha256<op><mode>. */ 406 1.3 mrg VAR1 (TERNOPU, crypto_sha256h, 0, v4si) 407 1.3 mrg VAR1 (TERNOPU, crypto_sha256h2, 0, v4si) 408 1.3 mrg VAR1 (BINOPU, crypto_sha256su0, 0, v4si) 409 1.3 mrg VAR1 (TERNOPU, crypto_sha256su1, 0, v4si) 410 1.3 mrg 411 1.3 mrg /* Implemented by aarch64_crypto_pmull<mode>. */ 412 1.3 mrg VAR1 (BINOPP, crypto_pmull, 0, di) 413 1.3 mrg VAR1 (BINOPP, crypto_pmull, 0, v2di) 414 1.1 mrg 415 1.4 mrg /* Implemented by aarch64_tbl3<mode>. */ 416 1.4 mrg VAR1 (BINOP, tbl3, 0, v8qi) 417 1.4 mrg VAR1 (BINOP, tbl3, 0, v16qi) 418 1.4 mrg 419 1.4 mrg /* Implemented by aarch64_qtbl3<mode>. */ 420 1.4 mrg VAR1 (BINOP, qtbl3, 0, v8qi) 421 1.4 mrg VAR1 (BINOP, qtbl3, 0, v16qi) 422 1.4 mrg 423 1.4 mrg /* Implemented by aarch64_qtbl4<mode>. */ 424 1.4 mrg VAR1 (BINOP, qtbl4, 0, v8qi) 425 1.4 mrg VAR1 (BINOP, qtbl4, 0, v16qi) 426 1.4 mrg 427 1.4 mrg /* Implemented by aarch64_tbx4<mode>. */ 428 1.4 mrg VAR1 (TERNOP, tbx4, 0, v8qi) 429 1.4 mrg VAR1 (TERNOP, tbx4, 0, v16qi) 430 1.4 mrg 431 1.4 mrg /* Implemented by aarch64_qtbx3<mode>. */ 432 1.4 mrg VAR1 (TERNOP, qtbx3, 0, v8qi) 433 1.4 mrg VAR1 (TERNOP, qtbx3, 0, v16qi) 434 1.4 mrg 435 1.4 mrg /* Implemented by aarch64_qtbx4<mode>. */ 436 1.4 mrg VAR1 (TERNOP, qtbx4, 0, v8qi) 437 1.4 mrg VAR1 (TERNOP, qtbx4, 0, v16qi) 438 1.4 mrg 439 1.4 mrg /* Builtins for ARMv8.1 Adv.SIMD instructions. */ 440 1.4 mrg 441 1.4 mrg /* Implemented by aarch64_sqrdml<SQRDMLH_AS:rdma_as>h<mode>. */ 442 1.4 mrg BUILTIN_VSDQ_HSI (TERNOP, sqrdmlah, 0) 443 1.4 mrg BUILTIN_VSDQ_HSI (TERNOP, sqrdmlsh, 0) 444 1.4 mrg 445 1.4 mrg /* Implemented by aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>. */ 446 1.4 mrg BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlah_lane, 0) 447 1.4 mrg BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlsh_lane, 0) 448 1.4 mrg 449 1.4 mrg /* Implemented by aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>. */ 450 1.4 mrg BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlah_laneq, 0) 451 1.4 mrg BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlsh_laneq, 0) 452
Indexes created Wed Jul 22 00:25:13 UTC 2026