alpha.md revision 1.1.1.5
1 1.1 mrg ;; Machine description for DEC Alpha for GNU C compiler 2 1.1.1.4 mrg ;; Copyright (C) 1992-2016 Free Software Foundation, Inc. 3 1.1 mrg ;; Contributed by Richard Kenner (kenner (a] vlsi1.ultra.nyu.edu) 4 1.1 mrg ;; 5 1.1 mrg ;; This file is part of GCC. 6 1.1 mrg ;; 7 1.1 mrg ;; GCC is free software; you can redistribute it and/or modify 8 1.1 mrg ;; it under the terms of the GNU General Public License as published by 9 1.1 mrg ;; the Free Software Foundation; either version 3, or (at your option) 10 1.1 mrg ;; any later version. 11 1.1 mrg ;; 12 1.1 mrg ;; GCC is distributed in the hope that it will be useful, 13 1.1 mrg ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14 1.1 mrg ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 1.1 mrg ;; GNU General Public License for more details. 16 1.1 mrg ;; 17 1.1 mrg ;; You should have received a copy of the GNU General Public License 18 1.1 mrg ;; along with GCC; see the file COPYING3. If not see 19 1.1 mrg ;; <http://www.gnu.org/licenses/>. 20 1.1 mrg 21 1.1 mrg ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 22 1.1 mrg 23 1.1 mrg ;; Uses of UNSPEC in this file: 24 1.1 mrg 25 1.1.1.2 mrg (define_c_enum "unspec" [ 26 1.1.1.2 mrg UNSPEC_XFLT_COMPARE 27 1.1.1.2 mrg UNSPEC_ARG_HOME 28 1.1.1.2 mrg UNSPEC_LDGP1 29 1.1.1.2 mrg UNSPEC_INSXH 30 1.1.1.2 mrg UNSPEC_MSKXH 31 1.1.1.2 mrg UNSPEC_CVTQL 32 1.1.1.2 mrg UNSPEC_CVTLQ 33 1.1.1.2 mrg UNSPEC_LDGP2 34 1.1.1.2 mrg UNSPEC_LITERAL 35 1.1.1.2 mrg UNSPEC_LITUSE 36 1.1.1.2 mrg UNSPEC_SIBCALL 37 1.1.1.2 mrg UNSPEC_SYMBOL 38 1.1.1.2 mrg 39 1.1.1.2 mrg ;; TLS Support 40 1.1.1.2 mrg UNSPEC_TLSGD_CALL 41 1.1.1.2 mrg UNSPEC_TLSLDM_CALL 42 1.1.1.2 mrg UNSPEC_TLSGD 43 1.1.1.2 mrg UNSPEC_TLSLDM 44 1.1.1.2 mrg UNSPEC_DTPREL 45 1.1.1.2 mrg UNSPEC_TPREL 46 1.1.1.2 mrg UNSPEC_TP 47 1.1.1.2 mrg 48 1.1.1.2 mrg ;; Builtins 49 1.1.1.2 mrg UNSPEC_CMPBGE 50 1.1.1.2 mrg UNSPEC_ZAP 51 1.1.1.2 mrg UNSPEC_AMASK 52 1.1.1.2 mrg UNSPEC_IMPLVER 53 1.1.1.2 mrg UNSPEC_PERR 54 1.1.1.2 mrg UNSPEC_COPYSIGN 55 1.1.1.2 mrg 56 1.1.1.2 mrg ;; Atomic operations 57 1.1.1.2 mrg UNSPEC_MB 58 1.1.1.2 mrg UNSPEC_ATOMIC 59 1.1.1.2 mrg UNSPEC_CMPXCHG 60 1.1.1.2 mrg UNSPEC_XCHG 61 1.1.1.2 mrg ]) 62 1.1 mrg 63 1.1 mrg ;; UNSPEC_VOLATILE: 64 1.1 mrg 65 1.1.1.2 mrg (define_c_enum "unspecv" [ 66 1.1.1.2 mrg UNSPECV_IMB 67 1.1.1.2 mrg UNSPECV_BLOCKAGE 68 1.1.1.2 mrg UNSPECV_SETJMPR ; builtin_setjmp_receiver 69 1.1.1.2 mrg UNSPECV_LONGJMP ; builtin_longjmp 70 1.1.1.2 mrg UNSPECV_TRAPB 71 1.1.1.2 mrg UNSPECV_PSPL ; prologue_stack_probe_loop 72 1.1.1.2 mrg UNSPECV_REALIGN 73 1.1.1.2 mrg UNSPECV_EHR ; exception_receiver 74 1.1.1.2 mrg UNSPECV_MCOUNT 75 1.1.1.2 mrg UNSPECV_FORCE_MOV 76 1.1.1.2 mrg UNSPECV_LDGP1 77 1.1.1.2 mrg UNSPECV_PLDGP2 ; prologue ldgp 78 1.1.1.2 mrg UNSPECV_SET_TP 79 1.1.1.2 mrg UNSPECV_RPCC 80 1.1.1.2 mrg UNSPECV_SETJMPR_ER ; builtin_setjmp_receiver fragment 81 1.1.1.2 mrg UNSPECV_LL ; load-locked 82 1.1.1.2 mrg UNSPECV_SC ; store-conditional 83 1.1.1.2 mrg UNSPECV_CMPXCHG 84 1.1.1.2 mrg ]) 85 1.1 mrg 86 1.1 mrg ;; On non-BWX targets, CQImode must be handled the similarly to HImode 87 1.1 mrg ;; when generating reloads. 88 1.1 mrg (define_mode_iterator RELOAD12 [QI HI CQI]) 89 1.1 mrg (define_mode_attr reloadmode [(QI "qi") (HI "hi") (CQI "hi")]) 90 1.1 mrg 91 1.1 mrg ;; Other mode iterators 92 1.1.1.2 mrg (define_mode_iterator IMODE [QI HI SI DI]) 93 1.1 mrg (define_mode_iterator I12MODE [QI HI]) 94 1.1.1.2 mrg (define_mode_iterator I124MODE [QI HI SI]) 95 1.1.1.2 mrg (define_mode_iterator I24MODE [HI SI]) 96 1.1.1.2 mrg (define_mode_iterator I248MODE [HI SI DI]) 97 1.1 mrg (define_mode_iterator I48MODE [SI DI]) 98 1.1.1.2 mrg 99 1.1.1.2 mrg (define_mode_attr DWI [(SI "DI") (DI "TI")]) 100 1.1.1.2 mrg (define_mode_attr modesuffix [(QI "b") (HI "w") (SI "l") (DI "q") 101 1.1.1.2 mrg (V8QI "b8") (V4HI "w4") 102 1.1.1.2 mrg (SF "%,") (DF "%-")]) 103 1.1.1.2 mrg (define_mode_attr vecmodesuffix [(QI "b8") (HI "w4")]) 104 1.1.1.2 mrg 105 1.1.1.2 mrg (define_code_iterator any_maxmin [smax smin umax umin]) 106 1.1.1.2 mrg 107 1.1.1.2 mrg (define_code_attr maxmin [(smax "maxs") (smin "mins") 108 1.1.1.2 mrg (umax "maxu") (umin "minu")]) 109 1.1 mrg 110 1.1 mrg ;; Where necessary, the suffixes _le and _be are used to distinguish between 111 1.1 mrg ;; little-endian and big-endian patterns. 112 1.1 mrg ;; 113 1.1 mrg ;; Note that the Unicos/Mk assembler does not support the following 114 1.1 mrg ;; opcodes: mov, fmov, nop, fnop, unop. 115 1.1 mrg 117 1.1 mrg ;; Processor type -- this attribute must exactly match the processor_type 118 1.1 mrg ;; enumeration in alpha.h. 119 1.1 mrg 120 1.1 mrg (define_attr "tune" "ev4,ev5,ev6" 121 1.1 mrg (const (symbol_ref "((enum attr_tune) alpha_tune)"))) 122 1.1 mrg 123 1.1 mrg ;; Define an insn type attribute. This is used in function unit delay 124 1.1 mrg ;; computations, among other purposes. For the most part, we use the names 125 1.1 mrg ;; defined in the EV4 documentation, but add a few that we have to know about 126 1.1 mrg ;; separately. 127 1.1 mrg 128 1.1 mrg (define_attr "type" 129 1.1 mrg "ild,fld,ldsym,ist,fst,ibr,callpal,fbr,jsr,iadd,ilog,shift,icmov,fcmov, 130 1.1 mrg icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,mb,ld_l,st_c, 131 1.1 mrg multi,none" 132 1.1 mrg (const_string "iadd")) 133 1.1 mrg 134 1.1 mrg ;; Describe a user's asm statement. 135 1.1 mrg (define_asm_attributes 136 1.1 mrg [(set_attr "type" "multi")]) 137 1.1 mrg 138 1.1 mrg ;; Define the operand size an insn operates on. Used primarily by mul 139 1.1 mrg ;; and div operations that have size dependent timings. 140 1.1 mrg 141 1.1 mrg (define_attr "opsize" "si,di,udi" 142 1.1 mrg (const_string "di")) 143 1.1 mrg 144 1.1 mrg ;; The TRAP attribute marks instructions that may generate traps 145 1.1 mrg ;; (which are imprecise and may need a trapb if software completion 146 1.1 mrg ;; is desired). 147 1.1 mrg 148 1.1 mrg (define_attr "trap" "no,yes" 149 1.1 mrg (const_string "no")) 150 1.1 mrg 151 1.1 mrg ;; The ROUND_SUFFIX attribute marks which instructions require a 152 1.1 mrg ;; rounding-mode suffix. The value NONE indicates no suffix, 153 1.1 mrg ;; the value NORMAL indicates a suffix controlled by alpha_fprm. 154 1.1 mrg 155 1.1 mrg (define_attr "round_suffix" "none,normal,c" 156 1.1 mrg (const_string "none")) 157 1.1 mrg 158 1.1 mrg ;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix: 159 1.1 mrg ;; NONE no suffix 160 1.1 mrg ;; SU accepts only /su (cmpt et al) 161 1.1 mrg ;; SUI accepts only /sui (cvtqt and cvtqs) 162 1.1 mrg ;; V_SV accepts /v and /sv (cvtql only) 163 1.1 mrg ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only) 164 1.1 mrg ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions) 165 1.1 mrg ;; 166 1.1 mrg ;; The actual suffix emitted is controlled by alpha_fptm. 167 1.1 mrg 168 1.1 mrg (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui" 169 1.1 mrg (const_string "none")) 170 1.1 mrg 171 1.1 mrg ;; The length of an instruction sequence in bytes. 172 1.1 mrg 173 1.1 mrg (define_attr "length" "" 174 1.1 mrg (const_int 4)) 175 1.1 mrg 176 1.1 mrg ;; The USEGP attribute marks instructions that have relocations that use 177 1.1 mrg ;; the GP. 178 1.1 mrg 179 1.1 mrg (define_attr "usegp" "no,yes" 180 1.1 mrg (cond [(eq_attr "type" "ldsym,jsr") 181 1.1 mrg (const_string "yes") 182 1.1 mrg (eq_attr "type" "ild,fld,ist,fst") 183 1.1 mrg (symbol_ref "((enum attr_usegp) alpha_find_lo_sum_using_gp (insn))") 184 1.1 mrg ] 185 1.1 mrg (const_string "no"))) 186 1.1 mrg 187 1.1 mrg ;; The CANNOT_COPY attribute marks instructions with relocations that 188 1.1 mrg ;; cannot easily be duplicated. This includes insns with gpdisp relocs 189 1.1 mrg ;; since they have to stay in 1-1 correspondence with one another. This 190 1.1 mrg ;; also includes jsr insns, since they must stay in correspondence with 191 1.1 mrg ;; the immediately following gpdisp instructions. 192 1.1 mrg 193 1.1 mrg (define_attr "cannot_copy" "false,true" 194 1.1.1.2 mrg (const_string "false")) 195 1.1.1.2 mrg 196 1.1.1.2 mrg ;; Used to control the "enabled" attribute on a per-instruction basis. 197 1.1.1.2 mrg ;; For convenience, conflate ABI issues re loading of addresses with 198 1.1.1.2 mrg ;; an "isa". 199 1.1.1.2 mrg (define_attr "isa" "base,bwx,max,fix,cix,vms,ner,er" 200 1.1.1.2 mrg (const_string "base")) 201 1.1.1.2 mrg 202 1.1.1.2 mrg (define_attr "enabled" "" 203 1.1.1.2 mrg (cond [(eq_attr "isa" "bwx") (symbol_ref "TARGET_BWX") 204 1.1.1.2 mrg (eq_attr "isa" "max") (symbol_ref "TARGET_MAX") 205 1.1.1.2 mrg (eq_attr "isa" "fix") (symbol_ref "TARGET_FIX") 206 1.1.1.2 mrg (eq_attr "isa" "cix") (symbol_ref "TARGET_CIX") 207 1.1.1.2 mrg (eq_attr "isa" "vms") (symbol_ref "TARGET_ABI_OPEN_VMS") 208 1.1.1.2 mrg (eq_attr "isa" "ner") (symbol_ref "!TARGET_EXPLICIT_RELOCS") 209 1.1.1.2 mrg (eq_attr "isa" "er") (symbol_ref "TARGET_EXPLICIT_RELOCS") 210 1.1.1.2 mrg ] 211 1.1 mrg (const_int 1))) 212 1.1 mrg 214 1.1 mrg ;; Include scheduling descriptions. 215 1.1 mrg 216 1.1 mrg (include "ev4.md") 217 1.1 mrg (include "ev5.md") 218 1.1 mrg (include "ev6.md") 219 1.1 mrg 220 1.1 mrg 222 1.1 mrg ;; Operand and operator predicates and constraints 223 1.1 mrg 224 1.1 mrg (include "predicates.md") 225 1.1 mrg (include "constraints.md") 226 1.1 mrg 227 1.1 mrg 229 1.1 mrg ;; First define the arithmetic insns. Note that the 32-bit forms also 230 1.1 mrg ;; sign-extend. 231 1.1 mrg 232 1.1 mrg ;; Handle 32-64 bit extension from memory to a floating point register 233 1.1 mrg ;; specially, since this occurs frequently in int->double conversions. 234 1.1 mrg ;; 235 1.1 mrg ;; Note that while we must retain the =f case in the insn for reload's 236 1.1.1.2 mrg ;; benefit, it should be eliminated after reload, so we should never emit 237 1.1.1.2 mrg ;; code for that case. But we don't reject the possibility. 238 1.1 mrg 239 1.1 mrg (define_expand "extendsidi2" 240 1.1 mrg [(set (match_operand:DI 0 "register_operand") 241 1.1 mrg (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]) 242 1.1 mrg 243 1.1 mrg (define_insn "*cvtlq" 244 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=f") 245 1.1 mrg (unspec:DI [(match_operand:SF 1 "reg_or_0_operand" "fG")] 246 1.1 mrg UNSPEC_CVTLQ))] 247 1.1 mrg "" 248 1.1 mrg "cvtlq %1,%0" 249 1.1 mrg [(set_attr "type" "fadd")]) 250 1.1 mrg 251 1.1 mrg (define_insn "*extendsidi2_1" 252 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r,r,!*f") 253 1.1 mrg (sign_extend:DI 254 1.1 mrg (match_operand:SI 1 "nonimmediate_operand" "r,m,m")))] 255 1.1 mrg "" 256 1.1 mrg "@ 257 1.1 mrg addl $31,%1,%0 258 1.1 mrg ldl %0,%1 259 1.1 mrg lds %0,%1\;cvtlq %0,%0" 260 1.1.1.2 mrg [(set_attr "type" "iadd,ild,fld") 261 1.1.1.2 mrg (set_attr "length" "*,*,8")]) 262 1.1 mrg 263 1.1 mrg (define_split 264 1.1 mrg [(set (match_operand:DI 0 "hard_fp_register_operand") 265 1.1 mrg (sign_extend:DI (match_operand:SI 1 "memory_operand")))] 266 1.1 mrg "reload_completed" 267 1.1 mrg [(set (match_dup 2) (match_dup 1)) 268 1.1 mrg (set (match_dup 0) (unspec:DI [(match_dup 2)] UNSPEC_CVTLQ))] 269 1.1 mrg { 270 1.1 mrg operands[1] = adjust_address (operands[1], SFmode, 0); 271 1.1 mrg operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0])); 272 1.1 mrg }) 273 1.1 mrg 274 1.1.1.2 mrg ;; Optimize sign-extension of SImode loads. This shows up in the wake of 275 1.1.1.2 mrg ;; reload when converting fp->int. 276 1.1.1.2 mrg 277 1.1 mrg (define_peephole2 278 1.1 mrg [(set (match_operand:SI 0 "hard_int_register_operand") 279 1.1 mrg (match_operand:SI 1 "memory_operand")) 280 1.1 mrg (set (match_operand:DI 2 "hard_int_register_operand") 281 1.1.1.2 mrg (sign_extend:DI (match_dup 0)))] 282 1.1 mrg "true_regnum (operands[0]) == true_regnum (operands[2]) 283 1.1 mrg || peep2_reg_dead_p (2, operands[0])" 284 1.1 mrg [(set (match_dup 2) 285 1.1 mrg (sign_extend:DI (match_dup 1)))]) 286 1.1 mrg 287 1.1 mrg (define_insn "addsi3" 288 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") 289 1.1 mrg (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ") 290 1.1 mrg (match_operand:SI 2 "add_operand" "rI,O,K,L")))] 291 1.1 mrg "" 292 1.1 mrg "@ 293 1.1 mrg addl %r1,%2,%0 294 1.1 mrg subl %r1,%n2,%0 295 1.1.1.2 mrg lda %0,%2(%r1) 296 1.1.1.2 mrg ldah %0,%h2(%r1)") 297 1.1.1.2 mrg 298 1.1 mrg (define_split 299 1.1 mrg [(set (match_operand:SI 0 "register_operand") 300 1.1 mrg (plus:SI (match_operand:SI 1 "register_operand") 301 1.1 mrg (match_operand:SI 2 "const_int_operand")))] 302 1.1 mrg "! add_operand (operands[2], SImode)" 303 1.1 mrg [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) 304 1.1 mrg (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] 305 1.1 mrg { 306 1.1 mrg HOST_WIDE_INT val = INTVAL (operands[2]); 307 1.1 mrg HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); 308 1.1 mrg HOST_WIDE_INT rest = val - low; 309 1.1 mrg 310 1.1 mrg operands[3] = GEN_INT (rest); 311 1.1 mrg operands[4] = GEN_INT (low); 312 1.1 mrg }) 313 1.1 mrg 314 1.1 mrg (define_insn "*addsi_se" 315 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r,r") 316 1.1 mrg (sign_extend:DI 317 1.1 mrg (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ") 318 1.1 mrg (match_operand:SI 2 "sext_add_operand" "rI,O"))))] 319 1.1 mrg "" 320 1.1 mrg "@ 321 1.1 mrg addl %r1,%2,%0 322 1.1 mrg subl %r1,%n2,%0") 323 1.1 mrg 324 1.1 mrg (define_insn "*addsi_se2" 325 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r,r") 326 1.1 mrg (sign_extend:DI 327 1.1 mrg (subreg:SI (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ") 328 1.1 mrg (match_operand:DI 2 "sext_add_operand" "rI,O")) 329 1.1 mrg 0)))] 330 1.1 mrg "" 331 1.1 mrg "@ 332 1.1.1.2 mrg addl %r1,%2,%0 333 1.1 mrg subl %r1,%n2,%0") 334 1.1.1.2 mrg 335 1.1.1.2 mrg (define_split 336 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand") 337 1.1 mrg (sign_extend:DI 338 1.1 mrg (plus:SI (match_operand:SI 1 "reg_not_elim_operand") 339 1.1 mrg (match_operand:SI 2 "const_int_operand")))) 340 1.1 mrg (clobber (match_operand:SI 3 "reg_not_elim_operand"))] 341 1.1 mrg "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0 342 1.1 mrg && INTVAL (operands[2]) % 4 == 0" 343 1.1 mrg [(set (match_dup 3) (match_dup 4)) 344 1.1 mrg (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3) 345 1.1 mrg (match_dup 5)) 346 1.1 mrg (match_dup 1))))] 347 1.1 mrg { 348 1.1 mrg HOST_WIDE_INT val = INTVAL (operands[2]) / 4; 349 1.1 mrg int mult = 4; 350 1.1 mrg 351 1.1 mrg if (val % 2 == 0) 352 1.1 mrg val /= 2, mult = 8; 353 1.1 mrg 354 1.1 mrg operands[4] = GEN_INT (val); 355 1.1.1.2 mrg operands[5] = GEN_INT (mult); 356 1.1 mrg }) 357 1.1 mrg 358 1.1.1.2 mrg (define_split 359 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand") 360 1.1.1.2 mrg (sign_extend:DI 361 1.1.1.2 mrg (plus:SI (match_operator:SI 1 "comparison_operator" 362 1.1 mrg [(match_operand 2) 363 1.1 mrg (match_operand 3)]) 364 1.1 mrg (match_operand:SI 4 "add_operand")))) 365 1.1 mrg (clobber (match_operand:DI 5 "register_operand"))] 366 1.1 mrg "" 367 1.1 mrg [(set (match_dup 5) (match_dup 6)) 368 1.1 mrg (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))] 369 1.1 mrg { 370 1.1 mrg operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode, 371 1.1 mrg operands[2], operands[3]); 372 1.1.1.2 mrg operands[7] = gen_lowpart (SImode, operands[5]); 373 1.1.1.2 mrg }) 374 1.1.1.2 mrg 375 1.1 mrg (define_expand "adddi3" 376 1.1 mrg [(set (match_operand:DI 0 "register_operand") 377 1.1 mrg (plus:DI (match_operand:DI 1 "register_operand") 378 1.1 mrg (match_operand:DI 2 "add_operand")))]) 379 1.1.1.2 mrg 380 1.1 mrg (define_insn "*adddi_er_lo16_dtp" 381 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 382 1.1 mrg (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 383 1.1 mrg (match_operand:DI 2 "dtp16_symbolic_operand")))] 384 1.1 mrg "HAVE_AS_TLS" 385 1.1 mrg "lda %0,%2(%1)\t\t!dtprel") 386 1.1.1.2 mrg 387 1.1 mrg (define_insn "*adddi_er_hi32_dtp" 388 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 389 1.1 mrg (plus:DI (match_operand:DI 1 "register_operand" "r") 390 1.1 mrg (high:DI (match_operand:DI 2 "dtp32_symbolic_operand"))))] 391 1.1 mrg "HAVE_AS_TLS" 392 1.1 mrg "ldah %0,%2(%1)\t\t!dtprelhi") 393 1.1.1.2 mrg 394 1.1 mrg (define_insn "*adddi_er_lo32_dtp" 395 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 396 1.1 mrg (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 397 1.1 mrg (match_operand:DI 2 "dtp32_symbolic_operand")))] 398 1.1 mrg "HAVE_AS_TLS" 399 1.1 mrg "lda %0,%2(%1)\t\t!dtprello") 400 1.1.1.2 mrg 401 1.1 mrg (define_insn "*adddi_er_lo16_tp" 402 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 403 1.1 mrg (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 404 1.1 mrg (match_operand:DI 2 "tp16_symbolic_operand")))] 405 1.1 mrg "HAVE_AS_TLS" 406 1.1 mrg "lda %0,%2(%1)\t\t!tprel") 407 1.1.1.2 mrg 408 1.1 mrg (define_insn "*adddi_er_hi32_tp" 409 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 410 1.1 mrg (plus:DI (match_operand:DI 1 "register_operand" "r") 411 1.1 mrg (high:DI (match_operand:DI 2 "tp32_symbolic_operand"))))] 412 1.1 mrg "HAVE_AS_TLS" 413 1.1 mrg "ldah %0,%2(%1)\t\t!tprelhi") 414 1.1.1.2 mrg 415 1.1 mrg (define_insn "*adddi_er_lo32_tp" 416 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 417 1.1 mrg (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 418 1.1 mrg (match_operand:DI 2 "tp32_symbolic_operand")))] 419 1.1 mrg "HAVE_AS_TLS" 420 1.1 mrg "lda %0,%2(%1)\t\t!tprello") 421 1.1.1.2 mrg 422 1.1 mrg (define_insn "*adddi_er_high_l" 423 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 424 1.1 mrg (plus:DI (match_operand:DI 1 "register_operand" "r") 425 1.1 mrg (high:DI (match_operand:DI 2 "local_symbolic_operand"))))] 426 1.1 mrg "TARGET_EXPLICIT_RELOCS && reload_completed" 427 1.1.1.2 mrg "ldah %0,%2(%1)\t\t!gprelhigh" 428 1.1.1.2 mrg [(set_attr "usegp" "yes")]) 429 1.1 mrg 430 1.1 mrg (define_split 431 1.1 mrg [(set (match_operand:DI 0 "register_operand") 432 1.1 mrg (high:DI (match_operand:DI 1 "local_symbolic_operand")))] 433 1.1 mrg "TARGET_EXPLICIT_RELOCS && reload_completed" 434 1.1 mrg [(set (match_dup 0) 435 1.1 mrg (plus:DI (match_dup 2) (high:DI (match_dup 1))))] 436 1.1 mrg "operands[2] = pic_offset_table_rtx;") 437 1.1 mrg 438 1.1 mrg ;; We used to expend quite a lot of effort choosing addq/subq/lda. 439 1.1 mrg ;; With complications like 440 1.1 mrg ;; 441 1.1 mrg ;; The NT stack unwind code can't handle a subq to adjust the stack 442 1.1 mrg ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3, 443 1.1 mrg ;; the exception handling code will loop if a subq is used and an 444 1.1 mrg ;; exception occurs. 445 1.1 mrg ;; 446 1.1 mrg ;; The 19980616 change to emit prologues as RTL also confused some 447 1.1 mrg ;; versions of GDB, which also interprets prologues. This has been 448 1.1 mrg ;; fixed as of GDB 4.18, but it does not harm to unconditionally 449 1.1 mrg ;; use lda here. 450 1.1 mrg ;; 451 1.1 mrg ;; and the fact that the three insns schedule exactly the same, it's 452 1.1 mrg ;; just not worth the effort. 453 1.1 mrg 454 1.1 mrg (define_insn "*adddi_internal" 455 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r,r,r") 456 1.1 mrg (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r") 457 1.1 mrg (match_operand:DI 2 "add_operand" "r,K,L")))] 458 1.1 mrg "" 459 1.1 mrg "@ 460 1.1 mrg addq %1,%2,%0 461 1.1 mrg lda %0,%2(%1) 462 1.1 mrg ldah %0,%h2(%1)") 463 1.1 mrg 464 1.1 mrg ;; ??? Allow large constants when basing off the frame pointer or some 465 1.1 mrg ;; virtual register that may eliminate to the frame pointer. This is 466 1.1 mrg ;; done because register elimination offsets will change the hi/lo split, 467 1.1 mrg ;; and if we split before reload, we will require additional instructions. 468 1.1 mrg 469 1.1 mrg (define_insn "*adddi_fp_hack" 470 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r,r,r") 471 1.1 mrg (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r,r,r") 472 1.1 mrg (match_operand:DI 2 "const_int_operand" "K,L,n")))] 473 1.1 mrg "NONSTRICT_REG_OK_FP_BASE_P (operands[1]) 474 1.1 mrg && INTVAL (operands[2]) >= 0 475 1.1 mrg /* This is the largest constant an lda+ldah pair can add, minus 476 1.1 mrg an upper bound on the displacement between SP and AP during 477 1.1 mrg register elimination. See INITIAL_ELIMINATION_OFFSET. */ 478 1.1 mrg && INTVAL (operands[2]) 479 1.1 mrg < (0x7fff8000 480 1.1 mrg - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD 481 1.1 mrg - ALPHA_ROUND(crtl->outgoing_args_size) 482 1.1 mrg - (ALPHA_ROUND (get_frame_size () 483 1.1 mrg + max_reg_num () * UNITS_PER_WORD 484 1.1 mrg + crtl->args.pretend_args_size) 485 1.1 mrg - crtl->args.pretend_args_size))" 486 1.1 mrg "@ 487 1.1 mrg lda %0,%2(%1) 488 1.1 mrg ldah %0,%h2(%1) 489 1.1 mrg #") 490 1.1.1.2 mrg 491 1.1.1.2 mrg ;; Don't do this if we are adjusting SP since we don't want to do it 492 1.1.1.2 mrg ;; in two steps. Don't split FP sources for the reason listed above. 493 1.1 mrg (define_split 494 1.1 mrg [(set (match_operand:DI 0 "register_operand") 495 1.1 mrg (plus:DI (match_operand:DI 1 "register_operand") 496 1.1 mrg (match_operand:DI 2 "const_int_operand")))] 497 1.1 mrg "! add_operand (operands[2], DImode) 498 1.1 mrg && operands[0] != stack_pointer_rtx 499 1.1 mrg && operands[1] != frame_pointer_rtx 500 1.1 mrg && operands[1] != arg_pointer_rtx" 501 1.1 mrg [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3))) 502 1.1 mrg (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] 503 1.1 mrg { 504 1.1 mrg HOST_WIDE_INT val = INTVAL (operands[2]); 505 1.1 mrg HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); 506 1.1 mrg HOST_WIDE_INT rest = val - low; 507 1.1 mrg rtx rest_rtx = GEN_INT (rest); 508 1.1 mrg 509 1.1 mrg operands[4] = GEN_INT (low); 510 1.1 mrg if (satisfies_constraint_L (rest_rtx)) 511 1.1 mrg operands[3] = rest_rtx; 512 1.1 mrg else if (can_create_pseudo_p ()) 513 1.1 mrg { 514 1.1 mrg operands[3] = gen_reg_rtx (DImode); 515 1.1 mrg emit_move_insn (operands[3], operands[2]); 516 1.1 mrg emit_insn (gen_adddi3 (operands[0], operands[1], operands[3])); 517 1.1 mrg DONE; 518 1.1 mrg } 519 1.1.1.2 mrg else 520 1.1.1.2 mrg FAIL; 521 1.1.1.2 mrg }) 522 1.1.1.2 mrg 523 1.1.1.2 mrg (define_insn "*sadd<modesuffix>" 524 1.1.1.2 mrg [(set (match_operand:I48MODE 0 "register_operand" "=r,r") 525 1.1 mrg (plus:I48MODE 526 1.1 mrg (mult:I48MODE (match_operand:I48MODE 1 "reg_not_elim_operand" "r,r") 527 1.1.1.2 mrg (match_operand:I48MODE 2 "const48_operand" "I,I")) 528 1.1.1.2 mrg (match_operand:I48MODE 3 "sext_add_operand" "rI,O")))] 529 1.1 mrg "" 530 1.1 mrg "@ 531 1.1 mrg s%2add<modesuffix> %1,%3,%0 532 1.1 mrg s%2sub<modesuffix> %1,%n3,%0") 533 1.1 mrg 534 1.1 mrg (define_insn "*saddl_se" 535 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r,r") 536 1.1 mrg (sign_extend:DI 537 1.1 mrg (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r") 538 1.1 mrg (match_operand:SI 2 "const48_operand" "I,I")) 539 1.1 mrg (match_operand:SI 3 "sext_add_operand" "rI,O"))))] 540 1.1 mrg "" 541 1.1 mrg "@ 542 1.1.1.2 mrg s%2addl %1,%3,%0 543 1.1 mrg s%2subl %1,%n3,%0") 544 1.1 mrg 545 1.1.1.2 mrg (define_split 546 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand") 547 1.1.1.2 mrg (sign_extend:DI 548 1.1.1.2 mrg (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator" 549 1.1.1.2 mrg [(match_operand 2) 550 1.1 mrg (match_operand 3)]) 551 1.1 mrg (match_operand:SI 4 "const48_operand")) 552 1.1 mrg (match_operand:SI 5 "sext_add_operand")))) 553 1.1 mrg (clobber (match_operand:DI 6 "reg_not_elim_operand"))] 554 1.1 mrg "" 555 1.1 mrg [(set (match_dup 6) (match_dup 7)) 556 1.1 mrg (set (match_dup 0) 557 1.1 mrg (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4)) 558 1.1 mrg (match_dup 5))))] 559 1.1 mrg { 560 1.1 mrg operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode, 561 1.1.1.2 mrg operands[2], operands[3]); 562 1.1.1.2 mrg operands[8] = gen_lowpart (SImode, operands[6]); 563 1.1.1.2 mrg }) 564 1.1.1.2 mrg 565 1.1.1.2 mrg (define_insn "addv<mode>3" 566 1.1.1.2 mrg [(set (match_operand:I48MODE 0 "register_operand" "=r,r") 567 1.1.1.2 mrg (plus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ,rJ") 568 1.1.1.2 mrg (match_operand:I48MODE 2 "sext_add_operand" "rI,O"))) 569 1.1 mrg (trap_if (ne (plus:<DWI> (sign_extend:<DWI> (match_dup 1)) 570 1.1 mrg (sign_extend:<DWI> (match_dup 2))) 571 1.1 mrg (sign_extend:<DWI> (plus:I48MODE (match_dup 1) 572 1.1.1.2 mrg (match_dup 2)))) 573 1.1.1.2 mrg (const_int 0))] 574 1.1 mrg "" 575 1.1.1.2 mrg "@ 576 1.1.1.2 mrg add<modesuffix>v %r1,%2,%0 577 1.1.1.2 mrg sub<modesuffix>v %r1,%n2,%0") 578 1.1 mrg 579 1.1.1.2 mrg (define_insn "neg<mode>2" 580 1.1 mrg [(set (match_operand:I48MODE 0 "register_operand" "=r") 581 1.1 mrg (neg:I48MODE (match_operand:I48MODE 1 "reg_or_8bit_operand" "rI")))] 582 1.1 mrg "" 583 1.1 mrg "sub<modesuffix> $31,%1,%0") 584 1.1 mrg 585 1.1 mrg (define_insn "*negsi_se" 586 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 587 1.1 mrg (sign_extend:DI (neg:SI 588 1.1.1.2 mrg (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))] 589 1.1.1.2 mrg "" 590 1.1.1.2 mrg "subl $31,%1,%0") 591 1.1.1.2 mrg 592 1.1.1.2 mrg (define_insn "negv<mode>2" 593 1.1 mrg [(set (match_operand:I48MODE 0 "register_operand" "=r") 594 1.1 mrg (neg:I48MODE (match_operand:I48MODE 1 "register_operand" "r"))) 595 1.1.1.2 mrg (trap_if (ne (neg:<DWI> (sign_extend:<DWI> (match_dup 1))) 596 1.1 mrg (sign_extend:<DWI> (neg:I48MODE (match_dup 1)))) 597 1.1.1.2 mrg (const_int 0))] 598 1.1.1.2 mrg "" 599 1.1.1.2 mrg "sub<modesuffix>v $31,%1,%0") 600 1.1.1.2 mrg 601 1.1 mrg (define_insn "sub<mode>3" 602 1.1.1.2 mrg [(set (match_operand:I48MODE 0 "register_operand" "=r") 603 1.1 mrg (minus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rJ") 604 1.1 mrg (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI")))] 605 1.1 mrg "" 606 1.1.1.2 mrg "sub<modesuffix> %r1,%2,%0") 607 1.1.1.2 mrg 608 1.1.1.2 mrg (define_insn "*subsi_se" 609 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 610 1.1 mrg (sign_extend:DI 611 1.1 mrg (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") 612 1.1 mrg (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))] 613 1.1 mrg "" 614 1.1 mrg "subl %r1,%2,%0") 615 1.1 mrg 616 1.1 mrg (define_insn "*subsi_se2" 617 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 618 1.1 mrg (sign_extend:DI 619 1.1 mrg (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 620 1.1 mrg (match_operand:DI 2 "reg_or_8bit_operand" "rI")) 621 1.1.1.2 mrg 0)))] 622 1.1.1.2 mrg "" 623 1.1.1.2 mrg "subl %r1,%2,%0") 624 1.1.1.2 mrg 625 1.1.1.2 mrg (define_insn "*ssub<modesuffix>" 626 1.1.1.2 mrg [(set (match_operand:I48MODE 0 "register_operand" "=r") 627 1.1 mrg (minus:I48MODE 628 1.1.1.2 mrg (mult:I48MODE (match_operand:I48MODE 1 "reg_not_elim_operand" "r") 629 1.1 mrg (match_operand:I48MODE 2 "const48_operand" "I")) 630 1.1 mrg (match_operand:I48MODE 3 "reg_or_8bit_operand" "rI")))] 631 1.1 mrg "" 632 1.1 mrg "s%2sub<modesuffix> %1,%3,%0") 633 1.1 mrg 634 1.1 mrg (define_insn "*ssubl_se" 635 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 636 1.1 mrg (sign_extend:DI 637 1.1 mrg (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r") 638 1.1 mrg (match_operand:SI 2 "const48_operand" "I")) 639 1.1.1.2 mrg (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))] 640 1.1.1.2 mrg "" 641 1.1.1.2 mrg "s%2subl %1,%3,%0") 642 1.1.1.2 mrg 643 1.1.1.2 mrg (define_insn "subv<mode>3" 644 1.1.1.2 mrg [(set (match_operand:I48MODE 0 "register_operand" "=r") 645 1.1.1.2 mrg (minus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rJ") 646 1.1.1.2 mrg (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI"))) 647 1.1 mrg (trap_if (ne (minus:<DWI> (sign_extend:<DWI> (match_dup 1)) 648 1.1 mrg (sign_extend:<DWI> (match_dup 2))) 649 1.1.1.2 mrg (sign_extend:<DWI> (minus:I48MODE (match_dup 1) 650 1.1 mrg (match_dup 2)))) 651 1.1.1.2 mrg (const_int 0))] 652 1.1.1.2 mrg "" 653 1.1.1.2 mrg "sub<modesuffix>v %r1,%2,%0") 654 1.1.1.2 mrg 655 1.1.1.2 mrg (define_insn "mul<mode>3" 656 1.1.1.2 mrg [(set (match_operand:I48MODE 0 "register_operand" "=r") 657 1.1 mrg (mult:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ") 658 1.1.1.2 mrg (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI")))] 659 1.1 mrg "" 660 1.1 mrg "mul<modesuffix> %r1,%2,%0" 661 1.1 mrg [(set_attr "type" "imul") 662 1.1 mrg (set_attr "opsize" "<mode>")]) 663 1.1 mrg 664 1.1 mrg (define_insn "*mulsi_se" 665 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand" "=r") 666 1.1 mrg (sign_extend:DI 667 1.1 mrg (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ") 668 1.1 mrg (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))] 669 1.1 mrg "" 670 1.1.1.2 mrg "mull %r1,%2,%0" 671 1.1.1.2 mrg [(set_attr "type" "imul") 672 1.1.1.2 mrg (set_attr "opsize" "si")]) 673 1.1.1.2 mrg 674 1.1.1.2 mrg (define_insn "mulv<mode>3" 675 1.1.1.2 mrg [(set (match_operand:I48MODE 0 "register_operand" "=r") 676 1.1.1.2 mrg (mult:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ") 677 1.1.1.2 mrg (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI"))) 678 1.1 mrg (trap_if (ne (mult:<DWI> (sign_extend:<DWI> (match_dup 1)) 679 1.1 mrg (sign_extend:<DWI> (match_dup 2))) 680 1.1.1.2 mrg (sign_extend:<DWI> (mult:I48MODE (match_dup 1) 681 1.1.1.2 mrg (match_dup 2)))) 682 1.1.1.2 mrg (const_int 0))] 683 1.1 mrg "" 684 1.1 mrg "mul<modesuffix>v %r1,%2,%0" 685 1.1.1.2 mrg [(set_attr "type" "imul") 686 1.1 mrg (set_attr "opsize" "<mode>")]) 687 1.1 mrg 688 1.1 mrg (define_expand "umuldi3_highpart" 689 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand") 690 1.1.1.2 mrg (truncate:DI 691 1.1 mrg (lshiftrt:TI 692 1.1 mrg (mult:TI (zero_extend:TI 693 1.1 mrg (match_operand:DI 1 "register_operand")) 694 1.1 mrg (match_operand:DI 2 "reg_or_8bit_operand")) 695 1.1 mrg (const_int 64))))] 696 1.1 mrg "" 697 1.1 mrg { 698 1.1 mrg if (REG_P (operands[2])) 699 1.1 mrg operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]); 700 1.1 mrg }) 701 1.1 mrg 702 1.1 mrg (define_insn "*umuldi3_highpart_reg" 703 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 704 1.1 mrg (truncate:DI 705 1.1 mrg (lshiftrt:TI 706 1.1 mrg (mult:TI (zero_extend:TI 707 1.1 mrg (match_operand:DI 1 "register_operand" "r")) 708 1.1 mrg (zero_extend:TI 709 1.1 mrg (match_operand:DI 2 "register_operand" "r"))) 710 1.1 mrg (const_int 64))))] 711 1.1 mrg "" 712 1.1 mrg "umulh %1,%2,%0" 713 1.1 mrg [(set_attr "type" "imul") 714 1.1 mrg (set_attr "opsize" "udi")]) 715 1.1 mrg 716 1.1 mrg (define_insn "*umuldi3_highpart_const" 717 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 718 1.1 mrg (truncate:DI 719 1.1 mrg (lshiftrt:TI 720 1.1 mrg (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r")) 721 1.1 mrg (match_operand:TI 2 "cint8_operand" "I")) 722 1.1 mrg (const_int 64))))] 723 1.1.1.2 mrg "" 724 1.1.1.2 mrg "umulh %1,%2,%0" 725 1.1.1.2 mrg [(set_attr "type" "imul") 726 1.1.1.2 mrg (set_attr "opsize" "udi")]) 727 1.1.1.2 mrg 728 1.1.1.2 mrg (define_expand "umulditi3" 729 1.1.1.2 mrg [(set (match_operand:TI 0 "register_operand") 730 1.1.1.2 mrg (mult:TI 731 1.1.1.2 mrg (zero_extend:TI (match_operand:DI 1 "reg_no_subreg_operand")) 732 1.1.1.2 mrg (zero_extend:TI (match_operand:DI 2 "reg_no_subreg_operand"))))] 733 1.1.1.2 mrg "" 734 1.1.1.2 mrg { 735 1.1.1.2 mrg rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode); 736 1.1.1.2 mrg emit_insn (gen_muldi3 (l, operands[1], operands[2])); 737 1.1.1.2 mrg emit_insn (gen_umuldi3_highpart (h, operands[1], operands[2])); 738 1.1 mrg emit_move_insn (gen_lowpart (DImode, operands[0]), l); 739 1.1 mrg emit_move_insn (gen_highpart (DImode, operands[0]), h); 740 1.1.1.2 mrg DONE; 741 1.1.1.2 mrg }) 742 1.1 mrg 744 1.1 mrg ;; The divide and remainder operations take their inputs from r24 and 745 1.1 mrg ;; r25, put their output in r27, and clobber r23 and r28 on all systems. 746 1.1 mrg ;; 747 1.1 mrg ;; ??? Force sign-extension here because some versions of OSF/1 and 748 1.1.1.2 mrg ;; Interix/NT don't do the right thing if the inputs are not properly 749 1.1 mrg ;; sign-extended. But Linux, for instance, does not have this 750 1.1.1.2 mrg ;; problem. Is it worth the complication here to eliminate the sign 751 1.1 mrg ;; extension? 752 1.1.1.2 mrg 753 1.1 mrg (define_code_iterator any_divmod [div mod udiv umod]) 754 1.1.1.2 mrg 755 1.1 mrg (define_expand "<code>si3" 756 1.1.1.2 mrg [(set (match_dup 3) 757 1.1.1.2 mrg (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"))) 758 1.1 mrg (set (match_dup 4) 759 1.1 mrg (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand"))) 760 1.1.1.2 mrg (parallel [(set (match_dup 5) 761 1.1 mrg (sign_extend:DI 762 1.1.1.2 mrg (any_divmod:SI (match_dup 3) (match_dup 4)))) 763 1.1 mrg (clobber (reg:DI 23)) 764 1.1 mrg (clobber (reg:DI 28))]) 765 1.1 mrg (set (match_operand:SI 0 "nonimmediate_operand") 766 1.1 mrg (subreg:SI (match_dup 5) 0))] 767 1.1 mrg "TARGET_ABI_OSF" 768 1.1 mrg { 769 1.1.1.2 mrg operands[3] = gen_reg_rtx (DImode); 770 1.1.1.2 mrg operands[4] = gen_reg_rtx (DImode); 771 1.1.1.2 mrg operands[5] = gen_reg_rtx (DImode); 772 1.1.1.2 mrg }) 773 1.1.1.2 mrg 774 1.1 mrg (define_expand "<code>di3" 775 1.1 mrg [(parallel [(set (match_operand:DI 0 "register_operand") 776 1.1.1.2 mrg (any_divmod:DI 777 1.1 mrg (match_operand:DI 1 "register_operand") 778 1.1 mrg (match_operand:DI 2 "register_operand"))) 779 1.1 mrg (clobber (reg:DI 23)) 780 1.1 mrg (clobber (reg:DI 28))])] 781 1.1 mrg "TARGET_ABI_OSF") 782 1.1 mrg 783 1.1 mrg ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as 784 1.1 mrg ;; expanded by the assembler. 785 1.1 mrg 786 1.1 mrg (define_insn_and_split "*divmodsi_internal_er" 787 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=c") 788 1.1.1.2 mrg (sign_extend:DI (match_operator:SI 3 "divmod_operator" 789 1.1 mrg [(match_operand:DI 1 "register_operand" "a") 790 1.1 mrg (match_operand:DI 2 "register_operand" "b")]))) 791 1.1 mrg (clobber (reg:DI 23)) 792 1.1 mrg (clobber (reg:DI 28))] 793 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 794 1.1 mrg "#" 795 1.1 mrg "&& reload_completed" 796 1.1 mrg [(parallel [(set (match_dup 0) 797 1.1 mrg (sign_extend:DI (match_dup 3))) 798 1.1 mrg (use (match_dup 0)) 799 1.1 mrg (use (match_dup 4)) 800 1.1 mrg (clobber (reg:DI 23)) 801 1.1 mrg (clobber (reg:DI 28))])] 802 1.1 mrg { 803 1.1 mrg const char *str; 804 1.1 mrg switch (GET_CODE (operands[3])) 805 1.1 mrg { 806 1.1 mrg case DIV: 807 1.1 mrg str = "__divl"; 808 1.1 mrg break; 809 1.1 mrg case UDIV: 810 1.1 mrg str = "__divlu"; 811 1.1 mrg break; 812 1.1 mrg case MOD: 813 1.1 mrg str = "__reml"; 814 1.1 mrg break; 815 1.1 mrg case UMOD: 816 1.1 mrg str = "__remlu"; 817 1.1 mrg break; 818 1.1 mrg default: 819 1.1 mrg gcc_unreachable (); 820 1.1 mrg } 821 1.1 mrg operands[4] = GEN_INT (alpha_next_sequence_number++); 822 1.1 mrg emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx, 823 1.1 mrg gen_rtx_SYMBOL_REF (DImode, str), 824 1.1 mrg operands[4])); 825 1.1 mrg } 826 1.1 mrg [(set_attr "type" "jsr") 827 1.1 mrg (set_attr "length" "8")]) 828 1.1 mrg 829 1.1 mrg (define_insn "*divmodsi_internal_er_1" 830 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand" "=c") 831 1.1 mrg (sign_extend:DI (match_operator:SI 3 "divmod_operator" 832 1.1 mrg [(match_operand:DI 1 "register_operand" "a") 833 1.1.1.2 mrg (match_operand:DI 2 "register_operand" "b")]))) 834 1.1 mrg (use (match_operand:DI 4 "register_operand" "c")) 835 1.1 mrg (use (match_operand 5 "const_int_operand")) 836 1.1 mrg (clobber (reg:DI 23)) 837 1.1 mrg (clobber (reg:DI 28))] 838 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 839 1.1 mrg "jsr $23,($27),__%E3%j5" 840 1.1 mrg [(set_attr "type" "jsr") 841 1.1 mrg (set_attr "length" "4")]) 842 1.1 mrg 843 1.1 mrg (define_insn "*divmodsi_internal" 844 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=c") 845 1.1.1.2 mrg (sign_extend:DI (match_operator:SI 3 "divmod_operator" 846 1.1 mrg [(match_operand:DI 1 "register_operand" "a") 847 1.1 mrg (match_operand:DI 2 "register_operand" "b")]))) 848 1.1 mrg (clobber (reg:DI 23)) 849 1.1 mrg (clobber (reg:DI 28))] 850 1.1 mrg "TARGET_ABI_OSF" 851 1.1 mrg "%E3 %1,%2,%0" 852 1.1 mrg [(set_attr "type" "jsr") 853 1.1 mrg (set_attr "length" "8")]) 854 1.1 mrg 855 1.1 mrg (define_insn_and_split "*divmoddi_internal_er" 856 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=c") 857 1.1.1.2 mrg (match_operator:DI 3 "divmod_operator" 858 1.1 mrg [(match_operand:DI 1 "register_operand" "a") 859 1.1 mrg (match_operand:DI 2 "register_operand" "b")])) 860 1.1 mrg (clobber (reg:DI 23)) 861 1.1 mrg (clobber (reg:DI 28))] 862 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 863 1.1 mrg "#" 864 1.1 mrg "&& reload_completed" 865 1.1 mrg [(parallel [(set (match_dup 0) (match_dup 3)) 866 1.1 mrg (use (match_dup 0)) 867 1.1 mrg (use (match_dup 4)) 868 1.1 mrg (clobber (reg:DI 23)) 869 1.1 mrg (clobber (reg:DI 28))])] 870 1.1 mrg { 871 1.1 mrg const char *str; 872 1.1 mrg switch (GET_CODE (operands[3])) 873 1.1 mrg { 874 1.1 mrg case DIV: 875 1.1 mrg str = "__divq"; 876 1.1 mrg break; 877 1.1 mrg case UDIV: 878 1.1 mrg str = "__divqu"; 879 1.1 mrg break; 880 1.1 mrg case MOD: 881 1.1 mrg str = "__remq"; 882 1.1 mrg break; 883 1.1 mrg case UMOD: 884 1.1 mrg str = "__remqu"; 885 1.1 mrg break; 886 1.1 mrg default: 887 1.1 mrg gcc_unreachable (); 888 1.1 mrg } 889 1.1 mrg operands[4] = GEN_INT (alpha_next_sequence_number++); 890 1.1 mrg emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx, 891 1.1 mrg gen_rtx_SYMBOL_REF (DImode, str), 892 1.1 mrg operands[4])); 893 1.1 mrg } 894 1.1 mrg [(set_attr "type" "jsr") 895 1.1 mrg (set_attr "length" "8")]) 896 1.1 mrg 897 1.1 mrg (define_insn "*divmoddi_internal_er_1" 898 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand" "=c") 899 1.1 mrg (match_operator:DI 3 "divmod_operator" 900 1.1 mrg [(match_operand:DI 1 "register_operand" "a") 901 1.1.1.2 mrg (match_operand:DI 2 "register_operand" "b")])) 902 1.1 mrg (use (match_operand:DI 4 "register_operand" "c")) 903 1.1 mrg (use (match_operand 5 "const_int_operand")) 904 1.1 mrg (clobber (reg:DI 23)) 905 1.1 mrg (clobber (reg:DI 28))] 906 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 907 1.1 mrg "jsr $23,($27),__%E3%j5" 908 1.1 mrg [(set_attr "type" "jsr") 909 1.1 mrg (set_attr "length" "4")]) 910 1.1 mrg 911 1.1 mrg (define_insn "*divmoddi_internal" 912 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=c") 913 1.1.1.2 mrg (match_operator:DI 3 "divmod_operator" 914 1.1 mrg [(match_operand:DI 1 "register_operand" "a") 915 1.1 mrg (match_operand:DI 2 "register_operand" "b")])) 916 1.1 mrg (clobber (reg:DI 23)) 917 1.1 mrg (clobber (reg:DI 28))] 918 1.1 mrg "TARGET_ABI_OSF" 919 1.1 mrg "%E3 %1,%2,%0" 920 1.1 mrg [(set_attr "type" "jsr") 921 1.1 mrg (set_attr "length" "8")]) 922 1.1 mrg 924 1.1 mrg ;; Next are the basic logical operations. We only expose the DImode operations 925 1.1.1.4 mrg ;; to the rtl expanders, but SImode versions exist for combine as well as for 926 1.1 mrg ;; the atomic operation splitters. 927 1.1 mrg 928 1.1 mrg (define_insn "*andsi_internal" 929 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=r,r,r") 930 1.1 mrg (and:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ") 931 1.1 mrg (match_operand:SI 2 "and_operand" "rI,N,M")))] 932 1.1 mrg "" 933 1.1 mrg "@ 934 1.1 mrg and %r1,%2,%0 935 1.1 mrg bic %r1,%N2,%0 936 1.1.1.4 mrg zapnot %r1,%m2,%0" 937 1.1 mrg [(set_attr "type" "ilog,ilog,shift")]) 938 1.1 mrg 939 1.1 mrg (define_insn "anddi3" 940 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r,r,r") 941 1.1 mrg (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ") 942 1.1 mrg (match_operand:DI 2 "and_operand" "rI,N,M")))] 943 1.1 mrg "" 944 1.1 mrg "@ 945 1.1 mrg and %r1,%2,%0 946 1.1 mrg bic %r1,%N2,%0 947 1.1 mrg zapnot %r1,%m2,%0" 948 1.1 mrg [(set_attr "type" "ilog,ilog,shift")]) 949 1.1 mrg 950 1.1 mrg ;; There are times when we can split an AND into two AND insns. This occurs 951 1.1.1.2 mrg ;; when we can first clear any bytes and then clear anything else. For 952 1.1.1.2 mrg ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07". 953 1.1.1.2 mrg ;; Only do this when running on 64-bit host since the computations are 954 1.1.1.4 mrg ;; too messy otherwise. 955 1.1 mrg 956 1.1 mrg (define_split 957 1.1 mrg [(set (match_operand:DI 0 "register_operand") 958 1.1 mrg (and:DI (match_operand:DI 1 "register_operand") 959 1.1 mrg (match_operand:DI 2 "const_int_operand")))] 960 1.1 mrg "! and_operand (operands[2], DImode)" 961 1.1 mrg [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3))) 962 1.1 mrg (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))] 963 1.1 mrg { 964 1.1 mrg unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]); 965 1.1 mrg unsigned HOST_WIDE_INT mask2 = mask1; 966 1.1 mrg int i; 967 1.1 mrg 968 1.1 mrg /* For each byte that isn't all zeros, make it all ones. */ 969 1.1 mrg for (i = 0; i < 64; i += 8) 970 1.1 mrg if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0) 971 1.1 mrg mask1 |= (HOST_WIDE_INT) 0xff << i; 972 1.1 mrg 973 1.1 mrg /* Now turn on any bits we've just turned off. */ 974 1.1.1.2 mrg mask2 |= ~ mask1; 975 1.1.1.2 mrg 976 1.1.1.2 mrg operands[3] = GEN_INT (mask1); 977 1.1.1.2 mrg operands[4] = GEN_INT (mask2); 978 1.1 mrg }) 979 1.1 mrg 980 1.1 mrg (define_insn "zero_extendqi<mode>2" 981 1.1 mrg [(set (match_operand:I248MODE 0 "register_operand" "=r,r") 982 1.1.1.2 mrg (zero_extend:I248MODE 983 1.1.1.2 mrg (match_operand:QI 1 "reg_or_bwx_memory_operand" "r,m")))] 984 1.1 mrg "" 985 1.1.1.2 mrg "@ 986 1.1.1.2 mrg and %1,0xff,%0 987 1.1.1.2 mrg ldbu %0,%1" 988 1.1.1.2 mrg [(set_attr "type" "ilog,ild") 989 1.1 mrg (set_attr "isa" "*,bwx")]) 990 1.1 mrg 991 1.1 mrg (define_insn "zero_extendhi<mode>2" 992 1.1 mrg [(set (match_operand:I48MODE 0 "register_operand" "=r,r") 993 1.1.1.2 mrg (zero_extend:I48MODE 994 1.1.1.2 mrg (match_operand:HI 1 "reg_or_bwx_memory_operand" "r,m")))] 995 1.1 mrg "" 996 1.1 mrg "@ 997 1.1 mrg zapnot %1,3,%0 998 1.1 mrg ldwu %0,%1" 999 1.1 mrg [(set_attr "type" "shift,ild") 1000 1.1 mrg (set_attr "isa" "*,bwx")]) 1001 1.1 mrg 1002 1.1 mrg (define_insn "zero_extendsidi2" 1003 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1004 1.1.1.2 mrg (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))] 1005 1.1.1.2 mrg "" 1006 1.1.1.2 mrg "zapnot %1,15,%0" 1007 1.1.1.2 mrg [(set_attr "type" "shift")]) 1008 1.1 mrg 1009 1.1 mrg (define_insn "andnot<mode>3" 1010 1.1 mrg [(set (match_operand:I48MODE 0 "register_operand" "=r") 1011 1.1 mrg (and:I48MODE 1012 1.1 mrg (not:I48MODE (match_operand:I48MODE 1 "reg_or_8bit_operand" "rI")) 1013 1.1 mrg (match_operand:I48MODE 2 "reg_or_0_operand" "rJ")))] 1014 1.1 mrg "" 1015 1.1 mrg "bic %r2,%1,%0" 1016 1.1 mrg [(set_attr "type" "ilog")]) 1017 1.1 mrg 1018 1.1 mrg (define_insn "*iorsi_internal" 1019 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=r,r") 1020 1.1 mrg (ior:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ") 1021 1.1 mrg (match_operand:SI 2 "or_operand" "rI,N")))] 1022 1.1 mrg "" 1023 1.1 mrg "@ 1024 1.1 mrg bis %r1,%2,%0 1025 1.1 mrg ornot %r1,%N2,%0" 1026 1.1 mrg [(set_attr "type" "ilog")]) 1027 1.1 mrg 1028 1.1 mrg (define_insn "iordi3" 1029 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r,r") 1030 1.1 mrg (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ") 1031 1.1 mrg (match_operand:DI 2 "or_operand" "rI,N")))] 1032 1.1 mrg "" 1033 1.1 mrg "@ 1034 1.1 mrg bis %r1,%2,%0 1035 1.1 mrg ornot %r1,%N2,%0" 1036 1.1 mrg [(set_attr "type" "ilog")]) 1037 1.1 mrg 1038 1.1 mrg (define_insn "*one_cmplsi_internal" 1039 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=r") 1040 1.1 mrg (not:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))] 1041 1.1 mrg "" 1042 1.1 mrg "ornot $31,%1,%0" 1043 1.1 mrg [(set_attr "type" "ilog")]) 1044 1.1 mrg 1045 1.1 mrg (define_insn "one_cmpldi2" 1046 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1047 1.1.1.2 mrg (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))] 1048 1.1.1.2 mrg "" 1049 1.1.1.2 mrg "ornot $31,%1,%0" 1050 1.1.1.2 mrg [(set_attr "type" "ilog")]) 1051 1.1 mrg 1052 1.1 mrg (define_insn "*iornot<mode>3" 1053 1.1 mrg [(set (match_operand:I48MODE 0 "register_operand" "=r") 1054 1.1 mrg (ior:I48MODE 1055 1.1 mrg (not:I48MODE (match_operand:I48MODE 1 "reg_or_8bit_operand" "rI")) 1056 1.1 mrg (match_operand:I48MODE 2 "reg_or_0_operand" "rJ")))] 1057 1.1 mrg "" 1058 1.1 mrg "ornot %r2,%1,%0" 1059 1.1 mrg [(set_attr "type" "ilog")]) 1060 1.1 mrg 1061 1.1 mrg (define_insn "*xorsi_internal" 1062 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=r,r") 1063 1.1 mrg (xor:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ") 1064 1.1 mrg (match_operand:SI 2 "or_operand" "rI,N")))] 1065 1.1 mrg "" 1066 1.1 mrg "@ 1067 1.1 mrg xor %r1,%2,%0 1068 1.1 mrg eqv %r1,%N2,%0" 1069 1.1 mrg [(set_attr "type" "ilog")]) 1070 1.1 mrg 1071 1.1 mrg (define_insn "xordi3" 1072 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r,r") 1073 1.1 mrg (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ") 1074 1.1 mrg (match_operand:DI 2 "or_operand" "rI,N")))] 1075 1.1.1.2 mrg "" 1076 1.1.1.2 mrg "@ 1077 1.1.1.2 mrg xor %r1,%2,%0 1078 1.1.1.2 mrg eqv %r1,%N2,%0" 1079 1.1.1.2 mrg [(set_attr "type" "ilog")]) 1080 1.1 mrg 1081 1.1 mrg (define_insn "*xornot<mode>3" 1082 1.1 mrg [(set (match_operand:I48MODE 0 "register_operand" "=r") 1083 1.1 mrg (not:I48MODE (xor:I48MODE 1084 1.1 mrg (match_operand:I48MODE 1 "register_operand" "%rJ") 1085 1.1 mrg (match_operand:I48MODE 2 "register_operand" "rI"))))] 1086 1.1 mrg "" 1087 1.1 mrg "eqv %r1,%2,%0" 1088 1.1.1.2 mrg [(set_attr "type" "ilog")]) 1089 1.1 mrg 1091 1.1.1.2 mrg ;; Handle FFS and related insns iff we support CIX. 1092 1.1 mrg 1093 1.1 mrg (define_expand "ffsdi2" 1094 1.1 mrg [(set (match_dup 2) 1095 1.1 mrg (ctz:DI (match_operand:DI 1 "register_operand"))) 1096 1.1 mrg (set (match_dup 3) 1097 1.1 mrg (plus:DI (match_dup 2) (const_int 1))) 1098 1.1 mrg (set (match_operand:DI 0 "register_operand") 1099 1.1 mrg (if_then_else:DI (eq (match_dup 1) (const_int 0)) 1100 1.1 mrg (const_int 0) (match_dup 3)))] 1101 1.1 mrg "TARGET_CIX" 1102 1.1 mrg { 1103 1.1 mrg operands[2] = gen_reg_rtx (DImode); 1104 1.1 mrg operands[3] = gen_reg_rtx (DImode); 1105 1.1 mrg }) 1106 1.1 mrg 1107 1.1 mrg (define_insn "clzdi2" 1108 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1109 1.1 mrg (clz:DI (match_operand:DI 1 "register_operand" "r")))] 1110 1.1 mrg "TARGET_CIX" 1111 1.1 mrg "ctlz %1,%0" 1112 1.1 mrg [(set_attr "type" "mvi")]) 1113 1.1 mrg 1114 1.1 mrg (define_insn "ctzdi2" 1115 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1116 1.1 mrg (ctz:DI (match_operand:DI 1 "register_operand" "r")))] 1117 1.1 mrg "TARGET_CIX" 1118 1.1 mrg "cttz %1,%0" 1119 1.1 mrg [(set_attr "type" "mvi")]) 1120 1.1 mrg 1121 1.1 mrg (define_insn "popcountdi2" 1122 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1123 1.1.1.2 mrg (popcount:DI (match_operand:DI 1 "register_operand" "r")))] 1124 1.1 mrg "TARGET_CIX" 1125 1.1 mrg "ctpop %1,%0" 1126 1.1 mrg [(set_attr "type" "mvi")]) 1127 1.1 mrg 1128 1.1 mrg (define_expand "bswapsi2" 1129 1.1 mrg [(set (match_operand:SI 0 "register_operand") 1130 1.1 mrg (bswap:SI (match_operand:SI 1 "register_operand")))] 1131 1.1.1.2 mrg "!optimize_size" 1132 1.1 mrg { 1133 1.1 mrg rtx t0, t1; 1134 1.1 mrg 1135 1.1 mrg t0 = gen_reg_rtx (DImode); 1136 1.1 mrg t1 = gen_reg_rtx (DImode); 1137 1.1 mrg 1138 1.1 mrg emit_insn (gen_inslh (t0, gen_lowpart (DImode, operands[1]), GEN_INT (7))); 1139 1.1 mrg emit_insn (gen_inswl_const (t1, gen_lowpart (HImode, operands[1]), 1140 1.1 mrg GEN_INT (24))); 1141 1.1 mrg emit_insn (gen_iordi3 (t1, t0, t1)); 1142 1.1 mrg emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (16))); 1143 1.1 mrg emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x5))); 1144 1.1.1.2 mrg emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xa))); 1145 1.1.1.2 mrg emit_insn (gen_addsi3 (operands[0], gen_lowpart (SImode, t0), 1146 1.1 mrg gen_lowpart (SImode, t1))); 1147 1.1 mrg DONE; 1148 1.1 mrg }) 1149 1.1 mrg 1150 1.1 mrg (define_expand "bswapdi2" 1151 1.1 mrg [(set (match_operand:DI 0 "register_operand") 1152 1.1 mrg (bswap:DI (match_operand:DI 1 "register_operand")))] 1153 1.1 mrg "!optimize_size" 1154 1.1 mrg { 1155 1.1 mrg rtx t0, t1; 1156 1.1 mrg 1157 1.1 mrg t0 = gen_reg_rtx (DImode); 1158 1.1 mrg t1 = gen_reg_rtx (DImode); 1159 1.1 mrg 1160 1.1 mrg /* This method of shifting and masking is not specific to Alpha, but 1161 1.1 mrg is only profitable on Alpha because of our handy byte zap insn. */ 1162 1.1 mrg 1163 1.1 mrg emit_insn (gen_lshrdi3 (t0, operands[1], GEN_INT (32))); 1164 1.1 mrg emit_insn (gen_ashldi3 (t1, operands[1], GEN_INT (32))); 1165 1.1 mrg emit_insn (gen_iordi3 (t1, t0, t1)); 1166 1.1 mrg 1167 1.1 mrg emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (16))); 1168 1.1 mrg emit_insn (gen_ashldi3 (t1, t1, GEN_INT (16))); 1169 1.1 mrg emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xcc))); 1170 1.1 mrg emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x33))); 1171 1.1 mrg emit_insn (gen_iordi3 (t1, t0, t1)); 1172 1.1 mrg 1173 1.1 mrg emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (8))); 1174 1.1 mrg emit_insn (gen_ashldi3 (t1, t1, GEN_INT (8))); 1175 1.1 mrg emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xaa))); 1176 1.1 mrg emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x55))); 1177 1.1 mrg emit_insn (gen_iordi3 (operands[0], t0, t1)); 1178 1.1 mrg DONE; 1179 1.1 mrg }) 1180 1.1 mrg 1182 1.1 mrg ;; Next come the shifts and the various extract and insert operations. 1183 1.1 mrg 1184 1.1 mrg (define_insn "ashldi3" 1185 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r,r") 1186 1.1 mrg (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ") 1187 1.1 mrg (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))] 1188 1.1 mrg "" 1189 1.1 mrg { 1190 1.1 mrg switch (which_alternative) 1191 1.1 mrg { 1192 1.1 mrg case 0: 1193 1.1 mrg if (operands[2] == const1_rtx) 1194 1.1 mrg return "addq %r1,%r1,%0"; 1195 1.1 mrg else 1196 1.1 mrg return "s%P2addq %r1,0,%0"; 1197 1.1 mrg case 1: 1198 1.1 mrg return "sll %r1,%2,%0"; 1199 1.1 mrg default: 1200 1.1 mrg gcc_unreachable (); 1201 1.1 mrg } 1202 1.1 mrg } 1203 1.1 mrg [(set_attr "type" "iadd,shift")]) 1204 1.1 mrg 1205 1.1 mrg (define_insn "*ashldi_se" 1206 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1207 1.1 mrg (sign_extend:DI 1208 1.1 mrg (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1209 1.1 mrg (match_operand:DI 2 "const_int_operand" "P")) 1210 1.1 mrg 0)))] 1211 1.1 mrg "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3" 1212 1.1 mrg { 1213 1.1 mrg if (operands[2] == const1_rtx) 1214 1.1 mrg return "addl %r1,%r1,%0"; 1215 1.1 mrg else 1216 1.1 mrg return "s%P2addl %r1,0,%0"; 1217 1.1 mrg } 1218 1.1 mrg [(set_attr "type" "iadd")]) 1219 1.1 mrg 1220 1.1 mrg (define_insn "lshrdi3" 1221 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1222 1.1 mrg (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1223 1.1 mrg (match_operand:DI 2 "reg_or_6bit_operand" "rS")))] 1224 1.1 mrg "" 1225 1.1 mrg "srl %r1,%2,%0" 1226 1.1 mrg [(set_attr "type" "shift")]) 1227 1.1 mrg 1228 1.1.1.2 mrg (define_insn "ashrdi3" 1229 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1230 1.1.1.2 mrg (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1231 1.1.1.2 mrg (match_operand:DI 2 "reg_or_6bit_operand" "rS")))] 1232 1.1.1.2 mrg "" 1233 1.1.1.2 mrg "sra %r1,%2,%0" 1234 1.1.1.2 mrg [(set_attr "type" "shift")]) 1235 1.1.1.2 mrg 1236 1.1.1.2 mrg (define_insn "extendqi<mode>2" 1237 1.1.1.2 mrg [(set (match_operand:I24MODE 0 "register_operand" "=r") 1238 1.1.1.4 mrg (sign_extend:I24MODE 1239 1.1 mrg (match_operand:QI 1 "register_operand" "r")))] 1240 1.1 mrg "TARGET_BWX" 1241 1.1 mrg "sextb %1,%0" 1242 1.1.1.2 mrg [(set_attr "type" "shift")]) 1243 1.1.1.2 mrg 1244 1.1 mrg (define_expand "extendqidi2" 1245 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand") 1246 1.1 mrg (sign_extend:DI (match_operand:QI 1 "general_operand")))] 1247 1.1.1.2 mrg "" 1248 1.1.1.2 mrg { 1249 1.1.1.2 mrg if (TARGET_BWX) 1250 1.1.1.2 mrg operands[1] = force_reg (QImode, operands[1]); 1251 1.1.1.2 mrg else 1252 1.1.1.2 mrg { 1253 1.1.1.2 mrg rtx x, t1, t2, i56; 1254 1.1 mrg 1255 1.1.1.2 mrg if (unaligned_memory_operand (operands[1], QImode)) 1256 1.1.1.2 mrg { 1257 1.1.1.2 mrg x = gen_unaligned_extendqidi (operands[0], XEXP (operands[1], 0)); 1258 1.1.1.2 mrg alpha_set_memflags (x, operands[1]); 1259 1.1.1.2 mrg emit_insn (x); 1260 1.1.1.2 mrg DONE; 1261 1.1.1.2 mrg } 1262 1.1.1.2 mrg 1263 1.1 mrg t1 = gen_reg_rtx (DImode); 1264 1.1 mrg t2 = gen_reg_rtx (DImode); 1265 1.1 mrg i56 = GEN_INT (56); 1266 1.1 mrg 1267 1.1.1.2 mrg x = gen_lowpart (DImode, force_reg (QImode, operands[1])); 1268 1.1 mrg emit_move_insn (t1, x); 1269 1.1 mrg emit_insn (gen_ashldi3 (t2, t1, i56)); 1270 1.1 mrg emit_insn (gen_ashrdi3 (operands[0], t2, i56)); 1271 1.1 mrg DONE; 1272 1.1 mrg } 1273 1.1 mrg }) 1274 1.1.1.2 mrg 1275 1.1 mrg (define_insn "*extendqidi2_bwx" 1276 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1277 1.1 mrg (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))] 1278 1.1 mrg "TARGET_BWX" 1279 1.1 mrg "sextb %1,%0" 1280 1.1 mrg [(set_attr "type" "shift")]) 1281 1.1.1.2 mrg 1282 1.1.1.2 mrg (define_insn "extendhisi2" 1283 1.1.1.4 mrg [(set (match_operand:SI 0 "register_operand" "=r") 1284 1.1 mrg (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))] 1285 1.1 mrg "TARGET_BWX" 1286 1.1 mrg "sextw %1,%0" 1287 1.1.1.2 mrg [(set_attr "type" "shift")]) 1288 1.1.1.2 mrg 1289 1.1 mrg (define_expand "extendhidi2" 1290 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand") 1291 1.1.1.2 mrg (sign_extend:DI (match_operand:HI 1 "general_operand")))] 1292 1.1.1.2 mrg "" 1293 1.1.1.2 mrg { 1294 1.1.1.2 mrg if (TARGET_BWX) 1295 1.1.1.2 mrg operands[1] = force_reg (HImode, operands[1]); 1296 1.1.1.2 mrg else 1297 1.1.1.2 mrg { 1298 1.1.1.2 mrg rtx x, t1, t2, i48; 1299 1.1.1.2 mrg 1300 1.1.1.2 mrg if (unaligned_memory_operand (operands[1], HImode)) 1301 1.1.1.2 mrg { 1302 1.1.1.2 mrg x = gen_unaligned_extendhidi (operands[0], XEXP (operands[1], 0)); 1303 1.1.1.2 mrg alpha_set_memflags (x, operands[1]); 1304 1.1.1.2 mrg emit_insn (x); 1305 1.1.1.2 mrg DONE; 1306 1.1.1.2 mrg } 1307 1.1.1.2 mrg 1308 1.1 mrg t1 = gen_reg_rtx (DImode); 1309 1.1 mrg t2 = gen_reg_rtx (DImode); 1310 1.1 mrg i48 = GEN_INT (48); 1311 1.1 mrg 1312 1.1.1.2 mrg x = gen_lowpart (DImode, force_reg (HImode, operands[1])); 1313 1.1.1.2 mrg emit_move_insn (t1, x); 1314 1.1.1.2 mrg emit_insn (gen_ashldi3 (t2, t1, i48)); 1315 1.1.1.2 mrg emit_insn (gen_ashrdi3 (operands[0], t2, i48)); 1316 1.1.1.2 mrg DONE; 1317 1.1.1.2 mrg } 1318 1.1 mrg }) 1319 1.1 mrg 1320 1.1 mrg (define_insn "*extendhidi2_bwx" 1321 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1322 1.1 mrg (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))] 1323 1.1 mrg "TARGET_BWX" 1324 1.1 mrg "sextw %1,%0" 1325 1.1.1.2 mrg [(set_attr "type" "shift")]) 1326 1.1 mrg 1327 1.1.1.2 mrg ;; Here's how we sign extend an unaligned byte and halfword. Doing this 1328 1.1 mrg ;; as a pattern saves one instruction. The code is similar to that for 1329 1.1 mrg ;; the unaligned loads (see below). 1330 1.1 mrg ;; 1331 1.1 mrg ;; Operand 1 is the address, operand 0 is the result. 1332 1.1 mrg 1333 1.1 mrg (define_expand "unaligned_extendqidi" 1334 1.1.1.2 mrg [(set (match_dup 3) 1335 1.1 mrg (mem:DI (and:DI (match_operand:DI 1 "address_operand") (const_int -8)))) 1336 1.1.1.2 mrg (set (match_dup 4) 1337 1.1 mrg (ashift:DI (match_dup 3) 1338 1.1.1.2 mrg (minus:DI (const_int 64) 1339 1.1 mrg (ashift:DI 1340 1.1 mrg (and:DI (match_dup 2) (const_int 7)) 1341 1.1 mrg (const_int 3))))) 1342 1.1 mrg (set (match_operand:QI 0 "register_operand") 1343 1.1 mrg (ashiftrt:DI (match_dup 4) (const_int 56)))] 1344 1.1 mrg "" 1345 1.1 mrg { 1346 1.1.1.2 mrg operands[0] = gen_lowpart (DImode, operands[0]); 1347 1.1 mrg operands[2] = get_unaligned_offset (operands[1], 1); 1348 1.1 mrg operands[3] = gen_reg_rtx (DImode); 1349 1.1 mrg operands[4] = gen_reg_rtx (DImode); 1350 1.1 mrg }) 1351 1.1 mrg 1352 1.1 mrg (define_expand "unaligned_extendhidi" 1353 1.1.1.2 mrg [(set (match_dup 3) 1354 1.1 mrg (mem:DI (and:DI (match_operand:DI 1 "address_operand") (const_int -8)))) 1355 1.1.1.2 mrg (set (match_dup 4) 1356 1.1 mrg (ashift:DI (match_dup 3) 1357 1.1.1.2 mrg (minus:DI (const_int 64) 1358 1.1 mrg (ashift:DI 1359 1.1 mrg (and:DI (match_dup 2) (const_int 7)) 1360 1.1 mrg (const_int 3))))) 1361 1.1 mrg (set (match_operand:HI 0 "register_operand") 1362 1.1 mrg (ashiftrt:DI (match_dup 4) (const_int 48)))] 1363 1.1 mrg "" 1364 1.1 mrg { 1365 1.1 mrg operands[0] = gen_lowpart (DImode, operands[0]); 1366 1.1 mrg operands[2] = get_unaligned_offset (operands[1], 2); 1367 1.1 mrg operands[3] = gen_reg_rtx (DImode); 1368 1.1 mrg operands[4] = gen_reg_rtx (DImode); 1369 1.1 mrg }) 1370 1.1 mrg 1371 1.1 mrg (define_insn "*extxl_const" 1372 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1373 1.1 mrg (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1374 1.1.1.2 mrg (match_operand:DI 2 "mode_width_operand" "n") 1375 1.1.1.2 mrg (match_operand:DI 3 "mul8_operand" "I")))] 1376 1.1.1.2 mrg "" 1377 1.1.1.2 mrg "ext%M2l %r1,%s3,%0" 1378 1.1.1.2 mrg [(set_attr "type" "shift")]) 1379 1.1.1.2 mrg 1380 1.1 mrg (define_insn "extxl" 1381 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1382 1.1 mrg (zero_extract:DI 1383 1.1 mrg (match_operand:DI 1 "reg_or_0_operand" "rJ") 1384 1.1 mrg (match_operand:DI 2 "mode_width_operand" "n") 1385 1.1 mrg (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI") 1386 1.1 mrg (const_int 3))))] 1387 1.1.1.2 mrg "" 1388 1.1 mrg "ext%M2l %r1,%3,%0" 1389 1.1 mrg [(set_attr "type" "shift")]) 1390 1.1 mrg 1391 1.1 mrg ;; Combine has some strange notion of preserving existing undefined behavior 1392 1.1 mrg ;; in shifts larger than a word size. So capture these patterns that it 1393 1.1.1.2 mrg ;; should have turned into zero_extracts. 1394 1.1 mrg 1395 1.1 mrg (define_insn "*extxl_1" 1396 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1397 1.1.1.2 mrg (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1398 1.1 mrg (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1399 1.1 mrg (const_int 3))) 1400 1.1 mrg (match_operand:DI 3 "mode_mask_operand" "n")))] 1401 1.1 mrg "" 1402 1.1.1.2 mrg "ext%U3l %1,%2,%0" 1403 1.1 mrg [(set_attr "type" "shift")]) 1404 1.1 mrg 1405 1.1 mrg (define_insn "*extql_2" 1406 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1407 1.1 mrg (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1408 1.1 mrg (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1409 1.1 mrg (const_int 3))))] 1410 1.1 mrg "" 1411 1.1 mrg "extql %1,%2,%0" 1412 1.1 mrg [(set_attr "type" "shift")]) 1413 1.1 mrg 1414 1.1 mrg (define_insn "extqh" 1415 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1416 1.1.1.2 mrg (ashift:DI 1417 1.1 mrg (match_operand:DI 1 "reg_or_0_operand" "rJ") 1418 1.1 mrg (minus:DI (const_int 64) 1419 1.1 mrg (ashift:DI 1420 1.1.1.2 mrg (and:DI 1421 1.1 mrg (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1422 1.1 mrg (const_int 7)) 1423 1.1 mrg (const_int 3)))))] 1424 1.1.1.2 mrg "" 1425 1.1 mrg "extqh %r1,%2,%0" 1426 1.1 mrg [(set_attr "type" "shift")]) 1427 1.1 mrg 1428 1.1 mrg (define_insn "extwh" 1429 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1430 1.1 mrg (ashift:DI 1431 1.1.1.2 mrg (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1432 1.1.1.2 mrg (const_int 65535)) 1433 1.1 mrg (minus:DI (const_int 64) 1434 1.1 mrg (ashift:DI 1435 1.1.1.2 mrg (and:DI 1436 1.1 mrg (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1437 1.1 mrg (const_int 7)) 1438 1.1 mrg (const_int 3)))))] 1439 1.1.1.2 mrg "" 1440 1.1 mrg "extwh %r1,%2,%0" 1441 1.1 mrg [(set_attr "type" "shift")]) 1442 1.1 mrg 1443 1.1 mrg (define_insn "extlh" 1444 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1445 1.1 mrg (ashift:DI 1446 1.1.1.2 mrg (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1447 1.1.1.2 mrg (const_int 2147483647)) 1448 1.1 mrg (minus:DI (const_int 64) 1449 1.1 mrg (ashift:DI 1450 1.1 mrg (and:DI 1451 1.1 mrg (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1452 1.1 mrg (const_int 7)) 1453 1.1 mrg (const_int 3)))))] 1454 1.1.1.2 mrg "" 1455 1.1.1.2 mrg "extlh %r1,%2,%0" 1456 1.1.1.2 mrg [(set_attr "type" "shift")]) 1457 1.1.1.2 mrg 1458 1.1 mrg ;; This converts an extXl into an extXh with an appropriate adjustment 1459 1.1.1.2 mrg ;; to the address calculation. 1460 1.1.1.2 mrg 1461 1.1 mrg ;;(define_split 1462 1.1 mrg ;; [(set (match_operand:DI 0 "register_operand") 1463 1.1 mrg ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand") 1464 1.1 mrg ;; (match_operand:DI 2 "mode_width_operand") 1465 1.1 mrg ;; (ashift:DI (match_operand:DI 3) 1466 1.1 mrg ;; (const_int 3))) 1467 1.1 mrg ;; (match_operand:DI 4 "const_int_operand"))) 1468 1.1 mrg ;; (clobber (match_operand:DI 5 "register_operand"))] 1469 1.1 mrg ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])" 1470 1.1 mrg ;; [(set (match_dup 5) (match_dup 6)) 1471 1.1.1.2 mrg ;; (set (match_dup 0) 1472 1.1 mrg ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2) 1473 1.1 mrg ;; (ashift:DI (plus:DI (match_dup 5) 1474 1.1 mrg ;; (match_dup 7)) 1475 1.1 mrg ;; (const_int 3))) 1476 1.1.1.2 mrg ;; (match_dup 4)))] 1477 1.1 mrg ;; " 1478 1.1.1.2 mrg ;;{ 1479 1.1.1.2 mrg ;; operands[6] = plus_constant (DImode, operands[3], 1480 1.1 mrg ;; INTVAL (operands[2]) / BITS_PER_UNIT); 1481 1.1 mrg ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT); 1482 1.1.1.2 mrg ;;}") 1483 1.1 mrg 1484 1.1 mrg (define_insn "ins<modesuffix>l_const" 1485 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1486 1.1 mrg (ashift:DI (zero_extend:DI 1487 1.1.1.2 mrg (match_operand:I124MODE 1 "register_operand" "r")) 1488 1.1.1.2 mrg (match_operand:DI 2 "mul8_operand" "I")))] 1489 1.1 mrg "" 1490 1.1 mrg "ins<modesuffix>l %1,%s2,%0" 1491 1.1.1.2 mrg [(set_attr "type" "shift")]) 1492 1.1.1.2 mrg 1493 1.1 mrg (define_insn "ins<modesuffix>l" 1494 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1495 1.1.1.2 mrg (ashift:DI (zero_extend:DI 1496 1.1 mrg (match_operand:I124MODE 1 "register_operand" "r")) 1497 1.1 mrg (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1498 1.1 mrg (const_int 3))))] 1499 1.1 mrg "" 1500 1.1.1.2 mrg "ins<modesuffix>l %1,%2,%0" 1501 1.1 mrg [(set_attr "type" "shift")]) 1502 1.1 mrg 1503 1.1 mrg (define_insn "insql" 1504 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1505 1.1 mrg (ashift:DI (match_operand:DI 1 "register_operand" "r") 1506 1.1 mrg (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1507 1.1 mrg (const_int 3))))] 1508 1.1 mrg "" 1509 1.1 mrg "insql %1,%2,%0" 1510 1.1 mrg [(set_attr "type" "shift")]) 1511 1.1.1.4 mrg 1512 1.1.1.4 mrg ;; Combine has this sometimes habit of moving the and outside of the 1513 1.1.1.4 mrg ;; shift, making life more interesting. 1514 1.1.1.4 mrg 1515 1.1 mrg (define_insn "*insxl" 1516 1.1.1.4 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1517 1.1.1.4 mrg (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") 1518 1.1 mrg (match_operand:DI 2 "mul8_operand" "I")) 1519 1.1 mrg (match_operand:DI 3 "const_int_operand" "i")))] 1520 1.1 mrg "((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2]) 1521 1.1 mrg == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1522 1.1 mrg || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2]) 1523 1.1 mrg == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1524 1.1 mrg || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2]) 1525 1.1 mrg == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))" 1526 1.1 mrg { 1527 1.1 mrg if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2]) 1528 1.1.1.4 mrg == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1529 1.1 mrg return "insbl %1,%s2,%0"; 1530 1.1 mrg if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2]) 1531 1.1 mrg == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1532 1.1 mrg return "inswl %1,%s2,%0"; 1533 1.1 mrg if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2]) 1534 1.1 mrg == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1535 1.1 mrg return "insll %1,%s2,%0"; 1536 1.1 mrg 1537 1.1 mrg gcc_unreachable (); 1538 1.1 mrg } 1539 1.1 mrg [(set_attr "type" "shift")]) 1540 1.1 mrg 1541 1.1 mrg ;; We do not include the insXh insns because they are complex to express 1542 1.1 mrg ;; and it does not appear that we would ever want to generate them. 1543 1.1 mrg ;; 1544 1.1 mrg ;; Since we need them for block moves, though, cop out and use unspec. 1545 1.1 mrg 1546 1.1 mrg (define_insn "insxh" 1547 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1548 1.1.1.2 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "r") 1549 1.1 mrg (match_operand:DI 2 "mode_width_operand" "n") 1550 1.1 mrg (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 1551 1.1 mrg UNSPEC_INSXH))] 1552 1.1 mrg "" 1553 1.1 mrg "ins%M2h %1,%3,%0" 1554 1.1 mrg [(set_attr "type" "shift")]) 1555 1.1 mrg 1556 1.1.1.2 mrg (define_insn "mskxl" 1557 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1558 1.1 mrg (and:DI (not:DI (ashift:DI 1559 1.1 mrg (match_operand:DI 2 "mode_mask_operand" "n") 1560 1.1 mrg (ashift:DI 1561 1.1 mrg (match_operand:DI 3 "reg_or_8bit_operand" "rI") 1562 1.1 mrg (const_int 3)))) 1563 1.1 mrg (match_operand:DI 1 "reg_or_0_operand" "rJ")))] 1564 1.1 mrg "" 1565 1.1 mrg "msk%U2l %r1,%3,%0" 1566 1.1 mrg [(set_attr "type" "shift")]) 1567 1.1 mrg 1568 1.1 mrg ;; We do not include the mskXh insns because it does not appear we would 1569 1.1 mrg ;; ever generate one. 1570 1.1 mrg ;; 1571 1.1 mrg ;; Again, we do for block moves and we use unspec again. 1572 1.1 mrg 1573 1.1 mrg (define_insn "mskxh" 1574 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1575 1.1 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "r") 1576 1.1 mrg (match_operand:DI 2 "mode_width_operand" "n") 1577 1.1 mrg (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 1578 1.1 mrg UNSPEC_MSKXH))] 1579 1.1 mrg "" 1580 1.1 mrg "msk%M2h %1,%3,%0" 1581 1.1 mrg [(set_attr "type" "shift")]) 1582 1.1 mrg 1583 1.1 mrg ;; Prefer AND + NE over LSHIFTRT + AND. 1584 1.1 mrg 1585 1.1 mrg (define_insn_and_split "*ze_and_ne" 1586 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1587 1.1 mrg (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1588 1.1 mrg (const_int 1) 1589 1.1 mrg (match_operand 2 "const_int_operand" "I")))] 1590 1.1 mrg "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8" 1591 1.1 mrg "#" 1592 1.1 mrg "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8" 1593 1.1 mrg [(set (match_dup 0) 1594 1.1 mrg (and:DI (match_dup 1) (match_dup 3))) 1595 1.1.1.2 mrg (set (match_dup 0) 1596 1.1 mrg (ne:DI (match_dup 0) (const_int 0)))] 1597 1.1.1.2 mrg "operands[3] = GEN_INT (1 << INTVAL (operands[2]));") 1598 1.1 mrg 1600 1.1.1.2 mrg ;; Floating-point operations. All the double-precision insns can extend 1601 1.1.1.2 mrg ;; from single, so indicate that. The exception are the ones that simply 1602 1.1 mrg ;; play with the sign bits; it's not clear what to do there. 1603 1.1 mrg 1604 1.1 mrg (define_mode_iterator FMODE [SF DF]) 1605 1.1 mrg 1606 1.1.1.2 mrg (define_mode_attr opmode [(SF "si") (DF "di")]) 1607 1.1.1.2 mrg 1608 1.1.1.2 mrg (define_insn "abs<mode>2" 1609 1.1.1.2 mrg [(set (match_operand:FMODE 0 "register_operand" "=f") 1610 1.1 mrg (abs:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))] 1611 1.1 mrg "TARGET_FP" 1612 1.1 mrg "cpys $f31,%R1,%0" 1613 1.1 mrg [(set_attr "type" "fcpys")]) 1614 1.1 mrg 1615 1.1.1.2 mrg (define_insn "*nabs<mode>2" 1616 1.1.1.2 mrg [(set (match_operand:FMODE 0 "register_operand" "=f") 1617 1.1 mrg (neg:FMODE 1618 1.1 mrg (abs:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG"))))] 1619 1.1.1.4 mrg "TARGET_FP" 1620 1.1 mrg "cpysn $f31,%R1,%0" 1621 1.1 mrg [(set_attr "type" "fadd")]) 1622 1.1 mrg 1623 1.1 mrg (define_expand "abstf2" 1624 1.1 mrg [(parallel [(set (match_operand:TF 0 "register_operand") 1625 1.1 mrg (abs:TF (match_operand:TF 1 "reg_or_0_operand"))) 1626 1.1 mrg (use (match_dup 2))])] 1627 1.1 mrg "TARGET_HAS_XFLOATING_LIBS" 1628 1.1 mrg "operands[2] = force_reg (DImode, GEN_INT (HOST_WIDE_INT_1U << 63));") 1629 1.1 mrg 1630 1.1 mrg (define_insn_and_split "*abstf_internal" 1631 1.1.1.2 mrg [(set (match_operand:TF 0 "register_operand" "=r") 1632 1.1.1.2 mrg (abs:TF (match_operand:TF 1 "reg_or_0_operand" "rG"))) 1633 1.1.1.2 mrg (use (match_operand:DI 2 "register_operand" "r"))] 1634 1.1 mrg "TARGET_HAS_XFLOATING_LIBS" 1635 1.1 mrg "#" 1636 1.1 mrg "&& reload_completed" 1637 1.1 mrg [(const_int 0)] 1638 1.1 mrg "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;") 1639 1.1.1.2 mrg 1640 1.1.1.2 mrg (define_insn "neg<mode>2" 1641 1.1 mrg [(set (match_operand:FMODE 0 "register_operand" "=f") 1642 1.1 mrg (neg:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))] 1643 1.1.1.4 mrg "TARGET_FP" 1644 1.1 mrg "cpysn %R1,%R1,%0" 1645 1.1 mrg [(set_attr "type" "fadd")]) 1646 1.1 mrg 1647 1.1 mrg (define_expand "negtf2" 1648 1.1 mrg [(parallel [(set (match_operand:TF 0 "register_operand") 1649 1.1 mrg (neg:TF (match_operand:TF 1 "reg_or_0_operand"))) 1650 1.1 mrg (use (match_dup 2))])] 1651 1.1 mrg "TARGET_HAS_XFLOATING_LIBS" 1652 1.1 mrg "operands[2] = force_reg (DImode, GEN_INT (HOST_WIDE_INT_1U << 63));") 1653 1.1 mrg 1654 1.1 mrg (define_insn_and_split "*negtf_internal" 1655 1.1.1.2 mrg [(set (match_operand:TF 0 "register_operand" "=r") 1656 1.1.1.2 mrg (neg:TF (match_operand:TF 1 "reg_or_0_operand" "rG"))) 1657 1.1.1.2 mrg (use (match_operand:DI 2 "register_operand" "r"))] 1658 1.1.1.2 mrg "TARGET_HAS_XFLOATING_LIBS" 1659 1.1.1.2 mrg "#" 1660 1.1 mrg "&& reload_completed" 1661 1.1 mrg [(const_int 0)] 1662 1.1 mrg "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;") 1663 1.1 mrg 1664 1.1.1.2 mrg (define_insn "copysign<mode>3" 1665 1.1.1.2 mrg [(set (match_operand:FMODE 0 "register_operand" "=f") 1666 1.1.1.2 mrg (unspec:FMODE [(match_operand:FMODE 1 "reg_or_0_operand" "fG") 1667 1.1.1.2 mrg (match_operand:FMODE 2 "reg_or_0_operand" "fG")] 1668 1.1.1.2 mrg UNSPEC_COPYSIGN))] 1669 1.1.1.2 mrg "TARGET_FP" 1670 1.1 mrg "cpys %R2,%R1,%0" 1671 1.1 mrg [(set_attr "type" "fadd")]) 1672 1.1 mrg 1673 1.1 mrg (define_insn "*ncopysign<mode>3" 1674 1.1.1.2 mrg [(set (match_operand:FMODE 0 "register_operand" "=f") 1675 1.1.1.2 mrg (neg:FMODE 1676 1.1.1.2 mrg (unspec:FMODE [(match_operand:FMODE 1 "reg_or_0_operand" "fG") 1677 1.1.1.2 mrg (match_operand:FMODE 2 "reg_or_0_operand" "fG")] 1678 1.1 mrg UNSPEC_COPYSIGN)))] 1679 1.1.1.2 mrg "TARGET_FP" 1680 1.1 mrg "cpysn %R2,%R1,%0" 1681 1.1 mrg [(set_attr "type" "fadd")]) 1682 1.1 mrg 1683 1.1 mrg (define_insn "*add<mode>3_ieee" 1684 1.1 mrg [(set (match_operand:FMODE 0 "register_operand" "=&f") 1685 1.1.1.2 mrg (plus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG") 1686 1.1.1.2 mrg (match_operand:FMODE 2 "reg_or_0_operand" "fG")))] 1687 1.1.1.2 mrg "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 1688 1.1.1.2 mrg "add<modesuffix>%/ %R1,%R2,%0" 1689 1.1 mrg [(set_attr "type" "fadd") 1690 1.1.1.2 mrg (set_attr "trap" "yes") 1691 1.1 mrg (set_attr "round_suffix" "normal") 1692 1.1 mrg (set_attr "trap_suffix" "u_su_sui")]) 1693 1.1 mrg 1694 1.1 mrg (define_insn "add<mode>3" 1695 1.1 mrg [(set (match_operand:FMODE 0 "register_operand" "=f") 1696 1.1 mrg (plus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG") 1697 1.1 mrg (match_operand:FMODE 2 "reg_or_0_operand" "fG")))] 1698 1.1 mrg "TARGET_FP" 1699 1.1 mrg "add<modesuffix>%/ %R1,%R2,%0" 1700 1.1 mrg [(set_attr "type" "fadd") 1701 1.1 mrg (set_attr "trap" "yes") 1702 1.1 mrg (set_attr "round_suffix" "normal") 1703 1.1 mrg (set_attr "trap_suffix" "u_su_sui")]) 1704 1.1 mrg 1705 1.1 mrg (define_insn "*adddf_ext1" 1706 1.1 mrg [(set (match_operand:DF 0 "register_operand" "=f") 1707 1.1 mrg (plus:DF (float_extend:DF 1708 1.1 mrg (match_operand:SF 1 "reg_or_0_operand" "fG")) 1709 1.1 mrg (match_operand:DF 2 "reg_or_0_operand" "fG")))] 1710 1.1 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1711 1.1 mrg "add%-%/ %R1,%R2,%0" 1712 1.1 mrg [(set_attr "type" "fadd") 1713 1.1 mrg (set_attr "trap" "yes") 1714 1.1 mrg (set_attr "round_suffix" "normal") 1715 1.1 mrg (set_attr "trap_suffix" "u_su_sui")]) 1716 1.1 mrg 1717 1.1 mrg (define_insn "*adddf_ext2" 1718 1.1 mrg [(set (match_operand:DF 0 "register_operand" "=f") 1719 1.1 mrg (plus:DF (float_extend:DF 1720 1.1 mrg (match_operand:SF 1 "reg_or_0_operand" "%fG")) 1721 1.1 mrg (float_extend:DF 1722 1.1.1.2 mrg (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1723 1.1.1.2 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1724 1.1.1.2 mrg "add%-%/ %R1,%R2,%0" 1725 1.1 mrg [(set_attr "type" "fadd") 1726 1.1 mrg (set_attr "trap" "yes") 1727 1.1 mrg (set_attr "round_suffix" "normal") 1728 1.1.1.2 mrg (set_attr "trap_suffix" "u_su_sui")]) 1729 1.1.1.2 mrg 1730 1.1.1.2 mrg (define_expand "addtf3" 1731 1.1.1.2 mrg [(use (match_operand:TF 0 "register_operand")) 1732 1.1.1.2 mrg (use (match_operand:TF 1 "general_operand")) 1733 1.1.1.2 mrg (use (match_operand:TF 2 "general_operand"))] 1734 1.1.1.2 mrg "TARGET_HAS_XFLOATING_LIBS" 1735 1.1.1.2 mrg "alpha_emit_xfloating_arith (PLUS, operands); DONE;") 1736 1.1.1.2 mrg 1737 1.1.1.2 mrg (define_insn "*sub<mode>3_ieee" 1738 1.1.1.2 mrg [(set (match_operand:FMODE 0 "register_operand" "=&f") 1739 1.1.1.2 mrg (minus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG") 1740 1.1.1.2 mrg (match_operand:FMODE 2 "reg_or_0_operand" "fG")))] 1741 1.1.1.2 mrg "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 1742 1.1.1.2 mrg "sub<modesuffix>%/ %R1,%R2,%0" 1743 1.1.1.2 mrg [(set_attr "type" "fadd") 1744 1.1.1.2 mrg (set_attr "trap" "yes") 1745 1.1.1.2 mrg (set_attr "round_suffix" "normal") 1746 1.1.1.2 mrg (set_attr "trap_suffix" "u_su_sui")]) 1747 1.1.1.2 mrg 1748 1.1.1.2 mrg (define_insn "sub<mode>3" 1749 1.1.1.2 mrg [(set (match_operand:FMODE 0 "register_operand" "=f") 1750 1.1.1.2 mrg (minus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG") 1751 1.1.1.2 mrg (match_operand:FMODE 2 "reg_or_0_operand" "fG")))] 1752 1.1.1.2 mrg "TARGET_FP" 1753 1.1.1.2 mrg "sub<modesuffix>%/ %R1,%R2,%0" 1754 1.1.1.2 mrg [(set_attr "type" "fadd") 1755 1.1.1.2 mrg (set_attr "trap" "yes") 1756 1.1.1.2 mrg (set_attr "round_suffix" "normal") 1757 1.1.1.2 mrg (set_attr "trap_suffix" "u_su_sui")]) 1758 1.1.1.2 mrg 1759 1.1.1.2 mrg (define_insn "*subdf_ext1" 1760 1.1.1.2 mrg [(set (match_operand:DF 0 "register_operand" "=f") 1761 1.1.1.2 mrg (minus:DF (float_extend:DF 1762 1.1.1.2 mrg (match_operand:SF 1 "reg_or_0_operand" "fG")) 1763 1.1.1.2 mrg (match_operand:DF 2 "reg_or_0_operand" "fG")))] 1764 1.1.1.2 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1765 1.1.1.2 mrg "sub%-%/ %R1,%R2,%0" 1766 1.1.1.2 mrg [(set_attr "type" "fadd") 1767 1.1.1.2 mrg (set_attr "trap" "yes") 1768 1.1.1.2 mrg (set_attr "round_suffix" "normal") 1769 1.1.1.2 mrg (set_attr "trap_suffix" "u_su_sui")]) 1770 1.1.1.2 mrg 1771 1.1.1.2 mrg (define_insn "*subdf_ext2" 1772 1.1.1.2 mrg [(set (match_operand:DF 0 "register_operand" "=f") 1773 1.1.1.2 mrg (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG") 1774 1.1.1.2 mrg (float_extend:DF 1775 1.1.1.2 mrg (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1776 1.1.1.2 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1777 1.1.1.2 mrg "sub%-%/ %R1,%R2,%0" 1778 1.1.1.2 mrg [(set_attr "type" "fadd") 1779 1.1.1.2 mrg (set_attr "trap" "yes") 1780 1.1.1.2 mrg (set_attr "round_suffix" "normal") 1781 1.1.1.2 mrg (set_attr "trap_suffix" "u_su_sui")]) 1782 1.1.1.2 mrg 1783 1.1.1.2 mrg (define_insn "*subdf_ext3" 1784 1.1.1.2 mrg [(set (match_operand:DF 0 "register_operand" "=f") 1785 1.1.1.2 mrg (minus:DF (float_extend:DF 1786 1.1.1.2 mrg (match_operand:SF 1 "reg_or_0_operand" "fG")) 1787 1.1.1.2 mrg (float_extend:DF 1788 1.1.1.2 mrg (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1789 1.1.1.2 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1790 1.1.1.2 mrg "sub%-%/ %R1,%R2,%0" 1791 1.1.1.2 mrg [(set_attr "type" "fadd") 1792 1.1.1.2 mrg (set_attr "trap" "yes") 1793 1.1.1.2 mrg (set_attr "round_suffix" "normal") 1794 1.1.1.2 mrg (set_attr "trap_suffix" "u_su_sui")]) 1795 1.1.1.2 mrg 1796 1.1.1.2 mrg (define_expand "subtf3" 1797 1.1.1.2 mrg [(use (match_operand:TF 0 "register_operand")) 1798 1.1.1.2 mrg (use (match_operand:TF 1 "general_operand")) 1799 1.1.1.2 mrg (use (match_operand:TF 2 "general_operand"))] 1800 1.1.1.2 mrg "TARGET_HAS_XFLOATING_LIBS" 1801 1.1.1.2 mrg "alpha_emit_xfloating_arith (MINUS, operands); DONE;") 1802 1.1.1.2 mrg 1803 1.1.1.2 mrg (define_insn "*mul<mode>3_ieee" 1804 1.1.1.2 mrg [(set (match_operand:FMODE 0 "register_operand" "=&f") 1805 1.1.1.2 mrg (mult:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG") 1806 1.1.1.2 mrg (match_operand:FMODE 2 "reg_or_0_operand" "fG")))] 1807 1.1.1.2 mrg "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 1808 1.1.1.2 mrg "mul<modesuffix>%/ %R1,%R2,%0" 1809 1.1.1.2 mrg [(set_attr "type" "fmul") 1810 1.1.1.2 mrg (set_attr "trap" "yes") 1811 1.1.1.2 mrg (set_attr "round_suffix" "normal") 1812 1.1.1.2 mrg (set_attr "trap_suffix" "u_su_sui")]) 1813 1.1.1.2 mrg 1814 1.1.1.2 mrg (define_insn "mul<mode>3" 1815 1.1.1.2 mrg [(set (match_operand:FMODE 0 "register_operand" "=f") 1816 1.1.1.2 mrg (mult:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG") 1817 1.1.1.2 mrg (match_operand:FMODE 2 "reg_or_0_operand" "fG")))] 1818 1.1.1.2 mrg "TARGET_FP" 1819 1.1.1.2 mrg "mul<modesuffix>%/ %R1,%R2,%0" 1820 1.1.1.2 mrg [(set_attr "type" "fmul") 1821 1.1.1.2 mrg (set_attr "trap" "yes") 1822 1.1.1.2 mrg (set_attr "round_suffix" "normal") 1823 1.1.1.2 mrg (set_attr "trap_suffix" "u_su_sui")]) 1824 1.1.1.2 mrg 1825 1.1.1.2 mrg (define_insn "*muldf_ext1" 1826 1.1.1.2 mrg [(set (match_operand:DF 0 "register_operand" "=f") 1827 1.1.1.2 mrg (mult:DF (float_extend:DF 1828 1.1.1.2 mrg (match_operand:SF 1 "reg_or_0_operand" "fG")) 1829 1.1.1.2 mrg (match_operand:DF 2 "reg_or_0_operand" "fG")))] 1830 1.1.1.2 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1831 1.1.1.2 mrg "mul%-%/ %R1,%R2,%0" 1832 1.1.1.2 mrg [(set_attr "type" "fmul") 1833 1.1.1.2 mrg (set_attr "trap" "yes") 1834 1.1.1.2 mrg (set_attr "round_suffix" "normal") 1835 1.1.1.2 mrg (set_attr "trap_suffix" "u_su_sui")]) 1836 1.1.1.2 mrg 1837 1.1.1.2 mrg (define_insn "*muldf_ext2" 1838 1.1.1.2 mrg [(set (match_operand:DF 0 "register_operand" "=f") 1839 1.1.1.2 mrg (mult:DF (float_extend:DF 1840 1.1.1.2 mrg (match_operand:SF 1 "reg_or_0_operand" "%fG")) 1841 1.1.1.2 mrg (float_extend:DF 1842 1.1.1.2 mrg (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1843 1.1.1.2 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1844 1.1.1.2 mrg "mul%-%/ %R1,%R2,%0" 1845 1.1.1.2 mrg [(set_attr "type" "fmul") 1846 1.1.1.2 mrg (set_attr "trap" "yes") 1847 1.1.1.2 mrg (set_attr "round_suffix" "normal") 1848 1.1.1.2 mrg (set_attr "trap_suffix" "u_su_sui")]) 1849 1.1.1.2 mrg 1850 1.1.1.2 mrg (define_expand "multf3" 1851 1.1.1.2 mrg [(use (match_operand:TF 0 "register_operand")) 1852 1.1.1.2 mrg (use (match_operand:TF 1 "general_operand")) 1853 1.1.1.2 mrg (use (match_operand:TF 2 "general_operand"))] 1854 1.1.1.2 mrg "TARGET_HAS_XFLOATING_LIBS" 1855 1.1.1.2 mrg "alpha_emit_xfloating_arith (MULT, operands); DONE;") 1856 1.1.1.2 mrg 1857 1.1.1.2 mrg (define_insn "*div<mode>3_ieee" 1858 1.1.1.2 mrg [(set (match_operand:FMODE 0 "register_operand" "=&f") 1859 1.1.1.2 mrg (div:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG") 1860 1.1.1.2 mrg (match_operand:FMODE 2 "reg_or_0_operand" "fG")))] 1861 1.1.1.2 mrg "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 1862 1.1.1.2 mrg "div<modesuffix>%/ %R1,%R2,%0" 1863 1.1.1.2 mrg [(set_attr "type" "fdiv") 1864 1.1.1.2 mrg (set_attr "opsize" "<opmode>") 1865 1.1.1.2 mrg (set_attr "trap" "yes") 1866 1.1.1.2 mrg (set_attr "round_suffix" "normal") 1867 1.1.1.2 mrg (set_attr "trap_suffix" "u_su_sui")]) 1868 1.1.1.2 mrg 1869 1.1.1.2 mrg (define_insn "div<mode>3" 1870 1.1.1.2 mrg [(set (match_operand:FMODE 0 "register_operand" "=f") 1871 1.1.1.2 mrg (div:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG") 1872 1.1.1.2 mrg (match_operand:FMODE 2 "reg_or_0_operand" "fG")))] 1873 1.1.1.2 mrg "TARGET_FP" 1874 1.1.1.2 mrg "div<modesuffix>%/ %R1,%R2,%0" 1875 1.1.1.2 mrg [(set_attr "type" "fdiv") 1876 1.1.1.2 mrg (set_attr "opsize" "<opmode>") 1877 1.1.1.2 mrg (set_attr "trap" "yes") 1878 1.1.1.2 mrg (set_attr "round_suffix" "normal") 1879 1.1.1.2 mrg (set_attr "trap_suffix" "u_su_sui")]) 1880 1.1.1.2 mrg 1881 1.1.1.2 mrg (define_insn "*divdf_ext1" 1882 1.1.1.2 mrg [(set (match_operand:DF 0 "register_operand" "=f") 1883 1.1.1.2 mrg (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG")) 1884 1.1.1.2 mrg (match_operand:DF 2 "reg_or_0_operand" "fG")))] 1885 1.1.1.2 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1886 1.1.1.2 mrg "div%-%/ %R1,%R2,%0" 1887 1.1.1.2 mrg [(set_attr "type" "fdiv") 1888 1.1.1.2 mrg (set_attr "trap" "yes") 1889 1.1.1.2 mrg (set_attr "round_suffix" "normal") 1890 1.1.1.2 mrg (set_attr "trap_suffix" "u_su_sui")]) 1891 1.1.1.2 mrg 1892 1.1.1.2 mrg (define_insn "*divdf_ext2" 1893 1.1.1.2 mrg [(set (match_operand:DF 0 "register_operand" "=f") 1894 1.1.1.2 mrg (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG") 1895 1.1.1.2 mrg (float_extend:DF 1896 1.1.1.2 mrg (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1897 1.1.1.2 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1898 1.1.1.2 mrg "div%-%/ %R1,%R2,%0" 1899 1.1.1.2 mrg [(set_attr "type" "fdiv") 1900 1.1.1.2 mrg (set_attr "trap" "yes") 1901 1.1.1.2 mrg (set_attr "round_suffix" "normal") 1902 1.1.1.2 mrg (set_attr "trap_suffix" "u_su_sui")]) 1903 1.1.1.2 mrg 1904 1.1.1.2 mrg (define_insn "*divdf_ext3" 1905 1.1.1.2 mrg [(set (match_operand:DF 0 "register_operand" "=f") 1906 1.1.1.2 mrg (div:DF (float_extend:DF 1907 1.1.1.2 mrg (match_operand:SF 1 "reg_or_0_operand" "fG")) 1908 1.1.1.2 mrg (float_extend:DF 1909 1.1.1.2 mrg (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1910 1.1.1.2 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1911 1.1.1.2 mrg "div%-%/ %R1,%R2,%0" 1912 1.1.1.2 mrg [(set_attr "type" "fdiv") 1913 1.1.1.2 mrg (set_attr "trap" "yes") 1914 1.1.1.2 mrg (set_attr "round_suffix" "normal") 1915 1.1.1.2 mrg (set_attr "trap_suffix" "u_su_sui")]) 1916 1.1.1.2 mrg 1917 1.1.1.2 mrg (define_expand "divtf3" 1918 1.1.1.2 mrg [(use (match_operand:TF 0 "register_operand")) 1919 1.1.1.2 mrg (use (match_operand:TF 1 "general_operand")) 1920 1.1.1.2 mrg (use (match_operand:TF 2 "general_operand"))] 1921 1.1.1.2 mrg "TARGET_HAS_XFLOATING_LIBS" 1922 1.1.1.2 mrg "alpha_emit_xfloating_arith (DIV, operands); DONE;") 1923 1.1.1.2 mrg 1924 1.1.1.2 mrg (define_insn "*sqrt<mode>2_ieee" 1925 1.1.1.2 mrg [(set (match_operand:FMODE 0 "register_operand" "=&f") 1926 1.1.1.2 mrg (sqrt:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))] 1927 1.1.1.2 mrg "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU" 1928 1.1.1.2 mrg "sqrt<modesuffix>%/ %R1,%0" 1929 1.1.1.2 mrg [(set_attr "type" "fsqrt") 1930 1.1.1.2 mrg (set_attr "opsize" "<opmode>") 1931 1.1.1.2 mrg (set_attr "trap" "yes") 1932 1.1.1.2 mrg (set_attr "round_suffix" "normal") 1933 1.1.1.2 mrg (set_attr "trap_suffix" "u_su_sui")]) 1934 1.1.1.2 mrg 1935 1.1.1.2 mrg (define_insn "sqrt<mode>2" 1936 1.1.1.2 mrg [(set (match_operand:FMODE 0 "register_operand" "=f") 1937 1.1.1.2 mrg (sqrt:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))] 1938 1.1.1.2 mrg "TARGET_FP && TARGET_FIX" 1939 1.1.1.2 mrg "sqrt<modesuffix>%/ %R1,%0" 1940 1.1.1.2 mrg [(set_attr "type" "fsqrt") 1941 1.1.1.2 mrg (set_attr "opsize" "<opmode>") 1942 1.1.1.2 mrg (set_attr "trap" "yes") 1943 1.1.1.2 mrg (set_attr "round_suffix" "normal") 1944 1.1.1.2 mrg (set_attr "trap_suffix" "u_su_sui")]) 1945 1.1 mrg 1946 1.1 mrg ;; Define conversion operators between DFmode and SImode, using the cvtql 1947 1.1 mrg ;; instruction. To allow combine et al to do useful things, we keep the 1948 1.1 mrg ;; operation as a unit until after reload, at which point we split the 1949 1.1 mrg ;; instructions. 1950 1.1 mrg ;; 1951 1.1 mrg ;; Note that we (attempt to) only consider this optimization when the 1952 1.1 mrg ;; ultimate destination is memory. If we will be doing further integer 1953 1.1 mrg ;; processing, it is cheaper to do the truncation in the int regs. 1954 1.1 mrg 1955 1.1 mrg (define_insn "*cvtql" 1956 1.1 mrg [(set (match_operand:SF 0 "register_operand" "=f") 1957 1.1 mrg (unspec:SF [(match_operand:DI 1 "reg_or_0_operand" "fG")] 1958 1.1 mrg UNSPEC_CVTQL))] 1959 1.1 mrg "TARGET_FP" 1960 1.1 mrg "cvtql%/ %R1,%0" 1961 1.1 mrg [(set_attr "type" "fadd") 1962 1.1 mrg (set_attr "trap" "yes") 1963 1.1 mrg (set_attr "trap_suffix" "v_sv")]) 1964 1.1 mrg 1965 1.1 mrg (define_insn_and_split "*fix_truncdfsi_ieee" 1966 1.1 mrg [(set (match_operand:SI 0 "memory_operand" "=m") 1967 1.1 mrg (subreg:SI 1968 1.1 mrg (match_operator:DI 4 "fix_operator" 1969 1.1 mrg [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0)) 1970 1.1 mrg (clobber (match_scratch:DI 2 "=&f")) 1971 1.1 mrg (clobber (match_scratch:SF 3 "=&f"))] 1972 1.1 mrg "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 1973 1.1 mrg "#" 1974 1.1 mrg "&& reload_completed" 1975 1.1 mrg [(set (match_dup 2) (match_op_dup 4 [(match_dup 1)])) 1976 1.1 mrg (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) 1977 1.1 mrg (set (match_dup 5) (match_dup 3))] 1978 1.1 mrg { 1979 1.1 mrg operands[5] = adjust_address (operands[0], SFmode, 0); 1980 1.1 mrg } 1981 1.1 mrg [(set_attr "type" "fadd") 1982 1.1 mrg (set_attr "trap" "yes")]) 1983 1.1 mrg 1984 1.1 mrg (define_insn_and_split "*fix_truncdfsi_internal" 1985 1.1 mrg [(set (match_operand:SI 0 "memory_operand" "=m") 1986 1.1 mrg (subreg:SI 1987 1.1 mrg (match_operator:DI 3 "fix_operator" 1988 1.1 mrg [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0)) 1989 1.1 mrg (clobber (match_scratch:DI 2 "=f"))] 1990 1.1 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1991 1.1 mrg "#" 1992 1.1 mrg "&& reload_completed" 1993 1.1 mrg [(set (match_dup 2) (match_op_dup 3 [(match_dup 1)])) 1994 1.1 mrg (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) 1995 1.1 mrg (set (match_dup 5) (match_dup 4))] 1996 1.1 mrg { 1997 1.1 mrg operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2])); 1998 1.1 mrg operands[5] = adjust_address (operands[0], SFmode, 0); 1999 1.1 mrg } 2000 1.1 mrg [(set_attr "type" "fadd") 2001 1.1 mrg (set_attr "trap" "yes")]) 2002 1.1 mrg 2003 1.1 mrg (define_insn "*fix_truncdfdi_ieee" 2004 1.1 mrg [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f") 2005 1.1 mrg (match_operator:DI 2 "fix_operator" 2006 1.1 mrg [(match_operand:DF 1 "reg_or_0_operand" "fG")]))] 2007 1.1 mrg "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2008 1.1 mrg "cvt%-q%/ %R1,%0" 2009 1.1 mrg [(set_attr "type" "fadd") 2010 1.1 mrg (set_attr "trap" "yes") 2011 1.1 mrg (set_attr "round_suffix" "c") 2012 1.1 mrg (set_attr "trap_suffix" "v_sv_svi")]) 2013 1.1 mrg 2014 1.1 mrg (define_insn "*fix_truncdfdi2" 2015 1.1 mrg [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f") 2016 1.1 mrg (match_operator:DI 2 "fix_operator" 2017 1.1.1.2 mrg [(match_operand:DF 1 "reg_or_0_operand" "fG")]))] 2018 1.1.1.2 mrg "TARGET_FP" 2019 1.1.1.2 mrg "cvt%-q%/ %R1,%0" 2020 1.1 mrg [(set_attr "type" "fadd") 2021 1.1 mrg (set_attr "trap" "yes") 2022 1.1.1.2 mrg (set_attr "round_suffix" "c") 2023 1.1.1.2 mrg (set_attr "trap_suffix" "v_sv_svi")]) 2024 1.1.1.2 mrg 2025 1.1 mrg (define_expand "fix_truncdfdi2" 2026 1.1 mrg [(set (match_operand:DI 0 "reg_no_subreg_operand") 2027 1.1 mrg (fix:DI (match_operand:DF 1 "reg_or_0_operand")))] 2028 1.1 mrg "TARGET_FP") 2029 1.1 mrg 2030 1.1 mrg (define_expand "fixuns_truncdfdi2" 2031 1.1 mrg [(set (match_operand:DI 0 "reg_no_subreg_operand") 2032 1.1 mrg (unsigned_fix:DI (match_operand:DF 1 "reg_or_0_operand")))] 2033 1.1 mrg "TARGET_FP") 2034 1.1 mrg 2035 1.1 mrg ;; Likewise between SFmode and SImode. 2036 1.1 mrg 2037 1.1 mrg (define_insn_and_split "*fix_truncsfsi_ieee" 2038 1.1 mrg [(set (match_operand:SI 0 "memory_operand" "=m") 2039 1.1 mrg (subreg:SI 2040 1.1 mrg (match_operator:DI 4 "fix_operator" 2041 1.1 mrg [(float_extend:DF 2042 1.1.1.2 mrg (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0)) 2043 1.1 mrg (clobber (match_scratch:DI 2 "=&f")) 2044 1.1 mrg (clobber (match_scratch:SF 3 "=&f"))] 2045 1.1 mrg "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2046 1.1 mrg "#" 2047 1.1 mrg "&& reload_completed" 2048 1.1 mrg [(set (match_dup 2) (match_op_dup 4 [(float_extend:DF (match_dup 1))])) 2049 1.1 mrg (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) 2050 1.1 mrg (set (match_dup 5) (match_dup 3))] 2051 1.1 mrg "operands[5] = adjust_address (operands[0], SFmode, 0);" 2052 1.1 mrg [(set_attr "type" "fadd") 2053 1.1 mrg (set_attr "trap" "yes")]) 2054 1.1 mrg 2055 1.1 mrg (define_insn_and_split "*fix_truncsfsi_internal" 2056 1.1 mrg [(set (match_operand:SI 0 "memory_operand" "=m") 2057 1.1 mrg (subreg:SI 2058 1.1 mrg (match_operator:DI 3 "fix_operator" 2059 1.1 mrg [(float_extend:DF 2060 1.1 mrg (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0)) 2061 1.1 mrg (clobber (match_scratch:DI 2 "=f"))] 2062 1.1 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2063 1.1 mrg "#" 2064 1.1 mrg "&& reload_completed" 2065 1.1 mrg [(set (match_dup 2) (match_op_dup 3 [(float_extend:DF (match_dup 1))])) 2066 1.1 mrg (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) 2067 1.1 mrg (set (match_dup 5) (match_dup 4))] 2068 1.1 mrg { 2069 1.1 mrg operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2])); 2070 1.1 mrg operands[5] = adjust_address (operands[0], SFmode, 0); 2071 1.1 mrg } 2072 1.1 mrg [(set_attr "type" "fadd") 2073 1.1 mrg (set_attr "trap" "yes")]) 2074 1.1 mrg 2075 1.1 mrg (define_insn "*fix_truncsfdi_ieee" 2076 1.1 mrg [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f") 2077 1.1 mrg (match_operator:DI 2 "fix_operator" 2078 1.1 mrg [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))] 2079 1.1 mrg "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2080 1.1 mrg "cvt%-q%/ %R1,%0" 2081 1.1 mrg [(set_attr "type" "fadd") 2082 1.1 mrg (set_attr "trap" "yes") 2083 1.1 mrg (set_attr "round_suffix" "c") 2084 1.1 mrg (set_attr "trap_suffix" "v_sv_svi")]) 2085 1.1 mrg 2086 1.1 mrg (define_insn "*fix_truncsfdi2" 2087 1.1 mrg [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f") 2088 1.1 mrg (match_operator:DI 2 "fix_operator" 2089 1.1.1.2 mrg [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))] 2090 1.1.1.2 mrg "TARGET_FP" 2091 1.1.1.2 mrg "cvt%-q%/ %R1,%0" 2092 1.1 mrg [(set_attr "type" "fadd") 2093 1.1 mrg (set_attr "trap" "yes") 2094 1.1.1.2 mrg (set_attr "round_suffix" "c") 2095 1.1 mrg (set_attr "trap_suffix" "v_sv_svi")]) 2096 1.1.1.2 mrg 2097 1.1.1.2 mrg (define_expand "fix_truncsfdi2" 2098 1.1 mrg [(set (match_operand:DI 0 "reg_no_subreg_operand") 2099 1.1 mrg (fix:DI (float_extend:DF (match_operand:SF 1 "reg_or_0_operand"))))] 2100 1.1.1.2 mrg "TARGET_FP") 2101 1.1.1.2 mrg 2102 1.1 mrg (define_expand "fixuns_truncsfdi2" 2103 1.1 mrg [(set (match_operand:DI 0 "reg_no_subreg_operand") 2104 1.1 mrg (unsigned_fix:DI 2105 1.1 mrg (float_extend:DF (match_operand:SF 1 "reg_or_0_operand"))))] 2106 1.1.1.2 mrg "TARGET_FP") 2107 1.1.1.2 mrg 2108 1.1 mrg (define_expand "fix_trunctfdi2" 2109 1.1 mrg [(use (match_operand:DI 0 "register_operand")) 2110 1.1 mrg (use (match_operand:TF 1 "general_operand"))] 2111 1.1 mrg "TARGET_HAS_XFLOATING_LIBS" 2112 1.1 mrg "alpha_emit_xfloating_cvt (FIX, operands); DONE;") 2113 1.1 mrg 2114 1.1 mrg (define_expand "fixuns_trunctfdi2" 2115 1.1 mrg [(use (match_operand:DI 0 "register_operand")) 2116 1.1 mrg (use (match_operand:TF 1 "general_operand"))] 2117 1.1 mrg "TARGET_HAS_XFLOATING_LIBS" 2118 1.1 mrg "alpha_emit_xfloating_cvt (UNSIGNED_FIX, operands); DONE;") 2119 1.1 mrg 2120 1.1 mrg (define_insn "*floatdisf_ieee" 2121 1.1 mrg [(set (match_operand:SF 0 "register_operand" "=&f") 2122 1.1 mrg (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))] 2123 1.1 mrg "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2124 1.1 mrg "cvtq%,%/ %1,%0" 2125 1.1 mrg [(set_attr "type" "fadd") 2126 1.1 mrg (set_attr "trap" "yes") 2127 1.1 mrg (set_attr "round_suffix" "normal") 2128 1.1 mrg (set_attr "trap_suffix" "sui")]) 2129 1.1 mrg 2130 1.1 mrg (define_insn "floatdisf2" 2131 1.1 mrg [(set (match_operand:SF 0 "register_operand" "=f") 2132 1.1 mrg (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))] 2133 1.1 mrg "TARGET_FP" 2134 1.1 mrg "cvtq%,%/ %1,%0" 2135 1.1 mrg [(set_attr "type" "fadd") 2136 1.1 mrg (set_attr "trap" "yes") 2137 1.1 mrg (set_attr "round_suffix" "normal") 2138 1.1 mrg (set_attr "trap_suffix" "sui")]) 2139 1.1 mrg 2140 1.1 mrg (define_insn_and_split "*floatsisf2_ieee" 2141 1.1 mrg [(set (match_operand:SF 0 "register_operand" "=&f") 2142 1.1.1.2 mrg (float:SF (match_operand:SI 1 "memory_operand" "m"))) 2143 1.1 mrg (clobber (match_scratch:DI 2 "=&f")) 2144 1.1 mrg (clobber (match_scratch:SF 3 "=&f"))] 2145 1.1 mrg "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2146 1.1 mrg "#" 2147 1.1 mrg "&& reload_completed" 2148 1.1 mrg [(set (match_dup 3) (match_dup 1)) 2149 1.1 mrg (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ)) 2150 1.1 mrg (set (match_dup 0) (float:SF (match_dup 2)))] 2151 1.1 mrg "operands[1] = adjust_address (operands[1], SFmode, 0);") 2152 1.1 mrg 2153 1.1 mrg (define_insn_and_split "*floatsisf2" 2154 1.1 mrg [(set (match_operand:SF 0 "register_operand" "=f") 2155 1.1 mrg (float:SF (match_operand:SI 1 "memory_operand" "m")))] 2156 1.1 mrg "TARGET_FP" 2157 1.1 mrg "#" 2158 1.1 mrg "&& reload_completed" 2159 1.1 mrg [(set (match_dup 0) (match_dup 1)) 2160 1.1 mrg (set (match_dup 2) (unspec:DI [(match_dup 0)] UNSPEC_CVTLQ)) 2161 1.1 mrg (set (match_dup 0) (float:SF (match_dup 2)))] 2162 1.1 mrg { 2163 1.1 mrg operands[1] = adjust_address (operands[1], SFmode, 0); 2164 1.1 mrg operands[2] = gen_rtx_REG (DImode, REGNO (operands[0])); 2165 1.1 mrg }) 2166 1.1 mrg 2167 1.1 mrg (define_insn "*floatdidf_ieee" 2168 1.1 mrg [(set (match_operand:DF 0 "register_operand" "=&f") 2169 1.1 mrg (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))] 2170 1.1 mrg "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2171 1.1 mrg "cvtq%-%/ %1,%0" 2172 1.1 mrg [(set_attr "type" "fadd") 2173 1.1 mrg (set_attr "trap" "yes") 2174 1.1 mrg (set_attr "round_suffix" "normal") 2175 1.1 mrg (set_attr "trap_suffix" "sui")]) 2176 1.1 mrg 2177 1.1 mrg (define_insn "floatdidf2" 2178 1.1 mrg [(set (match_operand:DF 0 "register_operand" "=f") 2179 1.1 mrg (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))] 2180 1.1 mrg "TARGET_FP" 2181 1.1 mrg "cvtq%-%/ %1,%0" 2182 1.1 mrg [(set_attr "type" "fadd") 2183 1.1 mrg (set_attr "trap" "yes") 2184 1.1 mrg (set_attr "round_suffix" "normal") 2185 1.1 mrg (set_attr "trap_suffix" "sui")]) 2186 1.1 mrg 2187 1.1 mrg (define_insn_and_split "*floatsidf2_ieee" 2188 1.1 mrg [(set (match_operand:DF 0 "register_operand" "=&f") 2189 1.1.1.2 mrg (float:DF (match_operand:SI 1 "memory_operand" "m"))) 2190 1.1 mrg (clobber (match_scratch:DI 2 "=&f")) 2191 1.1 mrg (clobber (match_scratch:SF 3 "=&f"))] 2192 1.1 mrg "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2193 1.1 mrg "#" 2194 1.1 mrg "&& reload_completed" 2195 1.1 mrg [(set (match_dup 3) (match_dup 1)) 2196 1.1 mrg (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ)) 2197 1.1 mrg (set (match_dup 0) (float:DF (match_dup 2)))] 2198 1.1 mrg "operands[1] = adjust_address (operands[1], SFmode, 0);") 2199 1.1 mrg 2200 1.1 mrg (define_insn_and_split "*floatsidf2" 2201 1.1 mrg [(set (match_operand:DF 0 "register_operand" "=f") 2202 1.1 mrg (float:DF (match_operand:SI 1 "memory_operand" "m")))] 2203 1.1 mrg "TARGET_FP" 2204 1.1 mrg "#" 2205 1.1 mrg "&& reload_completed" 2206 1.1 mrg [(set (match_dup 3) (match_dup 1)) 2207 1.1.1.2 mrg (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ)) 2208 1.1.1.2 mrg (set (match_dup 0) (float:DF (match_dup 2)))] 2209 1.1 mrg { 2210 1.1 mrg operands[1] = adjust_address (operands[1], SFmode, 0); 2211 1.1 mrg operands[2] = gen_rtx_REG (DImode, REGNO (operands[0])); 2212 1.1 mrg operands[3] = gen_rtx_REG (SFmode, REGNO (operands[0])); 2213 1.1.1.2 mrg }) 2214 1.1.1.2 mrg 2215 1.1 mrg (define_expand "floatditf2" 2216 1.1 mrg [(use (match_operand:TF 0 "register_operand")) 2217 1.1 mrg (use (match_operand:DI 1 "general_operand"))] 2218 1.1 mrg "TARGET_HAS_XFLOATING_LIBS" 2219 1.1.1.2 mrg "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;") 2220 1.1.1.2 mrg 2221 1.1 mrg (define_expand "floatunsdisf2" 2222 1.1 mrg [(use (match_operand:SF 0 "register_operand")) 2223 1.1 mrg (use (match_operand:DI 1 "register_operand"))] 2224 1.1 mrg "TARGET_FP" 2225 1.1.1.2 mrg "alpha_emit_floatuns (operands); DONE;") 2226 1.1.1.2 mrg 2227 1.1 mrg (define_expand "floatunsdidf2" 2228 1.1 mrg [(use (match_operand:DF 0 "register_operand")) 2229 1.1 mrg (use (match_operand:DI 1 "register_operand"))] 2230 1.1 mrg "TARGET_FP" 2231 1.1.1.2 mrg "alpha_emit_floatuns (operands); DONE;") 2232 1.1.1.2 mrg 2233 1.1 mrg (define_expand "floatunsditf2" 2234 1.1 mrg [(use (match_operand:TF 0 "register_operand")) 2235 1.1 mrg (use (match_operand:DI 1 "general_operand"))] 2236 1.1 mrg "TARGET_HAS_XFLOATING_LIBS" 2237 1.1 mrg "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;") 2238 1.1 mrg 2239 1.1 mrg (define_expand "extendsfdf2" 2240 1.1 mrg [(set (match_operand:DF 0 "register_operand") 2241 1.1 mrg (float_extend:DF (match_operand:SF 1 "nonimmediate_operand")))] 2242 1.1 mrg "TARGET_FP" 2243 1.1 mrg { 2244 1.1 mrg if (alpha_fptm >= ALPHA_FPTM_SU) 2245 1.1 mrg operands[1] = force_reg (SFmode, operands[1]); 2246 1.1 mrg }) 2247 1.1 mrg 2248 1.1 mrg ;; The Unicos/Mk assembler doesn't support cvtst, but we've already 2249 1.1 mrg ;; asserted that alpha_fptm == ALPHA_FPTM_N. 2250 1.1 mrg 2251 1.1 mrg (define_insn "*extendsfdf2_ieee" 2252 1.1 mrg [(set (match_operand:DF 0 "register_operand" "=&f") 2253 1.1 mrg (float_extend:DF (match_operand:SF 1 "register_operand" "f")))] 2254 1.1 mrg "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2255 1.1 mrg "cvtsts %1,%0" 2256 1.1 mrg [(set_attr "type" "fadd") 2257 1.1 mrg (set_attr "trap" "yes")]) 2258 1.1 mrg 2259 1.1 mrg (define_insn "*extendsfdf2_internal" 2260 1.1 mrg [(set (match_operand:DF 0 "register_operand" "=f,f,m") 2261 1.1 mrg (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))] 2262 1.1 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2263 1.1 mrg "@ 2264 1.1.1.2 mrg cpys %1,%1,%0 2265 1.1.1.2 mrg ld%, %0,%1 2266 1.1 mrg st%- %1,%0" 2267 1.1 mrg [(set_attr "type" "fcpys,fld,fst")]) 2268 1.1 mrg 2269 1.1 mrg ;; Use register_operand for operand 1 to prevent compress_float_constant 2270 1.1.1.2 mrg ;; from doing something silly. When optimizing we'll put things back 2271 1.1.1.2 mrg ;; together anyway. 2272 1.1.1.2 mrg (define_expand "extendsftf2" 2273 1.1 mrg [(use (match_operand:TF 0 "register_operand")) 2274 1.1.1.2 mrg (use (match_operand:SF 1 "register_operand"))] 2275 1.1.1.2 mrg "TARGET_HAS_XFLOATING_LIBS" 2276 1.1.1.2 mrg { 2277 1.1.1.2 mrg rtx tmp = gen_reg_rtx (DFmode); 2278 1.1.1.2 mrg emit_insn (gen_extendsfdf2 (tmp, operands[1])); 2279 1.1 mrg emit_insn (gen_extenddftf2 (operands[0], tmp)); 2280 1.1.1.2 mrg DONE; 2281 1.1.1.2 mrg }) 2282 1.1.1.2 mrg 2283 1.1.1.2 mrg (define_expand "extenddftf2" 2284 1.1.1.2 mrg [(use (match_operand:TF 0 "register_operand")) 2285 1.1 mrg (use (match_operand:DF 1 "register_operand"))] 2286 1.1 mrg "TARGET_HAS_XFLOATING_LIBS" 2287 1.1 mrg "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;") 2288 1.1 mrg 2289 1.1 mrg (define_insn "*truncdfsf2_ieee" 2290 1.1.1.2 mrg [(set (match_operand:SF 0 "register_operand" "=&f") 2291 1.1.1.2 mrg (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))] 2292 1.1.1.2 mrg "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2293 1.1.1.2 mrg "cvt%-%,%/ %R1,%0" 2294 1.1.1.2 mrg [(set_attr "type" "fadd") 2295 1.1 mrg (set_attr "trap" "yes") 2296 1.1 mrg (set_attr "round_suffix" "normal") 2297 1.1 mrg (set_attr "trap_suffix" "u_su_sui")]) 2298 1.1 mrg 2299 1.1 mrg (define_insn "truncdfsf2" 2300 1.1.1.2 mrg [(set (match_operand:SF 0 "register_operand" "=f") 2301 1.1.1.2 mrg (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))] 2302 1.1.1.2 mrg "TARGET_FP" 2303 1.1 mrg "cvt%-%,%/ %R1,%0" 2304 1.1.1.2 mrg [(set_attr "type" "fadd") 2305 1.1 mrg (set_attr "trap" "yes") 2306 1.1.1.2 mrg (set_attr "round_suffix" "normal") 2307 1.1.1.2 mrg (set_attr "trap_suffix" "u_su_sui")]) 2308 1.1.1.2 mrg 2309 1.1.1.2 mrg (define_expand "trunctfdf2" 2310 1.1.1.2 mrg [(use (match_operand:DF 0 "register_operand")) 2311 1.1.1.2 mrg (use (match_operand:TF 1 "general_operand"))] 2312 1.1 mrg "TARGET_HAS_XFLOATING_LIBS" 2313 1.1.1.2 mrg "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;") 2314 1.1.1.2 mrg 2315 1.1.1.2 mrg (define_expand "trunctfsf2" 2316 1.1.1.2 mrg [(use (match_operand:SF 0 "register_operand")) 2317 1.1.1.2 mrg (use (match_operand:TF 1 "general_operand"))] 2318 1.1 mrg "TARGET_FP && TARGET_HAS_XFLOATING_LIBS" 2319 1.1.1.2 mrg { 2320 1.1.1.2 mrg rtx tmpf, sticky, arg, lo, hi; 2321 1.1.1.2 mrg 2322 1.1.1.2 mrg tmpf = gen_reg_rtx (DFmode); 2323 1.1 mrg sticky = gen_reg_rtx (DImode); 2324 1.1.1.4 mrg arg = copy_to_mode_reg (TFmode, operands[1]); 2325 1.1.1.2 mrg lo = gen_lowpart (DImode, arg); 2326 1.1.1.2 mrg hi = gen_highpart (DImode, arg); 2327 1.1.1.2 mrg 2328 1.1.1.2 mrg /* Convert the low word of the TFmode value into a sticky rounding bit, 2329 1.1.1.2 mrg then or it into the low bit of the high word. This leaves the sticky 2330 1.1 mrg bit at bit 48 of the fraction, which is representable in DFmode, 2331 1.1 mrg which prevents rounding error in the final conversion to SFmode. */ 2332 1.1 mrg 2333 1.1 mrg emit_insn (gen_rtx_SET (sticky, gen_rtx_NE (DImode, lo, const0_rtx))); 2334 1.1 mrg emit_insn (gen_iordi3 (hi, hi, sticky)); 2335 1.1 mrg emit_insn (gen_trunctfdf2 (tmpf, arg)); 2336 1.1 mrg emit_insn (gen_truncdfsf2 (operands[0], tmpf)); 2337 1.1 mrg DONE; 2338 1.1 mrg }) 2339 1.1 mrg 2341 1.1 mrg ;; Next are all the integer comparisons, and conditional moves and branches 2342 1.1 mrg ;; and some of the related define_expand's and define_split's. 2343 1.1 mrg 2344 1.1 mrg (define_insn "*setcc_internal" 2345 1.1 mrg [(set (match_operand 0 "register_operand" "=r") 2346 1.1 mrg (match_operator 1 "alpha_comparison_operator" 2347 1.1 mrg [(match_operand:DI 2 "register_operand" "r") 2348 1.1 mrg (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))] 2349 1.1 mrg "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT 2350 1.1 mrg && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8 2351 1.1 mrg && GET_MODE (operands[0]) == GET_MODE (operands[1])" 2352 1.1 mrg "cmp%C1 %2,%3,%0" 2353 1.1 mrg [(set_attr "type" "icmp")]) 2354 1.1 mrg 2355 1.1 mrg ;; Yes, we can technically support reg_or_8bit_operand in operand 2, 2356 1.1 mrg ;; but that's non-canonical rtl and allowing that causes inefficiencies 2357 1.1 mrg ;; from cse on. 2358 1.1 mrg (define_insn "*setcc_swapped_internal" 2359 1.1 mrg [(set (match_operand 0 "register_operand" "=r") 2360 1.1 mrg (match_operator 1 "alpha_swapped_comparison_operator" 2361 1.1 mrg [(match_operand:DI 2 "register_operand" "r") 2362 1.1 mrg (match_operand:DI 3 "reg_or_0_operand" "rJ")]))] 2363 1.1 mrg "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT 2364 1.1 mrg && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8 2365 1.1 mrg && GET_MODE (operands[0]) == GET_MODE (operands[1])" 2366 1.1 mrg "cmp%c1 %r3,%2,%0" 2367 1.1 mrg [(set_attr "type" "icmp")]) 2368 1.1 mrg 2369 1.1 mrg ;; Use match_operator rather than ne directly so that we can match 2370 1.1 mrg ;; multiple integer modes. 2371 1.1 mrg (define_insn "*setne_internal" 2372 1.1 mrg [(set (match_operand 0 "register_operand" "=r") 2373 1.1 mrg (match_operator 1 "signed_comparison_operator" 2374 1.1 mrg [(match_operand:DI 2 "register_operand" "r") 2375 1.1 mrg (const_int 0)]))] 2376 1.1 mrg "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT 2377 1.1 mrg && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8 2378 1.1 mrg && GET_CODE (operands[1]) == NE 2379 1.1 mrg && GET_MODE (operands[0]) == GET_MODE (operands[1])" 2380 1.1.1.2 mrg "cmpult $31,%2,%0" 2381 1.1.1.2 mrg [(set_attr "type" "icmp")]) 2382 1.1.1.2 mrg 2383 1.1 mrg ;; The mode folding trick can't be used with const_int operands, since 2384 1.1 mrg ;; reload needs to know the proper mode. 2385 1.1 mrg ;; 2386 1.1.1.2 mrg ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand 2387 1.1.1.2 mrg ;; in order to create more pairs of constants. As long as we're allowing 2388 1.1 mrg ;; two constants at the same time, and will have to reload one of them... 2389 1.1 mrg 2390 1.1 mrg (define_insn "*mov<mode>cc_internal" 2391 1.1 mrg [(set (match_operand:IMODE 0 "register_operand" "=r,r,r,r") 2392 1.1 mrg (if_then_else:IMODE 2393 1.1 mrg (match_operator 2 "signed_comparison_operator" 2394 1.1 mrg [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J") 2395 1.1 mrg (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")]) 2396 1.1.1.2 mrg (match_operand:IMODE 1 "add_operand" "rI,0,rI,0") 2397 1.1.1.2 mrg (match_operand:IMODE 5 "add_operand" "0,rI,0,rI")))] 2398 1.1.1.2 mrg "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)" 2399 1.1 mrg "@ 2400 1.1 mrg cmov%C2 %r3,%1,%0 2401 1.1 mrg cmov%D2 %r3,%5,%0 2402 1.1 mrg cmov%c2 %r4,%1,%0 2403 1.1.1.2 mrg cmov%d2 %r4,%5,%0" 2404 1.1.1.2 mrg [(set_attr "type" "icmov")]) 2405 1.1 mrg 2406 1.1 mrg (define_insn "*mov<mode>cc_lbc" 2407 1.1 mrg [(set (match_operand:IMODE 0 "register_operand" "=r,r") 2408 1.1 mrg (if_then_else:IMODE 2409 1.1 mrg (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ") 2410 1.1 mrg (const_int 1) 2411 1.1.1.2 mrg (const_int 0)) 2412 1.1.1.2 mrg (const_int 0)) 2413 1.1.1.2 mrg (match_operand:IMODE 1 "reg_or_8bit_operand" "rI,0") 2414 1.1 mrg (match_operand:IMODE 3 "reg_or_8bit_operand" "0,rI")))] 2415 1.1 mrg "" 2416 1.1 mrg "@ 2417 1.1 mrg cmovlbc %r2,%1,%0 2418 1.1.1.2 mrg cmovlbs %r2,%3,%0" 2419 1.1.1.2 mrg [(set_attr "type" "icmov")]) 2420 1.1 mrg 2421 1.1 mrg (define_insn "*mov<mode>cc_lbs" 2422 1.1 mrg [(set (match_operand:IMODE 0 "register_operand" "=r,r") 2423 1.1 mrg (if_then_else:IMODE 2424 1.1 mrg (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ") 2425 1.1 mrg (const_int 1) 2426 1.1 mrg (const_int 0)) 2427 1.1 mrg (const_int 0)) 2428 1.1 mrg (match_operand:IMODE 1 "reg_or_8bit_operand" "rI,0") 2429 1.1.1.2 mrg (match_operand:IMODE 3 "reg_or_8bit_operand" "0,rI")))] 2430 1.1.1.2 mrg "" 2431 1.1 mrg "@ 2432 1.1 mrg cmovlbs %r2,%1,%0 2433 1.1 mrg cmovlbc %r2,%3,%0" 2434 1.1 mrg [(set_attr "type" "icmov")]) 2435 1.1 mrg 2436 1.1 mrg ;; For ABS, we have two choices, depending on whether the input and output 2437 1.1 mrg ;; registers are the same or not. 2438 1.1 mrg (define_expand "absdi2" 2439 1.1 mrg [(set (match_operand:DI 0 "register_operand") 2440 1.1 mrg (abs:DI (match_operand:DI 1 "register_operand")))] 2441 1.1.1.2 mrg "" 2442 1.1.1.2 mrg { 2443 1.1 mrg if (rtx_equal_p (operands[0], operands[1])) 2444 1.1 mrg emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode))); 2445 1.1 mrg else 2446 1.1.1.2 mrg emit_insn (gen_absdi2_diff (operands[0], operands[1])); 2447 1.1 mrg DONE; 2448 1.1 mrg }) 2449 1.1.1.2 mrg 2450 1.1.1.2 mrg (define_expand "absdi2_same" 2451 1.1 mrg [(set (match_operand:DI 1 "register_operand") 2452 1.1 mrg (neg:DI (match_operand:DI 0 "register_operand"))) 2453 1.1 mrg (set (match_dup 0) 2454 1.1.1.2 mrg (if_then_else:DI (ge (match_dup 0) (const_int 0)) 2455 1.1 mrg (match_dup 0) 2456 1.1 mrg (match_dup 1)))]) 2457 1.1.1.2 mrg 2458 1.1 mrg (define_expand "absdi2_diff" 2459 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand") 2460 1.1 mrg (neg:DI (match_operand:DI 1 "register_operand"))) 2461 1.1 mrg (set (match_dup 0) 2462 1.1 mrg (if_then_else:DI (lt (match_dup 1) (const_int 0)) 2463 1.1.1.2 mrg (match_dup 0) 2464 1.1 mrg (match_dup 1)))]) 2465 1.1 mrg 2466 1.1.1.2 mrg (define_split 2467 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand") 2468 1.1 mrg (abs:DI (match_dup 0))) 2469 1.1 mrg (clobber (match_operand:DI 1 "register_operand"))] 2470 1.1 mrg "" 2471 1.1.1.2 mrg [(set (match_dup 1) (neg:DI (match_dup 0))) 2472 1.1 mrg (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0)) 2473 1.1 mrg (match_dup 0) (match_dup 1)))]) 2474 1.1.1.2 mrg 2475 1.1 mrg (define_split 2476 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand") 2477 1.1 mrg (abs:DI (match_operand:DI 1 "register_operand")))] 2478 1.1 mrg "! rtx_equal_p (operands[0], operands[1])" 2479 1.1 mrg [(set (match_dup 0) (neg:DI (match_dup 1))) 2480 1.1.1.2 mrg (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0)) 2481 1.1 mrg (match_dup 0) (match_dup 1)))]) 2482 1.1 mrg 2483 1.1.1.2 mrg (define_split 2484 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand") 2485 1.1 mrg (neg:DI (abs:DI (match_dup 0)))) 2486 1.1 mrg (clobber (match_operand:DI 1 "register_operand"))] 2487 1.1 mrg "" 2488 1.1.1.2 mrg [(set (match_dup 1) (neg:DI (match_dup 0))) 2489 1.1 mrg (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0)) 2490 1.1.1.2 mrg (match_dup 0) (match_dup 1)))]) 2491 1.1.1.2 mrg 2492 1.1.1.2 mrg (define_split 2493 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand") 2494 1.1.1.2 mrg (neg:DI (abs:DI (match_operand:DI 1 "register_operand"))))] 2495 1.1 mrg "! rtx_equal_p (operands[0], operands[1])" 2496 1.1.1.2 mrg [(set (match_dup 0) (neg:DI (match_dup 1))) 2497 1.1 mrg (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0)) 2498 1.1 mrg (match_dup 0) (match_dup 1)))]) 2499 1.1 mrg 2500 1.1 mrg (define_insn "<code><mode>3" 2501 1.1.1.2 mrg [(set (match_operand:I12MODE 0 "register_operand" "=r") 2502 1.1.1.2 mrg (any_maxmin:I12MODE 2503 1.1.1.2 mrg (match_operand:I12MODE 1 "reg_or_0_operand" "%rJ") 2504 1.1 mrg (match_operand:I12MODE 2 "reg_or_8bit_operand" "rI")))] 2505 1.1 mrg "TARGET_MAX" 2506 1.1 mrg "<maxmin><vecmodesuffix> %r1,%2,%0" 2507 1.1.1.2 mrg [(set_attr "type" "mvi")]) 2508 1.1 mrg 2509 1.1 mrg (define_expand "smaxdi3" 2510 1.1.1.2 mrg [(set (match_dup 3) 2511 1.1.1.2 mrg (le:DI (match_operand:DI 1 "reg_or_0_operand") 2512 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand"))) 2513 1.1.1.2 mrg (set (match_operand:DI 0 "register_operand") 2514 1.1 mrg (if_then_else:DI (eq (match_dup 3) (const_int 0)) 2515 1.1 mrg (match_dup 1) (match_dup 2)))] 2516 1.1 mrg "" 2517 1.1.1.2 mrg "operands[3] = gen_reg_rtx (DImode);") 2518 1.1 mrg 2519 1.1 mrg (define_split 2520 1.1 mrg [(set (match_operand:DI 0 "register_operand") 2521 1.1 mrg (smax:DI (match_operand:DI 1 "reg_or_0_operand") 2522 1.1 mrg (match_operand:DI 2 "reg_or_8bit_operand"))) 2523 1.1 mrg (clobber (match_operand:DI 3 "register_operand"))] 2524 1.1 mrg "operands[2] != const0_rtx" 2525 1.1 mrg [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2))) 2526 1.1 mrg (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0)) 2527 1.1 mrg (match_dup 1) (match_dup 2)))]) 2528 1.1 mrg 2529 1.1.1.2 mrg (define_insn "*smax_const0" 2530 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand" "=r") 2531 1.1.1.2 mrg (smax:DI (match_operand:DI 1 "register_operand" "0") 2532 1.1 mrg (const_int 0)))] 2533 1.1 mrg "" 2534 1.1 mrg "cmovlt %0,0,%0" 2535 1.1.1.2 mrg [(set_attr "type" "icmov")]) 2536 1.1 mrg 2537 1.1 mrg (define_expand "smindi3" 2538 1.1.1.2 mrg [(set (match_dup 3) 2539 1.1.1.2 mrg (lt:DI (match_operand:DI 1 "reg_or_0_operand") 2540 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand"))) 2541 1.1.1.2 mrg (set (match_operand:DI 0 "register_operand") 2542 1.1 mrg (if_then_else:DI (ne (match_dup 3) (const_int 0)) 2543 1.1 mrg (match_dup 1) (match_dup 2)))] 2544 1.1 mrg "" 2545 1.1.1.2 mrg "operands[3] = gen_reg_rtx (DImode);") 2546 1.1 mrg 2547 1.1 mrg (define_split 2548 1.1 mrg [(set (match_operand:DI 0 "register_operand") 2549 1.1 mrg (smin:DI (match_operand:DI 1 "reg_or_0_operand") 2550 1.1 mrg (match_operand:DI 2 "reg_or_8bit_operand"))) 2551 1.1 mrg (clobber (match_operand:DI 3 "register_operand"))] 2552 1.1 mrg "operands[2] != const0_rtx" 2553 1.1 mrg [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2))) 2554 1.1 mrg (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0)) 2555 1.1 mrg (match_dup 1) (match_dup 2)))]) 2556 1.1 mrg 2557 1.1.1.2 mrg (define_insn "*smin_const0" 2558 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand" "=r") 2559 1.1.1.2 mrg (smin:DI (match_operand:DI 1 "register_operand" "0") 2560 1.1 mrg (const_int 0)))] 2561 1.1 mrg "" 2562 1.1 mrg "cmovgt %0,0,%0" 2563 1.1 mrg [(set_attr "type" "icmov")]) 2564 1.1 mrg 2565 1.1 mrg (define_expand "umaxdi3" 2566 1.1.1.2 mrg [(set (match_dup 3) 2567 1.1.1.2 mrg (leu:DI (match_operand:DI 1 "reg_or_0_operand") 2568 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand"))) 2569 1.1.1.2 mrg (set (match_operand:DI 0 "register_operand") 2570 1.1 mrg (if_then_else:DI (eq (match_dup 3) (const_int 0)) 2571 1.1 mrg (match_dup 1) (match_dup 2)))] 2572 1.1 mrg "" 2573 1.1.1.2 mrg "operands[3] = gen_reg_rtx (DImode);") 2574 1.1 mrg 2575 1.1 mrg (define_split 2576 1.1 mrg [(set (match_operand:DI 0 "register_operand") 2577 1.1.1.2 mrg (umax:DI (match_operand:DI 1 "reg_or_0_operand") 2578 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand"))) 2579 1.1.1.2 mrg (clobber (match_operand:DI 3 "register_operand"))] 2580 1.1 mrg "operands[2] != const0_rtx" 2581 1.1 mrg [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2))) 2582 1.1 mrg (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0)) 2583 1.1 mrg (match_dup 1) (match_dup 2)))]) 2584 1.1 mrg 2585 1.1 mrg (define_expand "umindi3" 2586 1.1.1.2 mrg [(set (match_dup 3) 2587 1.1.1.2 mrg (ltu:DI (match_operand:DI 1 "reg_or_0_operand") 2588 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand"))) 2589 1.1.1.2 mrg (set (match_operand:DI 0 "register_operand") 2590 1.1 mrg (if_then_else:DI (ne (match_dup 3) (const_int 0)) 2591 1.1 mrg (match_dup 1) (match_dup 2)))] 2592 1.1 mrg "" 2593 1.1.1.2 mrg "operands[3] = gen_reg_rtx (DImode);") 2594 1.1 mrg 2595 1.1 mrg (define_split 2596 1.1 mrg [(set (match_operand:DI 0 "register_operand") 2597 1.1 mrg (umin:DI (match_operand:DI 1 "reg_or_0_operand") 2598 1.1 mrg (match_operand:DI 2 "reg_or_8bit_operand"))) 2599 1.1 mrg (clobber (match_operand:DI 3 "register_operand"))] 2600 1.1 mrg "operands[2] != const0_rtx" 2601 1.1.1.2 mrg [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2))) 2602 1.1 mrg (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0)) 2603 1.1 mrg (match_dup 1) (match_dup 2)))]) 2604 1.1 mrg 2605 1.1 mrg (define_insn "*bcc_normal" 2606 1.1 mrg [(set (pc) 2607 1.1 mrg (if_then_else 2608 1.1 mrg (match_operator 1 "signed_comparison_operator" 2609 1.1 mrg [(match_operand:DI 2 "reg_or_0_operand" "rJ") 2610 1.1 mrg (const_int 0)]) 2611 1.1 mrg (label_ref (match_operand 0)) 2612 1.1 mrg (pc)))] 2613 1.1 mrg "" 2614 1.1 mrg "b%C1 %r2,%0" 2615 1.1.1.2 mrg [(set_attr "type" "ibr")]) 2616 1.1 mrg 2617 1.1 mrg (define_insn "*bcc_reverse" 2618 1.1 mrg [(set (pc) 2619 1.1 mrg (if_then_else 2620 1.1 mrg (match_operator 1 "signed_comparison_operator" 2621 1.1 mrg [(match_operand:DI 2 "register_operand" "r") 2622 1.1 mrg (const_int 0)]) 2623 1.1 mrg 2624 1.1 mrg (pc) 2625 1.1 mrg (label_ref (match_operand 0))))] 2626 1.1 mrg "" 2627 1.1.1.2 mrg "b%c1 %2,%0" 2628 1.1 mrg [(set_attr "type" "ibr")]) 2629 1.1 mrg 2630 1.1 mrg (define_insn "*blbs_normal" 2631 1.1 mrg [(set (pc) 2632 1.1 mrg (if_then_else 2633 1.1 mrg (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 2634 1.1 mrg (const_int 1) 2635 1.1 mrg (const_int 0)) 2636 1.1 mrg (const_int 0)) 2637 1.1 mrg (label_ref (match_operand 0)) 2638 1.1 mrg (pc)))] 2639 1.1 mrg "" 2640 1.1.1.2 mrg "blbs %r1,%0" 2641 1.1 mrg [(set_attr "type" "ibr")]) 2642 1.1 mrg 2643 1.1 mrg (define_insn "*blbc_normal" 2644 1.1 mrg [(set (pc) 2645 1.1 mrg (if_then_else 2646 1.1 mrg (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 2647 1.1 mrg (const_int 1) 2648 1.1 mrg (const_int 0)) 2649 1.1 mrg (const_int 0)) 2650 1.1 mrg (label_ref (match_operand 0)) 2651 1.1.1.2 mrg (pc)))] 2652 1.1.1.2 mrg "" 2653 1.1.1.2 mrg "blbc %r1,%0" 2654 1.1.1.2 mrg [(set_attr "type" "ibr")]) 2655 1.1.1.2 mrg 2656 1.1 mrg (define_split 2657 1.1.1.2 mrg [(parallel 2658 1.1 mrg [(set (pc) 2659 1.1 mrg (if_then_else 2660 1.1 mrg (match_operator 1 "comparison_operator" 2661 1.1 mrg [(zero_extract:DI (match_operand:DI 2 "register_operand") 2662 1.1 mrg (const_int 1) 2663 1.1 mrg (match_operand:DI 3 "const_int_operand")) 2664 1.1 mrg (const_int 0)]) 2665 1.1 mrg (label_ref (match_operand 0)) 2666 1.1 mrg (pc))) 2667 1.1 mrg (clobber (match_operand:DI 4 "register_operand"))])] 2668 1.1 mrg "INTVAL (operands[3]) != 0" 2669 1.1.1.2 mrg [(set (match_dup 4) 2670 1.1 mrg (lshiftrt:DI (match_dup 2) (match_dup 3))) 2671 1.1 mrg (set (pc) 2672 1.1 mrg (if_then_else (match_op_dup 1 2673 1.1 mrg [(zero_extract:DI (match_dup 4) 2674 1.1 mrg (const_int 1) 2675 1.1 mrg (const_int 0)) 2676 1.1 mrg (const_int 0)]) 2677 1.1 mrg (label_ref (match_dup 0)) 2678 1.1 mrg (pc)))] 2679 1.1 mrg ) 2680 1.1 mrg 2682 1.1 mrg ;; The following are the corresponding floating-point insns. Recall 2683 1.1 mrg ;; we need to have variants that expand the arguments from SFmode 2684 1.1 mrg ;; to DFmode. 2685 1.1 mrg 2686 1.1 mrg (define_insn "*cmpdf_ieee" 2687 1.1 mrg [(set (match_operand:DF 0 "register_operand" "=&f") 2688 1.1 mrg (match_operator:DF 1 "alpha_fp_comparison_operator" 2689 1.1 mrg [(match_operand:DF 2 "reg_or_0_operand" "fG") 2690 1.1 mrg (match_operand:DF 3 "reg_or_0_operand" "fG")]))] 2691 1.1 mrg "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2692 1.1 mrg "cmp%-%C1%/ %R2,%R3,%0" 2693 1.1 mrg [(set_attr "type" "fadd") 2694 1.1 mrg (set_attr "trap" "yes") 2695 1.1 mrg (set_attr "trap_suffix" "su")]) 2696 1.1 mrg 2697 1.1 mrg (define_insn "*cmpdf_internal" 2698 1.1 mrg [(set (match_operand:DF 0 "register_operand" "=f") 2699 1.1 mrg (match_operator:DF 1 "alpha_fp_comparison_operator" 2700 1.1 mrg [(match_operand:DF 2 "reg_or_0_operand" "fG") 2701 1.1 mrg (match_operand:DF 3 "reg_or_0_operand" "fG")]))] 2702 1.1 mrg "TARGET_FP" 2703 1.1 mrg "cmp%-%C1%/ %R2,%R3,%0" 2704 1.1 mrg [(set_attr "type" "fadd") 2705 1.1 mrg (set_attr "trap" "yes") 2706 1.1 mrg (set_attr "trap_suffix" "su")]) 2707 1.1 mrg 2708 1.1 mrg (define_insn "*cmpdf_ext1" 2709 1.1 mrg [(set (match_operand:DF 0 "register_operand" "=f") 2710 1.1 mrg (match_operator:DF 1 "alpha_fp_comparison_operator" 2711 1.1 mrg [(float_extend:DF 2712 1.1 mrg (match_operand:SF 2 "reg_or_0_operand" "fG")) 2713 1.1 mrg (match_operand:DF 3 "reg_or_0_operand" "fG")]))] 2714 1.1 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2715 1.1 mrg "cmp%-%C1%/ %R2,%R3,%0" 2716 1.1 mrg [(set_attr "type" "fadd") 2717 1.1 mrg (set_attr "trap" "yes") 2718 1.1 mrg (set_attr "trap_suffix" "su")]) 2719 1.1 mrg 2720 1.1 mrg (define_insn "*cmpdf_ext2" 2721 1.1 mrg [(set (match_operand:DF 0 "register_operand" "=f") 2722 1.1 mrg (match_operator:DF 1 "alpha_fp_comparison_operator" 2723 1.1 mrg [(match_operand:DF 2 "reg_or_0_operand" "fG") 2724 1.1 mrg (float_extend:DF 2725 1.1 mrg (match_operand:SF 3 "reg_or_0_operand" "fG"))]))] 2726 1.1 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2727 1.1 mrg "cmp%-%C1%/ %R2,%R3,%0" 2728 1.1 mrg [(set_attr "type" "fadd") 2729 1.1 mrg (set_attr "trap" "yes") 2730 1.1 mrg (set_attr "trap_suffix" "su")]) 2731 1.1 mrg 2732 1.1 mrg (define_insn "*cmpdf_ext3" 2733 1.1 mrg [(set (match_operand:DF 0 "register_operand" "=f") 2734 1.1.1.2 mrg (match_operator:DF 1 "alpha_fp_comparison_operator" 2735 1.1.1.2 mrg [(float_extend:DF 2736 1.1.1.2 mrg (match_operand:SF 2 "reg_or_0_operand" "fG")) 2737 1.1 mrg (float_extend:DF 2738 1.1 mrg (match_operand:SF 3 "reg_or_0_operand" "fG"))]))] 2739 1.1 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2740 1.1.1.2 mrg "cmp%-%C1%/ %R2,%R3,%0" 2741 1.1.1.2 mrg [(set_attr "type" "fadd") 2742 1.1 mrg (set_attr "trap" "yes") 2743 1.1 mrg (set_attr "trap_suffix" "su")]) 2744 1.1 mrg 2745 1.1 mrg (define_insn "*mov<mode>cc_internal" 2746 1.1 mrg [(set (match_operand:FMODE 0 "register_operand" "=f,f") 2747 1.1 mrg (if_then_else:FMODE 2748 1.1 mrg (match_operator 3 "signed_comparison_operator" 2749 1.1 mrg [(match_operand:DF 4 "reg_or_0_operand" "fG,fG") 2750 1.1 mrg (match_operand:DF 2 "const0_operand" "G,G")]) 2751 1.1 mrg (match_operand:FMODE 1 "reg_or_0_operand" "fG,0") 2752 1.1 mrg (match_operand:FMODE 5 "reg_or_0_operand" "0,fG")))] 2753 1.1 mrg "TARGET_FP" 2754 1.1 mrg "@ 2755 1.1 mrg fcmov%C3 %R4,%R1,%0 2756 1.1 mrg fcmov%D3 %R4,%R5,%0" 2757 1.1 mrg [(set_attr "type" "fcmov")]) 2758 1.1 mrg 2759 1.1 mrg (define_insn "*movdfcc_ext1" 2760 1.1 mrg [(set (match_operand:DF 0 "register_operand" "=f,f") 2761 1.1 mrg (if_then_else:DF 2762 1.1 mrg (match_operator 3 "signed_comparison_operator" 2763 1.1 mrg [(match_operand:DF 4 "reg_or_0_operand" "fG,fG") 2764 1.1 mrg (match_operand:DF 2 "const0_operand" "G,G")]) 2765 1.1 mrg (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0")) 2766 1.1 mrg (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] 2767 1.1 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2768 1.1 mrg "@ 2769 1.1 mrg fcmov%C3 %R4,%R1,%0 2770 1.1 mrg fcmov%D3 %R4,%R5,%0" 2771 1.1 mrg [(set_attr "type" "fcmov")]) 2772 1.1 mrg 2773 1.1 mrg (define_insn "*movdfcc_ext2" 2774 1.1 mrg [(set (match_operand:DF 0 "register_operand" "=f,f") 2775 1.1 mrg (if_then_else:DF 2776 1.1 mrg (match_operator 3 "signed_comparison_operator" 2777 1.1 mrg [(float_extend:DF 2778 1.1 mrg (match_operand:SF 4 "reg_or_0_operand" "fG,fG")) 2779 1.1 mrg (match_operand:DF 2 "const0_operand" "G,G")]) 2780 1.1 mrg (match_operand:DF 1 "reg_or_0_operand" "fG,0") 2781 1.1 mrg (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] 2782 1.1 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2783 1.1 mrg "@ 2784 1.1 mrg fcmov%C3 %R4,%R1,%0 2785 1.1 mrg fcmov%D3 %R4,%R5,%0" 2786 1.1 mrg [(set_attr "type" "fcmov")]) 2787 1.1 mrg 2788 1.1 mrg (define_insn "*movdfcc_ext3" 2789 1.1 mrg [(set (match_operand:SF 0 "register_operand" "=f,f") 2790 1.1 mrg (if_then_else:SF 2791 1.1 mrg (match_operator 3 "signed_comparison_operator" 2792 1.1 mrg [(float_extend:DF 2793 1.1 mrg (match_operand:SF 4 "reg_or_0_operand" "fG,fG")) 2794 1.1 mrg (match_operand:DF 2 "const0_operand" "G,G")]) 2795 1.1 mrg (match_operand:SF 1 "reg_or_0_operand" "fG,0") 2796 1.1 mrg (match_operand:SF 5 "reg_or_0_operand" "0,fG")))] 2797 1.1 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2798 1.1 mrg "@ 2799 1.1 mrg fcmov%C3 %R4,%R1,%0 2800 1.1 mrg fcmov%D3 %R4,%R5,%0" 2801 1.1 mrg [(set_attr "type" "fcmov")]) 2802 1.1 mrg 2803 1.1 mrg (define_insn "*movdfcc_ext4" 2804 1.1 mrg [(set (match_operand:DF 0 "register_operand" "=f,f") 2805 1.1 mrg (if_then_else:DF 2806 1.1 mrg (match_operator 3 "signed_comparison_operator" 2807 1.1 mrg [(float_extend:DF 2808 1.1 mrg (match_operand:SF 4 "reg_or_0_operand" "fG,fG")) 2809 1.1.1.2 mrg (match_operand:DF 2 "const0_operand" "G,G")]) 2810 1.1.1.2 mrg (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0")) 2811 1.1.1.2 mrg (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] 2812 1.1 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2813 1.1 mrg "@ 2814 1.1 mrg fcmov%C3 %R4,%R1,%0 2815 1.1 mrg fcmov%D3 %R4,%R5,%0" 2816 1.1 mrg [(set_attr "type" "fcmov")]) 2817 1.1 mrg 2818 1.1 mrg (define_expand "smaxdf3" 2819 1.1 mrg [(set (match_dup 3) 2820 1.1 mrg (le:DF (match_operand:DF 1 "reg_or_0_operand") 2821 1.1 mrg (match_operand:DF 2 "reg_or_0_operand"))) 2822 1.1.1.2 mrg (set (match_operand:DF 0 "register_operand") 2823 1.1.1.2 mrg (if_then_else:DF (eq (match_dup 3) (match_dup 4)) 2824 1.1.1.2 mrg (match_dup 1) (match_dup 2)))] 2825 1.1 mrg "TARGET_FP" 2826 1.1 mrg { 2827 1.1 mrg operands[3] = gen_reg_rtx (DFmode); 2828 1.1 mrg operands[4] = CONST0_RTX (DFmode); 2829 1.1 mrg }) 2830 1.1 mrg 2831 1.1 mrg (define_expand "smindf3" 2832 1.1 mrg [(set (match_dup 3) 2833 1.1 mrg (lt:DF (match_operand:DF 1 "reg_or_0_operand") 2834 1.1 mrg (match_operand:DF 2 "reg_or_0_operand"))) 2835 1.1.1.2 mrg (set (match_operand:DF 0 "register_operand") 2836 1.1.1.2 mrg (if_then_else:DF (ne (match_dup 3) (match_dup 4)) 2837 1.1.1.2 mrg (match_dup 1) (match_dup 2)))] 2838 1.1 mrg "TARGET_FP" 2839 1.1 mrg { 2840 1.1 mrg operands[3] = gen_reg_rtx (DFmode); 2841 1.1 mrg operands[4] = CONST0_RTX (DFmode); 2842 1.1 mrg }) 2843 1.1 mrg 2844 1.1 mrg (define_expand "smaxsf3" 2845 1.1 mrg [(set (match_dup 3) 2846 1.1 mrg (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand")) 2847 1.1 mrg (float_extend:DF (match_operand:SF 2 "reg_or_0_operand")))) 2848 1.1.1.2 mrg (set (match_operand:SF 0 "register_operand") 2849 1.1.1.2 mrg (if_then_else:SF (eq (match_dup 3) (match_dup 4)) 2850 1.1.1.2 mrg (match_dup 1) (match_dup 2)))] 2851 1.1 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2852 1.1 mrg { 2853 1.1 mrg operands[3] = gen_reg_rtx (DFmode); 2854 1.1 mrg operands[4] = CONST0_RTX (DFmode); 2855 1.1 mrg }) 2856 1.1 mrg 2857 1.1 mrg (define_expand "sminsf3" 2858 1.1 mrg [(set (match_dup 3) 2859 1.1 mrg (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand")) 2860 1.1 mrg (float_extend:DF (match_operand:SF 2 "reg_or_0_operand")))) 2861 1.1 mrg (set (match_operand:SF 0 "register_operand") 2862 1.1 mrg (if_then_else:SF (ne (match_dup 3) (match_dup 4)) 2863 1.1 mrg (match_dup 1) (match_dup 2)))] 2864 1.1 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2865 1.1.1.2 mrg { 2866 1.1 mrg operands[3] = gen_reg_rtx (DFmode); 2867 1.1 mrg operands[4] = CONST0_RTX (DFmode); 2868 1.1 mrg }) 2869 1.1 mrg 2870 1.1 mrg (define_insn "*fbcc_normal" 2871 1.1 mrg [(set (pc) 2872 1.1 mrg (if_then_else 2873 1.1 mrg (match_operator 1 "signed_comparison_operator" 2874 1.1 mrg [(match_operand:DF 2 "reg_or_0_operand" "fG") 2875 1.1 mrg (match_operand:DF 3 "const0_operand" "G")]) 2876 1.1 mrg (label_ref (match_operand 0)) 2877 1.1 mrg (pc)))] 2878 1.1.1.2 mrg "TARGET_FP" 2879 1.1 mrg "fb%C1 %R2,%0" 2880 1.1 mrg [(set_attr "type" "fbr")]) 2881 1.1 mrg 2882 1.1 mrg (define_insn "*fbcc_ext_normal" 2883 1.1 mrg [(set (pc) 2884 1.1 mrg (if_then_else 2885 1.1 mrg (match_operator 1 "signed_comparison_operator" 2886 1.1 mrg [(float_extend:DF 2887 1.1 mrg (match_operand:SF 2 "reg_or_0_operand" "fG")) 2888 1.1 mrg (match_operand:DF 3 "const0_operand" "G")]) 2889 1.1.1.2 mrg (label_ref (match_operand 0)) 2890 1.1.1.2 mrg (pc)))] 2891 1.1.1.2 mrg "TARGET_FP" 2892 1.1 mrg "fb%C1 %R2,%0" 2893 1.1.1.2 mrg [(set_attr "type" "fbr")]) 2894 1.1 mrg 2896 1.1 mrg ;; These are the main define_expand's used to make conditional branches 2897 1.1 mrg ;; and compares. 2898 1.1 mrg 2899 1.1.1.2 mrg (define_expand "cbranchdf4" 2900 1.1 mrg [(use (match_operator 0 "alpha_cbranch_operator" 2901 1.1.1.2 mrg [(match_operand:DF 1 "reg_or_0_operand") 2902 1.1 mrg (match_operand:DF 2 "reg_or_0_operand")])) 2903 1.1 mrg (use (match_operand 3))] 2904 1.1 mrg "TARGET_FP" 2905 1.1.1.4 mrg "alpha_emit_conditional_branch (operands, DFmode); DONE;") 2906 1.1.1.4 mrg 2907 1.1.1.2 mrg (define_expand "cbranchtf4" 2908 1.1 mrg [(use (match_operator 0 "alpha_cbranch_operator" 2909 1.1.1.2 mrg [(match_operand:TF 1 "general_operand") 2910 1.1 mrg (match_operand:TF 2 "general_operand")])) 2911 1.1 mrg (use (match_operand 3))] 2912 1.1 mrg "TARGET_HAS_XFLOATING_LIBS" 2913 1.1 mrg "alpha_emit_conditional_branch (operands, TFmode); DONE;") 2914 1.1 mrg 2915 1.1 mrg (define_expand "cbranchdi4" 2916 1.1 mrg [(use (match_operator 0 "alpha_cbranch_operator" 2917 1.1.1.2 mrg [(match_operand:DI 1 "general_operand") 2918 1.1.1.2 mrg (match_operand:DI 2 "general_operand")])) 2919 1.1.1.2 mrg (use (match_operand 3))] 2920 1.1.1.2 mrg "" 2921 1.1.1.2 mrg "alpha_emit_conditional_branch (operands, DImode); DONE;") 2922 1.1.1.2 mrg 2923 1.1 mrg (define_expand "cstoredf4" 2924 1.1 mrg [(use (match_operator:DI 1 "alpha_cbranch_operator" 2925 1.1 mrg [(match_operand:DF 2 "reg_or_0_operand") 2926 1.1 mrg (match_operand:DF 3 "reg_or_0_operand")])) 2927 1.1 mrg (clobber (match_operand:DI 0 "register_operand"))] 2928 1.1 mrg "TARGET_FP" 2929 1.1 mrg { 2930 1.1.1.2 mrg if (alpha_emit_setcc (operands, DFmode)) 2931 1.1.1.2 mrg DONE; 2932 1.1.1.2 mrg else 2933 1.1.1.2 mrg FAIL; 2934 1.1.1.2 mrg }) 2935 1.1.1.2 mrg 2936 1.1 mrg (define_expand "cstoretf4" 2937 1.1 mrg [(use (match_operator:DI 1 "alpha_cbranch_operator" 2938 1.1 mrg [(match_operand:TF 2 "general_operand") 2939 1.1.1.4 mrg (match_operand:TF 3 "general_operand")])) 2940 1.1.1.4 mrg (clobber (match_operand:DI 0 "register_operand"))] 2941 1.1.1.2 mrg "TARGET_HAS_XFLOATING_LIBS" 2942 1.1 mrg { 2943 1.1 mrg if (alpha_emit_setcc (operands, TFmode)) 2944 1.1.1.2 mrg DONE; 2945 1.1.1.2 mrg else 2946 1.1.1.2 mrg FAIL; 2947 1.1 mrg }) 2948 1.1 mrg 2949 1.1.1.2 mrg (define_expand "cstoredi4" 2950 1.1.1.2 mrg [(use (match_operator:DI 1 "alpha_cbranch_operator" 2951 1.1 mrg [(match_operand:DI 2 "general_operand") 2952 1.1.1.2 mrg (match_operand:DI 3 "general_operand")])) 2953 1.1.1.2 mrg (clobber (match_operand:DI 0 "register_operand"))] 2954 1.1.1.2 mrg "" 2955 1.1.1.2 mrg { 2956 1.1.1.2 mrg if (alpha_emit_setcc (operands, DImode)) 2957 1.1.1.2 mrg DONE; 2958 1.1 mrg else 2959 1.1 mrg FAIL; 2960 1.1.1.2 mrg }) 2961 1.1.1.2 mrg 2963 1.1 mrg ;; These are the main define_expand's used to make conditional moves. 2964 1.1 mrg 2965 1.1.1.2 mrg (define_expand "mov<mode>cc" 2966 1.1.1.2 mrg [(set (match_operand:I48MODE 0 "register_operand") 2967 1.1.1.2 mrg (if_then_else:I48MODE 2968 1.1.1.2 mrg (match_operand 1 "comparison_operator") 2969 1.1.1.2 mrg (match_operand:I48MODE 2 "reg_or_8bit_operand") 2970 1.1.1.2 mrg (match_operand:I48MODE 3 "reg_or_8bit_operand")))] 2971 1.1 mrg "" 2972 1.1 mrg { 2973 1.1.1.2 mrg operands[1] = alpha_emit_conditional_move (operands[1], <MODE>mode); 2974 1.1.1.2 mrg if (operands[1] == 0) 2975 1.1 mrg FAIL; 2976 1.1 mrg }) 2977 1.1 mrg 2978 1.1 mrg (define_expand "mov<mode>cc" 2979 1.1 mrg [(set (match_operand:FMODE 0 "register_operand") 2980 1.1 mrg (if_then_else:FMODE 2981 1.1 mrg (match_operand 1 "comparison_operator") 2982 1.1 mrg (match_operand:FMODE 2 "reg_or_8bit_operand") 2983 1.1 mrg (match_operand:FMODE 3 "reg_or_8bit_operand")))] 2984 1.1 mrg "" 2985 1.1 mrg { 2986 1.1 mrg operands[1] = alpha_emit_conditional_move (operands[1], <MODE>mode); 2987 1.1 mrg if (operands[1] == 0) 2988 1.1 mrg FAIL; 2989 1.1 mrg }) 2990 1.1 mrg 2992 1.1 mrg ;; These define_split definitions are used in cases when comparisons have 2993 1.1 mrg ;; not be stated in the correct way and we need to reverse the second 2994 1.1 mrg ;; comparison. For example, x >= 7 has to be done as x < 6 with the 2995 1.1 mrg ;; comparison that tests the result being reversed. We have one define_split 2996 1.1.1.2 mrg ;; for each use of a comparison. They do not match valid insns and need 2997 1.1 mrg ;; not generate valid insns. 2998 1.1 mrg ;; 2999 1.1.1.2 mrg ;; We can also handle equality comparisons (and inequality comparisons in 3000 1.1.1.2 mrg ;; cases where the resulting add cannot overflow) by doing an add followed by 3001 1.1.1.2 mrg ;; a comparison with zero. This is faster since the addition takes one 3002 1.1.1.2 mrg ;; less cycle than a compare when feeding into a conditional move. 3003 1.1.1.2 mrg ;; For this case, we also have an SImode pattern since we can merge the add 3004 1.1 mrg ;; and sign extend and the order doesn't matter. 3005 1.1 mrg ;; 3006 1.1 mrg ;; We do not do this for floating-point, since it isn't clear how the "wrong" 3007 1.1 mrg ;; operation could have been generated. 3008 1.1 mrg 3009 1.1 mrg (define_split 3010 1.1 mrg [(set (match_operand:DI 0 "register_operand") 3011 1.1 mrg (if_then_else:DI 3012 1.1 mrg (match_operator 1 "comparison_operator" 3013 1.1 mrg [(match_operand:DI 2 "reg_or_0_operand") 3014 1.1 mrg (match_operand:DI 3 "reg_or_cint_operand")]) 3015 1.1 mrg (match_operand:DI 4 "reg_or_cint_operand") 3016 1.1 mrg (match_operand:DI 5 "reg_or_cint_operand"))) 3017 1.1 mrg (clobber (match_operand:DI 6 "register_operand"))] 3018 1.1 mrg "operands[3] != const0_rtx" 3019 1.1 mrg [(set (match_dup 6) (match_dup 7)) 3020 1.1 mrg (set (match_dup 0) 3021 1.1 mrg (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))] 3022 1.1 mrg { 3023 1.1 mrg enum rtx_code code = GET_CODE (operands[1]); 3024 1.1 mrg int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU); 3025 1.1 mrg 3026 1.1 mrg /* If we are comparing for equality with a constant and that constant 3027 1.1 mrg appears in the arm when the register equals the constant, use the 3028 1.1 mrg register since that is more likely to match (and to produce better code 3029 1.1 mrg if both would). */ 3030 1.1 mrg 3031 1.1 mrg if (code == EQ && CONST_INT_P (operands[3]) 3032 1.1 mrg && rtx_equal_p (operands[4], operands[3])) 3033 1.1 mrg operands[4] = operands[2]; 3034 1.1 mrg 3035 1.1 mrg else if (code == NE && CONST_INT_P (operands[3]) 3036 1.1 mrg && rtx_equal_p (operands[5], operands[3])) 3037 1.1 mrg operands[5] = operands[2]; 3038 1.1 mrg 3039 1.1 mrg if (code == NE || code == EQ 3040 1.1 mrg || (extended_count (operands[2], DImode, unsignedp) >= 1 3041 1.1 mrg && extended_count (operands[3], DImode, unsignedp) >= 1)) 3042 1.1 mrg { 3043 1.1 mrg if (CONST_INT_P (operands[3])) 3044 1.1 mrg operands[7] = gen_rtx_PLUS (DImode, operands[2], 3045 1.1 mrg GEN_INT (- INTVAL (operands[3]))); 3046 1.1 mrg else 3047 1.1 mrg operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]); 3048 1.1 mrg 3049 1.1 mrg operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx); 3050 1.1 mrg } 3051 1.1 mrg 3052 1.1 mrg else if (code == EQ || code == LE || code == LT 3053 1.1.1.2 mrg || code == LEU || code == LTU) 3054 1.1 mrg { 3055 1.1 mrg operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]); 3056 1.1.1.2 mrg operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx); 3057 1.1.1.2 mrg } 3058 1.1.1.2 mrg else 3059 1.1.1.2 mrg { 3060 1.1.1.2 mrg operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode, 3061 1.1 mrg operands[2], operands[3]); 3062 1.1 mrg operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx); 3063 1.1 mrg } 3064 1.1 mrg }) 3065 1.1 mrg 3066 1.1 mrg (define_split 3067 1.1 mrg [(set (match_operand:DI 0 "register_operand") 3068 1.1 mrg (if_then_else:DI 3069 1.1 mrg (match_operator 1 "comparison_operator" 3070 1.1 mrg [(match_operand:SI 2 "reg_or_0_operand") 3071 1.1 mrg (match_operand:SI 3 "reg_or_cint_operand")]) 3072 1.1 mrg (match_operand:DI 4 "reg_or_8bit_operand") 3073 1.1 mrg (match_operand:DI 5 "reg_or_8bit_operand"))) 3074 1.1 mrg (clobber (match_operand:DI 6 "register_operand"))] 3075 1.1 mrg "operands[3] != const0_rtx 3076 1.1 mrg && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)" 3077 1.1 mrg [(set (match_dup 6) (match_dup 7)) 3078 1.1 mrg (set (match_dup 0) 3079 1.1 mrg (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))] 3080 1.1 mrg { 3081 1.1 mrg enum rtx_code code = GET_CODE (operands[1]); 3082 1.1 mrg int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU); 3083 1.1 mrg rtx tem; 3084 1.1 mrg 3085 1.1 mrg if ((code != NE && code != EQ 3086 1.1 mrg && ! (extended_count (operands[2], DImode, unsignedp) >= 1 3087 1.1 mrg && extended_count (operands[3], DImode, unsignedp) >= 1))) 3088 1.1 mrg FAIL; 3089 1.1 mrg 3090 1.1.1.2 mrg if (CONST_INT_P (operands[3])) 3091 1.1 mrg tem = gen_rtx_PLUS (SImode, operands[2], 3092 1.1.1.2 mrg GEN_INT (- INTVAL (operands[3]))); 3093 1.1 mrg else 3094 1.1.1.2 mrg tem = gen_rtx_MINUS (SImode, operands[2], operands[3]); 3095 1.1.1.2 mrg 3096 1.1 mrg operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem); 3097 1.1 mrg operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode, 3098 1.1 mrg operands[6], const0_rtx); 3099 1.1 mrg }) 3100 1.1 mrg 3101 1.1 mrg ;; Prefer to use cmp and arithmetic when possible instead of a cmove. 3102 1.1 mrg 3103 1.1 mrg (define_split 3104 1.1 mrg [(set (match_operand 0 "register_operand") 3105 1.1 mrg (if_then_else (match_operator 1 "signed_comparison_operator" 3106 1.1 mrg [(match_operand:DI 2 "reg_or_0_operand") 3107 1.1 mrg (const_int 0)]) 3108 1.1 mrg (match_operand 3 "const_int_operand") 3109 1.1.1.2 mrg (match_operand 4 "const_int_operand")))] 3110 1.1 mrg "" 3111 1.1 mrg [(const_int 0)] 3112 1.1.1.2 mrg { 3113 1.1.1.2 mrg if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0], 3114 1.1.1.2 mrg operands[2], operands[3], operands[4])) 3115 1.1 mrg DONE; 3116 1.1 mrg else 3117 1.1 mrg FAIL; 3118 1.1 mrg }) 3119 1.1 mrg 3120 1.1 mrg ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know. 3121 1.1 mrg ;; Oh well, we match it in movcc, so it must be partially our fault. 3122 1.1 mrg (define_split 3123 1.1 mrg [(set (match_operand 0 "register_operand") 3124 1.1 mrg (if_then_else (match_operator 1 "signed_comparison_operator" 3125 1.1 mrg [(const_int 0) 3126 1.1 mrg (match_operand:DI 2 "reg_or_0_operand")]) 3127 1.1 mrg (match_operand 3 "const_int_operand") 3128 1.1 mrg (match_operand 4 "const_int_operand")))] 3129 1.1 mrg "" 3130 1.1 mrg [(const_int 0)] 3131 1.1 mrg { 3132 1.1 mrg if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])), 3133 1.1 mrg operands[0], operands[2], operands[3], 3134 1.1 mrg operands[4])) 3135 1.1 mrg DONE; 3136 1.1 mrg else 3137 1.1 mrg FAIL; 3138 1.1 mrg }) 3139 1.1 mrg 3140 1.1 mrg (define_insn_and_split "*cmp_sadd_di" 3141 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 3142 1.1 mrg (plus:DI (if_then_else:DI 3143 1.1 mrg (match_operator 1 "alpha_zero_comparison_operator" 3144 1.1 mrg [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3145 1.1 mrg (const_int 0)]) 3146 1.1 mrg (match_operand:DI 3 "const48_operand" "I") 3147 1.1 mrg (const_int 0)) 3148 1.1 mrg (match_operand:DI 4 "sext_add_operand" "rIO"))) 3149 1.1 mrg (clobber (match_scratch:DI 5 "=r"))] 3150 1.1 mrg "" 3151 1.1 mrg "#" 3152 1.1 mrg "" 3153 1.1 mrg [(set (match_dup 5) 3154 1.1 mrg (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3155 1.1 mrg (set (match_dup 0) 3156 1.1 mrg (plus:DI (mult:DI (match_dup 5) (match_dup 3)) 3157 1.1 mrg (match_dup 4)))] 3158 1.1 mrg { 3159 1.1 mrg if (can_create_pseudo_p ()) 3160 1.1 mrg operands[5] = gen_reg_rtx (DImode); 3161 1.1 mrg else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3162 1.1 mrg operands[5] = operands[0]; 3163 1.1 mrg }) 3164 1.1 mrg 3165 1.1 mrg (define_insn_and_split "*cmp_sadd_si" 3166 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=r") 3167 1.1 mrg (plus:SI (if_then_else:SI 3168 1.1 mrg (match_operator 1 "alpha_zero_comparison_operator" 3169 1.1 mrg [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3170 1.1 mrg (const_int 0)]) 3171 1.1 mrg (match_operand:SI 3 "const48_operand" "I") 3172 1.1 mrg (const_int 0)) 3173 1.1 mrg (match_operand:SI 4 "sext_add_operand" "rIO"))) 3174 1.1 mrg (clobber (match_scratch:DI 5 "=r"))] 3175 1.1 mrg "" 3176 1.1 mrg "#" 3177 1.1 mrg "" 3178 1.1 mrg [(set (match_dup 5) 3179 1.1 mrg (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3180 1.1 mrg (set (match_dup 0) 3181 1.1 mrg (plus:SI (mult:SI (match_dup 6) (match_dup 3)) 3182 1.1 mrg (match_dup 4)))] 3183 1.1 mrg { 3184 1.1 mrg if (can_create_pseudo_p ()) 3185 1.1 mrg operands[5] = gen_reg_rtx (DImode); 3186 1.1 mrg else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3187 1.1 mrg operands[5] = gen_lowpart (DImode, operands[0]); 3188 1.1 mrg 3189 1.1 mrg operands[6] = gen_lowpart (SImode, operands[5]); 3190 1.1 mrg }) 3191 1.1 mrg 3192 1.1 mrg (define_insn_and_split "*cmp_sadd_sidi" 3193 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 3194 1.1 mrg (sign_extend:DI 3195 1.1 mrg (plus:SI (if_then_else:SI 3196 1.1 mrg (match_operator 1 "alpha_zero_comparison_operator" 3197 1.1 mrg [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3198 1.1 mrg (const_int 0)]) 3199 1.1 mrg (match_operand:SI 3 "const48_operand" "I") 3200 1.1 mrg (const_int 0)) 3201 1.1 mrg (match_operand:SI 4 "sext_add_operand" "rIO")))) 3202 1.1 mrg (clobber (match_scratch:DI 5 "=r"))] 3203 1.1 mrg "" 3204 1.1 mrg "#" 3205 1.1 mrg "" 3206 1.1 mrg [(set (match_dup 5) 3207 1.1 mrg (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3208 1.1 mrg (set (match_dup 0) 3209 1.1 mrg (sign_extend:DI (plus:SI (mult:SI (match_dup 6) (match_dup 3)) 3210 1.1 mrg (match_dup 4))))] 3211 1.1 mrg { 3212 1.1 mrg if (can_create_pseudo_p ()) 3213 1.1 mrg operands[5] = gen_reg_rtx (DImode); 3214 1.1 mrg else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3215 1.1 mrg operands[5] = operands[0]; 3216 1.1 mrg 3217 1.1 mrg operands[6] = gen_lowpart (SImode, operands[5]); 3218 1.1 mrg }) 3219 1.1 mrg 3220 1.1 mrg (define_insn_and_split "*cmp_ssub_di" 3221 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 3222 1.1 mrg (minus:DI (if_then_else:DI 3223 1.1 mrg (match_operator 1 "alpha_zero_comparison_operator" 3224 1.1 mrg [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3225 1.1 mrg (const_int 0)]) 3226 1.1 mrg (match_operand:DI 3 "const48_operand" "I") 3227 1.1 mrg (const_int 0)) 3228 1.1 mrg (match_operand:DI 4 "reg_or_8bit_operand" "rI"))) 3229 1.1 mrg (clobber (match_scratch:DI 5 "=r"))] 3230 1.1 mrg "" 3231 1.1 mrg "#" 3232 1.1 mrg "" 3233 1.1 mrg [(set (match_dup 5) 3234 1.1 mrg (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3235 1.1 mrg (set (match_dup 0) 3236 1.1 mrg (minus:DI (mult:DI (match_dup 5) (match_dup 3)) 3237 1.1 mrg (match_dup 4)))] 3238 1.1 mrg { 3239 1.1 mrg if (can_create_pseudo_p ()) 3240 1.1 mrg operands[5] = gen_reg_rtx (DImode); 3241 1.1 mrg else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3242 1.1 mrg operands[5] = operands[0]; 3243 1.1 mrg }) 3244 1.1 mrg 3245 1.1 mrg (define_insn_and_split "*cmp_ssub_si" 3246 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=r") 3247 1.1 mrg (minus:SI (if_then_else:SI 3248 1.1 mrg (match_operator 1 "alpha_zero_comparison_operator" 3249 1.1 mrg [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3250 1.1 mrg (const_int 0)]) 3251 1.1 mrg (match_operand:SI 3 "const48_operand" "I") 3252 1.1 mrg (const_int 0)) 3253 1.1 mrg (match_operand:SI 4 "reg_or_8bit_operand" "rI"))) 3254 1.1 mrg (clobber (match_scratch:DI 5 "=r"))] 3255 1.1 mrg "" 3256 1.1 mrg "#" 3257 1.1 mrg "" 3258 1.1 mrg [(set (match_dup 5) 3259 1.1 mrg (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3260 1.1 mrg (set (match_dup 0) 3261 1.1 mrg (minus:SI (mult:SI (match_dup 6) (match_dup 3)) 3262 1.1 mrg (match_dup 4)))] 3263 1.1 mrg { 3264 1.1 mrg if (can_create_pseudo_p ()) 3265 1.1 mrg operands[5] = gen_reg_rtx (DImode); 3266 1.1 mrg else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3267 1.1 mrg operands[5] = gen_lowpart (DImode, operands[0]); 3268 1.1 mrg 3269 1.1 mrg operands[6] = gen_lowpart (SImode, operands[5]); 3270 1.1 mrg }) 3271 1.1 mrg 3272 1.1 mrg (define_insn_and_split "*cmp_ssub_sidi" 3273 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 3274 1.1 mrg (sign_extend:DI 3275 1.1 mrg (minus:SI (if_then_else:SI 3276 1.1 mrg (match_operator 1 "alpha_zero_comparison_operator" 3277 1.1 mrg [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3278 1.1 mrg (const_int 0)]) 3279 1.1 mrg (match_operand:SI 3 "const48_operand" "I") 3280 1.1 mrg (const_int 0)) 3281 1.1 mrg (match_operand:SI 4 "reg_or_8bit_operand" "rI")))) 3282 1.1 mrg (clobber (match_scratch:DI 5 "=r"))] 3283 1.1 mrg "" 3284 1.1 mrg "#" 3285 1.1 mrg "" 3286 1.1 mrg [(set (match_dup 5) 3287 1.1 mrg (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3288 1.1 mrg (set (match_dup 0) 3289 1.1 mrg (sign_extend:DI (minus:SI (mult:SI (match_dup 6) (match_dup 3)) 3290 1.1.1.2 mrg (match_dup 4))))] 3291 1.1.1.2 mrg { 3292 1.1.1.2 mrg if (can_create_pseudo_p ()) 3293 1.1.1.2 mrg operands[5] = gen_reg_rtx (DImode); 3294 1.1 mrg else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3295 1.1 mrg operands[5] = operands[0]; 3296 1.1.1.2 mrg 3297 1.1 mrg operands[6] = gen_lowpart (SImode, operands[5]); 3298 1.1 mrg }) 3299 1.1 mrg 3301 1.1 mrg ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF 3302 1.1 mrg ;; work differently, so we have different patterns for each. 3303 1.1 mrg 3304 1.1.1.2 mrg (define_expand "call" 3305 1.1.1.2 mrg [(use (match_operand:DI 0)) 3306 1.1 mrg (use (match_operand 1)) 3307 1.1 mrg (use (match_operand 2)) 3308 1.1 mrg (use (match_operand 3))] 3309 1.1 mrg "" 3310 1.1 mrg { 3311 1.1 mrg if (TARGET_ABI_OPEN_VMS) 3312 1.1 mrg emit_call_insn (gen_call_vms (operands[0], operands[2])); 3313 1.1 mrg else 3314 1.1.1.2 mrg emit_call_insn (gen_call_osf (operands[0], operands[1])); 3315 1.1.1.2 mrg DONE; 3316 1.1 mrg }) 3317 1.1 mrg 3318 1.1 mrg (define_expand "sibcall" 3319 1.1 mrg [(parallel [(call (mem:DI (match_operand 0)) 3320 1.1 mrg (match_operand 1)) 3321 1.1 mrg (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])] 3322 1.1 mrg "TARGET_ABI_OSF" 3323 1.1 mrg { 3324 1.1 mrg gcc_assert (MEM_P (operands[0])); 3325 1.1 mrg operands[0] = XEXP (operands[0], 0); 3326 1.1 mrg }) 3327 1.1 mrg 3328 1.1 mrg (define_expand "call_osf" 3329 1.1 mrg [(parallel [(call (mem:DI (match_operand 0)) 3330 1.1 mrg (match_operand 1)) 3331 1.1 mrg (use (reg:DI 29)) 3332 1.1 mrg (clobber (reg:DI 26))])] 3333 1.1.1.2 mrg "" 3334 1.1.1.2 mrg { 3335 1.1 mrg gcc_assert (MEM_P (operands[0])); 3336 1.1 mrg 3337 1.1 mrg operands[0] = XEXP (operands[0], 0); 3338 1.1 mrg if (! call_operand (operands[0], Pmode)) 3339 1.1 mrg operands[0] = copy_to_mode_reg (Pmode, operands[0]); 3340 1.1 mrg }) 3341 1.1 mrg 3342 1.1 mrg ;; 3343 1.1 mrg ;; call openvms/alpha 3344 1.1 mrg ;; op 0: symbol ref for called function 3345 1.1 mrg ;; op 1: next_arg_reg (argument information value for R25) 3346 1.1 mrg ;; 3347 1.1 mrg (define_expand "call_vms" 3348 1.1 mrg [(parallel [(call (mem:DI (match_operand 0)) 3349 1.1 mrg (match_operand 1)) 3350 1.1 mrg (use (match_dup 2)) 3351 1.1 mrg (use (reg:DI 25)) 3352 1.1 mrg (use (reg:DI 26)) 3353 1.1 mrg (clobber (reg:DI 27))])] 3354 1.1 mrg "" 3355 1.1 mrg { 3356 1.1 mrg gcc_assert (MEM_P (operands[0])); 3357 1.1.1.2 mrg 3358 1.1.1.2 mrg operands[0] = XEXP (operands[0], 0); 3359 1.1 mrg 3360 1.1 mrg /* Always load AI with argument information, then handle symbolic and 3361 1.1 mrg indirect call differently. Load RA and set operands[2] to PV in 3362 1.1 mrg both cases. */ 3363 1.1 mrg 3364 1.1.1.2 mrg emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]); 3365 1.1.1.2 mrg if (GET_CODE (operands[0]) == SYMBOL_REF) 3366 1.1.1.2 mrg { 3367 1.1.1.2 mrg operands[2] = const0_rtx; 3368 1.1.1.2 mrg } 3369 1.1 mrg else 3370 1.1 mrg { 3371 1.1.1.2 mrg emit_move_insn (gen_rtx_REG (Pmode, 26), 3372 1.1 mrg gen_rtx_MEM (Pmode, plus_constant (Pmode, 3373 1.1 mrg operands[0], 8))); 3374 1.1 mrg operands[2] = operands[0]; 3375 1.1 mrg } 3376 1.1 mrg }) 3377 1.1 mrg 3378 1.1 mrg (define_expand "call_value" 3379 1.1 mrg [(use (match_operand 0)) 3380 1.1 mrg (use (match_operand:DI 1)) 3381 1.1.1.2 mrg (use (match_operand 2)) 3382 1.1.1.2 mrg (use (match_operand 3)) 3383 1.1.1.2 mrg (use (match_operand 4))] 3384 1.1 mrg "" 3385 1.1 mrg { 3386 1.1 mrg if (TARGET_ABI_OPEN_VMS) 3387 1.1 mrg emit_call_insn (gen_call_value_vms (operands[0], operands[1], 3388 1.1 mrg operands[3])); 3389 1.1 mrg else 3390 1.1 mrg emit_call_insn (gen_call_value_osf (operands[0], operands[1], 3391 1.1 mrg operands[2])); 3392 1.1.1.2 mrg DONE; 3393 1.1.1.2 mrg }) 3394 1.1.1.2 mrg 3395 1.1 mrg (define_expand "sibcall_value" 3396 1.1 mrg [(parallel [(set (match_operand 0) 3397 1.1 mrg (call (mem:DI (match_operand 1)) 3398 1.1 mrg (match_operand 2))) 3399 1.1 mrg (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])] 3400 1.1 mrg "TARGET_ABI_OSF" 3401 1.1 mrg { 3402 1.1 mrg gcc_assert (MEM_P (operands[1])); 3403 1.1 mrg operands[1] = XEXP (operands[1], 0); 3404 1.1 mrg }) 3405 1.1 mrg 3406 1.1 mrg (define_expand "call_value_osf" 3407 1.1.1.2 mrg [(parallel [(set (match_operand 0) 3408 1.1.1.2 mrg (call (mem:DI (match_operand 1)) 3409 1.1.1.2 mrg (match_operand 2))) 3410 1.1 mrg (use (reg:DI 29)) 3411 1.1 mrg (clobber (reg:DI 26))])] 3412 1.1 mrg "" 3413 1.1 mrg { 3414 1.1 mrg gcc_assert (MEM_P (operands[1])); 3415 1.1 mrg 3416 1.1 mrg operands[1] = XEXP (operands[1], 0); 3417 1.1 mrg if (! call_operand (operands[1], Pmode)) 3418 1.1 mrg operands[1] = copy_to_mode_reg (Pmode, operands[1]); 3419 1.1 mrg }) 3420 1.1 mrg 3421 1.1 mrg (define_expand "call_value_vms" 3422 1.1 mrg [(parallel [(set (match_operand 0) 3423 1.1 mrg (call (mem:DI (match_operand:DI 1)) 3424 1.1 mrg (match_operand 2))) 3425 1.1 mrg (use (match_dup 3)) 3426 1.1 mrg (use (reg:DI 25)) 3427 1.1 mrg (use (reg:DI 26)) 3428 1.1 mrg (clobber (reg:DI 27))])] 3429 1.1 mrg "" 3430 1.1 mrg { 3431 1.1 mrg gcc_assert (MEM_P (operands[1])); 3432 1.1.1.2 mrg 3433 1.1.1.2 mrg operands[1] = XEXP (operands[1], 0); 3434 1.1 mrg 3435 1.1 mrg /* Always load AI with argument information, then handle symbolic and 3436 1.1 mrg indirect call differently. Load RA and set operands[3] to PV in 3437 1.1 mrg both cases. */ 3438 1.1 mrg 3439 1.1 mrg emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]); 3440 1.1.1.2 mrg if (GET_CODE (operands[1]) == SYMBOL_REF) 3441 1.1 mrg { 3442 1.1 mrg operands[3] = const0_rtx; 3443 1.1 mrg } 3444 1.1 mrg else 3445 1.1 mrg { 3446 1.1 mrg emit_move_insn (gen_rtx_REG (Pmode, 26), 3447 1.1 mrg gen_rtx_MEM (Pmode, plus_constant (Pmode, 3448 1.1 mrg operands[1], 8))); 3449 1.1 mrg operands[3] = operands[1]; 3450 1.1 mrg } 3451 1.1 mrg }) 3452 1.1 mrg 3453 1.1 mrg (define_insn "*call_osf_1_er_noreturn" 3454 1.1.1.2 mrg [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) 3455 1.1 mrg (match_operand 1)) 3456 1.1 mrg (use (reg:DI 29)) 3457 1.1 mrg (clobber (reg:DI 26))] 3458 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF 3459 1.1 mrg && find_reg_note (insn, REG_NORETURN, NULL_RTX)" 3460 1.1 mrg "@ 3461 1.1 mrg jsr $26,($27),0 3462 1.1 mrg bsr $26,%0\t\t!samegp 3463 1.1 mrg ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#" 3464 1.1 mrg [(set_attr "type" "jsr") 3465 1.1 mrg (set_attr "length" "*,*,8")]) 3466 1.1 mrg 3467 1.1 mrg (define_insn "*call_osf_1_er" 3468 1.1.1.2 mrg [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) 3469 1.1.1.2 mrg (match_operand 1)) 3470 1.1 mrg (use (reg:DI 29)) 3471 1.1 mrg (clobber (reg:DI 26))] 3472 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3473 1.1 mrg "@ 3474 1.1 mrg jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%* 3475 1.1 mrg bsr $26,%0\t\t!samegp 3476 1.1 mrg ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*" 3477 1.1 mrg [(set_attr "type" "jsr") 3478 1.1 mrg (set_attr "length" "12,*,16")]) 3479 1.1 mrg 3480 1.1 mrg ;; We must use peep2 instead of a split because we need accurate life 3481 1.1 mrg ;; information for $gp. Consider the case of { bar(); while (1); }. 3482 1.1 mrg (define_peephole2 3483 1.1 mrg [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand")) 3484 1.1 mrg (match_operand 1)) 3485 1.1 mrg (use (reg:DI 29)) 3486 1.1 mrg (clobber (reg:DI 26))])] 3487 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed 3488 1.1 mrg && ! samegp_function_operand (operands[0], Pmode) 3489 1.1 mrg && (peep2_regno_dead_p (1, 29) 3490 1.1 mrg || find_reg_note (insn, REG_NORETURN, NULL_RTX))" 3491 1.1 mrg [(parallel [(call (mem:DI (match_dup 2)) 3492 1.1 mrg (match_dup 1)) 3493 1.1 mrg (use (reg:DI 29)) 3494 1.1 mrg (use (match_dup 0)) 3495 1.1 mrg (use (match_dup 3)) 3496 1.1 mrg (clobber (reg:DI 26))])] 3497 1.1 mrg { 3498 1.1 mrg if (CONSTANT_P (operands[0])) 3499 1.1.1.2 mrg { 3500 1.1.1.2 mrg operands[2] = gen_rtx_REG (Pmode, 27); 3501 1.1 mrg operands[3] = GEN_INT (alpha_next_sequence_number++); 3502 1.1 mrg emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx, 3503 1.1 mrg operands[0], operands[3])); 3504 1.1 mrg } 3505 1.1 mrg else 3506 1.1 mrg { 3507 1.1 mrg operands[2] = operands[0]; 3508 1.1 mrg operands[0] = const0_rtx; 3509 1.1 mrg operands[3] = const0_rtx; 3510 1.1 mrg } 3511 1.1 mrg }) 3512 1.1 mrg 3513 1.1 mrg (define_peephole2 3514 1.1 mrg [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand")) 3515 1.1 mrg (match_operand 1)) 3516 1.1 mrg (use (reg:DI 29)) 3517 1.1 mrg (clobber (reg:DI 26))])] 3518 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed 3519 1.1 mrg && ! samegp_function_operand (operands[0], Pmode) 3520 1.1 mrg && ! (peep2_regno_dead_p (1, 29) 3521 1.1 mrg || find_reg_note (insn, REG_NORETURN, NULL_RTX))" 3522 1.1 mrg [(parallel [(call (mem:DI (match_dup 2)) 3523 1.1 mrg (match_dup 1)) 3524 1.1 mrg (set (match_dup 5) 3525 1.1 mrg (unspec:DI [(match_dup 5) (match_dup 3)] UNSPEC_LDGP1)) 3526 1.1 mrg (use (match_dup 0)) 3527 1.1 mrg (use (match_dup 4)) 3528 1.1 mrg (clobber (reg:DI 26))]) 3529 1.1 mrg (set (match_dup 5) 3530 1.1 mrg (unspec:DI [(match_dup 5) (match_dup 3)] UNSPEC_LDGP2))] 3531 1.1 mrg { 3532 1.1 mrg if (CONSTANT_P (operands[0])) 3533 1.1 mrg { 3534 1.1 mrg operands[2] = gen_rtx_REG (Pmode, 27); 3535 1.1 mrg operands[4] = GEN_INT (alpha_next_sequence_number++); 3536 1.1.1.2 mrg emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx, 3537 1.1 mrg operands[0], operands[4])); 3538 1.1.1.2 mrg } 3539 1.1.1.2 mrg else 3540 1.1 mrg { 3541 1.1 mrg operands[2] = operands[0]; 3542 1.1 mrg operands[0] = const0_rtx; 3543 1.1 mrg operands[4] = const0_rtx; 3544 1.1 mrg } 3545 1.1 mrg operands[3] = GEN_INT (alpha_next_sequence_number++); 3546 1.1 mrg operands[5] = pic_offset_table_rtx; 3547 1.1.1.2 mrg }) 3548 1.1 mrg 3549 1.1.1.2 mrg (define_insn "*call_osf_2_er_nogp" 3550 1.1 mrg [(call (mem:DI (match_operand:DI 0 "register_operand" "c")) 3551 1.1.1.2 mrg (match_operand 1)) 3552 1.1.1.2 mrg (use (reg:DI 29)) 3553 1.1 mrg (use (match_operand 2)) 3554 1.1 mrg (use (match_operand 3 "const_int_operand")) 3555 1.1 mrg (clobber (reg:DI 26))] 3556 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3557 1.1 mrg "jsr $26,(%0),%2%J3" 3558 1.1 mrg [(set_attr "type" "jsr")]) 3559 1.1 mrg 3560 1.1 mrg (define_insn "*call_osf_2_er" 3561 1.1 mrg [(call (mem:DI (match_operand:DI 0 "register_operand" "c")) 3562 1.1.1.2 mrg (match_operand 1)) 3563 1.1 mrg (set (reg:DI 29) 3564 1.1 mrg (unspec:DI [(reg:DI 29) (match_operand 4 "const_int_operand")] 3565 1.1 mrg UNSPEC_LDGP1)) 3566 1.1 mrg (use (match_operand 2)) 3567 1.1 mrg (use (match_operand 3 "const_int_operand")) 3568 1.1 mrg (clobber (reg:DI 26))] 3569 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3570 1.1 mrg "jsr $26,(%0),%2%J3\;ldah $29,0($26)\t\t!gpdisp!%4" 3571 1.1 mrg [(set_attr "type" "jsr") 3572 1.1 mrg (set_attr "cannot_copy" "true") 3573 1.1 mrg (set_attr "length" "8")]) 3574 1.1 mrg 3575 1.1 mrg (define_insn "*call_osf_1_noreturn" 3576 1.1.1.2 mrg [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) 3577 1.1 mrg (match_operand 1)) 3578 1.1 mrg (use (reg:DI 29)) 3579 1.1 mrg (clobber (reg:DI 26))] 3580 1.1 mrg "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF 3581 1.1 mrg && find_reg_note (insn, REG_NORETURN, NULL_RTX)" 3582 1.1 mrg "@ 3583 1.1 mrg jsr $26,($27),0 3584 1.1 mrg bsr $26,$%0..ng 3585 1.1 mrg jsr $26,%0" 3586 1.1 mrg [(set_attr "type" "jsr") 3587 1.1 mrg (set_attr "length" "*,*,8")]) 3588 1.1 mrg 3589 1.1.1.2 mrg (define_insn "*call_osf_1" 3590 1.1 mrg [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) 3591 1.1 mrg (match_operand 1)) 3592 1.1 mrg (use (reg:DI 29)) 3593 1.1 mrg (clobber (reg:DI 26))] 3594 1.1 mrg "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3595 1.1 mrg "@ 3596 1.1 mrg jsr $26,($27),0\;ldgp $29,0($26) 3597 1.1 mrg bsr $26,$%0..ng 3598 1.1 mrg jsr $26,%0\;ldgp $29,0($26)" 3599 1.1 mrg [(set_attr "type" "jsr") 3600 1.1 mrg (set_attr "length" "12,*,16")]) 3601 1.1 mrg 3602 1.1.1.2 mrg (define_insn "*sibcall_osf_1_er" 3603 1.1 mrg [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s")) 3604 1.1 mrg (match_operand 1)) 3605 1.1 mrg (unspec [(reg:DI 29)] UNSPEC_SIBCALL)] 3606 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3607 1.1 mrg "@ 3608 1.1 mrg br $31,%0\t\t!samegp 3609 1.1 mrg ldq $27,%0($29)\t\t!literal!%#\;jmp $31,($27),%0\t\t!lituse_jsr!%#" 3610 1.1 mrg [(set_attr "type" "jsr") 3611 1.1 mrg (set_attr "length" "*,8")]) 3612 1.1 mrg 3613 1.1 mrg ;; Note that the DEC assembler expands "jmp foo" with $at, which 3614 1.1 mrg ;; doesn't do what we want. 3615 1.1 mrg (define_insn "*sibcall_osf_1" 3616 1.1.1.2 mrg [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s")) 3617 1.1 mrg (match_operand 1)) 3618 1.1 mrg (unspec [(reg:DI 29)] UNSPEC_SIBCALL)] 3619 1.1 mrg "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3620 1.1 mrg "@ 3621 1.1 mrg br $31,$%0..ng 3622 1.1 mrg lda $27,%0\;jmp $31,($27),%0" 3623 1.1 mrg [(set_attr "type" "jsr") 3624 1.1 mrg (set_attr "length" "*,8")]) 3625 1.1 mrg 3626 1.1 mrg ; GAS relies on the order and position of instructions output below in order 3627 1.1 mrg ; to generate relocs for VMS link to potentially optimize the call. 3628 1.1.1.2 mrg ; Please do not molest. 3629 1.1.1.2 mrg (define_insn "*call_vms_1" 3630 1.1 mrg [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s")) 3631 1.1 mrg (match_operand 1)) 3632 1.1 mrg (use (match_operand:DI 2 "nonmemory_operand" "r,n")) 3633 1.1 mrg (use (reg:DI 25)) 3634 1.1 mrg (use (reg:DI 26)) 3635 1.1 mrg (clobber (reg:DI 27))] 3636 1.1 mrg "TARGET_ABI_OPEN_VMS" 3637 1.1 mrg { 3638 1.1 mrg switch (which_alternative) 3639 1.1 mrg { 3640 1.1 mrg case 0: 3641 1.1.1.2 mrg return "mov %2,$27\;jsr $26,0\;ldq $27,0($29)"; 3642 1.1 mrg case 1: 3643 1.1.1.2 mrg operands [2] = alpha_use_linkage (operands [0], true, false); 3644 1.1.1.2 mrg operands [3] = alpha_use_linkage (operands [0], false, false); 3645 1.1 mrg return "ldq $26,%3\;ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"; 3646 1.1 mrg default: 3647 1.1 mrg gcc_unreachable (); 3648 1.1 mrg } 3649 1.1.1.4 mrg } 3650 1.1 mrg [(set_attr "type" "jsr") 3651 1.1 mrg (set_attr "length" "12,16")]) 3652 1.1 mrg 3653 1.1 mrg ;; Call subroutine returning any type. 3654 1.1 mrg 3655 1.1 mrg (define_expand "untyped_call" 3656 1.1 mrg [(parallel [(call (match_operand 0) 3657 1.1 mrg (const_int 0)) 3658 1.1 mrg (match_operand 1) 3659 1.1 mrg (match_operand 2)])] 3660 1.1 mrg "" 3661 1.1 mrg { 3662 1.1 mrg int i; 3663 1.1 mrg 3664 1.1 mrg emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); 3665 1.1 mrg 3666 1.1 mrg for (i = 0; i < XVECLEN (operands[2], 0); i++) 3667 1.1 mrg { 3668 1.1 mrg rtx set = XVECEXP (operands[2], 0, i); 3669 1.1 mrg emit_move_insn (SET_DEST (set), SET_SRC (set)); 3670 1.1 mrg } 3671 1.1 mrg 3672 1.1 mrg /* The optimizer does not know that the call sets the function value 3673 1.1 mrg registers we stored in the result block. We avoid problems by 3674 1.1 mrg claiming that all hard registers are used and clobbered at this 3675 1.1 mrg point. */ 3676 1.1 mrg emit_insn (gen_blockage ()); 3677 1.1 mrg 3678 1.1.1.2 mrg DONE; 3679 1.1 mrg }) 3680 1.1 mrg 3681 1.1 mrg ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 3682 1.1 mrg ;; all of memory. This blocks insns from being moved across this point. 3683 1.1 mrg 3684 1.1 mrg (define_insn "blockage" 3685 1.1.1.2 mrg [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] 3686 1.1 mrg "" 3687 1.1 mrg "" 3688 1.1 mrg [(set_attr "length" "0") 3689 1.1 mrg (set_attr "type" "none")]) 3690 1.1 mrg 3691 1.1 mrg (define_insn "jump" 3692 1.1 mrg [(set (pc) 3693 1.1 mrg (label_ref (match_operand 0)))] 3694 1.1 mrg "" 3695 1.1 mrg "br $31,%l0" 3696 1.1 mrg [(set_attr "type" "ibr")]) 3697 1.1 mrg 3698 1.1 mrg (define_expand "return" 3699 1.1 mrg [(return)] 3700 1.1 mrg "direct_return ()") 3701 1.1.1.2 mrg 3702 1.1.1.2 mrg (define_insn "*return_internal" 3703 1.1 mrg [(return)] 3704 1.1 mrg "reload_completed" 3705 1.1.1.2 mrg "ret $31,($26),1" 3706 1.1 mrg [(set_attr "type" "ibr")]) 3707 1.1 mrg 3708 1.1 mrg (define_insn "indirect_jump" 3709 1.1 mrg [(set (pc) (match_operand:DI 0 "register_operand" "r"))] 3710 1.1 mrg "" 3711 1.1 mrg "jmp $31,(%0),0" 3712 1.1 mrg [(set_attr "type" "ibr")]) 3713 1.1 mrg 3714 1.1 mrg (define_expand "tablejump" 3715 1.1 mrg [(parallel [(set (pc) 3716 1.1 mrg (match_operand 0 "register_operand")) 3717 1.1.1.2 mrg (use (label_ref:DI (match_operand 1)))])] 3718 1.1 mrg "" 3719 1.1 mrg { 3720 1.1 mrg if (TARGET_ABI_OSF) 3721 1.1 mrg { 3722 1.1 mrg rtx dest = gen_reg_rtx (DImode); 3723 1.1 mrg emit_insn (gen_extendsidi2 (dest, operands[0])); 3724 1.1 mrg emit_insn (gen_adddi3 (dest, pic_offset_table_rtx, dest)); 3725 1.1 mrg operands[0] = dest; 3726 1.1 mrg } 3727 1.1 mrg }) 3728 1.1 mrg 3729 1.1 mrg (define_insn "*tablejump_internal" 3730 1.1.1.2 mrg [(set (pc) 3731 1.1.1.2 mrg (match_operand:DI 0 "register_operand" "r")) 3732 1.1.1.2 mrg (use (label_ref (match_operand 1)))] 3733 1.1.1.2 mrg "" 3734 1.1.1.2 mrg "jmp $31,(%0),0" 3735 1.1.1.2 mrg [(set_attr "type" "ibr")]) 3736 1.1.1.2 mrg 3737 1.1.1.2 mrg ;; Cache flush. Used by alpha_trampoline_init. 0x86 is PAL_imb, but we don't 3738 1.1.1.2 mrg ;; want to have to include pal.h in our .s file. 3739 1.1 mrg (define_insn "imb" 3740 1.1 mrg [(unspec_volatile [(const_int 0)] UNSPECV_IMB)] 3741 1.1.1.3 mrg "" 3742 1.1.1.3 mrg "call_pal 0x86" 3743 1.1.1.2 mrg [(set_attr "type" "callpal")]) 3744 1.1 mrg 3745 1.1 mrg (define_expand "clear_cache" 3746 1.1 mrg [(match_operand:DI 0) ; region start 3747 1.1 mrg (match_operand:DI 1)] ; region end 3748 1.1 mrg "" 3749 1.1 mrg { 3750 1.1.1.2 mrg emit_insn (gen_imb ()); 3751 1.1 mrg DONE; 3752 1.1 mrg }) 3753 1.1 mrg 3754 1.1 mrg ;; BUGCHK is documented common to OSF/1 and VMS PALcode. 3755 1.1 mrg (define_insn "trap" 3756 1.1 mrg [(trap_if (const_int 1) (const_int 0)) 3757 1.1 mrg (use (reg:DI 29))] 3758 1.1 mrg "" 3759 1.1 mrg "call_pal 0x81" 3760 1.1 mrg [(set_attr "type" "callpal")]) 3761 1.1 mrg 3762 1.1 mrg ;; For userland, we load the thread pointer from the TCB. 3763 1.1 mrg ;; For the kernel, we load the per-cpu private value. 3764 1.1 mrg 3765 1.1 mrg (define_insn "get_thread_pointerdi" 3766 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=v") 3767 1.1.1.2 mrg (unspec:DI [(const_int 0)] UNSPEC_TP))] 3768 1.1.1.2 mrg "TARGET_ABI_OSF" 3769 1.1 mrg { 3770 1.1.1.2 mrg if (TARGET_TLS_KERNEL) 3771 1.1 mrg return "call_pal 0x32"; 3772 1.1 mrg else 3773 1.1 mrg return "call_pal 0x9e"; 3774 1.1 mrg } 3775 1.1 mrg [(set_attr "type" "callpal")]) 3776 1.1 mrg 3777 1.1 mrg ;; For completeness, and possibly a __builtin function, here's how to 3778 1.1 mrg ;; set the thread pointer. Since we don't describe enough of this 3779 1.1 mrg ;; quantity for CSE, we have to use a volatile unspec, and then there's 3780 1.1 mrg ;; not much point in creating an R16_REG register class. 3781 1.1 mrg 3782 1.1 mrg (define_expand "set_thread_pointerdi" 3783 1.1 mrg [(set (reg:DI 16) (match_operand:DI 0 "input_operand")) 3784 1.1 mrg (unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)] 3785 1.1 mrg "TARGET_ABI_OSF") 3786 1.1.1.2 mrg 3787 1.1.1.2 mrg (define_insn "*set_tp" 3788 1.1 mrg [(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)] 3789 1.1 mrg "TARGET_ABI_OSF" 3790 1.1 mrg { 3791 1.1 mrg if (TARGET_TLS_KERNEL) 3792 1.1 mrg return "call_pal 0x31"; 3793 1.1 mrg else 3794 1.1 mrg return "call_pal 0x9f"; 3795 1.1.1.2 mrg } 3796 1.1 mrg [(set_attr "type" "callpal")]) 3797 1.1.1.2 mrg 3798 1.1 mrg ;; Special builtins for establishing and reverting VMS condition handlers. 3799 1.1 mrg 3800 1.1 mrg (define_expand "builtin_establish_vms_condition_handler" 3801 1.1 mrg [(set (reg:DI 0) (match_operand:DI 0 "register_operand")) 3802 1.1 mrg (use (match_operand:DI 1 "address_operand"))] 3803 1.1.1.2 mrg "TARGET_ABI_OPEN_VMS" 3804 1.1.1.2 mrg { 3805 1.1.1.2 mrg alpha_expand_builtin_establish_vms_condition_handler (operands[0], 3806 1.1.1.2 mrg operands[1]); 3807 1.1.1.2 mrg }) 3808 1.1.1.2 mrg 3809 1.1.1.2 mrg (define_expand "builtin_revert_vms_condition_handler" 3810 1.1.1.2 mrg [(set (reg:DI 0) (match_operand:DI 0 "register_operand"))] 3811 1.1.1.2 mrg "TARGET_ABI_OPEN_VMS" 3812 1.1 mrg "alpha_expand_builtin_revert_vms_condition_handler (operands[0]);") 3813 1.1.1.2 mrg 3815 1.1 mrg ;; Finally, we have the basic data motion insns. The byte and word insns 3816 1.1.1.2 mrg ;; are done via define_expand. Start with the floating-point insns, since 3817 1.1.1.2 mrg ;; they are simpler. 3818 1.1 mrg 3819 1.1 mrg (define_expand "movsf" 3820 1.1 mrg [(set (match_operand:SF 0 "nonimmediate_operand") 3821 1.1 mrg (match_operand:SF 1 "general_operand"))] 3822 1.1 mrg "" 3823 1.1 mrg { 3824 1.1 mrg if (MEM_P (operands[0]) 3825 1.1 mrg && ! reg_or_0_operand (operands[1], SFmode)) 3826 1.1 mrg operands[1] = force_reg (SFmode, operands[1]); 3827 1.1.1.2 mrg }) 3828 1.1.1.2 mrg 3829 1.1 mrg (define_insn "*movsf" 3830 1.1.1.2 mrg [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r") 3831 1.1.1.2 mrg (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))] 3832 1.1.1.2 mrg "register_operand (operands[0], SFmode) 3833 1.1.1.2 mrg || reg_or_0_operand (operands[1], SFmode)" 3834 1.1.1.2 mrg "@ 3835 1.1.1.2 mrg cpys %R1,%R1,%0 3836 1.1.1.2 mrg ld%, %0,%1 3837 1.1.1.2 mrg bis $31,%r1,%0 3838 1.1.1.2 mrg ldl %0,%1 3839 1.1 mrg st%, %R1,%0 3840 1.1.1.2 mrg stl %r1,%0 3841 1.1 mrg itofs %1,%0 3842 1.1 mrg ftois %1,%0" 3843 1.1.1.2 mrg [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi") 3844 1.1.1.2 mrg (set_attr "isa" "*,*,*,*,*,*,fix,fix")]) 3845 1.1 mrg 3846 1.1 mrg (define_expand "movdf" 3847 1.1 mrg [(set (match_operand:DF 0 "nonimmediate_operand") 3848 1.1 mrg (match_operand:DF 1 "general_operand"))] 3849 1.1 mrg "" 3850 1.1 mrg { 3851 1.1 mrg if (MEM_P (operands[0]) 3852 1.1 mrg && ! reg_or_0_operand (operands[1], DFmode)) 3853 1.1 mrg operands[1] = force_reg (DFmode, operands[1]); 3854 1.1.1.2 mrg }) 3855 1.1.1.2 mrg 3856 1.1 mrg (define_insn "*movdf" 3857 1.1 mrg [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r") 3858 1.1 mrg (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))] 3859 1.1.1.2 mrg "register_operand (operands[0], DFmode) 3860 1.1.1.2 mrg || reg_or_0_operand (operands[1], DFmode)" 3861 1.1.1.2 mrg "@ 3862 1.1.1.2 mrg cpys %R1,%R1,%0 3863 1.1.1.2 mrg ld%- %0,%1 3864 1.1.1.2 mrg bis $31,%r1,%0 3865 1.1.1.2 mrg ldq %0,%1 3866 1.1.1.2 mrg st%- %R1,%0 3867 1.1.1.2 mrg stq %r1,%0 3868 1.1.1.2 mrg itoft %1,%0 3869 1.1.1.2 mrg ftoit %1,%0" 3870 1.1 mrg [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi") 3871 1.1.1.4 mrg (set_attr "isa" "*,*,*,*,*,*,fix,fix")]) 3872 1.1 mrg 3873 1.1 mrg ;; Subregs suck for register allocation. Pretend we can move TFmode 3874 1.1 mrg ;; data between general registers until after reload. 3875 1.1 mrg ;; ??? Is this still true now that we have the lower-subreg pass? 3876 1.1 mrg 3877 1.1 mrg (define_expand "movtf" 3878 1.1 mrg [(set (match_operand:TF 0 "nonimmediate_operand") 3879 1.1 mrg (match_operand:TF 1 "general_operand"))] 3880 1.1.1.2 mrg "" 3881 1.1 mrg { 3882 1.1.1.2 mrg if (MEM_P (operands[0]) 3883 1.1.1.2 mrg && ! reg_or_0_operand (operands[1], TFmode)) 3884 1.1 mrg operands[1] = force_reg (TFmode, operands[1]); 3885 1.1.1.2 mrg }) 3886 1.1.1.2 mrg 3887 1.1.1.2 mrg (define_insn_and_split "*movtf_internal" 3888 1.1 mrg [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o") 3889 1.1 mrg (match_operand:TF 1 "input_operand" "roG,rG"))] 3890 1.1.1.2 mrg "register_operand (operands[0], TFmode) 3891 1.1.1.2 mrg || reg_or_0_operand (operands[1], TFmode)" 3892 1.1 mrg "#" 3893 1.1 mrg "reload_completed" 3894 1.1 mrg [(set (match_dup 0) (match_dup 2)) 3895 1.1.1.2 mrg (set (match_dup 1) (match_dup 3))] 3896 1.1.1.2 mrg "alpha_split_tmode_pair (operands, TFmode, true);") 3897 1.1.1.2 mrg 3898 1.1.1.2 mrg ;; We do two major things here: handle mem->mem and construct long 3899 1.1 mrg ;; constants. 3900 1.1 mrg 3901 1.1 mrg (define_expand "movsi" 3902 1.1 mrg [(set (match_operand:SI 0 "nonimmediate_operand") 3903 1.1 mrg (match_operand:SI 1 "general_operand"))] 3904 1.1 mrg "" 3905 1.1.1.2 mrg { 3906 1.1.1.2 mrg if (alpha_expand_mov (SImode, operands)) 3907 1.1.1.2 mrg DONE; 3908 1.1.1.2 mrg }) 3909 1.1 mrg 3910 1.1 mrg (define_insn "*movsi" 3911 1.1 mrg [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,r") 3912 1.1 mrg (match_operand:SI 1 "input_operand" "rJ,K,L,n,m,rJ,s"))] 3913 1.1 mrg "register_operand (operands[0], SImode) 3914 1.1.1.2 mrg || reg_or_0_operand (operands[1], SImode)" 3915 1.1.1.2 mrg "@ 3916 1.1 mrg bis $31,%r1,%0 3917 1.1 mrg lda %0,%1($31) 3918 1.1 mrg ldah %0,%h1($31) 3919 1.1 mrg # 3920 1.1 mrg ldl %0,%1 3921 1.1 mrg stl %r1,%0 3922 1.1 mrg lda %0,%1" 3923 1.1 mrg [(set_attr "type" "ilog,iadd,iadd,multi,ild,ist,ldsym") 3924 1.1 mrg (set_attr "isa" "*,*,*,*,*,*,vms")]) 3925 1.1 mrg 3926 1.1 mrg ;; Split a load of a large constant into the appropriate two-insn 3927 1.1 mrg ;; sequence. 3928 1.1.1.2 mrg 3929 1.1 mrg (define_split 3930 1.1 mrg [(set (match_operand:SI 0 "register_operand") 3931 1.1 mrg (match_operand:SI 1 "non_add_const_operand"))] 3932 1.1 mrg "" 3933 1.1 mrg [(const_int 0)] 3934 1.1 mrg { 3935 1.1 mrg if (alpha_split_const_mov (SImode, operands)) 3936 1.1 mrg DONE; 3937 1.1 mrg else 3938 1.1 mrg FAIL; 3939 1.1.1.2 mrg }) 3940 1.1.1.2 mrg 3941 1.1 mrg (define_insn "*movdi_er_low_l" 3942 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 3943 1.1 mrg (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 3944 1.1 mrg (match_operand:DI 2 "local_symbolic_operand")))] 3945 1.1 mrg "TARGET_EXPLICIT_RELOCS" 3946 1.1 mrg { 3947 1.1.1.2 mrg if (true_regnum (operands[1]) == 29) 3948 1.1.1.2 mrg return "lda %0,%2(%1)\t\t!gprel"; 3949 1.1 mrg else 3950 1.1 mrg return "lda %0,%2(%1)\t\t!gprellow"; 3951 1.1 mrg } 3952 1.1 mrg [(set_attr "usegp" "yes")]) 3953 1.1 mrg 3954 1.1 mrg (define_split 3955 1.1 mrg [(set (match_operand:DI 0 "register_operand") 3956 1.1 mrg (match_operand:DI 1 "small_symbolic_operand"))] 3957 1.1.1.2 mrg "TARGET_EXPLICIT_RELOCS && reload_completed" 3958 1.1 mrg [(set (match_dup 0) 3959 1.1 mrg (lo_sum:DI (match_dup 2) (match_dup 1)))] 3960 1.1 mrg "operands[2] = pic_offset_table_rtx;") 3961 1.1 mrg 3962 1.1 mrg (define_split 3963 1.1 mrg [(set (match_operand:DI 0 "register_operand") 3964 1.1 mrg (match_operand:DI 1 "local_symbolic_operand"))] 3965 1.1 mrg "TARGET_EXPLICIT_RELOCS && reload_completed" 3966 1.1 mrg [(set (match_dup 0) 3967 1.1.1.2 mrg (plus:DI (match_dup 2) (high:DI (match_dup 1)))) 3968 1.1.1.2 mrg (set (match_dup 0) 3969 1.1 mrg (lo_sum:DI (match_dup 0) (match_dup 1)))] 3970 1.1 mrg "operands[2] = pic_offset_table_rtx;") 3971 1.1 mrg 3972 1.1 mrg (define_split 3973 1.1 mrg [(match_operand 0 "some_small_symbolic_operand")] 3974 1.1 mrg "" 3975 1.1 mrg [(match_dup 0)] 3976 1.1 mrg "operands[0] = split_small_symbolic_operand (operands[0]);") 3977 1.1 mrg 3978 1.1 mrg ;; Accepts any symbolic, not just global, since function calls that 3979 1.1 mrg ;; don't go via bsr still use !literal in hopes of linker relaxation. 3980 1.1.1.2 mrg (define_insn "movdi_er_high_g" 3981 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand" "=r") 3982 1.1 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "r") 3983 1.1 mrg (match_operand:DI 2 "symbolic_operand") 3984 1.1 mrg (match_operand 3 "const_int_operand")] 3985 1.1 mrg UNSPEC_LITERAL))] 3986 1.1 mrg "TARGET_EXPLICIT_RELOCS" 3987 1.1 mrg { 3988 1.1 mrg if (INTVAL (operands[3]) == 0) 3989 1.1 mrg return "ldq %0,%2(%1)\t\t!literal"; 3990 1.1 mrg else 3991 1.1 mrg return "ldq %0,%2(%1)\t\t!literal!%3"; 3992 1.1.1.2 mrg } 3993 1.1.1.2 mrg [(set_attr "type" "ldsym")]) 3994 1.1 mrg 3995 1.1 mrg (define_split 3996 1.1 mrg [(set (match_operand:DI 0 "register_operand") 3997 1.1 mrg (match_operand:DI 1 "global_symbolic_operand"))] 3998 1.1 mrg "TARGET_EXPLICIT_RELOCS && reload_completed" 3999 1.1 mrg [(set (match_dup 0) 4000 1.1 mrg (unspec:DI [(match_dup 2) 4001 1.1 mrg (match_dup 1) 4002 1.1 mrg (const_int 0)] UNSPEC_LITERAL))] 4003 1.1 mrg "operands[2] = pic_offset_table_rtx;") 4004 1.1 mrg 4005 1.1 mrg (define_insn "movdi_er_tlsgd" 4006 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand" "=r") 4007 1.1 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "r") 4008 1.1 mrg (match_operand:DI 2 "symbolic_operand") 4009 1.1 mrg (match_operand 3 "const_int_operand")] 4010 1.1 mrg UNSPEC_TLSGD))] 4011 1.1 mrg "HAVE_AS_TLS" 4012 1.1 mrg { 4013 1.1 mrg if (INTVAL (operands[3]) == 0) 4014 1.1 mrg return "lda %0,%2(%1)\t\t!tlsgd"; 4015 1.1 mrg else 4016 1.1 mrg return "lda %0,%2(%1)\t\t!tlsgd!%3"; 4017 1.1 mrg }) 4018 1.1 mrg 4019 1.1.1.2 mrg (define_insn "movdi_er_tlsldm" 4020 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 4021 1.1 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "r") 4022 1.1 mrg (match_operand 2 "const_int_operand")] 4023 1.1 mrg UNSPEC_TLSLDM))] 4024 1.1 mrg "HAVE_AS_TLS" 4025 1.1 mrg { 4026 1.1 mrg if (INTVAL (operands[2]) == 0) 4027 1.1.1.2 mrg return "lda %0,%&(%1)\t\t!tlsldm"; 4028 1.1.1.2 mrg else 4029 1.1 mrg return "lda %0,%&(%1)\t\t!tlsldm!%2"; 4030 1.1 mrg }) 4031 1.1 mrg 4032 1.1 mrg (define_insn "*movdi_er_gotdtp" 4033 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 4034 1.1 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "r") 4035 1.1 mrg (match_operand:DI 2 "symbolic_operand")] 4036 1.1 mrg UNSPEC_DTPREL))] 4037 1.1 mrg "HAVE_AS_TLS" 4038 1.1 mrg "ldq %0,%2(%1)\t\t!gotdtprel" 4039 1.1 mrg [(set_attr "type" "ild") 4040 1.1 mrg (set_attr "usegp" "yes")]) 4041 1.1.1.2 mrg 4042 1.1 mrg (define_split 4043 1.1 mrg [(set (match_operand:DI 0 "register_operand") 4044 1.1 mrg (match_operand:DI 1 "gotdtp_symbolic_operand"))] 4045 1.1 mrg "HAVE_AS_TLS && reload_completed" 4046 1.1 mrg [(set (match_dup 0) 4047 1.1 mrg (unspec:DI [(match_dup 2) 4048 1.1 mrg (match_dup 1)] UNSPEC_DTPREL))] 4049 1.1.1.2 mrg { 4050 1.1.1.2 mrg operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0); 4051 1.1 mrg operands[2] = pic_offset_table_rtx; 4052 1.1 mrg }) 4053 1.1 mrg 4054 1.1 mrg (define_insn "*movdi_er_gottp" 4055 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 4056 1.1 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "r") 4057 1.1 mrg (match_operand:DI 2 "symbolic_operand")] 4058 1.1 mrg UNSPEC_TPREL))] 4059 1.1 mrg "HAVE_AS_TLS" 4060 1.1.1.2 mrg "ldq %0,%2(%1)\t\t!gottprel" 4061 1.1 mrg [(set_attr "type" "ild") 4062 1.1.1.2 mrg (set_attr "usegp" "yes")]) 4063 1.1 mrg 4064 1.1.1.2 mrg (define_split 4065 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand") 4066 1.1.1.2 mrg (match_operand:DI 1 "gottp_symbolic_operand"))] 4067 1.1 mrg "HAVE_AS_TLS && reload_completed" 4068 1.1 mrg [(set (match_dup 0) 4069 1.1 mrg (unspec:DI [(match_dup 2) 4070 1.1 mrg (match_dup 1)] UNSPEC_TPREL))] 4071 1.1 mrg { 4072 1.1 mrg operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0); 4073 1.1 mrg operands[2] = pic_offset_table_rtx; 4074 1.1 mrg }) 4075 1.1 mrg 4076 1.1 mrg (define_insn "*movdi" 4077 1.1.1.2 mrg [(set (match_operand:DI 0 "nonimmediate_operand" 4078 1.1 mrg "=r,r,r,r,r,r,r,r, m, *f,*f, Q, r,*f") 4079 1.1 mrg (match_operand:DI 1 "input_operand" 4080 1.1 mrg "rJ,K,L,T,s,n,s,m,rJ,*fJ, Q,*f,*f, r"))] 4081 1.1 mrg "register_operand (operands[0], DImode) 4082 1.1.1.2 mrg || reg_or_0_operand (operands[1], DImode)" 4083 1.1.1.2 mrg "@ 4084 1.1.1.2 mrg mov %r1,%0 4085 1.1 mrg lda %0,%1($31) 4086 1.1 mrg ldah %0,%h1($31) 4087 1.1 mrg # 4088 1.1 mrg # 4089 1.1 mrg # 4090 1.1 mrg lda %0,%1 4091 1.1 mrg ldq%A1 %0,%1 4092 1.1 mrg stq%A0 %r1,%0 4093 1.1 mrg fmov %R1,%0 4094 1.1 mrg ldt %0,%1 4095 1.1 mrg stt %R1,%0 4096 1.1 mrg ftoit %1,%0 4097 1.1 mrg itoft %1,%0" 4098 1.1 mrg [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,multi,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof") 4099 1.1 mrg (set_attr "isa" "*,*,*,er,er,*,ner,*,*,*,*,*,fix,fix") 4100 1.1 mrg (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*,*,*,*")]) 4101 1.1 mrg 4102 1.1.1.2 mrg ;; VMS needs to set up "vms_base_regno" for unwinding. This move 4103 1.1.1.2 mrg ;; often appears dead to the life analysis code, at which point we 4104 1.1 mrg ;; die for emitting dead prologue instructions. Force this live. 4105 1.1 mrg 4106 1.1 mrg (define_insn "force_movdi" 4107 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 4108 1.1 mrg (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")] 4109 1.1 mrg UNSPECV_FORCE_MOV))] 4110 1.1 mrg "" 4111 1.1 mrg "mov %1,%0" 4112 1.1 mrg [(set_attr "type" "ilog")]) 4113 1.1 mrg 4114 1.1.1.2 mrg ;; We do three major things here: handle mem->mem, put 64-bit constants in 4115 1.1.1.2 mrg ;; memory, and construct long 32-bit constants. 4116 1.1 mrg 4117 1.1 mrg (define_expand "movdi" 4118 1.1 mrg [(set (match_operand:DI 0 "nonimmediate_operand") 4119 1.1 mrg (match_operand:DI 1 "general_operand"))] 4120 1.1 mrg "" 4121 1.1 mrg { 4122 1.1 mrg if (alpha_expand_mov (DImode, operands)) 4123 1.1 mrg DONE; 4124 1.1 mrg }) 4125 1.1 mrg 4126 1.1 mrg ;; Split a load of a large constant into the appropriate two-insn 4127 1.1 mrg ;; sequence. 4128 1.1 mrg 4129 1.1 mrg (define_split 4130 1.1 mrg [(set (match_operand:DI 0 "register_operand") 4131 1.1 mrg (match_operand:DI 1 "non_add_const_operand"))] 4132 1.1 mrg "" 4133 1.1 mrg [(const_int 0)] 4134 1.1 mrg { 4135 1.1 mrg if (alpha_split_const_mov (DImode, operands)) 4136 1.1 mrg DONE; 4137 1.1 mrg else 4138 1.1 mrg FAIL; 4139 1.1 mrg }) 4140 1.1 mrg 4141 1.1.1.2 mrg ;; We need to prevent reload from splitting TImode moves, because it 4142 1.1 mrg ;; might decide to overwrite a pointer with the value it points to. 4143 1.1 mrg ;; In that case we have to do the loads in the appropriate order so 4144 1.1.1.2 mrg ;; that the pointer is not destroyed too early. 4145 1.1.1.2 mrg 4146 1.1 mrg (define_insn_and_split "*movti_internal" 4147 1.1 mrg [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o") 4148 1.1 mrg (match_operand:TI 1 "input_operand" "roJ,rJ"))] 4149 1.1 mrg "(register_operand (operands[0], TImode) 4150 1.1 mrg /* Prevent rematerialization of constants. */ 4151 1.1 mrg && ! CONSTANT_P (operands[1])) 4152 1.1 mrg || reg_or_0_operand (operands[1], TImode)" 4153 1.1 mrg "#" 4154 1.1 mrg "reload_completed" 4155 1.1 mrg [(set (match_dup 0) (match_dup 2)) 4156 1.1 mrg (set (match_dup 1) (match_dup 3))] 4157 1.1.1.4 mrg "alpha_split_tmode_pair (operands, TImode, true);") 4158 1.1 mrg 4159 1.1 mrg (define_expand "movti" 4160 1.1 mrg [(set (match_operand:TI 0 "nonimmediate_operand") 4161 1.1 mrg (match_operand:TI 1 "general_operand"))] 4162 1.1 mrg "" 4163 1.1 mrg { 4164 1.1 mrg if (MEM_P (operands[0]) 4165 1.1 mrg && ! reg_or_0_operand (operands[1], TImode)) 4166 1.1 mrg operands[1] = force_reg (TImode, operands[1]); 4167 1.1 mrg 4168 1.1 mrg if (operands[1] == const0_rtx) 4169 1.1 mrg ; 4170 1.1 mrg /* We must put 64-bit constants in memory. We could keep the 4171 1.1 mrg 32-bit constants in TImode and rely on the splitter, but 4172 1.1 mrg this doesn't seem to be worth the pain. */ 4173 1.1 mrg else if (CONST_SCALAR_INT_P (operands[1])) 4174 1.1 mrg { 4175 1.1 mrg rtx in[2], out[2], target; 4176 1.1 mrg 4177 1.1 mrg gcc_assert (can_create_pseudo_p ()); 4178 1.1 mrg 4179 1.1 mrg split_double (operands[1], &in[0], &in[1]); 4180 1.1 mrg 4181 1.1 mrg if (in[0] == const0_rtx) 4182 1.1 mrg out[0] = const0_rtx; 4183 1.1 mrg else 4184 1.1 mrg { 4185 1.1 mrg out[0] = gen_reg_rtx (DImode); 4186 1.1 mrg emit_insn (gen_movdi (out[0], in[0])); 4187 1.1 mrg } 4188 1.1 mrg 4189 1.1 mrg if (in[1] == const0_rtx) 4190 1.1.1.4 mrg out[1] = const0_rtx; 4191 1.1 mrg else 4192 1.1 mrg { 4193 1.1 mrg out[1] = gen_reg_rtx (DImode); 4194 1.1 mrg emit_insn (gen_movdi (out[1], in[1])); 4195 1.1 mrg } 4196 1.1 mrg 4197 1.1 mrg if (!REG_P (operands[0])) 4198 1.1 mrg target = gen_reg_rtx (TImode); 4199 1.1 mrg else 4200 1.1 mrg target = operands[0]; 4201 1.1 mrg 4202 1.1 mrg emit_insn (gen_movdi (operand_subword (target, 0, 0, TImode), out[0])); 4203 1.1 mrg emit_insn (gen_movdi (operand_subword (target, 1, 0, TImode), out[1])); 4204 1.1 mrg 4205 1.1 mrg if (target != operands[0]) 4206 1.1.1.2 mrg emit_insn (gen_rtx_SET (operands[0], target)); 4207 1.1.1.2 mrg 4208 1.1.1.2 mrg DONE; 4209 1.1 mrg } 4210 1.1 mrg }) 4211 1.1.1.2 mrg 4212 1.1 mrg ;; These are the partial-word cases. 4213 1.1 mrg ;; 4214 1.1.1.2 mrg ;; First we have the code to load an aligned word. Operand 0 is the register 4215 1.1.1.2 mrg ;; in which to place the result. It's mode is QImode or HImode. Operand 1 4216 1.1.1.2 mrg ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the 4217 1.1 mrg ;; number of bits within the word that the value is. Operand 3 is an SImode 4218 1.1 mrg ;; scratch register. If operand 0 is a hard register, operand 3 may be the 4219 1.1.1.2 mrg ;; same register. It is allowed to conflict with operand 1 as well. 4220 1.1 mrg 4221 1.1 mrg (define_expand "aligned_loadqi" 4222 1.1 mrg [(set (match_operand:SI 3 "register_operand") 4223 1.1 mrg (match_operand:SI 1 "memory_operand")) 4224 1.1 mrg (set (match_operand:DI 0 "register_operand") 4225 1.1 mrg (zero_extract:DI (subreg:DI (match_dup 3) 0) 4226 1.1 mrg (const_int 8) 4227 1.1 mrg (match_operand:DI 2 "const_int_operand")))]) 4228 1.1 mrg 4229 1.1.1.2 mrg (define_expand "aligned_loadhi" 4230 1.1.1.2 mrg [(set (match_operand:SI 3 "register_operand") 4231 1.1 mrg (match_operand:SI 1 "memory_operand")) 4232 1.1.1.2 mrg (set (match_operand:DI 0 "register_operand") 4233 1.1 mrg (zero_extract:DI (subreg:DI (match_dup 3) 0) 4234 1.1.1.2 mrg (const_int 16) 4235 1.1 mrg (match_operand:DI 2 "const_int_operand")))]) 4236 1.1 mrg 4237 1.1.1.2 mrg ;; Similar for unaligned loads, where we use the sequence from the 4238 1.1 mrg ;; Alpha Architecture manual. We have to distinguish between little-endian 4239 1.1 mrg ;; and big-endian systems as the sequences are different. 4240 1.1.1.2 mrg ;; 4241 1.1.1.2 mrg ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where 4242 1.1 mrg ;; operand 3 can overlap the input and output registers. 4243 1.1.1.2 mrg 4244 1.1 mrg (define_expand "unaligned_loadqi" 4245 1.1.1.2 mrg [(set (match_operand:DI 2 "register_operand") 4246 1.1 mrg (mem:DI (and:DI (match_operand:DI 1 "address_operand") 4247 1.1 mrg (const_int -8)))) 4248 1.1.1.2 mrg (set (match_operand:DI 3 "register_operand") 4249 1.1 mrg (match_dup 1)) 4250 1.1 mrg (set (match_operand:DI 0 "register_operand") 4251 1.1 mrg (zero_extract:DI (match_dup 2) 4252 1.1 mrg (const_int 8) 4253 1.1 mrg (ashift:DI (match_dup 3) (const_int 3))))]) 4254 1.1 mrg 4255 1.1 mrg (define_expand "unaligned_loadhi" 4256 1.1.1.2 mrg [(set (match_operand:DI 2 "register_operand") 4257 1.1.1.2 mrg (mem:DI (and:DI (match_operand:DI 1 "address_operand") 4258 1.1 mrg (const_int -8)))) 4259 1.1 mrg (set (match_operand:DI 3 "register_operand") 4260 1.1.1.2 mrg (match_dup 1)) 4261 1.1.1.2 mrg (set (match_operand:DI 0 "register_operand") 4262 1.1.1.2 mrg (zero_extract:DI (match_dup 2) 4263 1.1 mrg (const_int 16) 4264 1.1 mrg (ashift:DI (match_dup 3) (const_int 3))))]) 4265 1.1 mrg 4266 1.1 mrg ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the 4267 1.1 mrg ;; aligned SImode MEM. Operand 1 is the register containing the 4268 1.1 mrg ;; byte or word to store. Operand 2 is the number of bits within the word that 4269 1.1 mrg ;; the value should be placed. Operands 3 and 4 are SImode temporaries. 4270 1.1 mrg 4271 1.1 mrg (define_expand "aligned_store" 4272 1.1 mrg [(set (match_operand:SI 3 "register_operand") 4273 1.1 mrg (match_operand:SI 0 "memory_operand")) 4274 1.1 mrg (set (subreg:DI (match_dup 3) 0) 4275 1.1 mrg (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5))) 4276 1.1 mrg (set (subreg:DI (match_operand:SI 4 "register_operand") 0) 4277 1.1 mrg (ashift:DI (zero_extend:DI (match_operand 1 "register_operand")) 4278 1.1 mrg (match_operand:DI 2 "const_int_operand"))) 4279 1.1.1.2 mrg (set (subreg:DI (match_dup 4) 0) 4280 1.1.1.2 mrg (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0))) 4281 1.1.1.2 mrg (set (match_dup 0) (match_dup 4))] 4282 1.1 mrg "" 4283 1.1.1.2 mrg { 4284 1.1 mrg operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1])) 4285 1.1 mrg << INTVAL (operands[2]))); 4286 1.1.1.2 mrg }) 4287 1.1 mrg 4288 1.1 mrg ;; For the unaligned byte and halfword cases, we use code similar to that 4289 1.1.1.2 mrg ;; in the ;; Architecture book, but reordered to lower the number of registers 4290 1.1.1.2 mrg ;; required. Operand 0 is the address. Operand 1 is the data to store. 4291 1.1.1.2 mrg ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may 4292 1.1 mrg ;; be the same temporary, if desired. If the address is in a register, 4293 1.1 mrg ;; operand 2 can be that register. 4294 1.1 mrg 4295 1.1 mrg (define_expand "unaligned_store<mode>" 4296 1.1 mrg [(set (match_operand:DI 3 "register_operand") 4297 1.1.1.2 mrg (mem:DI (and:DI (match_operand:DI 0 "address_operand") 4298 1.1 mrg (const_int -8)))) 4299 1.1 mrg (set (match_operand:DI 2 "register_operand") 4300 1.1 mrg (match_dup 0)) 4301 1.1 mrg (set (match_dup 3) 4302 1.1 mrg (and:DI (not:DI (ashift:DI (match_dup 5) 4303 1.1.1.2 mrg (ashift:DI (match_dup 2) (const_int 3)))) 4304 1.1.1.2 mrg (match_dup 3))) 4305 1.1.1.2 mrg (set (match_operand:DI 4 "register_operand") 4306 1.1 mrg (ashift:DI (zero_extend:DI 4307 1.1 mrg (match_operand:I12MODE 1 "register_operand")) 4308 1.1 mrg (ashift:DI (match_dup 2) (const_int 3)))) 4309 1.1.1.2 mrg (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3))) 4310 1.1.1.2 mrg (set (mem:DI (and:DI (match_dup 0) (const_int -8))) 4311 1.1 mrg (match_dup 4))] 4312 1.1 mrg "" 4313 1.1 mrg "operands[5] = GEN_INT (GET_MODE_MASK (<MODE>mode));") 4314 1.1.1.2 mrg 4315 1.1.1.2 mrg ;; Here are the define_expand's for QI and HI moves that use the above 4316 1.1.1.2 mrg ;; patterns. We have the normal sets, plus the ones that need scratch 4317 1.1.1.2 mrg ;; registers for reload. 4318 1.1.1.2 mrg 4319 1.1.1.2 mrg (define_expand "mov<mode>" 4320 1.1.1.2 mrg [(set (match_operand:I12MODE 0 "nonimmediate_operand") 4321 1.1.1.2 mrg (match_operand:I12MODE 1 "general_operand"))] 4322 1.1.1.2 mrg "" 4323 1.1.1.2 mrg { 4324 1.1.1.2 mrg if (TARGET_BWX 4325 1.1.1.2 mrg ? alpha_expand_mov (<MODE>mode, operands) 4326 1.1.1.2 mrg : alpha_expand_mov_nobwx (<MODE>mode, operands)) 4327 1.1.1.2 mrg DONE; 4328 1.1.1.2 mrg }) 4329 1.1.1.2 mrg 4330 1.1.1.2 mrg (define_insn "*movqi" 4331 1.1.1.2 mrg [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m") 4332 1.1.1.2 mrg (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))] 4333 1.1.1.2 mrg "register_operand (operands[0], QImode) 4334 1.1.1.2 mrg || reg_or_0_operand (operands[1], QImode)" 4335 1.1.1.2 mrg "@ 4336 1.1.1.2 mrg bis $31,%r1,%0 4337 1.1.1.2 mrg lda %0,%L1($31) 4338 1.1.1.2 mrg ldbu %0,%1 4339 1.1 mrg stb %r1,%0" 4340 1.1 mrg [(set_attr "type" "ilog,iadd,ild,ist") 4341 1.1 mrg (set_attr "isa" "*,*,bwx,bwx")]) 4342 1.1 mrg 4343 1.1.1.2 mrg (define_insn "*movhi" 4344 1.1.1.2 mrg [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m") 4345 1.1 mrg (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))] 4346 1.1 mrg "register_operand (operands[0], HImode) 4347 1.1 mrg || reg_or_0_operand (operands[1], HImode)" 4348 1.1 mrg "@ 4349 1.1 mrg bis $31,%r1,%0 4350 1.1 mrg lda %0,%L1($31) 4351 1.1 mrg ldwu %0,%1 4352 1.1 mrg stw %r1,%0" 4353 1.1 mrg [(set_attr "type" "ilog,iadd,ild,ist") 4354 1.1 mrg (set_attr "isa" "*,*,bwx,bwx")]) 4355 1.1 mrg 4356 1.1 mrg ;; We need to hook into the extra support that we have for HImode 4357 1.1 mrg ;; reloads when BWX insns are not available. 4358 1.1 mrg (define_expand "movcqi" 4359 1.1 mrg [(set (match_operand:CQI 0 "nonimmediate_operand") 4360 1.1 mrg (match_operand:CQI 1 "general_operand"))] 4361 1.1 mrg "!TARGET_BWX" 4362 1.1 mrg { 4363 1.1 mrg if (GET_CODE (operands[0]) == CONCAT || GET_CODE (operands[1]) == CONCAT) 4364 1.1 mrg ; 4365 1.1 mrg else if (!any_memory_operand (operands[0], CQImode)) 4366 1.1 mrg { 4367 1.1 mrg if (!any_memory_operand (operands[1], CQImode)) 4368 1.1 mrg { 4369 1.1 mrg emit_move_insn (gen_lowpart (HImode, operands[0]), 4370 1.1 mrg gen_lowpart (HImode, operands[1])); 4371 1.1 mrg DONE; 4372 1.1 mrg } 4373 1.1 mrg if (aligned_memory_operand (operands[1], CQImode)) 4374 1.1 mrg { 4375 1.1 mrg bool done; 4376 1.1 mrg do_aligned1: 4377 1.1 mrg operands[1] = gen_lowpart (HImode, operands[1]); 4378 1.1 mrg do_aligned2: 4379 1.1 mrg operands[0] = gen_lowpart (HImode, operands[0]); 4380 1.1 mrg done = alpha_expand_mov_nobwx (HImode, operands); 4381 1.1 mrg gcc_assert (done); 4382 1.1 mrg DONE; 4383 1.1 mrg } 4384 1.1 mrg } 4385 1.1 mrg else if (aligned_memory_operand (operands[0], CQImode)) 4386 1.1 mrg { 4387 1.1 mrg if (MEM_P (operands[1])) 4388 1.1 mrg { 4389 1.1 mrg rtx x = gen_reg_rtx (HImode); 4390 1.1 mrg emit_move_insn (gen_lowpart (CQImode, x), operands[1]); 4391 1.1 mrg operands[1] = x; 4392 1.1 mrg goto do_aligned2; 4393 1.1 mrg } 4394 1.1 mrg goto do_aligned1; 4395 1.1 mrg } 4396 1.1 mrg 4397 1.1 mrg gcc_assert (!reload_in_progress); 4398 1.1 mrg emit_move_complex_parts (operands[0], operands[1]); 4399 1.1 mrg DONE; 4400 1.1 mrg }) 4401 1.1 mrg 4402 1.1 mrg ;; Here are the versions for reload. 4403 1.1 mrg ;; 4404 1.1 mrg ;; The aligned input case is recognized early in alpha_secondary_reload 4405 1.1 mrg ;; in order to avoid allocating an unnecessary scratch register. 4406 1.1 mrg ;; 4407 1.1 mrg ;; Note that in the unaligned cases we know that the operand must not be 4408 1.1 mrg ;; a pseudo-register because stack slots are always aligned references. 4409 1.1 mrg 4410 1.1 mrg (define_expand "reload_in<mode>" 4411 1.1 mrg [(parallel [(match_operand:RELOAD12 0 "register_operand" "=r") 4412 1.1 mrg (match_operand:RELOAD12 1 "any_memory_operand" "m") 4413 1.1 mrg (match_operand:TI 2 "register_operand" "=&r")])] 4414 1.1 mrg "!TARGET_BWX" 4415 1.1 mrg { 4416 1.1 mrg rtx scratch, seq, addr; 4417 1.1 mrg unsigned regno = REGNO (operands[2]); 4418 1.1 mrg 4419 1.1 mrg /* It is possible that one of the registers we got for operands[2] 4420 1.1 mrg might coincide with that of operands[0] (which is why we made 4421 1.1 mrg it TImode). Pick the other one to use as our scratch. */ 4422 1.1 mrg if (regno == REGNO (operands[0])) 4423 1.1 mrg regno++; 4424 1.1.1.2 mrg scratch = gen_rtx_REG (DImode, regno); 4425 1.1 mrg 4426 1.1 mrg addr = get_unaligned_address (operands[1]); 4427 1.1 mrg operands[0] = gen_rtx_REG (DImode, REGNO (operands[0])); 4428 1.1 mrg seq = gen_unaligned_load<reloadmode> (operands[0], addr, 4429 1.1 mrg scratch, operands[0]); 4430 1.1 mrg alpha_set_memflags (seq, operands[1]); 4431 1.1 mrg 4432 1.1 mrg emit_insn (seq); 4433 1.1 mrg DONE; 4434 1.1 mrg }) 4435 1.1 mrg 4436 1.1 mrg (define_expand "reload_out<mode>" 4437 1.1 mrg [(parallel [(match_operand:RELOAD12 0 "any_memory_operand" "=m") 4438 1.1 mrg (match_operand:RELOAD12 1 "register_operand" "r") 4439 1.1 mrg (match_operand:TI 2 "register_operand" "=&r")])] 4440 1.1 mrg "!TARGET_BWX" 4441 1.1 mrg { 4442 1.1 mrg unsigned regno = REGNO (operands[2]); 4443 1.1 mrg 4444 1.1 mrg if (<MODE>mode == CQImode) 4445 1.1 mrg { 4446 1.1 mrg operands[0] = gen_lowpart (HImode, operands[0]); 4447 1.1 mrg operands[1] = gen_lowpart (HImode, operands[1]); 4448 1.1 mrg } 4449 1.1 mrg 4450 1.1 mrg if (aligned_memory_operand (operands[0], <MODE>mode)) 4451 1.1 mrg { 4452 1.1 mrg emit_insn (gen_reload_out<reloadmode>_aligned 4453 1.1 mrg (operands[0], operands[1], 4454 1.1 mrg gen_rtx_REG (SImode, regno), 4455 1.1 mrg gen_rtx_REG (SImode, regno + 1))); 4456 1.1 mrg } 4457 1.1 mrg else 4458 1.1 mrg { 4459 1.1 mrg rtx addr = get_unaligned_address (operands[0]); 4460 1.1 mrg rtx scratch1 = gen_rtx_REG (DImode, regno); 4461 1.1 mrg rtx scratch2 = gen_rtx_REG (DImode, regno + 1); 4462 1.1 mrg rtx scratch3 = scratch1; 4463 1.1 mrg rtx seq; 4464 1.1 mrg 4465 1.1 mrg if (REG_P (addr)) 4466 1.1 mrg scratch1 = addr; 4467 1.1 mrg 4468 1.1 mrg seq = gen_unaligned_store<reloadmode> (addr, operands[1], scratch1, 4469 1.1 mrg scratch2, scratch3); 4470 1.1 mrg alpha_set_memflags (seq, operands[0]); 4471 1.1 mrg emit_insn (seq); 4472 1.1 mrg } 4473 1.1 mrg DONE; 4474 1.1 mrg }) 4475 1.1 mrg 4476 1.1 mrg ;; Helpers for the above. The way reload is structured, we can't 4477 1.1 mrg ;; always get a proper address for a stack slot during reload_foo 4478 1.1 mrg ;; expansion, so we must delay our address manipulations until after. 4479 1.1 mrg 4480 1.1 mrg (define_insn_and_split "reload_in<mode>_aligned" 4481 1.1 mrg [(set (match_operand:I12MODE 0 "register_operand" "=r") 4482 1.1 mrg (match_operand:I12MODE 1 "memory_operand" "m"))] 4483 1.1.1.2 mrg "!TARGET_BWX && (reload_in_progress || reload_completed)" 4484 1.1.1.2 mrg "#" 4485 1.1 mrg "!TARGET_BWX && reload_completed" 4486 1.1 mrg [(const_int 0)] 4487 1.1 mrg { 4488 1.1 mrg rtx aligned_mem, bitnum; 4489 1.1 mrg get_aligned_mem (operands[1], &aligned_mem, &bitnum); 4490 1.1 mrg emit_insn (gen_aligned_load<reloadmode> 4491 1.1 mrg (gen_lowpart (DImode, operands[0]), aligned_mem, bitnum, 4492 1.1 mrg gen_rtx_REG (SImode, REGNO (operands[0])))); 4493 1.1 mrg DONE; 4494 1.1 mrg }) 4495 1.1 mrg 4496 1.1 mrg (define_insn_and_split "reload_out<mode>_aligned" 4497 1.1 mrg [(set (match_operand:I12MODE 0 "memory_operand" "=m") 4498 1.1 mrg (match_operand:I12MODE 1 "register_operand" "r")) 4499 1.1 mrg (clobber (match_operand:SI 2 "register_operand" "=&r")) 4500 1.1.1.2 mrg (clobber (match_operand:SI 3 "register_operand" "=&r"))] 4501 1.1 mrg "!TARGET_BWX && (reload_in_progress || reload_completed)" 4502 1.1 mrg "#" 4503 1.1.1.2 mrg "!TARGET_BWX && reload_completed" 4504 1.1.1.2 mrg [(const_int 0)] 4505 1.1 mrg { 4506 1.1 mrg rtx aligned_mem, bitnum; 4507 1.1 mrg get_aligned_mem (operands[0], &aligned_mem, &bitnum); 4508 1.1 mrg emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum, 4509 1.1 mrg operands[2], operands[3])); 4510 1.1 mrg DONE; 4511 1.1 mrg }) 4512 1.1.1.2 mrg 4514 1.1 mrg ;; Vector operations 4515 1.1 mrg 4516 1.1 mrg (define_mode_iterator VEC [V8QI V4HI V2SI]) 4517 1.1 mrg (define_mode_iterator VEC12 [V8QI V4HI]) 4518 1.1 mrg 4519 1.1 mrg (define_expand "mov<mode>" 4520 1.1 mrg [(set (match_operand:VEC 0 "nonimmediate_operand") 4521 1.1 mrg (match_operand:VEC 1 "general_operand"))] 4522 1.1 mrg "" 4523 1.1 mrg { 4524 1.1 mrg if (alpha_expand_mov (<MODE>mode, operands)) 4525 1.1.1.2 mrg DONE; 4526 1.1.1.2 mrg }) 4527 1.1 mrg 4528 1.1 mrg (define_split 4529 1.1 mrg [(set (match_operand:VEC 0 "register_operand") 4530 1.1 mrg (match_operand:VEC 1 "non_zero_const_operand"))] 4531 1.1 mrg "" 4532 1.1 mrg [(const_int 0)] 4533 1.1 mrg { 4534 1.1 mrg if (alpha_split_const_mov (<MODE>mode, operands)) 4535 1.1 mrg DONE; 4536 1.1.1.2 mrg else 4537 1.1.1.2 mrg FAIL; 4538 1.1 mrg }) 4539 1.1 mrg 4540 1.1 mrg 4541 1.1 mrg (define_expand "movmisalign<mode>" 4542 1.1 mrg [(set (match_operand:VEC 0 "nonimmediate_operand") 4543 1.1 mrg (match_operand:VEC 1 "general_operand"))] 4544 1.1 mrg "" 4545 1.1 mrg { 4546 1.1 mrg alpha_expand_movmisalign (<MODE>mode, operands); 4547 1.1 mrg DONE; 4548 1.1.1.2 mrg }) 4549 1.1.1.2 mrg 4550 1.1 mrg (define_insn "*mov<mode>_fix" 4551 1.1.1.2 mrg [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m,r,*f") 4552 1.1.1.2 mrg (match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f,*f,r"))] 4553 1.1.1.2 mrg "register_operand (operands[0], <MODE>mode) 4554 1.1.1.2 mrg || reg_or_0_operand (operands[1], <MODE>mode)" 4555 1.1.1.2 mrg "@ 4556 1.1 mrg bis $31,%r1,%0 4557 1.1.1.2 mrg # 4558 1.1 mrg ldq %0,%1 4559 1.1 mrg stq %r1,%0 4560 1.1 mrg cpys %R1,%R1,%0 4561 1.1 mrg ldt %0,%1 4562 1.1 mrg stt %R1,%0 4563 1.1 mrg ftoit %1,%0 4564 1.1 mrg itoft %1,%0" 4565 1.1 mrg [(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst,ftoi,itof") 4566 1.1 mrg (set_attr "isa" "*,*,*,*,*,*,*,fix,fix")]) 4567 1.1 mrg 4568 1.1 mrg (define_insn "<code><mode>3" 4569 1.1 mrg [(set (match_operand:VEC12 0 "register_operand" "=r") 4570 1.1 mrg (any_maxmin:VEC12 4571 1.1 mrg (match_operand:VEC12 1 "reg_or_0_operand" "rW") 4572 1.1 mrg (match_operand:VEC12 2 "reg_or_0_operand" "rW")))] 4573 1.1 mrg "TARGET_MAX" 4574 1.1 mrg "<maxmin><modesuffix> %r1,%r2,%0" 4575 1.1 mrg [(set_attr "type" "mvi")]) 4576 1.1 mrg 4577 1.1 mrg (define_insn "one_cmpl<mode>2" 4578 1.1 mrg [(set (match_operand:VEC 0 "register_operand" "=r") 4579 1.1 mrg (not:VEC (match_operand:VEC 1 "register_operand" "r")))] 4580 1.1 mrg "" 4581 1.1 mrg "ornot $31,%1,%0" 4582 1.1 mrg [(set_attr "type" "ilog")]) 4583 1.1 mrg 4584 1.1 mrg (define_insn "and<mode>3" 4585 1.1 mrg [(set (match_operand:VEC 0 "register_operand" "=r") 4586 1.1 mrg (and:VEC (match_operand:VEC 1 "register_operand" "r") 4587 1.1 mrg (match_operand:VEC 2 "register_operand" "r")))] 4588 1.1 mrg "" 4589 1.1 mrg "and %1,%2,%0" 4590 1.1 mrg [(set_attr "type" "ilog")]) 4591 1.1 mrg 4592 1.1 mrg (define_insn "*andnot<mode>3" 4593 1.1 mrg [(set (match_operand:VEC 0 "register_operand" "=r") 4594 1.1 mrg (and:VEC (not:VEC (match_operand:VEC 1 "register_operand" "r")) 4595 1.1 mrg (match_operand:VEC 2 "register_operand" "r")))] 4596 1.1 mrg "" 4597 1.1 mrg "bic %2,%1,%0" 4598 1.1 mrg [(set_attr "type" "ilog")]) 4599 1.1 mrg 4600 1.1 mrg (define_insn "ior<mode>3" 4601 1.1 mrg [(set (match_operand:VEC 0 "register_operand" "=r") 4602 1.1 mrg (ior:VEC (match_operand:VEC 1 "register_operand" "r") 4603 1.1 mrg (match_operand:VEC 2 "register_operand" "r")))] 4604 1.1 mrg "" 4605 1.1 mrg "bis %1,%2,%0" 4606 1.1 mrg [(set_attr "type" "ilog")]) 4607 1.1 mrg 4608 1.1 mrg (define_insn "*iornot<mode>3" 4609 1.1 mrg [(set (match_operand:VEC 0 "register_operand" "=r") 4610 1.1 mrg (ior:VEC (not:DI (match_operand:VEC 1 "register_operand" "r")) 4611 1.1 mrg (match_operand:VEC 2 "register_operand" "r")))] 4612 1.1 mrg "" 4613 1.1 mrg "ornot %2,%1,%0" 4614 1.1 mrg [(set_attr "type" "ilog")]) 4615 1.1 mrg 4616 1.1.1.2 mrg (define_insn "xor<mode>3" 4617 1.1.1.2 mrg [(set (match_operand:VEC 0 "register_operand" "=r") 4618 1.1.1.2 mrg (xor:VEC (match_operand:VEC 1 "register_operand" "r") 4619 1.1 mrg (match_operand:VEC 2 "register_operand" "r")))] 4620 1.1 mrg "" 4621 1.1 mrg "xor %1,%2,%0" 4622 1.1 mrg [(set_attr "type" "ilog")]) 4623 1.1 mrg 4624 1.1 mrg (define_insn "*xornot<mode>3" 4625 1.1 mrg [(set (match_operand:VEC 0 "register_operand" "=r") 4626 1.1.1.2 mrg (not:VEC (xor:VEC (match_operand:VEC 1 "register_operand" "r") 4627 1.1.1.2 mrg (match_operand:VEC 2 "register_operand" "r"))))] 4628 1.1.1.2 mrg "" 4629 1.1 mrg "eqv %1,%2,%0" 4630 1.1 mrg [(set_attr "type" "ilog")]) 4631 1.1 mrg 4632 1.1 mrg (define_expand "vec_shl_<mode>" 4633 1.1 mrg [(set (match_operand:VEC 0 "register_operand") 4634 1.1 mrg (ashift:DI (match_operand:VEC 1 "register_operand") 4635 1.1 mrg (match_operand:DI 2 "reg_or_6bit_operand")))] 4636 1.1 mrg "" 4637 1.1.1.2 mrg { 4638 1.1.1.2 mrg operands[0] = gen_lowpart (DImode, operands[0]); 4639 1.1.1.2 mrg operands[1] = gen_lowpart (DImode, operands[1]); 4640 1.1.1.2 mrg }) 4641 1.1.1.2 mrg 4642 1.1 mrg (define_expand "vec_shr_<mode>" 4643 1.1 mrg [(set (match_operand:VEC 0 "register_operand") 4644 1.1 mrg (lshiftrt:DI (match_operand:VEC 1 "register_operand") 4645 1.1 mrg (match_operand:DI 2 "reg_or_6bit_operand")))] 4646 1.1 mrg "" 4647 1.1 mrg { 4648 1.1 mrg operands[0] = gen_lowpart (DImode, operands[0]); 4649 1.1 mrg operands[1] = gen_lowpart (DImode, operands[1]); 4650 1.1 mrg }) 4651 1.1 mrg 4653 1.1.1.2 mrg ;; Bit field extract patterns which use ext[wlq][lh] 4654 1.1 mrg 4655 1.1 mrg (define_expand "extvmisaligndi" 4656 1.1 mrg [(set (match_operand:DI 0 "register_operand") 4657 1.1.1.2 mrg (sign_extract:DI (match_operand:BLK 1 "memory_operand") 4658 1.1.1.2 mrg (match_operand:DI 2 "const_int_operand") 4659 1.1.1.2 mrg (match_operand:DI 3 "const_int_operand")))] 4660 1.1.1.2 mrg "" 4661 1.1.1.2 mrg { 4662 1.1 mrg /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */ 4663 1.1 mrg if (INTVAL (operands[3]) % 8 != 0 4664 1.1 mrg || (INTVAL (operands[2]) != 16 4665 1.1 mrg && INTVAL (operands[2]) != 32 4666 1.1 mrg && INTVAL (operands[2]) != 64)) 4667 1.1.1.2 mrg FAIL; 4668 1.1 mrg 4669 1.1 mrg alpha_expand_unaligned_load (operands[0], operands[1], 4670 1.1 mrg INTVAL (operands[2]) / 8, 4671 1.1.1.2 mrg INTVAL (operands[3]) / 8, 1); 4672 1.1 mrg DONE; 4673 1.1.1.2 mrg }) 4674 1.1.1.2 mrg 4675 1.1.1.2 mrg (define_expand "extzvdi" 4676 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand") 4677 1.1.1.2 mrg (zero_extract:DI (match_operand:DI 1 "register_operand") 4678 1.1.1.2 mrg (match_operand:DI 2 "const_int_operand") 4679 1.1.1.2 mrg (match_operand:DI 3 "const_int_operand")))] 4680 1.1.1.2 mrg "" 4681 1.1.1.2 mrg { 4682 1.1.1.2 mrg /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */ 4683 1.1.1.2 mrg if (INTVAL (operands[3]) % 8 != 0 4684 1.1.1.2 mrg || (INTVAL (operands[2]) != 8 4685 1.1.1.2 mrg && INTVAL (operands[2]) != 16 4686 1.1.1.2 mrg && INTVAL (operands[2]) != 32 4687 1.1 mrg && INTVAL (operands[2]) != 64)) 4688 1.1.1.2 mrg FAIL; 4689 1.1.1.2 mrg }) 4690 1.1.1.2 mrg 4691 1.1.1.2 mrg (define_expand "extzvmisaligndi" 4692 1.1 mrg [(set (match_operand:DI 0 "register_operand") 4693 1.1 mrg (zero_extract:DI (match_operand:BLK 1 "memory_operand") 4694 1.1.1.2 mrg (match_operand:DI 2 "const_int_operand") 4695 1.1.1.2 mrg (match_operand:DI 3 "const_int_operand")))] 4696 1.1.1.2 mrg "" 4697 1.1.1.2 mrg { 4698 1.1.1.2 mrg /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. 4699 1.1 mrg We fail 8-bit fields, falling back on a simple byte load. */ 4700 1.1 mrg if (INTVAL (operands[3]) % 8 != 0 4701 1.1 mrg || (INTVAL (operands[2]) != 16 4702 1.1 mrg && INTVAL (operands[2]) != 32 4703 1.1 mrg && INTVAL (operands[2]) != 64)) 4704 1.1 mrg FAIL; 4705 1.1 mrg 4706 1.1 mrg alpha_expand_unaligned_load (operands[0], operands[1], 4707 1.1 mrg INTVAL (operands[2]) / 8, 4708 1.1 mrg INTVAL (operands[3]) / 8, 0); 4709 1.1.1.2 mrg DONE; 4710 1.1.1.2 mrg }) 4711 1.1 mrg 4712 1.1 mrg (define_expand "insvmisaligndi" 4713 1.1 mrg [(set (zero_extract:DI (match_operand:BLK 0 "memory_operand") 4714 1.1 mrg (match_operand:DI 1 "const_int_operand") 4715 1.1 mrg (match_operand:DI 2 "const_int_operand")) 4716 1.1 mrg (match_operand:DI 3 "register_operand"))] 4717 1.1 mrg "" 4718 1.1 mrg { 4719 1.1 mrg /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */ 4720 1.1 mrg if (INTVAL (operands[2]) % 8 != 0 4721 1.1.1.2 mrg || (INTVAL (operands[1]) != 16 4722 1.1.1.2 mrg && INTVAL (operands[1]) != 32 4723 1.1.1.2 mrg && INTVAL (operands[1]) != 64)) 4724 1.1.1.2 mrg FAIL; 4725 1.1 mrg 4726 1.1 mrg alpha_expand_unaligned_store (operands[0], operands[3], 4727 1.1 mrg INTVAL (operands[1]) / 8, 4728 1.1 mrg INTVAL (operands[2]) / 8); 4729 1.1 mrg DONE; 4730 1.1 mrg }) 4731 1.1 mrg 4732 1.1 mrg ;; Block move/clear, see alpha.c for more details. 4733 1.1 mrg ;; Argument 0 is the destination 4734 1.1.1.2 mrg ;; Argument 1 is the source 4735 1.1.1.2 mrg ;; Argument 2 is the length 4736 1.1.1.2 mrg ;; Argument 3 is the alignment 4737 1.1.1.2 mrg 4738 1.1 mrg (define_expand "movmemqi" 4739 1.1 mrg [(parallel [(set (match_operand:BLK 0 "memory_operand") 4740 1.1 mrg (match_operand:BLK 1 "memory_operand")) 4741 1.1 mrg (use (match_operand:DI 2 "immediate_operand")) 4742 1.1 mrg (use (match_operand:DI 3 "immediate_operand"))])] 4743 1.1 mrg "" 4744 1.1 mrg { 4745 1.1 mrg if (alpha_expand_block_move (operands)) 4746 1.1 mrg DONE; 4747 1.1 mrg else 4748 1.1.1.2 mrg FAIL; 4749 1.1 mrg }) 4750 1.1 mrg 4751 1.1.1.3 mrg (define_expand "movmemdi" 4752 1.1 mrg [(parallel [(set (match_operand:BLK 0 "memory_operand") 4753 1.1 mrg (match_operand:BLK 1 "memory_operand")) 4754 1.1.1.2 mrg (use (match_operand:DI 2 "immediate_operand")) 4755 1.1 mrg (use (match_operand:DI 3 "immediate_operand")) 4756 1.1 mrg (use (match_dup 4)) 4757 1.1 mrg (clobber (reg:DI 25)) 4758 1.1 mrg (clobber (reg:DI 16)) 4759 1.1 mrg (clobber (reg:DI 17)) 4760 1.1 mrg (clobber (reg:DI 18)) 4761 1.1 mrg (clobber (reg:DI 19)) 4762 1.1 mrg (clobber (reg:DI 20)) 4763 1.1 mrg (clobber (reg:DI 26)) 4764 1.1 mrg (clobber (reg:DI 27))])] 4765 1.1 mrg "TARGET_ABI_OPEN_VMS" 4766 1.1.1.2 mrg "operands[4] = gen_rtx_SYMBOL_REF (Pmode, \"OTS$MOVE\");") 4767 1.1 mrg 4768 1.1 mrg (define_insn "*movmemdi_1" 4769 1.1 mrg [(set (match_operand:BLK 0 "memory_operand" "=m,m") 4770 1.1 mrg (match_operand:BLK 1 "memory_operand" "m,m")) 4771 1.1 mrg (use (match_operand:DI 2 "nonmemory_operand" "r,i")) 4772 1.1 mrg (use (match_operand:DI 3 "immediate_operand")) 4773 1.1 mrg (use (match_operand:DI 4 "call_operand" "i,i")) 4774 1.1 mrg (clobber (reg:DI 25)) 4775 1.1 mrg (clobber (reg:DI 16)) 4776 1.1 mrg (clobber (reg:DI 17)) 4777 1.1 mrg (clobber (reg:DI 18)) 4778 1.1 mrg (clobber (reg:DI 19)) 4779 1.1 mrg (clobber (reg:DI 20)) 4780 1.1 mrg (clobber (reg:DI 26)) 4781 1.1.1.2 mrg (clobber (reg:DI 27))] 4782 1.1.1.2 mrg "TARGET_ABI_OPEN_VMS" 4783 1.1.1.2 mrg { 4784 1.1.1.2 mrg operands [5] = alpha_use_linkage (operands [4], false, true); 4785 1.1 mrg switch (which_alternative) 4786 1.1 mrg { 4787 1.1 mrg case 0: 4788 1.1 mrg return "lda $16,%0\;bis $31,%2,$17\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)"; 4789 1.1 mrg case 1: 4790 1.1 mrg return "lda $16,%0\;lda $17,%2($31)\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)"; 4791 1.1 mrg default: 4792 1.1 mrg gcc_unreachable (); 4793 1.1 mrg } 4794 1.1 mrg } 4795 1.1 mrg [(set_attr "type" "multi") 4796 1.1 mrg (set_attr "length" "28")]) 4797 1.1 mrg 4798 1.1.1.2 mrg (define_expand "setmemqi" 4799 1.1.1.2 mrg [(parallel [(set (match_operand:BLK 0 "memory_operand") 4800 1.1.1.2 mrg (match_operand 2 "const_int_operand")) 4801 1.1.1.2 mrg (use (match_operand:DI 1 "immediate_operand")) 4802 1.1 mrg (use (match_operand:DI 3 "immediate_operand"))])] 4803 1.1 mrg "" 4804 1.1 mrg { 4805 1.1 mrg /* If value to set is not zero, use the library routine. */ 4806 1.1 mrg if (operands[2] != const0_rtx) 4807 1.1 mrg FAIL; 4808 1.1 mrg 4809 1.1 mrg if (alpha_expand_block_clear (operands)) 4810 1.1 mrg DONE; 4811 1.1 mrg else 4812 1.1 mrg FAIL; 4813 1.1 mrg }) 4814 1.1.1.2 mrg 4815 1.1 mrg (define_expand "setmemdi" 4816 1.1 mrg [(parallel [(set (match_operand:BLK 0 "memory_operand") 4817 1.1 mrg (match_operand 2 "const_int_operand")) 4818 1.1.1.3 mrg (use (match_operand:DI 1 "immediate_operand")) 4819 1.1 mrg (use (match_operand:DI 3 "immediate_operand")) 4820 1.1 mrg (use (match_dup 4)) 4821 1.1.1.2 mrg (clobber (reg:DI 25)) 4822 1.1 mrg (clobber (reg:DI 16)) 4823 1.1 mrg (clobber (reg:DI 17)) 4824 1.1 mrg (clobber (reg:DI 26)) 4825 1.1 mrg (clobber (reg:DI 27))])] 4826 1.1 mrg "TARGET_ABI_OPEN_VMS" 4827 1.1 mrg { 4828 1.1 mrg /* If value to set is not zero, use the library routine. */ 4829 1.1 mrg if (operands[2] != const0_rtx) 4830 1.1.1.2 mrg FAIL; 4831 1.1 mrg 4832 1.1 mrg operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$ZERO"); 4833 1.1 mrg }) 4834 1.1 mrg 4835 1.1 mrg (define_insn "*clrmemdi_1" 4836 1.1 mrg [(set (match_operand:BLK 0 "memory_operand" "=m,m") 4837 1.1 mrg (const_int 0)) 4838 1.1 mrg (use (match_operand:DI 1 "nonmemory_operand" "r,i")) 4839 1.1 mrg (use (match_operand:DI 2 "immediate_operand")) 4840 1.1 mrg (use (match_operand:DI 3 "call_operand" "i,i")) 4841 1.1 mrg (clobber (reg:DI 25)) 4842 1.1 mrg (clobber (reg:DI 16)) 4843 1.1 mrg (clobber (reg:DI 17)) 4844 1.1 mrg (clobber (reg:DI 26)) 4845 1.1 mrg (clobber (reg:DI 27))] 4846 1.1.1.5 mrg "TARGET_ABI_OPEN_VMS" 4847 1.1.1.2 mrg { 4848 1.1 mrg operands [4] = alpha_use_linkage (operands [3], false, true); 4849 1.1 mrg switch (which_alternative) 4850 1.1.1.2 mrg { 4851 1.1 mrg case 0: 4852 1.1 mrg return "lda $16,%0\;bis $31,%1,$17\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)"; 4853 1.1 mrg case 1: 4854 1.1 mrg return "lda $16,%0\;lda $17,%1($31)\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)"; 4855 1.1 mrg default: 4856 1.1 mrg gcc_unreachable (); 4857 1.1 mrg } 4858 1.1 mrg } 4859 1.1 mrg [(set_attr "type" "multi") 4860 1.1 mrg (set_attr "length" "24")]) 4861 1.1 mrg 4862 1.1 mrg 4864 1.1 mrg ;; Subroutine of stack space allocation. Perform a stack probe. 4865 1.1 mrg (define_expand "stack_probe_internal" 4866 1.1.1.2 mrg [(set (match_dup 1) (match_operand:DI 0 "const_int_operand"))] 4867 1.1 mrg "" 4868 1.1 mrg { 4869 1.1 mrg operands[1] = gen_rtx_MEM (DImode, plus_constant (Pmode, stack_pointer_rtx, 4870 1.1 mrg INTVAL (operands[0]))); 4871 1.1 mrg MEM_VOLATILE_P (operands[1]) = 1; 4872 1.1 mrg 4873 1.1 mrg operands[0] = const0_rtx; 4874 1.1 mrg }) 4875 1.1 mrg 4876 1.1 mrg ;; This is how we allocate stack space. If we are allocating a 4877 1.1 mrg ;; constant amount of space and we know it is less than 4096 4878 1.1 mrg ;; bytes, we need do nothing. 4879 1.1 mrg ;; 4880 1.1 mrg ;; If it is more than 4096 bytes, we need to probe the stack 4881 1.1.1.5 mrg ;; periodically. 4882 1.1 mrg (define_expand "allocate_stack" 4883 1.1.1.5 mrg [(set (reg:DI 30) 4884 1.1.1.5 mrg (plus:DI (reg:DI 30) 4885 1.1 mrg (match_operand:DI 1 "reg_or_cint_operand"))) 4886 1.1 mrg (set (match_operand:DI 0 "register_operand" "=r") 4887 1.1.1.5 mrg (match_dup 2))] 4888 1.1.1.5 mrg "" 4889 1.1 mrg { 4890 1.1 mrg if (CONST_INT_P (operands[1]) 4891 1.1 mrg && INTVAL (operands[1]) < 32768) 4892 1.1 mrg { 4893 1.1 mrg if (INTVAL (operands[1]) >= 4096) 4894 1.1 mrg { 4895 1.1 mrg /* We do this the same way as in the prologue and generate explicit 4896 1.1.1.3 mrg probes. Then we update the stack by the constant. */ 4897 1.1.1.3 mrg 4898 1.1 mrg int probed = 4096; 4899 1.1 mrg 4900 1.1 mrg emit_insn (gen_stack_probe_internal (GEN_INT (- probed))); 4901 1.1 mrg while (probed + 8192 < INTVAL (operands[1])) 4902 1.1 mrg emit_insn (gen_stack_probe_internal 4903 1.1 mrg (GEN_INT (- (probed += 8192)))); 4904 1.1 mrg 4905 1.1 mrg if (probed + 4096 < INTVAL (operands[1])) 4906 1.1 mrg emit_insn (gen_stack_probe_internal 4907 1.1.1.2 mrg (GEN_INT (- INTVAL(operands[1])))); 4908 1.1 mrg } 4909 1.1.1.2 mrg 4910 1.1.1.2 mrg operands[1] = GEN_INT (- INTVAL (operands[1])); 4911 1.1.1.2 mrg operands[2] = virtual_stack_dynamic_rtx; 4912 1.1 mrg } 4913 1.1 mrg else 4914 1.1.1.2 mrg { 4915 1.1 mrg rtx_code_label *out_label = 0; 4916 1.1 mrg rtx_code_label *loop_label = gen_label_rtx (); 4917 1.1 mrg rtx want = gen_reg_rtx (Pmode); 4918 1.1 mrg rtx tmp = gen_reg_rtx (Pmode); 4919 1.1 mrg rtx memref, test; 4920 1.1 mrg 4921 1.1 mrg emit_insn (gen_subdi3 (want, stack_pointer_rtx, 4922 1.1 mrg force_reg (Pmode, operands[1]))); 4923 1.1 mrg 4924 1.1 mrg if (!CONST_INT_P (operands[1])) 4925 1.1 mrg { 4926 1.1 mrg rtx limit = GEN_INT (4096); 4927 1.1 mrg out_label = gen_label_rtx (); 4928 1.1 mrg test = gen_rtx_LTU (VOIDmode, operands[1], limit); 4929 1.1 mrg emit_jump_insn 4930 1.1 mrg (gen_cbranchdi4 (test, operands[1], limit, out_label)); 4931 1.1 mrg } 4932 1.1 mrg 4933 1.1 mrg emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096))); 4934 1.1 mrg emit_label (loop_label); 4935 1.1 mrg memref = gen_rtx_MEM (DImode, tmp); 4936 1.1 mrg MEM_VOLATILE_P (memref) = 1; 4937 1.1 mrg emit_move_insn (memref, const0_rtx); 4938 1.1 mrg emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192))); 4939 1.1 mrg test = gen_rtx_GTU (VOIDmode, tmp, want); 4940 1.1 mrg emit_jump_insn (gen_cbranchdi4 (test, tmp, want, loop_label)); 4941 1.1 mrg 4942 1.1 mrg memref = gen_rtx_MEM (DImode, want); 4943 1.1 mrg MEM_VOLATILE_P (memref) = 1; 4944 1.1 mrg emit_move_insn (memref, const0_rtx); 4945 1.1 mrg 4946 1.1 mrg if (out_label) 4947 1.1 mrg emit_label (out_label); 4948 1.1 mrg 4949 1.1 mrg emit_move_insn (stack_pointer_rtx, want); 4950 1.1 mrg emit_move_insn (operands[0], virtual_stack_dynamic_rtx); 4951 1.1 mrg DONE; 4952 1.1 mrg } 4953 1.1 mrg }) 4954 1.1 mrg 4955 1.1 mrg ;; This is used by alpha_expand_prolog to do the same thing as above, 4956 1.1.1.2 mrg ;; except we cannot at that time generate new basic blocks, so we hide 4957 1.1 mrg ;; the loop in this one insn. 4958 1.1 mrg 4959 1.1 mrg (define_insn "prologue_stack_probe_loop" 4960 1.1 mrg [(unspec_volatile [(match_operand:DI 0 "register_operand" "r") 4961 1.1 mrg (match_operand:DI 1 "register_operand" "r")] 4962 1.1 mrg UNSPECV_PSPL)] 4963 1.1 mrg "" 4964 1.1 mrg { 4965 1.1 mrg operands[2] = gen_label_rtx (); 4966 1.1 mrg (*targetm.asm_out.internal_label) (asm_out_file, "L", 4967 1.1 mrg CODE_LABEL_NUMBER (operands[2])); 4968 1.1 mrg 4969 1.1 mrg return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2"; 4970 1.1 mrg } 4971 1.1 mrg [(set_attr "length" "16") 4972 1.1 mrg (set_attr "type" "multi")]) 4973 1.1 mrg 4974 1.1 mrg (define_expand "prologue" 4975 1.1 mrg [(const_int 0)] 4976 1.1 mrg "" 4977 1.1 mrg { 4978 1.1 mrg alpha_expand_prologue (); 4979 1.1 mrg DONE; 4980 1.1 mrg }) 4981 1.1 mrg 4982 1.1 mrg ;; These take care of emitting the ldgp insn in the prologue. This will be 4983 1.1 mrg ;; an lda/ldah pair and we want to align them properly. So we have two 4984 1.1 mrg ;; unspec_volatile insns, the first of which emits the ldgp assembler macro 4985 1.1 mrg ;; and the second of which emits nothing. However, both are marked as type 4986 1.1 mrg ;; IADD (the default) so the alignment code in alpha.c does the right thing 4987 1.1.1.2 mrg ;; with them. 4988 1.1 mrg 4989 1.1 mrg (define_expand "prologue_ldgp" 4990 1.1 mrg [(set (match_dup 0) 4991 1.1 mrg (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1)) 4992 1.1 mrg (set (match_dup 0) 4993 1.1 mrg (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))] 4994 1.1 mrg "" 4995 1.1 mrg { 4996 1.1.1.2 mrg operands[0] = pic_offset_table_rtx; 4997 1.1 mrg operands[1] = gen_rtx_REG (Pmode, 27); 4998 1.1 mrg operands[2] = (TARGET_EXPLICIT_RELOCS 4999 1.1 mrg ? GEN_INT (alpha_next_sequence_number++) 5000 1.1 mrg : const0_rtx); 5001 1.1 mrg }) 5002 1.1 mrg 5003 1.1 mrg (define_insn "*ldgp_er_1" 5004 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 5005 1.1.1.2 mrg (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") 5006 1.1 mrg (match_operand 2 "const_int_operand")] 5007 1.1 mrg UNSPECV_LDGP1))] 5008 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 5009 1.1 mrg "ldah %0,0(%1)\t\t!gpdisp!%2" 5010 1.1 mrg [(set_attr "cannot_copy" "true")]) 5011 1.1 mrg 5012 1.1 mrg (define_insn "*ldgp_er_2" 5013 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 5014 1.1.1.2 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "r") 5015 1.1 mrg (match_operand 2 "const_int_operand")] 5016 1.1 mrg UNSPEC_LDGP2))] 5017 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 5018 1.1 mrg "lda %0,0(%1)\t\t!gpdisp!%2" 5019 1.1 mrg [(set_attr "cannot_copy" "true")]) 5020 1.1 mrg 5021 1.1 mrg (define_insn "*prologue_ldgp_er_2" 5022 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 5023 1.1.1.2 mrg (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") 5024 1.1 mrg (match_operand 2 "const_int_operand")] 5025 1.1 mrg UNSPECV_PLDGP2))] 5026 1.1.1.2 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 5027 1.1 mrg "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:" 5028 1.1 mrg [(set_attr "cannot_copy" "true")]) 5029 1.1 mrg 5030 1.1 mrg (define_insn "*prologue_ldgp_1" 5031 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 5032 1.1 mrg (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") 5033 1.1 mrg (match_operand 2 "const_int_operand")] 5034 1.1 mrg UNSPECV_LDGP1))] 5035 1.1 mrg "" 5036 1.1 mrg "ldgp %0,0(%1)\n$%~..ng:" 5037 1.1 mrg [(set_attr "cannot_copy" "true")]) 5038 1.1 mrg 5039 1.1 mrg (define_insn "*prologue_ldgp_2" 5040 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 5041 1.1 mrg (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") 5042 1.1 mrg (match_operand 2 "const_int_operand")] 5043 1.1 mrg UNSPECV_PLDGP2))] 5044 1.1 mrg "" 5045 1.1 mrg ) 5046 1.1 mrg 5047 1.1 mrg ;; The _mcount profiling hook has special calling conventions, and 5048 1.1 mrg ;; does not clobber all the registers that a normal call would. So 5049 1.1 mrg ;; hide the fact this is a call at all. 5050 1.1 mrg 5051 1.1 mrg (define_insn "prologue_mcount" 5052 1.1 mrg [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)] 5053 1.1 mrg "" 5054 1.1 mrg { 5055 1.1 mrg if (TARGET_EXPLICIT_RELOCS) 5056 1.1.1.2 mrg /* Note that we cannot use a lituse_jsr reloc, since _mcount 5057 1.1 mrg cannot be called via the PLT. */ 5058 1.1 mrg return "ldq $28,_mcount($29)\t\t!literal\;jsr $28,($28),_mcount"; 5059 1.1 mrg else 5060 1.1 mrg return "lda $28,_mcount\;jsr $28,($28),_mcount"; 5061 1.1 mrg } 5062 1.1 mrg [(set_attr "type" "multi") 5063 1.1 mrg (set_attr "length" "8")]) 5064 1.1 mrg 5065 1.1 mrg (define_insn "init_fp" 5066 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 5067 1.1 mrg (match_operand:DI 1 "register_operand" "r")) 5068 1.1 mrg (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))] 5069 1.1 mrg "" 5070 1.1 mrg "bis $31,%1,%0") 5071 1.1 mrg 5072 1.1.1.2 mrg (define_expand "epilogue" 5073 1.1.1.2 mrg [(return)] 5074 1.1 mrg "" 5075 1.1 mrg "alpha_expand_epilogue ();") 5076 1.1 mrg 5077 1.1 mrg (define_expand "sibcall_epilogue" 5078 1.1 mrg [(return)] 5079 1.1.1.2 mrg "TARGET_ABI_OSF" 5080 1.1 mrg { 5081 1.1 mrg alpha_expand_epilogue (); 5082 1.1 mrg DONE; 5083 1.1 mrg }) 5084 1.1 mrg 5085 1.1 mrg (define_expand "builtin_longjmp" 5086 1.1 mrg [(use (match_operand:DI 0 "register_operand" "r"))] 5087 1.1 mrg "TARGET_ABI_OSF" 5088 1.1 mrg { 5089 1.1 mrg /* The elements of the buffer are, in order: */ 5090 1.1 mrg rtx fp = gen_rtx_MEM (Pmode, operands[0]); 5091 1.1 mrg rtx lab = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 8)); 5092 1.1 mrg rtx stack = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 16)); 5093 1.1 mrg rtx pv = gen_rtx_REG (Pmode, 27); 5094 1.1 mrg 5095 1.1 mrg /* This bit is the same as expand_builtin_longjmp. */ 5096 1.1 mrg emit_move_insn (hard_frame_pointer_rtx, fp); 5097 1.1 mrg emit_move_insn (pv, lab); 5098 1.1 mrg emit_stack_restore (SAVE_NONLOCAL, stack); 5099 1.1 mrg emit_use (hard_frame_pointer_rtx); 5100 1.1 mrg emit_use (stack_pointer_rtx); 5101 1.1 mrg 5102 1.1.1.2 mrg /* Load the label we are jumping through into $27 so that we know 5103 1.1.1.2 mrg where to look for it when we get back to setjmp's function for 5104 1.1 mrg restoring the gp. */ 5105 1.1 mrg emit_jump_insn (gen_builtin_longjmp_internal (pv)); 5106 1.1.1.2 mrg emit_barrier (); 5107 1.1 mrg DONE; 5108 1.1 mrg }) 5109 1.1 mrg 5110 1.1 mrg ;; This is effectively a copy of indirect_jump, but constrained such 5111 1.1 mrg ;; that register renaming cannot foil our cunning plan with $27. 5112 1.1 mrg (define_insn "builtin_longjmp_internal" 5113 1.1 mrg [(set (pc) 5114 1.1 mrg (unspec_volatile [(match_operand:DI 0 "register_operand" "c")] 5115 1.1 mrg UNSPECV_LONGJMP))] 5116 1.1 mrg "" 5117 1.1 mrg "jmp $31,(%0),0" 5118 1.1 mrg [(set_attr "type" "ibr")]) 5119 1.1 mrg 5120 1.1 mrg (define_expand "builtin_setjmp_receiver" 5121 1.1 mrg [(unspec_volatile [(label_ref (match_operand 0))] UNSPECV_SETJMPR)] 5122 1.1 mrg "TARGET_ABI_OSF") 5123 1.1 mrg 5124 1.1 mrg (define_insn_and_split "*builtin_setjmp_receiver_1" 5125 1.1 mrg [(unspec_volatile [(match_operand 0)] UNSPECV_SETJMPR)] 5126 1.1 mrg "TARGET_ABI_OSF" 5127 1.1 mrg { 5128 1.1 mrg if (TARGET_EXPLICIT_RELOCS) 5129 1.1 mrg return "#"; 5130 1.1 mrg else 5131 1.1.1.2 mrg return "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)"; 5132 1.1.1.2 mrg } 5133 1.1 mrg "&& TARGET_EXPLICIT_RELOCS && reload_completed" 5134 1.1 mrg [(set (match_dup 1) 5135 1.1 mrg (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1)) 5136 1.1 mrg (set (match_dup 1) 5137 1.1 mrg (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))] 5138 1.1 mrg { 5139 1.1 mrg if (prev_nonnote_insn (curr_insn) != XEXP (operands[0], 0)) 5140 1.1.1.2 mrg emit_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode, gen_rtvec (1, operands[0]), 5141 1.1 mrg UNSPECV_SETJMPR_ER)); 5142 1.1 mrg operands[1] = pic_offset_table_rtx; 5143 1.1 mrg operands[2] = gen_rtx_REG (Pmode, 27); 5144 1.1 mrg operands[3] = GEN_INT (alpha_next_sequence_number++); 5145 1.1 mrg } 5146 1.1.1.2 mrg [(set_attr "length" "12") 5147 1.1 mrg (set_attr "type" "multi")]) 5148 1.1 mrg 5149 1.1 mrg (define_insn "*builtin_setjmp_receiver_er_sl_1" 5150 1.1 mrg [(unspec_volatile [(match_operand 0)] UNSPECV_SETJMPR_ER)] 5151 1.1 mrg "TARGET_ABI_OSF && TARGET_EXPLICIT_RELOCS" 5152 1.1 mrg "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:") 5153 1.1 mrg 5154 1.1.1.2 mrg ;; When flag_reorder_blocks_and_partition is in effect, compiler puts 5155 1.1 mrg ;; exception landing pads in a cold section. To prevent inter-section offset 5156 1.1 mrg ;; calculation, a jump to original landing pad is emitted in the place of the 5157 1.1 mrg ;; original landing pad. Since landing pad is moved, RA-relative GP 5158 1.1 mrg ;; calculation in the prologue of landing pad breaks. To solve this problem, 5159 1.1 mrg ;; we use alternative GP load approach. 5160 1.1 mrg 5161 1.1 mrg (define_expand "exception_receiver" 5162 1.1 mrg [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)] 5163 1.1.1.3 mrg "TARGET_ABI_OSF" 5164 1.1 mrg { 5165 1.1 mrg if (flag_reorder_blocks_and_partition) 5166 1.1 mrg operands[0] = alpha_gp_save_rtx (); 5167 1.1 mrg else 5168 1.1 mrg operands[0] = const0_rtx; 5169 1.1 mrg }) 5170 1.1 mrg 5171 1.1 mrg (define_insn "*exception_receiver_2" 5172 1.1 mrg [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_EHR)] 5173 1.1 mrg "TARGET_ABI_OSF && flag_reorder_blocks_and_partition" 5174 1.1 mrg "ldq $29,%0" 5175 1.1 mrg [(set_attr "type" "ild")]) 5176 1.1 mrg 5177 1.1 mrg (define_insn_and_split "*exception_receiver_1" 5178 1.1 mrg [(unspec_volatile [(const_int 0)] UNSPECV_EHR)] 5179 1.1 mrg "TARGET_ABI_OSF" 5180 1.1 mrg { 5181 1.1 mrg if (TARGET_EXPLICIT_RELOCS) 5182 1.1 mrg return "#"; 5183 1.1 mrg else 5184 1.1 mrg return "ldgp $29,0($26)"; 5185 1.1.1.2 mrg } 5186 1.1 mrg "&& TARGET_EXPLICIT_RELOCS && reload_completed" 5187 1.1 mrg [(set (match_dup 0) 5188 1.1 mrg (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1)) 5189 1.1 mrg (set (match_dup 0) 5190 1.1 mrg (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))] 5191 1.1 mrg { 5192 1.1 mrg operands[0] = pic_offset_table_rtx; 5193 1.1 mrg operands[1] = gen_rtx_REG (Pmode, 26); 5194 1.1 mrg operands[2] = GEN_INT (alpha_next_sequence_number++); 5195 1.1 mrg } 5196 1.1 mrg [(set_attr "length" "8") 5197 1.1 mrg (set_attr "type" "multi")]) 5198 1.1 mrg 5199 1.1 mrg (define_expand "nonlocal_goto_receiver" 5200 1.1 mrg [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE) 5201 1.1 mrg (set (reg:DI 27) (mem:DI (reg:DI 29))) 5202 1.1 mrg (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE) 5203 1.1 mrg (use (reg:DI 27))] 5204 1.1 mrg "TARGET_ABI_OPEN_VMS") 5205 1.1 mrg 5206 1.1 mrg (define_insn "arg_home" 5207 1.1 mrg [(unspec [(const_int 0)] UNSPEC_ARG_HOME) 5208 1.1 mrg (use (reg:DI 1)) 5209 1.1 mrg (use (reg:DI 25)) 5210 1.1 mrg (use (reg:DI 16)) 5211 1.1 mrg (use (reg:DI 17)) 5212 1.1 mrg (use (reg:DI 18)) 5213 1.1 mrg (use (reg:DI 19)) 5214 1.1 mrg (use (reg:DI 20)) 5215 1.1 mrg (use (reg:DI 21)) 5216 1.1 mrg (use (reg:DI 48)) 5217 1.1 mrg (use (reg:DI 49)) 5218 1.1 mrg (use (reg:DI 50)) 5219 1.1 mrg (use (reg:DI 51)) 5220 1.1 mrg (use (reg:DI 52)) 5221 1.1 mrg (use (reg:DI 53)) 5222 1.1 mrg (clobber (mem:BLK (const_int 0))) 5223 1.1 mrg (clobber (reg:DI 24)) 5224 1.1 mrg (clobber (reg:DI 25)) 5225 1.1 mrg (clobber (reg:DI 0))] 5226 1.1 mrg "TARGET_ABI_OPEN_VMS" 5227 1.1 mrg "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS" 5228 1.1 mrg [(set_attr "length" "16") 5229 1.1 mrg (set_attr "type" "multi")]) 5230 1.1 mrg 5231 1.1 mrg ;; Prefetch data. 5232 1.1 mrg ;; 5233 1.1 mrg ;; On EV4, these instructions are nops -- no load occurs. 5234 1.1 mrg ;; 5235 1.1 mrg ;; On EV5, these instructions act as a normal load, and thus can trap 5236 1.1 mrg ;; if the address is invalid. The OS may (or may not) handle this in 5237 1.1 mrg ;; the entMM fault handler and suppress the fault. If so, then this 5238 1.1 mrg ;; has the effect of a read prefetch instruction. 5239 1.1 mrg ;; 5240 1.1 mrg ;; On EV6, these become official prefetch instructions. 5241 1.1 mrg 5242 1.1 mrg (define_insn "prefetch" 5243 1.1 mrg [(prefetch (match_operand:DI 0 "address_operand" "p") 5244 1.1 mrg (match_operand:DI 1 "const_int_operand" "n") 5245 1.1 mrg (match_operand:DI 2 "const_int_operand" "n"))] 5246 1.1 mrg "TARGET_FIXUP_EV5_PREFETCH || alpha_cpu == PROCESSOR_EV6" 5247 1.1 mrg { 5248 1.1 mrg /* Interpret "no temporal locality" as this data should be evicted once 5249 1.1 mrg it is used. The "evict next" alternatives load the data into the cache 5250 1.1 mrg and leave the LRU eviction counter pointing to that block. */ 5251 1.1 mrg static const char * const alt[2][2] = { 5252 1.1 mrg { 5253 1.1 mrg "ldq $31,%a0", /* read, evict next */ 5254 1.1 mrg "ldl $31,%a0", /* read, evict last */ 5255 1.1 mrg }, 5256 1.1 mrg { 5257 1.1 mrg "ldt $f31,%a0", /* write, evict next */ 5258 1.1 mrg "lds $f31,%a0", /* write, evict last */ 5259 1.1 mrg } 5260 1.1 mrg }; 5261 1.1 mrg 5262 1.1 mrg bool write = INTVAL (operands[1]) != 0; 5263 1.1 mrg bool lru = INTVAL (operands[2]) != 0; 5264 1.1 mrg 5265 1.1 mrg return alt[write][lru]; 5266 1.1 mrg } 5267 1.1 mrg [(set_attr "type" "ild")]) 5268 1.1 mrg 5269 1.1 mrg ;; Close the trap shadow of preceding instructions. This is generated 5270 1.1 mrg ;; by alpha_reorg. 5271 1.1 mrg 5272 1.1 mrg (define_insn "trapb" 5273 1.1 mrg [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)] 5274 1.1 mrg "" 5275 1.1 mrg "trapb" 5276 1.1 mrg [(set_attr "type" "misc")]) 5277 1.1 mrg 5278 1.1 mrg ;; No-op instructions used by machine-dependent reorg to preserve 5279 1.1 mrg ;; alignment for instruction issue. 5280 1.1 mrg ;; The Unicos/Mk assembler does not support these opcodes. 5281 1.1 mrg 5282 1.1 mrg (define_insn "nop" 5283 1.1 mrg [(const_int 0)] 5284 1.1.1.2 mrg "" 5285 1.1 mrg "bis $31,$31,$31" 5286 1.1 mrg [(set_attr "type" "ilog")]) 5287 1.1 mrg 5288 1.1 mrg (define_insn "fnop" 5289 1.1 mrg [(const_int 1)] 5290 1.1 mrg "TARGET_FP" 5291 1.1 mrg "cpys $f31,$f31,$f31" 5292 1.1 mrg [(set_attr "type" "fcpys")]) 5293 1.1 mrg 5294 1.1 mrg (define_insn "unop" 5295 1.1 mrg [(const_int 2)] 5296 1.1 mrg "" 5297 1.1 mrg "ldq_u $31,0($30)") 5298 1.1 mrg 5299 1.1.1.2 mrg (define_insn "realign" 5300 1.1.1.2 mrg [(unspec_volatile [(match_operand 0 "immediate_operand" "i")] 5301 1.1.1.2 mrg UNSPECV_REALIGN)] 5302 1.1.1.2 mrg "" 5303 1.1 mrg ".align %0 #realign") 5304 1.1 mrg 5306 1.1 mrg ;; Instructions to be emitted from __builtins. 5307 1.1 mrg 5308 1.1 mrg (define_insn "builtin_cmpbge" 5309 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand" "=r") 5310 1.1.1.2 mrg (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rJ") 5311 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand" "rI")] 5312 1.1.1.2 mrg UNSPEC_CMPBGE))] 5313 1.1 mrg "" 5314 1.1 mrg "cmpbge %r1,%2,%0" 5315 1.1.1.2 mrg ;; The EV6 data sheets list this as ILOG. OTOH, EV6 doesn't 5316 1.1 mrg ;; actually differentiate between ILOG and ICMP in the schedule. 5317 1.1 mrg [(set_attr "type" "icmp")]) 5318 1.1 mrg 5319 1.1.1.2 mrg (define_expand "extbl" 5320 1.1.1.2 mrg [(match_operand:DI 0 "register_operand") 5321 1.1.1.2 mrg (match_operand:DI 1 "reg_or_0_operand") 5322 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5323 1.1 mrg "" 5324 1.1 mrg { 5325 1.1.1.2 mrg emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (8), operands[2])); 5326 1.1 mrg DONE; 5327 1.1 mrg }) 5328 1.1 mrg 5329 1.1.1.2 mrg (define_expand "extwl" 5330 1.1.1.2 mrg [(match_operand:DI 0 "register_operand") 5331 1.1.1.2 mrg (match_operand:DI 1 "reg_or_0_operand") 5332 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5333 1.1 mrg "" 5334 1.1 mrg { 5335 1.1.1.2 mrg emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (16), operands[2])); 5336 1.1 mrg DONE; 5337 1.1 mrg }) 5338 1.1 mrg 5339 1.1 mrg (define_expand "extll" 5340 1.1.1.2 mrg [(match_operand:DI 0 "register_operand") 5341 1.1.1.2 mrg (match_operand:DI 1 "reg_or_0_operand") 5342 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5343 1.1 mrg "" 5344 1.1 mrg { 5345 1.1 mrg emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (32), operands[2])); 5346 1.1.1.2 mrg DONE; 5347 1.1 mrg }) 5348 1.1 mrg 5349 1.1 mrg (define_expand "extql" 5350 1.1 mrg [(match_operand:DI 0 "register_operand") 5351 1.1.1.2 mrg (match_operand:DI 1 "reg_or_0_operand") 5352 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5353 1.1.1.2 mrg "" 5354 1.1 mrg { 5355 1.1 mrg emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (64), operands[2])); 5356 1.1 mrg DONE; 5357 1.1.1.2 mrg }) 5358 1.1 mrg 5359 1.1 mrg (define_expand "builtin_insbl" 5360 1.1 mrg [(match_operand:DI 0 "register_operand") 5361 1.1 mrg (match_operand:DI 1 "register_operand") 5362 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5363 1.1.1.2 mrg "" 5364 1.1.1.2 mrg { 5365 1.1 mrg operands[1] = gen_lowpart (QImode, operands[1]); 5366 1.1 mrg emit_insn (gen_insbl (operands[0], operands[1], operands[2])); 5367 1.1 mrg DONE; 5368 1.1.1.2 mrg }) 5369 1.1 mrg 5370 1.1 mrg (define_expand "builtin_inswl" 5371 1.1 mrg [(match_operand:DI 0 "register_operand") 5372 1.1.1.2 mrg (match_operand:DI 1 "register_operand") 5373 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5374 1.1.1.2 mrg "" 5375 1.1.1.2 mrg { 5376 1.1 mrg operands[1] = gen_lowpart (HImode, operands[1]); 5377 1.1 mrg emit_insn (gen_inswl (operands[0], operands[1], operands[2])); 5378 1.1 mrg DONE; 5379 1.1 mrg }) 5380 1.1 mrg 5381 1.1 mrg (define_expand "builtin_insll" 5382 1.1.1.2 mrg [(match_operand:DI 0 "register_operand") 5383 1.1.1.2 mrg (match_operand:DI 1 "register_operand") 5384 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5385 1.1.1.2 mrg "" 5386 1.1 mrg { 5387 1.1 mrg operands[1] = gen_lowpart (SImode, operands[1]); 5388 1.1 mrg emit_insn (gen_insll (operands[0], operands[1], operands[2])); 5389 1.1 mrg DONE; 5390 1.1 mrg }) 5391 1.1 mrg 5392 1.1.1.2 mrg (define_expand "inswh" 5393 1.1.1.2 mrg [(match_operand:DI 0 "register_operand") 5394 1.1.1.2 mrg (match_operand:DI 1 "register_operand") 5395 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5396 1.1 mrg "" 5397 1.1 mrg { 5398 1.1 mrg emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2])); 5399 1.1 mrg DONE; 5400 1.1 mrg }) 5401 1.1 mrg 5402 1.1.1.2 mrg (define_expand "inslh" 5403 1.1.1.2 mrg [(match_operand:DI 0 "register_operand") 5404 1.1.1.2 mrg (match_operand:DI 1 "register_operand") 5405 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5406 1.1 mrg "" 5407 1.1 mrg { 5408 1.1.1.2 mrg emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2])); 5409 1.1.1.2 mrg DONE; 5410 1.1 mrg }) 5411 1.1 mrg 5412 1.1 mrg (define_expand "insqh" 5413 1.1.1.2 mrg [(match_operand:DI 0 "register_operand") 5414 1.1.1.2 mrg (match_operand:DI 1 "register_operand") 5415 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5416 1.1.1.2 mrg "" 5417 1.1 mrg { 5418 1.1 mrg emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2])); 5419 1.1.1.2 mrg DONE; 5420 1.1.1.2 mrg }) 5421 1.1 mrg 5422 1.1 mrg (define_expand "mskbl" 5423 1.1 mrg [(match_operand:DI 0 "register_operand") 5424 1.1.1.2 mrg (match_operand:DI 1 "reg_or_0_operand") 5425 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5426 1.1.1.2 mrg "" 5427 1.1.1.2 mrg { 5428 1.1 mrg rtx mask = GEN_INT (0xff); 5429 1.1 mrg emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2])); 5430 1.1.1.4 mrg DONE; 5431 1.1.1.2 mrg }) 5432 1.1 mrg 5433 1.1 mrg (define_expand "mskwl" 5434 1.1 mrg [(match_operand:DI 0 "register_operand") 5435 1.1.1.2 mrg (match_operand:DI 1 "reg_or_0_operand") 5436 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5437 1.1.1.2 mrg "" 5438 1.1.1.2 mrg { 5439 1.1 mrg rtx mask = GEN_INT (0xffff); 5440 1.1 mrg emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2])); 5441 1.1.1.2 mrg DONE; 5442 1.1.1.2 mrg }) 5443 1.1 mrg 5444 1.1 mrg (define_expand "mskll" 5445 1.1 mrg [(match_operand:DI 0 "register_operand") 5446 1.1.1.2 mrg (match_operand:DI 1 "reg_or_0_operand") 5447 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5448 1.1.1.2 mrg "" 5449 1.1.1.2 mrg { 5450 1.1 mrg rtx mask = gen_int_mode (0xffffffff, DImode); 5451 1.1 mrg emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2])); 5452 1.1 mrg DONE; 5453 1.1 mrg }) 5454 1.1 mrg 5455 1.1 mrg (define_expand "mskql" 5456 1.1.1.2 mrg [(match_operand:DI 0 "register_operand") 5457 1.1.1.2 mrg (match_operand:DI 1 "reg_or_0_operand") 5458 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5459 1.1.1.2 mrg "" 5460 1.1 mrg { 5461 1.1 mrg rtx mask = constm1_rtx; 5462 1.1 mrg emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2])); 5463 1.1 mrg DONE; 5464 1.1 mrg }) 5465 1.1 mrg 5466 1.1.1.2 mrg (define_expand "mskwh" 5467 1.1.1.2 mrg [(match_operand:DI 0 "register_operand") 5468 1.1.1.2 mrg (match_operand:DI 1 "register_operand") 5469 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5470 1.1 mrg "" 5471 1.1 mrg { 5472 1.1 mrg emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2])); 5473 1.1 mrg DONE; 5474 1.1 mrg }) 5475 1.1 mrg 5476 1.1 mrg (define_expand "msklh" 5477 1.1.1.2 mrg [(match_operand:DI 0 "register_operand") 5478 1.1 mrg (match_operand:DI 1 "register_operand") 5479 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5480 1.1 mrg "" 5481 1.1.1.2 mrg { 5482 1.1 mrg emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2])); 5483 1.1 mrg DONE; 5484 1.1 mrg }) 5485 1.1 mrg 5486 1.1 mrg (define_expand "mskqh" 5487 1.1 mrg [(match_operand:DI 0 "register_operand") 5488 1.1 mrg (match_operand:DI 1 "register_operand") 5489 1.1 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5490 1.1 mrg "" 5491 1.1 mrg { 5492 1.1 mrg emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2])); 5493 1.1 mrg DONE; 5494 1.1 mrg }) 5495 1.1 mrg 5496 1.1 mrg (define_expand "builtin_zap" 5497 1.1 mrg [(set (match_operand:DI 0 "register_operand") 5498 1.1 mrg (and:DI (unspec:DI 5499 1.1 mrg [(match_operand:DI 2 "reg_or_cint_operand")] 5500 1.1 mrg UNSPEC_ZAP) 5501 1.1 mrg (match_operand:DI 1 "reg_or_cint_operand")))] 5502 1.1 mrg "" 5503 1.1 mrg { 5504 1.1 mrg if (CONST_INT_P (operands[2])) 5505 1.1 mrg { 5506 1.1 mrg rtx mask = alpha_expand_zap_mask (INTVAL (operands[2])); 5507 1.1 mrg 5508 1.1 mrg if (mask == const0_rtx) 5509 1.1 mrg { 5510 1.1 mrg emit_move_insn (operands[0], const0_rtx); 5511 1.1 mrg DONE; 5512 1.1 mrg } 5513 1.1 mrg if (mask == constm1_rtx) 5514 1.1 mrg { 5515 1.1 mrg emit_move_insn (operands[0], operands[1]); 5516 1.1 mrg DONE; 5517 1.1 mrg } 5518 1.1 mrg 5519 1.1 mrg operands[1] = force_reg (DImode, operands[1]); 5520 1.1 mrg emit_insn (gen_anddi3 (operands[0], operands[1], mask)); 5521 1.1 mrg DONE; 5522 1.1 mrg } 5523 1.1.1.2 mrg 5524 1.1 mrg operands[1] = force_reg (DImode, operands[1]); 5525 1.1.1.2 mrg operands[2] = gen_lowpart (QImode, operands[2]); 5526 1.1 mrg }) 5527 1.1.1.2 mrg 5528 1.1 mrg (define_insn "*builtin_zap_1" 5529 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r,r,r,r") 5530 1.1 mrg (and:DI (unspec:DI 5531 1.1 mrg [(match_operand:QI 2 "reg_or_cint_operand" "n,n,r,r")] 5532 1.1.1.4 mrg UNSPEC_ZAP) 5533 1.1.1.4 mrg (match_operand:DI 1 "reg_or_cint_operand" "n,r,J,r")))] 5534 1.1 mrg "" 5535 1.1 mrg "@ 5536 1.1 mrg # 5537 1.1 mrg # 5538 1.1 mrg bis $31,$31,%0 5539 1.1.1.2 mrg zap %r1,%2,%0" 5540 1.1 mrg [(set_attr "type" "shift,shift,ilog,shift")]) 5541 1.1.1.2 mrg 5542 1.1 mrg (define_split 5543 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand") 5544 1.1 mrg (and:DI (unspec:DI 5545 1.1 mrg [(match_operand:QI 2 "const_int_operand")] 5546 1.1 mrg UNSPEC_ZAP) 5547 1.1 mrg (match_operand:DI 1 "const_int_operand")))] 5548 1.1 mrg "" 5549 1.1 mrg [(const_int 0)] 5550 1.1 mrg { 5551 1.1 mrg rtx mask = alpha_expand_zap_mask (INTVAL (operands[2])); 5552 1.1 mrg 5553 1.1 mrg operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode); 5554 1.1 mrg emit_move_insn (operands[0], operands[1]); 5555 1.1 mrg DONE; 5556 1.1 mrg }) 5557 1.1 mrg 5558 1.1 mrg (define_split 5559 1.1 mrg [(set (match_operand:DI 0 "register_operand") 5560 1.1 mrg (and:DI (unspec:DI 5561 1.1 mrg [(match_operand:QI 2 "const_int_operand")] 5562 1.1.1.2 mrg UNSPEC_ZAP) 5563 1.1 mrg (match_operand:DI 1 "register_operand")))] 5564 1.1.1.2 mrg "" 5565 1.1 mrg [(set (match_dup 0) 5566 1.1.1.2 mrg (and:DI (match_dup 1) (match_dup 2)))] 5567 1.1 mrg { 5568 1.1 mrg operands[2] = alpha_expand_zap_mask (INTVAL (operands[2])); 5569 1.1 mrg if (operands[2] == const0_rtx) 5570 1.1 mrg { 5571 1.1 mrg emit_move_insn (operands[0], const0_rtx); 5572 1.1 mrg DONE; 5573 1.1 mrg } 5574 1.1 mrg if (operands[2] == constm1_rtx) 5575 1.1 mrg { 5576 1.1 mrg emit_move_insn (operands[0], operands[1]); 5577 1.1 mrg DONE; 5578 1.1 mrg } 5579 1.1 mrg }) 5580 1.1 mrg 5581 1.1 mrg (define_expand "builtin_zapnot" 5582 1.1 mrg [(set (match_operand:DI 0 "register_operand") 5583 1.1 mrg (and:DI (unspec:DI 5584 1.1 mrg [(not:QI (match_operand:DI 2 "reg_or_cint_operand"))] 5585 1.1 mrg UNSPEC_ZAP) 5586 1.1 mrg (match_operand:DI 1 "reg_or_cint_operand")))] 5587 1.1 mrg "" 5588 1.1 mrg { 5589 1.1 mrg if (CONST_INT_P (operands[2])) 5590 1.1 mrg { 5591 1.1 mrg rtx mask = alpha_expand_zap_mask (~ INTVAL (operands[2])); 5592 1.1 mrg 5593 1.1 mrg if (mask == const0_rtx) 5594 1.1 mrg { 5595 1.1 mrg emit_move_insn (operands[0], const0_rtx); 5596 1.1 mrg DONE; 5597 1.1 mrg } 5598 1.1 mrg if (mask == constm1_rtx) 5599 1.1 mrg { 5600 1.1 mrg emit_move_insn (operands[0], operands[1]); 5601 1.1 mrg DONE; 5602 1.1 mrg } 5603 1.1 mrg 5604 1.1 mrg operands[1] = force_reg (DImode, operands[1]); 5605 1.1 mrg emit_insn (gen_anddi3 (operands[0], operands[1], mask)); 5606 1.1 mrg DONE; 5607 1.1 mrg } 5608 1.1 mrg 5609 1.1 mrg operands[1] = force_reg (DImode, operands[1]); 5610 1.1 mrg operands[2] = gen_lowpart (QImode, operands[2]); 5611 1.1 mrg }) 5612 1.1 mrg 5613 1.1 mrg (define_insn "*builtin_zapnot_1" 5614 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 5615 1.1 mrg (and:DI (unspec:DI 5616 1.1 mrg [(not:QI (match_operand:QI 2 "register_operand" "r"))] 5617 1.1 mrg UNSPEC_ZAP) 5618 1.1 mrg (match_operand:DI 1 "reg_or_0_operand" "rJ")))] 5619 1.1 mrg "" 5620 1.1 mrg "zapnot %r1,%2,%0" 5621 1.1 mrg [(set_attr "type" "shift")]) 5622 1.1 mrg 5623 1.1 mrg (define_insn "builtin_amask" 5624 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 5625 1.1 mrg (unspec:DI [(match_operand:DI 1 "reg_or_8bit_operand" "rI")] 5626 1.1.1.2 mrg UNSPEC_AMASK))] 5627 1.1.1.2 mrg "" 5628 1.1.1.2 mrg "amask %1,%0" 5629 1.1 mrg [(set_attr "type" "ilog")]) 5630 1.1 mrg 5631 1.1 mrg (define_insn "builtin_implver" 5632 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 5633 1.1 mrg (unspec:DI [(const_int 0)] UNSPEC_IMPLVER))] 5634 1.1 mrg "" 5635 1.1 mrg "implver %0" 5636 1.1 mrg [(set_attr "type" "ilog")]) 5637 1.1.1.2 mrg 5638 1.1.1.2 mrg (define_insn "builtin_rpcc" 5639 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand" "=r") 5640 1.1 mrg (unspec_volatile:DI [(const_int 0)] UNSPECV_RPCC))] 5641 1.1 mrg "" 5642 1.1 mrg "rpcc %0" 5643 1.1 mrg [(set_attr "type" "ilog")]) 5644 1.1 mrg 5645 1.1 mrg (define_expand "builtin_minub8" 5646 1.1 mrg [(match_operand:DI 0 "register_operand") 5647 1.1 mrg (match_operand:DI 1 "reg_or_0_operand") 5648 1.1.1.2 mrg (match_operand:DI 2 "reg_or_0_operand")] 5649 1.1.1.2 mrg "TARGET_MAX" 5650 1.1.1.2 mrg { 5651 1.1 mrg alpha_expand_builtin_vector_binop (gen_uminv8qi3, V8QImode, operands[0], 5652 1.1 mrg operands[1], operands[2]); 5653 1.1 mrg DONE; 5654 1.1 mrg }) 5655 1.1 mrg 5656 1.1 mrg (define_expand "builtin_minsb8" 5657 1.1 mrg [(match_operand:DI 0 "register_operand") 5658 1.1 mrg (match_operand:DI 1 "reg_or_0_operand") 5659 1.1.1.2 mrg (match_operand:DI 2 "reg_or_0_operand")] 5660 1.1.1.2 mrg "TARGET_MAX" 5661 1.1.1.2 mrg { 5662 1.1 mrg alpha_expand_builtin_vector_binop (gen_sminv8qi3, V8QImode, operands[0], 5663 1.1 mrg operands[1], operands[2]); 5664 1.1 mrg DONE; 5665 1.1 mrg }) 5666 1.1 mrg 5667 1.1 mrg (define_expand "builtin_minuw4" 5668 1.1 mrg [(match_operand:DI 0 "register_operand") 5669 1.1 mrg (match_operand:DI 1 "reg_or_0_operand") 5670 1.1.1.2 mrg (match_operand:DI 2 "reg_or_0_operand")] 5671 1.1.1.2 mrg "TARGET_MAX" 5672 1.1.1.2 mrg { 5673 1.1 mrg alpha_expand_builtin_vector_binop (gen_uminv4hi3, V4HImode, operands[0], 5674 1.1 mrg operands[1], operands[2]); 5675 1.1 mrg DONE; 5676 1.1 mrg }) 5677 1.1 mrg 5678 1.1 mrg (define_expand "builtin_minsw4" 5679 1.1 mrg [(match_operand:DI 0 "register_operand") 5680 1.1 mrg (match_operand:DI 1 "reg_or_0_operand") 5681 1.1.1.2 mrg (match_operand:DI 2 "reg_or_0_operand")] 5682 1.1.1.2 mrg "TARGET_MAX" 5683 1.1.1.2 mrg { 5684 1.1 mrg alpha_expand_builtin_vector_binop (gen_sminv4hi3, V4HImode, operands[0], 5685 1.1 mrg operands[1], operands[2]); 5686 1.1 mrg DONE; 5687 1.1 mrg }) 5688 1.1 mrg 5689 1.1 mrg (define_expand "builtin_maxub8" 5690 1.1 mrg [(match_operand:DI 0 "register_operand") 5691 1.1 mrg (match_operand:DI 1 "reg_or_0_operand") 5692 1.1.1.2 mrg (match_operand:DI 2 "reg_or_0_operand")] 5693 1.1.1.2 mrg "TARGET_MAX" 5694 1.1.1.2 mrg { 5695 1.1 mrg alpha_expand_builtin_vector_binop (gen_umaxv8qi3, V8QImode, operands[0], 5696 1.1 mrg operands[1], operands[2]); 5697 1.1 mrg DONE; 5698 1.1 mrg }) 5699 1.1 mrg 5700 1.1 mrg (define_expand "builtin_maxsb8" 5701 1.1 mrg [(match_operand:DI 0 "register_operand") 5702 1.1 mrg (match_operand:DI 1 "reg_or_0_operand") 5703 1.1.1.2 mrg (match_operand:DI 2 "reg_or_0_operand")] 5704 1.1.1.2 mrg "TARGET_MAX" 5705 1.1.1.2 mrg { 5706 1.1 mrg alpha_expand_builtin_vector_binop (gen_smaxv8qi3, V8QImode, operands[0], 5707 1.1 mrg operands[1], operands[2]); 5708 1.1 mrg DONE; 5709 1.1 mrg }) 5710 1.1 mrg 5711 1.1 mrg (define_expand "builtin_maxuw4" 5712 1.1 mrg [(match_operand:DI 0 "register_operand") 5713 1.1 mrg (match_operand:DI 1 "reg_or_0_operand") 5714 1.1 mrg (match_operand:DI 2 "reg_or_0_operand")] 5715 1.1 mrg "TARGET_MAX" 5716 1.1 mrg { 5717 1.1 mrg alpha_expand_builtin_vector_binop (gen_umaxv4hi3, V4HImode, operands[0], 5718 1.1 mrg operands[1], operands[2]); 5719 1.1 mrg DONE; 5720 1.1 mrg }) 5721 1.1 mrg 5722 1.1 mrg (define_expand "builtin_maxsw4" 5723 1.1.1.2 mrg [(match_operand:DI 0 "register_operand") 5724 1.1 mrg (match_operand:DI 1 "reg_or_0_operand") 5725 1.1 mrg (match_operand:DI 2 "reg_or_0_operand")] 5726 1.1.1.2 mrg "TARGET_MAX" 5727 1.1 mrg { 5728 1.1 mrg alpha_expand_builtin_vector_binop (gen_smaxv4hi3, V4HImode, operands[0], 5729 1.1 mrg operands[1], operands[2]); 5730 1.1 mrg DONE; 5731 1.1 mrg }) 5732 1.1 mrg 5733 1.1 mrg (define_insn "builtin_perr" 5734 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 5735 1.1 mrg (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "%rJ") 5736 1.1 mrg (match_operand:DI 2 "reg_or_8bit_operand" "rJ")] 5737 1.1 mrg UNSPEC_PERR))] 5738 1.1 mrg "TARGET_MAX" 5739 1.1 mrg "perr %r1,%r2,%0" 5740 1.1 mrg [(set_attr "type" "mvi")]) 5741 1.1 mrg 5742 1.1.1.2 mrg (define_expand "builtin_pklb" 5743 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand") 5744 1.1 mrg (vec_concat:V8QI 5745 1.1 mrg (vec_concat:V4QI 5746 1.1 mrg (truncate:V2QI (match_operand:DI 1 "register_operand")) 5747 1.1 mrg (match_dup 2)) 5748 1.1 mrg (match_dup 3)))] 5749 1.1.1.2 mrg "TARGET_MAX" 5750 1.1 mrg { 5751 1.1.1.2 mrg operands[0] = gen_lowpart (V8QImode, operands[0]); 5752 1.1 mrg operands[1] = gen_lowpart (V2SImode, operands[1]); 5753 1.1 mrg operands[2] = CONST0_RTX (V2QImode); 5754 1.1 mrg operands[3] = CONST0_RTX (V4QImode); 5755 1.1 mrg }) 5756 1.1 mrg 5757 1.1 mrg (define_insn "*pklb" 5758 1.1 mrg [(set (match_operand:V8QI 0 "register_operand" "=r") 5759 1.1 mrg (vec_concat:V8QI 5760 1.1 mrg (vec_concat:V4QI 5761 1.1 mrg (truncate:V2QI (match_operand:V2SI 1 "register_operand" "r")) 5762 1.1 mrg (match_operand:V2QI 2 "const0_operand")) 5763 1.1 mrg (match_operand:V4QI 3 "const0_operand")))] 5764 1.1.1.2 mrg "TARGET_MAX" 5765 1.1 mrg "pklb %r1,%0" 5766 1.1 mrg [(set_attr "type" "mvi")]) 5767 1.1 mrg 5768 1.1 mrg (define_expand "builtin_pkwb" 5769 1.1 mrg [(set (match_operand:DI 0 "register_operand") 5770 1.1.1.2 mrg (vec_concat:V8QI 5771 1.1 mrg (truncate:V4QI (match_operand:DI 1 "register_operand")) 5772 1.1.1.2 mrg (match_dup 2)))] 5773 1.1 mrg "TARGET_MAX" 5774 1.1 mrg { 5775 1.1 mrg operands[0] = gen_lowpart (V8QImode, operands[0]); 5776 1.1 mrg operands[1] = gen_lowpart (V4HImode, operands[1]); 5777 1.1 mrg operands[2] = CONST0_RTX (V4QImode); 5778 1.1 mrg }) 5779 1.1 mrg 5780 1.1 mrg (define_insn "*pkwb" 5781 1.1 mrg [(set (match_operand:V8QI 0 "register_operand" "=r") 5782 1.1 mrg (vec_concat:V8QI 5783 1.1 mrg (truncate:V4QI (match_operand:V4HI 1 "register_operand" "r")) 5784 1.1 mrg (match_operand:V4QI 2 "const0_operand")))] 5785 1.1 mrg "TARGET_MAX" 5786 1.1 mrg "pkwb %r1,%0" 5787 1.1 mrg [(set_attr "type" "mvi")]) 5788 1.1 mrg 5789 1.1 mrg (define_expand "builtin_unpkbl" 5790 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand") 5791 1.1 mrg (zero_extend:V2SI 5792 1.1.1.2 mrg (vec_select:V2QI (match_operand:DI 1 "register_operand") 5793 1.1 mrg (parallel [(const_int 0) (const_int 1)]))))] 5794 1.1 mrg "TARGET_MAX" 5795 1.1 mrg { 5796 1.1 mrg operands[0] = gen_lowpart (V2SImode, operands[0]); 5797 1.1 mrg operands[1] = gen_lowpart (V8QImode, operands[1]); 5798 1.1 mrg }) 5799 1.1 mrg 5800 1.1 mrg (define_insn "*unpkbl" 5801 1.1 mrg [(set (match_operand:V2SI 0 "register_operand" "=r") 5802 1.1 mrg (zero_extend:V2SI 5803 1.1 mrg (vec_select:V2QI (match_operand:V8QI 1 "reg_or_0_operand" "rW") 5804 1.1 mrg (parallel [(const_int 0) (const_int 1)]))))] 5805 1.1 mrg "TARGET_MAX" 5806 1.1 mrg "unpkbl %r1,%0" 5807 1.1 mrg [(set_attr "type" "mvi")]) 5808 1.1 mrg 5809 1.1 mrg (define_expand "builtin_unpkbw" 5810 1.1 mrg [(set (match_operand:DI 0 "register_operand") 5811 1.1 mrg (zero_extend:V4HI 5812 1.1 mrg (vec_select:V4QI (match_operand:DI 1 "register_operand") 5813 1.1 mrg (parallel [(const_int 0) 5814 1.1 mrg (const_int 1) 5815 1.1 mrg (const_int 2) 5816 1.1 mrg (const_int 3)]))))] 5817 1.1 mrg "TARGET_MAX" 5818 1.1 mrg { 5819 1.1 mrg operands[0] = gen_lowpart (V4HImode, operands[0]); 5820 1.1 mrg operands[1] = gen_lowpart (V8QImode, operands[1]); 5821 1.1.1.2 mrg }) 5822 1.1 mrg 5823 1.1.1.2 mrg (define_insn "*unpkbw" 5824 1.1 mrg [(set (match_operand:V4HI 0 "register_operand" "=r") 5825 1.1 mrg (zero_extend:V4HI 5826 1.1 mrg (vec_select:V4QI (match_operand:V8QI 1 "reg_or_0_operand" "rW") 5827 1.1 mrg (parallel [(const_int 0) 5828 1.1 mrg (const_int 1) 5829 1.1 mrg (const_int 2) 5830 1.1 mrg (const_int 3)]))))] 5831 1.1 mrg "TARGET_MAX" 5832 1.1 mrg "unpkbw %r1,%0" 5833 1.1 mrg [(set_attr "type" "mvi")]) 5834 1.1 mrg 5836 1.1.1.2 mrg (include "sync.md") 5837 1.1 mrg 5839 1.1 mrg ;; The call patterns are at the end of the file because their 5840 1.1 mrg ;; wildcard operand0 interferes with nice recognition. 5841 1.1 mrg 5842 1.1 mrg (define_insn "*call_value_osf_1_er_noreturn" 5843 1.1 mrg [(set (match_operand 0) 5844 1.1 mrg (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) 5845 1.1 mrg (match_operand 2))) 5846 1.1 mrg (use (reg:DI 29)) 5847 1.1 mrg (clobber (reg:DI 26))] 5848 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF 5849 1.1 mrg && find_reg_note (insn, REG_NORETURN, NULL_RTX)" 5850 1.1 mrg "@ 5851 1.1 mrg jsr $26,($27),0 5852 1.1.1.2 mrg bsr $26,%1\t\t!samegp 5853 1.1.1.2 mrg ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),%1\t\t!lituse_jsr!%#" 5854 1.1.1.2 mrg [(set_attr "type" "jsr") 5855 1.1 mrg (set_attr "length" "*,*,8")]) 5856 1.1 mrg 5857 1.1 mrg (define_insn "*call_value_osf_1_er" 5858 1.1 mrg [(set (match_operand 0) 5859 1.1 mrg (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) 5860 1.1 mrg (match_operand 2))) 5861 1.1 mrg (use (reg:DI 29)) 5862 1.1 mrg (clobber (reg:DI 26))] 5863 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 5864 1.1 mrg "@ 5865 1.1 mrg jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%* 5866 1.1 mrg bsr $26,%1\t\t!samegp 5867 1.1 mrg ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*" 5868 1.1 mrg [(set_attr "type" "jsr") 5869 1.1 mrg (set_attr "length" "12,*,16")]) 5870 1.1 mrg 5871 1.1 mrg ;; We must use peep2 instead of a split because we need accurate life 5872 1.1 mrg ;; information for $gp. Consider the case of { bar(); while (1); }. 5873 1.1 mrg (define_peephole2 5874 1.1 mrg [(parallel [(set (match_operand 0) 5875 1.1 mrg (call (mem:DI (match_operand:DI 1 "call_operand")) 5876 1.1 mrg (match_operand 2))) 5877 1.1 mrg (use (reg:DI 29)) 5878 1.1 mrg (clobber (reg:DI 26))])] 5879 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed 5880 1.1 mrg && ! samegp_function_operand (operands[1], Pmode) 5881 1.1 mrg && (peep2_regno_dead_p (1, 29) 5882 1.1 mrg || find_reg_note (insn, REG_NORETURN, NULL_RTX))" 5883 1.1 mrg [(parallel [(set (match_dup 0) 5884 1.1 mrg (call (mem:DI (match_dup 3)) 5885 1.1.1.2 mrg (match_dup 2))) 5886 1.1.1.2 mrg (use (reg:DI 29)) 5887 1.1.1.2 mrg (use (match_dup 1)) 5888 1.1 mrg (use (match_dup 4)) 5889 1.1 mrg (clobber (reg:DI 26))])] 5890 1.1 mrg { 5891 1.1 mrg if (CONSTANT_P (operands[1])) 5892 1.1 mrg { 5893 1.1 mrg operands[3] = gen_rtx_REG (Pmode, 27); 5894 1.1 mrg operands[4] = GEN_INT (alpha_next_sequence_number++); 5895 1.1 mrg emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx, 5896 1.1 mrg operands[1], operands[4])); 5897 1.1 mrg } 5898 1.1 mrg else 5899 1.1 mrg { 5900 1.1 mrg operands[3] = operands[1]; 5901 1.1 mrg operands[1] = const0_rtx; 5902 1.1 mrg operands[4] = const0_rtx; 5903 1.1 mrg } 5904 1.1 mrg }) 5905 1.1 mrg 5906 1.1 mrg (define_peephole2 5907 1.1 mrg [(parallel [(set (match_operand 0) 5908 1.1 mrg (call (mem:DI (match_operand:DI 1 "call_operand")) 5909 1.1 mrg (match_operand 2))) 5910 1.1 mrg (use (reg:DI 29)) 5911 1.1 mrg (clobber (reg:DI 26))])] 5912 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed 5913 1.1 mrg && ! samegp_function_operand (operands[1], Pmode) 5914 1.1 mrg && ! (peep2_regno_dead_p (1, 29) 5915 1.1 mrg || find_reg_note (insn, REG_NORETURN, NULL_RTX))" 5916 1.1 mrg [(parallel [(set (match_dup 0) 5917 1.1 mrg (call (mem:DI (match_dup 3)) 5918 1.1 mrg (match_dup 2))) 5919 1.1 mrg (set (match_dup 6) 5920 1.1 mrg (unspec:DI [(match_dup 6) (match_dup 4)] UNSPEC_LDGP1)) 5921 1.1 mrg (use (match_dup 1)) 5922 1.1 mrg (use (match_dup 5)) 5923 1.1.1.2 mrg (clobber (reg:DI 26))]) 5924 1.1 mrg (set (match_dup 6) 5925 1.1.1.2 mrg (unspec:DI [(match_dup 6) (match_dup 4)] UNSPEC_LDGP2))] 5926 1.1 mrg { 5927 1.1.1.2 mrg if (CONSTANT_P (operands[1])) 5928 1.1.1.2 mrg { 5929 1.1 mrg operands[3] = gen_rtx_REG (Pmode, 27); 5930 1.1 mrg operands[5] = GEN_INT (alpha_next_sequence_number++); 5931 1.1 mrg emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx, 5932 1.1 mrg operands[1], operands[5])); 5933 1.1 mrg } 5934 1.1 mrg else 5935 1.1.1.2 mrg { 5936 1.1 mrg operands[3] = operands[1]; 5937 1.1.1.2 mrg operands[1] = const0_rtx; 5938 1.1 mrg operands[5] = const0_rtx; 5939 1.1.1.2 mrg } 5940 1.1 mrg operands[4] = GEN_INT (alpha_next_sequence_number++); 5941 1.1.1.2 mrg operands[6] = pic_offset_table_rtx; 5942 1.1.1.2 mrg }) 5943 1.1 mrg 5944 1.1 mrg (define_insn "*call_value_osf_2_er_nogp" 5945 1.1 mrg [(set (match_operand 0) 5946 1.1 mrg (call (mem:DI (match_operand:DI 1 "register_operand" "c")) 5947 1.1 mrg (match_operand 2))) 5948 1.1 mrg (use (reg:DI 29)) 5949 1.1 mrg (use (match_operand 3)) 5950 1.1 mrg (use (match_operand 4)) 5951 1.1.1.2 mrg (clobber (reg:DI 26))] 5952 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 5953 1.1.1.2 mrg "jsr $26,(%1),%3%J4" 5954 1.1 mrg [(set_attr "type" "jsr")]) 5955 1.1 mrg 5956 1.1 mrg (define_insn "*call_value_osf_2_er" 5957 1.1 mrg [(set (match_operand 0) 5958 1.1 mrg (call (mem:DI (match_operand:DI 1 "register_operand" "c")) 5959 1.1 mrg (match_operand 2))) 5960 1.1 mrg (set (reg:DI 29) 5961 1.1 mrg (unspec:DI [(reg:DI 29) (match_operand 5 "const_int_operand")] 5962 1.1 mrg UNSPEC_LDGP1)) 5963 1.1 mrg (use (match_operand 3)) 5964 1.1 mrg (use (match_operand 4)) 5965 1.1.1.2 mrg (clobber (reg:DI 26))] 5966 1.1.1.2 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 5967 1.1.1.2 mrg "jsr $26,(%1),%3%J4\;ldah $29,0($26)\t\t!gpdisp!%5" 5968 1.1.1.2 mrg [(set_attr "type" "jsr") 5969 1.1.1.2 mrg (set_attr "cannot_copy" "true") 5970 1.1.1.2 mrg (set_attr "length" "8")]) 5971 1.1.1.2 mrg 5972 1.1.1.2 mrg (define_insn "*call_value_osf_1_noreturn" 5973 1.1.1.2 mrg [(set (match_operand 0) 5974 1.1.1.2 mrg (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) 5975 1.1.1.2 mrg (match_operand 2))) 5976 1.1 mrg (use (reg:DI 29)) 5977 1.1.1.2 mrg (clobber (reg:DI 26))] 5978 1.1 mrg "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF 5979 1.1 mrg && find_reg_note (insn, REG_NORETURN, NULL_RTX)" 5980 1.1 mrg "@ 5981 1.1.1.2 mrg jsr $26,($27),0 5982 1.1.1.2 mrg bsr $26,$%1..ng 5983 1.1.1.2 mrg jsr $26,%1" 5984 1.1.1.2 mrg [(set_attr "type" "jsr") 5985 1.1.1.2 mrg (set_attr "length" "*,*,8")]) 5986 1.1.1.2 mrg 5987 1.1.1.2 mrg (define_int_iterator TLS_CALL 5988 1.1.1.2 mrg [UNSPEC_TLSGD_CALL 5989 1.1.1.2 mrg UNSPEC_TLSLDM_CALL]) 5990 1.1.1.2 mrg 5991 1.1.1.2 mrg (define_int_attr tls 5992 1.1.1.2 mrg [(UNSPEC_TLSGD_CALL "tlsgd") 5993 1.1.1.2 mrg (UNSPEC_TLSLDM_CALL "tlsldm")]) 5994 1.1.1.2 mrg 5995 1.1.1.2 mrg (define_insn "call_value_osf_<tls>" 5996 1.1.1.2 mrg [(set (match_operand 0) 5997 1.1 mrg (call (mem:DI (match_operand:DI 1 "symbolic_operand")) 5998 1.1 mrg (const_int 0))) 5999 1.1 mrg (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL) 6000 1.1 mrg (use (reg:DI 29)) 6001 1.1 mrg (clobber (reg:DI 26))] 6002 1.1 mrg "HAVE_AS_TLS" 6003 1.1 mrg "ldq $27,%1($29)\t\t!literal!%2\;jsr $26,($27),%1\t\t!lituse_<tls>!%2\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*" 6004 1.1.1.2 mrg [(set_attr "type" "jsr") 6005 1.1 mrg (set_attr "length" "16")]) 6006 1.1.1.2 mrg 6007 1.1 mrg ;; We must use peep2 instead of a split because we need accurate life 6008 1.1 mrg ;; information for $gp. 6009 1.1 mrg (define_peephole2 6010 1.1 mrg [(parallel 6011 1.1 mrg [(set (match_operand 0) 6012 1.1 mrg (call (mem:DI (match_operand:DI 1 "symbolic_operand")) 6013 1.1 mrg (const_int 0))) 6014 1.1.1.2 mrg (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL) 6015 1.1 mrg (use (reg:DI 29)) 6016 1.1.1.2 mrg (clobber (reg:DI 26))])] 6017 1.1.1.2 mrg "HAVE_AS_TLS && reload_completed 6018 1.1.1.2 mrg && peep2_regno_dead_p (1, 29)" 6019 1.1.1.2 mrg [(set (match_dup 3) 6020 1.1.1.2 mrg (unspec:DI [(match_dup 5) 6021 1.1.1.2 mrg (match_dup 1) 6022 1.1.1.2 mrg (match_dup 2)] UNSPEC_LITERAL)) 6023 1.1.1.2 mrg (parallel [(set (match_dup 0) 6024 1.1.1.2 mrg (call (mem:DI (match_dup 3)) 6025 1.1.1.2 mrg (const_int 0))) 6026 1.1 mrg (use (match_dup 5)) 6027 1.1 mrg (use (match_dup 1)) 6028 1.1 mrg (use (unspec [(match_dup 2)] TLS_CALL)) 6029 1.1 mrg (clobber (reg:DI 26))]) 6030 1.1 mrg (set (match_dup 5) 6031 1.1 mrg (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))] 6032 1.1 mrg { 6033 1.1 mrg operands[3] = gen_rtx_REG (Pmode, 27); 6034 1.1 mrg operands[4] = GEN_INT (alpha_next_sequence_number++); 6035 1.1 mrg operands[5] = pic_offset_table_rtx; 6036 1.1.1.2 mrg }) 6037 1.1 mrg 6038 1.1 mrg (define_peephole2 6039 1.1 mrg [(parallel 6040 1.1 mrg [(set (match_operand 0) 6041 1.1 mrg (call (mem:DI (match_operand:DI 1 "symbolic_operand")) 6042 1.1 mrg (const_int 0))) 6043 1.1 mrg (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL) 6044 1.1.1.2 mrg (use (reg:DI 29)) 6045 1.1 mrg (clobber (reg:DI 26))])] 6046 1.1 mrg "HAVE_AS_TLS && reload_completed 6047 1.1.1.2 mrg && !peep2_regno_dead_p (1, 29)" 6048 1.1 mrg [(set (match_dup 3) 6049 1.1.1.2 mrg (unspec:DI [(match_dup 5) 6050 1.1 mrg (match_dup 1) 6051 1.1 mrg (match_dup 2)] UNSPEC_LITERAL)) 6052 1.1 mrg (parallel [(set (match_dup 0) 6053 1.1 mrg (call (mem:DI (match_dup 3)) 6054 1.1 mrg (const_int 0))) 6055 1.1 mrg (set (match_dup 5) 6056 1.1 mrg (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP1)) 6057 1.1 mrg (use (match_dup 1)) 6058 1.1 mrg (use (unspec [(match_dup 2)] TLS_CALL)) 6059 1.1 mrg (clobber (reg:DI 26))]) 6060 1.1 mrg (set (match_dup 5) 6061 1.1.1.2 mrg (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))] 6062 1.1 mrg { 6063 1.1.1.2 mrg operands[3] = gen_rtx_REG (Pmode, 27); 6064 1.1 mrg operands[4] = GEN_INT (alpha_next_sequence_number++); 6065 1.1 mrg operands[5] = pic_offset_table_rtx; 6066 1.1 mrg }) 6067 1.1 mrg 6068 1.1 mrg (define_insn "*call_value_osf_1" 6069 1.1 mrg [(set (match_operand 0) 6070 1.1 mrg (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) 6071 1.1 mrg (match_operand 2))) 6072 1.1 mrg (use (reg:DI 29)) 6073 1.1.1.2 mrg (clobber (reg:DI 26))] 6074 1.1 mrg "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 6075 1.1.1.2 mrg "@ 6076 1.1 mrg jsr $26,($27),0\;ldgp $29,0($26) 6077 1.1 mrg bsr $26,$%1..ng 6078 1.1 mrg jsr $26,%1\;ldgp $29,0($26)" 6079 1.1 mrg [(set_attr "type" "jsr") 6080 1.1 mrg (set_attr "length" "12,*,16")]) 6081 1.1 mrg 6082 1.1 mrg (define_insn "*sibcall_value_osf_1_er" 6083 1.1 mrg [(set (match_operand 0) 6084 1.1 mrg (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s")) 6085 1.1 mrg (match_operand 2))) 6086 1.1 mrg (unspec [(reg:DI 29)] UNSPEC_SIBCALL)] 6087 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 6088 1.1.1.2 mrg "@ 6089 1.1 mrg br $31,%1\t\t!samegp 6090 1.1.1.2 mrg ldq $27,%1($29)\t\t!literal!%#\;jmp $31,($27),%1\t\t!lituse_jsr!%#" 6091 1.1 mrg [(set_attr "type" "jsr") 6092 1.1 mrg (set_attr "length" "*,8")]) 6093 1.1 mrg 6094 1.1 mrg (define_insn "*sibcall_value_osf_1" 6095 1.1 mrg [(set (match_operand 0) 6096 1.1 mrg (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s")) 6097 1.1 mrg (match_operand 2))) 6098 1.1 mrg (unspec [(reg:DI 29)] UNSPEC_SIBCALL)] 6099 1.1 mrg "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 6100 1.1 mrg "@ 6101 1.1 mrg br $31,$%1..ng 6102 1.1.1.2 mrg lda $27,%1\;jmp $31,($27),%1" 6103 1.1.1.2 mrg [(set_attr "type" "jsr") 6104 1.1 mrg (set_attr "length" "*,8")]) 6105 1.1 mrg 6106 1.1 mrg ; GAS relies on the order and position of instructions output below in order 6107 1.1 mrg ; to generate relocs for VMS link to potentially optimize the call. 6108 1.1 mrg ; Please do not molest. 6109 1.1 mrg (define_insn "*call_value_vms_1" 6110 1.1 mrg [(set (match_operand 0) 6111 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s")) 6112 (match_operand 2))) 6113 (use (match_operand:DI 3 "nonmemory_operand" "r,n")) 6114 (use (reg:DI 25)) 6115 (use (reg:DI 26)) 6116 (clobber (reg:DI 27))] 6117 "TARGET_ABI_OPEN_VMS" 6118 { 6119 switch (which_alternative) 6120 { 6121 case 0: 6122 return "mov %3,$27\;jsr $26,0\;ldq $27,0($29)"; 6123 case 1: 6124 operands [3] = alpha_use_linkage (operands [1], true, false); 6125 operands [4] = alpha_use_linkage (operands [1], false, false); 6126 return "ldq $26,%4\;ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"; 6127 default: 6128 gcc_unreachable (); 6129 } 6130 } 6131 [(set_attr "type" "jsr") 6132 (set_attr "length" "12,16")]) 6133
Indexes created Thu Sep 10 00:26:39 UTC 2026