alpha.md revision 1.1.1.8
1 1.1 mrg ;; Machine description for DEC Alpha for GNU C compiler 2 1.1.1.8 mrg ;; Copyright (C) 1992-2019 Free Software Foundation, Inc. 3 1.1 mrg ;; Contributed by Richard Kenner (kenner (a] vlsi1.ultra.nyu.edu) 4 1.1 mrg ;; 5 1.1 mrg ;; This file is part of GCC. 6 1.1 mrg ;; 7 1.1 mrg ;; GCC is free software; you can redistribute it and/or modify 8 1.1 mrg ;; it under the terms of the GNU General Public License as published by 9 1.1 mrg ;; the Free Software Foundation; either version 3, or (at your option) 10 1.1 mrg ;; any later version. 11 1.1 mrg ;; 12 1.1 mrg ;; GCC is distributed in the hope that it will be useful, 13 1.1 mrg ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14 1.1 mrg ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 1.1 mrg ;; GNU General Public License for more details. 16 1.1 mrg ;; 17 1.1 mrg ;; You should have received a copy of the GNU General Public License 18 1.1 mrg ;; along with GCC; see the file COPYING3. If not see 19 1.1 mrg ;; <http://www.gnu.org/licenses/>. 20 1.1 mrg 21 1.1 mrg ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 22 1.1 mrg 23 1.1 mrg ;; Uses of UNSPEC in this file: 24 1.1 mrg 25 1.1.1.2 mrg (define_c_enum "unspec" [ 26 1.1.1.2 mrg UNSPEC_XFLT_COMPARE 27 1.1.1.2 mrg UNSPEC_ARG_HOME 28 1.1.1.2 mrg UNSPEC_LDGP1 29 1.1.1.2 mrg UNSPEC_INSXH 30 1.1.1.2 mrg UNSPEC_MSKXH 31 1.1.1.2 mrg UNSPEC_CVTQL 32 1.1.1.2 mrg UNSPEC_CVTLQ 33 1.1.1.2 mrg UNSPEC_LDGP2 34 1.1.1.2 mrg UNSPEC_LITERAL 35 1.1.1.2 mrg UNSPEC_LITUSE 36 1.1.1.2 mrg UNSPEC_SIBCALL 37 1.1.1.2 mrg UNSPEC_SYMBOL 38 1.1.1.2 mrg 39 1.1.1.2 mrg ;; TLS Support 40 1.1.1.2 mrg UNSPEC_TLSGD_CALL 41 1.1.1.2 mrg UNSPEC_TLSLDM_CALL 42 1.1.1.2 mrg UNSPEC_TLSGD 43 1.1.1.2 mrg UNSPEC_TLSLDM 44 1.1.1.2 mrg UNSPEC_DTPREL 45 1.1.1.2 mrg UNSPEC_TPREL 46 1.1.1.2 mrg UNSPEC_TP 47 1.1.1.2 mrg 48 1.1.1.2 mrg ;; Builtins 49 1.1.1.2 mrg UNSPEC_CMPBGE 50 1.1.1.2 mrg UNSPEC_ZAP 51 1.1.1.2 mrg UNSPEC_AMASK 52 1.1.1.2 mrg UNSPEC_IMPLVER 53 1.1.1.2 mrg UNSPEC_PERR 54 1.1.1.2 mrg UNSPEC_COPYSIGN 55 1.1.1.2 mrg 56 1.1.1.2 mrg ;; Atomic operations 57 1.1.1.2 mrg UNSPEC_MB 58 1.1.1.2 mrg UNSPEC_ATOMIC 59 1.1.1.2 mrg UNSPEC_CMPXCHG 60 1.1.1.2 mrg UNSPEC_XCHG 61 1.1.1.2 mrg ]) 62 1.1 mrg 63 1.1 mrg ;; UNSPEC_VOLATILE: 64 1.1 mrg 65 1.1.1.2 mrg (define_c_enum "unspecv" [ 66 1.1.1.2 mrg UNSPECV_IMB 67 1.1.1.2 mrg UNSPECV_BLOCKAGE 68 1.1.1.2 mrg UNSPECV_SETJMPR ; builtin_setjmp_receiver 69 1.1.1.2 mrg UNSPECV_LONGJMP ; builtin_longjmp 70 1.1.1.2 mrg UNSPECV_TRAPB 71 1.1.1.2 mrg UNSPECV_PSPL ; prologue_stack_probe_loop 72 1.1.1.2 mrg UNSPECV_REALIGN 73 1.1.1.2 mrg UNSPECV_EHR ; exception_receiver 74 1.1.1.2 mrg UNSPECV_MCOUNT 75 1.1.1.2 mrg UNSPECV_FORCE_MOV 76 1.1.1.2 mrg UNSPECV_LDGP1 77 1.1.1.2 mrg UNSPECV_PLDGP2 ; prologue ldgp 78 1.1.1.2 mrg UNSPECV_SET_TP 79 1.1.1.2 mrg UNSPECV_RPCC 80 1.1.1.2 mrg UNSPECV_SETJMPR_ER ; builtin_setjmp_receiver fragment 81 1.1.1.2 mrg UNSPECV_LL ; load-locked 82 1.1.1.2 mrg UNSPECV_SC ; store-conditional 83 1.1.1.2 mrg UNSPECV_CMPXCHG 84 1.1.1.2 mrg ]) 85 1.1 mrg 86 1.1 mrg ;; On non-BWX targets, CQImode must be handled the similarly to HImode 87 1.1 mrg ;; when generating reloads. 88 1.1 mrg (define_mode_iterator RELOAD12 [QI HI CQI]) 89 1.1 mrg (define_mode_attr reloadmode [(QI "qi") (HI "hi") (CQI "hi")]) 90 1.1 mrg 91 1.1 mrg ;; Other mode iterators 92 1.1.1.2 mrg (define_mode_iterator IMODE [QI HI SI DI]) 93 1.1 mrg (define_mode_iterator I12MODE [QI HI]) 94 1.1.1.2 mrg (define_mode_iterator I124MODE [QI HI SI]) 95 1.1.1.2 mrg (define_mode_iterator I24MODE [HI SI]) 96 1.1.1.2 mrg (define_mode_iterator I248MODE [HI SI DI]) 97 1.1 mrg (define_mode_iterator I48MODE [SI DI]) 98 1.1.1.2 mrg 99 1.1.1.2 mrg (define_mode_attr DWI [(SI "DI") (DI "TI")]) 100 1.1.1.2 mrg (define_mode_attr modesuffix [(QI "b") (HI "w") (SI "l") (DI "q") 101 1.1.1.2 mrg (V8QI "b8") (V4HI "w4") 102 1.1.1.2 mrg (SF "%,") (DF "%-")]) 103 1.1.1.2 mrg (define_mode_attr vecmodesuffix [(QI "b8") (HI "w4")]) 104 1.1.1.2 mrg 105 1.1.1.2 mrg (define_code_iterator any_maxmin [smax smin umax umin]) 106 1.1.1.2 mrg 107 1.1.1.2 mrg (define_code_attr maxmin [(smax "maxs") (smin "mins") 108 1.1.1.2 mrg (umax "maxu") (umin "minu")]) 109 1.1 mrg 110 1.1 mrg ;; Where necessary, the suffixes _le and _be are used to distinguish between 111 1.1 mrg ;; little-endian and big-endian patterns. 112 1.1 mrg ;; 113 1.1 mrg ;; Note that the Unicos/Mk assembler does not support the following 114 1.1 mrg ;; opcodes: mov, fmov, nop, fnop, unop. 115 1.1 mrg 117 1.1 mrg ;; Processor type -- this attribute must exactly match the processor_type 118 1.1 mrg ;; enumeration in alpha.h. 119 1.1 mrg 120 1.1 mrg (define_attr "tune" "ev4,ev5,ev6" 121 1.1 mrg (const (symbol_ref "((enum attr_tune) alpha_tune)"))) 122 1.1 mrg 123 1.1 mrg ;; Define an insn type attribute. This is used in function unit delay 124 1.1 mrg ;; computations, among other purposes. For the most part, we use the names 125 1.1 mrg ;; defined in the EV4 documentation, but add a few that we have to know about 126 1.1 mrg ;; separately. 127 1.1 mrg 128 1.1 mrg (define_attr "type" 129 1.1 mrg "ild,fld,ldsym,ist,fst,ibr,callpal,fbr,jsr,iadd,ilog,shift,icmov,fcmov, 130 1.1 mrg icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,mb,ld_l,st_c, 131 1.1 mrg multi,none" 132 1.1 mrg (const_string "iadd")) 133 1.1 mrg 134 1.1 mrg ;; Describe a user's asm statement. 135 1.1 mrg (define_asm_attributes 136 1.1 mrg [(set_attr "type" "multi")]) 137 1.1 mrg 138 1.1 mrg ;; Define the operand size an insn operates on. Used primarily by mul 139 1.1 mrg ;; and div operations that have size dependent timings. 140 1.1 mrg 141 1.1 mrg (define_attr "opsize" "si,di,udi" 142 1.1 mrg (const_string "di")) 143 1.1 mrg 144 1.1 mrg ;; The TRAP attribute marks instructions that may generate traps 145 1.1 mrg ;; (which are imprecise and may need a trapb if software completion 146 1.1 mrg ;; is desired). 147 1.1 mrg 148 1.1 mrg (define_attr "trap" "no,yes" 149 1.1 mrg (const_string "no")) 150 1.1 mrg 151 1.1 mrg ;; The ROUND_SUFFIX attribute marks which instructions require a 152 1.1 mrg ;; rounding-mode suffix. The value NONE indicates no suffix, 153 1.1 mrg ;; the value NORMAL indicates a suffix controlled by alpha_fprm. 154 1.1 mrg 155 1.1 mrg (define_attr "round_suffix" "none,normal,c" 156 1.1 mrg (const_string "none")) 157 1.1 mrg 158 1.1 mrg ;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix: 159 1.1 mrg ;; NONE no suffix 160 1.1 mrg ;; SU accepts only /su (cmpt et al) 161 1.1 mrg ;; SUI accepts only /sui (cvtqt and cvtqs) 162 1.1 mrg ;; V_SV accepts /v and /sv (cvtql only) 163 1.1 mrg ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only) 164 1.1 mrg ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions) 165 1.1 mrg ;; 166 1.1 mrg ;; The actual suffix emitted is controlled by alpha_fptm. 167 1.1 mrg 168 1.1 mrg (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui" 169 1.1 mrg (const_string "none")) 170 1.1 mrg 171 1.1 mrg ;; The length of an instruction sequence in bytes. 172 1.1 mrg 173 1.1 mrg (define_attr "length" "" 174 1.1 mrg (const_int 4)) 175 1.1 mrg 176 1.1 mrg ;; The USEGP attribute marks instructions that have relocations that use 177 1.1 mrg ;; the GP. 178 1.1 mrg 179 1.1 mrg (define_attr "usegp" "no,yes" 180 1.1 mrg (cond [(eq_attr "type" "ldsym,jsr") 181 1.1 mrg (const_string "yes") 182 1.1 mrg (eq_attr "type" "ild,fld,ist,fst") 183 1.1 mrg (symbol_ref "((enum attr_usegp) alpha_find_lo_sum_using_gp (insn))") 184 1.1 mrg ] 185 1.1 mrg (const_string "no"))) 186 1.1 mrg 187 1.1 mrg ;; The CANNOT_COPY attribute marks instructions with relocations that 188 1.1 mrg ;; cannot easily be duplicated. This includes insns with gpdisp relocs 189 1.1 mrg ;; since they have to stay in 1-1 correspondence with one another. This 190 1.1 mrg ;; also includes jsr insns, since they must stay in correspondence with 191 1.1 mrg ;; the immediately following gpdisp instructions. 192 1.1 mrg 193 1.1 mrg (define_attr "cannot_copy" "false,true" 194 1.1.1.2 mrg (const_string "false")) 195 1.1.1.2 mrg 196 1.1.1.2 mrg ;; Used to control the "enabled" attribute on a per-instruction basis. 197 1.1.1.2 mrg ;; For convenience, conflate ABI issues re loading of addresses with 198 1.1.1.2 mrg ;; an "isa". 199 1.1.1.2 mrg (define_attr "isa" "base,bwx,max,fix,cix,vms,ner,er" 200 1.1.1.2 mrg (const_string "base")) 201 1.1.1.2 mrg 202 1.1.1.2 mrg (define_attr "enabled" "" 203 1.1.1.2 mrg (cond [(eq_attr "isa" "bwx") (symbol_ref "TARGET_BWX") 204 1.1.1.2 mrg (eq_attr "isa" "max") (symbol_ref "TARGET_MAX") 205 1.1.1.2 mrg (eq_attr "isa" "fix") (symbol_ref "TARGET_FIX") 206 1.1.1.2 mrg (eq_attr "isa" "cix") (symbol_ref "TARGET_CIX") 207 1.1.1.2 mrg (eq_attr "isa" "vms") (symbol_ref "TARGET_ABI_OPEN_VMS") 208 1.1.1.2 mrg (eq_attr "isa" "ner") (symbol_ref "!TARGET_EXPLICIT_RELOCS") 209 1.1.1.2 mrg (eq_attr "isa" "er") (symbol_ref "TARGET_EXPLICIT_RELOCS") 210 1.1.1.2 mrg ] 211 1.1 mrg (const_int 1))) 212 1.1 mrg 214 1.1 mrg ;; Include scheduling descriptions. 215 1.1 mrg 216 1.1 mrg (include "ev4.md") 217 1.1 mrg (include "ev5.md") 218 1.1 mrg (include "ev6.md") 219 1.1 mrg 220 1.1 mrg 222 1.1 mrg ;; Operand and operator predicates and constraints 223 1.1 mrg 224 1.1 mrg (include "predicates.md") 225 1.1 mrg (include "constraints.md") 226 1.1 mrg 227 1.1 mrg 229 1.1 mrg ;; First define the arithmetic insns. Note that the 32-bit forms also 230 1.1 mrg ;; sign-extend. 231 1.1 mrg 232 1.1 mrg ;; Handle 32-64 bit extension from memory to a floating point register 233 1.1 mrg ;; specially, since this occurs frequently in int->double conversions. 234 1.1 mrg ;; 235 1.1 mrg ;; Note that while we must retain the =f case in the insn for reload's 236 1.1.1.2 mrg ;; benefit, it should be eliminated after reload, so we should never emit 237 1.1.1.2 mrg ;; code for that case. But we don't reject the possibility. 238 1.1 mrg 239 1.1 mrg (define_expand "extendsidi2" 240 1.1 mrg [(set (match_operand:DI 0 "register_operand") 241 1.1 mrg (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]) 242 1.1 mrg 243 1.1 mrg (define_insn "*cvtlq" 244 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=f") 245 1.1 mrg (unspec:DI [(match_operand:SF 1 "reg_or_0_operand" "fG")] 246 1.1 mrg UNSPEC_CVTLQ))] 247 1.1 mrg "" 248 1.1 mrg "cvtlq %1,%0" 249 1.1 mrg [(set_attr "type" "fadd")]) 250 1.1 mrg 251 1.1 mrg (define_insn "*extendsidi2_1" 252 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r,r,!*f") 253 1.1 mrg (sign_extend:DI 254 1.1 mrg (match_operand:SI 1 "nonimmediate_operand" "r,m,m")))] 255 1.1 mrg "" 256 1.1 mrg "@ 257 1.1 mrg addl $31,%1,%0 258 1.1 mrg ldl %0,%1 259 1.1 mrg lds %0,%1\;cvtlq %0,%0" 260 1.1.1.2 mrg [(set_attr "type" "iadd,ild,fld") 261 1.1.1.2 mrg (set_attr "length" "*,*,8")]) 262 1.1 mrg 263 1.1 mrg (define_split 264 1.1 mrg [(set (match_operand:DI 0 "hard_fp_register_operand") 265 1.1 mrg (sign_extend:DI (match_operand:SI 1 "memory_operand")))] 266 1.1 mrg "reload_completed" 267 1.1 mrg [(set (match_dup 2) (match_dup 1)) 268 1.1 mrg (set (match_dup 0) (unspec:DI [(match_dup 2)] UNSPEC_CVTLQ))] 269 1.1 mrg { 270 1.1 mrg operands[1] = adjust_address (operands[1], SFmode, 0); 271 1.1 mrg operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0])); 272 1.1 mrg }) 273 1.1 mrg 274 1.1.1.2 mrg ;; Optimize sign-extension of SImode loads. This shows up in the wake of 275 1.1.1.2 mrg ;; reload when converting fp->int. 276 1.1.1.2 mrg 277 1.1 mrg (define_peephole2 278 1.1 mrg [(set (match_operand:SI 0 "hard_int_register_operand") 279 1.1 mrg (match_operand:SI 1 "memory_operand")) 280 1.1 mrg (set (match_operand:DI 2 "hard_int_register_operand") 281 1.1.1.2 mrg (sign_extend:DI (match_dup 0)))] 282 1.1 mrg "true_regnum (operands[0]) == true_regnum (operands[2]) 283 1.1 mrg || peep2_reg_dead_p (2, operands[0])" 284 1.1 mrg [(set (match_dup 2) 285 1.1 mrg (sign_extend:DI (match_dup 1)))]) 286 1.1 mrg 287 1.1 mrg (define_insn "addsi3" 288 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") 289 1.1 mrg (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ") 290 1.1 mrg (match_operand:SI 2 "add_operand" "rI,O,K,L")))] 291 1.1 mrg "" 292 1.1 mrg "@ 293 1.1 mrg addl %r1,%2,%0 294 1.1 mrg subl %r1,%n2,%0 295 1.1.1.2 mrg lda %0,%2(%r1) 296 1.1.1.2 mrg ldah %0,%h2(%r1)") 297 1.1.1.2 mrg 298 1.1 mrg (define_split 299 1.1 mrg [(set (match_operand:SI 0 "register_operand") 300 1.1 mrg (plus:SI (match_operand:SI 1 "register_operand") 301 1.1 mrg (match_operand:SI 2 "const_int_operand")))] 302 1.1 mrg "! add_operand (operands[2], SImode)" 303 1.1 mrg [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) 304 1.1 mrg (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] 305 1.1 mrg { 306 1.1 mrg HOST_WIDE_INT val = INTVAL (operands[2]); 307 1.1 mrg HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); 308 1.1 mrg HOST_WIDE_INT rest = val - low; 309 1.1 mrg 310 1.1 mrg operands[3] = GEN_INT (rest); 311 1.1 mrg operands[4] = GEN_INT (low); 312 1.1 mrg }) 313 1.1 mrg 314 1.1 mrg (define_insn "*addsi_se" 315 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r,r") 316 1.1 mrg (sign_extend:DI 317 1.1 mrg (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ") 318 1.1 mrg (match_operand:SI 2 "sext_add_operand" "rI,O"))))] 319 1.1 mrg "" 320 1.1 mrg "@ 321 1.1 mrg addl %r1,%2,%0 322 1.1 mrg subl %r1,%n2,%0") 323 1.1 mrg 324 1.1 mrg (define_insn "*addsi_se2" 325 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r,r") 326 1.1 mrg (sign_extend:DI 327 1.1 mrg (subreg:SI (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ") 328 1.1 mrg (match_operand:DI 2 "sext_add_operand" "rI,O")) 329 1.1 mrg 0)))] 330 1.1 mrg "" 331 1.1 mrg "@ 332 1.1.1.2 mrg addl %r1,%2,%0 333 1.1 mrg subl %r1,%n2,%0") 334 1.1.1.2 mrg 335 1.1.1.2 mrg (define_split 336 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand") 337 1.1 mrg (sign_extend:DI 338 1.1 mrg (plus:SI (match_operand:SI 1 "reg_not_elim_operand") 339 1.1 mrg (match_operand:SI 2 "const_int_operand")))) 340 1.1.1.6 mrg (clobber (match_operand:SI 3 "reg_not_elim_operand"))] 341 1.1.1.6 mrg "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0 342 1.1 mrg && INTVAL (operands[2]) % 4 == 0" 343 1.1 mrg [(set (match_dup 3) (match_dup 4)) 344 1.1 mrg (set (match_dup 0) (sign_extend:DI (plus:SI (ashift:SI (match_dup 3) 345 1.1 mrg (match_dup 5)) 346 1.1 mrg (match_dup 1))))] 347 1.1 mrg { 348 1.1 mrg HOST_WIDE_INT val = INTVAL (operands[2]) / 4; 349 1.1 mrg int mult = 4; 350 1.1 mrg 351 1.1.1.6 mrg if (val % 2 == 0) 352 1.1 mrg val /= 2, mult = 8; 353 1.1 mrg 354 1.1 mrg operands[4] = GEN_INT (val); 355 1.1.1.2 mrg operands[5] = GEN_INT (exact_log2 (mult)); 356 1.1 mrg }) 357 1.1 mrg 358 1.1.1.2 mrg (define_split 359 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand") 360 1.1.1.2 mrg (sign_extend:DI 361 1.1.1.2 mrg (plus:SI (match_operator:SI 1 "comparison_operator" 362 1.1 mrg [(match_operand 2) 363 1.1 mrg (match_operand 3)]) 364 1.1 mrg (match_operand:SI 4 "add_operand")))) 365 1.1 mrg (clobber (match_operand:DI 5 "register_operand"))] 366 1.1 mrg "" 367 1.1 mrg [(set (match_dup 5) (match_dup 6)) 368 1.1 mrg (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))] 369 1.1 mrg { 370 1.1 mrg operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode, 371 1.1 mrg operands[2], operands[3]); 372 1.1.1.2 mrg operands[7] = gen_lowpart (SImode, operands[5]); 373 1.1.1.2 mrg }) 374 1.1.1.2 mrg 375 1.1 mrg (define_expand "adddi3" 376 1.1 mrg [(set (match_operand:DI 0 "register_operand") 377 1.1 mrg (plus:DI (match_operand:DI 1 "register_operand") 378 1.1 mrg (match_operand:DI 2 "add_operand")))]) 379 1.1.1.2 mrg 380 1.1 mrg (define_insn "*adddi_er_lo16_dtp" 381 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 382 1.1 mrg (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 383 1.1 mrg (match_operand:DI 2 "dtp16_symbolic_operand")))] 384 1.1 mrg "HAVE_AS_TLS" 385 1.1 mrg "lda %0,%2(%1)\t\t!dtprel") 386 1.1.1.2 mrg 387 1.1 mrg (define_insn "*adddi_er_hi32_dtp" 388 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 389 1.1 mrg (plus:DI (match_operand:DI 1 "register_operand" "r") 390 1.1 mrg (high:DI (match_operand:DI 2 "dtp32_symbolic_operand"))))] 391 1.1 mrg "HAVE_AS_TLS" 392 1.1 mrg "ldah %0,%2(%1)\t\t!dtprelhi") 393 1.1.1.2 mrg 394 1.1 mrg (define_insn "*adddi_er_lo32_dtp" 395 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 396 1.1 mrg (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 397 1.1 mrg (match_operand:DI 2 "dtp32_symbolic_operand")))] 398 1.1 mrg "HAVE_AS_TLS" 399 1.1 mrg "lda %0,%2(%1)\t\t!dtprello") 400 1.1.1.2 mrg 401 1.1 mrg (define_insn "*adddi_er_lo16_tp" 402 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 403 1.1 mrg (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 404 1.1 mrg (match_operand:DI 2 "tp16_symbolic_operand")))] 405 1.1 mrg "HAVE_AS_TLS" 406 1.1 mrg "lda %0,%2(%1)\t\t!tprel") 407 1.1.1.2 mrg 408 1.1 mrg (define_insn "*adddi_er_hi32_tp" 409 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 410 1.1 mrg (plus:DI (match_operand:DI 1 "register_operand" "r") 411 1.1 mrg (high:DI (match_operand:DI 2 "tp32_symbolic_operand"))))] 412 1.1 mrg "HAVE_AS_TLS" 413 1.1 mrg "ldah %0,%2(%1)\t\t!tprelhi") 414 1.1.1.2 mrg 415 1.1 mrg (define_insn "*adddi_er_lo32_tp" 416 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 417 1.1 mrg (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 418 1.1 mrg (match_operand:DI 2 "tp32_symbolic_operand")))] 419 1.1 mrg "HAVE_AS_TLS" 420 1.1 mrg "lda %0,%2(%1)\t\t!tprello") 421 1.1.1.2 mrg 422 1.1 mrg (define_insn "*adddi_er_high_l" 423 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 424 1.1 mrg (plus:DI (match_operand:DI 1 "register_operand" "r") 425 1.1 mrg (high:DI (match_operand:DI 2 "local_symbolic_operand"))))] 426 1.1 mrg "TARGET_EXPLICIT_RELOCS && reload_completed" 427 1.1.1.2 mrg "ldah %0,%2(%1)\t\t!gprelhigh" 428 1.1.1.2 mrg [(set_attr "usegp" "yes")]) 429 1.1 mrg 430 1.1 mrg (define_split 431 1.1 mrg [(set (match_operand:DI 0 "register_operand") 432 1.1 mrg (high:DI (match_operand:DI 1 "local_symbolic_operand")))] 433 1.1 mrg "TARGET_EXPLICIT_RELOCS && reload_completed" 434 1.1 mrg [(set (match_dup 0) 435 1.1 mrg (plus:DI (match_dup 2) (high:DI (match_dup 1))))] 436 1.1 mrg "operands[2] = pic_offset_table_rtx;") 437 1.1 mrg 438 1.1 mrg ;; We used to expend quite a lot of effort choosing addq/subq/lda. 439 1.1 mrg ;; With complications like 440 1.1 mrg ;; 441 1.1 mrg ;; The NT stack unwind code can't handle a subq to adjust the stack 442 1.1 mrg ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3, 443 1.1 mrg ;; the exception handling code will loop if a subq is used and an 444 1.1 mrg ;; exception occurs. 445 1.1 mrg ;; 446 1.1 mrg ;; The 19980616 change to emit prologues as RTL also confused some 447 1.1 mrg ;; versions of GDB, which also interprets prologues. This has been 448 1.1 mrg ;; fixed as of GDB 4.18, but it does not harm to unconditionally 449 1.1 mrg ;; use lda here. 450 1.1 mrg ;; 451 1.1 mrg ;; and the fact that the three insns schedule exactly the same, it's 452 1.1 mrg ;; just not worth the effort. 453 1.1 mrg 454 1.1 mrg (define_insn "*adddi_internal" 455 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r,r,r") 456 1.1 mrg (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r") 457 1.1 mrg (match_operand:DI 2 "add_operand" "r,K,L")))] 458 1.1 mrg "" 459 1.1 mrg "@ 460 1.1 mrg addq %1,%2,%0 461 1.1 mrg lda %0,%2(%1) 462 1.1 mrg ldah %0,%h2(%1)") 463 1.1 mrg 464 1.1 mrg ;; ??? Allow large constants when basing off the frame pointer or some 465 1.1 mrg ;; virtual register that may eliminate to the frame pointer. This is 466 1.1 mrg ;; done because register elimination offsets will change the hi/lo split, 467 1.1 mrg ;; and if we split before reload, we will require additional instructions. 468 1.1 mrg 469 1.1 mrg (define_insn "*adddi_fp_hack" 470 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r,r,r") 471 1.1 mrg (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r,r,r") 472 1.1 mrg (match_operand:DI 2 "const_int_operand" "K,L,n")))] 473 1.1 mrg "NONSTRICT_REG_OK_FP_BASE_P (operands[1]) 474 1.1 mrg && INTVAL (operands[2]) >= 0 475 1.1 mrg /* This is the largest constant an lda+ldah pair can add, minus 476 1.1 mrg an upper bound on the displacement between SP and AP during 477 1.1 mrg register elimination. See INITIAL_ELIMINATION_OFFSET. */ 478 1.1 mrg && INTVAL (operands[2]) 479 1.1 mrg < (0x7fff8000 480 1.1 mrg - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD 481 1.1 mrg - ALPHA_ROUND(crtl->outgoing_args_size) 482 1.1 mrg - (ALPHA_ROUND (get_frame_size () 483 1.1 mrg + max_reg_num () * UNITS_PER_WORD 484 1.1 mrg + crtl->args.pretend_args_size) 485 1.1 mrg - crtl->args.pretend_args_size))" 486 1.1 mrg "@ 487 1.1 mrg lda %0,%2(%1) 488 1.1 mrg ldah %0,%h2(%1) 489 1.1 mrg #") 490 1.1.1.2 mrg 491 1.1.1.2 mrg ;; Don't do this if we are adjusting SP since we don't want to do it 492 1.1.1.2 mrg ;; in two steps. Don't split FP sources for the reason listed above. 493 1.1 mrg (define_split 494 1.1 mrg [(set (match_operand:DI 0 "register_operand") 495 1.1 mrg (plus:DI (match_operand:DI 1 "register_operand") 496 1.1 mrg (match_operand:DI 2 "const_int_operand")))] 497 1.1 mrg "! add_operand (operands[2], DImode) 498 1.1 mrg && operands[0] != stack_pointer_rtx 499 1.1 mrg && operands[1] != frame_pointer_rtx 500 1.1 mrg && operands[1] != arg_pointer_rtx" 501 1.1 mrg [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3))) 502 1.1 mrg (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] 503 1.1 mrg { 504 1.1 mrg HOST_WIDE_INT val = INTVAL (operands[2]); 505 1.1 mrg HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); 506 1.1 mrg HOST_WIDE_INT rest = val - low; 507 1.1 mrg rtx rest_rtx = GEN_INT (rest); 508 1.1 mrg 509 1.1 mrg operands[4] = GEN_INT (low); 510 1.1 mrg if (satisfies_constraint_L (rest_rtx)) 511 1.1 mrg operands[3] = rest_rtx; 512 1.1 mrg else if (can_create_pseudo_p ()) 513 1.1 mrg { 514 1.1 mrg operands[3] = gen_reg_rtx (DImode); 515 1.1 mrg emit_move_insn (operands[3], operands[2]); 516 1.1 mrg emit_insn (gen_adddi3 (operands[0], operands[1], operands[3])); 517 1.1 mrg DONE; 518 1.1 mrg } 519 1.1.1.2 mrg else 520 1.1.1.2 mrg FAIL; 521 1.1.1.2 mrg }) 522 1.1.1.6 mrg 523 1.1.1.6 mrg (define_insn "*sadd<modesuffix>" 524 1.1.1.2 mrg [(set (match_operand:I48MODE 0 "register_operand" "=r,r") 525 1.1 mrg (plus:I48MODE 526 1.1 mrg (ashift:I48MODE (match_operand:I48MODE 1 "reg_not_elim_operand" "r,r") 527 1.1.1.6 mrg (match_operand:I48MODE 2 "const23_operand" "I,I")) 528 1.1.1.6 mrg (match_operand:I48MODE 3 "sext_add_operand" "rI,O")))] 529 1.1.1.6 mrg "" 530 1.1 mrg "@ 531 1.1 mrg s%P2add<modesuffix> %1,%3,%0 532 1.1 mrg s%P2sub<modesuffix> %1,%n3,%0") 533 1.1.1.6 mrg 534 1.1.1.6 mrg (define_insn "*saddl_se" 535 1.1.1.6 mrg [(set (match_operand:DI 0 "register_operand" "=r,r") 536 1.1.1.6 mrg (sign_extend:DI 537 1.1 mrg (plus:SI 538 1.1 mrg (ashift:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r") 539 1.1.1.6 mrg (match_operand:SI 2 "const23_operand" "I,I")) 540 1.1.1.6 mrg (match_operand:SI 3 "sext_add_operand" "rI,O"))))] 541 1.1.1.6 mrg "" 542 1.1 mrg "@ 543 1.1.1.2 mrg s%P2addl %1,%3,%0 544 1.1 mrg s%P2subl %1,%n3,%0") 545 1.1.1.6 mrg 546 1.1.1.2 mrg (define_split 547 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand") 548 1.1.1.6 mrg (sign_extend:DI 549 1.1.1.2 mrg (plus:SI (ashift:SI (match_operator:SI 1 "comparison_operator" 550 1.1.1.2 mrg [(match_operand 2) 551 1.1 mrg (match_operand 3)]) 552 1.1 mrg (match_operand:SI 4 "const23_operand")) 553 1.1 mrg (match_operand:SI 5 "sext_add_operand")))) 554 1.1.1.6 mrg (clobber (match_operand:DI 6 "reg_not_elim_operand"))] 555 1.1 mrg "" 556 1.1 mrg [(set (match_dup 6) (match_dup 7)) 557 1.1 mrg (set (match_dup 0) 558 1.1 mrg (sign_extend:DI (plus:SI (ashift:SI (match_dup 8) (match_dup 4)) 559 1.1 mrg (match_dup 5))))] 560 1.1 mrg { 561 1.1 mrg operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode, 562 1.1.1.2 mrg operands[2], operands[3]); 563 1.1.1.2 mrg operands[8] = gen_lowpart (SImode, operands[6]); 564 1.1.1.2 mrg }) 565 1.1.1.2 mrg 566 1.1.1.2 mrg (define_insn "addv<mode>3" 567 1.1.1.2 mrg [(set (match_operand:I48MODE 0 "register_operand" "=r,r") 568 1.1.1.2 mrg (plus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ,rJ") 569 1.1.1.2 mrg (match_operand:I48MODE 2 "sext_add_operand" "rI,O"))) 570 1.1 mrg (trap_if (ne (plus:<DWI> (sign_extend:<DWI> (match_dup 1)) 571 1.1 mrg (sign_extend:<DWI> (match_dup 2))) 572 1.1 mrg (sign_extend:<DWI> (plus:I48MODE (match_dup 1) 573 1.1.1.2 mrg (match_dup 2)))) 574 1.1.1.2 mrg (const_int 0))] 575 1.1 mrg "" 576 1.1.1.2 mrg "@ 577 1.1.1.2 mrg add<modesuffix>v %r1,%2,%0 578 1.1.1.2 mrg sub<modesuffix>v %r1,%n2,%0") 579 1.1 mrg 580 1.1.1.2 mrg (define_insn "neg<mode>2" 581 1.1 mrg [(set (match_operand:I48MODE 0 "register_operand" "=r") 582 1.1 mrg (neg:I48MODE (match_operand:I48MODE 1 "reg_or_8bit_operand" "rI")))] 583 1.1 mrg "" 584 1.1 mrg "sub<modesuffix> $31,%1,%0") 585 1.1 mrg 586 1.1 mrg (define_insn "*negsi_se" 587 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 588 1.1 mrg (sign_extend:DI (neg:SI 589 1.1.1.2 mrg (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))] 590 1.1.1.2 mrg "" 591 1.1.1.2 mrg "subl $31,%1,%0") 592 1.1.1.2 mrg 593 1.1.1.2 mrg (define_insn "negv<mode>2" 594 1.1 mrg [(set (match_operand:I48MODE 0 "register_operand" "=r") 595 1.1 mrg (neg:I48MODE (match_operand:I48MODE 1 "register_operand" "r"))) 596 1.1.1.2 mrg (trap_if (ne (neg:<DWI> (sign_extend:<DWI> (match_dup 1))) 597 1.1 mrg (sign_extend:<DWI> (neg:I48MODE (match_dup 1)))) 598 1.1.1.2 mrg (const_int 0))] 599 1.1.1.2 mrg "" 600 1.1.1.2 mrg "sub<modesuffix>v $31,%1,%0") 601 1.1.1.2 mrg 602 1.1 mrg (define_insn "sub<mode>3" 603 1.1.1.2 mrg [(set (match_operand:I48MODE 0 "register_operand" "=r") 604 1.1 mrg (minus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rJ") 605 1.1 mrg (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI")))] 606 1.1 mrg "" 607 1.1.1.2 mrg "sub<modesuffix> %r1,%2,%0") 608 1.1.1.2 mrg 609 1.1.1.2 mrg (define_insn "*subsi_se" 610 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 611 1.1 mrg (sign_extend:DI 612 1.1 mrg (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") 613 1.1 mrg (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))] 614 1.1 mrg "" 615 1.1 mrg "subl %r1,%2,%0") 616 1.1 mrg 617 1.1 mrg (define_insn "*subsi_se2" 618 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 619 1.1 mrg (sign_extend:DI 620 1.1 mrg (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 621 1.1 mrg (match_operand:DI 2 "reg_or_8bit_operand" "rI")) 622 1.1.1.2 mrg 0)))] 623 1.1.1.2 mrg "" 624 1.1.1.2 mrg "subl %r1,%2,%0") 625 1.1.1.6 mrg 626 1.1.1.6 mrg (define_insn "*ssub<modesuffix>" 627 1.1.1.2 mrg [(set (match_operand:I48MODE 0 "register_operand" "=r") 628 1.1 mrg (minus:I48MODE 629 1.1.1.6 mrg (ashift:I48MODE (match_operand:I48MODE 1 "reg_not_elim_operand" "r") 630 1.1.1.6 mrg (match_operand:I48MODE 2 "const23_operand" "I")) 631 1.1 mrg (match_operand:I48MODE 3 "reg_or_8bit_operand" "rI")))] 632 1.1 mrg "" 633 1.1 mrg "s%P2sub<modesuffix> %1,%3,%0") 634 1.1.1.6 mrg 635 1.1.1.6 mrg (define_insn "*ssubl_se" 636 1.1.1.6 mrg [(set (match_operand:DI 0 "register_operand" "=r") 637 1.1.1.6 mrg (sign_extend:DI 638 1.1.1.6 mrg (minus:SI 639 1.1.1.6 mrg (ashift:SI (match_operand:SI 1 "reg_not_elim_operand" "r") 640 1.1.1.6 mrg (match_operand:SI 2 "const23_operand" "I")) 641 1.1.1.2 mrg (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))] 642 1.1.1.2 mrg "" 643 1.1.1.2 mrg "s%P2subl %1,%3,%0") 644 1.1.1.2 mrg 645 1.1.1.2 mrg (define_insn "subv<mode>3" 646 1.1.1.2 mrg [(set (match_operand:I48MODE 0 "register_operand" "=r") 647 1.1.1.2 mrg (minus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rJ") 648 1.1.1.2 mrg (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI"))) 649 1.1 mrg (trap_if (ne (minus:<DWI> (sign_extend:<DWI> (match_dup 1)) 650 1.1 mrg (sign_extend:<DWI> (match_dup 2))) 651 1.1.1.2 mrg (sign_extend:<DWI> (minus:I48MODE (match_dup 1) 652 1.1 mrg (match_dup 2)))) 653 1.1.1.2 mrg (const_int 0))] 654 1.1.1.2 mrg "" 655 1.1.1.2 mrg "sub<modesuffix>v %r1,%2,%0") 656 1.1.1.2 mrg 657 1.1.1.2 mrg (define_insn "mul<mode>3" 658 1.1.1.2 mrg [(set (match_operand:I48MODE 0 "register_operand" "=r") 659 1.1 mrg (mult:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ") 660 1.1.1.2 mrg (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI")))] 661 1.1 mrg "" 662 1.1 mrg "mul<modesuffix> %r1,%2,%0" 663 1.1 mrg [(set_attr "type" "imul") 664 1.1 mrg (set_attr "opsize" "<mode>")]) 665 1.1 mrg 666 1.1 mrg (define_insn "*mulsi_se" 667 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand" "=r") 668 1.1 mrg (sign_extend:DI 669 1.1 mrg (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ") 670 1.1 mrg (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))] 671 1.1 mrg "" 672 1.1.1.2 mrg "mull %r1,%2,%0" 673 1.1.1.2 mrg [(set_attr "type" "imul") 674 1.1.1.2 mrg (set_attr "opsize" "si")]) 675 1.1.1.2 mrg 676 1.1.1.2 mrg (define_insn "mulv<mode>3" 677 1.1.1.2 mrg [(set (match_operand:I48MODE 0 "register_operand" "=r") 678 1.1.1.2 mrg (mult:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ") 679 1.1.1.2 mrg (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI"))) 680 1.1 mrg (trap_if (ne (mult:<DWI> (sign_extend:<DWI> (match_dup 1)) 681 1.1 mrg (sign_extend:<DWI> (match_dup 2))) 682 1.1.1.2 mrg (sign_extend:<DWI> (mult:I48MODE (match_dup 1) 683 1.1.1.2 mrg (match_dup 2)))) 684 1.1.1.2 mrg (const_int 0))] 685 1.1 mrg "" 686 1.1 mrg "mul<modesuffix>v %r1,%2,%0" 687 1.1.1.2 mrg [(set_attr "type" "imul") 688 1.1 mrg (set_attr "opsize" "<mode>")]) 689 1.1 mrg 690 1.1 mrg (define_expand "umuldi3_highpart" 691 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand") 692 1.1.1.2 mrg (truncate:DI 693 1.1 mrg (lshiftrt:TI 694 1.1 mrg (mult:TI (zero_extend:TI 695 1.1 mrg (match_operand:DI 1 "register_operand")) 696 1.1 mrg (match_operand:DI 2 "reg_or_8bit_operand")) 697 1.1 mrg (const_int 64))))] 698 1.1 mrg "" 699 1.1 mrg { 700 1.1 mrg if (REG_P (operands[2])) 701 1.1 mrg operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]); 702 1.1 mrg }) 703 1.1 mrg 704 1.1 mrg (define_insn "*umuldi3_highpart_reg" 705 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 706 1.1 mrg (truncate:DI 707 1.1 mrg (lshiftrt:TI 708 1.1 mrg (mult:TI (zero_extend:TI 709 1.1 mrg (match_operand:DI 1 "register_operand" "r")) 710 1.1 mrg (zero_extend:TI 711 1.1 mrg (match_operand:DI 2 "register_operand" "r"))) 712 1.1 mrg (const_int 64))))] 713 1.1 mrg "" 714 1.1 mrg "umulh %1,%2,%0" 715 1.1 mrg [(set_attr "type" "imul") 716 1.1 mrg (set_attr "opsize" "udi")]) 717 1.1 mrg 718 1.1 mrg (define_insn "*umuldi3_highpart_const" 719 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 720 1.1 mrg (truncate:DI 721 1.1 mrg (lshiftrt:TI 722 1.1 mrg (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r")) 723 1.1 mrg (match_operand:TI 2 "cint8_operand" "I")) 724 1.1 mrg (const_int 64))))] 725 1.1.1.2 mrg "" 726 1.1.1.2 mrg "umulh %1,%2,%0" 727 1.1.1.2 mrg [(set_attr "type" "imul") 728 1.1.1.2 mrg (set_attr "opsize" "udi")]) 729 1.1.1.2 mrg 730 1.1.1.2 mrg (define_expand "umulditi3" 731 1.1.1.2 mrg [(set (match_operand:TI 0 "register_operand") 732 1.1.1.2 mrg (mult:TI 733 1.1.1.2 mrg (zero_extend:TI (match_operand:DI 1 "reg_no_subreg_operand")) 734 1.1.1.2 mrg (zero_extend:TI (match_operand:DI 2 "reg_no_subreg_operand"))))] 735 1.1.1.2 mrg "" 736 1.1.1.2 mrg { 737 1.1.1.2 mrg rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode); 738 1.1.1.2 mrg emit_insn (gen_muldi3 (l, operands[1], operands[2])); 739 1.1.1.2 mrg emit_insn (gen_umuldi3_highpart (h, operands[1], operands[2])); 740 1.1 mrg emit_move_insn (gen_lowpart (DImode, operands[0]), l); 741 1.1 mrg emit_move_insn (gen_highpart (DImode, operands[0]), h); 742 1.1.1.2 mrg DONE; 743 1.1.1.2 mrg }) 744 1.1 mrg 746 1.1 mrg ;; The divide and remainder operations take their inputs from r24 and 747 1.1 mrg ;; r25, put their output in r27, and clobber r23 and r28 on all systems. 748 1.1 mrg ;; 749 1.1 mrg ;; ??? Force sign-extension here because some versions of OSF/1 and 750 1.1.1.2 mrg ;; Interix/NT don't do the right thing if the inputs are not properly 751 1.1 mrg ;; sign-extended. But Linux, for instance, does not have this 752 1.1.1.2 mrg ;; problem. Is it worth the complication here to eliminate the sign 753 1.1 mrg ;; extension? 754 1.1.1.2 mrg 755 1.1 mrg (define_code_iterator any_divmod [div mod udiv umod]) 756 1.1.1.2 mrg 757 1.1 mrg (define_expand "<code>si3" 758 1.1.1.2 mrg [(set (match_dup 3) 759 1.1.1.2 mrg (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"))) 760 1.1 mrg (set (match_dup 4) 761 1.1 mrg (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand"))) 762 1.1.1.2 mrg (parallel [(set (match_dup 5) 763 1.1 mrg (sign_extend:DI 764 1.1.1.2 mrg (any_divmod:SI (match_dup 3) (match_dup 4)))) 765 1.1 mrg (clobber (reg:DI 23)) 766 1.1 mrg (clobber (reg:DI 28))]) 767 1.1 mrg (set (match_operand:SI 0 "nonimmediate_operand") 768 1.1 mrg (subreg:SI (match_dup 5) 0))] 769 1.1 mrg "TARGET_ABI_OSF" 770 1.1 mrg { 771 1.1.1.2 mrg operands[3] = gen_reg_rtx (DImode); 772 1.1.1.2 mrg operands[4] = gen_reg_rtx (DImode); 773 1.1.1.2 mrg operands[5] = gen_reg_rtx (DImode); 774 1.1.1.2 mrg }) 775 1.1.1.2 mrg 776 1.1 mrg (define_expand "<code>di3" 777 1.1 mrg [(parallel [(set (match_operand:DI 0 "register_operand") 778 1.1.1.2 mrg (any_divmod:DI 779 1.1 mrg (match_operand:DI 1 "register_operand") 780 1.1 mrg (match_operand:DI 2 "register_operand"))) 781 1.1 mrg (clobber (reg:DI 23)) 782 1.1 mrg (clobber (reg:DI 28))])] 783 1.1 mrg "TARGET_ABI_OSF") 784 1.1 mrg 785 1.1 mrg ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as 786 1.1 mrg ;; expanded by the assembler. 787 1.1 mrg 788 1.1 mrg (define_insn_and_split "*divmodsi_internal_er" 789 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=c") 790 1.1.1.2 mrg (sign_extend:DI (match_operator:SI 3 "divmod_operator" 791 1.1 mrg [(match_operand:DI 1 "register_operand" "a") 792 1.1 mrg (match_operand:DI 2 "register_operand" "b")]))) 793 1.1 mrg (clobber (reg:DI 23)) 794 1.1 mrg (clobber (reg:DI 28))] 795 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 796 1.1 mrg "#" 797 1.1 mrg "&& reload_completed" 798 1.1 mrg [(parallel [(set (match_dup 0) 799 1.1 mrg (sign_extend:DI (match_dup 3))) 800 1.1 mrg (use (match_dup 0)) 801 1.1 mrg (use (match_dup 4)) 802 1.1 mrg (clobber (reg:DI 23)) 803 1.1 mrg (clobber (reg:DI 28))])] 804 1.1 mrg { 805 1.1 mrg const char *str; 806 1.1 mrg switch (GET_CODE (operands[3])) 807 1.1 mrg { 808 1.1 mrg case DIV: 809 1.1 mrg str = "__divl"; 810 1.1 mrg break; 811 1.1 mrg case UDIV: 812 1.1 mrg str = "__divlu"; 813 1.1 mrg break; 814 1.1 mrg case MOD: 815 1.1 mrg str = "__reml"; 816 1.1 mrg break; 817 1.1 mrg case UMOD: 818 1.1 mrg str = "__remlu"; 819 1.1 mrg break; 820 1.1 mrg default: 821 1.1 mrg gcc_unreachable (); 822 1.1 mrg } 823 1.1 mrg operands[4] = GEN_INT (alpha_next_sequence_number++); 824 1.1 mrg emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx, 825 1.1 mrg gen_rtx_SYMBOL_REF (DImode, str), 826 1.1 mrg operands[4])); 827 1.1 mrg } 828 1.1 mrg [(set_attr "type" "jsr") 829 1.1 mrg (set_attr "length" "8")]) 830 1.1 mrg 831 1.1 mrg (define_insn "*divmodsi_internal_er_1" 832 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand" "=c") 833 1.1 mrg (sign_extend:DI (match_operator:SI 3 "divmod_operator" 834 1.1 mrg [(match_operand:DI 1 "register_operand" "a") 835 1.1.1.2 mrg (match_operand:DI 2 "register_operand" "b")]))) 836 1.1 mrg (use (match_operand:DI 4 "register_operand" "c")) 837 1.1 mrg (use (match_operand 5 "const_int_operand")) 838 1.1 mrg (clobber (reg:DI 23)) 839 1.1 mrg (clobber (reg:DI 28))] 840 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 841 1.1 mrg "jsr $23,($27),__%E3%j5" 842 1.1 mrg [(set_attr "type" "jsr") 843 1.1 mrg (set_attr "length" "4")]) 844 1.1 mrg 845 1.1 mrg (define_insn "*divmodsi_internal" 846 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=c") 847 1.1.1.2 mrg (sign_extend:DI (match_operator:SI 3 "divmod_operator" 848 1.1 mrg [(match_operand:DI 1 "register_operand" "a") 849 1.1 mrg (match_operand:DI 2 "register_operand" "b")]))) 850 1.1 mrg (clobber (reg:DI 23)) 851 1.1 mrg (clobber (reg:DI 28))] 852 1.1 mrg "TARGET_ABI_OSF" 853 1.1 mrg "%E3 %1,%2,%0" 854 1.1 mrg [(set_attr "type" "jsr") 855 1.1 mrg (set_attr "length" "8")]) 856 1.1 mrg 857 1.1 mrg (define_insn_and_split "*divmoddi_internal_er" 858 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=c") 859 1.1.1.2 mrg (match_operator:DI 3 "divmod_operator" 860 1.1 mrg [(match_operand:DI 1 "register_operand" "a") 861 1.1 mrg (match_operand:DI 2 "register_operand" "b")])) 862 1.1 mrg (clobber (reg:DI 23)) 863 1.1 mrg (clobber (reg:DI 28))] 864 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 865 1.1 mrg "#" 866 1.1 mrg "&& reload_completed" 867 1.1 mrg [(parallel [(set (match_dup 0) (match_dup 3)) 868 1.1 mrg (use (match_dup 0)) 869 1.1 mrg (use (match_dup 4)) 870 1.1 mrg (clobber (reg:DI 23)) 871 1.1 mrg (clobber (reg:DI 28))])] 872 1.1 mrg { 873 1.1 mrg const char *str; 874 1.1 mrg switch (GET_CODE (operands[3])) 875 1.1 mrg { 876 1.1 mrg case DIV: 877 1.1 mrg str = "__divq"; 878 1.1 mrg break; 879 1.1 mrg case UDIV: 880 1.1 mrg str = "__divqu"; 881 1.1 mrg break; 882 1.1 mrg case MOD: 883 1.1 mrg str = "__remq"; 884 1.1 mrg break; 885 1.1 mrg case UMOD: 886 1.1 mrg str = "__remqu"; 887 1.1 mrg break; 888 1.1 mrg default: 889 1.1 mrg gcc_unreachable (); 890 1.1 mrg } 891 1.1 mrg operands[4] = GEN_INT (alpha_next_sequence_number++); 892 1.1 mrg emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx, 893 1.1 mrg gen_rtx_SYMBOL_REF (DImode, str), 894 1.1 mrg operands[4])); 895 1.1 mrg } 896 1.1 mrg [(set_attr "type" "jsr") 897 1.1 mrg (set_attr "length" "8")]) 898 1.1 mrg 899 1.1 mrg (define_insn "*divmoddi_internal_er_1" 900 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand" "=c") 901 1.1 mrg (match_operator:DI 3 "divmod_operator" 902 1.1 mrg [(match_operand:DI 1 "register_operand" "a") 903 1.1.1.2 mrg (match_operand:DI 2 "register_operand" "b")])) 904 1.1 mrg (use (match_operand:DI 4 "register_operand" "c")) 905 1.1 mrg (use (match_operand 5 "const_int_operand")) 906 1.1 mrg (clobber (reg:DI 23)) 907 1.1 mrg (clobber (reg:DI 28))] 908 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 909 1.1 mrg "jsr $23,($27),__%E3%j5" 910 1.1 mrg [(set_attr "type" "jsr") 911 1.1 mrg (set_attr "length" "4")]) 912 1.1 mrg 913 1.1 mrg (define_insn "*divmoddi_internal" 914 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=c") 915 1.1.1.2 mrg (match_operator:DI 3 "divmod_operator" 916 1.1 mrg [(match_operand:DI 1 "register_operand" "a") 917 1.1 mrg (match_operand:DI 2 "register_operand" "b")])) 918 1.1 mrg (clobber (reg:DI 23)) 919 1.1 mrg (clobber (reg:DI 28))] 920 1.1 mrg "TARGET_ABI_OSF" 921 1.1 mrg "%E3 %1,%2,%0" 922 1.1 mrg [(set_attr "type" "jsr") 923 1.1 mrg (set_attr "length" "8")]) 924 1.1 mrg 926 1.1 mrg ;; Next are the basic logical operations. We only expose the DImode operations 927 1.1.1.4 mrg ;; to the rtl expanders, but SImode versions exist for combine as well as for 928 1.1 mrg ;; the atomic operation splitters. 929 1.1 mrg 930 1.1 mrg (define_insn "*andsi_internal" 931 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=r,r,r") 932 1.1 mrg (and:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ") 933 1.1 mrg (match_operand:SI 2 "and_operand" "rI,N,M")))] 934 1.1 mrg "" 935 1.1 mrg "@ 936 1.1 mrg and %r1,%2,%0 937 1.1 mrg bic %r1,%N2,%0 938 1.1.1.4 mrg zapnot %r1,%m2,%0" 939 1.1 mrg [(set_attr "type" "ilog,ilog,shift")]) 940 1.1 mrg 941 1.1 mrg (define_insn "anddi3" 942 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r,r,r") 943 1.1 mrg (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ") 944 1.1 mrg (match_operand:DI 2 "and_operand" "rI,N,M")))] 945 1.1 mrg "" 946 1.1 mrg "@ 947 1.1 mrg and %r1,%2,%0 948 1.1 mrg bic %r1,%N2,%0 949 1.1 mrg zapnot %r1,%m2,%0" 950 1.1 mrg [(set_attr "type" "ilog,ilog,shift")]) 951 1.1 mrg 952 1.1 mrg ;; There are times when we can split an AND into two AND insns. This occurs 953 1.1.1.2 mrg ;; when we can first clear any bytes and then clear anything else. For 954 1.1.1.2 mrg ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07". 955 1.1.1.2 mrg ;; Only do this when running on 64-bit host since the computations are 956 1.1.1.4 mrg ;; too messy otherwise. 957 1.1 mrg 958 1.1 mrg (define_split 959 1.1 mrg [(set (match_operand:DI 0 "register_operand") 960 1.1 mrg (and:DI (match_operand:DI 1 "register_operand") 961 1.1 mrg (match_operand:DI 2 "const_int_operand")))] 962 1.1 mrg "! and_operand (operands[2], DImode)" 963 1.1 mrg [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3))) 964 1.1 mrg (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))] 965 1.1 mrg { 966 1.1 mrg unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]); 967 1.1 mrg unsigned HOST_WIDE_INT mask2 = mask1; 968 1.1 mrg int i; 969 1.1 mrg 970 1.1 mrg /* For each byte that isn't all zeros, make it all ones. */ 971 1.1 mrg for (i = 0; i < 64; i += 8) 972 1.1 mrg if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0) 973 1.1 mrg mask1 |= (HOST_WIDE_INT) 0xff << i; 974 1.1 mrg 975 1.1 mrg /* Now turn on any bits we've just turned off. */ 976 1.1.1.2 mrg mask2 |= ~ mask1; 977 1.1.1.2 mrg 978 1.1.1.2 mrg operands[3] = GEN_INT (mask1); 979 1.1.1.2 mrg operands[4] = GEN_INT (mask2); 980 1.1 mrg }) 981 1.1 mrg 982 1.1 mrg (define_insn "zero_extendqi<mode>2" 983 1.1 mrg [(set (match_operand:I248MODE 0 "register_operand" "=r,r") 984 1.1.1.2 mrg (zero_extend:I248MODE 985 1.1.1.2 mrg (match_operand:QI 1 "reg_or_bwx_memory_operand" "r,m")))] 986 1.1 mrg "" 987 1.1.1.2 mrg "@ 988 1.1.1.2 mrg and %1,0xff,%0 989 1.1.1.2 mrg ldbu %0,%1" 990 1.1.1.2 mrg [(set_attr "type" "ilog,ild") 991 1.1 mrg (set_attr "isa" "*,bwx")]) 992 1.1 mrg 993 1.1 mrg (define_insn "zero_extendhi<mode>2" 994 1.1 mrg [(set (match_operand:I48MODE 0 "register_operand" "=r,r") 995 1.1.1.2 mrg (zero_extend:I48MODE 996 1.1.1.2 mrg (match_operand:HI 1 "reg_or_bwx_memory_operand" "r,m")))] 997 1.1 mrg "" 998 1.1 mrg "@ 999 1.1 mrg zapnot %1,3,%0 1000 1.1 mrg ldwu %0,%1" 1001 1.1 mrg [(set_attr "type" "shift,ild") 1002 1.1 mrg (set_attr "isa" "*,bwx")]) 1003 1.1 mrg 1004 1.1 mrg (define_insn "zero_extendsidi2" 1005 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1006 1.1.1.2 mrg (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))] 1007 1.1.1.2 mrg "" 1008 1.1.1.2 mrg "zapnot %1,15,%0" 1009 1.1.1.2 mrg [(set_attr "type" "shift")]) 1010 1.1 mrg 1011 1.1 mrg (define_insn "andnot<mode>3" 1012 1.1 mrg [(set (match_operand:I48MODE 0 "register_operand" "=r") 1013 1.1 mrg (and:I48MODE 1014 1.1 mrg (not:I48MODE (match_operand:I48MODE 1 "reg_or_8bit_operand" "rI")) 1015 1.1 mrg (match_operand:I48MODE 2 "reg_or_0_operand" "rJ")))] 1016 1.1 mrg "" 1017 1.1 mrg "bic %r2,%1,%0" 1018 1.1 mrg [(set_attr "type" "ilog")]) 1019 1.1 mrg 1020 1.1 mrg (define_insn "*iorsi_internal" 1021 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=r,r") 1022 1.1 mrg (ior:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ") 1023 1.1 mrg (match_operand:SI 2 "or_operand" "rI,N")))] 1024 1.1 mrg "" 1025 1.1 mrg "@ 1026 1.1 mrg bis %r1,%2,%0 1027 1.1 mrg ornot %r1,%N2,%0" 1028 1.1 mrg [(set_attr "type" "ilog")]) 1029 1.1 mrg 1030 1.1 mrg (define_insn "iordi3" 1031 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r,r") 1032 1.1 mrg (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ") 1033 1.1 mrg (match_operand:DI 2 "or_operand" "rI,N")))] 1034 1.1 mrg "" 1035 1.1 mrg "@ 1036 1.1 mrg bis %r1,%2,%0 1037 1.1 mrg ornot %r1,%N2,%0" 1038 1.1 mrg [(set_attr "type" "ilog")]) 1039 1.1 mrg 1040 1.1 mrg (define_insn "*one_cmplsi_internal" 1041 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=r") 1042 1.1 mrg (not:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))] 1043 1.1 mrg "" 1044 1.1 mrg "ornot $31,%1,%0" 1045 1.1 mrg [(set_attr "type" "ilog")]) 1046 1.1 mrg 1047 1.1 mrg (define_insn "one_cmpldi2" 1048 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1049 1.1.1.2 mrg (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))] 1050 1.1.1.2 mrg "" 1051 1.1.1.2 mrg "ornot $31,%1,%0" 1052 1.1.1.2 mrg [(set_attr "type" "ilog")]) 1053 1.1 mrg 1054 1.1 mrg (define_insn "*iornot<mode>3" 1055 1.1 mrg [(set (match_operand:I48MODE 0 "register_operand" "=r") 1056 1.1 mrg (ior:I48MODE 1057 1.1 mrg (not:I48MODE (match_operand:I48MODE 1 "reg_or_8bit_operand" "rI")) 1058 1.1 mrg (match_operand:I48MODE 2 "reg_or_0_operand" "rJ")))] 1059 1.1 mrg "" 1060 1.1 mrg "ornot %r2,%1,%0" 1061 1.1 mrg [(set_attr "type" "ilog")]) 1062 1.1 mrg 1063 1.1 mrg (define_insn "*xorsi_internal" 1064 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=r,r") 1065 1.1 mrg (xor:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ") 1066 1.1 mrg (match_operand:SI 2 "or_operand" "rI,N")))] 1067 1.1 mrg "" 1068 1.1 mrg "@ 1069 1.1 mrg xor %r1,%2,%0 1070 1.1 mrg eqv %r1,%N2,%0" 1071 1.1 mrg [(set_attr "type" "ilog")]) 1072 1.1 mrg 1073 1.1 mrg (define_insn "xordi3" 1074 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r,r") 1075 1.1 mrg (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ") 1076 1.1 mrg (match_operand:DI 2 "or_operand" "rI,N")))] 1077 1.1.1.2 mrg "" 1078 1.1.1.2 mrg "@ 1079 1.1.1.2 mrg xor %r1,%2,%0 1080 1.1.1.2 mrg eqv %r1,%N2,%0" 1081 1.1.1.2 mrg [(set_attr "type" "ilog")]) 1082 1.1 mrg 1083 1.1 mrg (define_insn "*xornot<mode>3" 1084 1.1 mrg [(set (match_operand:I48MODE 0 "register_operand" "=r") 1085 1.1 mrg (not:I48MODE (xor:I48MODE 1086 1.1 mrg (match_operand:I48MODE 1 "register_operand" "%rJ") 1087 1.1 mrg (match_operand:I48MODE 2 "register_operand" "rI"))))] 1088 1.1 mrg "" 1089 1.1 mrg "eqv %r1,%2,%0" 1090 1.1.1.2 mrg [(set_attr "type" "ilog")]) 1091 1.1 mrg 1093 1.1.1.2 mrg ;; Handle FFS and related insns iff we support CIX. 1094 1.1 mrg 1095 1.1 mrg (define_expand "ffsdi2" 1096 1.1 mrg [(set (match_dup 2) 1097 1.1 mrg (ctz:DI (match_operand:DI 1 "register_operand"))) 1098 1.1 mrg (set (match_dup 3) 1099 1.1 mrg (plus:DI (match_dup 2) (const_int 1))) 1100 1.1 mrg (set (match_operand:DI 0 "register_operand") 1101 1.1 mrg (if_then_else:DI (eq (match_dup 1) (const_int 0)) 1102 1.1 mrg (const_int 0) (match_dup 3)))] 1103 1.1 mrg "TARGET_CIX" 1104 1.1 mrg { 1105 1.1 mrg operands[2] = gen_reg_rtx (DImode); 1106 1.1 mrg operands[3] = gen_reg_rtx (DImode); 1107 1.1 mrg }) 1108 1.1 mrg 1109 1.1 mrg (define_insn "clzdi2" 1110 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1111 1.1 mrg (clz:DI (match_operand:DI 1 "register_operand" "r")))] 1112 1.1 mrg "TARGET_CIX" 1113 1.1 mrg "ctlz %1,%0" 1114 1.1 mrg [(set_attr "type" "mvi")]) 1115 1.1 mrg 1116 1.1 mrg (define_insn "ctzdi2" 1117 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1118 1.1 mrg (ctz:DI (match_operand:DI 1 "register_operand" "r")))] 1119 1.1 mrg "TARGET_CIX" 1120 1.1 mrg "cttz %1,%0" 1121 1.1 mrg [(set_attr "type" "mvi")]) 1122 1.1 mrg 1123 1.1 mrg (define_insn "popcountdi2" 1124 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1125 1.1.1.2 mrg (popcount:DI (match_operand:DI 1 "register_operand" "r")))] 1126 1.1 mrg "TARGET_CIX" 1127 1.1 mrg "ctpop %1,%0" 1128 1.1 mrg [(set_attr "type" "mvi")]) 1129 1.1 mrg 1130 1.1 mrg (define_expand "bswapsi2" 1131 1.1 mrg [(set (match_operand:SI 0 "register_operand") 1132 1.1 mrg (bswap:SI (match_operand:SI 1 "register_operand")))] 1133 1.1.1.2 mrg "!optimize_size" 1134 1.1 mrg { 1135 1.1 mrg rtx t0, t1; 1136 1.1 mrg 1137 1.1 mrg t0 = gen_reg_rtx (DImode); 1138 1.1 mrg t1 = gen_reg_rtx (DImode); 1139 1.1 mrg 1140 1.1 mrg emit_insn (gen_inslh (t0, gen_lowpart (DImode, operands[1]), GEN_INT (7))); 1141 1.1 mrg emit_insn (gen_inswl_const (t1, gen_lowpart (HImode, operands[1]), 1142 1.1 mrg GEN_INT (24))); 1143 1.1 mrg emit_insn (gen_iordi3 (t1, t0, t1)); 1144 1.1 mrg emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (16))); 1145 1.1 mrg emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x5))); 1146 1.1.1.2 mrg emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xa))); 1147 1.1.1.2 mrg emit_insn (gen_addsi3 (operands[0], gen_lowpart (SImode, t0), 1148 1.1 mrg gen_lowpart (SImode, t1))); 1149 1.1 mrg DONE; 1150 1.1 mrg }) 1151 1.1 mrg 1152 1.1 mrg (define_expand "bswapdi2" 1153 1.1 mrg [(set (match_operand:DI 0 "register_operand") 1154 1.1 mrg (bswap:DI (match_operand:DI 1 "register_operand")))] 1155 1.1 mrg "!optimize_size" 1156 1.1 mrg { 1157 1.1 mrg rtx t0, t1; 1158 1.1 mrg 1159 1.1 mrg t0 = gen_reg_rtx (DImode); 1160 1.1 mrg t1 = gen_reg_rtx (DImode); 1161 1.1 mrg 1162 1.1 mrg /* This method of shifting and masking is not specific to Alpha, but 1163 1.1 mrg is only profitable on Alpha because of our handy byte zap insn. */ 1164 1.1 mrg 1165 1.1 mrg emit_insn (gen_lshrdi3 (t0, operands[1], GEN_INT (32))); 1166 1.1 mrg emit_insn (gen_ashldi3 (t1, operands[1], GEN_INT (32))); 1167 1.1 mrg emit_insn (gen_iordi3 (t1, t0, t1)); 1168 1.1 mrg 1169 1.1 mrg emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (16))); 1170 1.1 mrg emit_insn (gen_ashldi3 (t1, t1, GEN_INT (16))); 1171 1.1 mrg emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xcc))); 1172 1.1 mrg emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x33))); 1173 1.1 mrg emit_insn (gen_iordi3 (t1, t0, t1)); 1174 1.1 mrg 1175 1.1 mrg emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (8))); 1176 1.1 mrg emit_insn (gen_ashldi3 (t1, t1, GEN_INT (8))); 1177 1.1 mrg emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xaa))); 1178 1.1 mrg emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x55))); 1179 1.1 mrg emit_insn (gen_iordi3 (operands[0], t0, t1)); 1180 1.1 mrg DONE; 1181 1.1 mrg }) 1182 1.1 mrg 1184 1.1 mrg ;; Next come the shifts and the various extract and insert operations. 1185 1.1 mrg 1186 1.1 mrg (define_insn "ashldi3" 1187 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r,r") 1188 1.1 mrg (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ") 1189 1.1 mrg (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))] 1190 1.1 mrg "" 1191 1.1 mrg { 1192 1.1 mrg switch (which_alternative) 1193 1.1 mrg { 1194 1.1 mrg case 0: 1195 1.1 mrg if (operands[2] == const1_rtx) 1196 1.1 mrg return "addq %r1,%r1,%0"; 1197 1.1 mrg else 1198 1.1 mrg return "s%P2addq %r1,0,%0"; 1199 1.1.1.8 mrg case 1: 1200 1.1.1.8 mrg return "sll %r1,%2,%0"; 1201 1.1.1.8 mrg default: 1202 1.1.1.8 mrg gcc_unreachable (); 1203 1.1.1.8 mrg } 1204 1.1.1.8 mrg } 1205 1.1.1.8 mrg [(set_attr "type" "iadd,shift")]) 1206 1.1.1.8 mrg 1207 1.1.1.8 mrg (define_insn "ashlsi3" 1208 1.1.1.8 mrg [(set (match_operand:SI 0 "register_operand" "=r") 1209 1.1.1.8 mrg (ashift:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") 1210 1.1.1.8 mrg (match_operand:SI 2 "const123_operand" "P")))] 1211 1.1.1.8 mrg "" 1212 1.1.1.8 mrg { 1213 1.1 mrg if (operands[2] == const1_rtx) 1214 1.1 mrg return "addl %r1,%r1,%0"; 1215 1.1.1.8 mrg else 1216 1.1.1.8 mrg return "s%P2addl %r1,0,%0"; 1217 1.1.1.8 mrg } 1218 1.1 mrg [(set_attr "type" "iadd")]) 1219 1.1 mrg 1220 1.1 mrg (define_insn "*ashlsi_se" 1221 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1222 1.1 mrg (sign_extend:DI 1223 1.1 mrg (ashift:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") 1224 1.1 mrg (match_operand:SI 2 "const123_operand" "P"))))] 1225 1.1 mrg "" 1226 1.1 mrg { 1227 1.1 mrg if (operands[2] == const1_rtx) 1228 1.1 mrg return "addl %r1,%r1,%0"; 1229 1.1 mrg else 1230 1.1 mrg return "s%P2addl %r1,0,%0"; 1231 1.1 mrg } 1232 1.1 mrg [(set_attr "type" "iadd")]) 1233 1.1 mrg 1234 1.1 mrg (define_insn "lshrdi3" 1235 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1236 1.1 mrg (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1237 1.1 mrg (match_operand:DI 2 "reg_or_6bit_operand" "rS")))] 1238 1.1 mrg "" 1239 1.1 mrg "srl %r1,%2,%0" 1240 1.1 mrg [(set_attr "type" "shift")]) 1241 1.1 mrg 1242 1.1.1.2 mrg (define_insn "ashrdi3" 1243 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1244 1.1.1.2 mrg (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1245 1.1.1.2 mrg (match_operand:DI 2 "reg_or_6bit_operand" "rS")))] 1246 1.1.1.2 mrg "" 1247 1.1.1.2 mrg "sra %r1,%2,%0" 1248 1.1.1.2 mrg [(set_attr "type" "shift")]) 1249 1.1.1.2 mrg 1250 1.1.1.2 mrg (define_insn "extendqi<mode>2" 1251 1.1.1.2 mrg [(set (match_operand:I24MODE 0 "register_operand" "=r") 1252 1.1.1.4 mrg (sign_extend:I24MODE 1253 1.1 mrg (match_operand:QI 1 "register_operand" "r")))] 1254 1.1 mrg "TARGET_BWX" 1255 1.1 mrg "sextb %1,%0" 1256 1.1.1.2 mrg [(set_attr "type" "shift")]) 1257 1.1.1.2 mrg 1258 1.1 mrg (define_expand "extendqidi2" 1259 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand") 1260 1.1 mrg (sign_extend:DI (match_operand:QI 1 "general_operand")))] 1261 1.1.1.2 mrg "" 1262 1.1.1.2 mrg { 1263 1.1.1.2 mrg if (TARGET_BWX) 1264 1.1.1.2 mrg operands[1] = force_reg (QImode, operands[1]); 1265 1.1.1.2 mrg else 1266 1.1.1.2 mrg { 1267 1.1.1.2 mrg rtx x, t1, t2, i56; 1268 1.1 mrg 1269 1.1.1.2 mrg if (unaligned_memory_operand (operands[1], QImode)) 1270 1.1.1.2 mrg { 1271 1.1.1.2 mrg x = gen_unaligned_extendqidi (operands[0], XEXP (operands[1], 0)); 1272 1.1.1.2 mrg alpha_set_memflags (x, operands[1]); 1273 1.1.1.2 mrg emit_insn (x); 1274 1.1.1.2 mrg DONE; 1275 1.1.1.2 mrg } 1276 1.1.1.2 mrg 1277 1.1 mrg t1 = gen_reg_rtx (DImode); 1278 1.1 mrg t2 = gen_reg_rtx (DImode); 1279 1.1 mrg i56 = GEN_INT (56); 1280 1.1 mrg 1281 1.1.1.2 mrg x = gen_lowpart (DImode, force_reg (QImode, operands[1])); 1282 1.1 mrg emit_move_insn (t1, x); 1283 1.1 mrg emit_insn (gen_ashldi3 (t2, t1, i56)); 1284 1.1 mrg emit_insn (gen_ashrdi3 (operands[0], t2, i56)); 1285 1.1 mrg DONE; 1286 1.1 mrg } 1287 1.1 mrg }) 1288 1.1.1.2 mrg 1289 1.1 mrg (define_insn "*extendqidi2_bwx" 1290 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1291 1.1 mrg (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))] 1292 1.1 mrg "TARGET_BWX" 1293 1.1 mrg "sextb %1,%0" 1294 1.1 mrg [(set_attr "type" "shift")]) 1295 1.1.1.2 mrg 1296 1.1.1.2 mrg (define_insn "extendhisi2" 1297 1.1.1.4 mrg [(set (match_operand:SI 0 "register_operand" "=r") 1298 1.1 mrg (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))] 1299 1.1 mrg "TARGET_BWX" 1300 1.1 mrg "sextw %1,%0" 1301 1.1.1.2 mrg [(set_attr "type" "shift")]) 1302 1.1.1.2 mrg 1303 1.1 mrg (define_expand "extendhidi2" 1304 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand") 1305 1.1.1.2 mrg (sign_extend:DI (match_operand:HI 1 "general_operand")))] 1306 1.1.1.2 mrg "" 1307 1.1.1.2 mrg { 1308 1.1.1.2 mrg if (TARGET_BWX) 1309 1.1.1.2 mrg operands[1] = force_reg (HImode, operands[1]); 1310 1.1.1.2 mrg else 1311 1.1.1.2 mrg { 1312 1.1.1.2 mrg rtx x, t1, t2, i48; 1313 1.1.1.2 mrg 1314 1.1.1.2 mrg if (unaligned_memory_operand (operands[1], HImode)) 1315 1.1.1.2 mrg { 1316 1.1.1.2 mrg x = gen_unaligned_extendhidi (operands[0], XEXP (operands[1], 0)); 1317 1.1.1.2 mrg alpha_set_memflags (x, operands[1]); 1318 1.1.1.2 mrg emit_insn (x); 1319 1.1.1.2 mrg DONE; 1320 1.1.1.2 mrg } 1321 1.1.1.2 mrg 1322 1.1 mrg t1 = gen_reg_rtx (DImode); 1323 1.1 mrg t2 = gen_reg_rtx (DImode); 1324 1.1 mrg i48 = GEN_INT (48); 1325 1.1 mrg 1326 1.1.1.2 mrg x = gen_lowpart (DImode, force_reg (HImode, operands[1])); 1327 1.1.1.2 mrg emit_move_insn (t1, x); 1328 1.1.1.2 mrg emit_insn (gen_ashldi3 (t2, t1, i48)); 1329 1.1.1.2 mrg emit_insn (gen_ashrdi3 (operands[0], t2, i48)); 1330 1.1.1.2 mrg DONE; 1331 1.1.1.2 mrg } 1332 1.1 mrg }) 1333 1.1 mrg 1334 1.1 mrg (define_insn "*extendhidi2_bwx" 1335 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1336 1.1 mrg (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))] 1337 1.1 mrg "TARGET_BWX" 1338 1.1 mrg "sextw %1,%0" 1339 1.1.1.2 mrg [(set_attr "type" "shift")]) 1340 1.1 mrg 1341 1.1.1.2 mrg ;; Here's how we sign extend an unaligned byte and halfword. Doing this 1342 1.1 mrg ;; as a pattern saves one instruction. The code is similar to that for 1343 1.1 mrg ;; the unaligned loads (see below). 1344 1.1 mrg ;; 1345 1.1 mrg ;; Operand 1 is the address, operand 0 is the result. 1346 1.1 mrg 1347 1.1 mrg (define_expand "unaligned_extendqidi" 1348 1.1.1.2 mrg [(set (match_dup 3) 1349 1.1 mrg (mem:DI (and:DI (match_operand:DI 1 "address_operand") (const_int -8)))) 1350 1.1.1.2 mrg (set (match_dup 4) 1351 1.1 mrg (ashift:DI (match_dup 3) 1352 1.1.1.2 mrg (minus:DI (const_int 64) 1353 1.1 mrg (ashift:DI 1354 1.1 mrg (and:DI (match_dup 2) (const_int 7)) 1355 1.1 mrg (const_int 3))))) 1356 1.1 mrg (set (match_operand:QI 0 "register_operand") 1357 1.1 mrg (ashiftrt:DI (match_dup 4) (const_int 56)))] 1358 1.1 mrg "" 1359 1.1 mrg { 1360 1.1.1.2 mrg operands[0] = gen_lowpart (DImode, operands[0]); 1361 1.1 mrg operands[2] = get_unaligned_offset (operands[1], 1); 1362 1.1 mrg operands[3] = gen_reg_rtx (DImode); 1363 1.1 mrg operands[4] = gen_reg_rtx (DImode); 1364 1.1 mrg }) 1365 1.1 mrg 1366 1.1 mrg (define_expand "unaligned_extendhidi" 1367 1.1.1.2 mrg [(set (match_dup 3) 1368 1.1 mrg (mem:DI (and:DI (match_operand:DI 1 "address_operand") (const_int -8)))) 1369 1.1.1.2 mrg (set (match_dup 4) 1370 1.1 mrg (ashift:DI (match_dup 3) 1371 1.1.1.2 mrg (minus:DI (const_int 64) 1372 1.1 mrg (ashift:DI 1373 1.1 mrg (and:DI (match_dup 2) (const_int 7)) 1374 1.1 mrg (const_int 3))))) 1375 1.1 mrg (set (match_operand:HI 0 "register_operand") 1376 1.1 mrg (ashiftrt:DI (match_dup 4) (const_int 48)))] 1377 1.1 mrg "" 1378 1.1 mrg { 1379 1.1 mrg operands[0] = gen_lowpart (DImode, operands[0]); 1380 1.1 mrg operands[2] = get_unaligned_offset (operands[1], 2); 1381 1.1 mrg operands[3] = gen_reg_rtx (DImode); 1382 1.1 mrg operands[4] = gen_reg_rtx (DImode); 1383 1.1 mrg }) 1384 1.1 mrg 1385 1.1 mrg (define_insn "*extxl_const" 1386 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1387 1.1 mrg (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1388 1.1.1.2 mrg (match_operand:DI 2 "mode_width_operand" "n") 1389 1.1.1.2 mrg (match_operand:DI 3 "mul8_operand" "I")))] 1390 1.1.1.2 mrg "" 1391 1.1.1.2 mrg "ext%M2l %r1,%s3,%0" 1392 1.1.1.2 mrg [(set_attr "type" "shift")]) 1393 1.1.1.2 mrg 1394 1.1 mrg (define_insn "extxl" 1395 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1396 1.1 mrg (zero_extract:DI 1397 1.1 mrg (match_operand:DI 1 "reg_or_0_operand" "rJ") 1398 1.1 mrg (match_operand:DI 2 "mode_width_operand" "n") 1399 1.1 mrg (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI") 1400 1.1 mrg (const_int 3))))] 1401 1.1.1.2 mrg "" 1402 1.1 mrg "ext%M2l %r1,%3,%0" 1403 1.1 mrg [(set_attr "type" "shift")]) 1404 1.1 mrg 1405 1.1 mrg ;; Combine has some strange notion of preserving existing undefined behavior 1406 1.1 mrg ;; in shifts larger than a word size. So capture these patterns that it 1407 1.1.1.2 mrg ;; should have turned into zero_extracts. 1408 1.1 mrg 1409 1.1 mrg (define_insn "*extxl_1" 1410 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1411 1.1.1.2 mrg (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1412 1.1 mrg (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1413 1.1 mrg (const_int 3))) 1414 1.1 mrg (match_operand:DI 3 "mode_mask_operand" "n")))] 1415 1.1 mrg "" 1416 1.1.1.2 mrg "ext%U3l %1,%2,%0" 1417 1.1 mrg [(set_attr "type" "shift")]) 1418 1.1 mrg 1419 1.1 mrg (define_insn "*extql_2" 1420 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1421 1.1 mrg (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1422 1.1 mrg (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1423 1.1 mrg (const_int 3))))] 1424 1.1 mrg "" 1425 1.1 mrg "extql %1,%2,%0" 1426 1.1 mrg [(set_attr "type" "shift")]) 1427 1.1 mrg 1428 1.1 mrg (define_insn "extqh" 1429 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1430 1.1.1.2 mrg (ashift:DI 1431 1.1 mrg (match_operand:DI 1 "reg_or_0_operand" "rJ") 1432 1.1 mrg (minus:DI (const_int 64) 1433 1.1 mrg (ashift:DI 1434 1.1.1.2 mrg (and:DI 1435 1.1 mrg (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1436 1.1 mrg (const_int 7)) 1437 1.1 mrg (const_int 3)))))] 1438 1.1.1.2 mrg "" 1439 1.1 mrg "extqh %r1,%2,%0" 1440 1.1 mrg [(set_attr "type" "shift")]) 1441 1.1 mrg 1442 1.1 mrg (define_insn "extwh" 1443 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1444 1.1 mrg (ashift:DI 1445 1.1.1.2 mrg (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1446 1.1.1.2 mrg (const_int 65535)) 1447 1.1 mrg (minus:DI (const_int 64) 1448 1.1 mrg (ashift:DI 1449 1.1.1.2 mrg (and:DI 1450 1.1 mrg (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1451 1.1 mrg (const_int 7)) 1452 1.1 mrg (const_int 3)))))] 1453 1.1.1.2 mrg "" 1454 1.1 mrg "extwh %r1,%2,%0" 1455 1.1 mrg [(set_attr "type" "shift")]) 1456 1.1 mrg 1457 1.1 mrg (define_insn "extlh" 1458 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1459 1.1 mrg (ashift:DI 1460 1.1.1.2 mrg (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1461 1.1.1.2 mrg (const_int 2147483647)) 1462 1.1 mrg (minus:DI (const_int 64) 1463 1.1 mrg (ashift:DI 1464 1.1 mrg (and:DI 1465 1.1 mrg (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1466 1.1 mrg (const_int 7)) 1467 1.1 mrg (const_int 3)))))] 1468 1.1.1.2 mrg "" 1469 1.1.1.2 mrg "extlh %r1,%2,%0" 1470 1.1.1.2 mrg [(set_attr "type" "shift")]) 1471 1.1.1.2 mrg 1472 1.1 mrg ;; This converts an extXl into an extXh with an appropriate adjustment 1473 1.1.1.2 mrg ;; to the address calculation. 1474 1.1.1.2 mrg 1475 1.1 mrg ;;(define_split 1476 1.1 mrg ;; [(set (match_operand:DI 0 "register_operand") 1477 1.1 mrg ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand") 1478 1.1 mrg ;; (match_operand:DI 2 "mode_width_operand") 1479 1.1 mrg ;; (ashift:DI (match_operand:DI 3) 1480 1.1 mrg ;; (const_int 3))) 1481 1.1 mrg ;; (match_operand:DI 4 "const_int_operand"))) 1482 1.1 mrg ;; (clobber (match_operand:DI 5 "register_operand"))] 1483 1.1 mrg ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])" 1484 1.1 mrg ;; [(set (match_dup 5) (match_dup 6)) 1485 1.1.1.2 mrg ;; (set (match_dup 0) 1486 1.1 mrg ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2) 1487 1.1 mrg ;; (ashift:DI (plus:DI (match_dup 5) 1488 1.1 mrg ;; (match_dup 7)) 1489 1.1 mrg ;; (const_int 3))) 1490 1.1.1.2 mrg ;; (match_dup 4)))] 1491 1.1 mrg ;; " 1492 1.1.1.2 mrg ;;{ 1493 1.1.1.2 mrg ;; operands[6] = plus_constant (DImode, operands[3], 1494 1.1 mrg ;; INTVAL (operands[2]) / BITS_PER_UNIT); 1495 1.1 mrg ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT); 1496 1.1.1.2 mrg ;;}") 1497 1.1 mrg 1498 1.1 mrg (define_insn "ins<modesuffix>l_const" 1499 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1500 1.1 mrg (ashift:DI (zero_extend:DI 1501 1.1.1.2 mrg (match_operand:I124MODE 1 "register_operand" "r")) 1502 1.1.1.2 mrg (match_operand:DI 2 "mul8_operand" "I")))] 1503 1.1 mrg "" 1504 1.1 mrg "ins<modesuffix>l %1,%s2,%0" 1505 1.1.1.2 mrg [(set_attr "type" "shift")]) 1506 1.1.1.2 mrg 1507 1.1 mrg (define_insn "ins<modesuffix>l" 1508 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1509 1.1.1.2 mrg (ashift:DI (zero_extend:DI 1510 1.1 mrg (match_operand:I124MODE 1 "register_operand" "r")) 1511 1.1 mrg (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1512 1.1 mrg (const_int 3))))] 1513 1.1 mrg "" 1514 1.1.1.2 mrg "ins<modesuffix>l %1,%2,%0" 1515 1.1 mrg [(set_attr "type" "shift")]) 1516 1.1 mrg 1517 1.1 mrg (define_insn "insql" 1518 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1519 1.1 mrg (ashift:DI (match_operand:DI 1 "register_operand" "r") 1520 1.1 mrg (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1521 1.1 mrg (const_int 3))))] 1522 1.1 mrg "" 1523 1.1 mrg "insql %1,%2,%0" 1524 1.1 mrg [(set_attr "type" "shift")]) 1525 1.1.1.4 mrg 1526 1.1.1.4 mrg ;; Combine has this sometimes habit of moving the and outside of the 1527 1.1.1.4 mrg ;; shift, making life more interesting. 1528 1.1.1.4 mrg 1529 1.1 mrg (define_insn "*insxl" 1530 1.1.1.4 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1531 1.1.1.4 mrg (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") 1532 1.1 mrg (match_operand:DI 2 "mul8_operand" "I")) 1533 1.1 mrg (match_operand:DI 3 "const_int_operand" "i")))] 1534 1.1 mrg "((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2]) 1535 1.1 mrg == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1536 1.1 mrg || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2]) 1537 1.1 mrg == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1538 1.1 mrg || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2]) 1539 1.1 mrg == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))" 1540 1.1 mrg { 1541 1.1 mrg if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2]) 1542 1.1.1.4 mrg == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1543 1.1 mrg return "insbl %1,%s2,%0"; 1544 1.1 mrg if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2]) 1545 1.1 mrg == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1546 1.1 mrg return "inswl %1,%s2,%0"; 1547 1.1 mrg if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2]) 1548 1.1 mrg == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1549 1.1 mrg return "insll %1,%s2,%0"; 1550 1.1 mrg 1551 1.1 mrg gcc_unreachable (); 1552 1.1 mrg } 1553 1.1 mrg [(set_attr "type" "shift")]) 1554 1.1 mrg 1555 1.1 mrg ;; We do not include the insXh insns because they are complex to express 1556 1.1 mrg ;; and it does not appear that we would ever want to generate them. 1557 1.1 mrg ;; 1558 1.1 mrg ;; Since we need them for block moves, though, cop out and use unspec. 1559 1.1 mrg 1560 1.1 mrg (define_insn "insxh" 1561 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1562 1.1.1.2 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "r") 1563 1.1 mrg (match_operand:DI 2 "mode_width_operand" "n") 1564 1.1 mrg (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 1565 1.1 mrg UNSPEC_INSXH))] 1566 1.1 mrg "" 1567 1.1 mrg "ins%M2h %1,%3,%0" 1568 1.1 mrg [(set_attr "type" "shift")]) 1569 1.1 mrg 1570 1.1.1.2 mrg (define_insn "mskxl" 1571 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1572 1.1 mrg (and:DI (not:DI (ashift:DI 1573 1.1 mrg (match_operand:DI 2 "mode_mask_operand" "n") 1574 1.1 mrg (ashift:DI 1575 1.1 mrg (match_operand:DI 3 "reg_or_8bit_operand" "rI") 1576 1.1 mrg (const_int 3)))) 1577 1.1 mrg (match_operand:DI 1 "reg_or_0_operand" "rJ")))] 1578 1.1 mrg "" 1579 1.1 mrg "msk%U2l %r1,%3,%0" 1580 1.1 mrg [(set_attr "type" "shift")]) 1581 1.1 mrg 1582 1.1 mrg ;; We do not include the mskXh insns because it does not appear we would 1583 1.1 mrg ;; ever generate one. 1584 1.1 mrg ;; 1585 1.1 mrg ;; Again, we do for block moves and we use unspec again. 1586 1.1 mrg 1587 1.1 mrg (define_insn "mskxh" 1588 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1589 1.1 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "r") 1590 1.1 mrg (match_operand:DI 2 "mode_width_operand" "n") 1591 1.1 mrg (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 1592 1.1 mrg UNSPEC_MSKXH))] 1593 1.1 mrg "" 1594 1.1 mrg "msk%M2h %1,%3,%0" 1595 1.1 mrg [(set_attr "type" "shift")]) 1596 1.1 mrg 1597 1.1 mrg ;; Prefer AND + NE over LSHIFTRT + AND. 1598 1.1 mrg 1599 1.1 mrg (define_insn_and_split "*ze_and_ne" 1600 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 1601 1.1 mrg (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1602 1.1 mrg (const_int 1) 1603 1.1 mrg (match_operand 2 "const_int_operand" "I")))] 1604 1.1 mrg "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8" 1605 1.1 mrg "#" 1606 1.1 mrg "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8" 1607 1.1 mrg [(set (match_dup 0) 1608 1.1 mrg (and:DI (match_dup 1) (match_dup 3))) 1609 1.1.1.2 mrg (set (match_dup 0) 1610 1.1 mrg (ne:DI (match_dup 0) (const_int 0)))] 1611 1.1.1.2 mrg "operands[3] = GEN_INT (1 << INTVAL (operands[2]));") 1612 1.1 mrg 1614 1.1.1.2 mrg ;; Floating-point operations. All the double-precision insns can extend 1615 1.1.1.2 mrg ;; from single, so indicate that. The exception are the ones that simply 1616 1.1 mrg ;; play with the sign bits; it's not clear what to do there. 1617 1.1 mrg 1618 1.1 mrg (define_mode_iterator FMODE [SF DF]) 1619 1.1 mrg 1620 1.1.1.2 mrg (define_mode_attr opmode [(SF "si") (DF "di")]) 1621 1.1.1.2 mrg 1622 1.1.1.2 mrg (define_insn "abs<mode>2" 1623 1.1.1.2 mrg [(set (match_operand:FMODE 0 "register_operand" "=f") 1624 1.1 mrg (abs:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))] 1625 1.1 mrg "TARGET_FP" 1626 1.1 mrg "cpys $f31,%R1,%0" 1627 1.1 mrg [(set_attr "type" "fcpys")]) 1628 1.1 mrg 1629 1.1.1.2 mrg (define_insn "*nabs<mode>2" 1630 1.1.1.2 mrg [(set (match_operand:FMODE 0 "register_operand" "=f") 1631 1.1 mrg (neg:FMODE 1632 1.1 mrg (abs:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG"))))] 1633 1.1.1.4 mrg "TARGET_FP" 1634 1.1 mrg "cpysn $f31,%R1,%0" 1635 1.1 mrg [(set_attr "type" "fadd")]) 1636 1.1 mrg 1637 1.1 mrg (define_expand "abstf2" 1638 1.1 mrg [(parallel [(set (match_operand:TF 0 "register_operand") 1639 1.1 mrg (abs:TF (match_operand:TF 1 "reg_or_0_operand"))) 1640 1.1 mrg (use (match_dup 2))])] 1641 1.1 mrg "TARGET_HAS_XFLOATING_LIBS" 1642 1.1 mrg "operands[2] = force_reg (DImode, GEN_INT (HOST_WIDE_INT_1U << 63));") 1643 1.1 mrg 1644 1.1 mrg (define_insn_and_split "*abstf_internal" 1645 1.1.1.2 mrg [(set (match_operand:TF 0 "register_operand" "=r") 1646 1.1.1.2 mrg (abs:TF (match_operand:TF 1 "reg_or_0_operand" "rG"))) 1647 1.1.1.2 mrg (use (match_operand:DI 2 "register_operand" "r"))] 1648 1.1 mrg "TARGET_HAS_XFLOATING_LIBS" 1649 1.1 mrg "#" 1650 1.1 mrg "&& reload_completed" 1651 1.1 mrg [(const_int 0)] 1652 1.1 mrg "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;") 1653 1.1.1.2 mrg 1654 1.1.1.2 mrg (define_insn "neg<mode>2" 1655 1.1 mrg [(set (match_operand:FMODE 0 "register_operand" "=f") 1656 1.1 mrg (neg:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))] 1657 1.1.1.4 mrg "TARGET_FP" 1658 1.1 mrg "cpysn %R1,%R1,%0" 1659 1.1 mrg [(set_attr "type" "fadd")]) 1660 1.1 mrg 1661 1.1 mrg (define_expand "negtf2" 1662 1.1 mrg [(parallel [(set (match_operand:TF 0 "register_operand") 1663 1.1 mrg (neg:TF (match_operand:TF 1 "reg_or_0_operand"))) 1664 1.1 mrg (use (match_dup 2))])] 1665 1.1 mrg "TARGET_HAS_XFLOATING_LIBS" 1666 1.1 mrg "operands[2] = force_reg (DImode, GEN_INT (HOST_WIDE_INT_1U << 63));") 1667 1.1 mrg 1668 1.1 mrg (define_insn_and_split "*negtf_internal" 1669 1.1.1.2 mrg [(set (match_operand:TF 0 "register_operand" "=r") 1670 1.1.1.2 mrg (neg:TF (match_operand:TF 1 "reg_or_0_operand" "rG"))) 1671 1.1.1.2 mrg (use (match_operand:DI 2 "register_operand" "r"))] 1672 1.1.1.2 mrg "TARGET_HAS_XFLOATING_LIBS" 1673 1.1.1.2 mrg "#" 1674 1.1 mrg "&& reload_completed" 1675 1.1 mrg [(const_int 0)] 1676 1.1 mrg "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;") 1677 1.1 mrg 1678 1.1.1.2 mrg (define_insn "copysign<mode>3" 1679 1.1.1.2 mrg [(set (match_operand:FMODE 0 "register_operand" "=f") 1680 1.1.1.2 mrg (unspec:FMODE [(match_operand:FMODE 1 "reg_or_0_operand" "fG") 1681 1.1.1.2 mrg (match_operand:FMODE 2 "reg_or_0_operand" "fG")] 1682 1.1.1.2 mrg UNSPEC_COPYSIGN))] 1683 1.1.1.2 mrg "TARGET_FP" 1684 1.1 mrg "cpys %R2,%R1,%0" 1685 1.1 mrg [(set_attr "type" "fadd")]) 1686 1.1 mrg 1687 1.1 mrg (define_insn "*ncopysign<mode>3" 1688 1.1.1.2 mrg [(set (match_operand:FMODE 0 "register_operand" "=f") 1689 1.1.1.7 mrg (neg:FMODE 1690 1.1.1.7 mrg (unspec:FMODE [(match_operand:FMODE 1 "reg_or_0_operand" "fG") 1691 1.1.1.7 mrg (match_operand:FMODE 2 "reg_or_0_operand" "fG")] 1692 1.1 mrg UNSPEC_COPYSIGN)))] 1693 1.1.1.2 mrg "TARGET_FP" 1694 1.1 mrg "cpysn %R2,%R1,%0" 1695 1.1 mrg [(set_attr "type" "fadd")]) 1696 1.1 mrg 1697 1.1.1.7 mrg (define_insn "add<mode>3" 1698 1.1.1.7 mrg [(set (match_operand:FMODE 0 "register_operand" "=f,&f") 1699 1.1.1.7 mrg (plus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG,fG") 1700 1.1.1.7 mrg (match_operand:FMODE 2 "reg_or_0_operand" "fG,fG")))] 1701 1.1.1.7 mrg "TARGET_FP" 1702 1.1.1.7 mrg "add<modesuffix>%/ %R1,%R2,%0" 1703 1.1 mrg [(set_attr "type" "fadd") 1704 1.1 mrg (set_attr "trap" "yes") 1705 1.1 mrg (set_attr "round_suffix" "normal") 1706 1.1 mrg (set_attr "trap_suffix" "u_su_sui") 1707 1.1 mrg (set (attr "enabled") 1708 1.1 mrg (cond [(eq_attr "alternative" "0") 1709 1.1 mrg (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 1710 1.1 mrg ] 1711 1.1 mrg (symbol_ref "true")))]) 1712 1.1 mrg 1713 1.1 mrg (define_insn "*adddf_ext1" 1714 1.1 mrg [(set (match_operand:DF 0 "register_operand" "=f") 1715 1.1 mrg (plus:DF (float_extend:DF 1716 1.1 mrg (match_operand:SF 1 "reg_or_0_operand" "fG")) 1717 1.1 mrg (match_operand:DF 2 "reg_or_0_operand" "fG")))] 1718 1.1 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1719 1.1 mrg "add%-%/ %R1,%R2,%0" 1720 1.1 mrg [(set_attr "type" "fadd") 1721 1.1 mrg (set_attr "trap" "yes") 1722 1.1 mrg (set_attr "round_suffix" "normal") 1723 1.1 mrg (set_attr "trap_suffix" "u_su_sui")]) 1724 1.1 mrg 1725 1.1 mrg (define_insn "*adddf_ext2" 1726 1.1 mrg [(set (match_operand:DF 0 "register_operand" "=f") 1727 1.1 mrg (plus:DF (float_extend:DF 1728 1.1 mrg (match_operand:SF 1 "reg_or_0_operand" "%fG")) 1729 1.1 mrg (float_extend:DF 1730 1.1.1.2 mrg (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1731 1.1.1.2 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1732 1.1.1.2 mrg "add%-%/ %R1,%R2,%0" 1733 1.1 mrg [(set_attr "type" "fadd") 1734 1.1 mrg (set_attr "trap" "yes") 1735 1.1 mrg (set_attr "round_suffix" "normal") 1736 1.1.1.2 mrg (set_attr "trap_suffix" "u_su_sui")]) 1737 1.1.1.7 mrg 1738 1.1.1.7 mrg (define_expand "addtf3" 1739 1.1.1.7 mrg [(use (match_operand:TF 0 "register_operand")) 1740 1.1.1.2 mrg (use (match_operand:TF 1 "general_operand")) 1741 1.1.1.2 mrg (use (match_operand:TF 2 "general_operand"))] 1742 1.1.1.2 mrg "TARGET_HAS_XFLOATING_LIBS" 1743 1.1.1.2 mrg "alpha_emit_xfloating_arith (PLUS, operands); DONE;") 1744 1.1.1.2 mrg 1745 1.1.1.7 mrg (define_insn "sub<mode>3" 1746 1.1.1.7 mrg [(set (match_operand:FMODE 0 "register_operand" "=f,&f") 1747 1.1.1.7 mrg (minus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG,fG") 1748 1.1.1.7 mrg (match_operand:FMODE 2 "reg_or_0_operand" "fG,fG")))] 1749 1.1.1.7 mrg "TARGET_FP" 1750 1.1.1.7 mrg "sub<modesuffix>%/ %R1,%R2,%0" 1751 1.1.1.2 mrg [(set_attr "type" "fadd") 1752 1.1.1.2 mrg (set_attr "trap" "yes") 1753 1.1.1.2 mrg (set_attr "round_suffix" "normal") 1754 1.1.1.2 mrg (set_attr "trap_suffix" "u_su_sui") 1755 1.1.1.2 mrg (set (attr "enabled") 1756 1.1.1.2 mrg (cond [(eq_attr "alternative" "0") 1757 1.1.1.2 mrg (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 1758 1.1.1.2 mrg ] 1759 1.1.1.2 mrg (symbol_ref "true")))]) 1760 1.1.1.2 mrg 1761 1.1.1.2 mrg (define_insn "*subdf_ext1" 1762 1.1.1.2 mrg [(set (match_operand:DF 0 "register_operand" "=f") 1763 1.1.1.2 mrg (minus:DF (float_extend:DF 1764 1.1.1.2 mrg (match_operand:SF 1 "reg_or_0_operand" "fG")) 1765 1.1.1.2 mrg (match_operand:DF 2 "reg_or_0_operand" "fG")))] 1766 1.1.1.2 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1767 1.1.1.2 mrg "sub%-%/ %R1,%R2,%0" 1768 1.1.1.2 mrg [(set_attr "type" "fadd") 1769 1.1.1.2 mrg (set_attr "trap" "yes") 1770 1.1.1.2 mrg (set_attr "round_suffix" "normal") 1771 1.1.1.2 mrg (set_attr "trap_suffix" "u_su_sui")]) 1772 1.1.1.2 mrg 1773 1.1.1.2 mrg (define_insn "*subdf_ext2" 1774 1.1.1.2 mrg [(set (match_operand:DF 0 "register_operand" "=f") 1775 1.1.1.2 mrg (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG") 1776 1.1.1.2 mrg (float_extend:DF 1777 1.1.1.2 mrg (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1778 1.1.1.2 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1779 1.1.1.2 mrg "sub%-%/ %R1,%R2,%0" 1780 1.1.1.2 mrg [(set_attr "type" "fadd") 1781 1.1.1.2 mrg (set_attr "trap" "yes") 1782 1.1.1.2 mrg (set_attr "round_suffix" "normal") 1783 1.1.1.2 mrg (set_attr "trap_suffix" "u_su_sui")]) 1784 1.1.1.2 mrg 1785 1.1.1.2 mrg (define_insn "*subdf_ext3" 1786 1.1.1.2 mrg [(set (match_operand:DF 0 "register_operand" "=f") 1787 1.1.1.2 mrg (minus:DF (float_extend:DF 1788 1.1.1.2 mrg (match_operand:SF 1 "reg_or_0_operand" "fG")) 1789 1.1.1.2 mrg (float_extend:DF 1790 1.1.1.2 mrg (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1791 1.1.1.2 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1792 1.1.1.2 mrg "sub%-%/ %R1,%R2,%0" 1793 1.1.1.2 mrg [(set_attr "type" "fadd") 1794 1.1.1.2 mrg (set_attr "trap" "yes") 1795 1.1.1.2 mrg (set_attr "round_suffix" "normal") 1796 1.1.1.2 mrg (set_attr "trap_suffix" "u_su_sui")]) 1797 1.1.1.7 mrg 1798 1.1.1.7 mrg (define_expand "subtf3" 1799 1.1.1.7 mrg [(use (match_operand:TF 0 "register_operand")) 1800 1.1.1.2 mrg (use (match_operand:TF 1 "general_operand")) 1801 1.1.1.2 mrg (use (match_operand:TF 2 "general_operand"))] 1802 1.1.1.2 mrg "TARGET_HAS_XFLOATING_LIBS" 1803 1.1.1.2 mrg "alpha_emit_xfloating_arith (MINUS, operands); DONE;") 1804 1.1.1.2 mrg 1805 1.1.1.7 mrg (define_insn "mul<mode>3" 1806 1.1.1.7 mrg [(set (match_operand:FMODE 0 "register_operand" "=f,&f") 1807 1.1.1.7 mrg (mult:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG,fG") 1808 1.1.1.7 mrg (match_operand:FMODE 2 "reg_or_0_operand" "fG,fG")))] 1809 1.1.1.7 mrg "TARGET_FP" 1810 1.1.1.7 mrg "mul<modesuffix>%/ %R1,%R2,%0" 1811 1.1.1.2 mrg [(set_attr "type" "fmul") 1812 1.1.1.2 mrg (set_attr "trap" "yes") 1813 1.1.1.2 mrg (set_attr "round_suffix" "normal") 1814 1.1.1.2 mrg (set_attr "trap_suffix" "u_su_sui") 1815 1.1.1.2 mrg (set (attr "enabled") 1816 1.1.1.2 mrg (cond [(eq_attr "alternative" "0") 1817 1.1.1.2 mrg (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 1818 1.1.1.2 mrg ] 1819 1.1.1.2 mrg (symbol_ref "true")))]) 1820 1.1.1.2 mrg 1821 1.1.1.2 mrg (define_insn "*muldf_ext1" 1822 1.1.1.2 mrg [(set (match_operand:DF 0 "register_operand" "=f") 1823 1.1.1.2 mrg (mult:DF (float_extend:DF 1824 1.1.1.2 mrg (match_operand:SF 1 "reg_or_0_operand" "fG")) 1825 1.1.1.2 mrg (match_operand:DF 2 "reg_or_0_operand" "fG")))] 1826 1.1.1.2 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1827 1.1.1.2 mrg "mul%-%/ %R1,%R2,%0" 1828 1.1.1.2 mrg [(set_attr "type" "fmul") 1829 1.1.1.2 mrg (set_attr "trap" "yes") 1830 1.1.1.2 mrg (set_attr "round_suffix" "normal") 1831 1.1.1.2 mrg (set_attr "trap_suffix" "u_su_sui")]) 1832 1.1.1.2 mrg 1833 1.1.1.2 mrg (define_insn "*muldf_ext2" 1834 1.1.1.2 mrg [(set (match_operand:DF 0 "register_operand" "=f") 1835 1.1.1.2 mrg (mult:DF (float_extend:DF 1836 1.1.1.2 mrg (match_operand:SF 1 "reg_or_0_operand" "%fG")) 1837 1.1.1.2 mrg (float_extend:DF 1838 1.1.1.2 mrg (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1839 1.1.1.2 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1840 1.1.1.2 mrg "mul%-%/ %R1,%R2,%0" 1841 1.1.1.2 mrg [(set_attr "type" "fmul") 1842 1.1.1.2 mrg (set_attr "trap" "yes") 1843 1.1.1.2 mrg (set_attr "round_suffix" "normal") 1844 1.1.1.2 mrg (set_attr "trap_suffix" "u_su_sui")]) 1845 1.1.1.7 mrg 1846 1.1.1.7 mrg (define_expand "multf3" 1847 1.1.1.7 mrg [(use (match_operand:TF 0 "register_operand")) 1848 1.1.1.2 mrg (use (match_operand:TF 1 "general_operand")) 1849 1.1.1.2 mrg (use (match_operand:TF 2 "general_operand"))] 1850 1.1.1.2 mrg "TARGET_HAS_XFLOATING_LIBS" 1851 1.1.1.2 mrg "alpha_emit_xfloating_arith (MULT, operands); DONE;") 1852 1.1.1.2 mrg 1853 1.1.1.2 mrg (define_insn "div<mode>3" 1854 1.1.1.7 mrg [(set (match_operand:FMODE 0 "register_operand" "=f,&f") 1855 1.1.1.7 mrg (div:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG,fG") 1856 1.1.1.7 mrg (match_operand:FMODE 2 "reg_or_0_operand" "fG,fG")))] 1857 1.1.1.7 mrg "TARGET_FP" 1858 1.1.1.7 mrg "div<modesuffix>%/ %R1,%R2,%0" 1859 1.1.1.7 mrg [(set_attr "type" "fdiv") 1860 1.1.1.2 mrg (set_attr "opsize" "<opmode>") 1861 1.1.1.2 mrg (set_attr "trap" "yes") 1862 1.1.1.2 mrg (set_attr "round_suffix" "normal") 1863 1.1.1.2 mrg (set_attr "trap_suffix" "u_su_sui") 1864 1.1.1.2 mrg (set (attr "enabled") 1865 1.1.1.2 mrg (cond [(eq_attr "alternative" "0") 1866 1.1.1.2 mrg (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 1867 1.1.1.2 mrg ] 1868 1.1.1.2 mrg (symbol_ref "true")))]) 1869 1.1.1.2 mrg 1870 1.1.1.2 mrg (define_insn "*divdf_ext1" 1871 1.1.1.2 mrg [(set (match_operand:DF 0 "register_operand" "=f") 1872 1.1.1.2 mrg (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG")) 1873 1.1.1.2 mrg (match_operand:DF 2 "reg_or_0_operand" "fG")))] 1874 1.1.1.2 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1875 1.1.1.2 mrg "div%-%/ %R1,%R2,%0" 1876 1.1.1.2 mrg [(set_attr "type" "fdiv") 1877 1.1.1.2 mrg (set_attr "trap" "yes") 1878 1.1.1.2 mrg (set_attr "round_suffix" "normal") 1879 1.1.1.2 mrg (set_attr "trap_suffix" "u_su_sui")]) 1880 1.1.1.2 mrg 1881 1.1.1.2 mrg (define_insn "*divdf_ext2" 1882 1.1.1.2 mrg [(set (match_operand:DF 0 "register_operand" "=f") 1883 1.1.1.2 mrg (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG") 1884 1.1.1.2 mrg (float_extend:DF 1885 1.1.1.2 mrg (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1886 1.1.1.2 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1887 1.1.1.2 mrg "div%-%/ %R1,%R2,%0" 1888 1.1.1.2 mrg [(set_attr "type" "fdiv") 1889 1.1.1.2 mrg (set_attr "trap" "yes") 1890 1.1.1.2 mrg (set_attr "round_suffix" "normal") 1891 1.1.1.2 mrg (set_attr "trap_suffix" "u_su_sui")]) 1892 1.1.1.2 mrg 1893 1.1.1.2 mrg (define_insn "*divdf_ext3" 1894 1.1.1.2 mrg [(set (match_operand:DF 0 "register_operand" "=f") 1895 1.1.1.2 mrg (div:DF (float_extend:DF 1896 1.1.1.2 mrg (match_operand:SF 1 "reg_or_0_operand" "fG")) 1897 1.1.1.2 mrg (float_extend:DF 1898 1.1.1.2 mrg (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1899 1.1.1.2 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1900 1.1.1.2 mrg "div%-%/ %R1,%R2,%0" 1901 1.1.1.2 mrg [(set_attr "type" "fdiv") 1902 1.1.1.2 mrg (set_attr "trap" "yes") 1903 1.1.1.2 mrg (set_attr "round_suffix" "normal") 1904 1.1.1.2 mrg (set_attr "trap_suffix" "u_su_sui")]) 1905 1.1.1.7 mrg 1906 1.1.1.7 mrg (define_expand "divtf3" 1907 1.1.1.2 mrg [(use (match_operand:TF 0 "register_operand")) 1908 1.1.1.2 mrg (use (match_operand:TF 1 "general_operand")) 1909 1.1.1.2 mrg (use (match_operand:TF 2 "general_operand"))] 1910 1.1.1.2 mrg "TARGET_HAS_XFLOATING_LIBS" 1911 1.1.1.2 mrg "alpha_emit_xfloating_arith (DIV, operands); DONE;") 1912 1.1.1.2 mrg 1913 1.1.1.7 mrg (define_insn "sqrt<mode>2" 1914 1.1.1.7 mrg [(set (match_operand:FMODE 0 "register_operand" "=f,&f") 1915 1.1.1.7 mrg (sqrt:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG,fG")))] 1916 1.1.1.7 mrg "TARGET_FP && TARGET_FIX" 1917 1.1.1.7 mrg "sqrt<modesuffix>%/ %R1,%0" 1918 1.1.1.7 mrg [(set_attr "type" "fsqrt") 1919 1.1.1.2 mrg (set_attr "opsize" "<opmode>") 1920 1.1.1.2 mrg (set_attr "trap" "yes") 1921 1.1.1.2 mrg (set_attr "round_suffix" "normal") 1922 1.1.1.2 mrg (set_attr "trap_suffix" "u_su_sui") 1923 1.1.1.2 mrg (set (attr "enabled") 1924 1.1.1.2 mrg (cond [(eq_attr "alternative" "0") 1925 1.1.1.2 mrg (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 1926 1.1.1.2 mrg ] 1927 1.1.1.2 mrg (symbol_ref "true")))]) 1928 1.1 mrg 1929 1.1 mrg ;; Define conversion operators between DFmode and SImode, using the cvtql 1930 1.1 mrg ;; instruction. To allow combine et al to do useful things, we keep the 1931 1.1 mrg ;; operation as a unit until after reload, at which point we split the 1932 1.1 mrg ;; instructions. 1933 1.1 mrg ;; 1934 1.1 mrg ;; Note that we (attempt to) only consider this optimization when the 1935 1.1 mrg ;; ultimate destination is memory. If we will be doing further integer 1936 1.1 mrg ;; processing, it is cheaper to do the truncation in the int regs. 1937 1.1 mrg 1938 1.1 mrg (define_insn "*cvtql" 1939 1.1 mrg [(set (match_operand:SF 0 "register_operand" "=f") 1940 1.1 mrg (unspec:SF [(match_operand:DI 1 "reg_or_0_operand" "fG")] 1941 1.1 mrg UNSPEC_CVTQL))] 1942 1.1 mrg "TARGET_FP" 1943 1.1 mrg "cvtql%/ %R1,%0" 1944 1.1 mrg [(set_attr "type" "fadd") 1945 1.1 mrg (set_attr "trap" "yes") 1946 1.1 mrg (set_attr "trap_suffix" "v_sv")]) 1947 1.1 mrg 1948 1.1 mrg (define_insn_and_split "*fix_truncdfsi_ieee" 1949 1.1 mrg [(set (match_operand:SI 0 "memory_operand" "=m") 1950 1.1 mrg (subreg:SI 1951 1.1 mrg (match_operator:DI 4 "fix_operator" 1952 1.1 mrg [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0)) 1953 1.1 mrg (clobber (match_scratch:DI 2 "=&f")) 1954 1.1 mrg (clobber (match_scratch:SF 3 "=&f"))] 1955 1.1 mrg "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 1956 1.1 mrg "#" 1957 1.1 mrg "&& reload_completed" 1958 1.1 mrg [(set (match_dup 2) (match_op_dup 4 [(match_dup 1)])) 1959 1.1 mrg (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) 1960 1.1 mrg (set (match_dup 5) (match_dup 3))] 1961 1.1 mrg { 1962 1.1 mrg operands[5] = adjust_address (operands[0], SFmode, 0); 1963 1.1 mrg } 1964 1.1 mrg [(set_attr "type" "fadd") 1965 1.1 mrg (set_attr "trap" "yes")]) 1966 1.1 mrg 1967 1.1 mrg (define_insn_and_split "*fix_truncdfsi_internal" 1968 1.1 mrg [(set (match_operand:SI 0 "memory_operand" "=m") 1969 1.1 mrg (subreg:SI 1970 1.1 mrg (match_operator:DI 3 "fix_operator" 1971 1.1 mrg [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0)) 1972 1.1 mrg (clobber (match_scratch:DI 2 "=f"))] 1973 1.1 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1974 1.1 mrg "#" 1975 1.1 mrg "&& reload_completed" 1976 1.1 mrg [(set (match_dup 2) (match_op_dup 3 [(match_dup 1)])) 1977 1.1 mrg (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) 1978 1.1.1.7 mrg (set (match_dup 5) (match_dup 4))] 1979 1.1 mrg { 1980 1.1.1.7 mrg operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2])); 1981 1.1 mrg operands[5] = adjust_address (operands[0], SFmode, 0); 1982 1.1 mrg } 1983 1.1 mrg [(set_attr "type" "fadd") 1984 1.1 mrg (set_attr "trap" "yes")]) 1985 1.1 mrg 1986 1.1.1.7 mrg (define_insn "*fix_truncdfdi2" 1987 1.1.1.7 mrg [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f,&f") 1988 1.1.1.7 mrg (match_operator:DI 2 "fix_operator" 1989 1.1.1.7 mrg [(match_operand:DF 1 "reg_or_0_operand" "fG,fG")]))] 1990 1.1.1.7 mrg "TARGET_FP" 1991 1.1.1.7 mrg "cvt%-q%/ %R1,%0" 1992 1.1 mrg [(set_attr "type" "fadd") 1993 1.1 mrg (set_attr "trap" "yes") 1994 1.1.1.2 mrg (set_attr "round_suffix" "c") 1995 1.1.1.2 mrg (set_attr "trap_suffix" "v_sv_svi") 1996 1.1.1.2 mrg (set (attr "enabled") 1997 1.1 mrg (cond [(eq_attr "alternative" "0") 1998 1.1 mrg (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 1999 1.1.1.2 mrg ] 2000 1.1.1.2 mrg (symbol_ref "true")))]) 2001 1.1.1.2 mrg 2002 1.1 mrg (define_expand "fix_truncdfdi2" 2003 1.1 mrg [(set (match_operand:DI 0 "reg_no_subreg_operand") 2004 1.1 mrg (fix:DI (match_operand:DF 1 "reg_or_0_operand")))] 2005 1.1 mrg "TARGET_FP") 2006 1.1 mrg 2007 1.1 mrg (define_expand "fixuns_truncdfdi2" 2008 1.1 mrg [(set (match_operand:DI 0 "reg_no_subreg_operand") 2009 1.1 mrg (unsigned_fix:DI (match_operand:DF 1 "reg_or_0_operand")))] 2010 1.1 mrg "TARGET_FP") 2011 1.1 mrg 2012 1.1 mrg ;; Likewise between SFmode and SImode. 2013 1.1 mrg 2014 1.1 mrg (define_insn_and_split "*fix_truncsfsi_ieee" 2015 1.1 mrg [(set (match_operand:SI 0 "memory_operand" "=m") 2016 1.1 mrg (subreg:SI 2017 1.1 mrg (match_operator:DI 4 "fix_operator" 2018 1.1 mrg [(float_extend:DF 2019 1.1.1.2 mrg (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0)) 2020 1.1 mrg (clobber (match_scratch:DI 2 "=&f")) 2021 1.1 mrg (clobber (match_scratch:SF 3 "=&f"))] 2022 1.1 mrg "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2023 1.1 mrg "#" 2024 1.1 mrg "&& reload_completed" 2025 1.1 mrg [(set (match_dup 2) (match_op_dup 4 [(float_extend:DF (match_dup 1))])) 2026 1.1 mrg (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) 2027 1.1 mrg (set (match_dup 5) (match_dup 3))] 2028 1.1 mrg "operands[5] = adjust_address (operands[0], SFmode, 0);" 2029 1.1 mrg [(set_attr "type" "fadd") 2030 1.1 mrg (set_attr "trap" "yes")]) 2031 1.1 mrg 2032 1.1 mrg (define_insn_and_split "*fix_truncsfsi_internal" 2033 1.1 mrg [(set (match_operand:SI 0 "memory_operand" "=m") 2034 1.1 mrg (subreg:SI 2035 1.1 mrg (match_operator:DI 3 "fix_operator" 2036 1.1 mrg [(float_extend:DF 2037 1.1 mrg (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0)) 2038 1.1 mrg (clobber (match_scratch:DI 2 "=f"))] 2039 1.1 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2040 1.1 mrg "#" 2041 1.1 mrg "&& reload_completed" 2042 1.1 mrg [(set (match_dup 2) (match_op_dup 3 [(float_extend:DF (match_dup 1))])) 2043 1.1 mrg (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) 2044 1.1.1.7 mrg (set (match_dup 5) (match_dup 4))] 2045 1.1 mrg { 2046 1.1.1.7 mrg operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2])); 2047 1.1 mrg operands[5] = adjust_address (operands[0], SFmode, 0); 2048 1.1 mrg } 2049 1.1 mrg [(set_attr "type" "fadd") 2050 1.1 mrg (set_attr "trap" "yes")]) 2051 1.1 mrg 2052 1.1.1.7 mrg (define_insn "*fix_truncsfdi2" 2053 1.1.1.7 mrg [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f,&f") 2054 1.1.1.7 mrg (match_operator:DI 2 "fix_operator" 2055 1.1.1.7 mrg [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,fG"))]))] 2056 1.1.1.7 mrg "TARGET_FP" 2057 1.1.1.7 mrg "cvt%-q%/ %R1,%0" 2058 1.1 mrg [(set_attr "type" "fadd") 2059 1.1 mrg (set_attr "trap" "yes") 2060 1.1.1.2 mrg (set_attr "round_suffix" "c") 2061 1.1.1.2 mrg (set_attr "trap_suffix" "v_sv_svi") 2062 1.1.1.2 mrg (set (attr "enabled") 2063 1.1 mrg (cond [(eq_attr "alternative" "0") 2064 1.1 mrg (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 2065 1.1.1.2 mrg ] 2066 1.1 mrg (symbol_ref "true")))]) 2067 1.1.1.2 mrg 2068 1.1.1.2 mrg (define_expand "fix_truncsfdi2" 2069 1.1 mrg [(set (match_operand:DI 0 "reg_no_subreg_operand") 2070 1.1 mrg (fix:DI (float_extend:DF (match_operand:SF 1 "reg_or_0_operand"))))] 2071 1.1.1.2 mrg "TARGET_FP") 2072 1.1.1.2 mrg 2073 1.1 mrg (define_expand "fixuns_truncsfdi2" 2074 1.1 mrg [(set (match_operand:DI 0 "reg_no_subreg_operand") 2075 1.1 mrg (unsigned_fix:DI 2076 1.1 mrg (float_extend:DF (match_operand:SF 1 "reg_or_0_operand"))))] 2077 1.1.1.2 mrg "TARGET_FP") 2078 1.1.1.2 mrg 2079 1.1 mrg (define_expand "fix_trunctfdi2" 2080 1.1 mrg [(use (match_operand:DI 0 "register_operand")) 2081 1.1 mrg (use (match_operand:TF 1 "general_operand"))] 2082 1.1 mrg "TARGET_HAS_XFLOATING_LIBS" 2083 1.1.1.7 mrg "alpha_emit_xfloating_cvt (FIX, operands); DONE;") 2084 1.1.1.7 mrg 2085 1.1 mrg (define_expand "fixuns_trunctfdi2" 2086 1.1 mrg [(use (match_operand:DI 0 "register_operand")) 2087 1.1 mrg (use (match_operand:TF 1 "general_operand"))] 2088 1.1 mrg "TARGET_HAS_XFLOATING_LIBS" 2089 1.1 mrg "alpha_emit_xfloating_cvt (UNSIGNED_FIX, operands); DONE;") 2090 1.1.1.7 mrg 2091 1.1.1.7 mrg (define_insn "floatdisf2" 2092 1.1.1.7 mrg [(set (match_operand:SF 0 "register_operand" "=f,&f") 2093 1.1.1.7 mrg (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f,f")))] 2094 1.1.1.7 mrg "TARGET_FP" 2095 1.1.1.7 mrg "cvtq%,%/ %1,%0" 2096 1.1 mrg [(set_attr "type" "fadd") 2097 1.1 mrg (set_attr "trap" "yes") 2098 1.1 mrg (set_attr "round_suffix" "normal") 2099 1.1 mrg (set_attr "trap_suffix" "sui") 2100 1.1 mrg (set (attr "enabled") 2101 1.1 mrg (cond [(eq_attr "alternative" "0") 2102 1.1 mrg (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 2103 1.1 mrg ] 2104 1.1 mrg (symbol_ref "true")))]) 2105 1.1 mrg 2106 1.1 mrg (define_insn_and_split "*floatsisf2_ieee" 2107 1.1 mrg [(set (match_operand:SF 0 "register_operand" "=&f") 2108 1.1.1.2 mrg (float:SF (match_operand:SI 1 "memory_operand" "m"))) 2109 1.1 mrg (clobber (match_scratch:DI 2 "=&f")) 2110 1.1 mrg (clobber (match_scratch:SF 3 "=&f"))] 2111 1.1 mrg "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2112 1.1 mrg "#" 2113 1.1 mrg "&& reload_completed" 2114 1.1 mrg [(set (match_dup 3) (match_dup 1)) 2115 1.1 mrg (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ)) 2116 1.1 mrg (set (match_dup 0) (float:SF (match_dup 2)))] 2117 1.1 mrg "operands[1] = adjust_address (operands[1], SFmode, 0);") 2118 1.1 mrg 2119 1.1 mrg (define_insn_and_split "*floatsisf2" 2120 1.1 mrg [(set (match_operand:SF 0 "register_operand" "=f") 2121 1.1 mrg (float:SF (match_operand:SI 1 "memory_operand" "m")))] 2122 1.1 mrg "TARGET_FP" 2123 1.1 mrg "#" 2124 1.1 mrg "&& reload_completed" 2125 1.1.1.7 mrg [(set (match_dup 0) (match_dup 1)) 2126 1.1.1.7 mrg (set (match_dup 2) (unspec:DI [(match_dup 0)] UNSPEC_CVTLQ)) 2127 1.1 mrg (set (match_dup 0) (float:SF (match_dup 2)))] 2128 1.1 mrg { 2129 1.1 mrg operands[1] = adjust_address (operands[1], SFmode, 0); 2130 1.1 mrg operands[2] = gen_rtx_REG (DImode, REGNO (operands[0])); 2131 1.1 mrg }) 2132 1.1.1.7 mrg 2133 1.1.1.7 mrg (define_insn "floatdidf2" 2134 1.1.1.7 mrg [(set (match_operand:DF 0 "register_operand" "=f,&f") 2135 1.1.1.7 mrg (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f,f")))] 2136 1.1.1.7 mrg "TARGET_FP" 2137 1.1.1.7 mrg "cvtq%-%/ %1,%0" 2138 1.1 mrg [(set_attr "type" "fadd") 2139 1.1 mrg (set_attr "trap" "yes") 2140 1.1 mrg (set_attr "round_suffix" "normal") 2141 1.1 mrg (set_attr "trap_suffix" "sui") 2142 1.1 mrg (set (attr "enabled") 2143 1.1 mrg (cond [(eq_attr "alternative" "0") 2144 1.1 mrg (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 2145 1.1 mrg ] 2146 1.1 mrg (symbol_ref "true")))]) 2147 1.1 mrg 2148 1.1 mrg (define_insn_and_split "*floatsidf2_ieee" 2149 1.1 mrg [(set (match_operand:DF 0 "register_operand" "=&f") 2150 1.1.1.2 mrg (float:DF (match_operand:SI 1 "memory_operand" "m"))) 2151 1.1 mrg (clobber (match_scratch:DI 2 "=&f")) 2152 1.1 mrg (clobber (match_scratch:SF 3 "=&f"))] 2153 1.1 mrg "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2154 1.1 mrg "#" 2155 1.1 mrg "&& reload_completed" 2156 1.1 mrg [(set (match_dup 3) (match_dup 1)) 2157 1.1 mrg (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ)) 2158 1.1 mrg (set (match_dup 0) (float:DF (match_dup 2)))] 2159 1.1 mrg "operands[1] = adjust_address (operands[1], SFmode, 0);") 2160 1.1 mrg 2161 1.1 mrg (define_insn_and_split "*floatsidf2" 2162 1.1 mrg [(set (match_operand:DF 0 "register_operand" "=f") 2163 1.1 mrg (float:DF (match_operand:SI 1 "memory_operand" "m")))] 2164 1.1 mrg "TARGET_FP" 2165 1.1 mrg "#" 2166 1.1 mrg "&& reload_completed" 2167 1.1 mrg [(set (match_dup 3) (match_dup 1)) 2168 1.1.1.2 mrg (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ)) 2169 1.1.1.2 mrg (set (match_dup 0) (float:DF (match_dup 2)))] 2170 1.1 mrg { 2171 1.1 mrg operands[1] = adjust_address (operands[1], SFmode, 0); 2172 1.1 mrg operands[2] = gen_rtx_REG (DImode, REGNO (operands[0])); 2173 1.1 mrg operands[3] = gen_rtx_REG (SFmode, REGNO (operands[0])); 2174 1.1.1.2 mrg }) 2175 1.1.1.2 mrg 2176 1.1 mrg (define_expand "floatditf2" 2177 1.1 mrg [(use (match_operand:TF 0 "register_operand")) 2178 1.1 mrg (use (match_operand:DI 1 "general_operand"))] 2179 1.1 mrg "TARGET_HAS_XFLOATING_LIBS" 2180 1.1.1.2 mrg "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;") 2181 1.1.1.2 mrg 2182 1.1 mrg (define_expand "floatunsdisf2" 2183 1.1 mrg [(use (match_operand:SF 0 "register_operand")) 2184 1.1 mrg (use (match_operand:DI 1 "register_operand"))] 2185 1.1 mrg "TARGET_FP" 2186 1.1.1.2 mrg "alpha_emit_floatuns (operands); DONE;") 2187 1.1.1.2 mrg 2188 1.1 mrg (define_expand "floatunsdidf2" 2189 1.1 mrg [(use (match_operand:DF 0 "register_operand")) 2190 1.1 mrg (use (match_operand:DI 1 "register_operand"))] 2191 1.1 mrg "TARGET_FP" 2192 1.1.1.2 mrg "alpha_emit_floatuns (operands); DONE;") 2193 1.1.1.2 mrg 2194 1.1 mrg (define_expand "floatunsditf2" 2195 1.1 mrg [(use (match_operand:TF 0 "register_operand")) 2196 1.1 mrg (use (match_operand:DI 1 "general_operand"))] 2197 1.1 mrg "TARGET_HAS_XFLOATING_LIBS" 2198 1.1 mrg "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;") 2199 1.1 mrg 2200 1.1 mrg (define_expand "extendsfdf2" 2201 1.1 mrg [(set (match_operand:DF 0 "register_operand") 2202 1.1 mrg (float_extend:DF (match_operand:SF 1 "nonimmediate_operand")))] 2203 1.1 mrg "TARGET_FP" 2204 1.1 mrg { 2205 1.1 mrg if (alpha_fptm >= ALPHA_FPTM_SU) 2206 1.1 mrg operands[1] = force_reg (SFmode, operands[1]); 2207 1.1 mrg }) 2208 1.1 mrg 2209 1.1 mrg ;; The Unicos/Mk assembler doesn't support cvtst, but we've already 2210 1.1 mrg ;; asserted that alpha_fptm == ALPHA_FPTM_N. 2211 1.1 mrg 2212 1.1 mrg (define_insn "*extendsfdf2_ieee" 2213 1.1 mrg [(set (match_operand:DF 0 "register_operand" "=&f") 2214 1.1 mrg (float_extend:DF (match_operand:SF 1 "register_operand" "f")))] 2215 1.1 mrg "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2216 1.1 mrg "cvtsts %1,%0" 2217 1.1 mrg [(set_attr "type" "fadd") 2218 1.1 mrg (set_attr "trap" "yes")]) 2219 1.1 mrg 2220 1.1 mrg (define_insn "*extendsfdf2_internal" 2221 1.1 mrg [(set (match_operand:DF 0 "register_operand" "=f,f,m") 2222 1.1 mrg (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))] 2223 1.1 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2224 1.1 mrg "@ 2225 1.1.1.2 mrg cpys %1,%1,%0 2226 1.1.1.2 mrg ld%, %0,%1 2227 1.1 mrg st%- %1,%0" 2228 1.1 mrg [(set_attr "type" "fcpys,fld,fst")]) 2229 1.1 mrg 2230 1.1 mrg ;; Use register_operand for operand 1 to prevent compress_float_constant 2231 1.1.1.2 mrg ;; from doing something silly. When optimizing we'll put things back 2232 1.1.1.2 mrg ;; together anyway. 2233 1.1.1.2 mrg (define_expand "extendsftf2" 2234 1.1 mrg [(use (match_operand:TF 0 "register_operand")) 2235 1.1.1.2 mrg (use (match_operand:SF 1 "register_operand"))] 2236 1.1.1.2 mrg "TARGET_HAS_XFLOATING_LIBS" 2237 1.1.1.2 mrg { 2238 1.1.1.2 mrg rtx tmp = gen_reg_rtx (DFmode); 2239 1.1.1.2 mrg emit_insn (gen_extendsfdf2 (tmp, operands[1])); 2240 1.1 mrg emit_insn (gen_extenddftf2 (operands[0], tmp)); 2241 1.1.1.2 mrg DONE; 2242 1.1.1.7 mrg }) 2243 1.1.1.7 mrg 2244 1.1.1.2 mrg (define_expand "extenddftf2" 2245 1.1.1.2 mrg [(use (match_operand:TF 0 "register_operand")) 2246 1.1 mrg (use (match_operand:DF 1 "register_operand"))] 2247 1.1 mrg "TARGET_HAS_XFLOATING_LIBS" 2248 1.1 mrg "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;") 2249 1.1.1.7 mrg 2250 1.1.1.7 mrg (define_insn "truncdfsf2" 2251 1.1.1.7 mrg [(set (match_operand:SF 0 "register_operand" "=f,&f") 2252 1.1.1.7 mrg (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG,fG")))] 2253 1.1.1.7 mrg "TARGET_FP" 2254 1.1.1.7 mrg "cvt%-%,%/ %R1,%0" 2255 1.1 mrg [(set_attr "type" "fadd") 2256 1.1.1.2 mrg (set_attr "trap" "yes") 2257 1.1.1.2 mrg (set_attr "round_suffix" "normal") 2258 1.1.1.2 mrg (set_attr "trap_suffix" "u_su_sui") 2259 1.1 mrg (set (attr "enabled") 2260 1.1.1.2 mrg (cond [(eq_attr "alternative" "0") 2261 1.1 mrg (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 2262 1.1.1.2 mrg ] 2263 1.1.1.2 mrg (symbol_ref "true")))]) 2264 1.1.1.2 mrg 2265 1.1.1.2 mrg (define_expand "trunctfdf2" 2266 1.1.1.2 mrg [(use (match_operand:DF 0 "register_operand")) 2267 1.1.1.2 mrg (use (match_operand:TF 1 "general_operand"))] 2268 1.1 mrg "TARGET_HAS_XFLOATING_LIBS" 2269 1.1.1.2 mrg "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;") 2270 1.1.1.2 mrg 2271 1.1.1.2 mrg (define_expand "trunctfsf2" 2272 1.1.1.2 mrg [(use (match_operand:SF 0 "register_operand")) 2273 1.1.1.2 mrg (use (match_operand:TF 1 "general_operand"))] 2274 1.1 mrg "TARGET_FP && TARGET_HAS_XFLOATING_LIBS" 2275 1.1.1.2 mrg { 2276 1.1.1.2 mrg rtx tmpf, sticky, arg, lo, hi; 2277 1.1.1.2 mrg 2278 1.1.1.2 mrg tmpf = gen_reg_rtx (DFmode); 2279 1.1 mrg sticky = gen_reg_rtx (DImode); 2280 1.1.1.4 mrg arg = copy_to_mode_reg (TFmode, operands[1]); 2281 1.1.1.2 mrg lo = gen_lowpart (DImode, arg); 2282 1.1.1.2 mrg hi = gen_highpart (DImode, arg); 2283 1.1.1.2 mrg 2284 1.1.1.2 mrg /* Convert the low word of the TFmode value into a sticky rounding bit, 2285 1.1.1.2 mrg then or it into the low bit of the high word. This leaves the sticky 2286 1.1 mrg bit at bit 48 of the fraction, which is representable in DFmode, 2287 1.1 mrg which prevents rounding error in the final conversion to SFmode. */ 2288 1.1 mrg 2289 1.1 mrg emit_insn (gen_rtx_SET (sticky, gen_rtx_NE (DImode, lo, const0_rtx))); 2290 1.1 mrg emit_insn (gen_iordi3 (hi, hi, sticky)); 2291 1.1 mrg emit_insn (gen_trunctfdf2 (tmpf, arg)); 2292 1.1 mrg emit_insn (gen_truncdfsf2 (operands[0], tmpf)); 2293 1.1 mrg DONE; 2294 1.1 mrg }) 2295 1.1 mrg 2297 1.1 mrg ;; Next are all the integer comparisons, and conditional moves and branches 2298 1.1 mrg ;; and some of the related define_expand's and define_split's. 2299 1.1 mrg 2300 1.1 mrg (define_insn "*setcc_internal" 2301 1.1 mrg [(set (match_operand 0 "register_operand" "=r") 2302 1.1 mrg (match_operator 1 "alpha_comparison_operator" 2303 1.1 mrg [(match_operand:DI 2 "register_operand" "r") 2304 1.1 mrg (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))] 2305 1.1 mrg "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT 2306 1.1 mrg && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8 2307 1.1 mrg && GET_MODE (operands[0]) == GET_MODE (operands[1])" 2308 1.1 mrg "cmp%C1 %2,%3,%0" 2309 1.1 mrg [(set_attr "type" "icmp")]) 2310 1.1 mrg 2311 1.1 mrg ;; Yes, we can technically support reg_or_8bit_operand in operand 2, 2312 1.1 mrg ;; but that's non-canonical rtl and allowing that causes inefficiencies 2313 1.1 mrg ;; from cse on. 2314 1.1 mrg (define_insn "*setcc_swapped_internal" 2315 1.1 mrg [(set (match_operand 0 "register_operand" "=r") 2316 1.1 mrg (match_operator 1 "alpha_swapped_comparison_operator" 2317 1.1 mrg [(match_operand:DI 2 "register_operand" "r") 2318 1.1 mrg (match_operand:DI 3 "reg_or_0_operand" "rJ")]))] 2319 1.1 mrg "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT 2320 1.1 mrg && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8 2321 1.1 mrg && GET_MODE (operands[0]) == GET_MODE (operands[1])" 2322 1.1 mrg "cmp%c1 %r3,%2,%0" 2323 1.1 mrg [(set_attr "type" "icmp")]) 2324 1.1 mrg 2325 1.1 mrg ;; Use match_operator rather than ne directly so that we can match 2326 1.1 mrg ;; multiple integer modes. 2327 1.1 mrg (define_insn "*setne_internal" 2328 1.1 mrg [(set (match_operand 0 "register_operand" "=r") 2329 1.1 mrg (match_operator 1 "signed_comparison_operator" 2330 1.1 mrg [(match_operand:DI 2 "register_operand" "r") 2331 1.1 mrg (const_int 0)]))] 2332 1.1 mrg "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT 2333 1.1 mrg && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8 2334 1.1 mrg && GET_CODE (operands[1]) == NE 2335 1.1 mrg && GET_MODE (operands[0]) == GET_MODE (operands[1])" 2336 1.1.1.2 mrg "cmpult $31,%2,%0" 2337 1.1.1.2 mrg [(set_attr "type" "icmp")]) 2338 1.1.1.2 mrg 2339 1.1 mrg ;; The mode folding trick can't be used with const_int operands, since 2340 1.1 mrg ;; reload needs to know the proper mode. 2341 1.1 mrg ;; 2342 1.1.1.2 mrg ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand 2343 1.1.1.2 mrg ;; in order to create more pairs of constants. As long as we're allowing 2344 1.1 mrg ;; two constants at the same time, and will have to reload one of them... 2345 1.1 mrg 2346 1.1 mrg (define_insn "*mov<mode>cc_internal" 2347 1.1 mrg [(set (match_operand:IMODE 0 "register_operand" "=r,r,r,r") 2348 1.1 mrg (if_then_else:IMODE 2349 1.1 mrg (match_operator 2 "signed_comparison_operator" 2350 1.1 mrg [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J") 2351 1.1 mrg (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")]) 2352 1.1.1.2 mrg (match_operand:IMODE 1 "add_operand" "rI,0,rI,0") 2353 1.1.1.2 mrg (match_operand:IMODE 5 "add_operand" "0,rI,0,rI")))] 2354 1.1.1.2 mrg "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)" 2355 1.1 mrg "@ 2356 1.1 mrg cmov%C2 %r3,%1,%0 2357 1.1 mrg cmov%D2 %r3,%5,%0 2358 1.1 mrg cmov%c2 %r4,%1,%0 2359 1.1.1.2 mrg cmov%d2 %r4,%5,%0" 2360 1.1.1.2 mrg [(set_attr "type" "icmov")]) 2361 1.1 mrg 2362 1.1 mrg (define_insn "*mov<mode>cc_lbc" 2363 1.1 mrg [(set (match_operand:IMODE 0 "register_operand" "=r,r") 2364 1.1 mrg (if_then_else:IMODE 2365 1.1 mrg (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ") 2366 1.1 mrg (const_int 1) 2367 1.1.1.2 mrg (const_int 0)) 2368 1.1.1.2 mrg (const_int 0)) 2369 1.1.1.2 mrg (match_operand:IMODE 1 "reg_or_8bit_operand" "rI,0") 2370 1.1 mrg (match_operand:IMODE 3 "reg_or_8bit_operand" "0,rI")))] 2371 1.1 mrg "" 2372 1.1 mrg "@ 2373 1.1 mrg cmovlbc %r2,%1,%0 2374 1.1.1.2 mrg cmovlbs %r2,%3,%0" 2375 1.1.1.2 mrg [(set_attr "type" "icmov")]) 2376 1.1 mrg 2377 1.1 mrg (define_insn "*mov<mode>cc_lbs" 2378 1.1 mrg [(set (match_operand:IMODE 0 "register_operand" "=r,r") 2379 1.1 mrg (if_then_else:IMODE 2380 1.1 mrg (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ") 2381 1.1 mrg (const_int 1) 2382 1.1 mrg (const_int 0)) 2383 1.1 mrg (const_int 0)) 2384 1.1 mrg (match_operand:IMODE 1 "reg_or_8bit_operand" "rI,0") 2385 1.1.1.2 mrg (match_operand:IMODE 3 "reg_or_8bit_operand" "0,rI")))] 2386 1.1.1.2 mrg "" 2387 1.1 mrg "@ 2388 1.1 mrg cmovlbs %r2,%1,%0 2389 1.1 mrg cmovlbc %r2,%3,%0" 2390 1.1 mrg [(set_attr "type" "icmov")]) 2391 1.1 mrg 2392 1.1 mrg ;; For ABS, we have two choices, depending on whether the input and output 2393 1.1 mrg ;; registers are the same or not. 2394 1.1 mrg (define_expand "absdi2" 2395 1.1 mrg [(set (match_operand:DI 0 "register_operand") 2396 1.1 mrg (abs:DI (match_operand:DI 1 "register_operand")))] 2397 1.1.1.2 mrg "" 2398 1.1.1.2 mrg { 2399 1.1 mrg if (rtx_equal_p (operands[0], operands[1])) 2400 1.1 mrg emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode))); 2401 1.1 mrg else 2402 1.1.1.2 mrg emit_insn (gen_absdi2_diff (operands[0], operands[1])); 2403 1.1 mrg DONE; 2404 1.1 mrg }) 2405 1.1.1.2 mrg 2406 1.1.1.2 mrg (define_expand "absdi2_same" 2407 1.1 mrg [(set (match_operand:DI 1 "register_operand") 2408 1.1 mrg (neg:DI (match_operand:DI 0 "register_operand"))) 2409 1.1 mrg (set (match_dup 0) 2410 1.1.1.2 mrg (if_then_else:DI (ge (match_dup 0) (const_int 0)) 2411 1.1 mrg (match_dup 0) 2412 1.1 mrg (match_dup 1)))]) 2413 1.1.1.2 mrg 2414 1.1 mrg (define_expand "absdi2_diff" 2415 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand") 2416 1.1 mrg (neg:DI (match_operand:DI 1 "register_operand"))) 2417 1.1 mrg (set (match_dup 0) 2418 1.1 mrg (if_then_else:DI (lt (match_dup 1) (const_int 0)) 2419 1.1.1.2 mrg (match_dup 0) 2420 1.1 mrg (match_dup 1)))]) 2421 1.1 mrg 2422 1.1.1.2 mrg (define_split 2423 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand") 2424 1.1 mrg (abs:DI (match_dup 0))) 2425 1.1 mrg (clobber (match_operand:DI 1 "register_operand"))] 2426 1.1 mrg "" 2427 1.1.1.2 mrg [(set (match_dup 1) (neg:DI (match_dup 0))) 2428 1.1 mrg (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0)) 2429 1.1 mrg (match_dup 0) (match_dup 1)))]) 2430 1.1.1.2 mrg 2431 1.1 mrg (define_split 2432 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand") 2433 1.1 mrg (abs:DI (match_operand:DI 1 "register_operand")))] 2434 1.1 mrg "! rtx_equal_p (operands[0], operands[1])" 2435 1.1 mrg [(set (match_dup 0) (neg:DI (match_dup 1))) 2436 1.1.1.2 mrg (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0)) 2437 1.1 mrg (match_dup 0) (match_dup 1)))]) 2438 1.1 mrg 2439 1.1.1.2 mrg (define_split 2440 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand") 2441 1.1 mrg (neg:DI (abs:DI (match_dup 0)))) 2442 1.1 mrg (clobber (match_operand:DI 1 "register_operand"))] 2443 1.1 mrg "" 2444 1.1.1.2 mrg [(set (match_dup 1) (neg:DI (match_dup 0))) 2445 1.1 mrg (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0)) 2446 1.1.1.2 mrg (match_dup 0) (match_dup 1)))]) 2447 1.1.1.2 mrg 2448 1.1.1.2 mrg (define_split 2449 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand") 2450 1.1.1.2 mrg (neg:DI (abs:DI (match_operand:DI 1 "register_operand"))))] 2451 1.1 mrg "! rtx_equal_p (operands[0], operands[1])" 2452 1.1.1.2 mrg [(set (match_dup 0) (neg:DI (match_dup 1))) 2453 1.1 mrg (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0)) 2454 1.1 mrg (match_dup 0) (match_dup 1)))]) 2455 1.1 mrg 2456 1.1 mrg (define_insn "<code><mode>3" 2457 1.1.1.2 mrg [(set (match_operand:I12MODE 0 "register_operand" "=r") 2458 1.1.1.2 mrg (any_maxmin:I12MODE 2459 1.1.1.2 mrg (match_operand:I12MODE 1 "reg_or_0_operand" "%rJ") 2460 1.1 mrg (match_operand:I12MODE 2 "reg_or_8bit_operand" "rI")))] 2461 1.1 mrg "TARGET_MAX" 2462 1.1 mrg "<maxmin><vecmodesuffix> %r1,%2,%0" 2463 1.1.1.2 mrg [(set_attr "type" "mvi")]) 2464 1.1 mrg 2465 1.1 mrg (define_expand "smaxdi3" 2466 1.1.1.2 mrg [(set (match_dup 3) 2467 1.1.1.2 mrg (le:DI (match_operand:DI 1 "reg_or_0_operand") 2468 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand"))) 2469 1.1.1.2 mrg (set (match_operand:DI 0 "register_operand") 2470 1.1 mrg (if_then_else:DI (eq (match_dup 3) (const_int 0)) 2471 1.1 mrg (match_dup 1) (match_dup 2)))] 2472 1.1 mrg "" 2473 1.1.1.2 mrg "operands[3] = gen_reg_rtx (DImode);") 2474 1.1 mrg 2475 1.1 mrg (define_split 2476 1.1 mrg [(set (match_operand:DI 0 "register_operand") 2477 1.1 mrg (smax:DI (match_operand:DI 1 "reg_or_0_operand") 2478 1.1 mrg (match_operand:DI 2 "reg_or_8bit_operand"))) 2479 1.1 mrg (clobber (match_operand:DI 3 "register_operand"))] 2480 1.1 mrg "operands[2] != const0_rtx" 2481 1.1 mrg [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2))) 2482 1.1 mrg (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0)) 2483 1.1 mrg (match_dup 1) (match_dup 2)))]) 2484 1.1 mrg 2485 1.1.1.2 mrg (define_insn "*smax_const0" 2486 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand" "=r") 2487 1.1.1.2 mrg (smax:DI (match_operand:DI 1 "register_operand" "0") 2488 1.1 mrg (const_int 0)))] 2489 1.1 mrg "" 2490 1.1 mrg "cmovlt %0,0,%0" 2491 1.1.1.2 mrg [(set_attr "type" "icmov")]) 2492 1.1 mrg 2493 1.1 mrg (define_expand "smindi3" 2494 1.1.1.2 mrg [(set (match_dup 3) 2495 1.1.1.2 mrg (lt:DI (match_operand:DI 1 "reg_or_0_operand") 2496 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand"))) 2497 1.1.1.2 mrg (set (match_operand:DI 0 "register_operand") 2498 1.1 mrg (if_then_else:DI (ne (match_dup 3) (const_int 0)) 2499 1.1 mrg (match_dup 1) (match_dup 2)))] 2500 1.1 mrg "" 2501 1.1.1.2 mrg "operands[3] = gen_reg_rtx (DImode);") 2502 1.1 mrg 2503 1.1 mrg (define_split 2504 1.1 mrg [(set (match_operand:DI 0 "register_operand") 2505 1.1 mrg (smin:DI (match_operand:DI 1 "reg_or_0_operand") 2506 1.1 mrg (match_operand:DI 2 "reg_or_8bit_operand"))) 2507 1.1 mrg (clobber (match_operand:DI 3 "register_operand"))] 2508 1.1 mrg "operands[2] != const0_rtx" 2509 1.1 mrg [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2))) 2510 1.1 mrg (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0)) 2511 1.1 mrg (match_dup 1) (match_dup 2)))]) 2512 1.1 mrg 2513 1.1.1.2 mrg (define_insn "*smin_const0" 2514 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand" "=r") 2515 1.1.1.2 mrg (smin:DI (match_operand:DI 1 "register_operand" "0") 2516 1.1 mrg (const_int 0)))] 2517 1.1 mrg "" 2518 1.1 mrg "cmovgt %0,0,%0" 2519 1.1 mrg [(set_attr "type" "icmov")]) 2520 1.1 mrg 2521 1.1 mrg (define_expand "umaxdi3" 2522 1.1.1.2 mrg [(set (match_dup 3) 2523 1.1.1.2 mrg (leu:DI (match_operand:DI 1 "reg_or_0_operand") 2524 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand"))) 2525 1.1.1.2 mrg (set (match_operand:DI 0 "register_operand") 2526 1.1 mrg (if_then_else:DI (eq (match_dup 3) (const_int 0)) 2527 1.1 mrg (match_dup 1) (match_dup 2)))] 2528 1.1 mrg "" 2529 1.1.1.2 mrg "operands[3] = gen_reg_rtx (DImode);") 2530 1.1 mrg 2531 1.1 mrg (define_split 2532 1.1 mrg [(set (match_operand:DI 0 "register_operand") 2533 1.1.1.2 mrg (umax:DI (match_operand:DI 1 "reg_or_0_operand") 2534 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand"))) 2535 1.1.1.2 mrg (clobber (match_operand:DI 3 "register_operand"))] 2536 1.1 mrg "operands[2] != const0_rtx" 2537 1.1 mrg [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2))) 2538 1.1 mrg (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0)) 2539 1.1 mrg (match_dup 1) (match_dup 2)))]) 2540 1.1 mrg 2541 1.1 mrg (define_expand "umindi3" 2542 1.1.1.2 mrg [(set (match_dup 3) 2543 1.1.1.2 mrg (ltu:DI (match_operand:DI 1 "reg_or_0_operand") 2544 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand"))) 2545 1.1.1.2 mrg (set (match_operand:DI 0 "register_operand") 2546 1.1 mrg (if_then_else:DI (ne (match_dup 3) (const_int 0)) 2547 1.1 mrg (match_dup 1) (match_dup 2)))] 2548 1.1 mrg "" 2549 1.1.1.2 mrg "operands[3] = gen_reg_rtx (DImode);") 2550 1.1 mrg 2551 1.1 mrg (define_split 2552 1.1 mrg [(set (match_operand:DI 0 "register_operand") 2553 1.1 mrg (umin:DI (match_operand:DI 1 "reg_or_0_operand") 2554 1.1 mrg (match_operand:DI 2 "reg_or_8bit_operand"))) 2555 1.1 mrg (clobber (match_operand:DI 3 "register_operand"))] 2556 1.1 mrg "operands[2] != const0_rtx" 2557 1.1.1.2 mrg [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2))) 2558 1.1 mrg (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0)) 2559 1.1 mrg (match_dup 1) (match_dup 2)))]) 2560 1.1 mrg 2561 1.1 mrg (define_insn "*bcc_normal" 2562 1.1 mrg [(set (pc) 2563 1.1 mrg (if_then_else 2564 1.1 mrg (match_operator 1 "signed_comparison_operator" 2565 1.1 mrg [(match_operand:DI 2 "reg_or_0_operand" "rJ") 2566 1.1 mrg (const_int 0)]) 2567 1.1 mrg (label_ref (match_operand 0)) 2568 1.1 mrg (pc)))] 2569 1.1 mrg "" 2570 1.1 mrg "b%C1 %r2,%0" 2571 1.1.1.2 mrg [(set_attr "type" "ibr")]) 2572 1.1 mrg 2573 1.1 mrg (define_insn "*bcc_reverse" 2574 1.1 mrg [(set (pc) 2575 1.1 mrg (if_then_else 2576 1.1 mrg (match_operator 1 "signed_comparison_operator" 2577 1.1 mrg [(match_operand:DI 2 "register_operand" "r") 2578 1.1 mrg (const_int 0)]) 2579 1.1 mrg 2580 1.1 mrg (pc) 2581 1.1 mrg (label_ref (match_operand 0))))] 2582 1.1 mrg "" 2583 1.1.1.2 mrg "b%c1 %2,%0" 2584 1.1 mrg [(set_attr "type" "ibr")]) 2585 1.1 mrg 2586 1.1 mrg (define_insn "*blbs_normal" 2587 1.1 mrg [(set (pc) 2588 1.1 mrg (if_then_else 2589 1.1 mrg (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 2590 1.1 mrg (const_int 1) 2591 1.1 mrg (const_int 0)) 2592 1.1 mrg (const_int 0)) 2593 1.1 mrg (label_ref (match_operand 0)) 2594 1.1 mrg (pc)))] 2595 1.1 mrg "" 2596 1.1.1.2 mrg "blbs %r1,%0" 2597 1.1 mrg [(set_attr "type" "ibr")]) 2598 1.1 mrg 2599 1.1 mrg (define_insn "*blbc_normal" 2600 1.1 mrg [(set (pc) 2601 1.1 mrg (if_then_else 2602 1.1 mrg (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 2603 1.1 mrg (const_int 1) 2604 1.1 mrg (const_int 0)) 2605 1.1 mrg (const_int 0)) 2606 1.1 mrg (label_ref (match_operand 0)) 2607 1.1.1.2 mrg (pc)))] 2608 1.1.1.2 mrg "" 2609 1.1.1.2 mrg "blbc %r1,%0" 2610 1.1.1.2 mrg [(set_attr "type" "ibr")]) 2611 1.1.1.2 mrg 2612 1.1 mrg (define_split 2613 1.1.1.2 mrg [(parallel 2614 1.1 mrg [(set (pc) 2615 1.1 mrg (if_then_else 2616 1.1 mrg (match_operator 1 "comparison_operator" 2617 1.1 mrg [(zero_extract:DI (match_operand:DI 2 "register_operand") 2618 1.1 mrg (const_int 1) 2619 1.1 mrg (match_operand:DI 3 "const_int_operand")) 2620 1.1 mrg (const_int 0)]) 2621 1.1 mrg (label_ref (match_operand 0)) 2622 1.1 mrg (pc))) 2623 1.1 mrg (clobber (match_operand:DI 4 "register_operand"))])] 2624 1.1 mrg "INTVAL (operands[3]) != 0" 2625 1.1.1.2 mrg [(set (match_dup 4) 2626 1.1 mrg (lshiftrt:DI (match_dup 2) (match_dup 3))) 2627 1.1 mrg (set (pc) 2628 1.1 mrg (if_then_else (match_op_dup 1 2629 1.1 mrg [(zero_extract:DI (match_dup 4) 2630 1.1 mrg (const_int 1) 2631 1.1 mrg (const_int 0)) 2632 1.1.1.7 mrg (const_int 0)]) 2633 1.1 mrg (label_ref (match_dup 0)) 2634 1.1.1.7 mrg (pc)))] 2635 1.1.1.7 mrg ) 2636 1.1 mrg 2638 1.1 mrg ;; The following are the corresponding floating-point insns. Recall 2639 1.1 mrg ;; we need to have variants that expand the arguments from SFmode 2640 1.1.1.7 mrg ;; to DFmode. 2641 1.1.1.7 mrg 2642 1.1.1.7 mrg (define_insn "*cmpdf_internal" 2643 1.1.1.7 mrg [(set (match_operand:DF 0 "register_operand" "=f,&f") 2644 1.1.1.7 mrg (match_operator:DF 1 "alpha_fp_comparison_operator" 2645 1.1.1.7 mrg [(match_operand:DF 2 "reg_or_0_operand" "fG,fG") 2646 1.1 mrg (match_operand:DF 3 "reg_or_0_operand" "fG,fG")]))] 2647 1.1 mrg "TARGET_FP" 2648 1.1 mrg "cmp%-%C1%/ %R2,%R3,%0" 2649 1.1 mrg [(set_attr "type" "fadd") 2650 1.1 mrg (set_attr "trap" "yes") 2651 1.1 mrg (set_attr "trap_suffix" "su") 2652 1.1 mrg (set (attr "enabled") 2653 1.1 mrg (cond [(eq_attr "alternative" "0") 2654 1.1 mrg (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 2655 1.1 mrg ] 2656 1.1 mrg (symbol_ref "true")))]) 2657 1.1 mrg 2658 1.1 mrg (define_insn "*cmpdf_ext1" 2659 1.1 mrg [(set (match_operand:DF 0 "register_operand" "=f") 2660 1.1 mrg (match_operator:DF 1 "alpha_fp_comparison_operator" 2661 1.1 mrg [(float_extend:DF 2662 1.1 mrg (match_operand:SF 2 "reg_or_0_operand" "fG")) 2663 1.1 mrg (match_operand:DF 3 "reg_or_0_operand" "fG")]))] 2664 1.1 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2665 1.1 mrg "cmp%-%C1%/ %R2,%R3,%0" 2666 1.1 mrg [(set_attr "type" "fadd") 2667 1.1 mrg (set_attr "trap" "yes") 2668 1.1 mrg (set_attr "trap_suffix" "su")]) 2669 1.1 mrg 2670 1.1 mrg (define_insn "*cmpdf_ext2" 2671 1.1 mrg [(set (match_operand:DF 0 "register_operand" "=f") 2672 1.1 mrg (match_operator:DF 1 "alpha_fp_comparison_operator" 2673 1.1 mrg [(match_operand:DF 2 "reg_or_0_operand" "fG") 2674 1.1 mrg (float_extend:DF 2675 1.1 mrg (match_operand:SF 3 "reg_or_0_operand" "fG"))]))] 2676 1.1 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2677 1.1 mrg "cmp%-%C1%/ %R2,%R3,%0" 2678 1.1 mrg [(set_attr "type" "fadd") 2679 1.1 mrg (set_attr "trap" "yes") 2680 1.1 mrg (set_attr "trap_suffix" "su")]) 2681 1.1 mrg 2682 1.1 mrg (define_insn "*cmpdf_ext3" 2683 1.1 mrg [(set (match_operand:DF 0 "register_operand" "=f") 2684 1.1.1.2 mrg (match_operator:DF 1 "alpha_fp_comparison_operator" 2685 1.1.1.2 mrg [(float_extend:DF 2686 1.1.1.2 mrg (match_operand:SF 2 "reg_or_0_operand" "fG")) 2687 1.1 mrg (float_extend:DF 2688 1.1 mrg (match_operand:SF 3 "reg_or_0_operand" "fG"))]))] 2689 1.1 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2690 1.1.1.2 mrg "cmp%-%C1%/ %R2,%R3,%0" 2691 1.1.1.2 mrg [(set_attr "type" "fadd") 2692 1.1 mrg (set_attr "trap" "yes") 2693 1.1 mrg (set_attr "trap_suffix" "su")]) 2694 1.1 mrg 2695 1.1 mrg (define_insn "*mov<mode>cc_internal" 2696 1.1 mrg [(set (match_operand:FMODE 0 "register_operand" "=f,f") 2697 1.1 mrg (if_then_else:FMODE 2698 1.1 mrg (match_operator 3 "signed_comparison_operator" 2699 1.1 mrg [(match_operand:DF 4 "reg_or_0_operand" "fG,fG") 2700 1.1 mrg (match_operand:DF 2 "const0_operand" "G,G")]) 2701 1.1 mrg (match_operand:FMODE 1 "reg_or_0_operand" "fG,0") 2702 1.1 mrg (match_operand:FMODE 5 "reg_or_0_operand" "0,fG")))] 2703 1.1 mrg "TARGET_FP" 2704 1.1 mrg "@ 2705 1.1 mrg fcmov%C3 %R4,%R1,%0 2706 1.1 mrg fcmov%D3 %R4,%R5,%0" 2707 1.1 mrg [(set_attr "type" "fcmov")]) 2708 1.1 mrg 2709 1.1 mrg (define_insn "*movdfcc_ext1" 2710 1.1 mrg [(set (match_operand:DF 0 "register_operand" "=f,f") 2711 1.1 mrg (if_then_else:DF 2712 1.1 mrg (match_operator 3 "signed_comparison_operator" 2713 1.1 mrg [(match_operand:DF 4 "reg_or_0_operand" "fG,fG") 2714 1.1 mrg (match_operand:DF 2 "const0_operand" "G,G")]) 2715 1.1 mrg (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0")) 2716 1.1 mrg (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] 2717 1.1 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2718 1.1 mrg "@ 2719 1.1 mrg fcmov%C3 %R4,%R1,%0 2720 1.1 mrg fcmov%D3 %R4,%R5,%0" 2721 1.1 mrg [(set_attr "type" "fcmov")]) 2722 1.1 mrg 2723 1.1 mrg (define_insn "*movdfcc_ext2" 2724 1.1 mrg [(set (match_operand:DF 0 "register_operand" "=f,f") 2725 1.1 mrg (if_then_else:DF 2726 1.1 mrg (match_operator 3 "signed_comparison_operator" 2727 1.1 mrg [(float_extend:DF 2728 1.1 mrg (match_operand:SF 4 "reg_or_0_operand" "fG,fG")) 2729 1.1 mrg (match_operand:DF 2 "const0_operand" "G,G")]) 2730 1.1 mrg (match_operand:DF 1 "reg_or_0_operand" "fG,0") 2731 1.1 mrg (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] 2732 1.1 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2733 1.1 mrg "@ 2734 1.1 mrg fcmov%C3 %R4,%R1,%0 2735 1.1 mrg fcmov%D3 %R4,%R5,%0" 2736 1.1 mrg [(set_attr "type" "fcmov")]) 2737 1.1 mrg 2738 1.1 mrg (define_insn "*movdfcc_ext3" 2739 1.1 mrg [(set (match_operand:SF 0 "register_operand" "=f,f") 2740 1.1 mrg (if_then_else:SF 2741 1.1 mrg (match_operator 3 "signed_comparison_operator" 2742 1.1 mrg [(float_extend:DF 2743 1.1 mrg (match_operand:SF 4 "reg_or_0_operand" "fG,fG")) 2744 1.1 mrg (match_operand:DF 2 "const0_operand" "G,G")]) 2745 1.1 mrg (match_operand:SF 1 "reg_or_0_operand" "fG,0") 2746 1.1 mrg (match_operand:SF 5 "reg_or_0_operand" "0,fG")))] 2747 1.1 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2748 1.1 mrg "@ 2749 1.1 mrg fcmov%C3 %R4,%R1,%0 2750 1.1 mrg fcmov%D3 %R4,%R5,%0" 2751 1.1 mrg [(set_attr "type" "fcmov")]) 2752 1.1 mrg 2753 1.1 mrg (define_insn "*movdfcc_ext4" 2754 1.1 mrg [(set (match_operand:DF 0 "register_operand" "=f,f") 2755 1.1 mrg (if_then_else:DF 2756 1.1 mrg (match_operator 3 "signed_comparison_operator" 2757 1.1 mrg [(float_extend:DF 2758 1.1 mrg (match_operand:SF 4 "reg_or_0_operand" "fG,fG")) 2759 1.1.1.2 mrg (match_operand:DF 2 "const0_operand" "G,G")]) 2760 1.1.1.2 mrg (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0")) 2761 1.1.1.2 mrg (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] 2762 1.1 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2763 1.1 mrg "@ 2764 1.1 mrg fcmov%C3 %R4,%R1,%0 2765 1.1 mrg fcmov%D3 %R4,%R5,%0" 2766 1.1 mrg [(set_attr "type" "fcmov")]) 2767 1.1 mrg 2768 1.1 mrg (define_expand "smaxdf3" 2769 1.1 mrg [(set (match_dup 3) 2770 1.1 mrg (le:DF (match_operand:DF 1 "reg_or_0_operand") 2771 1.1 mrg (match_operand:DF 2 "reg_or_0_operand"))) 2772 1.1.1.2 mrg (set (match_operand:DF 0 "register_operand") 2773 1.1.1.2 mrg (if_then_else:DF (eq (match_dup 3) (match_dup 4)) 2774 1.1.1.2 mrg (match_dup 1) (match_dup 2)))] 2775 1.1 mrg "TARGET_FP" 2776 1.1 mrg { 2777 1.1 mrg operands[3] = gen_reg_rtx (DFmode); 2778 1.1 mrg operands[4] = CONST0_RTX (DFmode); 2779 1.1 mrg }) 2780 1.1 mrg 2781 1.1 mrg (define_expand "smindf3" 2782 1.1 mrg [(set (match_dup 3) 2783 1.1 mrg (lt:DF (match_operand:DF 1 "reg_or_0_operand") 2784 1.1 mrg (match_operand:DF 2 "reg_or_0_operand"))) 2785 1.1.1.2 mrg (set (match_operand:DF 0 "register_operand") 2786 1.1.1.2 mrg (if_then_else:DF (ne (match_dup 3) (match_dup 4)) 2787 1.1.1.2 mrg (match_dup 1) (match_dup 2)))] 2788 1.1 mrg "TARGET_FP" 2789 1.1 mrg { 2790 1.1 mrg operands[3] = gen_reg_rtx (DFmode); 2791 1.1 mrg operands[4] = CONST0_RTX (DFmode); 2792 1.1 mrg }) 2793 1.1 mrg 2794 1.1 mrg (define_expand "smaxsf3" 2795 1.1 mrg [(set (match_dup 3) 2796 1.1 mrg (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand")) 2797 1.1 mrg (float_extend:DF (match_operand:SF 2 "reg_or_0_operand")))) 2798 1.1.1.2 mrg (set (match_operand:SF 0 "register_operand") 2799 1.1.1.2 mrg (if_then_else:SF (eq (match_dup 3) (match_dup 4)) 2800 1.1.1.2 mrg (match_dup 1) (match_dup 2)))] 2801 1.1 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2802 1.1 mrg { 2803 1.1 mrg operands[3] = gen_reg_rtx (DFmode); 2804 1.1 mrg operands[4] = CONST0_RTX (DFmode); 2805 1.1 mrg }) 2806 1.1 mrg 2807 1.1 mrg (define_expand "sminsf3" 2808 1.1 mrg [(set (match_dup 3) 2809 1.1 mrg (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand")) 2810 1.1 mrg (float_extend:DF (match_operand:SF 2 "reg_or_0_operand")))) 2811 1.1 mrg (set (match_operand:SF 0 "register_operand") 2812 1.1 mrg (if_then_else:SF (ne (match_dup 3) (match_dup 4)) 2813 1.1 mrg (match_dup 1) (match_dup 2)))] 2814 1.1 mrg "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2815 1.1.1.2 mrg { 2816 1.1 mrg operands[3] = gen_reg_rtx (DFmode); 2817 1.1 mrg operands[4] = CONST0_RTX (DFmode); 2818 1.1 mrg }) 2819 1.1 mrg 2820 1.1 mrg (define_insn "*fbcc_normal" 2821 1.1 mrg [(set (pc) 2822 1.1 mrg (if_then_else 2823 1.1 mrg (match_operator 1 "signed_comparison_operator" 2824 1.1 mrg [(match_operand:DF 2 "reg_or_0_operand" "fG") 2825 1.1 mrg (match_operand:DF 3 "const0_operand" "G")]) 2826 1.1 mrg (label_ref (match_operand 0)) 2827 1.1 mrg (pc)))] 2828 1.1.1.2 mrg "TARGET_FP" 2829 1.1 mrg "fb%C1 %R2,%0" 2830 1.1 mrg [(set_attr "type" "fbr")]) 2831 1.1 mrg 2832 1.1 mrg (define_insn "*fbcc_ext_normal" 2833 1.1 mrg [(set (pc) 2834 1.1 mrg (if_then_else 2835 1.1 mrg (match_operator 1 "signed_comparison_operator" 2836 1.1 mrg [(float_extend:DF 2837 1.1 mrg (match_operand:SF 2 "reg_or_0_operand" "fG")) 2838 1.1 mrg (match_operand:DF 3 "const0_operand" "G")]) 2839 1.1.1.2 mrg (label_ref (match_operand 0)) 2840 1.1.1.2 mrg (pc)))] 2841 1.1.1.2 mrg "TARGET_FP" 2842 1.1 mrg "fb%C1 %R2,%0" 2843 1.1.1.2 mrg [(set_attr "type" "fbr")]) 2844 1.1 mrg 2846 1.1 mrg ;; These are the main define_expand's used to make conditional branches 2847 1.1 mrg ;; and compares. 2848 1.1 mrg 2849 1.1.1.2 mrg (define_expand "cbranchdf4" 2850 1.1 mrg [(use (match_operator 0 "alpha_cbranch_operator" 2851 1.1.1.2 mrg [(match_operand:DF 1 "reg_or_0_operand") 2852 1.1 mrg (match_operand:DF 2 "reg_or_0_operand")])) 2853 1.1 mrg (use (match_operand 3))] 2854 1.1 mrg "TARGET_FP" 2855 1.1.1.4 mrg "alpha_emit_conditional_branch (operands, DFmode); DONE;") 2856 1.1.1.4 mrg 2857 1.1.1.2 mrg (define_expand "cbranchtf4" 2858 1.1 mrg [(use (match_operator 0 "alpha_cbranch_operator" 2859 1.1.1.2 mrg [(match_operand:TF 1 "general_operand") 2860 1.1 mrg (match_operand:TF 2 "general_operand")])) 2861 1.1 mrg (use (match_operand 3))] 2862 1.1 mrg "TARGET_HAS_XFLOATING_LIBS" 2863 1.1 mrg "alpha_emit_conditional_branch (operands, TFmode); DONE;") 2864 1.1 mrg 2865 1.1 mrg (define_expand "cbranchdi4" 2866 1.1 mrg [(use (match_operator 0 "alpha_cbranch_operator" 2867 1.1.1.2 mrg [(match_operand:DI 1 "general_operand") 2868 1.1.1.2 mrg (match_operand:DI 2 "general_operand")])) 2869 1.1.1.2 mrg (use (match_operand 3))] 2870 1.1.1.2 mrg "" 2871 1.1.1.2 mrg "alpha_emit_conditional_branch (operands, DImode); DONE;") 2872 1.1.1.2 mrg 2873 1.1 mrg (define_expand "cstoredf4" 2874 1.1 mrg [(use (match_operator:DI 1 "alpha_cbranch_operator" 2875 1.1 mrg [(match_operand:DF 2 "reg_or_0_operand") 2876 1.1 mrg (match_operand:DF 3 "reg_or_0_operand")])) 2877 1.1 mrg (clobber (match_operand:DI 0 "register_operand"))] 2878 1.1 mrg "TARGET_FP" 2879 1.1 mrg { 2880 1.1.1.2 mrg if (alpha_emit_setcc (operands, DFmode)) 2881 1.1.1.2 mrg DONE; 2882 1.1.1.2 mrg else 2883 1.1.1.2 mrg FAIL; 2884 1.1.1.2 mrg }) 2885 1.1.1.2 mrg 2886 1.1 mrg (define_expand "cstoretf4" 2887 1.1 mrg [(use (match_operator:DI 1 "alpha_cbranch_operator" 2888 1.1 mrg [(match_operand:TF 2 "general_operand") 2889 1.1.1.4 mrg (match_operand:TF 3 "general_operand")])) 2890 1.1.1.4 mrg (clobber (match_operand:DI 0 "register_operand"))] 2891 1.1.1.2 mrg "TARGET_HAS_XFLOATING_LIBS" 2892 1.1 mrg { 2893 1.1 mrg if (alpha_emit_setcc (operands, TFmode)) 2894 1.1.1.2 mrg DONE; 2895 1.1.1.2 mrg else 2896 1.1.1.2 mrg FAIL; 2897 1.1 mrg }) 2898 1.1 mrg 2899 1.1.1.2 mrg (define_expand "cstoredi4" 2900 1.1.1.2 mrg [(use (match_operator:DI 1 "alpha_cbranch_operator" 2901 1.1 mrg [(match_operand:DI 2 "general_operand") 2902 1.1.1.2 mrg (match_operand:DI 3 "general_operand")])) 2903 1.1.1.2 mrg (clobber (match_operand:DI 0 "register_operand"))] 2904 1.1.1.2 mrg "" 2905 1.1.1.2 mrg { 2906 1.1.1.2 mrg if (alpha_emit_setcc (operands, DImode)) 2907 1.1.1.2 mrg DONE; 2908 1.1 mrg else 2909 1.1 mrg FAIL; 2910 1.1.1.2 mrg }) 2911 1.1.1.2 mrg 2913 1.1 mrg ;; These are the main define_expand's used to make conditional moves. 2914 1.1 mrg 2915 1.1.1.2 mrg (define_expand "mov<mode>cc" 2916 1.1.1.2 mrg [(set (match_operand:I48MODE 0 "register_operand") 2917 1.1.1.2 mrg (if_then_else:I48MODE 2918 1.1.1.2 mrg (match_operand 1 "comparison_operator") 2919 1.1.1.2 mrg (match_operand:I48MODE 2 "reg_or_8bit_operand") 2920 1.1.1.2 mrg (match_operand:I48MODE 3 "reg_or_8bit_operand")))] 2921 1.1 mrg "" 2922 1.1 mrg { 2923 1.1.1.2 mrg operands[1] = alpha_emit_conditional_move (operands[1], <MODE>mode); 2924 1.1.1.2 mrg if (operands[1] == 0) 2925 1.1 mrg FAIL; 2926 1.1 mrg }) 2927 1.1 mrg 2928 1.1 mrg (define_expand "mov<mode>cc" 2929 1.1 mrg [(set (match_operand:FMODE 0 "register_operand") 2930 1.1 mrg (if_then_else:FMODE 2931 1.1 mrg (match_operand 1 "comparison_operator") 2932 1.1 mrg (match_operand:FMODE 2 "reg_or_8bit_operand") 2933 1.1 mrg (match_operand:FMODE 3 "reg_or_8bit_operand")))] 2934 1.1 mrg "" 2935 1.1 mrg { 2936 1.1 mrg operands[1] = alpha_emit_conditional_move (operands[1], <MODE>mode); 2937 1.1 mrg if (operands[1] == 0) 2938 1.1 mrg FAIL; 2939 1.1 mrg }) 2940 1.1 mrg 2942 1.1 mrg ;; These define_split definitions are used in cases when comparisons have 2943 1.1 mrg ;; not be stated in the correct way and we need to reverse the second 2944 1.1 mrg ;; comparison. For example, x >= 7 has to be done as x < 6 with the 2945 1.1 mrg ;; comparison that tests the result being reversed. We have one define_split 2946 1.1.1.2 mrg ;; for each use of a comparison. They do not match valid insns and need 2947 1.1 mrg ;; not generate valid insns. 2948 1.1 mrg ;; 2949 1.1.1.2 mrg ;; We can also handle equality comparisons (and inequality comparisons in 2950 1.1.1.2 mrg ;; cases where the resulting add cannot overflow) by doing an add followed by 2951 1.1.1.2 mrg ;; a comparison with zero. This is faster since the addition takes one 2952 1.1.1.2 mrg ;; less cycle than a compare when feeding into a conditional move. 2953 1.1.1.2 mrg ;; For this case, we also have an SImode pattern since we can merge the add 2954 1.1 mrg ;; and sign extend and the order doesn't matter. 2955 1.1 mrg ;; 2956 1.1 mrg ;; We do not do this for floating-point, since it isn't clear how the "wrong" 2957 1.1 mrg ;; operation could have been generated. 2958 1.1 mrg 2959 1.1 mrg (define_split 2960 1.1 mrg [(set (match_operand:DI 0 "register_operand") 2961 1.1 mrg (if_then_else:DI 2962 1.1 mrg (match_operator 1 "comparison_operator" 2963 1.1 mrg [(match_operand:DI 2 "reg_or_0_operand") 2964 1.1 mrg (match_operand:DI 3 "reg_or_cint_operand")]) 2965 1.1 mrg (match_operand:DI 4 "reg_or_cint_operand") 2966 1.1 mrg (match_operand:DI 5 "reg_or_cint_operand"))) 2967 1.1 mrg (clobber (match_operand:DI 6 "register_operand"))] 2968 1.1 mrg "operands[3] != const0_rtx" 2969 1.1 mrg [(set (match_dup 6) (match_dup 7)) 2970 1.1 mrg (set (match_dup 0) 2971 1.1 mrg (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))] 2972 1.1 mrg { 2973 1.1 mrg enum rtx_code code = GET_CODE (operands[1]); 2974 1.1 mrg int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU); 2975 1.1 mrg 2976 1.1 mrg /* If we are comparing for equality with a constant and that constant 2977 1.1 mrg appears in the arm when the register equals the constant, use the 2978 1.1 mrg register since that is more likely to match (and to produce better code 2979 1.1 mrg if both would). */ 2980 1.1 mrg 2981 1.1 mrg if (code == EQ && CONST_INT_P (operands[3]) 2982 1.1 mrg && rtx_equal_p (operands[4], operands[3])) 2983 1.1 mrg operands[4] = operands[2]; 2984 1.1 mrg 2985 1.1 mrg else if (code == NE && CONST_INT_P (operands[3]) 2986 1.1 mrg && rtx_equal_p (operands[5], operands[3])) 2987 1.1 mrg operands[5] = operands[2]; 2988 1.1 mrg 2989 1.1 mrg if (code == NE || code == EQ 2990 1.1 mrg || (extended_count (operands[2], DImode, unsignedp) >= 1 2991 1.1 mrg && extended_count (operands[3], DImode, unsignedp) >= 1)) 2992 1.1 mrg { 2993 1.1 mrg if (CONST_INT_P (operands[3])) 2994 1.1 mrg operands[7] = gen_rtx_PLUS (DImode, operands[2], 2995 1.1 mrg GEN_INT (- INTVAL (operands[3]))); 2996 1.1 mrg else 2997 1.1 mrg operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]); 2998 1.1 mrg 2999 1.1 mrg operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx); 3000 1.1 mrg } 3001 1.1 mrg 3002 1.1 mrg else if (code == EQ || code == LE || code == LT 3003 1.1.1.2 mrg || code == LEU || code == LTU) 3004 1.1 mrg { 3005 1.1 mrg operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]); 3006 1.1.1.2 mrg operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx); 3007 1.1.1.2 mrg } 3008 1.1.1.2 mrg else 3009 1.1.1.2 mrg { 3010 1.1.1.2 mrg operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode, 3011 1.1 mrg operands[2], operands[3]); 3012 1.1 mrg operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx); 3013 1.1 mrg } 3014 1.1 mrg }) 3015 1.1 mrg 3016 1.1 mrg (define_split 3017 1.1 mrg [(set (match_operand:DI 0 "register_operand") 3018 1.1 mrg (if_then_else:DI 3019 1.1 mrg (match_operator 1 "comparison_operator" 3020 1.1 mrg [(match_operand:SI 2 "reg_or_0_operand") 3021 1.1 mrg (match_operand:SI 3 "reg_or_cint_operand")]) 3022 1.1 mrg (match_operand:DI 4 "reg_or_8bit_operand") 3023 1.1 mrg (match_operand:DI 5 "reg_or_8bit_operand"))) 3024 1.1 mrg (clobber (match_operand:DI 6 "register_operand"))] 3025 1.1 mrg "operands[3] != const0_rtx 3026 1.1 mrg && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)" 3027 1.1 mrg [(set (match_dup 6) (match_dup 7)) 3028 1.1 mrg (set (match_dup 0) 3029 1.1 mrg (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))] 3030 1.1 mrg { 3031 1.1 mrg enum rtx_code code = GET_CODE (operands[1]); 3032 1.1 mrg int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU); 3033 1.1 mrg rtx tem; 3034 1.1 mrg 3035 1.1 mrg if ((code != NE && code != EQ 3036 1.1 mrg && ! (extended_count (operands[2], DImode, unsignedp) >= 1 3037 1.1 mrg && extended_count (operands[3], DImode, unsignedp) >= 1))) 3038 1.1 mrg FAIL; 3039 1.1 mrg 3040 1.1.1.2 mrg if (CONST_INT_P (operands[3])) 3041 1.1 mrg tem = gen_rtx_PLUS (SImode, operands[2], 3042 1.1.1.2 mrg GEN_INT (- INTVAL (operands[3]))); 3043 1.1 mrg else 3044 1.1.1.2 mrg tem = gen_rtx_MINUS (SImode, operands[2], operands[3]); 3045 1.1.1.2 mrg 3046 1.1 mrg operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem); 3047 1.1 mrg operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode, 3048 1.1 mrg operands[6], const0_rtx); 3049 1.1 mrg }) 3050 1.1 mrg 3051 1.1 mrg ;; Prefer to use cmp and arithmetic when possible instead of a cmove. 3052 1.1 mrg 3053 1.1 mrg (define_split 3054 1.1 mrg [(set (match_operand 0 "register_operand") 3055 1.1 mrg (if_then_else (match_operator 1 "signed_comparison_operator" 3056 1.1 mrg [(match_operand:DI 2 "reg_or_0_operand") 3057 1.1 mrg (const_int 0)]) 3058 1.1 mrg (match_operand 3 "const_int_operand") 3059 1.1.1.2 mrg (match_operand 4 "const_int_operand")))] 3060 1.1 mrg "" 3061 1.1 mrg [(const_int 0)] 3062 1.1.1.2 mrg { 3063 1.1.1.2 mrg if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0], 3064 1.1.1.2 mrg operands[2], operands[3], operands[4])) 3065 1.1 mrg DONE; 3066 1.1 mrg else 3067 1.1 mrg FAIL; 3068 1.1 mrg }) 3069 1.1 mrg 3070 1.1 mrg ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know. 3071 1.1 mrg ;; Oh well, we match it in movcc, so it must be partially our fault. 3072 1.1 mrg (define_split 3073 1.1 mrg [(set (match_operand 0 "register_operand") 3074 1.1 mrg (if_then_else (match_operator 1 "signed_comparison_operator" 3075 1.1 mrg [(const_int 0) 3076 1.1 mrg (match_operand:DI 2 "reg_or_0_operand")]) 3077 1.1 mrg (match_operand 3 "const_int_operand") 3078 1.1 mrg (match_operand 4 "const_int_operand")))] 3079 1.1 mrg "" 3080 1.1 mrg [(const_int 0)] 3081 1.1 mrg { 3082 1.1 mrg if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])), 3083 1.1 mrg operands[0], operands[2], operands[3], 3084 1.1 mrg operands[4])) 3085 1.1 mrg DONE; 3086 1.1 mrg else 3087 1.1 mrg FAIL; 3088 1.1 mrg }) 3089 1.1 mrg 3090 1.1 mrg (define_insn_and_split "*cmp_sadd_di" 3091 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 3092 1.1.1.6 mrg (plus:DI (if_then_else:DI 3093 1.1 mrg (match_operator 1 "alpha_zero_comparison_operator" 3094 1.1 mrg [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3095 1.1.1.6 mrg (const_int 0)]) 3096 1.1 mrg (match_operand:DI 3 "const48_operand" "I") 3097 1.1 mrg (const_int 0)) 3098 1.1 mrg (match_operand:DI 4 "sext_add_operand" "rIO"))) 3099 1.1 mrg (clobber (match_scratch:DI 5 "=r"))] 3100 1.1 mrg "" 3101 1.1 mrg "#" 3102 1.1 mrg "" 3103 1.1 mrg [(set (match_dup 5) 3104 1.1 mrg (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3105 1.1 mrg (set (match_dup 0) 3106 1.1 mrg (plus:DI (ashift:DI (match_dup 5) (match_dup 3)) 3107 1.1 mrg (match_dup 4)))] 3108 1.1 mrg { 3109 1.1 mrg operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3]))); 3110 1.1 mrg if (can_create_pseudo_p ()) 3111 1.1 mrg operands[5] = gen_reg_rtx (DImode); 3112 1.1 mrg else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3113 1.1 mrg operands[5] = operands[0]; 3114 1.1 mrg }) 3115 1.1 mrg 3116 1.1 mrg (define_insn_and_split "*cmp_sadd_si" 3117 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=r") 3118 1.1.1.6 mrg (plus:SI (if_then_else:SI 3119 1.1 mrg (match_operator 1 "alpha_zero_comparison_operator" 3120 1.1 mrg [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3121 1.1.1.6 mrg (const_int 0)]) 3122 1.1 mrg (match_operand:SI 3 "const48_operand" "I") 3123 1.1 mrg (const_int 0)) 3124 1.1 mrg (match_operand:SI 4 "sext_add_operand" "rIO"))) 3125 1.1 mrg (clobber (match_scratch:DI 5 "=r"))] 3126 1.1 mrg "" 3127 1.1 mrg "#" 3128 1.1 mrg "" 3129 1.1 mrg [(set (match_dup 5) 3130 1.1 mrg (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3131 1.1 mrg (set (match_dup 0) 3132 1.1 mrg (plus:SI (ashift:SI (match_dup 6) (match_dup 3)) 3133 1.1 mrg (match_dup 4)))] 3134 1.1 mrg { 3135 1.1 mrg operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3]))); 3136 1.1 mrg if (can_create_pseudo_p ()) 3137 1.1 mrg operands[5] = gen_reg_rtx (DImode); 3138 1.1 mrg else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3139 1.1 mrg operands[5] = gen_lowpart (DImode, operands[0]); 3140 1.1 mrg 3141 1.1 mrg operands[6] = gen_lowpart (SImode, operands[5]); 3142 1.1 mrg }) 3143 1.1 mrg 3144 1.1 mrg (define_insn_and_split "*cmp_sadd_sidi" 3145 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 3146 1.1 mrg (sign_extend:DI 3147 1.1.1.6 mrg (plus:SI (if_then_else:SI 3148 1.1 mrg (match_operator 1 "alpha_zero_comparison_operator" 3149 1.1 mrg [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3150 1.1.1.6 mrg (const_int 0)]) 3151 1.1 mrg (match_operand:SI 3 "const48_operand" "I") 3152 1.1 mrg (const_int 0)) 3153 1.1 mrg (match_operand:SI 4 "sext_add_operand" "rIO")))) 3154 1.1 mrg (clobber (match_scratch:DI 5 "=r"))] 3155 1.1 mrg "" 3156 1.1 mrg "#" 3157 1.1 mrg "" 3158 1.1 mrg [(set (match_dup 5) 3159 1.1 mrg (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3160 1.1 mrg (set (match_dup 0) 3161 1.1 mrg (sign_extend:DI (plus:SI (ashift:SI (match_dup 6) (match_dup 3)) 3162 1.1 mrg (match_dup 4))))] 3163 1.1 mrg { 3164 1.1 mrg operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3]))); 3165 1.1 mrg if (can_create_pseudo_p ()) 3166 1.1 mrg operands[5] = gen_reg_rtx (DImode); 3167 1.1 mrg else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3168 1.1 mrg operands[5] = operands[0]; 3169 1.1 mrg 3170 1.1 mrg operands[6] = gen_lowpart (SImode, operands[5]); 3171 1.1 mrg }) 3172 1.1 mrg 3173 1.1 mrg (define_insn_and_split "*cmp_ssub_di" 3174 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 3175 1.1.1.6 mrg (minus:DI (if_then_else:DI 3176 1.1 mrg (match_operator 1 "alpha_zero_comparison_operator" 3177 1.1 mrg [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3178 1.1.1.6 mrg (const_int 0)]) 3179 1.1 mrg (match_operand:DI 3 "const48_operand" "I") 3180 1.1 mrg (const_int 0)) 3181 1.1 mrg (match_operand:DI 4 "reg_or_8bit_operand" "rI"))) 3182 1.1 mrg (clobber (match_scratch:DI 5 "=r"))] 3183 1.1 mrg "" 3184 1.1 mrg "#" 3185 1.1 mrg "" 3186 1.1 mrg [(set (match_dup 5) 3187 1.1 mrg (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3188 1.1 mrg (set (match_dup 0) 3189 1.1 mrg (minus:DI (ashift:DI (match_dup 5) (match_dup 3)) 3190 1.1 mrg (match_dup 4)))] 3191 1.1 mrg { 3192 1.1 mrg operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3]))); 3193 1.1 mrg if (can_create_pseudo_p ()) 3194 1.1 mrg operands[5] = gen_reg_rtx (DImode); 3195 1.1 mrg else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3196 1.1 mrg operands[5] = operands[0]; 3197 1.1 mrg }) 3198 1.1 mrg 3199 1.1 mrg (define_insn_and_split "*cmp_ssub_si" 3200 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=r") 3201 1.1.1.6 mrg (minus:SI (if_then_else:SI 3202 1.1 mrg (match_operator 1 "alpha_zero_comparison_operator" 3203 1.1 mrg [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3204 1.1.1.6 mrg (const_int 0)]) 3205 1.1 mrg (match_operand:SI 3 "const48_operand" "I") 3206 1.1 mrg (const_int 0)) 3207 1.1 mrg (match_operand:SI 4 "reg_or_8bit_operand" "rI"))) 3208 1.1 mrg (clobber (match_scratch:DI 5 "=r"))] 3209 1.1 mrg "" 3210 1.1 mrg "#" 3211 1.1 mrg "" 3212 1.1 mrg [(set (match_dup 5) 3213 1.1 mrg (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3214 1.1 mrg (set (match_dup 0) 3215 1.1 mrg (minus:SI (ashift:SI (match_dup 6) (match_dup 3)) 3216 1.1 mrg (match_dup 4)))] 3217 1.1 mrg { 3218 1.1 mrg operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3]))); 3219 1.1 mrg if (can_create_pseudo_p ()) 3220 1.1 mrg operands[5] = gen_reg_rtx (DImode); 3221 1.1 mrg else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3222 1.1 mrg operands[5] = gen_lowpart (DImode, operands[0]); 3223 1.1 mrg 3224 1.1 mrg operands[6] = gen_lowpart (SImode, operands[5]); 3225 1.1 mrg }) 3226 1.1 mrg 3227 1.1 mrg (define_insn_and_split "*cmp_ssub_sidi" 3228 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 3229 1.1 mrg (sign_extend:DI 3230 1.1.1.6 mrg (minus:SI (if_then_else:SI 3231 1.1 mrg (match_operator 1 "alpha_zero_comparison_operator" 3232 1.1 mrg [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3233 1.1.1.6 mrg (const_int 0)]) 3234 1.1 mrg (match_operand:SI 3 "const48_operand" "I") 3235 1.1 mrg (const_int 0)) 3236 1.1 mrg (match_operand:SI 4 "reg_or_8bit_operand" "rI")))) 3237 1.1 mrg (clobber (match_scratch:DI 5 "=r"))] 3238 1.1 mrg "" 3239 1.1 mrg "#" 3240 1.1 mrg "" 3241 1.1 mrg [(set (match_dup 5) 3242 1.1 mrg (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3243 1.1 mrg (set (match_dup 0) 3244 1.1 mrg (sign_extend:DI (minus:SI (ashift:SI (match_dup 6) (match_dup 3)) 3245 1.1 mrg (match_dup 4))))] 3246 1.1.1.2 mrg { 3247 1.1.1.2 mrg operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3]))); 3248 1.1.1.2 mrg if (can_create_pseudo_p ()) 3249 1.1.1.2 mrg operands[5] = gen_reg_rtx (DImode); 3250 1.1 mrg else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3251 1.1 mrg operands[5] = operands[0]; 3252 1.1.1.2 mrg 3253 1.1 mrg operands[6] = gen_lowpart (SImode, operands[5]); 3254 1.1 mrg }) 3255 1.1 mrg 3257 1.1 mrg ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF 3258 1.1 mrg ;; work differently, so we have different patterns for each. 3259 1.1 mrg 3260 1.1.1.2 mrg (define_expand "call" 3261 1.1.1.2 mrg [(use (match_operand:DI 0)) 3262 1.1 mrg (use (match_operand 1)) 3263 1.1 mrg (use (match_operand 2)) 3264 1.1 mrg (use (match_operand 3))] 3265 1.1 mrg "" 3266 1.1 mrg { 3267 1.1 mrg if (TARGET_ABI_OPEN_VMS) 3268 1.1 mrg emit_call_insn (gen_call_vms (operands[0], operands[2])); 3269 1.1 mrg else 3270 1.1.1.2 mrg emit_call_insn (gen_call_osf (operands[0], operands[1])); 3271 1.1.1.2 mrg DONE; 3272 1.1 mrg }) 3273 1.1 mrg 3274 1.1 mrg (define_expand "sibcall" 3275 1.1 mrg [(parallel [(call (mem:DI (match_operand 0)) 3276 1.1 mrg (match_operand 1)) 3277 1.1 mrg (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])] 3278 1.1 mrg "TARGET_ABI_OSF" 3279 1.1 mrg { 3280 1.1 mrg gcc_assert (MEM_P (operands[0])); 3281 1.1 mrg operands[0] = XEXP (operands[0], 0); 3282 1.1 mrg }) 3283 1.1 mrg 3284 1.1 mrg (define_expand "call_osf" 3285 1.1 mrg [(parallel [(call (mem:DI (match_operand 0)) 3286 1.1 mrg (match_operand 1)) 3287 1.1 mrg (use (reg:DI 29)) 3288 1.1 mrg (clobber (reg:DI 26))])] 3289 1.1.1.2 mrg "" 3290 1.1.1.2 mrg { 3291 1.1 mrg gcc_assert (MEM_P (operands[0])); 3292 1.1 mrg 3293 1.1 mrg operands[0] = XEXP (operands[0], 0); 3294 1.1 mrg if (! call_operand (operands[0], Pmode)) 3295 1.1 mrg operands[0] = copy_to_mode_reg (Pmode, operands[0]); 3296 1.1 mrg }) 3297 1.1 mrg 3298 1.1 mrg ;; 3299 1.1 mrg ;; call openvms/alpha 3300 1.1 mrg ;; op 0: symbol ref for called function 3301 1.1 mrg ;; op 1: next_arg_reg (argument information value for R25) 3302 1.1 mrg ;; 3303 1.1 mrg (define_expand "call_vms" 3304 1.1 mrg [(parallel [(call (mem:DI (match_operand 0)) 3305 1.1 mrg (match_operand 1)) 3306 1.1 mrg (use (match_dup 2)) 3307 1.1 mrg (use (reg:DI 25)) 3308 1.1 mrg (use (reg:DI 26)) 3309 1.1 mrg (clobber (reg:DI 27))])] 3310 1.1 mrg "" 3311 1.1 mrg { 3312 1.1 mrg gcc_assert (MEM_P (operands[0])); 3313 1.1.1.2 mrg 3314 1.1.1.2 mrg operands[0] = XEXP (operands[0], 0); 3315 1.1 mrg 3316 1.1 mrg /* Always load AI with argument information, then handle symbolic and 3317 1.1 mrg indirect call differently. Load RA and set operands[2] to PV in 3318 1.1 mrg both cases. */ 3319 1.1 mrg 3320 1.1.1.2 mrg emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]); 3321 1.1.1.2 mrg if (GET_CODE (operands[0]) == SYMBOL_REF) 3322 1.1.1.2 mrg { 3323 1.1.1.2 mrg operands[2] = const0_rtx; 3324 1.1.1.2 mrg } 3325 1.1 mrg else 3326 1.1 mrg { 3327 1.1.1.2 mrg emit_move_insn (gen_rtx_REG (Pmode, 26), 3328 1.1 mrg gen_rtx_MEM (Pmode, plus_constant (Pmode, 3329 1.1 mrg operands[0], 8))); 3330 1.1 mrg operands[2] = operands[0]; 3331 1.1 mrg } 3332 1.1 mrg }) 3333 1.1 mrg 3334 1.1 mrg (define_expand "call_value" 3335 1.1 mrg [(use (match_operand 0)) 3336 1.1 mrg (use (match_operand:DI 1)) 3337 1.1.1.2 mrg (use (match_operand 2)) 3338 1.1.1.2 mrg (use (match_operand 3)) 3339 1.1.1.2 mrg (use (match_operand 4))] 3340 1.1 mrg "" 3341 1.1 mrg { 3342 1.1 mrg if (TARGET_ABI_OPEN_VMS) 3343 1.1 mrg emit_call_insn (gen_call_value_vms (operands[0], operands[1], 3344 1.1 mrg operands[3])); 3345 1.1 mrg else 3346 1.1 mrg emit_call_insn (gen_call_value_osf (operands[0], operands[1], 3347 1.1 mrg operands[2])); 3348 1.1.1.2 mrg DONE; 3349 1.1.1.2 mrg }) 3350 1.1.1.2 mrg 3351 1.1 mrg (define_expand "sibcall_value" 3352 1.1 mrg [(parallel [(set (match_operand 0) 3353 1.1 mrg (call (mem:DI (match_operand 1)) 3354 1.1 mrg (match_operand 2))) 3355 1.1 mrg (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])] 3356 1.1 mrg "TARGET_ABI_OSF" 3357 1.1 mrg { 3358 1.1 mrg gcc_assert (MEM_P (operands[1])); 3359 1.1 mrg operands[1] = XEXP (operands[1], 0); 3360 1.1 mrg }) 3361 1.1 mrg 3362 1.1 mrg (define_expand "call_value_osf" 3363 1.1.1.2 mrg [(parallel [(set (match_operand 0) 3364 1.1.1.2 mrg (call (mem:DI (match_operand 1)) 3365 1.1.1.2 mrg (match_operand 2))) 3366 1.1 mrg (use (reg:DI 29)) 3367 1.1 mrg (clobber (reg:DI 26))])] 3368 1.1 mrg "" 3369 1.1 mrg { 3370 1.1 mrg gcc_assert (MEM_P (operands[1])); 3371 1.1 mrg 3372 1.1 mrg operands[1] = XEXP (operands[1], 0); 3373 1.1 mrg if (! call_operand (operands[1], Pmode)) 3374 1.1 mrg operands[1] = copy_to_mode_reg (Pmode, operands[1]); 3375 1.1 mrg }) 3376 1.1 mrg 3377 1.1 mrg (define_expand "call_value_vms" 3378 1.1 mrg [(parallel [(set (match_operand 0) 3379 1.1 mrg (call (mem:DI (match_operand:DI 1)) 3380 1.1 mrg (match_operand 2))) 3381 1.1 mrg (use (match_dup 3)) 3382 1.1 mrg (use (reg:DI 25)) 3383 1.1 mrg (use (reg:DI 26)) 3384 1.1 mrg (clobber (reg:DI 27))])] 3385 1.1 mrg "" 3386 1.1 mrg { 3387 1.1 mrg gcc_assert (MEM_P (operands[1])); 3388 1.1.1.2 mrg 3389 1.1.1.2 mrg operands[1] = XEXP (operands[1], 0); 3390 1.1 mrg 3391 1.1 mrg /* Always load AI with argument information, then handle symbolic and 3392 1.1 mrg indirect call differently. Load RA and set operands[3] to PV in 3393 1.1 mrg both cases. */ 3394 1.1 mrg 3395 1.1 mrg emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]); 3396 1.1.1.2 mrg if (GET_CODE (operands[1]) == SYMBOL_REF) 3397 1.1 mrg { 3398 1.1 mrg operands[3] = const0_rtx; 3399 1.1 mrg } 3400 1.1 mrg else 3401 1.1 mrg { 3402 1.1 mrg emit_move_insn (gen_rtx_REG (Pmode, 26), 3403 1.1 mrg gen_rtx_MEM (Pmode, plus_constant (Pmode, 3404 1.1 mrg operands[1], 8))); 3405 1.1 mrg operands[3] = operands[1]; 3406 1.1 mrg } 3407 1.1 mrg }) 3408 1.1 mrg 3409 1.1 mrg (define_insn "*call_osf_1_er_noreturn" 3410 1.1.1.2 mrg [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) 3411 1.1 mrg (match_operand 1)) 3412 1.1 mrg (use (reg:DI 29)) 3413 1.1 mrg (clobber (reg:DI 26))] 3414 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF 3415 1.1 mrg && find_reg_note (insn, REG_NORETURN, NULL_RTX)" 3416 1.1 mrg "@ 3417 1.1 mrg jsr $26,($27),0 3418 1.1 mrg bsr $26,%0\t\t!samegp 3419 1.1 mrg ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#" 3420 1.1 mrg [(set_attr "type" "jsr") 3421 1.1 mrg (set_attr "length" "*,*,8")]) 3422 1.1 mrg 3423 1.1 mrg (define_insn "*call_osf_1_er" 3424 1.1.1.2 mrg [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) 3425 1.1.1.2 mrg (match_operand 1)) 3426 1.1 mrg (use (reg:DI 29)) 3427 1.1 mrg (clobber (reg:DI 26))] 3428 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3429 1.1 mrg "@ 3430 1.1 mrg jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%* 3431 1.1 mrg bsr $26,%0\t\t!samegp 3432 1.1 mrg ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*" 3433 1.1 mrg [(set_attr "type" "jsr") 3434 1.1 mrg (set_attr "length" "12,*,16")]) 3435 1.1 mrg 3436 1.1 mrg ;; We must use peep2 instead of a split because we need accurate life 3437 1.1 mrg ;; information for $gp. Consider the case of { bar(); while (1); }. 3438 1.1 mrg (define_peephole2 3439 1.1 mrg [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand")) 3440 1.1 mrg (match_operand 1)) 3441 1.1 mrg (use (reg:DI 29)) 3442 1.1 mrg (clobber (reg:DI 26))])] 3443 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed 3444 1.1 mrg && ! samegp_function_operand (operands[0], Pmode) 3445 1.1 mrg && (peep2_regno_dead_p (1, 29) 3446 1.1 mrg || find_reg_note (insn, REG_NORETURN, NULL_RTX))" 3447 1.1 mrg [(parallel [(call (mem:DI (match_dup 2)) 3448 1.1 mrg (match_dup 1)) 3449 1.1 mrg (use (reg:DI 29)) 3450 1.1 mrg (use (match_dup 0)) 3451 1.1 mrg (use (match_dup 3)) 3452 1.1 mrg (clobber (reg:DI 26))])] 3453 1.1 mrg { 3454 1.1 mrg if (CONSTANT_P (operands[0])) 3455 1.1.1.2 mrg { 3456 1.1.1.2 mrg operands[2] = gen_rtx_REG (Pmode, 27); 3457 1.1 mrg operands[3] = GEN_INT (alpha_next_sequence_number++); 3458 1.1 mrg emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx, 3459 1.1 mrg operands[0], operands[3])); 3460 1.1 mrg } 3461 1.1 mrg else 3462 1.1 mrg { 3463 1.1 mrg operands[2] = operands[0]; 3464 1.1 mrg operands[0] = const0_rtx; 3465 1.1 mrg operands[3] = const0_rtx; 3466 1.1 mrg } 3467 1.1 mrg }) 3468 1.1 mrg 3469 1.1 mrg (define_peephole2 3470 1.1 mrg [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand")) 3471 1.1 mrg (match_operand 1)) 3472 1.1 mrg (use (reg:DI 29)) 3473 1.1 mrg (clobber (reg:DI 26))])] 3474 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed 3475 1.1 mrg && ! samegp_function_operand (operands[0], Pmode) 3476 1.1 mrg && ! (peep2_regno_dead_p (1, 29) 3477 1.1 mrg || find_reg_note (insn, REG_NORETURN, NULL_RTX))" 3478 1.1 mrg [(parallel [(call (mem:DI (match_dup 2)) 3479 1.1 mrg (match_dup 1)) 3480 1.1 mrg (set (match_dup 5) 3481 1.1 mrg (unspec:DI [(match_dup 5) (match_dup 3)] UNSPEC_LDGP1)) 3482 1.1 mrg (use (match_dup 0)) 3483 1.1 mrg (use (match_dup 4)) 3484 1.1 mrg (clobber (reg:DI 26))]) 3485 1.1 mrg (set (match_dup 5) 3486 1.1 mrg (unspec:DI [(match_dup 5) (match_dup 3)] UNSPEC_LDGP2))] 3487 1.1 mrg { 3488 1.1 mrg if (CONSTANT_P (operands[0])) 3489 1.1 mrg { 3490 1.1 mrg operands[2] = gen_rtx_REG (Pmode, 27); 3491 1.1 mrg operands[4] = GEN_INT (alpha_next_sequence_number++); 3492 1.1.1.2 mrg emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx, 3493 1.1 mrg operands[0], operands[4])); 3494 1.1.1.2 mrg } 3495 1.1.1.2 mrg else 3496 1.1 mrg { 3497 1.1 mrg operands[2] = operands[0]; 3498 1.1 mrg operands[0] = const0_rtx; 3499 1.1 mrg operands[4] = const0_rtx; 3500 1.1 mrg } 3501 1.1 mrg operands[3] = GEN_INT (alpha_next_sequence_number++); 3502 1.1 mrg operands[5] = pic_offset_table_rtx; 3503 1.1.1.2 mrg }) 3504 1.1 mrg 3505 1.1.1.2 mrg (define_insn "*call_osf_2_er_nogp" 3506 1.1 mrg [(call (mem:DI (match_operand:DI 0 "register_operand" "c")) 3507 1.1.1.2 mrg (match_operand 1)) 3508 1.1.1.2 mrg (use (reg:DI 29)) 3509 1.1 mrg (use (match_operand 2)) 3510 1.1 mrg (use (match_operand 3 "const_int_operand")) 3511 1.1 mrg (clobber (reg:DI 26))] 3512 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3513 1.1 mrg "jsr $26,(%0),%2%J3" 3514 1.1 mrg [(set_attr "type" "jsr")]) 3515 1.1 mrg 3516 1.1 mrg (define_insn "*call_osf_2_er" 3517 1.1 mrg [(call (mem:DI (match_operand:DI 0 "register_operand" "c")) 3518 1.1.1.2 mrg (match_operand 1)) 3519 1.1 mrg (set (reg:DI 29) 3520 1.1 mrg (unspec:DI [(reg:DI 29) (match_operand 4 "const_int_operand")] 3521 1.1 mrg UNSPEC_LDGP1)) 3522 1.1 mrg (use (match_operand 2)) 3523 1.1 mrg (use (match_operand 3 "const_int_operand")) 3524 1.1 mrg (clobber (reg:DI 26))] 3525 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3526 1.1 mrg "jsr $26,(%0),%2%J3\;ldah $29,0($26)\t\t!gpdisp!%4" 3527 1.1 mrg [(set_attr "type" "jsr") 3528 1.1 mrg (set_attr "cannot_copy" "true") 3529 1.1 mrg (set_attr "length" "8")]) 3530 1.1 mrg 3531 1.1 mrg (define_insn "*call_osf_1_noreturn" 3532 1.1.1.2 mrg [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) 3533 1.1 mrg (match_operand 1)) 3534 1.1 mrg (use (reg:DI 29)) 3535 1.1 mrg (clobber (reg:DI 26))] 3536 1.1 mrg "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF 3537 1.1 mrg && find_reg_note (insn, REG_NORETURN, NULL_RTX)" 3538 1.1 mrg "@ 3539 1.1 mrg jsr $26,($27),0 3540 1.1 mrg bsr $26,$%0..ng 3541 1.1 mrg jsr $26,%0" 3542 1.1 mrg [(set_attr "type" "jsr") 3543 1.1 mrg (set_attr "length" "*,*,8")]) 3544 1.1 mrg 3545 1.1.1.2 mrg (define_insn "*call_osf_1" 3546 1.1 mrg [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) 3547 1.1 mrg (match_operand 1)) 3548 1.1 mrg (use (reg:DI 29)) 3549 1.1 mrg (clobber (reg:DI 26))] 3550 1.1 mrg "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3551 1.1 mrg "@ 3552 1.1 mrg jsr $26,($27),0\;ldgp $29,0($26) 3553 1.1 mrg bsr $26,$%0..ng 3554 1.1 mrg jsr $26,%0\;ldgp $29,0($26)" 3555 1.1 mrg [(set_attr "type" "jsr") 3556 1.1 mrg (set_attr "length" "12,*,16")]) 3557 1.1 mrg 3558 1.1.1.2 mrg (define_insn "*sibcall_osf_1_er" 3559 1.1 mrg [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s")) 3560 1.1 mrg (match_operand 1)) 3561 1.1 mrg (unspec [(reg:DI 29)] UNSPEC_SIBCALL)] 3562 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3563 1.1 mrg "@ 3564 1.1 mrg br $31,%0\t\t!samegp 3565 1.1 mrg ldq $27,%0($29)\t\t!literal!%#\;jmp $31,($27),%0\t\t!lituse_jsr!%#" 3566 1.1 mrg [(set_attr "type" "jsr") 3567 1.1 mrg (set_attr "length" "*,8")]) 3568 1.1 mrg 3569 1.1 mrg ;; Note that the DEC assembler expands "jmp foo" with $at, which 3570 1.1 mrg ;; doesn't do what we want. 3571 1.1 mrg (define_insn "*sibcall_osf_1" 3572 1.1.1.2 mrg [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s")) 3573 1.1 mrg (match_operand 1)) 3574 1.1 mrg (unspec [(reg:DI 29)] UNSPEC_SIBCALL)] 3575 1.1 mrg "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3576 1.1 mrg "@ 3577 1.1 mrg br $31,$%0..ng 3578 1.1 mrg lda $27,%0\;jmp $31,($27),%0" 3579 1.1 mrg [(set_attr "type" "jsr") 3580 1.1 mrg (set_attr "length" "*,8")]) 3581 1.1 mrg 3582 1.1 mrg ; GAS relies on the order and position of instructions output below in order 3583 1.1 mrg ; to generate relocs for VMS link to potentially optimize the call. 3584 1.1.1.2 mrg ; Please do not molest. 3585 1.1.1.2 mrg (define_insn "*call_vms_1" 3586 1.1 mrg [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s")) 3587 1.1 mrg (match_operand 1)) 3588 1.1 mrg (use (match_operand:DI 2 "nonmemory_operand" "r,n")) 3589 1.1 mrg (use (reg:DI 25)) 3590 1.1 mrg (use (reg:DI 26)) 3591 1.1 mrg (clobber (reg:DI 27))] 3592 1.1 mrg "TARGET_ABI_OPEN_VMS" 3593 1.1 mrg { 3594 1.1 mrg switch (which_alternative) 3595 1.1 mrg { 3596 1.1 mrg case 0: 3597 1.1.1.2 mrg return "mov %2,$27\;jsr $26,0\;ldq $27,0($29)"; 3598 1.1 mrg case 1: 3599 1.1.1.2 mrg operands [2] = alpha_use_linkage (operands [0], true, false); 3600 1.1.1.2 mrg operands [3] = alpha_use_linkage (operands [0], false, false); 3601 1.1 mrg return "ldq $26,%3\;ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"; 3602 1.1 mrg default: 3603 1.1 mrg gcc_unreachable (); 3604 1.1 mrg } 3605 1.1.1.4 mrg } 3606 1.1 mrg [(set_attr "type" "jsr") 3607 1.1 mrg (set_attr "length" "12,16")]) 3608 1.1 mrg 3609 1.1 mrg ;; Call subroutine returning any type. 3610 1.1 mrg 3611 1.1 mrg (define_expand "untyped_call" 3612 1.1 mrg [(parallel [(call (match_operand 0) 3613 1.1 mrg (const_int 0)) 3614 1.1 mrg (match_operand 1) 3615 1.1 mrg (match_operand 2)])] 3616 1.1 mrg "" 3617 1.1 mrg { 3618 1.1 mrg int i; 3619 1.1 mrg 3620 1.1 mrg emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); 3621 1.1 mrg 3622 1.1 mrg for (i = 0; i < XVECLEN (operands[2], 0); i++) 3623 1.1 mrg { 3624 1.1 mrg rtx set = XVECEXP (operands[2], 0, i); 3625 1.1 mrg emit_move_insn (SET_DEST (set), SET_SRC (set)); 3626 1.1 mrg } 3627 1.1 mrg 3628 1.1 mrg /* The optimizer does not know that the call sets the function value 3629 1.1 mrg registers we stored in the result block. We avoid problems by 3630 1.1 mrg claiming that all hard registers are used and clobbered at this 3631 1.1 mrg point. */ 3632 1.1 mrg emit_insn (gen_blockage ()); 3633 1.1 mrg 3634 1.1.1.2 mrg DONE; 3635 1.1 mrg }) 3636 1.1 mrg 3637 1.1 mrg ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 3638 1.1 mrg ;; all of memory. This blocks insns from being moved across this point. 3639 1.1 mrg 3640 1.1 mrg (define_insn "blockage" 3641 1.1.1.2 mrg [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] 3642 1.1 mrg "" 3643 1.1 mrg "" 3644 1.1 mrg [(set_attr "length" "0") 3645 1.1 mrg (set_attr "type" "none")]) 3646 1.1 mrg 3647 1.1 mrg (define_insn "jump" 3648 1.1 mrg [(set (pc) 3649 1.1 mrg (label_ref (match_operand 0)))] 3650 1.1 mrg "" 3651 1.1 mrg "br $31,%l0" 3652 1.1 mrg [(set_attr "type" "ibr")]) 3653 1.1 mrg 3654 1.1 mrg (define_expand "return" 3655 1.1 mrg [(return)] 3656 1.1 mrg "direct_return ()") 3657 1.1.1.2 mrg 3658 1.1.1.2 mrg (define_insn "*return_internal" 3659 1.1 mrg [(return)] 3660 1.1 mrg "reload_completed" 3661 1.1.1.2 mrg "ret $31,($26),1" 3662 1.1 mrg [(set_attr "type" "ibr")]) 3663 1.1 mrg 3664 1.1 mrg (define_insn "indirect_jump" 3665 1.1 mrg [(set (pc) (match_operand:DI 0 "register_operand" "r"))] 3666 1.1 mrg "" 3667 1.1 mrg "jmp $31,(%0),0" 3668 1.1 mrg [(set_attr "type" "ibr")]) 3669 1.1 mrg 3670 1.1 mrg (define_expand "tablejump" 3671 1.1 mrg [(parallel [(set (pc) 3672 1.1 mrg (match_operand 0 "register_operand")) 3673 1.1.1.2 mrg (use (label_ref:DI (match_operand 1)))])] 3674 1.1 mrg "" 3675 1.1 mrg { 3676 1.1 mrg if (TARGET_ABI_OSF) 3677 1.1 mrg { 3678 1.1 mrg rtx dest = gen_reg_rtx (DImode); 3679 1.1 mrg emit_insn (gen_extendsidi2 (dest, operands[0])); 3680 1.1 mrg emit_insn (gen_adddi3 (dest, pic_offset_table_rtx, dest)); 3681 1.1 mrg operands[0] = dest; 3682 1.1 mrg } 3683 1.1 mrg }) 3684 1.1 mrg 3685 1.1 mrg (define_insn "*tablejump_internal" 3686 1.1.1.2 mrg [(set (pc) 3687 1.1.1.2 mrg (match_operand:DI 0 "register_operand" "r")) 3688 1.1.1.2 mrg (use (label_ref (match_operand 1)))] 3689 1.1.1.2 mrg "" 3690 1.1.1.2 mrg "jmp $31,(%0),0" 3691 1.1.1.2 mrg [(set_attr "type" "ibr")]) 3692 1.1.1.2 mrg 3693 1.1.1.2 mrg ;; Cache flush. Used by alpha_trampoline_init. 0x86 is PAL_imb, but we don't 3694 1.1.1.2 mrg ;; want to have to include pal.h in our .s file. 3695 1.1 mrg (define_insn "imb" 3696 1.1 mrg [(unspec_volatile [(const_int 0)] UNSPECV_IMB)] 3697 1.1.1.3 mrg "" 3698 1.1.1.3 mrg "call_pal 0x86" 3699 1.1.1.2 mrg [(set_attr "type" "callpal")]) 3700 1.1 mrg 3701 1.1 mrg (define_expand "clear_cache" 3702 1.1 mrg [(match_operand:DI 0) ; region start 3703 1.1 mrg (match_operand:DI 1)] ; region end 3704 1.1 mrg "" 3705 1.1 mrg { 3706 1.1.1.2 mrg emit_insn (gen_imb ()); 3707 1.1 mrg DONE; 3708 1.1 mrg }) 3709 1.1 mrg 3710 1.1 mrg ;; BUGCHK is documented common to OSF/1 and VMS PALcode. 3711 1.1 mrg (define_insn "trap" 3712 1.1 mrg [(trap_if (const_int 1) (const_int 0)) 3713 1.1 mrg (use (reg:DI 29))] 3714 1.1 mrg "" 3715 1.1 mrg "call_pal 0x81" 3716 1.1 mrg [(set_attr "type" "callpal")]) 3717 1.1 mrg 3718 1.1 mrg ;; For userland, we load the thread pointer from the TCB. 3719 1.1 mrg ;; For the kernel, we load the per-cpu private value. 3720 1.1 mrg 3721 1.1 mrg (define_insn "get_thread_pointerdi" 3722 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=v") 3723 1.1.1.2 mrg (unspec:DI [(const_int 0)] UNSPEC_TP))] 3724 1.1.1.2 mrg "TARGET_ABI_OSF" 3725 1.1 mrg { 3726 1.1.1.2 mrg if (TARGET_TLS_KERNEL) 3727 1.1 mrg return "call_pal 0x32"; 3728 1.1 mrg else 3729 1.1 mrg return "call_pal 0x9e"; 3730 1.1 mrg } 3731 1.1 mrg [(set_attr "type" "callpal")]) 3732 1.1 mrg 3733 1.1 mrg ;; For completeness, and possibly a __builtin function, here's how to 3734 1.1 mrg ;; set the thread pointer. Since we don't describe enough of this 3735 1.1 mrg ;; quantity for CSE, we have to use a volatile unspec, and then there's 3736 1.1 mrg ;; not much point in creating an R16_REG register class. 3737 1.1 mrg 3738 1.1 mrg (define_expand "set_thread_pointerdi" 3739 1.1 mrg [(set (reg:DI 16) (match_operand:DI 0 "input_operand")) 3740 1.1 mrg (unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)] 3741 1.1 mrg "TARGET_ABI_OSF") 3742 1.1.1.2 mrg 3743 1.1.1.2 mrg (define_insn "*set_tp" 3744 1.1 mrg [(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)] 3745 1.1 mrg "TARGET_ABI_OSF" 3746 1.1 mrg { 3747 1.1 mrg if (TARGET_TLS_KERNEL) 3748 1.1 mrg return "call_pal 0x31"; 3749 1.1 mrg else 3750 1.1 mrg return "call_pal 0x9f"; 3751 1.1.1.2 mrg } 3752 1.1 mrg [(set_attr "type" "callpal")]) 3753 1.1.1.2 mrg 3754 1.1 mrg ;; Special builtins for establishing and reverting VMS condition handlers. 3755 1.1 mrg 3756 1.1 mrg (define_expand "builtin_establish_vms_condition_handler" 3757 1.1 mrg [(set (reg:DI 0) (match_operand:DI 0 "register_operand")) 3758 1.1 mrg (use (match_operand:DI 1 "address_operand"))] 3759 1.1.1.2 mrg "TARGET_ABI_OPEN_VMS" 3760 1.1.1.2 mrg { 3761 1.1.1.2 mrg alpha_expand_builtin_establish_vms_condition_handler (operands[0], 3762 1.1.1.2 mrg operands[1]); 3763 1.1.1.2 mrg }) 3764 1.1.1.2 mrg 3765 1.1.1.2 mrg (define_expand "builtin_revert_vms_condition_handler" 3766 1.1.1.2 mrg [(set (reg:DI 0) (match_operand:DI 0 "register_operand"))] 3767 1.1.1.2 mrg "TARGET_ABI_OPEN_VMS" 3768 1.1 mrg "alpha_expand_builtin_revert_vms_condition_handler (operands[0]);") 3769 1.1.1.2 mrg 3771 1.1 mrg ;; Finally, we have the basic data motion insns. The byte and word insns 3772 1.1.1.2 mrg ;; are done via define_expand. Start with the floating-point insns, since 3773 1.1.1.2 mrg ;; they are simpler. 3774 1.1 mrg 3775 1.1 mrg (define_expand "movsf" 3776 1.1 mrg [(set (match_operand:SF 0 "nonimmediate_operand") 3777 1.1 mrg (match_operand:SF 1 "general_operand"))] 3778 1.1 mrg "" 3779 1.1 mrg { 3780 1.1 mrg if (MEM_P (operands[0]) 3781 1.1 mrg && ! reg_or_0_operand (operands[1], SFmode)) 3782 1.1 mrg operands[1] = force_reg (SFmode, operands[1]); 3783 1.1.1.2 mrg }) 3784 1.1.1.2 mrg 3785 1.1 mrg (define_insn "*movsf" 3786 1.1.1.2 mrg [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r") 3787 1.1.1.2 mrg (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))] 3788 1.1.1.2 mrg "register_operand (operands[0], SFmode) 3789 1.1.1.2 mrg || reg_or_0_operand (operands[1], SFmode)" 3790 1.1.1.2 mrg "@ 3791 1.1.1.2 mrg cpys %R1,%R1,%0 3792 1.1.1.2 mrg ld%, %0,%1 3793 1.1.1.2 mrg bis $31,%r1,%0 3794 1.1.1.2 mrg ldl %0,%1 3795 1.1 mrg st%, %R1,%0 3796 1.1.1.2 mrg stl %r1,%0 3797 1.1 mrg itofs %1,%0 3798 1.1 mrg ftois %1,%0" 3799 1.1.1.2 mrg [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi") 3800 1.1.1.2 mrg (set_attr "isa" "*,*,*,*,*,*,fix,fix")]) 3801 1.1 mrg 3802 1.1 mrg (define_expand "movdf" 3803 1.1 mrg [(set (match_operand:DF 0 "nonimmediate_operand") 3804 1.1 mrg (match_operand:DF 1 "general_operand"))] 3805 1.1 mrg "" 3806 1.1 mrg { 3807 1.1 mrg if (MEM_P (operands[0]) 3808 1.1 mrg && ! reg_or_0_operand (operands[1], DFmode)) 3809 1.1 mrg operands[1] = force_reg (DFmode, operands[1]); 3810 1.1.1.2 mrg }) 3811 1.1.1.2 mrg 3812 1.1 mrg (define_insn "*movdf" 3813 1.1 mrg [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r") 3814 1.1 mrg (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))] 3815 1.1.1.2 mrg "register_operand (operands[0], DFmode) 3816 1.1.1.2 mrg || reg_or_0_operand (operands[1], DFmode)" 3817 1.1.1.2 mrg "@ 3818 1.1.1.2 mrg cpys %R1,%R1,%0 3819 1.1.1.2 mrg ld%- %0,%1 3820 1.1.1.2 mrg bis $31,%r1,%0 3821 1.1.1.2 mrg ldq %0,%1 3822 1.1.1.2 mrg st%- %R1,%0 3823 1.1.1.2 mrg stq %r1,%0 3824 1.1.1.2 mrg itoft %1,%0 3825 1.1.1.2 mrg ftoit %1,%0" 3826 1.1 mrg [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi") 3827 1.1.1.4 mrg (set_attr "isa" "*,*,*,*,*,*,fix,fix")]) 3828 1.1 mrg 3829 1.1 mrg ;; Subregs suck for register allocation. Pretend we can move TFmode 3830 1.1 mrg ;; data between general registers until after reload. 3831 1.1 mrg ;; ??? Is this still true now that we have the lower-subreg pass? 3832 1.1 mrg 3833 1.1 mrg (define_expand "movtf" 3834 1.1 mrg [(set (match_operand:TF 0 "nonimmediate_operand") 3835 1.1 mrg (match_operand:TF 1 "general_operand"))] 3836 1.1.1.2 mrg "" 3837 1.1 mrg { 3838 1.1.1.2 mrg if (MEM_P (operands[0]) 3839 1.1.1.2 mrg && ! reg_or_0_operand (operands[1], TFmode)) 3840 1.1 mrg operands[1] = force_reg (TFmode, operands[1]); 3841 1.1.1.2 mrg }) 3842 1.1.1.2 mrg 3843 1.1.1.2 mrg (define_insn_and_split "*movtf_internal" 3844 1.1 mrg [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o") 3845 1.1 mrg (match_operand:TF 1 "input_operand" "roG,rG"))] 3846 1.1.1.2 mrg "register_operand (operands[0], TFmode) 3847 1.1.1.2 mrg || reg_or_0_operand (operands[1], TFmode)" 3848 1.1 mrg "#" 3849 1.1 mrg "reload_completed" 3850 1.1 mrg [(set (match_dup 0) (match_dup 2)) 3851 1.1.1.2 mrg (set (match_dup 1) (match_dup 3))] 3852 1.1.1.2 mrg "alpha_split_tmode_pair (operands, TFmode, true);") 3853 1.1.1.2 mrg 3854 1.1.1.2 mrg ;; We do two major things here: handle mem->mem and construct long 3855 1.1 mrg ;; constants. 3856 1.1 mrg 3857 1.1 mrg (define_expand "movsi" 3858 1.1 mrg [(set (match_operand:SI 0 "nonimmediate_operand") 3859 1.1 mrg (match_operand:SI 1 "general_operand"))] 3860 1.1 mrg "" 3861 1.1.1.2 mrg { 3862 1.1.1.2 mrg if (alpha_expand_mov (SImode, operands)) 3863 1.1.1.2 mrg DONE; 3864 1.1.1.2 mrg }) 3865 1.1 mrg 3866 1.1 mrg (define_insn "*movsi" 3867 1.1 mrg [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,r") 3868 1.1 mrg (match_operand:SI 1 "input_operand" "rJ,K,L,n,m,rJ,s"))] 3869 1.1 mrg "register_operand (operands[0], SImode) 3870 1.1.1.2 mrg || reg_or_0_operand (operands[1], SImode)" 3871 1.1.1.2 mrg "@ 3872 1.1 mrg bis $31,%r1,%0 3873 1.1 mrg lda %0,%1($31) 3874 1.1 mrg ldah %0,%h1($31) 3875 1.1 mrg # 3876 1.1 mrg ldl %0,%1 3877 1.1 mrg stl %r1,%0 3878 1.1 mrg lda %0,%1" 3879 1.1 mrg [(set_attr "type" "ilog,iadd,iadd,multi,ild,ist,ldsym") 3880 1.1 mrg (set_attr "isa" "*,*,*,*,*,*,vms")]) 3881 1.1 mrg 3882 1.1 mrg ;; Split a load of a large constant into the appropriate two-insn 3883 1.1 mrg ;; sequence. 3884 1.1.1.2 mrg 3885 1.1 mrg (define_split 3886 1.1 mrg [(set (match_operand:SI 0 "register_operand") 3887 1.1 mrg (match_operand:SI 1 "non_add_const_operand"))] 3888 1.1 mrg "" 3889 1.1 mrg [(const_int 0)] 3890 1.1 mrg { 3891 1.1 mrg if (alpha_split_const_mov (SImode, operands)) 3892 1.1 mrg DONE; 3893 1.1 mrg else 3894 1.1 mrg FAIL; 3895 1.1.1.2 mrg }) 3896 1.1.1.2 mrg 3897 1.1 mrg (define_insn "*movdi_er_low_l" 3898 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 3899 1.1 mrg (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 3900 1.1 mrg (match_operand:DI 2 "local_symbolic_operand")))] 3901 1.1 mrg "TARGET_EXPLICIT_RELOCS" 3902 1.1 mrg { 3903 1.1.1.2 mrg if (true_regnum (operands[1]) == 29) 3904 1.1.1.2 mrg return "lda %0,%2(%1)\t\t!gprel"; 3905 1.1 mrg else 3906 1.1 mrg return "lda %0,%2(%1)\t\t!gprellow"; 3907 1.1 mrg } 3908 1.1 mrg [(set_attr "usegp" "yes")]) 3909 1.1 mrg 3910 1.1 mrg (define_split 3911 1.1 mrg [(set (match_operand:DI 0 "register_operand") 3912 1.1 mrg (match_operand:DI 1 "small_symbolic_operand"))] 3913 1.1.1.2 mrg "TARGET_EXPLICIT_RELOCS && reload_completed" 3914 1.1 mrg [(set (match_dup 0) 3915 1.1 mrg (lo_sum:DI (match_dup 2) (match_dup 1)))] 3916 1.1 mrg "operands[2] = pic_offset_table_rtx;") 3917 1.1 mrg 3918 1.1 mrg (define_split 3919 1.1 mrg [(set (match_operand:DI 0 "register_operand") 3920 1.1 mrg (match_operand:DI 1 "local_symbolic_operand"))] 3921 1.1 mrg "TARGET_EXPLICIT_RELOCS && reload_completed" 3922 1.1 mrg [(set (match_dup 0) 3923 1.1.1.2 mrg (plus:DI (match_dup 2) (high:DI (match_dup 1)))) 3924 1.1.1.2 mrg (set (match_dup 0) 3925 1.1 mrg (lo_sum:DI (match_dup 0) (match_dup 1)))] 3926 1.1 mrg "operands[2] = pic_offset_table_rtx;") 3927 1.1 mrg 3928 1.1 mrg (define_split 3929 1.1 mrg [(match_operand 0 "some_small_symbolic_operand")] 3930 1.1 mrg "" 3931 1.1 mrg [(match_dup 0)] 3932 1.1 mrg "operands[0] = split_small_symbolic_operand (operands[0]);") 3933 1.1 mrg 3934 1.1 mrg ;; Accepts any symbolic, not just global, since function calls that 3935 1.1 mrg ;; don't go via bsr still use !literal in hopes of linker relaxation. 3936 1.1.1.2 mrg (define_insn "movdi_er_high_g" 3937 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand" "=r") 3938 1.1 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "r") 3939 1.1 mrg (match_operand:DI 2 "symbolic_operand") 3940 1.1 mrg (match_operand 3 "const_int_operand")] 3941 1.1 mrg UNSPEC_LITERAL))] 3942 1.1 mrg "TARGET_EXPLICIT_RELOCS" 3943 1.1 mrg { 3944 1.1 mrg if (INTVAL (operands[3]) == 0) 3945 1.1 mrg return "ldq %0,%2(%1)\t\t!literal"; 3946 1.1 mrg else 3947 1.1 mrg return "ldq %0,%2(%1)\t\t!literal!%3"; 3948 1.1.1.2 mrg } 3949 1.1.1.2 mrg [(set_attr "type" "ldsym")]) 3950 1.1 mrg 3951 1.1 mrg (define_split 3952 1.1 mrg [(set (match_operand:DI 0 "register_operand") 3953 1.1 mrg (match_operand:DI 1 "global_symbolic_operand"))] 3954 1.1 mrg "TARGET_EXPLICIT_RELOCS && reload_completed" 3955 1.1 mrg [(set (match_dup 0) 3956 1.1 mrg (unspec:DI [(match_dup 2) 3957 1.1 mrg (match_dup 1) 3958 1.1 mrg (const_int 0)] UNSPEC_LITERAL))] 3959 1.1 mrg "operands[2] = pic_offset_table_rtx;") 3960 1.1 mrg 3961 1.1 mrg (define_insn "movdi_er_tlsgd" 3962 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand" "=r") 3963 1.1 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "r") 3964 1.1 mrg (match_operand:DI 2 "symbolic_operand") 3965 1.1 mrg (match_operand 3 "const_int_operand")] 3966 1.1 mrg UNSPEC_TLSGD))] 3967 1.1 mrg "HAVE_AS_TLS" 3968 1.1 mrg { 3969 1.1 mrg if (INTVAL (operands[3]) == 0) 3970 1.1 mrg return "lda %0,%2(%1)\t\t!tlsgd"; 3971 1.1 mrg else 3972 1.1 mrg return "lda %0,%2(%1)\t\t!tlsgd!%3"; 3973 1.1 mrg }) 3974 1.1 mrg 3975 1.1.1.2 mrg (define_insn "movdi_er_tlsldm" 3976 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 3977 1.1 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "r") 3978 1.1 mrg (match_operand 2 "const_int_operand")] 3979 1.1 mrg UNSPEC_TLSLDM))] 3980 1.1 mrg "HAVE_AS_TLS" 3981 1.1 mrg { 3982 1.1 mrg if (INTVAL (operands[2]) == 0) 3983 1.1.1.2 mrg return "lda %0,%&(%1)\t\t!tlsldm"; 3984 1.1.1.2 mrg else 3985 1.1 mrg return "lda %0,%&(%1)\t\t!tlsldm!%2"; 3986 1.1 mrg }) 3987 1.1 mrg 3988 1.1 mrg (define_insn "*movdi_er_gotdtp" 3989 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 3990 1.1 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "r") 3991 1.1 mrg (match_operand:DI 2 "symbolic_operand")] 3992 1.1 mrg UNSPEC_DTPREL))] 3993 1.1 mrg "HAVE_AS_TLS" 3994 1.1 mrg "ldq %0,%2(%1)\t\t!gotdtprel" 3995 1.1 mrg [(set_attr "type" "ild") 3996 1.1 mrg (set_attr "usegp" "yes")]) 3997 1.1.1.2 mrg 3998 1.1 mrg (define_split 3999 1.1 mrg [(set (match_operand:DI 0 "register_operand") 4000 1.1 mrg (match_operand:DI 1 "gotdtp_symbolic_operand"))] 4001 1.1 mrg "HAVE_AS_TLS && reload_completed" 4002 1.1 mrg [(set (match_dup 0) 4003 1.1 mrg (unspec:DI [(match_dup 2) 4004 1.1 mrg (match_dup 1)] UNSPEC_DTPREL))] 4005 1.1.1.2 mrg { 4006 1.1.1.2 mrg operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0); 4007 1.1 mrg operands[2] = pic_offset_table_rtx; 4008 1.1 mrg }) 4009 1.1 mrg 4010 1.1 mrg (define_insn "*movdi_er_gottp" 4011 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 4012 1.1 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "r") 4013 1.1 mrg (match_operand:DI 2 "symbolic_operand")] 4014 1.1 mrg UNSPEC_TPREL))] 4015 1.1 mrg "HAVE_AS_TLS" 4016 1.1.1.2 mrg "ldq %0,%2(%1)\t\t!gottprel" 4017 1.1 mrg [(set_attr "type" "ild") 4018 1.1.1.2 mrg (set_attr "usegp" "yes")]) 4019 1.1 mrg 4020 1.1.1.2 mrg (define_split 4021 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand") 4022 1.1.1.2 mrg (match_operand:DI 1 "gottp_symbolic_operand"))] 4023 1.1 mrg "HAVE_AS_TLS && reload_completed" 4024 1.1 mrg [(set (match_dup 0) 4025 1.1 mrg (unspec:DI [(match_dup 2) 4026 1.1 mrg (match_dup 1)] UNSPEC_TPREL))] 4027 1.1 mrg { 4028 1.1 mrg operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0); 4029 1.1 mrg operands[2] = pic_offset_table_rtx; 4030 1.1 mrg }) 4031 1.1 mrg 4032 1.1 mrg (define_insn "*movdi" 4033 1.1.1.2 mrg [(set (match_operand:DI 0 "nonimmediate_operand" 4034 1.1 mrg "=r,r,r,r,r,r,r,r, m, *f,*f, Q, r,*f") 4035 1.1 mrg (match_operand:DI 1 "input_operand" 4036 1.1 mrg "rJ,K,L,T,s,n,s,m,rJ,*fJ, Q,*f,*f, r"))] 4037 1.1 mrg "register_operand (operands[0], DImode) 4038 1.1.1.2 mrg || reg_or_0_operand (operands[1], DImode)" 4039 1.1.1.2 mrg "@ 4040 1.1.1.2 mrg mov %r1,%0 4041 1.1 mrg lda %0,%1($31) 4042 1.1 mrg ldah %0,%h1($31) 4043 1.1 mrg # 4044 1.1 mrg # 4045 1.1 mrg # 4046 1.1 mrg lda %0,%1 4047 1.1 mrg ldq%A1 %0,%1 4048 1.1 mrg stq%A0 %r1,%0 4049 1.1 mrg fmov %R1,%0 4050 1.1 mrg ldt %0,%1 4051 1.1 mrg stt %R1,%0 4052 1.1 mrg ftoit %1,%0 4053 1.1 mrg itoft %1,%0" 4054 1.1 mrg [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,multi,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof") 4055 1.1 mrg (set_attr "isa" "*,*,*,er,er,*,ner,*,*,*,*,*,fix,fix") 4056 1.1 mrg (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*,*,*,*")]) 4057 1.1 mrg 4058 1.1.1.2 mrg ;; VMS needs to set up "vms_base_regno" for unwinding. This move 4059 1.1.1.2 mrg ;; often appears dead to the life analysis code, at which point we 4060 1.1 mrg ;; die for emitting dead prologue instructions. Force this live. 4061 1.1 mrg 4062 1.1 mrg (define_insn "force_movdi" 4063 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 4064 1.1 mrg (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")] 4065 1.1 mrg UNSPECV_FORCE_MOV))] 4066 1.1 mrg "" 4067 1.1 mrg "mov %1,%0" 4068 1.1 mrg [(set_attr "type" "ilog")]) 4069 1.1 mrg 4070 1.1.1.2 mrg ;; We do three major things here: handle mem->mem, put 64-bit constants in 4071 1.1.1.2 mrg ;; memory, and construct long 32-bit constants. 4072 1.1 mrg 4073 1.1 mrg (define_expand "movdi" 4074 1.1 mrg [(set (match_operand:DI 0 "nonimmediate_operand") 4075 1.1 mrg (match_operand:DI 1 "general_operand"))] 4076 1.1 mrg "" 4077 1.1 mrg { 4078 1.1 mrg if (alpha_expand_mov (DImode, operands)) 4079 1.1 mrg DONE; 4080 1.1 mrg }) 4081 1.1 mrg 4082 1.1 mrg ;; Split a load of a large constant into the appropriate two-insn 4083 1.1 mrg ;; sequence. 4084 1.1 mrg 4085 1.1 mrg (define_split 4086 1.1 mrg [(set (match_operand:DI 0 "register_operand") 4087 1.1 mrg (match_operand:DI 1 "non_add_const_operand"))] 4088 1.1 mrg "" 4089 1.1 mrg [(const_int 0)] 4090 1.1 mrg { 4091 1.1 mrg if (alpha_split_const_mov (DImode, operands)) 4092 1.1 mrg DONE; 4093 1.1 mrg else 4094 1.1 mrg FAIL; 4095 1.1 mrg }) 4096 1.1 mrg 4097 1.1.1.2 mrg ;; We need to prevent reload from splitting TImode moves, because it 4098 1.1 mrg ;; might decide to overwrite a pointer with the value it points to. 4099 1.1 mrg ;; In that case we have to do the loads in the appropriate order so 4100 1.1.1.2 mrg ;; that the pointer is not destroyed too early. 4101 1.1.1.2 mrg 4102 1.1 mrg (define_insn_and_split "*movti_internal" 4103 1.1 mrg [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o") 4104 1.1 mrg (match_operand:TI 1 "input_operand" "roJ,rJ"))] 4105 1.1 mrg "(register_operand (operands[0], TImode) 4106 1.1 mrg /* Prevent rematerialization of constants. */ 4107 1.1 mrg && ! CONSTANT_P (operands[1])) 4108 1.1 mrg || reg_or_0_operand (operands[1], TImode)" 4109 1.1 mrg "#" 4110 1.1 mrg "reload_completed" 4111 1.1 mrg [(set (match_dup 0) (match_dup 2)) 4112 1.1 mrg (set (match_dup 1) (match_dup 3))] 4113 1.1.1.4 mrg "alpha_split_tmode_pair (operands, TImode, true);") 4114 1.1 mrg 4115 1.1 mrg (define_expand "movti" 4116 1.1 mrg [(set (match_operand:TI 0 "nonimmediate_operand") 4117 1.1 mrg (match_operand:TI 1 "general_operand"))] 4118 1.1 mrg "" 4119 1.1 mrg { 4120 1.1 mrg if (MEM_P (operands[0]) 4121 1.1 mrg && ! reg_or_0_operand (operands[1], TImode)) 4122 1.1 mrg operands[1] = force_reg (TImode, operands[1]); 4123 1.1 mrg 4124 1.1 mrg if (operands[1] == const0_rtx) 4125 1.1 mrg ; 4126 1.1 mrg /* We must put 64-bit constants in memory. We could keep the 4127 1.1 mrg 32-bit constants in TImode and rely on the splitter, but 4128 1.1 mrg this doesn't seem to be worth the pain. */ 4129 1.1 mrg else if (CONST_SCALAR_INT_P (operands[1])) 4130 1.1 mrg { 4131 1.1 mrg rtx in[2], out[2], target; 4132 1.1 mrg 4133 1.1 mrg gcc_assert (can_create_pseudo_p ()); 4134 1.1 mrg 4135 1.1 mrg split_double (operands[1], &in[0], &in[1]); 4136 1.1 mrg 4137 1.1 mrg if (in[0] == const0_rtx) 4138 1.1 mrg out[0] = const0_rtx; 4139 1.1 mrg else 4140 1.1 mrg { 4141 1.1 mrg out[0] = gen_reg_rtx (DImode); 4142 1.1 mrg emit_insn (gen_movdi (out[0], in[0])); 4143 1.1 mrg } 4144 1.1 mrg 4145 1.1 mrg if (in[1] == const0_rtx) 4146 1.1.1.4 mrg out[1] = const0_rtx; 4147 1.1 mrg else 4148 1.1 mrg { 4149 1.1 mrg out[1] = gen_reg_rtx (DImode); 4150 1.1 mrg emit_insn (gen_movdi (out[1], in[1])); 4151 1.1 mrg } 4152 1.1 mrg 4153 1.1 mrg if (!REG_P (operands[0])) 4154 1.1 mrg target = gen_reg_rtx (TImode); 4155 1.1 mrg else 4156 1.1 mrg target = operands[0]; 4157 1.1 mrg 4158 1.1 mrg emit_insn (gen_movdi (operand_subword (target, 0, 0, TImode), out[0])); 4159 1.1 mrg emit_insn (gen_movdi (operand_subword (target, 1, 0, TImode), out[1])); 4160 1.1 mrg 4161 1.1 mrg if (target != operands[0]) 4162 1.1.1.2 mrg emit_insn (gen_rtx_SET (operands[0], target)); 4163 1.1.1.2 mrg 4164 1.1.1.2 mrg DONE; 4165 1.1 mrg } 4166 1.1 mrg }) 4167 1.1.1.2 mrg 4168 1.1 mrg ;; These are the partial-word cases. 4169 1.1 mrg ;; 4170 1.1.1.2 mrg ;; First we have the code to load an aligned word. Operand 0 is the register 4171 1.1.1.2 mrg ;; in which to place the result. It's mode is QImode or HImode. Operand 1 4172 1.1.1.2 mrg ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the 4173 1.1 mrg ;; number of bits within the word that the value is. Operand 3 is an SImode 4174 1.1 mrg ;; scratch register. If operand 0 is a hard register, operand 3 may be the 4175 1.1.1.2 mrg ;; same register. It is allowed to conflict with operand 1 as well. 4176 1.1 mrg 4177 1.1 mrg (define_expand "aligned_loadqi" 4178 1.1 mrg [(set (match_operand:SI 3 "register_operand") 4179 1.1 mrg (match_operand:SI 1 "memory_operand")) 4180 1.1 mrg (set (match_operand:DI 0 "register_operand") 4181 1.1 mrg (zero_extract:DI (subreg:DI (match_dup 3) 0) 4182 1.1 mrg (const_int 8) 4183 1.1 mrg (match_operand:DI 2 "const_int_operand")))]) 4184 1.1 mrg 4185 1.1.1.2 mrg (define_expand "aligned_loadhi" 4186 1.1.1.2 mrg [(set (match_operand:SI 3 "register_operand") 4187 1.1 mrg (match_operand:SI 1 "memory_operand")) 4188 1.1.1.2 mrg (set (match_operand:DI 0 "register_operand") 4189 1.1 mrg (zero_extract:DI (subreg:DI (match_dup 3) 0) 4190 1.1.1.2 mrg (const_int 16) 4191 1.1 mrg (match_operand:DI 2 "const_int_operand")))]) 4192 1.1 mrg 4193 1.1.1.2 mrg ;; Similar for unaligned loads, where we use the sequence from the 4194 1.1 mrg ;; Alpha Architecture manual. We have to distinguish between little-endian 4195 1.1 mrg ;; and big-endian systems as the sequences are different. 4196 1.1.1.2 mrg ;; 4197 1.1.1.2 mrg ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where 4198 1.1 mrg ;; operand 3 can overlap the input and output registers. 4199 1.1.1.2 mrg 4200 1.1 mrg (define_expand "unaligned_loadqi" 4201 1.1.1.2 mrg [(set (match_operand:DI 2 "register_operand") 4202 1.1 mrg (mem:DI (and:DI (match_operand:DI 1 "address_operand") 4203 1.1 mrg (const_int -8)))) 4204 1.1.1.2 mrg (set (match_operand:DI 3 "register_operand") 4205 1.1 mrg (match_dup 1)) 4206 1.1 mrg (set (match_operand:DI 0 "register_operand") 4207 1.1 mrg (zero_extract:DI (match_dup 2) 4208 1.1 mrg (const_int 8) 4209 1.1 mrg (ashift:DI (match_dup 3) (const_int 3))))]) 4210 1.1 mrg 4211 1.1 mrg (define_expand "unaligned_loadhi" 4212 1.1.1.2 mrg [(set (match_operand:DI 2 "register_operand") 4213 1.1.1.2 mrg (mem:DI (and:DI (match_operand:DI 1 "address_operand") 4214 1.1 mrg (const_int -8)))) 4215 1.1 mrg (set (match_operand:DI 3 "register_operand") 4216 1.1.1.2 mrg (match_dup 1)) 4217 1.1.1.2 mrg (set (match_operand:DI 0 "register_operand") 4218 1.1.1.2 mrg (zero_extract:DI (match_dup 2) 4219 1.1 mrg (const_int 16) 4220 1.1 mrg (ashift:DI (match_dup 3) (const_int 3))))]) 4221 1.1 mrg 4222 1.1 mrg ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the 4223 1.1 mrg ;; aligned SImode MEM. Operand 1 is the register containing the 4224 1.1 mrg ;; byte or word to store. Operand 2 is the number of bits within the word that 4225 1.1 mrg ;; the value should be placed. Operands 3 and 4 are SImode temporaries. 4226 1.1 mrg 4227 1.1 mrg (define_expand "aligned_store" 4228 1.1 mrg [(set (match_operand:SI 3 "register_operand") 4229 1.1 mrg (match_operand:SI 0 "memory_operand")) 4230 1.1 mrg (set (subreg:DI (match_dup 3) 0) 4231 1.1 mrg (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5))) 4232 1.1 mrg (set (subreg:DI (match_operand:SI 4 "register_operand") 0) 4233 1.1 mrg (ashift:DI (zero_extend:DI (match_operand 1 "register_operand")) 4234 1.1 mrg (match_operand:DI 2 "const_int_operand"))) 4235 1.1.1.2 mrg (set (subreg:DI (match_dup 4) 0) 4236 1.1.1.2 mrg (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0))) 4237 1.1.1.2 mrg (set (match_dup 0) (match_dup 4))] 4238 1.1 mrg "" 4239 1.1.1.2 mrg { 4240 1.1 mrg operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1])) 4241 1.1 mrg << INTVAL (operands[2]))); 4242 1.1.1.2 mrg }) 4243 1.1 mrg 4244 1.1 mrg ;; For the unaligned byte and halfword cases, we use code similar to that 4245 1.1.1.2 mrg ;; in the ;; Architecture book, but reordered to lower the number of registers 4246 1.1.1.2 mrg ;; required. Operand 0 is the address. Operand 1 is the data to store. 4247 1.1.1.2 mrg ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may 4248 1.1 mrg ;; be the same temporary, if desired. If the address is in a register, 4249 1.1 mrg ;; operand 2 can be that register. 4250 1.1 mrg 4251 1.1 mrg (define_expand "unaligned_store<mode>" 4252 1.1 mrg [(set (match_operand:DI 3 "register_operand") 4253 1.1.1.2 mrg (mem:DI (and:DI (match_operand:DI 0 "address_operand") 4254 1.1 mrg (const_int -8)))) 4255 1.1 mrg (set (match_operand:DI 2 "register_operand") 4256 1.1 mrg (match_dup 0)) 4257 1.1 mrg (set (match_dup 3) 4258 1.1 mrg (and:DI (not:DI (ashift:DI (match_dup 5) 4259 1.1.1.2 mrg (ashift:DI (match_dup 2) (const_int 3)))) 4260 1.1.1.2 mrg (match_dup 3))) 4261 1.1.1.2 mrg (set (match_operand:DI 4 "register_operand") 4262 1.1 mrg (ashift:DI (zero_extend:DI 4263 1.1 mrg (match_operand:I12MODE 1 "register_operand")) 4264 1.1 mrg (ashift:DI (match_dup 2) (const_int 3)))) 4265 1.1.1.2 mrg (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3))) 4266 1.1.1.2 mrg (set (mem:DI (and:DI (match_dup 0) (const_int -8))) 4267 1.1 mrg (match_dup 4))] 4268 1.1 mrg "" 4269 1.1 mrg "operands[5] = GEN_INT (GET_MODE_MASK (<MODE>mode));") 4270 1.1.1.2 mrg 4271 1.1.1.2 mrg ;; Here are the define_expand's for QI and HI moves that use the above 4272 1.1.1.2 mrg ;; patterns. We have the normal sets, plus the ones that need scratch 4273 1.1.1.2 mrg ;; registers for reload. 4274 1.1.1.2 mrg 4275 1.1.1.2 mrg (define_expand "mov<mode>" 4276 1.1.1.2 mrg [(set (match_operand:I12MODE 0 "nonimmediate_operand") 4277 1.1.1.2 mrg (match_operand:I12MODE 1 "general_operand"))] 4278 1.1.1.2 mrg "" 4279 1.1.1.2 mrg { 4280 1.1.1.2 mrg if (TARGET_BWX 4281 1.1.1.2 mrg ? alpha_expand_mov (<MODE>mode, operands) 4282 1.1.1.2 mrg : alpha_expand_mov_nobwx (<MODE>mode, operands)) 4283 1.1.1.2 mrg DONE; 4284 1.1.1.2 mrg }) 4285 1.1.1.2 mrg 4286 1.1.1.2 mrg (define_insn "*movqi" 4287 1.1.1.2 mrg [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m") 4288 1.1.1.2 mrg (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))] 4289 1.1.1.2 mrg "register_operand (operands[0], QImode) 4290 1.1.1.2 mrg || reg_or_0_operand (operands[1], QImode)" 4291 1.1.1.2 mrg "@ 4292 1.1.1.2 mrg bis $31,%r1,%0 4293 1.1.1.2 mrg lda %0,%L1($31) 4294 1.1.1.2 mrg ldbu %0,%1 4295 1.1 mrg stb %r1,%0" 4296 1.1 mrg [(set_attr "type" "ilog,iadd,ild,ist") 4297 1.1 mrg (set_attr "isa" "*,*,bwx,bwx")]) 4298 1.1 mrg 4299 1.1.1.2 mrg (define_insn "*movhi" 4300 1.1.1.2 mrg [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m") 4301 1.1 mrg (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))] 4302 1.1 mrg "register_operand (operands[0], HImode) 4303 1.1 mrg || reg_or_0_operand (operands[1], HImode)" 4304 1.1 mrg "@ 4305 1.1 mrg bis $31,%r1,%0 4306 1.1 mrg lda %0,%L1($31) 4307 1.1 mrg ldwu %0,%1 4308 1.1 mrg stw %r1,%0" 4309 1.1 mrg [(set_attr "type" "ilog,iadd,ild,ist") 4310 1.1 mrg (set_attr "isa" "*,*,bwx,bwx")]) 4311 1.1 mrg 4312 1.1 mrg ;; We need to hook into the extra support that we have for HImode 4313 1.1 mrg ;; reloads when BWX insns are not available. 4314 1.1 mrg (define_expand "movcqi" 4315 1.1 mrg [(set (match_operand:CQI 0 "nonimmediate_operand") 4316 1.1 mrg (match_operand:CQI 1 "general_operand"))] 4317 1.1 mrg "!TARGET_BWX" 4318 1.1 mrg { 4319 1.1 mrg if (GET_CODE (operands[0]) == CONCAT || GET_CODE (operands[1]) == CONCAT) 4320 1.1 mrg ; 4321 1.1 mrg else if (!any_memory_operand (operands[0], CQImode)) 4322 1.1 mrg { 4323 1.1 mrg if (!any_memory_operand (operands[1], CQImode)) 4324 1.1 mrg { 4325 1.1 mrg emit_move_insn (gen_lowpart (HImode, operands[0]), 4326 1.1 mrg gen_lowpart (HImode, operands[1])); 4327 1.1 mrg DONE; 4328 1.1 mrg } 4329 1.1 mrg if (aligned_memory_operand (operands[1], CQImode)) 4330 1.1 mrg { 4331 1.1 mrg bool done; 4332 1.1 mrg do_aligned1: 4333 1.1 mrg operands[1] = gen_lowpart (HImode, operands[1]); 4334 1.1 mrg do_aligned2: 4335 1.1 mrg operands[0] = gen_lowpart (HImode, operands[0]); 4336 1.1 mrg done = alpha_expand_mov_nobwx (HImode, operands); 4337 1.1 mrg gcc_assert (done); 4338 1.1 mrg DONE; 4339 1.1 mrg } 4340 1.1 mrg } 4341 1.1 mrg else if (aligned_memory_operand (operands[0], CQImode)) 4342 1.1 mrg { 4343 1.1 mrg if (MEM_P (operands[1])) 4344 1.1 mrg { 4345 1.1 mrg rtx x = gen_reg_rtx (HImode); 4346 1.1 mrg emit_move_insn (gen_lowpart (CQImode, x), operands[1]); 4347 1.1 mrg operands[1] = x; 4348 1.1 mrg goto do_aligned2; 4349 1.1 mrg } 4350 1.1 mrg goto do_aligned1; 4351 1.1 mrg } 4352 1.1 mrg 4353 1.1 mrg gcc_assert (!reload_in_progress); 4354 1.1 mrg emit_move_complex_parts (operands[0], operands[1]); 4355 1.1 mrg DONE; 4356 1.1 mrg }) 4357 1.1 mrg 4358 1.1 mrg ;; Here are the versions for reload. 4359 1.1 mrg ;; 4360 1.1 mrg ;; The aligned input case is recognized early in alpha_secondary_reload 4361 1.1 mrg ;; in order to avoid allocating an unnecessary scratch register. 4362 1.1 mrg ;; 4363 1.1 mrg ;; Note that in the unaligned cases we know that the operand must not be 4364 1.1 mrg ;; a pseudo-register because stack slots are always aligned references. 4365 1.1 mrg 4366 1.1 mrg (define_expand "reload_in<mode>" 4367 1.1 mrg [(parallel [(match_operand:RELOAD12 0 "register_operand" "=r") 4368 1.1 mrg (match_operand:RELOAD12 1 "any_memory_operand" "m") 4369 1.1 mrg (match_operand:TI 2 "register_operand" "=&r")])] 4370 1.1 mrg "!TARGET_BWX" 4371 1.1 mrg { 4372 1.1 mrg rtx scratch, seq, addr; 4373 1.1 mrg unsigned regno = REGNO (operands[2]); 4374 1.1 mrg 4375 1.1 mrg /* It is possible that one of the registers we got for operands[2] 4376 1.1 mrg might coincide with that of operands[0] (which is why we made 4377 1.1 mrg it TImode). Pick the other one to use as our scratch. */ 4378 1.1 mrg if (regno == REGNO (operands[0])) 4379 1.1 mrg regno++; 4380 1.1.1.2 mrg scratch = gen_rtx_REG (DImode, regno); 4381 1.1 mrg 4382 1.1 mrg addr = get_unaligned_address (operands[1]); 4383 1.1 mrg operands[0] = gen_rtx_REG (DImode, REGNO (operands[0])); 4384 1.1 mrg seq = gen_unaligned_load<reloadmode> (operands[0], addr, 4385 1.1 mrg scratch, operands[0]); 4386 1.1 mrg alpha_set_memflags (seq, operands[1]); 4387 1.1 mrg 4388 1.1 mrg emit_insn (seq); 4389 1.1 mrg DONE; 4390 1.1 mrg }) 4391 1.1 mrg 4392 1.1 mrg (define_expand "reload_out<mode>" 4393 1.1 mrg [(parallel [(match_operand:RELOAD12 0 "any_memory_operand" "=m") 4394 1.1 mrg (match_operand:RELOAD12 1 "register_operand" "r") 4395 1.1 mrg (match_operand:TI 2 "register_operand" "=&r")])] 4396 1.1 mrg "!TARGET_BWX" 4397 1.1 mrg { 4398 1.1 mrg unsigned regno = REGNO (operands[2]); 4399 1.1 mrg 4400 1.1 mrg if (<MODE>mode == CQImode) 4401 1.1 mrg { 4402 1.1 mrg operands[0] = gen_lowpart (HImode, operands[0]); 4403 1.1 mrg operands[1] = gen_lowpart (HImode, operands[1]); 4404 1.1 mrg } 4405 1.1 mrg 4406 1.1 mrg if (aligned_memory_operand (operands[0], <MODE>mode)) 4407 1.1 mrg { 4408 1.1 mrg emit_insn (gen_reload_out<reloadmode>_aligned 4409 1.1 mrg (operands[0], operands[1], 4410 1.1 mrg gen_rtx_REG (SImode, regno), 4411 1.1 mrg gen_rtx_REG (SImode, regno + 1))); 4412 1.1 mrg } 4413 1.1 mrg else 4414 1.1 mrg { 4415 1.1 mrg rtx addr = get_unaligned_address (operands[0]); 4416 1.1 mrg rtx scratch1 = gen_rtx_REG (DImode, regno); 4417 1.1 mrg rtx scratch2 = gen_rtx_REG (DImode, regno + 1); 4418 1.1 mrg rtx scratch3 = scratch1; 4419 1.1 mrg rtx seq; 4420 1.1 mrg 4421 1.1 mrg if (REG_P (addr)) 4422 1.1 mrg scratch1 = addr; 4423 1.1 mrg 4424 1.1 mrg seq = gen_unaligned_store<reloadmode> (addr, operands[1], scratch1, 4425 1.1 mrg scratch2, scratch3); 4426 1.1 mrg alpha_set_memflags (seq, operands[0]); 4427 1.1 mrg emit_insn (seq); 4428 1.1 mrg } 4429 1.1 mrg DONE; 4430 1.1 mrg }) 4431 1.1 mrg 4432 1.1 mrg ;; Helpers for the above. The way reload is structured, we can't 4433 1.1 mrg ;; always get a proper address for a stack slot during reload_foo 4434 1.1 mrg ;; expansion, so we must delay our address manipulations until after. 4435 1.1 mrg 4436 1.1 mrg (define_insn_and_split "reload_in<mode>_aligned" 4437 1.1 mrg [(set (match_operand:I12MODE 0 "register_operand" "=r") 4438 1.1 mrg (match_operand:I12MODE 1 "memory_operand" "m"))] 4439 1.1.1.2 mrg "!TARGET_BWX && (reload_in_progress || reload_completed)" 4440 1.1.1.2 mrg "#" 4441 1.1 mrg "!TARGET_BWX && reload_completed" 4442 1.1 mrg [(const_int 0)] 4443 1.1 mrg { 4444 1.1 mrg rtx aligned_mem, bitnum; 4445 1.1 mrg get_aligned_mem (operands[1], &aligned_mem, &bitnum); 4446 1.1 mrg emit_insn (gen_aligned_load<reloadmode> 4447 1.1 mrg (gen_lowpart (DImode, operands[0]), aligned_mem, bitnum, 4448 1.1 mrg gen_rtx_REG (SImode, REGNO (operands[0])))); 4449 1.1 mrg DONE; 4450 1.1 mrg }) 4451 1.1 mrg 4452 1.1 mrg (define_insn_and_split "reload_out<mode>_aligned" 4453 1.1 mrg [(set (match_operand:I12MODE 0 "memory_operand" "=m") 4454 1.1 mrg (match_operand:I12MODE 1 "register_operand" "r")) 4455 1.1 mrg (clobber (match_operand:SI 2 "register_operand" "=&r")) 4456 1.1.1.2 mrg (clobber (match_operand:SI 3 "register_operand" "=&r"))] 4457 1.1 mrg "!TARGET_BWX && (reload_in_progress || reload_completed)" 4458 1.1 mrg "#" 4459 1.1.1.2 mrg "!TARGET_BWX && reload_completed" 4460 1.1.1.2 mrg [(const_int 0)] 4461 1.1 mrg { 4462 1.1 mrg rtx aligned_mem, bitnum; 4463 1.1 mrg get_aligned_mem (operands[0], &aligned_mem, &bitnum); 4464 1.1 mrg emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum, 4465 1.1 mrg operands[2], operands[3])); 4466 1.1 mrg DONE; 4467 1.1 mrg }) 4468 1.1.1.2 mrg 4470 1.1 mrg ;; Vector operations 4471 1.1 mrg 4472 1.1 mrg (define_mode_iterator VEC [V8QI V4HI V2SI]) 4473 1.1 mrg (define_mode_iterator VEC12 [V8QI V4HI]) 4474 1.1 mrg 4475 1.1 mrg (define_expand "mov<mode>" 4476 1.1 mrg [(set (match_operand:VEC 0 "nonimmediate_operand") 4477 1.1 mrg (match_operand:VEC 1 "general_operand"))] 4478 1.1 mrg "" 4479 1.1 mrg { 4480 1.1 mrg if (alpha_expand_mov (<MODE>mode, operands)) 4481 1.1.1.2 mrg DONE; 4482 1.1.1.2 mrg }) 4483 1.1 mrg 4484 1.1 mrg (define_split 4485 1.1 mrg [(set (match_operand:VEC 0 "register_operand") 4486 1.1 mrg (match_operand:VEC 1 "non_zero_const_operand"))] 4487 1.1 mrg "" 4488 1.1 mrg [(const_int 0)] 4489 1.1 mrg { 4490 1.1 mrg if (alpha_split_const_mov (<MODE>mode, operands)) 4491 1.1 mrg DONE; 4492 1.1.1.2 mrg else 4493 1.1.1.2 mrg FAIL; 4494 1.1 mrg }) 4495 1.1 mrg 4496 1.1 mrg 4497 1.1 mrg (define_expand "movmisalign<mode>" 4498 1.1 mrg [(set (match_operand:VEC 0 "nonimmediate_operand") 4499 1.1 mrg (match_operand:VEC 1 "general_operand"))] 4500 1.1 mrg "" 4501 1.1 mrg { 4502 1.1 mrg alpha_expand_movmisalign (<MODE>mode, operands); 4503 1.1 mrg DONE; 4504 1.1.1.2 mrg }) 4505 1.1.1.2 mrg 4506 1.1 mrg (define_insn "*mov<mode>_fix" 4507 1.1.1.2 mrg [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m,r,*f") 4508 1.1.1.2 mrg (match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f,*f,r"))] 4509 1.1.1.2 mrg "register_operand (operands[0], <MODE>mode) 4510 1.1.1.2 mrg || reg_or_0_operand (operands[1], <MODE>mode)" 4511 1.1.1.2 mrg "@ 4512 1.1 mrg bis $31,%r1,%0 4513 1.1.1.2 mrg # 4514 1.1 mrg ldq %0,%1 4515 1.1 mrg stq %r1,%0 4516 1.1 mrg cpys %R1,%R1,%0 4517 1.1 mrg ldt %0,%1 4518 1.1 mrg stt %R1,%0 4519 1.1 mrg ftoit %1,%0 4520 1.1 mrg itoft %1,%0" 4521 1.1 mrg [(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst,ftoi,itof") 4522 1.1 mrg (set_attr "isa" "*,*,*,*,*,*,*,fix,fix")]) 4523 1.1 mrg 4524 1.1 mrg (define_insn "<code><mode>3" 4525 1.1 mrg [(set (match_operand:VEC12 0 "register_operand" "=r") 4526 1.1 mrg (any_maxmin:VEC12 4527 1.1 mrg (match_operand:VEC12 1 "reg_or_0_operand" "rW") 4528 1.1 mrg (match_operand:VEC12 2 "reg_or_0_operand" "rW")))] 4529 1.1 mrg "TARGET_MAX" 4530 1.1 mrg "<maxmin><modesuffix> %r1,%r2,%0" 4531 1.1 mrg [(set_attr "type" "mvi")]) 4532 1.1 mrg 4533 1.1 mrg (define_insn "one_cmpl<mode>2" 4534 1.1 mrg [(set (match_operand:VEC 0 "register_operand" "=r") 4535 1.1 mrg (not:VEC (match_operand:VEC 1 "register_operand" "r")))] 4536 1.1 mrg "" 4537 1.1 mrg "ornot $31,%1,%0" 4538 1.1 mrg [(set_attr "type" "ilog")]) 4539 1.1 mrg 4540 1.1 mrg (define_insn "and<mode>3" 4541 1.1 mrg [(set (match_operand:VEC 0 "register_operand" "=r") 4542 1.1 mrg (and:VEC (match_operand:VEC 1 "register_operand" "r") 4543 1.1 mrg (match_operand:VEC 2 "register_operand" "r")))] 4544 1.1 mrg "" 4545 1.1 mrg "and %1,%2,%0" 4546 1.1 mrg [(set_attr "type" "ilog")]) 4547 1.1 mrg 4548 1.1 mrg (define_insn "*andnot<mode>3" 4549 1.1 mrg [(set (match_operand:VEC 0 "register_operand" "=r") 4550 1.1 mrg (and:VEC (not:VEC (match_operand:VEC 1 "register_operand" "r")) 4551 1.1 mrg (match_operand:VEC 2 "register_operand" "r")))] 4552 1.1 mrg "" 4553 1.1 mrg "bic %2,%1,%0" 4554 1.1 mrg [(set_attr "type" "ilog")]) 4555 1.1 mrg 4556 1.1 mrg (define_insn "ior<mode>3" 4557 1.1 mrg [(set (match_operand:VEC 0 "register_operand" "=r") 4558 1.1 mrg (ior:VEC (match_operand:VEC 1 "register_operand" "r") 4559 1.1 mrg (match_operand:VEC 2 "register_operand" "r")))] 4560 1.1 mrg "" 4561 1.1 mrg "bis %1,%2,%0" 4562 1.1 mrg [(set_attr "type" "ilog")]) 4563 1.1 mrg 4564 1.1 mrg (define_insn "*iornot<mode>3" 4565 1.1 mrg [(set (match_operand:VEC 0 "register_operand" "=r") 4566 1.1 mrg (ior:VEC (not:DI (match_operand:VEC 1 "register_operand" "r")) 4567 1.1 mrg (match_operand:VEC 2 "register_operand" "r")))] 4568 1.1 mrg "" 4569 1.1 mrg "ornot %2,%1,%0" 4570 1.1 mrg [(set_attr "type" "ilog")]) 4571 1.1 mrg 4572 1.1.1.2 mrg (define_insn "xor<mode>3" 4573 1.1.1.2 mrg [(set (match_operand:VEC 0 "register_operand" "=r") 4574 1.1.1.2 mrg (xor:VEC (match_operand:VEC 1 "register_operand" "r") 4575 1.1 mrg (match_operand:VEC 2 "register_operand" "r")))] 4576 1.1 mrg "" 4577 1.1 mrg "xor %1,%2,%0" 4578 1.1 mrg [(set_attr "type" "ilog")]) 4579 1.1 mrg 4580 1.1 mrg (define_insn "*xornot<mode>3" 4581 1.1 mrg [(set (match_operand:VEC 0 "register_operand" "=r") 4582 1.1.1.2 mrg (not:VEC (xor:VEC (match_operand:VEC 1 "register_operand" "r") 4583 1.1.1.2 mrg (match_operand:VEC 2 "register_operand" "r"))))] 4584 1.1.1.2 mrg "" 4585 1.1 mrg "eqv %1,%2,%0" 4586 1.1 mrg [(set_attr "type" "ilog")]) 4587 1.1 mrg 4588 1.1 mrg (define_expand "vec_shl_<mode>" 4589 1.1 mrg [(set (match_operand:VEC 0 "register_operand") 4590 1.1 mrg (ashift:DI (match_operand:VEC 1 "register_operand") 4591 1.1 mrg (match_operand:DI 2 "reg_or_6bit_operand")))] 4592 1.1 mrg "" 4593 1.1.1.2 mrg { 4594 1.1.1.2 mrg operands[0] = gen_lowpart (DImode, operands[0]); 4595 1.1.1.2 mrg operands[1] = gen_lowpart (DImode, operands[1]); 4596 1.1.1.2 mrg }) 4597 1.1.1.2 mrg 4598 1.1 mrg (define_expand "vec_shr_<mode>" 4599 1.1 mrg [(set (match_operand:VEC 0 "register_operand") 4600 1.1 mrg (lshiftrt:DI (match_operand:VEC 1 "register_operand") 4601 1.1 mrg (match_operand:DI 2 "reg_or_6bit_operand")))] 4602 1.1 mrg "" 4603 1.1 mrg { 4604 1.1 mrg operands[0] = gen_lowpart (DImode, operands[0]); 4605 1.1 mrg operands[1] = gen_lowpart (DImode, operands[1]); 4606 1.1 mrg }) 4607 1.1 mrg 4609 1.1.1.2 mrg ;; Bit field extract patterns which use ext[wlq][lh] 4610 1.1 mrg 4611 1.1 mrg (define_expand "extvmisaligndi" 4612 1.1 mrg [(set (match_operand:DI 0 "register_operand") 4613 1.1.1.2 mrg (sign_extract:DI (match_operand:BLK 1 "memory_operand") 4614 1.1.1.2 mrg (match_operand:DI 2 "const_int_operand") 4615 1.1.1.2 mrg (match_operand:DI 3 "const_int_operand")))] 4616 1.1.1.2 mrg "" 4617 1.1.1.2 mrg { 4618 1.1 mrg /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */ 4619 1.1 mrg if (INTVAL (operands[3]) % 8 != 0 4620 1.1 mrg || (INTVAL (operands[2]) != 16 4621 1.1 mrg && INTVAL (operands[2]) != 32 4622 1.1 mrg && INTVAL (operands[2]) != 64)) 4623 1.1.1.2 mrg FAIL; 4624 1.1 mrg 4625 1.1 mrg alpha_expand_unaligned_load (operands[0], operands[1], 4626 1.1 mrg INTVAL (operands[2]) / 8, 4627 1.1.1.2 mrg INTVAL (operands[3]) / 8, 1); 4628 1.1 mrg DONE; 4629 1.1.1.2 mrg }) 4630 1.1.1.2 mrg 4631 1.1.1.2 mrg (define_expand "extzvdi" 4632 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand") 4633 1.1.1.2 mrg (zero_extract:DI (match_operand:DI 1 "register_operand") 4634 1.1.1.2 mrg (match_operand:DI 2 "const_int_operand") 4635 1.1.1.2 mrg (match_operand:DI 3 "const_int_operand")))] 4636 1.1.1.2 mrg "" 4637 1.1.1.2 mrg { 4638 1.1.1.2 mrg /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */ 4639 1.1.1.2 mrg if (INTVAL (operands[3]) % 8 != 0 4640 1.1.1.2 mrg || (INTVAL (operands[2]) != 8 4641 1.1.1.2 mrg && INTVAL (operands[2]) != 16 4642 1.1.1.2 mrg && INTVAL (operands[2]) != 32 4643 1.1 mrg && INTVAL (operands[2]) != 64)) 4644 1.1.1.2 mrg FAIL; 4645 1.1.1.2 mrg }) 4646 1.1.1.2 mrg 4647 1.1.1.2 mrg (define_expand "extzvmisaligndi" 4648 1.1 mrg [(set (match_operand:DI 0 "register_operand") 4649 1.1 mrg (zero_extract:DI (match_operand:BLK 1 "memory_operand") 4650 1.1.1.2 mrg (match_operand:DI 2 "const_int_operand") 4651 1.1.1.2 mrg (match_operand:DI 3 "const_int_operand")))] 4652 1.1.1.2 mrg "" 4653 1.1.1.2 mrg { 4654 1.1.1.2 mrg /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. 4655 1.1 mrg We fail 8-bit fields, falling back on a simple byte load. */ 4656 1.1 mrg if (INTVAL (operands[3]) % 8 != 0 4657 1.1 mrg || (INTVAL (operands[2]) != 16 4658 1.1 mrg && INTVAL (operands[2]) != 32 4659 1.1 mrg && INTVAL (operands[2]) != 64)) 4660 1.1 mrg FAIL; 4661 1.1 mrg 4662 1.1 mrg alpha_expand_unaligned_load (operands[0], operands[1], 4663 1.1 mrg INTVAL (operands[2]) / 8, 4664 1.1 mrg INTVAL (operands[3]) / 8, 0); 4665 1.1.1.2 mrg DONE; 4666 1.1.1.2 mrg }) 4667 1.1 mrg 4668 1.1 mrg (define_expand "insvmisaligndi" 4669 1.1 mrg [(set (zero_extract:DI (match_operand:BLK 0 "memory_operand") 4670 1.1 mrg (match_operand:DI 1 "const_int_operand") 4671 1.1 mrg (match_operand:DI 2 "const_int_operand")) 4672 1.1 mrg (match_operand:DI 3 "register_operand"))] 4673 1.1 mrg "" 4674 1.1 mrg { 4675 1.1 mrg /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */ 4676 1.1 mrg if (INTVAL (operands[2]) % 8 != 0 4677 1.1.1.2 mrg || (INTVAL (operands[1]) != 16 4678 1.1.1.2 mrg && INTVAL (operands[1]) != 32 4679 1.1.1.2 mrg && INTVAL (operands[1]) != 64)) 4680 1.1.1.2 mrg FAIL; 4681 1.1 mrg 4682 1.1 mrg alpha_expand_unaligned_store (operands[0], operands[3], 4683 1.1 mrg INTVAL (operands[1]) / 8, 4684 1.1 mrg INTVAL (operands[2]) / 8); 4685 1.1 mrg DONE; 4686 1.1 mrg }) 4687 1.1 mrg 4688 1.1 mrg ;; Block move/clear, see alpha.c for more details. 4689 1.1 mrg ;; Argument 0 is the destination 4690 1.1.1.2 mrg ;; Argument 1 is the source 4691 1.1.1.2 mrg ;; Argument 2 is the length 4692 1.1.1.2 mrg ;; Argument 3 is the alignment 4693 1.1.1.2 mrg 4694 1.1 mrg (define_expand "movmemqi" 4695 1.1 mrg [(parallel [(set (match_operand:BLK 0 "memory_operand") 4696 1.1 mrg (match_operand:BLK 1 "memory_operand")) 4697 1.1 mrg (use (match_operand:DI 2 "immediate_operand")) 4698 1.1 mrg (use (match_operand:DI 3 "immediate_operand"))])] 4699 1.1 mrg "" 4700 1.1 mrg { 4701 1.1 mrg if (alpha_expand_block_move (operands)) 4702 1.1 mrg DONE; 4703 1.1 mrg else 4704 1.1.1.2 mrg FAIL; 4705 1.1 mrg }) 4706 1.1 mrg 4707 1.1.1.3 mrg (define_expand "movmemdi" 4708 1.1 mrg [(parallel [(set (match_operand:BLK 0 "memory_operand") 4709 1.1 mrg (match_operand:BLK 1 "memory_operand")) 4710 1.1.1.2 mrg (use (match_operand:DI 2 "immediate_operand")) 4711 1.1 mrg (use (match_operand:DI 3 "immediate_operand")) 4712 1.1 mrg (use (match_dup 4)) 4713 1.1 mrg (clobber (reg:DI 25)) 4714 1.1 mrg (clobber (reg:DI 16)) 4715 1.1 mrg (clobber (reg:DI 17)) 4716 1.1 mrg (clobber (reg:DI 18)) 4717 1.1 mrg (clobber (reg:DI 19)) 4718 1.1 mrg (clobber (reg:DI 20)) 4719 1.1 mrg (clobber (reg:DI 26)) 4720 1.1 mrg (clobber (reg:DI 27))])] 4721 1.1 mrg "TARGET_ABI_OPEN_VMS" 4722 1.1.1.2 mrg "operands[4] = gen_rtx_SYMBOL_REF (Pmode, \"OTS$MOVE\");") 4723 1.1 mrg 4724 1.1 mrg (define_insn "*movmemdi_1" 4725 1.1 mrg [(set (match_operand:BLK 0 "memory_operand" "=m,m") 4726 1.1 mrg (match_operand:BLK 1 "memory_operand" "m,m")) 4727 1.1 mrg (use (match_operand:DI 2 "nonmemory_operand" "r,i")) 4728 1.1 mrg (use (match_operand:DI 3 "immediate_operand")) 4729 1.1 mrg (use (match_operand:DI 4 "call_operand" "i,i")) 4730 1.1 mrg (clobber (reg:DI 25)) 4731 1.1 mrg (clobber (reg:DI 16)) 4732 1.1 mrg (clobber (reg:DI 17)) 4733 1.1 mrg (clobber (reg:DI 18)) 4734 1.1 mrg (clobber (reg:DI 19)) 4735 1.1 mrg (clobber (reg:DI 20)) 4736 1.1 mrg (clobber (reg:DI 26)) 4737 1.1.1.2 mrg (clobber (reg:DI 27))] 4738 1.1.1.2 mrg "TARGET_ABI_OPEN_VMS" 4739 1.1.1.2 mrg { 4740 1.1.1.2 mrg operands [5] = alpha_use_linkage (operands [4], false, true); 4741 1.1 mrg switch (which_alternative) 4742 1.1 mrg { 4743 1.1 mrg case 0: 4744 1.1 mrg return "lda $16,%0\;bis $31,%2,$17\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)"; 4745 1.1 mrg case 1: 4746 1.1 mrg return "lda $16,%0\;lda $17,%2($31)\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)"; 4747 1.1 mrg default: 4748 1.1 mrg gcc_unreachable (); 4749 1.1 mrg } 4750 1.1 mrg } 4751 1.1 mrg [(set_attr "type" "multi") 4752 1.1 mrg (set_attr "length" "28")]) 4753 1.1 mrg 4754 1.1.1.2 mrg (define_expand "setmemqi" 4755 1.1.1.2 mrg [(parallel [(set (match_operand:BLK 0 "memory_operand") 4756 1.1.1.2 mrg (match_operand 2 "const_int_operand")) 4757 1.1.1.2 mrg (use (match_operand:DI 1 "immediate_operand")) 4758 1.1 mrg (use (match_operand:DI 3 "immediate_operand"))])] 4759 1.1 mrg "" 4760 1.1 mrg { 4761 1.1 mrg /* If value to set is not zero, use the library routine. */ 4762 1.1 mrg if (operands[2] != const0_rtx) 4763 1.1 mrg FAIL; 4764 1.1 mrg 4765 1.1 mrg if (alpha_expand_block_clear (operands)) 4766 1.1 mrg DONE; 4767 1.1 mrg else 4768 1.1 mrg FAIL; 4769 1.1 mrg }) 4770 1.1.1.2 mrg 4771 1.1 mrg (define_expand "setmemdi" 4772 1.1 mrg [(parallel [(set (match_operand:BLK 0 "memory_operand") 4773 1.1 mrg (match_operand 2 "const_int_operand")) 4774 1.1.1.3 mrg (use (match_operand:DI 1 "immediate_operand")) 4775 1.1 mrg (use (match_operand:DI 3 "immediate_operand")) 4776 1.1 mrg (use (match_dup 4)) 4777 1.1.1.2 mrg (clobber (reg:DI 25)) 4778 1.1 mrg (clobber (reg:DI 16)) 4779 1.1 mrg (clobber (reg:DI 17)) 4780 1.1 mrg (clobber (reg:DI 26)) 4781 1.1 mrg (clobber (reg:DI 27))])] 4782 1.1 mrg "TARGET_ABI_OPEN_VMS" 4783 1.1 mrg { 4784 1.1 mrg /* If value to set is not zero, use the library routine. */ 4785 1.1 mrg if (operands[2] != const0_rtx) 4786 1.1.1.2 mrg FAIL; 4787 1.1 mrg 4788 1.1 mrg operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$ZERO"); 4789 1.1 mrg }) 4790 1.1 mrg 4791 1.1 mrg (define_insn "*clrmemdi_1" 4792 1.1 mrg [(set (match_operand:BLK 0 "memory_operand" "=m,m") 4793 1.1 mrg (const_int 0)) 4794 1.1 mrg (use (match_operand:DI 1 "nonmemory_operand" "r,i")) 4795 1.1 mrg (use (match_operand:DI 2 "immediate_operand")) 4796 1.1 mrg (use (match_operand:DI 3 "call_operand" "i,i")) 4797 1.1 mrg (clobber (reg:DI 25)) 4798 1.1 mrg (clobber (reg:DI 16)) 4799 1.1 mrg (clobber (reg:DI 17)) 4800 1.1 mrg (clobber (reg:DI 26)) 4801 1.1 mrg (clobber (reg:DI 27))] 4802 1.1.1.5 mrg "TARGET_ABI_OPEN_VMS" 4803 1.1.1.2 mrg { 4804 1.1 mrg operands [4] = alpha_use_linkage (operands [3], false, true); 4805 1.1 mrg switch (which_alternative) 4806 1.1.1.2 mrg { 4807 1.1 mrg case 0: 4808 1.1 mrg return "lda $16,%0\;bis $31,%1,$17\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)"; 4809 1.1 mrg case 1: 4810 1.1 mrg return "lda $16,%0\;lda $17,%1($31)\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)"; 4811 1.1 mrg default: 4812 1.1 mrg gcc_unreachable (); 4813 1.1 mrg } 4814 1.1 mrg } 4815 1.1 mrg [(set_attr "type" "multi") 4816 1.1 mrg (set_attr "length" "24")]) 4817 1.1 mrg 4818 1.1 mrg 4820 1.1 mrg ;; Subroutine of stack space allocation. Perform a stack probe. 4821 1.1 mrg (define_expand "stack_probe_internal" 4822 1.1.1.2 mrg [(set (match_dup 1) (match_operand:DI 0 "const_int_operand"))] 4823 1.1 mrg "" 4824 1.1 mrg { 4825 1.1 mrg operands[1] = gen_rtx_MEM (DImode, plus_constant (Pmode, stack_pointer_rtx, 4826 1.1 mrg INTVAL (operands[0]))); 4827 1.1 mrg MEM_VOLATILE_P (operands[1]) = 1; 4828 1.1 mrg 4829 1.1 mrg operands[0] = const0_rtx; 4830 1.1 mrg }) 4831 1.1 mrg 4832 1.1 mrg ;; This is how we allocate stack space. If we are allocating a 4833 1.1 mrg ;; constant amount of space and we know it is less than 4096 4834 1.1 mrg ;; bytes, we need do nothing. 4835 1.1 mrg ;; 4836 1.1 mrg ;; If it is more than 4096 bytes, we need to probe the stack 4837 1.1.1.5 mrg ;; periodically. 4838 1.1 mrg (define_expand "allocate_stack" 4839 1.1.1.5 mrg [(set (reg:DI 30) 4840 1.1.1.5 mrg (plus:DI (reg:DI 30) 4841 1.1 mrg (match_operand:DI 1 "reg_or_cint_operand"))) 4842 1.1 mrg (set (match_operand:DI 0 "register_operand" "=r") 4843 1.1.1.5 mrg (match_dup 2))] 4844 1.1.1.5 mrg "" 4845 1.1 mrg { 4846 1.1 mrg if (CONST_INT_P (operands[1]) 4847 1.1 mrg && INTVAL (operands[1]) < 32768) 4848 1.1 mrg { 4849 1.1 mrg if (INTVAL (operands[1]) >= 4096) 4850 1.1 mrg { 4851 1.1 mrg /* We do this the same way as in the prologue and generate explicit 4852 1.1.1.3 mrg probes. Then we update the stack by the constant. */ 4853 1.1.1.3 mrg 4854 1.1 mrg int probed = 4096; 4855 1.1 mrg 4856 1.1 mrg emit_insn (gen_stack_probe_internal (GEN_INT (- probed))); 4857 1.1 mrg while (probed + 8192 < INTVAL (operands[1])) 4858 1.1 mrg emit_insn (gen_stack_probe_internal 4859 1.1 mrg (GEN_INT (- (probed += 8192)))); 4860 1.1 mrg 4861 1.1 mrg if (probed + 4096 < INTVAL (operands[1])) 4862 1.1 mrg emit_insn (gen_stack_probe_internal 4863 1.1.1.2 mrg (GEN_INT (- INTVAL(operands[1])))); 4864 1.1 mrg } 4865 1.1.1.2 mrg 4866 1.1.1.2 mrg operands[1] = GEN_INT (- INTVAL (operands[1])); 4867 1.1.1.2 mrg operands[2] = virtual_stack_dynamic_rtx; 4868 1.1 mrg } 4869 1.1 mrg else 4870 1.1.1.2 mrg { 4871 1.1 mrg rtx_code_label *out_label = 0; 4872 1.1 mrg rtx_code_label *loop_label = gen_label_rtx (); 4873 1.1 mrg rtx want = gen_reg_rtx (Pmode); 4874 1.1 mrg rtx tmp = gen_reg_rtx (Pmode); 4875 1.1 mrg rtx memref, test; 4876 1.1 mrg 4877 1.1 mrg emit_insn (gen_subdi3 (want, stack_pointer_rtx, 4878 1.1 mrg force_reg (Pmode, operands[1]))); 4879 1.1 mrg 4880 1.1 mrg if (!CONST_INT_P (operands[1])) 4881 1.1 mrg { 4882 1.1 mrg rtx limit = GEN_INT (4096); 4883 1.1 mrg out_label = gen_label_rtx (); 4884 1.1 mrg test = gen_rtx_LTU (VOIDmode, operands[1], limit); 4885 1.1 mrg emit_jump_insn 4886 1.1 mrg (gen_cbranchdi4 (test, operands[1], limit, out_label)); 4887 1.1 mrg } 4888 1.1 mrg 4889 1.1 mrg emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096))); 4890 1.1 mrg emit_label (loop_label); 4891 1.1 mrg memref = gen_rtx_MEM (DImode, tmp); 4892 1.1 mrg MEM_VOLATILE_P (memref) = 1; 4893 1.1 mrg emit_move_insn (memref, const0_rtx); 4894 1.1 mrg emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192))); 4895 1.1 mrg test = gen_rtx_GTU (VOIDmode, tmp, want); 4896 1.1 mrg emit_jump_insn (gen_cbranchdi4 (test, tmp, want, loop_label)); 4897 1.1 mrg 4898 1.1 mrg memref = gen_rtx_MEM (DImode, want); 4899 1.1 mrg MEM_VOLATILE_P (memref) = 1; 4900 1.1 mrg emit_move_insn (memref, const0_rtx); 4901 1.1 mrg 4902 1.1 mrg if (out_label) 4903 1.1 mrg emit_label (out_label); 4904 1.1 mrg 4905 1.1 mrg emit_move_insn (stack_pointer_rtx, want); 4906 1.1 mrg emit_move_insn (operands[0], virtual_stack_dynamic_rtx); 4907 1.1 mrg DONE; 4908 1.1 mrg } 4909 1.1 mrg }) 4910 1.1 mrg 4911 1.1 mrg ;; This is used by alpha_expand_prolog to do the same thing as above, 4912 1.1.1.2 mrg ;; except we cannot at that time generate new basic blocks, so we hide 4913 1.1 mrg ;; the loop in this one insn. 4914 1.1 mrg 4915 1.1 mrg (define_insn "prologue_stack_probe_loop" 4916 1.1 mrg [(unspec_volatile [(match_operand:DI 0 "register_operand" "r") 4917 1.1 mrg (match_operand:DI 1 "register_operand" "r")] 4918 1.1 mrg UNSPECV_PSPL)] 4919 1.1 mrg "" 4920 1.1 mrg { 4921 1.1 mrg operands[2] = gen_label_rtx (); 4922 1.1 mrg (*targetm.asm_out.internal_label) (asm_out_file, "L", 4923 1.1 mrg CODE_LABEL_NUMBER (operands[2])); 4924 1.1 mrg 4925 1.1 mrg return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2"; 4926 1.1 mrg } 4927 1.1 mrg [(set_attr "length" "16") 4928 1.1 mrg (set_attr "type" "multi")]) 4929 1.1 mrg 4930 1.1 mrg (define_expand "prologue" 4931 1.1 mrg [(const_int 0)] 4932 1.1 mrg "" 4933 1.1 mrg { 4934 1.1 mrg alpha_expand_prologue (); 4935 1.1 mrg DONE; 4936 1.1 mrg }) 4937 1.1 mrg 4938 1.1 mrg ;; These take care of emitting the ldgp insn in the prologue. This will be 4939 1.1 mrg ;; an lda/ldah pair and we want to align them properly. So we have two 4940 1.1 mrg ;; unspec_volatile insns, the first of which emits the ldgp assembler macro 4941 1.1 mrg ;; and the second of which emits nothing. However, both are marked as type 4942 1.1 mrg ;; IADD (the default) so the alignment code in alpha.c does the right thing 4943 1.1.1.2 mrg ;; with them. 4944 1.1 mrg 4945 1.1 mrg (define_expand "prologue_ldgp" 4946 1.1 mrg [(set (match_dup 0) 4947 1.1 mrg (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1)) 4948 1.1 mrg (set (match_dup 0) 4949 1.1 mrg (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))] 4950 1.1 mrg "" 4951 1.1 mrg { 4952 1.1.1.2 mrg operands[0] = pic_offset_table_rtx; 4953 1.1 mrg operands[1] = gen_rtx_REG (Pmode, 27); 4954 1.1 mrg operands[2] = (TARGET_EXPLICIT_RELOCS 4955 1.1 mrg ? GEN_INT (alpha_next_sequence_number++) 4956 1.1 mrg : const0_rtx); 4957 1.1 mrg }) 4958 1.1 mrg 4959 1.1 mrg (define_insn "*ldgp_er_1" 4960 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 4961 1.1.1.2 mrg (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") 4962 1.1 mrg (match_operand 2 "const_int_operand")] 4963 1.1 mrg UNSPECV_LDGP1))] 4964 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 4965 1.1 mrg "ldah %0,0(%1)\t\t!gpdisp!%2" 4966 1.1 mrg [(set_attr "cannot_copy" "true")]) 4967 1.1 mrg 4968 1.1 mrg (define_insn "*ldgp_er_2" 4969 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 4970 1.1.1.2 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "r") 4971 1.1 mrg (match_operand 2 "const_int_operand")] 4972 1.1 mrg UNSPEC_LDGP2))] 4973 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 4974 1.1 mrg "lda %0,0(%1)\t\t!gpdisp!%2" 4975 1.1 mrg [(set_attr "cannot_copy" "true")]) 4976 1.1 mrg 4977 1.1 mrg (define_insn "*prologue_ldgp_er_2" 4978 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 4979 1.1.1.2 mrg (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") 4980 1.1 mrg (match_operand 2 "const_int_operand")] 4981 1.1 mrg UNSPECV_PLDGP2))] 4982 1.1.1.2 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 4983 1.1 mrg "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:" 4984 1.1 mrg [(set_attr "cannot_copy" "true")]) 4985 1.1 mrg 4986 1.1 mrg (define_insn "*prologue_ldgp_1" 4987 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 4988 1.1 mrg (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") 4989 1.1 mrg (match_operand 2 "const_int_operand")] 4990 1.1 mrg UNSPECV_LDGP1))] 4991 1.1 mrg "" 4992 1.1 mrg "ldgp %0,0(%1)\n$%~..ng:" 4993 1.1 mrg [(set_attr "cannot_copy" "true")]) 4994 1.1 mrg 4995 1.1 mrg (define_insn "*prologue_ldgp_2" 4996 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 4997 1.1 mrg (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") 4998 1.1 mrg (match_operand 2 "const_int_operand")] 4999 1.1 mrg UNSPECV_PLDGP2))] 5000 1.1 mrg "" 5001 1.1 mrg ) 5002 1.1 mrg 5003 1.1 mrg ;; The _mcount profiling hook has special calling conventions, and 5004 1.1 mrg ;; does not clobber all the registers that a normal call would. So 5005 1.1 mrg ;; hide the fact this is a call at all. 5006 1.1 mrg 5007 1.1 mrg (define_insn "prologue_mcount" 5008 1.1 mrg [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)] 5009 1.1 mrg "" 5010 1.1 mrg { 5011 1.1 mrg if (TARGET_EXPLICIT_RELOCS) 5012 1.1.1.2 mrg /* Note that we cannot use a lituse_jsr reloc, since _mcount 5013 1.1 mrg cannot be called via the PLT. */ 5014 1.1 mrg return "ldq $28,_mcount($29)\t\t!literal\;jsr $28,($28),_mcount"; 5015 1.1 mrg else 5016 1.1 mrg return "lda $28,_mcount\;jsr $28,($28),_mcount"; 5017 1.1 mrg } 5018 1.1 mrg [(set_attr "type" "multi") 5019 1.1 mrg (set_attr "length" "8")]) 5020 1.1 mrg 5021 1.1 mrg (define_insn "init_fp" 5022 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 5023 1.1 mrg (match_operand:DI 1 "register_operand" "r")) 5024 1.1 mrg (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))] 5025 1.1 mrg "" 5026 1.1 mrg "bis $31,%1,%0") 5027 1.1 mrg 5028 1.1.1.2 mrg (define_expand "epilogue" 5029 1.1.1.2 mrg [(return)] 5030 1.1 mrg "" 5031 1.1 mrg "alpha_expand_epilogue ();") 5032 1.1 mrg 5033 1.1 mrg (define_expand "sibcall_epilogue" 5034 1.1 mrg [(return)] 5035 1.1.1.2 mrg "TARGET_ABI_OSF" 5036 1.1 mrg { 5037 1.1 mrg alpha_expand_epilogue (); 5038 1.1 mrg DONE; 5039 1.1 mrg }) 5040 1.1 mrg 5041 1.1 mrg (define_expand "builtin_longjmp" 5042 1.1 mrg [(use (match_operand:DI 0 "register_operand" "r"))] 5043 1.1 mrg "TARGET_ABI_OSF" 5044 1.1 mrg { 5045 1.1 mrg /* The elements of the buffer are, in order: */ 5046 1.1 mrg rtx fp = gen_rtx_MEM (Pmode, operands[0]); 5047 1.1 mrg rtx lab = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 8)); 5048 1.1 mrg rtx stack = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 16)); 5049 1.1 mrg rtx pv = gen_rtx_REG (Pmode, 27); 5050 1.1 mrg 5051 1.1 mrg /* This bit is the same as expand_builtin_longjmp. */ 5052 1.1 mrg emit_move_insn (hard_frame_pointer_rtx, fp); 5053 1.1 mrg emit_move_insn (pv, lab); 5054 1.1 mrg emit_stack_restore (SAVE_NONLOCAL, stack); 5055 1.1 mrg emit_use (hard_frame_pointer_rtx); 5056 1.1 mrg emit_use (stack_pointer_rtx); 5057 1.1 mrg 5058 1.1.1.2 mrg /* Load the label we are jumping through into $27 so that we know 5059 1.1.1.2 mrg where to look for it when we get back to setjmp's function for 5060 1.1 mrg restoring the gp. */ 5061 1.1 mrg emit_jump_insn (gen_builtin_longjmp_internal (pv)); 5062 1.1.1.2 mrg emit_barrier (); 5063 1.1 mrg DONE; 5064 1.1 mrg }) 5065 1.1 mrg 5066 1.1 mrg ;; This is effectively a copy of indirect_jump, but constrained such 5067 1.1 mrg ;; that register renaming cannot foil our cunning plan with $27. 5068 1.1 mrg (define_insn "builtin_longjmp_internal" 5069 1.1 mrg [(set (pc) 5070 1.1 mrg (unspec_volatile [(match_operand:DI 0 "register_operand" "c")] 5071 1.1 mrg UNSPECV_LONGJMP))] 5072 1.1 mrg "" 5073 1.1 mrg "jmp $31,(%0),0" 5074 1.1 mrg [(set_attr "type" "ibr")]) 5075 1.1 mrg 5076 1.1 mrg (define_expand "builtin_setjmp_receiver" 5077 1.1 mrg [(unspec_volatile [(label_ref (match_operand 0))] UNSPECV_SETJMPR)] 5078 1.1 mrg "TARGET_ABI_OSF") 5079 1.1 mrg 5080 1.1 mrg (define_insn_and_split "*builtin_setjmp_receiver_1" 5081 1.1 mrg [(unspec_volatile [(match_operand 0)] UNSPECV_SETJMPR)] 5082 1.1 mrg "TARGET_ABI_OSF" 5083 1.1 mrg { 5084 1.1 mrg if (TARGET_EXPLICIT_RELOCS) 5085 1.1 mrg return "#"; 5086 1.1 mrg else 5087 1.1.1.2 mrg return "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)"; 5088 1.1.1.2 mrg } 5089 1.1 mrg "&& TARGET_EXPLICIT_RELOCS && reload_completed" 5090 1.1 mrg [(set (match_dup 1) 5091 1.1 mrg (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1)) 5092 1.1 mrg (set (match_dup 1) 5093 1.1 mrg (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))] 5094 1.1 mrg { 5095 1.1 mrg if (prev_nonnote_insn (curr_insn) != XEXP (operands[0], 0)) 5096 1.1.1.2 mrg emit_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode, gen_rtvec (1, operands[0]), 5097 1.1 mrg UNSPECV_SETJMPR_ER)); 5098 1.1 mrg operands[1] = pic_offset_table_rtx; 5099 1.1 mrg operands[2] = gen_rtx_REG (Pmode, 27); 5100 1.1 mrg operands[3] = GEN_INT (alpha_next_sequence_number++); 5101 1.1 mrg } 5102 1.1.1.2 mrg [(set_attr "length" "12") 5103 1.1.1.6 mrg (set_attr "type" "multi")]) 5104 1.1 mrg 5105 1.1 mrg (define_insn "*builtin_setjmp_receiver_er_sl_1" 5106 1.1 mrg [(unspec_volatile [(match_operand 0)] UNSPECV_SETJMPR_ER)] 5107 1.1 mrg "TARGET_ABI_OSF && TARGET_EXPLICIT_RELOCS" 5108 1.1 mrg "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:") 5109 1.1 mrg 5110 1.1.1.2 mrg ;; When flag_reorder_blocks_and_partition is in effect, compiler puts 5111 1.1 mrg ;; exception landing pads in a cold section. To prevent inter-section offset 5112 1.1 mrg ;; calculation, a jump to original landing pad is emitted in the place of the 5113 1.1 mrg ;; original landing pad. Since landing pad is moved, RA-relative GP 5114 1.1 mrg ;; calculation in the prologue of landing pad breaks. To solve this problem, 5115 1.1 mrg ;; we use alternative GP load approach. 5116 1.1 mrg 5117 1.1 mrg (define_expand "exception_receiver" 5118 1.1 mrg [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)] 5119 1.1.1.3 mrg "TARGET_ABI_OSF" 5120 1.1 mrg { 5121 1.1 mrg if (flag_reorder_blocks_and_partition) 5122 1.1 mrg operands[0] = copy_rtx (alpha_gp_save_rtx ()); 5123 1.1 mrg else 5124 1.1 mrg operands[0] = const0_rtx; 5125 1.1 mrg }) 5126 1.1 mrg 5127 1.1 mrg (define_insn "*exception_receiver_2" 5128 1.1 mrg [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_EHR)] 5129 1.1 mrg "TARGET_ABI_OSF && flag_reorder_blocks_and_partition" 5130 1.1 mrg "ldq $29,%0" 5131 1.1 mrg [(set_attr "type" "ild")]) 5132 1.1 mrg 5133 1.1 mrg (define_insn_and_split "*exception_receiver_1" 5134 1.1 mrg [(unspec_volatile [(const_int 0)] UNSPECV_EHR)] 5135 1.1 mrg "TARGET_ABI_OSF" 5136 1.1 mrg { 5137 1.1 mrg if (TARGET_EXPLICIT_RELOCS) 5138 1.1 mrg return "#"; 5139 1.1 mrg else 5140 1.1 mrg return "ldgp $29,0($26)"; 5141 1.1.1.2 mrg } 5142 1.1 mrg "&& TARGET_EXPLICIT_RELOCS && reload_completed" 5143 1.1 mrg [(set (match_dup 0) 5144 1.1 mrg (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1)) 5145 1.1 mrg (set (match_dup 0) 5146 1.1 mrg (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))] 5147 1.1 mrg { 5148 1.1 mrg operands[0] = pic_offset_table_rtx; 5149 1.1 mrg operands[1] = gen_rtx_REG (Pmode, 26); 5150 1.1 mrg operands[2] = GEN_INT (alpha_next_sequence_number++); 5151 1.1 mrg } 5152 1.1 mrg [(set_attr "length" "8") 5153 1.1 mrg (set_attr "type" "multi")]) 5154 1.1 mrg 5155 1.1 mrg (define_expand "nonlocal_goto_receiver" 5156 1.1 mrg [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE) 5157 1.1 mrg (set (reg:DI 27) (mem:DI (reg:DI 29))) 5158 1.1 mrg (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE) 5159 1.1 mrg (use (reg:DI 27))] 5160 1.1 mrg "TARGET_ABI_OPEN_VMS") 5161 1.1 mrg 5162 1.1 mrg (define_insn "arg_home" 5163 1.1 mrg [(unspec [(const_int 0)] UNSPEC_ARG_HOME) 5164 1.1 mrg (use (reg:DI 1)) 5165 1.1 mrg (use (reg:DI 25)) 5166 1.1 mrg (use (reg:DI 16)) 5167 1.1 mrg (use (reg:DI 17)) 5168 1.1 mrg (use (reg:DI 18)) 5169 1.1 mrg (use (reg:DI 19)) 5170 1.1 mrg (use (reg:DI 20)) 5171 1.1 mrg (use (reg:DI 21)) 5172 1.1 mrg (use (reg:DI 48)) 5173 1.1 mrg (use (reg:DI 49)) 5174 1.1 mrg (use (reg:DI 50)) 5175 1.1 mrg (use (reg:DI 51)) 5176 1.1 mrg (use (reg:DI 52)) 5177 1.1 mrg (use (reg:DI 53)) 5178 1.1 mrg (clobber (mem:BLK (const_int 0))) 5179 1.1 mrg (clobber (reg:DI 24)) 5180 1.1 mrg (clobber (reg:DI 25)) 5181 1.1 mrg (clobber (reg:DI 0))] 5182 1.1 mrg "TARGET_ABI_OPEN_VMS" 5183 1.1 mrg "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS" 5184 1.1 mrg [(set_attr "length" "16") 5185 1.1 mrg (set_attr "type" "multi")]) 5186 1.1 mrg 5187 1.1 mrg ;; Prefetch data. 5188 1.1 mrg ;; 5189 1.1 mrg ;; On EV4, these instructions are nops -- no load occurs. 5190 1.1 mrg ;; 5191 1.1 mrg ;; On EV5, these instructions act as a normal load, and thus can trap 5192 1.1 mrg ;; if the address is invalid. The OS may (or may not) handle this in 5193 1.1 mrg ;; the entMM fault handler and suppress the fault. If so, then this 5194 1.1 mrg ;; has the effect of a read prefetch instruction. 5195 1.1 mrg ;; 5196 1.1 mrg ;; On EV6, these become official prefetch instructions. 5197 1.1 mrg 5198 1.1 mrg (define_insn "prefetch" 5199 1.1 mrg [(prefetch (match_operand:DI 0 "address_operand" "p") 5200 1.1 mrg (match_operand:DI 1 "const_int_operand" "n") 5201 1.1 mrg (match_operand:DI 2 "const_int_operand" "n"))] 5202 1.1 mrg "TARGET_FIXUP_EV5_PREFETCH || alpha_cpu == PROCESSOR_EV6" 5203 1.1 mrg { 5204 1.1 mrg /* Interpret "no temporal locality" as this data should be evicted once 5205 1.1 mrg it is used. The "evict next" alternatives load the data into the cache 5206 1.1 mrg and leave the LRU eviction counter pointing to that block. */ 5207 1.1 mrg static const char * const alt[2][2] = { 5208 1.1 mrg { 5209 1.1 mrg "ldq $31,%a0", /* read, evict next */ 5210 1.1 mrg "ldl $31,%a0", /* read, evict last */ 5211 1.1 mrg }, 5212 1.1 mrg { 5213 1.1 mrg "ldt $f31,%a0", /* write, evict next */ 5214 1.1 mrg "lds $f31,%a0", /* write, evict last */ 5215 1.1 mrg } 5216 1.1 mrg }; 5217 1.1 mrg 5218 1.1 mrg bool write = INTVAL (operands[1]) != 0; 5219 1.1 mrg bool lru = INTVAL (operands[2]) != 0; 5220 1.1 mrg 5221 1.1 mrg return alt[write][lru]; 5222 1.1 mrg } 5223 1.1 mrg [(set_attr "type" "ild")]) 5224 1.1 mrg 5225 1.1 mrg ;; Close the trap shadow of preceding instructions. This is generated 5226 1.1 mrg ;; by alpha_reorg. 5227 1.1 mrg 5228 1.1 mrg (define_insn "trapb" 5229 1.1 mrg [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)] 5230 1.1 mrg "" 5231 1.1 mrg "trapb" 5232 1.1 mrg [(set_attr "type" "misc")]) 5233 1.1 mrg 5234 1.1 mrg ;; No-op instructions used by machine-dependent reorg to preserve 5235 1.1 mrg ;; alignment for instruction issue. 5236 1.1 mrg ;; The Unicos/Mk assembler does not support these opcodes. 5237 1.1 mrg 5238 1.1 mrg (define_insn "nop" 5239 1.1 mrg [(const_int 0)] 5240 1.1.1.2 mrg "" 5241 1.1 mrg "bis $31,$31,$31" 5242 1.1 mrg [(set_attr "type" "ilog")]) 5243 1.1 mrg 5244 1.1 mrg (define_insn "fnop" 5245 1.1 mrg [(const_int 1)] 5246 1.1 mrg "TARGET_FP" 5247 1.1 mrg "cpys $f31,$f31,$f31" 5248 1.1 mrg [(set_attr "type" "fcpys")]) 5249 1.1 mrg 5250 1.1 mrg (define_insn "unop" 5251 1.1 mrg [(const_int 2)] 5252 1.1 mrg "" 5253 1.1 mrg "ldq_u $31,0($30)") 5254 1.1 mrg 5255 1.1.1.2 mrg (define_insn "realign" 5256 1.1.1.2 mrg [(unspec_volatile [(match_operand 0 "immediate_operand" "i")] 5257 1.1.1.2 mrg UNSPECV_REALIGN)] 5258 1.1.1.2 mrg "" 5259 1.1 mrg ".align %0 #realign") 5260 1.1 mrg 5262 1.1 mrg ;; Instructions to be emitted from __builtins. 5263 1.1 mrg 5264 1.1 mrg (define_insn "builtin_cmpbge" 5265 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand" "=r") 5266 1.1.1.2 mrg (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rJ") 5267 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand" "rI")] 5268 1.1.1.2 mrg UNSPEC_CMPBGE))] 5269 1.1 mrg "" 5270 1.1 mrg "cmpbge %r1,%2,%0" 5271 1.1.1.2 mrg ;; The EV6 data sheets list this as ILOG. OTOH, EV6 doesn't 5272 1.1 mrg ;; actually differentiate between ILOG and ICMP in the schedule. 5273 1.1 mrg [(set_attr "type" "icmp")]) 5274 1.1 mrg 5275 1.1.1.2 mrg (define_expand "extbl" 5276 1.1.1.2 mrg [(match_operand:DI 0 "register_operand") 5277 1.1.1.2 mrg (match_operand:DI 1 "reg_or_0_operand") 5278 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5279 1.1 mrg "" 5280 1.1 mrg { 5281 1.1.1.2 mrg emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (8), operands[2])); 5282 1.1 mrg DONE; 5283 1.1 mrg }) 5284 1.1 mrg 5285 1.1.1.2 mrg (define_expand "extwl" 5286 1.1.1.2 mrg [(match_operand:DI 0 "register_operand") 5287 1.1.1.2 mrg (match_operand:DI 1 "reg_or_0_operand") 5288 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5289 1.1 mrg "" 5290 1.1 mrg { 5291 1.1.1.2 mrg emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (16), operands[2])); 5292 1.1 mrg DONE; 5293 1.1 mrg }) 5294 1.1 mrg 5295 1.1 mrg (define_expand "extll" 5296 1.1.1.2 mrg [(match_operand:DI 0 "register_operand") 5297 1.1.1.2 mrg (match_operand:DI 1 "reg_or_0_operand") 5298 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5299 1.1 mrg "" 5300 1.1 mrg { 5301 1.1 mrg emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (32), operands[2])); 5302 1.1.1.2 mrg DONE; 5303 1.1 mrg }) 5304 1.1 mrg 5305 1.1 mrg (define_expand "extql" 5306 1.1 mrg [(match_operand:DI 0 "register_operand") 5307 1.1.1.2 mrg (match_operand:DI 1 "reg_or_0_operand") 5308 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5309 1.1.1.2 mrg "" 5310 1.1 mrg { 5311 1.1 mrg emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (64), operands[2])); 5312 1.1 mrg DONE; 5313 1.1.1.2 mrg }) 5314 1.1 mrg 5315 1.1 mrg (define_expand "builtin_insbl" 5316 1.1 mrg [(match_operand:DI 0 "register_operand") 5317 1.1 mrg (match_operand:DI 1 "register_operand") 5318 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5319 1.1.1.2 mrg "" 5320 1.1.1.2 mrg { 5321 1.1 mrg operands[1] = gen_lowpart (QImode, operands[1]); 5322 1.1 mrg emit_insn (gen_insbl (operands[0], operands[1], operands[2])); 5323 1.1 mrg DONE; 5324 1.1.1.2 mrg }) 5325 1.1 mrg 5326 1.1 mrg (define_expand "builtin_inswl" 5327 1.1 mrg [(match_operand:DI 0 "register_operand") 5328 1.1.1.2 mrg (match_operand:DI 1 "register_operand") 5329 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5330 1.1.1.2 mrg "" 5331 1.1.1.2 mrg { 5332 1.1 mrg operands[1] = gen_lowpart (HImode, operands[1]); 5333 1.1 mrg emit_insn (gen_inswl (operands[0], operands[1], operands[2])); 5334 1.1 mrg DONE; 5335 1.1 mrg }) 5336 1.1 mrg 5337 1.1 mrg (define_expand "builtin_insll" 5338 1.1.1.2 mrg [(match_operand:DI 0 "register_operand") 5339 1.1.1.2 mrg (match_operand:DI 1 "register_operand") 5340 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5341 1.1.1.2 mrg "" 5342 1.1 mrg { 5343 1.1 mrg operands[1] = gen_lowpart (SImode, operands[1]); 5344 1.1 mrg emit_insn (gen_insll (operands[0], operands[1], operands[2])); 5345 1.1 mrg DONE; 5346 1.1 mrg }) 5347 1.1 mrg 5348 1.1.1.2 mrg (define_expand "inswh" 5349 1.1.1.2 mrg [(match_operand:DI 0 "register_operand") 5350 1.1.1.2 mrg (match_operand:DI 1 "register_operand") 5351 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5352 1.1 mrg "" 5353 1.1 mrg { 5354 1.1 mrg emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2])); 5355 1.1 mrg DONE; 5356 1.1 mrg }) 5357 1.1 mrg 5358 1.1.1.2 mrg (define_expand "inslh" 5359 1.1.1.2 mrg [(match_operand:DI 0 "register_operand") 5360 1.1.1.2 mrg (match_operand:DI 1 "register_operand") 5361 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5362 1.1 mrg "" 5363 1.1 mrg { 5364 1.1.1.2 mrg emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2])); 5365 1.1.1.2 mrg DONE; 5366 1.1 mrg }) 5367 1.1 mrg 5368 1.1 mrg (define_expand "insqh" 5369 1.1.1.2 mrg [(match_operand:DI 0 "register_operand") 5370 1.1.1.2 mrg (match_operand:DI 1 "register_operand") 5371 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5372 1.1.1.2 mrg "" 5373 1.1 mrg { 5374 1.1 mrg emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2])); 5375 1.1.1.2 mrg DONE; 5376 1.1.1.2 mrg }) 5377 1.1 mrg 5378 1.1 mrg (define_expand "mskbl" 5379 1.1 mrg [(match_operand:DI 0 "register_operand") 5380 1.1.1.2 mrg (match_operand:DI 1 "reg_or_0_operand") 5381 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5382 1.1.1.2 mrg "" 5383 1.1.1.2 mrg { 5384 1.1 mrg rtx mask = GEN_INT (0xff); 5385 1.1 mrg emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2])); 5386 1.1.1.4 mrg DONE; 5387 1.1.1.2 mrg }) 5388 1.1 mrg 5389 1.1 mrg (define_expand "mskwl" 5390 1.1 mrg [(match_operand:DI 0 "register_operand") 5391 1.1.1.2 mrg (match_operand:DI 1 "reg_or_0_operand") 5392 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5393 1.1.1.2 mrg "" 5394 1.1.1.2 mrg { 5395 1.1 mrg rtx mask = GEN_INT (0xffff); 5396 1.1 mrg emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2])); 5397 1.1.1.2 mrg DONE; 5398 1.1.1.2 mrg }) 5399 1.1 mrg 5400 1.1 mrg (define_expand "mskll" 5401 1.1 mrg [(match_operand:DI 0 "register_operand") 5402 1.1.1.2 mrg (match_operand:DI 1 "reg_or_0_operand") 5403 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5404 1.1.1.2 mrg "" 5405 1.1.1.2 mrg { 5406 1.1 mrg rtx mask = gen_int_mode (0xffffffff, DImode); 5407 1.1 mrg emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2])); 5408 1.1 mrg DONE; 5409 1.1 mrg }) 5410 1.1 mrg 5411 1.1 mrg (define_expand "mskql" 5412 1.1.1.2 mrg [(match_operand:DI 0 "register_operand") 5413 1.1.1.2 mrg (match_operand:DI 1 "reg_or_0_operand") 5414 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5415 1.1.1.2 mrg "" 5416 1.1 mrg { 5417 1.1 mrg rtx mask = constm1_rtx; 5418 1.1 mrg emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2])); 5419 1.1 mrg DONE; 5420 1.1 mrg }) 5421 1.1 mrg 5422 1.1.1.2 mrg (define_expand "mskwh" 5423 1.1.1.2 mrg [(match_operand:DI 0 "register_operand") 5424 1.1.1.2 mrg (match_operand:DI 1 "register_operand") 5425 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5426 1.1 mrg "" 5427 1.1 mrg { 5428 1.1 mrg emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2])); 5429 1.1 mrg DONE; 5430 1.1 mrg }) 5431 1.1 mrg 5432 1.1 mrg (define_expand "msklh" 5433 1.1.1.2 mrg [(match_operand:DI 0 "register_operand") 5434 1.1 mrg (match_operand:DI 1 "register_operand") 5435 1.1.1.2 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5436 1.1 mrg "" 5437 1.1.1.2 mrg { 5438 1.1 mrg emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2])); 5439 1.1 mrg DONE; 5440 1.1 mrg }) 5441 1.1 mrg 5442 1.1 mrg (define_expand "mskqh" 5443 1.1 mrg [(match_operand:DI 0 "register_operand") 5444 1.1 mrg (match_operand:DI 1 "register_operand") 5445 1.1 mrg (match_operand:DI 2 "reg_or_8bit_operand")] 5446 1.1 mrg "" 5447 1.1 mrg { 5448 1.1 mrg emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2])); 5449 1.1 mrg DONE; 5450 1.1 mrg }) 5451 1.1 mrg 5452 1.1 mrg (define_expand "builtin_zap" 5453 1.1 mrg [(set (match_operand:DI 0 "register_operand") 5454 1.1 mrg (and:DI (unspec:DI 5455 1.1 mrg [(match_operand:DI 2 "reg_or_cint_operand")] 5456 1.1 mrg UNSPEC_ZAP) 5457 1.1 mrg (match_operand:DI 1 "reg_or_cint_operand")))] 5458 1.1 mrg "" 5459 1.1 mrg { 5460 1.1 mrg if (CONST_INT_P (operands[2])) 5461 1.1 mrg { 5462 1.1 mrg rtx mask = alpha_expand_zap_mask (INTVAL (operands[2])); 5463 1.1 mrg 5464 1.1 mrg if (mask == const0_rtx) 5465 1.1 mrg { 5466 1.1 mrg emit_move_insn (operands[0], const0_rtx); 5467 1.1 mrg DONE; 5468 1.1 mrg } 5469 1.1 mrg if (mask == constm1_rtx) 5470 1.1 mrg { 5471 1.1 mrg emit_move_insn (operands[0], operands[1]); 5472 1.1 mrg DONE; 5473 1.1 mrg } 5474 1.1 mrg 5475 1.1 mrg operands[1] = force_reg (DImode, operands[1]); 5476 1.1 mrg emit_insn (gen_anddi3 (operands[0], operands[1], mask)); 5477 1.1 mrg DONE; 5478 1.1 mrg } 5479 1.1.1.2 mrg 5480 1.1 mrg operands[1] = force_reg (DImode, operands[1]); 5481 1.1.1.2 mrg operands[2] = gen_lowpart (QImode, operands[2]); 5482 1.1 mrg }) 5483 1.1.1.2 mrg 5484 1.1 mrg (define_insn "*builtin_zap_1" 5485 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r,r,r,r") 5486 1.1 mrg (and:DI (unspec:DI 5487 1.1 mrg [(match_operand:QI 2 "reg_or_cint_operand" "n,n,r,r")] 5488 1.1.1.4 mrg UNSPEC_ZAP) 5489 1.1.1.4 mrg (match_operand:DI 1 "reg_or_cint_operand" "n,r,J,r")))] 5490 1.1 mrg "" 5491 1.1 mrg "@ 5492 1.1 mrg # 5493 1.1 mrg # 5494 1.1 mrg bis $31,$31,%0 5495 1.1.1.2 mrg zap %r1,%2,%0" 5496 1.1 mrg [(set_attr "type" "shift,shift,ilog,shift")]) 5497 1.1.1.2 mrg 5498 1.1 mrg (define_split 5499 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand") 5500 1.1 mrg (and:DI (unspec:DI 5501 1.1 mrg [(match_operand:QI 2 "const_int_operand")] 5502 1.1 mrg UNSPEC_ZAP) 5503 1.1 mrg (match_operand:DI 1 "const_int_operand")))] 5504 1.1 mrg "" 5505 1.1 mrg [(const_int 0)] 5506 1.1 mrg { 5507 1.1 mrg rtx mask = alpha_expand_zap_mask (INTVAL (operands[2])); 5508 1.1 mrg 5509 1.1 mrg operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode); 5510 1.1 mrg emit_move_insn (operands[0], operands[1]); 5511 1.1 mrg DONE; 5512 1.1 mrg }) 5513 1.1 mrg 5514 1.1 mrg (define_split 5515 1.1 mrg [(set (match_operand:DI 0 "register_operand") 5516 1.1 mrg (and:DI (unspec:DI 5517 1.1 mrg [(match_operand:QI 2 "const_int_operand")] 5518 1.1.1.2 mrg UNSPEC_ZAP) 5519 1.1 mrg (match_operand:DI 1 "register_operand")))] 5520 1.1.1.2 mrg "" 5521 1.1 mrg [(set (match_dup 0) 5522 1.1.1.2 mrg (and:DI (match_dup 1) (match_dup 2)))] 5523 1.1 mrg { 5524 1.1 mrg operands[2] = alpha_expand_zap_mask (INTVAL (operands[2])); 5525 1.1 mrg if (operands[2] == const0_rtx) 5526 1.1 mrg { 5527 1.1 mrg emit_move_insn (operands[0], const0_rtx); 5528 1.1 mrg DONE; 5529 1.1 mrg } 5530 1.1 mrg if (operands[2] == constm1_rtx) 5531 1.1 mrg { 5532 1.1 mrg emit_move_insn (operands[0], operands[1]); 5533 1.1 mrg DONE; 5534 1.1 mrg } 5535 1.1 mrg }) 5536 1.1 mrg 5537 1.1 mrg (define_expand "builtin_zapnot" 5538 1.1 mrg [(set (match_operand:DI 0 "register_operand") 5539 1.1 mrg (and:DI (unspec:DI 5540 1.1 mrg [(not:QI (match_operand:DI 2 "reg_or_cint_operand"))] 5541 1.1 mrg UNSPEC_ZAP) 5542 1.1 mrg (match_operand:DI 1 "reg_or_cint_operand")))] 5543 1.1 mrg "" 5544 1.1 mrg { 5545 1.1 mrg if (CONST_INT_P (operands[2])) 5546 1.1 mrg { 5547 1.1 mrg rtx mask = alpha_expand_zap_mask (~ INTVAL (operands[2])); 5548 1.1 mrg 5549 1.1 mrg if (mask == const0_rtx) 5550 1.1 mrg { 5551 1.1 mrg emit_move_insn (operands[0], const0_rtx); 5552 1.1 mrg DONE; 5553 1.1 mrg } 5554 1.1 mrg if (mask == constm1_rtx) 5555 1.1 mrg { 5556 1.1 mrg emit_move_insn (operands[0], operands[1]); 5557 1.1 mrg DONE; 5558 1.1 mrg } 5559 1.1 mrg 5560 1.1 mrg operands[1] = force_reg (DImode, operands[1]); 5561 1.1 mrg emit_insn (gen_anddi3 (operands[0], operands[1], mask)); 5562 1.1 mrg DONE; 5563 1.1 mrg } 5564 1.1 mrg 5565 1.1 mrg operands[1] = force_reg (DImode, operands[1]); 5566 1.1 mrg operands[2] = gen_lowpart (QImode, operands[2]); 5567 1.1 mrg }) 5568 1.1 mrg 5569 1.1 mrg (define_insn "*builtin_zapnot_1" 5570 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 5571 1.1 mrg (and:DI (unspec:DI 5572 1.1 mrg [(not:QI (match_operand:QI 2 "register_operand" "r"))] 5573 1.1 mrg UNSPEC_ZAP) 5574 1.1 mrg (match_operand:DI 1 "reg_or_0_operand" "rJ")))] 5575 1.1 mrg "" 5576 1.1 mrg "zapnot %r1,%2,%0" 5577 1.1 mrg [(set_attr "type" "shift")]) 5578 1.1 mrg 5579 1.1 mrg (define_insn "builtin_amask" 5580 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 5581 1.1 mrg (unspec:DI [(match_operand:DI 1 "reg_or_8bit_operand" "rI")] 5582 1.1.1.2 mrg UNSPEC_AMASK))] 5583 1.1.1.2 mrg "" 5584 1.1.1.2 mrg "amask %1,%0" 5585 1.1 mrg [(set_attr "type" "ilog")]) 5586 1.1 mrg 5587 1.1 mrg (define_insn "builtin_implver" 5588 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 5589 1.1 mrg (unspec:DI [(const_int 0)] UNSPEC_IMPLVER))] 5590 1.1 mrg "" 5591 1.1 mrg "implver %0" 5592 1.1 mrg [(set_attr "type" "ilog")]) 5593 1.1.1.2 mrg 5594 1.1.1.2 mrg (define_insn "builtin_rpcc" 5595 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand" "=r") 5596 1.1 mrg (unspec_volatile:DI [(const_int 0)] UNSPECV_RPCC))] 5597 1.1 mrg "" 5598 1.1 mrg "rpcc %0" 5599 1.1 mrg [(set_attr "type" "ilog")]) 5600 1.1 mrg 5601 1.1 mrg (define_expand "builtin_minub8" 5602 1.1 mrg [(match_operand:DI 0 "register_operand") 5603 1.1 mrg (match_operand:DI 1 "reg_or_0_operand") 5604 1.1.1.2 mrg (match_operand:DI 2 "reg_or_0_operand")] 5605 1.1.1.2 mrg "TARGET_MAX" 5606 1.1.1.2 mrg { 5607 1.1 mrg alpha_expand_builtin_vector_binop (gen_uminv8qi3, V8QImode, operands[0], 5608 1.1 mrg operands[1], operands[2]); 5609 1.1 mrg DONE; 5610 1.1 mrg }) 5611 1.1 mrg 5612 1.1 mrg (define_expand "builtin_minsb8" 5613 1.1 mrg [(match_operand:DI 0 "register_operand") 5614 1.1 mrg (match_operand:DI 1 "reg_or_0_operand") 5615 1.1.1.2 mrg (match_operand:DI 2 "reg_or_0_operand")] 5616 1.1.1.2 mrg "TARGET_MAX" 5617 1.1.1.2 mrg { 5618 1.1 mrg alpha_expand_builtin_vector_binop (gen_sminv8qi3, V8QImode, operands[0], 5619 1.1 mrg operands[1], operands[2]); 5620 1.1 mrg DONE; 5621 1.1 mrg }) 5622 1.1 mrg 5623 1.1 mrg (define_expand "builtin_minuw4" 5624 1.1 mrg [(match_operand:DI 0 "register_operand") 5625 1.1 mrg (match_operand:DI 1 "reg_or_0_operand") 5626 1.1.1.2 mrg (match_operand:DI 2 "reg_or_0_operand")] 5627 1.1.1.2 mrg "TARGET_MAX" 5628 1.1.1.2 mrg { 5629 1.1 mrg alpha_expand_builtin_vector_binop (gen_uminv4hi3, V4HImode, operands[0], 5630 1.1 mrg operands[1], operands[2]); 5631 1.1 mrg DONE; 5632 1.1 mrg }) 5633 1.1 mrg 5634 1.1 mrg (define_expand "builtin_minsw4" 5635 1.1 mrg [(match_operand:DI 0 "register_operand") 5636 1.1 mrg (match_operand:DI 1 "reg_or_0_operand") 5637 1.1.1.2 mrg (match_operand:DI 2 "reg_or_0_operand")] 5638 1.1.1.2 mrg "TARGET_MAX" 5639 1.1.1.2 mrg { 5640 1.1 mrg alpha_expand_builtin_vector_binop (gen_sminv4hi3, V4HImode, operands[0], 5641 1.1 mrg operands[1], operands[2]); 5642 1.1 mrg DONE; 5643 1.1 mrg }) 5644 1.1 mrg 5645 1.1 mrg (define_expand "builtin_maxub8" 5646 1.1 mrg [(match_operand:DI 0 "register_operand") 5647 1.1 mrg (match_operand:DI 1 "reg_or_0_operand") 5648 1.1.1.2 mrg (match_operand:DI 2 "reg_or_0_operand")] 5649 1.1.1.2 mrg "TARGET_MAX" 5650 1.1.1.2 mrg { 5651 1.1 mrg alpha_expand_builtin_vector_binop (gen_umaxv8qi3, V8QImode, operands[0], 5652 1.1 mrg operands[1], operands[2]); 5653 1.1 mrg DONE; 5654 1.1 mrg }) 5655 1.1 mrg 5656 1.1 mrg (define_expand "builtin_maxsb8" 5657 1.1 mrg [(match_operand:DI 0 "register_operand") 5658 1.1 mrg (match_operand:DI 1 "reg_or_0_operand") 5659 1.1.1.2 mrg (match_operand:DI 2 "reg_or_0_operand")] 5660 1.1.1.2 mrg "TARGET_MAX" 5661 1.1.1.2 mrg { 5662 1.1 mrg alpha_expand_builtin_vector_binop (gen_smaxv8qi3, V8QImode, operands[0], 5663 1.1 mrg operands[1], operands[2]); 5664 1.1 mrg DONE; 5665 1.1 mrg }) 5666 1.1 mrg 5667 1.1 mrg (define_expand "builtin_maxuw4" 5668 1.1 mrg [(match_operand:DI 0 "register_operand") 5669 1.1 mrg (match_operand:DI 1 "reg_or_0_operand") 5670 1.1 mrg (match_operand:DI 2 "reg_or_0_operand")] 5671 1.1 mrg "TARGET_MAX" 5672 1.1 mrg { 5673 1.1 mrg alpha_expand_builtin_vector_binop (gen_umaxv4hi3, V4HImode, operands[0], 5674 1.1 mrg operands[1], operands[2]); 5675 1.1 mrg DONE; 5676 1.1 mrg }) 5677 1.1 mrg 5678 1.1 mrg (define_expand "builtin_maxsw4" 5679 1.1.1.2 mrg [(match_operand:DI 0 "register_operand") 5680 1.1 mrg (match_operand:DI 1 "reg_or_0_operand") 5681 1.1 mrg (match_operand:DI 2 "reg_or_0_operand")] 5682 1.1.1.2 mrg "TARGET_MAX" 5683 1.1 mrg { 5684 1.1 mrg alpha_expand_builtin_vector_binop (gen_smaxv4hi3, V4HImode, operands[0], 5685 1.1 mrg operands[1], operands[2]); 5686 1.1 mrg DONE; 5687 1.1 mrg }) 5688 1.1 mrg 5689 1.1 mrg (define_insn "builtin_perr" 5690 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=r") 5691 1.1 mrg (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "%rJ") 5692 1.1 mrg (match_operand:DI 2 "reg_or_8bit_operand" "rJ")] 5693 1.1 mrg UNSPEC_PERR))] 5694 1.1 mrg "TARGET_MAX" 5695 1.1 mrg "perr %r1,%r2,%0" 5696 1.1 mrg [(set_attr "type" "mvi")]) 5697 1.1 mrg 5698 1.1.1.2 mrg (define_expand "builtin_pklb" 5699 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand") 5700 1.1 mrg (vec_concat:V8QI 5701 1.1 mrg (vec_concat:V4QI 5702 1.1 mrg (truncate:V2QI (match_operand:DI 1 "register_operand")) 5703 1.1 mrg (match_dup 2)) 5704 1.1 mrg (match_dup 3)))] 5705 1.1.1.2 mrg "TARGET_MAX" 5706 1.1 mrg { 5707 1.1.1.2 mrg operands[0] = gen_lowpart (V8QImode, operands[0]); 5708 1.1 mrg operands[1] = gen_lowpart (V2SImode, operands[1]); 5709 1.1 mrg operands[2] = CONST0_RTX (V2QImode); 5710 1.1 mrg operands[3] = CONST0_RTX (V4QImode); 5711 1.1 mrg }) 5712 1.1 mrg 5713 1.1 mrg (define_insn "*pklb" 5714 1.1 mrg [(set (match_operand:V8QI 0 "register_operand" "=r") 5715 1.1 mrg (vec_concat:V8QI 5716 1.1 mrg (vec_concat:V4QI 5717 1.1 mrg (truncate:V2QI (match_operand:V2SI 1 "register_operand" "r")) 5718 1.1 mrg (match_operand:V2QI 2 "const0_operand")) 5719 1.1 mrg (match_operand:V4QI 3 "const0_operand")))] 5720 1.1.1.2 mrg "TARGET_MAX" 5721 1.1 mrg "pklb %r1,%0" 5722 1.1 mrg [(set_attr "type" "mvi")]) 5723 1.1 mrg 5724 1.1 mrg (define_expand "builtin_pkwb" 5725 1.1 mrg [(set (match_operand:DI 0 "register_operand") 5726 1.1.1.2 mrg (vec_concat:V8QI 5727 1.1 mrg (truncate:V4QI (match_operand:DI 1 "register_operand")) 5728 1.1.1.2 mrg (match_dup 2)))] 5729 1.1 mrg "TARGET_MAX" 5730 1.1 mrg { 5731 1.1 mrg operands[0] = gen_lowpart (V8QImode, operands[0]); 5732 1.1 mrg operands[1] = gen_lowpart (V4HImode, operands[1]); 5733 1.1 mrg operands[2] = CONST0_RTX (V4QImode); 5734 1.1 mrg }) 5735 1.1 mrg 5736 1.1 mrg (define_insn "*pkwb" 5737 1.1 mrg [(set (match_operand:V8QI 0 "register_operand" "=r") 5738 1.1 mrg (vec_concat:V8QI 5739 1.1 mrg (truncate:V4QI (match_operand:V4HI 1 "register_operand" "r")) 5740 1.1 mrg (match_operand:V4QI 2 "const0_operand")))] 5741 1.1 mrg "TARGET_MAX" 5742 1.1 mrg "pkwb %r1,%0" 5743 1.1 mrg [(set_attr "type" "mvi")]) 5744 1.1 mrg 5745 1.1 mrg (define_expand "builtin_unpkbl" 5746 1.1.1.2 mrg [(set (match_operand:DI 0 "register_operand") 5747 1.1 mrg (zero_extend:V2SI 5748 1.1.1.2 mrg (vec_select:V2QI (match_operand:DI 1 "register_operand") 5749 1.1 mrg (parallel [(const_int 0) (const_int 1)]))))] 5750 1.1 mrg "TARGET_MAX" 5751 1.1 mrg { 5752 1.1 mrg operands[0] = gen_lowpart (V2SImode, operands[0]); 5753 1.1 mrg operands[1] = gen_lowpart (V8QImode, operands[1]); 5754 1.1 mrg }) 5755 1.1 mrg 5756 1.1 mrg (define_insn "*unpkbl" 5757 1.1 mrg [(set (match_operand:V2SI 0 "register_operand" "=r") 5758 1.1 mrg (zero_extend:V2SI 5759 1.1 mrg (vec_select:V2QI (match_operand:V8QI 1 "reg_or_0_operand" "rW") 5760 1.1 mrg (parallel [(const_int 0) (const_int 1)]))))] 5761 1.1 mrg "TARGET_MAX" 5762 1.1 mrg "unpkbl %r1,%0" 5763 1.1 mrg [(set_attr "type" "mvi")]) 5764 1.1 mrg 5765 1.1 mrg (define_expand "builtin_unpkbw" 5766 1.1 mrg [(set (match_operand:DI 0 "register_operand") 5767 1.1 mrg (zero_extend:V4HI 5768 1.1 mrg (vec_select:V4QI (match_operand:DI 1 "register_operand") 5769 1.1 mrg (parallel [(const_int 0) 5770 1.1 mrg (const_int 1) 5771 1.1 mrg (const_int 2) 5772 1.1 mrg (const_int 3)]))))] 5773 1.1 mrg "TARGET_MAX" 5774 1.1 mrg { 5775 1.1 mrg operands[0] = gen_lowpart (V4HImode, operands[0]); 5776 1.1 mrg operands[1] = gen_lowpart (V8QImode, operands[1]); 5777 1.1.1.2 mrg }) 5778 1.1 mrg 5779 1.1.1.2 mrg (define_insn "*unpkbw" 5780 1.1 mrg [(set (match_operand:V4HI 0 "register_operand" "=r") 5781 1.1 mrg (zero_extend:V4HI 5782 1.1 mrg (vec_select:V4QI (match_operand:V8QI 1 "reg_or_0_operand" "rW") 5783 1.1 mrg (parallel [(const_int 0) 5784 1.1 mrg (const_int 1) 5785 1.1 mrg (const_int 2) 5786 1.1 mrg (const_int 3)]))))] 5787 1.1 mrg "TARGET_MAX" 5788 1.1 mrg "unpkbw %r1,%0" 5789 1.1 mrg [(set_attr "type" "mvi")]) 5790 1.1 mrg 5792 1.1.1.2 mrg (include "sync.md") 5793 1.1 mrg 5795 1.1 mrg ;; The call patterns are at the end of the file because their 5796 1.1 mrg ;; wildcard operand0 interferes with nice recognition. 5797 1.1 mrg 5798 1.1 mrg (define_insn "*call_value_osf_1_er_noreturn" 5799 1.1 mrg [(set (match_operand 0) 5800 1.1 mrg (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) 5801 1.1 mrg (match_operand 2))) 5802 1.1 mrg (use (reg:DI 29)) 5803 1.1 mrg (clobber (reg:DI 26))] 5804 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF 5805 1.1 mrg && find_reg_note (insn, REG_NORETURN, NULL_RTX)" 5806 1.1 mrg "@ 5807 1.1 mrg jsr $26,($27),0 5808 1.1.1.2 mrg bsr $26,%1\t\t!samegp 5809 1.1.1.2 mrg ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),%1\t\t!lituse_jsr!%#" 5810 1.1.1.2 mrg [(set_attr "type" "jsr") 5811 1.1 mrg (set_attr "length" "*,*,8")]) 5812 1.1 mrg 5813 1.1 mrg (define_insn "*call_value_osf_1_er" 5814 1.1 mrg [(set (match_operand 0) 5815 1.1 mrg (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) 5816 1.1 mrg (match_operand 2))) 5817 1.1 mrg (use (reg:DI 29)) 5818 1.1 mrg (clobber (reg:DI 26))] 5819 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 5820 1.1 mrg "@ 5821 1.1 mrg jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%* 5822 1.1 mrg bsr $26,%1\t\t!samegp 5823 1.1 mrg ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*" 5824 1.1 mrg [(set_attr "type" "jsr") 5825 1.1 mrg (set_attr "length" "12,*,16")]) 5826 1.1 mrg 5827 1.1 mrg ;; We must use peep2 instead of a split because we need accurate life 5828 1.1 mrg ;; information for $gp. Consider the case of { bar(); while (1); }. 5829 1.1 mrg (define_peephole2 5830 1.1 mrg [(parallel [(set (match_operand 0) 5831 1.1 mrg (call (mem:DI (match_operand:DI 1 "call_operand")) 5832 1.1 mrg (match_operand 2))) 5833 1.1 mrg (use (reg:DI 29)) 5834 1.1 mrg (clobber (reg:DI 26))])] 5835 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed 5836 1.1 mrg && ! samegp_function_operand (operands[1], Pmode) 5837 1.1 mrg && (peep2_regno_dead_p (1, 29) 5838 1.1 mrg || find_reg_note (insn, REG_NORETURN, NULL_RTX))" 5839 1.1 mrg [(parallel [(set (match_dup 0) 5840 1.1 mrg (call (mem:DI (match_dup 3)) 5841 1.1.1.2 mrg (match_dup 2))) 5842 1.1.1.2 mrg (use (reg:DI 29)) 5843 1.1.1.2 mrg (use (match_dup 1)) 5844 1.1 mrg (use (match_dup 4)) 5845 1.1 mrg (clobber (reg:DI 26))])] 5846 1.1 mrg { 5847 1.1 mrg if (CONSTANT_P (operands[1])) 5848 1.1 mrg { 5849 1.1 mrg operands[3] = gen_rtx_REG (Pmode, 27); 5850 1.1 mrg operands[4] = GEN_INT (alpha_next_sequence_number++); 5851 1.1 mrg emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx, 5852 1.1 mrg operands[1], operands[4])); 5853 1.1 mrg } 5854 1.1 mrg else 5855 1.1 mrg { 5856 1.1 mrg operands[3] = operands[1]; 5857 1.1 mrg operands[1] = const0_rtx; 5858 1.1 mrg operands[4] = const0_rtx; 5859 1.1 mrg } 5860 1.1 mrg }) 5861 1.1 mrg 5862 1.1 mrg (define_peephole2 5863 1.1 mrg [(parallel [(set (match_operand 0) 5864 1.1 mrg (call (mem:DI (match_operand:DI 1 "call_operand")) 5865 1.1 mrg (match_operand 2))) 5866 1.1 mrg (use (reg:DI 29)) 5867 1.1 mrg (clobber (reg:DI 26))])] 5868 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed 5869 1.1 mrg && ! samegp_function_operand (operands[1], Pmode) 5870 1.1 mrg && ! (peep2_regno_dead_p (1, 29) 5871 1.1 mrg || find_reg_note (insn, REG_NORETURN, NULL_RTX))" 5872 1.1 mrg [(parallel [(set (match_dup 0) 5873 1.1 mrg (call (mem:DI (match_dup 3)) 5874 1.1 mrg (match_dup 2))) 5875 1.1 mrg (set (match_dup 6) 5876 1.1 mrg (unspec:DI [(match_dup 6) (match_dup 4)] UNSPEC_LDGP1)) 5877 1.1 mrg (use (match_dup 1)) 5878 1.1 mrg (use (match_dup 5)) 5879 1.1.1.2 mrg (clobber (reg:DI 26))]) 5880 1.1 mrg (set (match_dup 6) 5881 1.1.1.2 mrg (unspec:DI [(match_dup 6) (match_dup 4)] UNSPEC_LDGP2))] 5882 1.1 mrg { 5883 1.1.1.2 mrg if (CONSTANT_P (operands[1])) 5884 1.1.1.2 mrg { 5885 1.1 mrg operands[3] = gen_rtx_REG (Pmode, 27); 5886 1.1 mrg operands[5] = GEN_INT (alpha_next_sequence_number++); 5887 1.1 mrg emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx, 5888 1.1 mrg operands[1], operands[5])); 5889 1.1 mrg } 5890 1.1 mrg else 5891 1.1.1.2 mrg { 5892 1.1 mrg operands[3] = operands[1]; 5893 1.1.1.2 mrg operands[1] = const0_rtx; 5894 1.1 mrg operands[5] = const0_rtx; 5895 1.1.1.2 mrg } 5896 1.1 mrg operands[4] = GEN_INT (alpha_next_sequence_number++); 5897 1.1.1.2 mrg operands[6] = pic_offset_table_rtx; 5898 1.1.1.2 mrg }) 5899 1.1 mrg 5900 1.1 mrg (define_insn "*call_value_osf_2_er_nogp" 5901 1.1 mrg [(set (match_operand 0) 5902 1.1 mrg (call (mem:DI (match_operand:DI 1 "register_operand" "c")) 5903 1.1 mrg (match_operand 2))) 5904 1.1 mrg (use (reg:DI 29)) 5905 1.1 mrg (use (match_operand 3)) 5906 1.1 mrg (use (match_operand 4)) 5907 1.1.1.2 mrg (clobber (reg:DI 26))] 5908 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 5909 1.1.1.2 mrg "jsr $26,(%1),%3%J4" 5910 1.1 mrg [(set_attr "type" "jsr")]) 5911 1.1 mrg 5912 1.1 mrg (define_insn "*call_value_osf_2_er" 5913 1.1 mrg [(set (match_operand 0) 5914 1.1 mrg (call (mem:DI (match_operand:DI 1 "register_operand" "c")) 5915 1.1 mrg (match_operand 2))) 5916 1.1 mrg (set (reg:DI 29) 5917 1.1 mrg (unspec:DI [(reg:DI 29) (match_operand 5 "const_int_operand")] 5918 1.1 mrg UNSPEC_LDGP1)) 5919 1.1 mrg (use (match_operand 3)) 5920 1.1 mrg (use (match_operand 4)) 5921 1.1.1.2 mrg (clobber (reg:DI 26))] 5922 1.1.1.2 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 5923 1.1.1.2 mrg "jsr $26,(%1),%3%J4\;ldah $29,0($26)\t\t!gpdisp!%5" 5924 1.1.1.2 mrg [(set_attr "type" "jsr") 5925 1.1.1.2 mrg (set_attr "cannot_copy" "true") 5926 1.1.1.2 mrg (set_attr "length" "8")]) 5927 1.1.1.2 mrg 5928 1.1.1.2 mrg (define_insn "*call_value_osf_1_noreturn" 5929 1.1.1.2 mrg [(set (match_operand 0) 5930 1.1.1.2 mrg (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) 5931 1.1.1.2 mrg (match_operand 2))) 5932 1.1 mrg (use (reg:DI 29)) 5933 1.1.1.2 mrg (clobber (reg:DI 26))] 5934 1.1 mrg "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF 5935 1.1 mrg && find_reg_note (insn, REG_NORETURN, NULL_RTX)" 5936 1.1 mrg "@ 5937 1.1.1.2 mrg jsr $26,($27),0 5938 1.1.1.2 mrg bsr $26,$%1..ng 5939 1.1.1.2 mrg jsr $26,%1" 5940 1.1.1.2 mrg [(set_attr "type" "jsr") 5941 1.1.1.2 mrg (set_attr "length" "*,*,8")]) 5942 1.1.1.2 mrg 5943 1.1.1.2 mrg (define_int_iterator TLS_CALL 5944 1.1.1.2 mrg [UNSPEC_TLSGD_CALL 5945 1.1.1.2 mrg UNSPEC_TLSLDM_CALL]) 5946 1.1.1.2 mrg 5947 1.1.1.2 mrg (define_int_attr tls 5948 1.1.1.2 mrg [(UNSPEC_TLSGD_CALL "tlsgd") 5949 1.1.1.2 mrg (UNSPEC_TLSLDM_CALL "tlsldm")]) 5950 1.1.1.2 mrg 5951 1.1.1.2 mrg (define_insn "call_value_osf_<tls>" 5952 1.1.1.2 mrg [(set (match_operand 0) 5953 1.1 mrg (call (mem:DI (match_operand:DI 1 "symbolic_operand")) 5954 1.1 mrg (const_int 0))) 5955 1.1 mrg (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL) 5956 1.1 mrg (use (reg:DI 29)) 5957 1.1 mrg (clobber (reg:DI 26))] 5958 1.1 mrg "HAVE_AS_TLS" 5959 1.1 mrg "ldq $27,%1($29)\t\t!literal!%2\;jsr $26,($27),%1\t\t!lituse_<tls>!%2\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*" 5960 1.1.1.2 mrg [(set_attr "type" "jsr") 5961 1.1 mrg (set_attr "length" "16")]) 5962 1.1.1.2 mrg 5963 1.1 mrg ;; We must use peep2 instead of a split because we need accurate life 5964 1.1 mrg ;; information for $gp. 5965 1.1 mrg (define_peephole2 5966 1.1 mrg [(parallel 5967 1.1 mrg [(set (match_operand 0) 5968 1.1 mrg (call (mem:DI (match_operand:DI 1 "symbolic_operand")) 5969 1.1 mrg (const_int 0))) 5970 1.1.1.2 mrg (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL) 5971 1.1 mrg (use (reg:DI 29)) 5972 1.1.1.2 mrg (clobber (reg:DI 26))])] 5973 1.1.1.2 mrg "HAVE_AS_TLS && reload_completed 5974 1.1.1.2 mrg && peep2_regno_dead_p (1, 29)" 5975 1.1.1.2 mrg [(set (match_dup 3) 5976 1.1.1.2 mrg (unspec:DI [(match_dup 5) 5977 1.1.1.2 mrg (match_dup 1) 5978 1.1.1.2 mrg (match_dup 2)] UNSPEC_LITERAL)) 5979 1.1.1.2 mrg (parallel [(set (match_dup 0) 5980 1.1.1.2 mrg (call (mem:DI (match_dup 3)) 5981 1.1.1.2 mrg (const_int 0))) 5982 1.1 mrg (use (match_dup 5)) 5983 1.1 mrg (use (match_dup 1)) 5984 1.1 mrg (use (unspec [(match_dup 2)] TLS_CALL)) 5985 1.1 mrg (clobber (reg:DI 26))]) 5986 1.1 mrg (set (match_dup 5) 5987 1.1 mrg (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))] 5988 1.1 mrg { 5989 1.1 mrg operands[3] = gen_rtx_REG (Pmode, 27); 5990 1.1 mrg operands[4] = GEN_INT (alpha_next_sequence_number++); 5991 1.1 mrg operands[5] = pic_offset_table_rtx; 5992 1.1.1.2 mrg }) 5993 1.1 mrg 5994 1.1 mrg (define_peephole2 5995 1.1 mrg [(parallel 5996 1.1 mrg [(set (match_operand 0) 5997 1.1 mrg (call (mem:DI (match_operand:DI 1 "symbolic_operand")) 5998 1.1 mrg (const_int 0))) 5999 1.1 mrg (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL) 6000 1.1.1.2 mrg (use (reg:DI 29)) 6001 1.1 mrg (clobber (reg:DI 26))])] 6002 1.1 mrg "HAVE_AS_TLS && reload_completed 6003 1.1.1.2 mrg && !peep2_regno_dead_p (1, 29)" 6004 1.1 mrg [(set (match_dup 3) 6005 1.1.1.2 mrg (unspec:DI [(match_dup 5) 6006 1.1 mrg (match_dup 1) 6007 1.1 mrg (match_dup 2)] UNSPEC_LITERAL)) 6008 1.1 mrg (parallel [(set (match_dup 0) 6009 1.1 mrg (call (mem:DI (match_dup 3)) 6010 1.1 mrg (const_int 0))) 6011 1.1 mrg (set (match_dup 5) 6012 1.1 mrg (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP1)) 6013 1.1 mrg (use (match_dup 1)) 6014 1.1 mrg (use (unspec [(match_dup 2)] TLS_CALL)) 6015 1.1 mrg (clobber (reg:DI 26))]) 6016 1.1 mrg (set (match_dup 5) 6017 1.1.1.2 mrg (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))] 6018 1.1 mrg { 6019 1.1.1.2 mrg operands[3] = gen_rtx_REG (Pmode, 27); 6020 1.1 mrg operands[4] = GEN_INT (alpha_next_sequence_number++); 6021 1.1 mrg operands[5] = pic_offset_table_rtx; 6022 1.1 mrg }) 6023 1.1 mrg 6024 1.1 mrg (define_insn "*call_value_osf_1" 6025 1.1 mrg [(set (match_operand 0) 6026 1.1 mrg (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) 6027 1.1 mrg (match_operand 2))) 6028 1.1 mrg (use (reg:DI 29)) 6029 1.1.1.2 mrg (clobber (reg:DI 26))] 6030 1.1 mrg "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 6031 1.1.1.2 mrg "@ 6032 1.1 mrg jsr $26,($27),0\;ldgp $29,0($26) 6033 1.1 mrg bsr $26,$%1..ng 6034 1.1 mrg jsr $26,%1\;ldgp $29,0($26)" 6035 1.1 mrg [(set_attr "type" "jsr") 6036 1.1 mrg (set_attr "length" "12,*,16")]) 6037 1.1 mrg 6038 1.1 mrg (define_insn "*sibcall_value_osf_1_er" 6039 1.1 mrg [(set (match_operand 0) 6040 1.1 mrg (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s")) 6041 1.1 mrg (match_operand 2))) 6042 1.1 mrg (unspec [(reg:DI 29)] UNSPEC_SIBCALL)] 6043 1.1 mrg "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 6044 1.1.1.2 mrg "@ 6045 1.1 mrg br $31,%1\t\t!samegp 6046 1.1.1.2 mrg ldq $27,%1($29)\t\t!literal!%#\;jmp $31,($27),%1\t\t!lituse_jsr!%#" 6047 1.1 mrg [(set_attr "type" "jsr") 6048 1.1 mrg (set_attr "length" "*,8")]) 6049 1.1 mrg 6050 1.1 mrg (define_insn "*sibcall_value_osf_1" 6051 1.1 mrg [(set (match_operand 0) 6052 1.1 mrg (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s")) 6053 1.1 mrg (match_operand 2))) 6054 1.1 mrg (unspec [(reg:DI 29)] UNSPEC_SIBCALL)] 6055 1.1 mrg "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 6056 1.1 mrg "@ 6057 1.1 mrg br $31,$%1..ng 6058 1.1.1.2 mrg lda $27,%1\;jmp $31,($27),%1" 6059 1.1.1.2 mrg [(set_attr "type" "jsr") 6060 1.1 mrg (set_attr "length" "*,8")]) 6061 1.1 mrg 6062 1.1 mrg ; GAS relies on the order and position of instructions output below in order 6063 1.1 mrg ; to generate relocs for VMS link to potentially optimize the call. 6064 1.1 mrg ; Please do not molest. 6065 1.1 mrg (define_insn "*call_value_vms_1" 6066 1.1 mrg [(set (match_operand 0) 6067 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s")) 6068 (match_operand 2))) 6069 (use (match_operand:DI 3 "nonmemory_operand" "r,n")) 6070 (use (reg:DI 25)) 6071 (use (reg:DI 26)) 6072 (clobber (reg:DI 27))] 6073 "TARGET_ABI_OPEN_VMS" 6074 { 6075 switch (which_alternative) 6076 { 6077 case 0: 6078 return "mov %3,$27\;jsr $26,0\;ldq $27,0($29)"; 6079 case 1: 6080 operands [3] = alpha_use_linkage (operands [1], true, false); 6081 operands [4] = alpha_use_linkage (operands [1], false, false); 6082 return "ldq $26,%4\;ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"; 6083 default: 6084 gcc_unreachable (); 6085 } 6086 } 6087 [(set_attr "type" "jsr") 6088 (set_attr "length" "12,16")]) 6089
Indexes created Thu Sep 10 00:26:39 UTC 2026